src-test2/sys/sparc64/include, branch release/8.1.0

MFC: r209695

2010-07-07T21:00:17Z

- Pin the IPI cache and TLB demap functions in order to prevent migration between determining the other CPUs and calling cpu_ipi_selected(), which apart from generally doing the wrong thing can lead to a panic when a CPU is told to IPI itself (which sun4u doesn't support). Reported and tested by: Nathaniel W Filardo - Add __unused where appropriate. Approved by: re (kib)

MFC: r208349

2010-05-23T16:16:33Z

Change ad_firmware_geom_adjust() to operate on a struct disk * only and hook it up to ada(4) also. While at it, rename *ad_firmware_geom_adjust() to *ata_disk_firmware_geom_adjust() etc now that these are no longer limited to ad(4). This also allows to maintain a compatibility shim for pc98_ad_firmware_geom_adjust() for the tier-1 PC98 in stable/8. Reviewed by: mav (r208349)

MFC: r207537

2010-05-10T20:25:51Z

Add support for SPARC64 V (and where it already makes sense for other HAL/Fujitsu) CPUs. For the most part this consists of fleshing out the MMU and cache handling, it doesn't add pmap optimizations possible with these CPU, yet, though. With these changes FreeBSD runs stable on Fujitsu Siemens PRIMEPOWER 250 and likely also other models based on SPARC64 V like 450, 650 and 850. Thanks go to Michael Moll for providing access to a PRIMEPOWER 250.

MFC: r207243

2010-05-10T18:47:52Z

Add OF_getscsinitid(), a helper similar to OF_getetheraddr() but for obtaining the initiator ID to be used for SPI controllers from the Open Firmware device tree.

MFC r204051 (by imp):

2010-05-08T18:54:47Z

n64 has a different size for KINFO_PROC_SIZE. Approved by: imp MFC r207152: Move the constants specifying the size of struct kinfo_proc into machine-specific header files. Add KINFO_PROC32_SIZE for struct kinfo_proc32 for architectures providing COMPAT_FREEBSD32. Add CTASSERT for the size of struct kinfo_proc32. MFC r207269: Style: use #define instead of #define.

MFC: r206480

2010-05-02T16:47:50Z

Update for UltraSPARC-IV{,+} and SPARC64 V, VI, VII and VIIIfx CPUs.

MFC: r206450

2010-05-02T16:46:20Z

Correct the DCR_IPE macro to refer to the right bit. Also improve the associated comment as besides US-IV+ these bits are only available with US-III++, i.e. the 1.2GHz version of the US-III+.

MFC: r205269

2010-04-04T14:57:46Z

o Add support for UltraSparc-IV+: - Swap the configuration of the first and second large dTLB as with US-IV+ these can only hold entries of certain page sizes each, which we happened to chose the non-working way around. - Additionally ensure that the large iTLB is set up to hold 8k pages (currently this happens to be a NOP though). - Add a workaround for US-IV+ erratum #2. - Turn off dTLB parity error reporting as otherwise we get seemingly false positives when copying in the user window by simulating a fill trap on return to usermode. Given that these parity errors can be avoided by disabling multi issue mode and the problem could be reproduced with a second machine this appears to be a silicon bug of some sort. - Add a membar #Sync also before the stores to ASI_DCACHE_TAG. While at it, turn of interrupts across the whole cheetah_cache_flush() for simplicity instead of around every flush. This should have next to no impact as for cheetah-class machines we typically only need to flush the caches a few times during boot when recovering from peeking/poking non-existent PCI devices, if at all. - Just use KERNBASE for FLUSH as we also do elsewhere as the US-IV+ documentation doesn't seem to mention that these CPUs also ignore the address like previous cheetah-class CPUs do. Again the code changing LSU_IC is executed seldom enough that the negligible optimization of using %g0 instead should have no real impact. With these changes FreeBSD runs stable on V890 equipped with US-IV+ and -j128 buildworlds in a loop for days are no problem. Unfortunately, the performance isn't were it should be as a buildworld on a 4x1.5GHz US-IV+ V890 takes nearly 3h while on a V440 with (theoretically) less powerfull 4x1.5GHz US-IIIi it takes just over 1h. It's unclear whether this is related to the supposed silicon bug mentioned above or due to another issue. The documentation (which contains a sever bug in the description of the bits added to the context registers though) at least doesn't mention any requirements for changes in the CPU handling besides those implemented and the cache as well as the TLB configurations and handling look fine. o Re-arrange cheetah_init() so it's easier to add support for SPARC64 V up to VIIIfx CPUs, which only require parts of this initialization. Committed from: EH2010

MFC: r205409

2010-04-01T15:17:50Z

- The firmware of Sun Fire V1280 has a misfeature of setting %wstate to 7 which corresponds to WSTATE_KMIX in OpenSolaris whenever calling into it which totally screws us even when restoring %wstate afterwards as spill/fill traps can happen while in OFW. The rather hackish OpenBSD approach of just setting the equivalent of WSTATE_KERNEL to 7 also is no option as we treat %wstate as a bit field. So in order to deal with this problem actually implement spill/fill handlers for %wstate 7 which just act as the WSTATE_KERNEL ones except of theoretically also handling 32-bit, turn off interrupts completely so we don't even take IPIs while in OFW which should ensure we only take spill/fill traps at most and restore %wstate after calling into OFW once we have taken over the trap table. While at it, actually set WSTATE_{,PROM}_KMIX before calling into OFW just like OpenSolaris does, which should at least help testing this change on non-V1280. - Remove comments referring to the %wstate usage in BSD/OS. - Remove the no longer used RSF_ALIGN_RETRY macro. - Correct some trap table addresses in comments. - Ensure %wstate is set to WSTATE_KERNEL when taking over the trap table. - Ensure PSTATE_AM is off when entering or exiting to OFW as well as that interrupts are also completely off when exiting to OFW as the firmware trap table shouldn't be used to handle our interrupts.

MFC: r205263

2010-03-31T22:00:22Z

Add macros for the VER.impl of SPARC64 II to VIIIfx.