Remove unused functions and variables in cpufunc.[ch].

4 files changed, 3 insertions, 125 deletions

diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 19a66d05c0a4..3f773a3ece72 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -62,24 +62,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/cpufunc.h>
 
 /* PRIMARY CACHE VARIABLES */
-int	arm_picache_size;
-int	arm_picache_line_size;
-int	arm_picache_ways;
-
-int	arm_pdcache_size;	/* and unified */
-int	arm_pdcache_line_size;
-int	arm_pdcache_ways;
-
-int	arm_pcache_type;
-int	arm_pcache_unified;
 
 int	arm_dcache_align;
 int	arm_dcache_align_mask;
 
-u_int	arm_cache_level;
-u_int	arm_cache_type[14];
-u_int	arm_cache_loc;
-
 #ifdef CPU_MV_PJ4B
 static void pj4bv7_setup(void);
 #endif
@@ -155,16 +141,10 @@ u_int cputype;
 
 static void get_cachetype_cp15(void);
 
-/* Additional cache information local to this file.  Log2 of some of the
-   above numbers.  */
-static int	arm_dcache_l2_nsets;
-static int	arm_dcache_l2_assoc;
-static int	arm_dcache_l2_linesize;
-
 static void
 get_cachetype_cp15(void)
 {
-	u_int ctype, isize, dsize, cpuid;
+	u_int ctype, dsize, cpuid;
 	u_int clevel, csize, i, sel;
 	u_int multiplier;
 	u_char type;
@@ -184,8 +164,6 @@ get_cachetype_cp15(void)
 	if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) {
 		__asm __volatile("mrc p15, 1, %0, c0, c0, 1"
 		    : "=r" (clevel));
-		arm_cache_level = clevel;
-		arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level);
 		i = 0;
 		while ((type = (clevel & 0x7)) && i < 7) {
 			if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
@@ -195,7 +173,6 @@ get_cachetype_cp15(void)
 				    : : "r" (sel));
 				__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
 				    : "=r" (csize));
-				arm_cache_type[sel] = csize;
 				arm_dcache_align = 1 <<
 				    (CPUV7_CT_xSIZE_LEN(csize) + 4);
 				arm_dcache_align_mask = arm_dcache_align - 1;
@@ -206,57 +183,22 @@ get_cachetype_cp15(void)
 				    : : "r" (sel));
 				__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
 				    : "=r" (csize));
-				arm_cache_type[sel] = csize;
 			}
 			i++;
 			clevel >>= 3;
 		}
 	} else {
-		if ((ctype & CPU_CT_S) == 0)
-			arm_pcache_unified = 1;
-
 		/*
 		 * If you want to know how this code works, go read the ARM ARM.
 		 */
 
-		arm_pcache_type = CPU_CT_CTYPE(ctype);
-
-		if (arm_pcache_unified == 0) {
-			isize = CPU_CT_ISIZE(ctype);
-			multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
-			arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
-			if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
-				if (isize & CPU_CT_xSIZE_M)
-					arm_picache_line_size = 0; /* not present */
-				else
-					arm_picache_ways = 1;
-			} else {
-				arm_picache_ways = multiplier <<
-				    (CPU_CT_xSIZE_ASSOC(isize) - 1);
-			}
-			arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
-		}
-
 		dsize = CPU_CT_DSIZE(ctype);
 		multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
-		arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
+		arm_dcache_align = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
 		if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
 			if (dsize & CPU_CT_xSIZE_M)
-				arm_pdcache_line_size = 0; /* not present */
-			else
-				arm_pdcache_ways = 1;
-		} else {
-			arm_pdcache_ways = multiplier <<
-			    (CPU_CT_xSIZE_ASSOC(dsize) - 1);
+				arm_dcache_align = 0; /* not present */
 		}
-		arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
-
-		arm_dcache_align = arm_pdcache_line_size;
-
-		arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2;
-		arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3;
-		arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) -
-		    CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize);
 
 	out:
 		arm_dcache_align_mask = arm_dcache_align - 1;
diff --git a/sys/arm/arm/cpufunc_asm.S b/sys/arm/arm/cpufunc_asm.S
index 1cd41cabc74a..94b34714bfe4 100644
--- a/sys/arm/arm/cpufunc_asm.S
+++ b/sys/arm/arm/cpufunc_asm.S
@@ -53,21 +53,6 @@ ENTRY(cpufunc_nullop)
 END(cpufunc_nullop)
 
 /*
- * Generic functions to write the internal coprocessor registers
- *
- * Currently these registers are
- *  c1 - CPU Control
- *  c3 - Domain Access Control
- *
- * All other registers are CPU architecture specific
- */
-
-ENTRY(cpu_domains)
-	mcr	p15, 0, r0, c3, c0, 0
-	RET
-END(cpu_domains)
-
-/*
  * Generic functions to read/modify/write the internal coprocessor registers
  *
  *
@@ -90,35 +75,3 @@ ENTRY(cpufunc_control)
 	RET
 END(cpufunc_control)
 
-/*
- * other potentially useful software functions are:
- *  clean D cache entry and flush I cache entry
- *   for the moment use cache_purgeID_E
- */
-
-/* Random odd functions */
-
-/* Allocate and lock a cacheline for the specified address. */
-
-#define CPWAIT_BRANCH			\
-	sub	pc, pc, #4
-#define CPWAIT() \
-	mrc	p15, 0, r2, c2, c0, 0;	\
-	mov	r2, r2;			\
-	CPWAIT_BRANCH
-
-ENTRY(arm_lock_cache_line)
-	mcr	p15, 0, r0, c7, c10, 4 /* Drain write buffer */
-	mov	r1, #1
-	mcr	p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */
-	CPWAIT()
-	mcr	p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
-	mcr	p15, 0, r0, c7, c10, 4 /* Drain write buffer */
-	mov	r1, #0
-	str	r1, [r0]
-	mcr	p15, 0, r0, c7, c10, 4 /* Drain write buffer */
-	mcr	p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
-	CPWAIT()
-	RET
-END(arm_lock_cache_line)
-
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index 70f0f19b589f..a5db3486aff1 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -87,11 +87,9 @@ extern u_int cputype;
 
 int	set_cpufuncs		(void);
 #define ARCHITECTURE_NOT_PRESENT	1	/* known but not configured */
-#define ARCHITECTURE_NOT_SUPPORTED	2	/* not known */
 
 void	cpufunc_nullop		(void);
 u_int	cpufunc_control		(u_int clear, u_int bic);
-void	cpu_domains		(u_int domains);
 
 
 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
@@ -182,23 +180,9 @@ void cpu_reset		(void) __attribute__((__noreturn__));
  */
 
 /* PRIMARY CACHE VARIABLES */
-extern int	arm_picache_size;
-extern int	arm_picache_line_size;
-extern int	arm_picache_ways;
-
-extern int	arm_pdcache_size;	/* and unified */
-extern int	arm_pdcache_line_size;
-extern int	arm_pdcache_ways;
-
-extern int	arm_pcache_type;
-extern int	arm_pcache_unified;
-
 extern int	arm_dcache_align;
 extern int	arm_dcache_align_mask;
 
-extern u_int	arm_cache_level;
-extern u_int	arm_cache_loc;
-extern u_int	arm_cache_type[14];
 
 #define	HAVE_INLINE_FFS
 
diff --git a/sys/arm/include/machdep.h b/sys/arm/include/machdep.h
index f41f99f2f976..3efad39753d3 100644
--- a/sys/arm/include/machdep.h
+++ b/sys/arm/include/machdep.h
@@ -16,7 +16,6 @@ extern vm_offset_t abtstack;
 
 /* misc prototypes used by the many arm machdeps */
 struct trapframe;
-void arm_lock_cache_line(vm_offset_t);
 void init_proc0(vm_offset_t kstack);
 void halt(void);
 void abort_handler(struct trapframe *, int );