5 files changed, 100 insertions, 17 deletions

diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index 5ed426d9f10a..077aa316b7ab 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- *		$Id: initcpu.c,v 1.6 1997/06/27 13:46:19 kato Exp $
+ *		$Id: initcpu.c,v 1.7 1997/07/24 14:19:25 kato Exp $
  */
 
 #include "opt_cpu.h"
@@ -304,6 +304,15 @@ init_6x86(void)
 	/* Initialize CCR0. */
 	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 
+	/* Initialize CCR1. */
+#ifdef CPU_CYRIX_NO_LOCK
+	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK);
+#else
+#ifdef FAILSAFE
+	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK);
+#endif
+#endif
+
 	/* Initialize CCR2. */
 #ifdef CPU_SUSP_HLT
 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
@@ -324,6 +333,11 @@ init_6x86(void)
 	write_cyrix_reg(CCR4, ccr4 | 7);
 #endif
 
+	/* Initialize CCR5. */
+#ifdef CPU_WT_ALLOC
+	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
+#endif
+
 	/* Restore CCR3. */
 	write_cyrix_reg(CCR3, ccr3);
 
@@ -373,6 +387,15 @@ init_6x86MX(void)
 	/* Initialize CCR0. */
 	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 
+	/* Initialize CCR1. */
+#ifdef CPU_CYRIX_NO_LOCK
+	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK);
+#else
+#ifdef FAILSAFE
+	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK);
+#endif
+#endif
+
 	/* Initialize CCR2. */
 #ifdef CPU_SUSP_HLT
 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
@@ -392,6 +415,11 @@ init_6x86MX(void)
 	write_cyrix_reg(CCR4, ccr4 | 7);
 #endif
 
+	/* Initialize CCR5. */
+#ifdef CPU_WT_ALLOC
+	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
+#endif
+
 	/* Restore CCR3. */
 	write_cyrix_reg(CCR3, ccr3);
 
@@ -506,10 +534,10 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 		ccr1 = read_cyrix_reg(CCR1);
 		ccr2 = read_cyrix_reg(CCR2);
 		ccr3 = read_cyrix_reg(CCR3);
-		if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
+		if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 			write_cyrix_reg(CCR3, CCR3_MAPEN0);
 			ccr4 = read_cyrix_reg(CCR4);
-			if (cpu == CPU_M1)
+			if ((cpu == CPU_M1) || (cpu == CPU_M2))
 				ccr5 = read_cyrix_reg(CCR5);
 			else
 				pcr0 = read_cyrix_reg(PCR0);
@@ -522,12 +550,12 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 
 		printf("CCR1=%x, CCR2=%x, CCR3=%x",
 			(u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
-		if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
+		if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 			printf(", CCR4=%x, ", (u_int)ccr4);
-			if (cpu == CPU_M1)
-				printf("CCR5=%x\n", ccr5);
-			else
+			if (cpu == CPU_M1SC)
 				printf("PCR0=%x\n", pcr0);
+			else
+				printf("CCR5=%x\n", ccr5);
 		}
 	}
 	printf("CR0=%x\n", cr0);
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index b8bb5a2de20e..2db3cfa36c08 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.369 1997/09/23 08:42:42 jkh Exp $
+#	$Id: LINT,v 1.370 1997/09/23 16:28:00 jkh Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -132,6 +132,10 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
 # mapped mode.  Default is 2-way set associative mode.
 #
+# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
+# of Cyrix 6x86 and 6x86MX CPUs.  If this option is not set and
+# FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared.  (NOTE 3)
+#
 # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s). 
@@ -154,6 +158,8 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # CPU_SUSP_HLT enables suspend on HALT.  If this option is set, CPU
 # enters suspend mode following execution of HALT instruction.
 #
+# CPU_WT_ALLOC enables write-through allocation.
+#
 # CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
 # flush at hold state.
 #
@@ -169,6 +175,9 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # in write-through mode when revision < 2.7.  If revision of Cyrix
 # 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
 #
+# NOTE 3: This option may cause failures for software that requires
+# locked cycles in order to operate correctly.
+#
 options		"CPU_BLUELIGHTNING_FPU_OP_CACHE"
 options		"CPU_BLUELIGHTNING_3X"
 options		"CPU_BTB_EN"
diff --git a/sys/i386/conf/LINT b/sys/i386/conf/LINT
index b8bb5a2de20e..2db3cfa36c08 100644
--- a/sys/i386/conf/LINT
+++ b/sys/i386/conf/LINT
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.369 1997/09/23 08:42:42 jkh Exp $
+#	$Id: LINT,v 1.370 1997/09/23 16:28:00 jkh Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -132,6 +132,10 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
 # mapped mode.  Default is 2-way set associative mode.
 #
+# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
+# of Cyrix 6x86 and 6x86MX CPUs.  If this option is not set and
+# FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared.  (NOTE 3)
+#
 # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s). 
@@ -154,6 +158,8 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # CPU_SUSP_HLT enables suspend on HALT.  If this option is set, CPU
 # enters suspend mode following execution of HALT instruction.
 #
+# CPU_WT_ALLOC enables write-through allocation.
+#
 # CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
 # flush at hold state.
 #
@@ -169,6 +175,9 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # in write-through mode when revision < 2.7.  If revision of Cyrix
 # 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
 #
+# NOTE 3: This option may cause failures for software that requires
+# locked cycles in order to operate correctly.
+#
 options		"CPU_BLUELIGHTNING_FPU_OP_CACHE"
 options		"CPU_BLUELIGHTNING_3X"
 options		"CPU_BTB_EN"
diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES
index b8bb5a2de20e..2db3cfa36c08 100644
--- a/sys/i386/conf/NOTES
+++ b/sys/i386/conf/NOTES
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.369 1997/09/23 08:42:42 jkh Exp $
+#	$Id: LINT,v 1.370 1997/09/23 16:28:00 jkh Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -132,6 +132,10 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
 # mapped mode.  Default is 2-way set associative mode.
 #
+# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
+# of Cyrix 6x86 and 6x86MX CPUs.  If this option is not set and
+# FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared.  (NOTE 3)
+#
 # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s). 
@@ -154,6 +158,8 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # CPU_SUSP_HLT enables suspend on HALT.  If this option is set, CPU
 # enters suspend mode following execution of HALT instruction.
 #
+# CPU_WT_ALLOC enables write-through allocation.
+#
 # CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
 # flush at hold state.
 #
@@ -169,6 +175,9 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 # in write-through mode when revision < 2.7.  If revision of Cyrix
 # 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
 #
+# NOTE 3: This option may cause failures for software that requires
+# locked cycles in order to operate correctly.
+#
 options		"CPU_BLUELIGHTNING_FPU_OP_CACHE"
 options		"CPU_BLUELIGHTNING_3X"
 options		"CPU_BTB_EN"
diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c
index 5ed426d9f10a..077aa316b7ab 100644
--- a/sys/i386/i386/initcpu.c
+++ b/sys/i386/i386/initcpu.c
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- *		$Id: initcpu.c,v 1.6 1997/06/27 13:46:19 kato Exp $
+ *		$Id: initcpu.c,v 1.7 1997/07/24 14:19:25 kato Exp $
  */
 
 #include "opt_cpu.h"
@@ -304,6 +304,15 @@ init_6x86(void)
 	/* Initialize CCR0. */
 	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 
+	/* Initialize CCR1. */
+#ifdef CPU_CYRIX_NO_LOCK
+	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK);
+#else
+#ifdef FAILSAFE
+	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK);
+#endif
+#endif
+
 	/* Initialize CCR2. */
 #ifdef CPU_SUSP_HLT
 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
@@ -324,6 +333,11 @@ init_6x86(void)
 	write_cyrix_reg(CCR4, ccr4 | 7);
 #endif
 
+	/* Initialize CCR5. */
+#ifdef CPU_WT_ALLOC
+	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
+#endif
+
 	/* Restore CCR3. */
 	write_cyrix_reg(CCR3, ccr3);
 
@@ -373,6 +387,15 @@ init_6x86MX(void)
 	/* Initialize CCR0. */
 	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
 
+	/* Initialize CCR1. */
+#ifdef CPU_CYRIX_NO_LOCK
+	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK);
+#else
+#ifdef FAILSAFE
+	write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK);
+#endif
+#endif
+
 	/* Initialize CCR2. */
 #ifdef CPU_SUSP_HLT
 	write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
@@ -392,6 +415,11 @@ init_6x86MX(void)
 	write_cyrix_reg(CCR4, ccr4 | 7);
 #endif
 
+	/* Initialize CCR5. */
+#ifdef CPU_WT_ALLOC
+	write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
+#endif
+
 	/* Restore CCR3. */
 	write_cyrix_reg(CCR3, ccr3);
 
@@ -506,10 +534,10 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 		ccr1 = read_cyrix_reg(CCR1);
 		ccr2 = read_cyrix_reg(CCR2);
 		ccr3 = read_cyrix_reg(CCR3);
-		if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
+		if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 			write_cyrix_reg(CCR3, CCR3_MAPEN0);
 			ccr4 = read_cyrix_reg(CCR4);
-			if (cpu == CPU_M1)
+			if ((cpu == CPU_M1) || (cpu == CPU_M2))
 				ccr5 = read_cyrix_reg(CCR5);
 			else
 				pcr0 = read_cyrix_reg(PCR0);
@@ -522,12 +550,12 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
 
 		printf("CCR1=%x, CCR2=%x, CCR3=%x",
 			(u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
-		if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
+		if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
 			printf(", CCR4=%x, ", (u_int)ccr4);
-			if (cpu == CPU_M1)
-				printf("CCR5=%x\n", ccr5);
-			else
+			if (cpu == CPU_M1SC)
 				printf("PCR0=%x\n", pcr0);
+			else
+				printf("CCR5=%x\n", ccr5);
 		}
 	}
 	printf("CR0=%x\n", cr0);