diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2018-03-09 09:21:22 +0000 | 
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-03-09 09:21:22 +0000 | 
| commit | a3fedceefa6ee0592dd80dbf2909a9574be7bf68 (patch) | |
| tree | b9e633e56bddd947c4cedc2f6bd9393c088b8b4d | |
| parent | 9f5fab694ca58cffd6a4d62dce0eb184ba31ef39 (diff) | |
Notes
| -rw-r--r-- | contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp | 25 | 
1 files changed, 17 insertions, 8 deletions
| diff --git a/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp b/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp index aeda7c06a27a..c4c7ad088c0b 100644 --- a/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -10201,7 +10201,14 @@ static SDValue PerformSHLSimplify(SDNode *N,      case ISD::XOR:      case ISD::SETCC:      case ARMISD::CMP: -      // Check that its not already using a shl. +      // Check that the user isn't already using a constant because there +      // aren't any instructions that support an immediate operand and a +      // shifted operand. +      if (isa<ConstantSDNode>(U->getOperand(0)) || +          isa<ConstantSDNode>(U->getOperand(1))) +        return SDValue(); + +      // Check that it's not already using a shift.        if (U->getOperand(0).getOpcode() == ISD::SHL ||            U->getOperand(1).getOpcode() == ISD::SHL)          return SDValue(); @@ -10223,8 +10230,6 @@ static SDValue PerformSHLSimplify(SDNode *N,    if (!C1ShlC2 || !C2)      return SDValue(); -  DEBUG(dbgs() << "Trying to simplify shl: "; N->dump()); -    APInt C2Int = C2->getAPIntValue();    APInt C1Int = C1ShlC2->getAPIntValue(); @@ -10238,12 +10243,12 @@ static SDValue PerformSHLSimplify(SDNode *N,    C1Int.lshrInPlace(C2Int);    // The immediates are encoded as an 8-bit value that can be rotated. -  unsigned Zeros = C1Int.countLeadingZeros() + C1Int.countTrailingZeros(); -  if (C1Int.getBitWidth() - Zeros > 8) -    return SDValue(); +  auto LargeImm = [](const APInt &Imm) { +    unsigned Zeros = Imm.countLeadingZeros() + Imm.countTrailingZeros(); +    return Imm.getBitWidth() - Zeros > 8; +  }; -  Zeros = C2Int.countLeadingZeros() + C2Int.countTrailingZeros(); -  if (C2Int.getBitWidth() - Zeros > 8) +  if (LargeImm(C1Int) || LargeImm(C2Int))      return SDValue();    SelectionDAG &DAG = DCI.DAG; @@ -10254,6 +10259,10 @@ static SDValue PerformSHLSimplify(SDNode *N,    // Shift left to compensate for the lshr of C1Int.    SDValue Res = DAG.getNode(ISD::SHL, dl, MVT::i32, BinOp, SHL.getOperand(1)); +  DEBUG(dbgs() << "Simplify shl use:\n"; SHL.getOperand(0).dump(); SHL.dump(); +        N->dump()); +  DEBUG(dbgs() << "Into:\n"; X.dump(); BinOp.dump(); Res.dump()); +    DAG.ReplaceAllUsesWith(SDValue(N, 0), Res);    return SDValue(N, 0);  } | 
