diff options
| author | Pedro F. Giffuni <pfg@FreeBSD.org> | 2019-05-29 02:08:23 +0000 |
|---|---|---|
| committer | Pedro F. Giffuni <pfg@FreeBSD.org> | 2019-05-29 02:08:23 +0000 |
| commit | ec845b07c603ce6c02f62e3ac79b480596d88ae8 (patch) | |
| tree | 816d49412ae8969a728a7c42b614112d6b1db572 | |
| parent | d9a48fc632f31e2c0465aae9265da673f584c11d (diff) | |
Notes
| -rw-r--r-- | lib/libc/net/rthdr.c | 2 | ||||
| -rw-r--r-- | sys/i386/i386/initcpu.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/libc/net/rthdr.c b/lib/libc/net/rthdr.c index 5a035e9d32d0..81f07c0e77dd 100644 --- a/lib/libc/net/rthdr.c +++ b/lib/libc/net/rthdr.c @@ -282,7 +282,7 @@ inet6_rth_space(int type, int segments) return (((segments * 2) + 1) << 3); /* FALLTHROUGH */ default: - return (0); /* type not suppported */ + return (0); /* type not supported */ } } diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c index e48ebdb69276..93a0343ede32 100644 --- a/sys/i386/i386/initcpu.c +++ b/sys/i386/i386/initcpu.c @@ -848,7 +848,7 @@ enable_K6_wt_alloc(void) */ /* * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), - * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. + * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. * All other bits in TR12 have no effect on the processer's operation. * The I/O Trap Restart function (bit 9 of TR12) is always enabled * on the AMD-K6. @@ -898,7 +898,7 @@ enable_K6_2_wt_alloc(void) */ /* * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), - * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. + * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. * All other bits in TR12 have no effect on the processer's operation. * The I/O Trap Restart function (bit 9 of TR12) is always enabled * on the AMD-K6. |