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author | Emmanuel Vadot <manu@FreeBSD.org> | 2017-03-07 12:41:06 +0000 |
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committer | Emmanuel Vadot <manu@FreeBSD.org> | 2017-03-07 12:41:06 +0000 |
commit | ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e (patch) | |
tree | 5cd0b74d984dae06ea54b6b09998163538d3c162 /Bindings/interrupt-controller/jcore,aic.txt | |
parent | c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5 (diff) | |
download | src-test2-ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e.tar.gz src-test2-ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e.zip |
Notes
Diffstat (limited to 'Bindings/interrupt-controller/jcore,aic.txt')
-rw-r--r-- | Bindings/interrupt-controller/jcore,aic.txt | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Bindings/interrupt-controller/jcore,aic.txt b/Bindings/interrupt-controller/jcore,aic.txt new file mode 100644 index 000000000000..ee2ad36f8df8 --- /dev/null +++ b/Bindings/interrupt-controller/jcore,aic.txt @@ -0,0 +1,26 @@ +J-Core Advanced Interrupt Controller + +Required properties: + +- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for + the "aic2" core with 64 interrupts. + +- reg: Memory region(s) for configuration. For SMP, there should be one + region per cpu, indexed by the sequential, zero-based hardware cpu + number. + +- interrupt-controller: Identifies the node as an interrupt controller + +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. + + +Example: + +aic: interrupt-controller@200 { + compatible = "jcore,aic2"; + reg = < 0x200 0x30 0x500 0x30 >; + interrupt-controller; + #interrupt-cells = <1>; +}; |