vendor/llvm/llvm-release_38-r260756

1 files changed, 131 insertions, 15 deletions

diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst
index dccb7f4d1cce..7b284d59656b 100644
--- a/docs/ReleaseNotes.rst
+++ b/docs/ReleaseNotes.rst
@@ -5,11 +5,6 @@ LLVM 3.8 Release Notes
 .. contents::
     :local:
 
-.. warning::
-   These are in-progress notes for the upcoming LLVM 3.8 release.  You may
-   prefer the `LLVM 3.7 Release Notes <http://llvm.org/releases/3.7.0/docs
-   /ReleaseNotes.html>`_.
-
 
 Introduction
 ============
@@ -26,11 +21,6 @@ have questions or comments, the `LLVM Developer's Mailing List
 <http://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send
 them.
 
-Note that if you are reading this file from a Subversion checkout or the main
-LLVM web page, this document applies to the *next* release, not the current
-one.  To see the release notes for a specific release, please see the `releases
-page <http://llvm.org/releases/>`_.
-
 Non-comprehensive list of changes in this release
 =================================================
 * With this release, the minimum Windows version required for running LLVM is
@@ -79,6 +69,26 @@ Non-comprehensive list of changes in this release
 
 * Support for dematerializing has been dropped.
 
+* RegisterScheduler::setDefault was removed. Targets that used to call into the
+  command line parser to set the DAGScheduler, and that don't have enough
+  control with setSchedulingPreference, should look into overriding the
+  SubTargetHook "getDAGScheduler()".
+
+* ``ilist_iterator<T>`` no longer has implicit conversions to and from ``T*``,
+  since ``ilist_iterator<T>`` may be pointing at the sentinel (which is usually
+  not of type ``T`` at all).  To convert from an iterator ``I`` to a pointer,
+  use ``&*I``; to convert from a pointer ``P`` to an iterator, use
+  ``P->getIterator()``.  Alternatively, explicit conversions via
+  ``static_cast<T>(U)`` are still available.
+
+* ``ilist_node<T>::getNextNode()`` and ``ilist_node<T>::getPrevNode()`` now
+  fail at compile time when the node cannot access its parent list.
+  Previously, when the sentinel was was an ``ilist_half_node<T>``, this API
+  could return the sentinal instead of ``nullptr``.  Frustrated callers should
+  be updated to use ``iplist<T>::getNextNode(T*)`` instead.  Alternatively, if
+  the node ``N`` is guaranteed not to be the last in the list, it is safe to
+  call ``&*++N->getIterator()`` directly.
+
 .. NOTE
    For small 1-3 sentence descriptions, just add an entry at the end of
    this list. If your description won't fit comfortably in one bullet
@@ -98,17 +108,97 @@ Non-comprehensive list of changes in this release
 
    Makes programs 10x faster by doing Special New Thing.
 
-Changes to the ARM Backend
---------------------------
 
- During this release ...
+Changes to the ARM Backends
+---------------------------
+
+During this release the AArch64 target has:
+
+* Added support for more sanitizers (MSAN, TSAN) and made them compatible with
+  all VMA kernel configurations (kurrently tested on 39 and 42 bits).
+* Gained initial LLD support in the new ELF back-end
+* Extended the Load/Store optimiser and cleaned up some of the bad decisions
+  made earlier.
+* Expanded LLDB support, including watchpoints, native building, Renderscript,
+  LLDB-server, debugging 32-bit applications.
+* Added support for the ``Exynos M1`` chip.
+
+During this release the ARM target has:
+
+* Gained massive performance improvements on embedded benchmarks due to finally
+  running the stride vectorizer in full form, incrementing the performance gains
+  that we already had in the previous releases with limited stride vectorization.
+* Expanded LLDB support, including watchpoints, unwind tables
+* Extended the Load/Store optimiser and cleaned up some of the bad decisions
+  made earlier.
+* Simplified code generation for global variable addresses in ELF, resulting in
+  a significant (4% in Chromium) reduction in code size.
+* Gained some additional code size improvements, though there's still a long road
+  ahead, especially for older cores.
+* Added some EABI floating point comparison functions to Compiler-RT
+* Added support for Windows+GNU triple, +features in -mcpu/-march options.
 
 
 Changes to the MIPS Target
 --------------------------
 
- During this release ...
+During this release the MIPS target has:
 
+* Significantly extended support for the Integrated Assembler. See below for
+  more information
+* Added support for the ``P5600`` processor.
+* Added support for the ``interrupt`` attribute for MIPS32R2 and later. This
+  attribute will generate a function which can be used as a interrupt handler
+  on bare metal MIPS targets using the static relocation model.
+* Added support for the ``ERETNC`` instruction found in MIPS32R5 and later.
+* Added support for OpenCL. See http://portablecl.org/.
+
+  * Address spaces 1 to 255 are now reserved for software use and conversions
+    between them are no-op casts.
+
+* Removed the ``mips16`` value for the -mcpu option since it is an :abbr:`ASE
+  (Application Specific Extension)` and not a processor. If you were using this,
+  please specify another CPU and use ``-mips16`` to enable MIPS16.
+* Removed ``copy_u.w`` from 32-bit MSA and ``copy_u.d`` from 64-bit MSA since
+  they have been removed from the MSA specification due to forward compatibility
+  issues.  For example, 32-bit MSA code containing ``copy_u.w`` would behave
+  differently on a 64-bit processor supporting MSA. The corresponding intrinsics
+  are still available and may expand to ``copy_s.[wd]`` where this is
+  appropriate for forward compatibility purposes.
+* Relaxed the ``-mnan`` option to allow ``-mnan=2008`` on MIPS32R2/MIPS64R2 for
+  compatibility with GCC.
+* Made MIPS64R6 the default CPU for 64-bit Android triples.
+
+The MIPS target has also fixed various bugs including the following notable
+fixes:
+
+* Fixed reversed operands on ``mthi``/``mtlo`` in the DSP :abbr:`ASE
+  (Application Specific Extension)`.
+* The code generator no longer uses ``jal`` for calls to absolute immediate
+  addresses.
+* Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is not
+  yet supported.
+* Corrected addend for ``R_MIPS_HI16`` and ``R_MIPS_PCHI16`` in MCJIT
+* The code generator no longer crashes when handling subregisters of an 64-bit
+  FPU register with undefined value.
+* The code generator no longer attempts to use ``$zero`` for operands that do
+  not permit ``$zero``.
+* Corrected the opcode used for ``ll``/``sc`` when using MIPS32R6/MIPS64R6 and
+  the Integrated Assembler.
+* Added support for atomic load and atomic store.
+* Corrected debug info when dynamically re-aligning the stack.
+
+Integrated Assembler
+^^^^^^^^^^^^^^^^^^^^
+We have made a large number of improvements to the integrated assembler for
+MIPS. In this release, the integrated assembler isn't quite production-ready
+since there are a few known issues related to bare-metal support, checking
+immediates on instructions, and the N32/N64 ABI's. However, the current support
+should be sufficient for many users of the O32 ABI, particularly those targeting
+MIPS32 on Linux or bare-metal MIPS32.
+
+If you would like to try the integrated assembler, please use
+``-fintegrated-as``.
 
 Changes to the PowerPC Target
 -----------------------------
@@ -123,6 +213,20 @@ Changes to the X86 Target
 
 * TLS is enabled for Cygwin as emutls.
 
+* Smaller code for materializing 32-bit 1 and -1 constants at ``-Os``.
+
+* More efficient code for wide integer compares. (E.g. 64-bit compares
+  on 32-bit targets.)
+
+* Tail call support for ``thiscall``, ``stdcall`, ``vectorcall``, and
+  ``fastcall`` functions.
+
+Changes to the AVR Target
+-------------------------
+
+Slightly less than half of the AVR backend has been merged in at this point. It is still
+missing a number large parts which cause it to be unusable, but is well on the
+road to being completely merged and workable.
 
 Changes to the OCaml bindings
 -----------------------------
@@ -140,7 +244,19 @@ An exciting aspect of LLVM is that it is used as an enabling technology for
 a lot of other language and tools projects. This section lists some of the
 projects that have already been updated to work with LLVM 3.8.
 
-* A project
+LDC - the LLVM-based D compiler
+-------------------------------
+
+`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
+pragmatically combines efficiency, control, and modeling power, with safety and
+programmer productivity. D supports powerful concepts like Compile-Time Function
+Execution (CTFE) and Template Meta-Programming, provides an innovative approach
+to concurrency and offers many classical paradigms.
+
+`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
+combined with LLVM as backend to produce efficient native code. LDC targets
+x86/x86_64 systems like Linux, OS X and Windows and also PowerPC (32/64 bit)
+and ARM. Ports to other architectures like AArch64 and MIPS64 are underway.
 
 
 Additional Information