vendor/device-tree/devicetree-965f3718

50 files changed, 3892 insertions, 120 deletions

diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
new file mode 100644
index 000000000000..27359ad83904
--- /dev/null
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_ATH79_CLK_H
+#define __DT_BINDINGS_ATH79_CLK_H
+
+#define ATH79_CLK_CPU		0
+#define ATH79_CLK_DDR		1
+#define ATH79_CLK_AHB		2
+
+#define ATH79_CLK_END		3
+
+#endif /* __DT_BINDINGS_ATH79_CLK_H */
diff --git a/include/dt-bindings/clock/axis,artpec6-clkctrl.h b/include/dt-bindings/clock/axis,artpec6-clkctrl.h
new file mode 100644
index 000000000000..f9f04dccc996
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec6-clkctrl.h
@@ -0,0 +1,38 @@
+/*
+ * ARTPEC-6 clock controller indexes
+ *
+ * Copyright 2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+
+#define ARTPEC6_CLK_CPU			0
+#define ARTPEC6_CLK_CPU_PERIPH		1
+#define ARTPEC6_CLK_NAND_CLKA		2
+#define ARTPEC6_CLK_NAND_CLKB		3
+#define ARTPEC6_CLK_ETH_ACLK		4
+#define ARTPEC6_CLK_DMA_ACLK		5
+#define ARTPEC6_CLK_PTP_REF		6
+#define ARTPEC6_CLK_SD_PCLK		7
+#define ARTPEC6_CLK_SD_IMCLK		8
+#define ARTPEC6_CLK_I2S_HST		9
+#define ARTPEC6_CLK_I2S0_CLK		10
+#define ARTPEC6_CLK_I2S1_CLK		11
+#define ARTPEC6_CLK_UART_PCLK		12
+#define ARTPEC6_CLK_UART_REFCLK		13
+#define ARTPEC6_CLK_I2C			14
+#define ARTPEC6_CLK_SPI_PCLK		15
+#define ARTPEC6_CLK_SPI_SSPCLK		16
+#define ARTPEC6_CLK_SYS_TIMER		17
+#define ARTPEC6_CLK_FRACDIV_IN		18
+#define ARTPEC6_CLK_DBG_PCLK		19
+
+/* This must be the highest clock index plus one. */
+#define ARTPEC6_CLK_NUMCLOCKS		20
+
+#endif
diff --git a/include/dt-bindings/clock/bcm-cygnus.h b/include/dt-bindings/clock/bcm-cygnus.h
index 32fbc475087a..62ac5d782a00 100644
--- a/include/dt-bindings/clock/bcm-cygnus.h
+++ b/include/dt-bindings/clock/bcm-cygnus.h
@@ -65,4 +65,10 @@
 #define BCM_CYGNUS_ASIU_ADC_CLK       1
 #define BCM_CYGNUS_ASIU_PWM_CLK       2
 
+/* AUDIO clock ID */
+#define BCM_CYGNUS_AUDIOPLL           0
+#define BCM_CYGNUS_AUDIOPLL_CH0       1
+#define BCM_CYGNUS_AUDIOPLL_CH1       2
+#define BCM_CYGNUS_AUDIOPLL_CH2       3
+
 #endif /* _CLOCK_BCM_CYGNUS_H */
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 61f1d20c2a67..360e00cefd35 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -44,5 +44,23 @@
 #define BCM2835_CLOCK_EMMC		28
 #define BCM2835_CLOCK_PERI_IMAGE	29
 #define BCM2835_CLOCK_PWM		30
+#define BCM2835_CLOCK_PCM		31
 
-#define BCM2835_CLOCK_COUNT		31
+#define BCM2835_PLLA_DSI0		32
+#define BCM2835_PLLA_CCP2		33
+#define BCM2835_PLLD_DSI0		34
+#define BCM2835_PLLD_DSI1		35
+
+#define BCM2835_CLOCK_AVEO		36
+#define BCM2835_CLOCK_DFT		37
+#define BCM2835_CLOCK_GP0		38
+#define BCM2835_CLOCK_GP1		39
+#define BCM2835_CLOCK_GP2		40
+#define BCM2835_CLOCK_SLIM		41
+#define BCM2835_CLOCK_SMI		42
+#define BCM2835_CLOCK_TEC		43
+#define BCM2835_CLOCK_DPI		44
+#define BCM2835_CLOCK_CAM0		45
+#define BCM2835_CLOCK_CAM1		46
+#define BCM2835_CLOCK_DSI0E		47
+#define BCM2835_CLOCK_DSI1E		48
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index 63d01c15d2b3..c796ff02ceeb 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -79,6 +79,8 @@
 #define CLK_MOUT_CORE			58
 #define CLK_MOUT_APLL			59
 #define CLK_MOUT_ACLK_266_SUB		60
+#define CLK_MOUT_UART2			61
+#define CLK_MOUT_MMC2			62
 
 /* Dividers */
 #define CLK_DIV_GPL			64
@@ -127,6 +129,9 @@
 #define CLK_DIV_CORE			107
 #define CLK_DIV_HPM			108
 #define CLK_DIV_COPY			109
+#define CLK_DIV_UART2			110
+#define CLK_DIV_MMC2_PRE		111
+#define CLK_DIV_MMC2			112
 
 /* Gates */
 #define CLK_ASYNC_G3D			128
@@ -223,6 +228,8 @@
 #define CLK_BLOCK_MFC			219
 #define CLK_BLOCK_CAM			220
 #define CLK_SMIES			221
+#define CLK_UART2			222
+#define CLK_SDMMC2			223
 
 /* Special clocks */
 #define CLK_SCLK_JPEG			224
@@ -249,12 +256,14 @@
 #define CLK_SCLK_SPI0			245
 #define CLK_SCLK_UART1			246
 #define CLK_SCLK_UART0			247
+#define CLK_SCLK_UART2			248
+#define CLK_SCLK_MMC2			249
 
 /*
  * Total number of clocks of main CMU.
  * NOTE: Must be equal to last clock ID increased by one.
  */
-#define CLK_NR_CLKS			248
+#define CLK_NR_CLKS			250
 
 /*
  * CMU DMC
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 7699ee9c16c0..17ab8394bec7 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -217,8 +217,30 @@
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
+#define CLK_DOUT_ACLK400_WCORE	769
+#define CLK_DOUT_ACLK400_ISP	770
+#define CLK_DOUT_ACLK400_MSCL	771
+#define CLK_DOUT_ACLK200	772
+#define CLK_DOUT_ACLK200_FSYS2	773
+#define CLK_DOUT_ACLK100_NOC	774
+#define CLK_DOUT_PCLK200_FSYS	775
+#define CLK_DOUT_ACLK200_FSYS	776
+#define CLK_DOUT_ACLK333_432_GSCL	777
+#define CLK_DOUT_ACLK333_432_ISP	778
+#define CLK_DOUT_ACLK66		779
+#define CLK_DOUT_ACLK333_432_ISP0	780
+#define CLK_DOUT_ACLK266	781
+#define CLK_DOUT_ACLK166	782
+#define CLK_DOUT_ACLK333	783
+#define CLK_DOUT_ACLK333_G2D	784
+#define CLK_DOUT_ACLK266_G2D	785
+#define CLK_DOUT_ACLK_G3D	786
+#define CLK_DOUT_ACLK300_JPEG	787
+#define CLK_DOUT_ACLK300_DISP1	788
+#define CLK_DOUT_ACLK300_GSCL	789
+#define CLK_DOUT_ACLK400_DISP1	790
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		769
+#define CLK_NR_CLKS		791
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 5bd80d5ecd0f..8e024fea26e7 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -765,7 +765,12 @@
 #define CLK_SCLK_RGB_VCLK				109
 #define CLK_SCLK_RGB_TV_VCLK				110
 
-#define DISP_NR_CLK					111
+#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY		111
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY		112
+
+#define CLK_PCLK_DECON					113
+
+#define DISP_NR_CLK					114
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER				1
@@ -1298,7 +1303,7 @@
 #define CLK_MOUT_ACLK_LITE_C_B				13
 #define CLK_MOUT_ACLK_LITE_C_A				14
 
-#define CLK_DIV_SCLK_ISP_WPWM				15
+#define CLK_DIV_SCLK_ISP_MPWM				15
 #define CLK_DIV_PCLK_CAM1_83				16
 #define CLK_DIV_PCLK_CAM1_166				17
 #define CLK_DIV_PCLK_DBG_CAM1				18
diff --git a/include/dt-bindings/clock/hi3519-clock.h b/include/dt-bindings/clock/hi3519-clock.h
new file mode 100644
index 000000000000..14f4d2184e5a
--- /dev/null
+++ b/include/dt-bindings/clock/hi3519-clock.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FMC_CLK			1
+#define HI3519_SPI0_CLK			2
+#define HI3519_SPI1_CLK			3
+#define HI3519_SPI2_CLK			4
+#define HI3519_UART0_CLK		5
+#define HI3519_UART1_CLK		6
+#define HI3519_UART2_CLK		7
+#define HI3519_UART3_CLK		8
+#define HI3519_UART4_CLK		9
+#define HI3519_PWM_CLK			10
+#define HI3519_DMA_CLK			11
+#define HI3519_IR_CLK			12
+#define HI3519_ETH_PHY_CLK		13
+#define HI3519_ETH_MAC_CLK		14
+#define HI3519_ETH_MACIF_CLK		15
+#define HI3519_USB2_BUS_CLK		16
+#define HI3519_USB2_PORT_CLK		17
+#define HI3519_USB3_CLK			18
+
+#endif	/* __DTS_HI3519_CLOCK_H */
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 77985cc43316..29050337d9d5 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -255,6 +255,20 @@
 #define IMX6QDL_CLK_CAAM_ACLK			242
 #define IMX6QDL_CLK_CAAM_IPG			243
 #define IMX6QDL_CLK_SPDIF_GCLK			244
-#define IMX6QDL_CLK_END				245
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_END				259
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
index c343894ce603..fd8aee8f64ae 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -21,13 +21,13 @@
 #define IMX6UL_PLL5_BYPASS_SRC		8
 #define IMX6UL_PLL6_BYPASS_SRC		9
 #define IMX6UL_PLL7_BYPASS_SRC		10
-#define IMX6UL_CLK_PLL1 		11
-#define IMX6UL_CLK_PLL2 		12
-#define IMX6UL_CLK_PLL3 		13
-#define IMX6UL_CLK_PLL4 		14
-#define IMX6UL_CLK_PLL5 		15
-#define IMX6UL_CLK_PLL6 		16
-#define IMX6UL_CLK_PLL7 		17
+#define IMX6UL_CLK_PLL1			11
+#define IMX6UL_CLK_PLL2			12
+#define IMX6UL_CLK_PLL3			13
+#define IMX6UL_CLK_PLL4			14
+#define IMX6UL_CLK_PLL5			15
+#define IMX6UL_CLK_PLL6			16
+#define IMX6UL_CLK_PLL7			17
 #define IMX6UL_PLL1_BYPASS		18
 #define IMX6UL_PLL2_BYPASS		19
 #define IMX6UL_PLL3_BYPASS		20
@@ -37,7 +37,7 @@
 #define IMX6UL_PLL7_BYPASS		24
 #define IMX6UL_CLK_PLL1_SYS		25
 #define IMX6UL_CLK_PLL2_BUS		26
-#define IMX6UL_CLK_PLL3_USB_OTG 	27
+#define IMX6UL_CLK_PLL3_USB_OTG		27
 #define IMX6UL_CLK_PLL4_AUDIO		28
 #define IMX6UL_CLK_PLL5_VIDEO		29
 #define IMX6UL_CLK_PLL6_ENET		30
@@ -66,7 +66,7 @@
 #define IMX6UL_CLK_PLL2_198M		53
 #define IMX6UL_CLK_PLL3_80M		54
 #define IMX6UL_CLK_PLL3_60M		55
-#define IMX6UL_CLK_STEP 		56
+#define IMX6UL_CLK_STEP			56
 #define IMX6UL_CLK_PLL1_SW		57
 #define IMX6UL_CLK_AXI_ALT_SEL		58
 #define IMX6UL_CLK_AXI_SEL		59
@@ -78,7 +78,7 @@
 #define IMX6UL_CLK_USDHC2_SEL		65
 #define IMX6UL_CLK_BCH_SEL		66
 #define IMX6UL_CLK_GPMI_SEL		67
-#define IMX6UL_CLK_EIM_SLOW_SEL 	68
+#define IMX6UL_CLK_EIM_SLOW_SEL		68
 #define IMX6UL_CLK_SPDIF_SEL		69
 #define IMX6UL_CLK_SAI1_SEL		70
 #define IMX6UL_CLK_SAI2_SEL		71
@@ -105,9 +105,9 @@
 #define IMX6UL_CLK_LDB_DI1_DIV_SEL	92
 #define IMX6UL_CLK_ARM			93
 #define IMX6UL_CLK_PERIPH_CLK2		94
-#define IMX6UL_CLK_PERIPH2_CLK2 	95
+#define IMX6UL_CLK_PERIPH2_CLK2		95
 #define IMX6UL_CLK_AHB			96
-#define IMX6UL_CLK_MMDC_PODF 		97
+#define IMX6UL_CLK_MMDC_PODF		97
 #define IMX6UL_CLK_AXI_PODF		98
 #define IMX6UL_CLK_PERCLK		99
 #define IMX6UL_CLK_IPG			100
@@ -133,16 +133,16 @@
 #define IMX6UL_CLK_CAN_PODF		120
 #define IMX6UL_CLK_ECSPI_PODF		121
 #define IMX6UL_CLK_UART_PODF		122
-#define IMX6UL_CLK_ADC1 		123
-#define IMX6UL_CLK_ADC2 		124
+#define IMX6UL_CLK_ADC1			123
+#define IMX6UL_CLK_ADC2			124
 #define IMX6UL_CLK_AIPSTZ1		125
 #define IMX6UL_CLK_AIPSTZ2		126
 #define IMX6UL_CLK_AIPSTZ3		127
 #define IMX6UL_CLK_APBHDMA		128
 #define IMX6UL_CLK_ASRC_IPG		129
 #define IMX6UL_CLK_ASRC_MEM		130
-#define IMX6UL_CLK_GPMI_BCH_APB  	131
-#define IMX6UL_CLK_GPMI_BCH 		132
+#define IMX6UL_CLK_GPMI_BCH_APB		131
+#define IMX6UL_CLK_GPMI_BCH		132
 #define IMX6UL_CLK_GPMI_IO		133
 #define IMX6UL_CLK_GPMI_APB		134
 #define IMX6UL_CLK_CAAM_MEM		135
@@ -154,7 +154,7 @@
 #define IMX6UL_CLK_ECSPI3		141
 #define IMX6UL_CLK_ECSPI4		142
 #define IMX6UL_CLK_EIM			143
-#define IMX6UL_CLK_ENET  		144
+#define IMX6UL_CLK_ENET			144
 #define IMX6UL_CLK_ENET_AHB		145
 #define IMX6UL_CLK_EPIT1		146
 #define IMX6UL_CLK_EPIT2		147
@@ -166,63 +166,63 @@
 #define IMX6UL_CLK_GPT1_SERIAL		153
 #define IMX6UL_CLK_GPT2_BUS		154
 #define IMX6UL_CLK_GPT2_SERIAL		155
-#define IMX6UL_CLK_I2C1 		156
-#define IMX6UL_CLK_I2C2 		157
-#define IMX6UL_CLK_I2C3 		158
-#define IMX6UL_CLK_I2C4 		159
-#define IMX6UL_CLK_IOMUXC 		160
-#define IMX6UL_CLK_LCDIF_APB 		161
-#define IMX6UL_CLK_LCDIF_PIX 		162
-#define IMX6UL_CLK_MMDC_P0_FAST 	163
-#define IMX6UL_CLK_MMDC_P0_IPG  	164
-#define IMX6UL_CLK_OCOTP 		165
-#define IMX6UL_CLK_OCRAM 		166
-#define IMX6UL_CLK_PWM1 		167
-#define IMX6UL_CLK_PWM2 		168
-#define IMX6UL_CLK_PWM3 		169
-#define IMX6UL_CLK_PWM4 		170
-#define IMX6UL_CLK_PWM5 		171
-#define IMX6UL_CLK_PWM6 		172
-#define IMX6UL_CLK_PWM7 		173
-#define IMX6UL_CLK_PWM8 		174
-#define IMX6UL_CLK_PXP  		175
-#define IMX6UL_CLK_QSPI 		176
-#define IMX6UL_CLK_ROM  		177
-#define IMX6UL_CLK_SAI1 		178
-#define IMX6UL_CLK_SAI1_IPG 		179
-#define IMX6UL_CLK_SAI2 		180
-#define IMX6UL_CLK_SAI2_IPG 		181
-#define IMX6UL_CLK_SAI3 		182
-#define IMX6UL_CLK_SAI3_IPG 		183
-#define IMX6UL_CLK_SDMA 		184
-#define IMX6UL_CLK_SIM  		185
-#define IMX6UL_CLK_SIM_S 		186
-#define IMX6UL_CLK_SPBA 		187
-#define IMX6UL_CLK_SPDIF 		188
-#define IMX6UL_CLK_UART1_IPG 		189
-#define IMX6UL_CLK_UART1_SERIAL 	190
-#define IMX6UL_CLK_UART2_IPG 		191
-#define IMX6UL_CLK_UART2_SERIAL 	192
-#define IMX6UL_CLK_UART3_IPG 		193
-#define IMX6UL_CLK_UART3_SERIAL 	194
-#define IMX6UL_CLK_UART4_IPG 		195
-#define IMX6UL_CLK_UART4_SERIAL 	196
-#define IMX6UL_CLK_UART5_IPG 		197
-#define IMX6UL_CLK_UART5_SERIAL 	198
-#define IMX6UL_CLK_UART6_IPG 		199
-#define IMX6UL_CLK_UART6_SERIAL 	200
-#define IMX6UL_CLK_UART7_IPG 		201
-#define IMX6UL_CLK_UART7_SERIAL 	202
-#define IMX6UL_CLK_UART8_IPG 		203
-#define IMX6UL_CLK_UART8_SERIAL 	204
-#define IMX6UL_CLK_USBOH3 		205
-#define IMX6UL_CLK_USDHC1 		206
-#define IMX6UL_CLK_USDHC2 		207
-#define IMX6UL_CLK_WDOG1 		208
-#define IMX6UL_CLK_WDOG2 		209
-#define IMX6UL_CLK_WDOG3 		210
+#define IMX6UL_CLK_I2C1			156
+#define IMX6UL_CLK_I2C2			157
+#define IMX6UL_CLK_I2C3			158
+#define IMX6UL_CLK_I2C4			159
+#define IMX6UL_CLK_IOMUXC		160
+#define IMX6UL_CLK_LCDIF_APB		161
+#define IMX6UL_CLK_LCDIF_PIX		162
+#define IMX6UL_CLK_MMDC_P0_FAST		163
+#define IMX6UL_CLK_MMDC_P0_IPG		164
+#define IMX6UL_CLK_OCOTP		165
+#define IMX6UL_CLK_OCRAM		166
+#define IMX6UL_CLK_PWM1			167
+#define IMX6UL_CLK_PWM2			168
+#define IMX6UL_CLK_PWM3			169
+#define IMX6UL_CLK_PWM4			170
+#define IMX6UL_CLK_PWM5			171
+#define IMX6UL_CLK_PWM6			172
+#define IMX6UL_CLK_PWM7			173
+#define IMX6UL_CLK_PWM8			174
+#define IMX6UL_CLK_PXP			175
+#define IMX6UL_CLK_QSPI			176
+#define IMX6UL_CLK_ROM			177
+#define IMX6UL_CLK_SAI1			178
+#define IMX6UL_CLK_SAI1_IPG		179
+#define IMX6UL_CLK_SAI2			180
+#define IMX6UL_CLK_SAI2_IPG		181
+#define IMX6UL_CLK_SAI3			182
+#define IMX6UL_CLK_SAI3_IPG		183
+#define IMX6UL_CLK_SDMA			184
+#define IMX6UL_CLK_SIM			185
+#define IMX6UL_CLK_SIM_S		186
+#define IMX6UL_CLK_SPBA			187
+#define IMX6UL_CLK_SPDIF		188
+#define IMX6UL_CLK_UART1_IPG		189
+#define IMX6UL_CLK_UART1_SERIAL		190
+#define IMX6UL_CLK_UART2_IPG		191
+#define IMX6UL_CLK_UART2_SERIAL		192
+#define IMX6UL_CLK_UART3_IPG		193
+#define IMX6UL_CLK_UART3_SERIAL		194
+#define IMX6UL_CLK_UART4_IPG		195
+#define IMX6UL_CLK_UART4_SERIAL		196
+#define IMX6UL_CLK_UART5_IPG		197
+#define IMX6UL_CLK_UART5_SERIAL		198
+#define IMX6UL_CLK_UART6_IPG		199
+#define IMX6UL_CLK_UART6_SERIAL		200
+#define IMX6UL_CLK_UART7_IPG		201
+#define IMX6UL_CLK_UART7_SERIAL		202
+#define IMX6UL_CLK_UART8_IPG		203
+#define IMX6UL_CLK_UART8_SERIAL		204
+#define IMX6UL_CLK_USBOH3		205
+#define IMX6UL_CLK_USDHC1		206
+#define IMX6UL_CLK_USDHC2		207
+#define IMX6UL_CLK_WDOG1		208
+#define IMX6UL_CLK_WDOG2		209
+#define IMX6UL_CLK_WDOG3		210
 #define IMX6UL_CLK_LDB_DI0		211
-#define IMX6UL_CLK_AXI  		212
+#define IMX6UL_CLK_AXI			212
 #define IMX6UL_CLK_SPDIF_GCLK		213
 #define IMX6UL_CLK_GPT_3M		214
 #define IMX6UL_CLK_SIM2			215
@@ -234,7 +234,8 @@
 #define IMX6UL_CLK_CSI_SEL		221
 #define IMX6UL_CLK_CSI_PODF		222
 #define IMX6UL_CLK_PLL3_120M		223
+#define IMX6UL_CLK_KPP			224
 
-#define IMX6UL_CLK_END			224
+#define IMX6UL_CLK_END			225
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index edca8985c50e..1183347c383f 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -448,5 +448,6 @@
 #define IMX7D_PLL_DRAM_TEST_DIV		435
 #define IMX7D_ADC_ROOT_CLK		436
 #define IMX7D_CLK_ARM			437
-#define IMX7D_CLK_END			438
+#define IMX7D_CKIL			438
+#define IMX7D_CLK_END			439
 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h
index bcb1c9a73519..d41b6fea1450 100644
--- a/include/dt-bindings/clock/lpc32xx-clock.h
+++ b/include/dt-bindings/clock/lpc32xx-clock.h
@@ -47,6 +47,7 @@
 #define LPC32XX_CLK_PWM1	32
 #define LPC32XX_CLK_PWM2	33
 #define LPC32XX_CLK_ADC		34
+#define LPC32XX_CLK_HCLK_PLL	35
 
 /* LPC32XX USB clocks */
 #define LPC32XX_USB_CLK_I2C	1
diff --git a/include/dt-bindings/clock/microchip,pic32-clock.h b/include/dt-bindings/clock/microchip,pic32-clock.h
new file mode 100644
index 000000000000..184647a6a8de
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,pic32-clock.h
@@ -0,0 +1,42 @@
+/*
+ * Purna Chandra Mandal,<purna.mandal@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+
+/* clock output indices */
+#define POSCCLK		0
+#define FRCCLK		1
+#define BFRCCLK		2
+#define LPRCCLK		3
+#define SOSCCLK		4
+#define FRCDIVCLK	5
+#define PLLCLK		6
+#define SCLK		7
+#define PB1CLK		8
+#define PB2CLK		9
+#define PB3CLK		10
+#define PB4CLK		11
+#define PB5CLK		12
+#define PB6CLK		13
+#define PB7CLK		14
+#define REF1CLK		15
+#define REF2CLK		16
+#define REF3CLK		17
+#define REF4CLK		18
+#define REF5CLK		19
+#define UPLLCLK		20
+#define MAXCLKS		21
+
+#endif	/* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 7956ba1bc974..6094bf7e50ab 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -176,7 +176,8 @@
 #define CLK_APMIXED_LVDSPLL		13
 #define CLK_APMIXED_MSDCPLL2		14
 #define CLK_APMIXED_REF2USB_TX		15
-#define CLK_APMIXED_NR_CLK		16
+#define CLK_APMIXED_HDMI_REF		16
+#define CLK_APMIXED_NR_CLK		17
 
 /* INFRA_SYS */
 
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
new file mode 100644
index 000000000000..6240e5b0e900
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -0,0 +1,158 @@
+/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef __QCOM_CLK_IPQ4019_H__
+#define __QCOM_CLK_IPQ4019_H__
+
+#define GCC_DUMMY_CLK					0
+#define AUDIO_CLK_SRC					1
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			2
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			3
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			4
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			5
+#define BLSP1_UART1_APPS_CLK_SRC			6
+#define BLSP1_UART2_APPS_CLK_SRC			7
+#define GCC_USB3_MOCK_UTMI_CLK_SRC			8
+#define GCC_APPS_CLK_SRC				9
+#define GCC_APPS_AHB_CLK_SRC				10
+#define GP1_CLK_SRC					11
+#define GP2_CLK_SRC					12
+#define GP3_CLK_SRC					13
+#define SDCC1_APPS_CLK_SRC				14
+#define FEPHY_125M_DLY_CLK_SRC				15
+#define WCSS2G_CLK_SRC					16
+#define WCSS5G_CLK_SRC					17
+#define GCC_APSS_AHB_CLK				18
+#define GCC_AUDIO_AHB_CLK				19
+#define GCC_AUDIO_PWM_CLK				20
+#define GCC_BLSP1_AHB_CLK				21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			25
+#define GCC_BLSP1_UART1_APPS_CLK			26
+#define GCC_BLSP1_UART2_APPS_CLK			27
+#define GCC_DCD_XO_CLK					28
+#define GCC_GP1_CLK					29
+#define GCC_GP2_CLK					30
+#define GCC_GP3_CLK					31
+#define GCC_BOOT_ROM_AHB_CLK				32
+#define GCC_CRYPTO_AHB_CLK				33
+#define GCC_CRYPTO_AXI_CLK				34
+#define GCC_CRYPTO_CLK					35
+#define GCC_ESS_CLK					36
+#define GCC_IMEM_AXI_CLK				37
+#define GCC_IMEM_CFG_AHB_CLK				38
+#define GCC_PCIE_AHB_CLK				39
+#define GCC_PCIE_AXI_M_CLK				40
+#define GCC_PCIE_AXI_S_CLK				41
+#define GCC_PCNOC_AHB_CLK				42
+#define GCC_PRNG_AHB_CLK				43
+#define GCC_QPIC_AHB_CLK				44
+#define GCC_QPIC_CLK					45
+#define GCC_SDCC1_AHB_CLK				46
+#define GCC_SDCC1_APPS_CLK				47
+#define GCC_SNOC_PCNOC_AHB_CLK				48
+#define GCC_SYS_NOC_125M_CLK				49
+#define GCC_SYS_NOC_AXI_CLK				50
+#define GCC_TCSR_AHB_CLK				51
+#define GCC_TLMM_AHB_CLK				52
+#define GCC_USB2_MASTER_CLK				53
+#define GCC_USB2_SLEEP_CLK				54
+#define GCC_USB2_MOCK_UTMI_CLK				55
+#define GCC_USB3_MASTER_CLK				56
+#define GCC_USB3_SLEEP_CLK				57
+#define GCC_USB3_MOCK_UTMI_CLK				58
+#define GCC_WCSS2G_CLK					59
+#define GCC_WCSS2G_REF_CLK				60
+#define GCC_WCSS2G_RTC_CLK				61
+#define GCC_WCSS5G_CLK					62
+#define GCC_WCSS5G_REF_CLK				63
+#define GCC_WCSS5G_RTC_CLK				64
+
+#define WIFI0_CPU_INIT_RESET				0
+#define WIFI0_RADIO_SRIF_RESET				1
+#define WIFI0_RADIO_WARM_RESET				2
+#define WIFI0_RADIO_COLD_RESET				3
+#define WIFI0_CORE_WARM_RESET				4
+#define WIFI0_CORE_COLD_RESET				5
+#define WIFI1_CPU_INIT_RESET				6
+#define WIFI1_RADIO_SRIF_RESET				7
+#define WIFI1_RADIO_WARM_RESET				8
+#define WIFI1_RADIO_COLD_RESET				9
+#define WIFI1_CORE_WARM_RESET				10
+#define WIFI1_CORE_COLD_RESET				11
+#define USB3_UNIPHY_PHY_ARES				12
+#define USB3_HSPHY_POR_ARES				13
+#define USB3_HSPHY_S_ARES				14
+#define USB2_HSPHY_POR_ARES				15
+#define USB2_HSPHY_S_ARES				16
+#define PCIE_PHY_AHB_ARES				17
+#define PCIE_AHB_ARES					18
+#define PCIE_PWR_ARES					19
+#define PCIE_PIPE_STICKY_ARES				20
+#define PCIE_AXI_M_STICKY_ARES				21
+#define PCIE_PHY_ARES					22
+#define PCIE_PARF_XPU_ARES				23
+#define PCIE_AXI_S_XPU_ARES				24
+#define PCIE_AXI_M_VMIDMT_ARES				25
+#define PCIE_PIPE_ARES					26
+#define PCIE_AXI_S_ARES					27
+#define PCIE_AXI_M_ARES					28
+#define ESS_RESET					29
+#define GCC_BLSP1_BCR					30
+#define GCC_BLSP1_QUP1_BCR				31
+#define GCC_BLSP1_UART1_BCR				32
+#define GCC_BLSP1_QUP2_BCR				33
+#define GCC_BLSP1_UART2_BCR				34
+#define GCC_BIMC_BCR					35
+#define GCC_TLMM_BCR					36
+#define GCC_IMEM_BCR					37
+#define GCC_ESS_BCR					38
+#define GCC_PRNG_BCR					39
+#define GCC_BOOT_ROM_BCR				40
+#define GCC_CRYPTO_BCR					41
+#define GCC_SDCC1_BCR					42
+#define GCC_SEC_CTRL_BCR				43
+#define GCC_AUDIO_BCR					44
+#define GCC_QPIC_BCR					45
+#define GCC_PCIE_BCR					46
+#define GCC_USB2_BCR					47
+#define GCC_USB2_PHY_BCR				48
+#define GCC_USB3_BCR					49
+#define GCC_USB3_PHY_BCR				50
+#define GCC_SYSTEM_NOC_BCR				51
+#define GCC_PCNOC_BCR					52
+#define GCC_DCD_BCR					53
+#define GCC_SNOC_BUS_TIMEOUT0_BCR			54
+#define GCC_SNOC_BUS_TIMEOUT1_BCR			55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR			56
+#define GCC_SNOC_BUS_TIMEOUT3_BCR			57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR			58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR			59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR			60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR			61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR			62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR			63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR			64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR			65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR			66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR			67
+#define GCC_TCSR_BCR					68
+#define GCC_QDSS_BCR					69
+#define GCC_MPM_BCR					70
+#define GCC_SPDM_BCR					71
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
index 257e2fbedd94..28a27a4ed3c3 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -174,6 +174,7 @@
 #define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK		157
 #define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK		158
 #define GCC_CODEC_DIGCODEC_CLK			159
+#define GCC_MSS_Q6_BIMC_AXI_CLK			160
 
 /* Indexes for GDSCs */
 #define BIMC_GDSC				0
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index 888e75ce8fec..6f814db11c7e 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -336,4 +336,15 @@
 #define GCC_MSS_Q6_BCR						99
 #define GCC_QREFS_VBG_CAL_BCR					100
 
+/* Indexes for GDSCs */
+#define AGGRE0_NOC_GDSC			0
+#define HLOS1_VOTE_AGGRE0_NOC_GDSC	1
+#define HLOS1_VOTE_LPASS_ADSP_GDSC	2
+#define HLOS1_VOTE_LPASS_CORE_GDSC	3
+#define USB30_GDSC			4
+#define PCIE0_GDSC			5
+#define PCIE1_GDSC			6
+#define PCIE2_GDSC			7
+#define UFS_GDSC			8
+
 #endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
index 9b81ca65fcec..7d3a7fa1a1bd 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h
@@ -282,4 +282,21 @@
 #define FD_BCR						58
 #define MMSS_SPDM_RM_BCR				59
 
+/* Indexes for GDSCs */
+#define MMAGIC_VIDEO_GDSC	0
+#define MMAGIC_MDSS_GDSC	1
+#define MMAGIC_CAMSS_GDSC	2
+#define GPU_GDSC		3
+#define VENUS_GDSC		4
+#define VENUS_CORE0_GDSC	5
+#define VENUS_CORE1_GDSC	6
+#define CAMSS_GDSC		7
+#define VFE0_GDSC		8
+#define VFE1_GDSC		9
+#define JPEG_GDSC		10
+#define CPP_GDSC		11
+#define FD_GDSC			12
+#define MDSS_GDSC		13
+#define GPU_GX_GDSC		14
+
 #endif
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 7b1ad8922eec..fa5e8da809f2 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -66,6 +66,7 @@
 #define R8A7790_CLK_IIC2		0
 #define R8A7790_CLK_TPU0		4
 #define R8A7790_CLK_MMCIF1		5
+#define R8A7790_CLK_SCIF2		10
 #define R8A7790_CLK_SDHI3		11
 #define R8A7790_CLK_SDHI2		12
 #define R8A7790_CLK_SDHI1		13
diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h
index 1579e07f96a3..efcbc594fe82 100644
--- a/include/dt-bindings/clock/r8a7793-clock.h
+++ b/include/dt-bindings/clock/r8a7793-clock.h
@@ -145,6 +145,8 @@
 #define R8A7793_CLK_SCU_ALL		17
 #define R8A7793_CLK_SCU_DVC1		18
 #define R8A7793_CLK_SCU_DVC0		19
+#define R8A7793_CLK_SCU_CTU1_MIX1	20
+#define R8A7793_CLK_SCU_CTU0_MIX0	21
 #define R8A7793_CLK_SCU_SRC9		22
 #define R8A7793_CLK_SCU_SRC8		23
 #define R8A7793_CLK_SCU_SRC7		24
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index a7a7e0370968..4d3ecd626c1f 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -21,6 +21,7 @@
 #define R8A7794_CLK_SDH			6
 #define R8A7794_CLK_SD0			7
 #define R8A7794_CLK_Z			8
+#define R8A7794_CLK_RCAN		9
 
 /* MSTP0 */
 #define R8A7794_CLK_MSIOF0		0
@@ -56,6 +57,8 @@
 #define R8A7794_CLK_SDHI1		12
 #define R8A7794_CLK_SDHI0		14
 #define R8A7794_CLK_MMCIF0		15
+#define R8A7794_CLK_IIC0		18
+#define R8A7794_CLK_IIC1		23
 #define R8A7794_CLK_CMT1		29
 #define R8A7794_CLK_USBDMAC0		30
 #define R8A7794_CLK_USBDMAC1		31
@@ -84,6 +87,7 @@
 /* MSTP8 */
 #define R8A7794_CLK_VIN1		10
 #define R8A7794_CLK_VIN0		11
+#define R8A7794_CLK_ETHERAVB		12
 #define R8A7794_CLK_ETHER		13
 
 /* MSTP9 */
@@ -94,6 +98,8 @@
 #define R8A7794_CLK_GPIO2		10
 #define R8A7794_CLK_GPIO1		11
 #define R8A7794_CLK_GPIO0		12
+#define R8A7794_CLK_RCAN1		15
+#define R8A7794_CLK_RCAN0		16
 #define R8A7794_CLK_QSPI_MOD		17
 #define R8A7794_CLK_I2C5		25
 #define R8A7794_CLK_I2C4		27
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
index ebc7a7b43f52..de44109a3a04 100644
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -54,6 +54,7 @@
 #define SCLK_PVTM_VIDEO		125
 #define SCLK_MAC		151
 #define SCLK_MACREF		152
+#define SCLK_MACPLL		153
 #define SCLK_SFC		160
 
 /* aclk gates */
@@ -92,6 +93,7 @@
 #define HCLK_SDMMC		456
 #define HCLK_SDIO		457
 #define HCLK_EMMC		459
+#define HCLK_MAC		460
 #define HCLK_I2S		462
 #define HCLK_LCDC		465
 #define HCLK_ROM		467
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
index 8df77a7c030b..4f53e70f68ee 100644
--- a/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -55,6 +55,7 @@
 #define SCLK_TIMER6		90
 #define SCLK_JTAG		91
 #define SCLK_SMC		92
+#define SCLK_TSADC		93
 
 #define DCLK_LCDC0		190
 #define DCLK_LCDC1		191
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index a78dd891e24a..5d43ed9b05ad 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -29,6 +29,7 @@
 #define SCLK_SDMMC		68
 #define SCLK_SDIO		69
 #define SCLK_EMMC		71
+#define SCLK_TSADC		72
 #define SCLK_UART0		77
 #define SCLK_UART1		78
 #define SCLK_UART2		79
@@ -49,10 +50,17 @@
 #define SCLK_SDMMC_SAMPLE	118
 #define SCLK_SDIO_SAMPLE	119
 #define SCLK_EMMC_SAMPLE	121
+#define SCLK_VOP		122
+#define SCLK_HDMI_HDCP		123
+
+/* dclk gates */
+#define DCLK_VOP		190
+#define DCLK_HDMI_PHY		191
 
 /* aclk gates */
 #define ACLK_DMAC		194
 #define ACLK_PERI		210
+#define ACLK_VOP		211
 
 /* pclk gates */
 #define PCLK_GPIO0		320
@@ -68,11 +76,15 @@
 #define PCLK_UART0		341
 #define PCLK_UART1		342
 #define PCLK_UART2		343
+#define PCLK_TSADC		344
 #define PCLK_PWM		350
 #define PCLK_TIMER		353
 #define PCLK_PERI		363
+#define PCLK_HDMI_CTRL		364
+#define PCLK_HDMI_PHY		365
 
 /* hclk gates */
+#define HCLK_VOP		452
 #define HCLK_NANDC		453
 #define HCLK_SDMMC		456
 #define HCLK_SDIO		457
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
new file mode 100644
index 000000000000..50a44cffb070
--- /dev/null
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -0,0 +1,755 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng <zhengxing@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+
+/* core clocks */
+#define PLL_APLLL			1
+#define PLL_APLLB			2
+#define PLL_DPLL			3
+#define PLL_CPLL			4
+#define PLL_GPLL			5
+#define PLL_NPLL			6
+#define PLL_VPLL			7
+#define ARMCLKL				8
+#define ARMCLKB				9
+
+/* sclk gates (special clocks) */
+#define SCLK_I2C1			65
+#define SCLK_I2C2			66
+#define SCLK_I2C3			67
+#define SCLK_I2C5			68
+#define SCLK_I2C6			69
+#define SCLK_I2C7			70
+#define SCLK_SPI0			71
+#define SCLK_SPI1			72
+#define SCLK_SPI2			73
+#define SCLK_SPI4			74
+#define SCLK_SPI5			75
+#define SCLK_SDMMC			76
+#define SCLK_SDIO			77
+#define SCLK_EMMC			78
+#define SCLK_TSADC			79
+#define SCLK_SARADC			80
+#define SCLK_UART0			81
+#define SCLK_UART1			82
+#define SCLK_UART2			83
+#define SCLK_UART3			84
+#define SCLK_SPDIF_8CH			85
+#define SCLK_I2S0_8CH			86
+#define SCLK_I2S1_8CH			87
+#define SCLK_I2S2_8CH			88
+#define SCLK_I2S_8CH_OUT		89
+#define SCLK_TIMER00			90
+#define SCLK_TIMER01			91
+#define SCLK_TIMER02			92
+#define SCLK_TIMER03			93
+#define SCLK_TIMER04			94
+#define SCLK_TIMER05			95
+#define SCLK_TIMER06			96
+#define SCLK_TIMER07			97
+#define SCLK_TIMER08			98
+#define SCLK_TIMER09			99
+#define SCLK_TIMER10			100
+#define SCLK_TIMER11			101
+#define SCLK_MACREF			102
+#define SCLK_MAC_RX			103
+#define SCLK_MAC_TX			104
+#define SCLK_MAC			105
+#define SCLK_MACREF_OUT			106
+#define SCLK_VOP0_PWM			107
+#define SCLK_VOP1_PWM			108
+#define SCLK_RGA_CORE			109
+#define SCLK_ISP0			110
+#define SCLK_ISP1			111
+#define SCLK_HDMI_CEC			112
+#define SCLK_HDMI_SFR			113
+#define SCLK_DP_CORE			114
+#define SCLK_PVTM_CORE_L		115
+#define SCLK_PVTM_CORE_B		116
+#define SCLK_PVTM_GPU			117
+#define SCLK_PVTM_DDR			118
+#define SCLK_MIPIDPHY_REF		119
+#define SCLK_MIPIDPHY_CFG		120
+#define SCLK_HSICPHY			121
+#define SCLK_USBPHY480M			122
+#define SCLK_USB2PHY0_REF		123
+#define SCLK_USB2PHY1_REF		124
+#define SCLK_UPHY0_TCPDPHY_REF		125
+#define SCLK_UPHY0_TCPDCORE		126
+#define SCLK_UPHY1_TCPDPHY_REF		127
+#define SCLK_UPHY1_TCPDCORE		128
+#define SCLK_USB3OTG0_REF		129
+#define SCLK_USB3OTG1_REF		130
+#define SCLK_USB3OTG0_SUSPEND		131
+#define SCLK_USB3OTG1_SUSPEND		132
+#define SCLK_CRYPTO0			133
+#define SCLK_CRYPTO1			134
+#define SCLK_CCI_TRACE			135
+#define SCLK_CS				136
+#define SCLK_CIF_OUT			137
+#define SCLK_PCIEPHY_REF		138
+#define SCLK_PCIE_CORE			139
+#define SCLK_M0_PERILP			140
+#define SCLK_M0_PERILP_DEC		141
+#define SCLK_CM0S			142
+#define SCLK_DBG_NOC			143
+#define SCLK_DBG_PD_CORE_B		144
+#define SCLK_DBG_PD_CORE_L		145
+#define SCLK_DFIMON0_TIMER		146
+#define SCLK_DFIMON1_TIMER		147
+#define SCLK_INTMEM0			148
+#define SCLK_INTMEM1			149
+#define SCLK_INTMEM2			150
+#define SCLK_INTMEM3			151
+#define SCLK_INTMEM4			152
+#define SCLK_INTMEM5			153
+#define SCLK_SDMMC_DRV			154
+#define SCLK_SDMMC_SAMPLE		155
+#define SCLK_SDIO_DRV			156
+#define SCLK_SDIO_SAMPLE		157
+#define SCLK_VDU_CORE			158
+#define SCLK_VDU_CA			159
+#define SCLK_PCIE_PM			160
+#define SCLK_SPDIF_REC_DPTX		161
+#define SCLK_DPHY_PLL			162
+#define SCLK_DPHY_TX0_CFG		163
+#define SCLK_DPHY_TX1RX1_CFG		164
+#define SCLK_DPHY_RX0_CFG		165
+#define SCLK_RMII_SRC			166
+#define SCLK_PCIEPHY_REF100M		167
+
+#define DCLK_VOP0			180
+#define DCLK_VOP1			181
+#define DCLK_VOP0_DIV			182
+#define DCLK_VOP1_DIV			183
+#define DCLK_M0_PERILP			184
+
+#define FCLK_CM0S			190
+
+/* aclk gates */
+#define ACLK_PERIHP			192
+#define ACLK_PERIHP_NOC			193
+#define ACLK_PERILP0			194
+#define ACLK_PERILP0_NOC		195
+#define ACLK_PERF_PCIE			196
+#define ACLK_PCIE			197
+#define ACLK_INTMEM			198
+#define ACLK_TZMA			199
+#define ACLK_DCF			200
+#define ACLK_CCI			201
+#define ACLK_CCI_NOC0			202
+#define ACLK_CCI_NOC1			203
+#define ACLK_CCI_GRF			204
+#define ACLK_CENTER			205
+#define ACLK_CENTER_MAIN_NOC		206
+#define ACLK_CENTER_PERI_NOC		207
+#define ACLK_GPU			208
+#define ACLK_PERF_GPU			209
+#define ACLK_GPU_GRF			210
+#define ACLK_DMAC0_PERILP		211
+#define ACLK_DMAC1_PERILP		212
+#define ACLK_GMAC			213
+#define ACLK_GMAC_NOC			214
+#define ACLK_PERF_GMAC			215
+#define ACLK_VOP0_NOC			216
+#define ACLK_VOP0			217
+#define ACLK_VOP1_NOC			218
+#define ACLK_VOP1			219
+#define ACLK_RGA			220
+#define ACLK_RGA_NOC			221
+#define ACLK_HDCP			222
+#define ACLK_HDCP_NOC			223
+#define ACLK_HDCP22			224
+#define ACLK_IEP			225
+#define ACLK_IEP_NOC			226
+#define ACLK_VIO			227
+#define ACLK_VIO_NOC			228
+#define ACLK_ISP0			229
+#define ACLK_ISP1			230
+#define ACLK_ISP0_NOC			231
+#define ACLK_ISP1_NOC			232
+#define ACLK_ISP0_WRAPPER		233
+#define ACLK_ISP1_WRAPPER		234
+#define ACLK_VCODEC			235
+#define ACLK_VCODEC_NOC			236
+#define ACLK_VDU			237
+#define ACLK_VDU_NOC			238
+#define ACLK_PERI			239
+#define ACLK_EMMC			240
+#define ACLK_EMMC_CORE			241
+#define ACLK_EMMC_NOC			242
+#define ACLK_EMMC_GRF			243
+#define ACLK_USB3			244
+#define ACLK_USB3_NOC			245
+#define ACLK_USB3OTG0			246
+#define ACLK_USB3OTG1			247
+#define ACLK_USB3_RKSOC_AXI_PERF	248
+#define ACLK_USB3_GRF			249
+#define ACLK_GIC			250
+#define ACLK_GIC_NOC			251
+#define ACLK_GIC_ADB400_CORE_L_2_GIC	252
+#define ACLK_GIC_ADB400_CORE_B_2_GIC	253
+#define ACLK_GIC_ADB400_GIC_2_CORE_L	254
+#define ACLK_GIC_ADB400_GIC_2_CORE_B	255
+#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
+#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
+#define ACLK_ADB400M_PD_CORE_L		258
+#define ACLK_ADB400M_PD_CORE_B		259
+#define ACLK_PERF_CORE_L		260
+#define ACLK_PERF_CORE_B		261
+#define ACLK_GIC_PRE			262
+#define ACLK_VOP0_PRE			263
+#define ACLK_VOP1_PRE			264
+
+/* pclk gates */
+#define PCLK_PERIHP			320
+#define PCLK_PERIHP_NOC			321
+#define PCLK_PERILP0			322
+#define PCLK_PERILP1			323
+#define PCLK_PERILP1_NOC		324
+#define PCLK_PERILP_SGRF		325
+#define PCLK_PERIHP_GRF			326
+#define PCLK_PCIE			327
+#define PCLK_SGRF			328
+#define PCLK_INTR_ARB			329
+#define PCLK_CENTER_MAIN_NOC		330
+#define PCLK_CIC			331
+#define PCLK_COREDBG_B			332
+#define PCLK_COREDBG_L			333
+#define PCLK_DBG_CXCS_PD_CORE_B		334
+#define PCLK_DCF			335
+#define PCLK_GPIO2			336
+#define PCLK_GPIO3			337
+#define PCLK_GPIO4			338
+#define PCLK_GRF			339
+#define PCLK_HSICPHY			340
+#define PCLK_I2C1			341
+#define PCLK_I2C2			342
+#define PCLK_I2C3			343
+#define PCLK_I2C5			344
+#define PCLK_I2C6			345
+#define PCLK_I2C7			346
+#define PCLK_SPI0			347
+#define PCLK_SPI1			348
+#define PCLK_SPI2			349
+#define PCLK_SPI4			350
+#define PCLK_SPI5			351
+#define PCLK_UART0			352
+#define PCLK_UART1			353
+#define PCLK_UART2			354
+#define PCLK_UART3			355
+#define PCLK_TSADC			356
+#define PCLK_SARADC			357
+#define PCLK_GMAC			358
+#define PCLK_GMAC_NOC			359
+#define PCLK_TIMER0			360
+#define PCLK_TIMER1			361
+#define PCLK_EDP			362
+#define PCLK_EDP_NOC			363
+#define PCLK_EDP_CTRL			364
+#define PCLK_VIO			365
+#define PCLK_VIO_NOC			366
+#define PCLK_VIO_GRF			367
+#define PCLK_MIPI_DSI0			368
+#define PCLK_MIPI_DSI1			369
+#define PCLK_HDCP			370
+#define PCLK_HDCP_NOC			371
+#define PCLK_HDMI_CTRL			372
+#define PCLK_DP_CTRL			373
+#define PCLK_HDCP22			374
+#define PCLK_GASKET			375
+#define PCLK_DDR			376
+#define PCLK_DDR_MON			377
+#define PCLK_DDR_SGRF			378
+#define PCLK_ISP1_WRAPPER		379
+#define PCLK_WDT			380
+#define PCLK_EFUSE1024NS		381
+#define PCLK_EFUSE1024S			382
+#define PCLK_PMU_INTR_ARB		383
+#define PCLK_MAILBOX0			384
+#define PCLK_USBPHY_MUX_G		385
+#define PCLK_UPHY0_TCPHY_G		386
+#define PCLK_UPHY0_TCPD_G		387
+#define PCLK_UPHY1_TCPHY_G		388
+#define PCLK_UPHY1_TCPD_G		389
+#define PCLK_ALIVE			390
+
+/* hclk gates */
+#define HCLK_PERIHP			448
+#define HCLK_PERILP0			449
+#define HCLK_PERILP1			450
+#define HCLK_PERILP0_NOC		451
+#define HCLK_PERILP1_NOC		452
+#define HCLK_M0_PERILP			453
+#define HCLK_M0_PERILP_NOC		454
+#define HCLK_AHB1TOM			455
+#define HCLK_HOST0			456
+#define HCLK_HOST0_ARB			457
+#define HCLK_HOST1			458
+#define HCLK_HOST1_ARB			459
+#define HCLK_HSIC			460
+#define HCLK_SD				461
+#define HCLK_SDMMC			462
+#define HCLK_SDMMC_NOC			463
+#define HCLK_M_CRYPTO0			464
+#define HCLK_M_CRYPTO1			465
+#define HCLK_S_CRYPTO0			466
+#define HCLK_S_CRYPTO1			467
+#define HCLK_I2S0_8CH			468
+#define HCLK_I2S1_8CH			469
+#define HCLK_I2S2_8CH			470
+#define HCLK_SPDIF			471
+#define HCLK_VOP0_NOC			472
+#define HCLK_VOP0			473
+#define HCLK_VOP1_NOC			474
+#define HCLK_VOP1			475
+#define HCLK_ROM			476
+#define HCLK_IEP			477
+#define HCLK_IEP_NOC			478
+#define HCLK_ISP0			479
+#define HCLK_ISP1			480
+#define HCLK_ISP0_NOC			481
+#define HCLK_ISP1_NOC			482
+#define HCLK_ISP0_WRAPPER		483
+#define HCLK_ISP1_WRAPPER		484
+#define HCLK_RGA			485
+#define HCLK_RGA_NOC			486
+#define HCLK_HDCP			487
+#define HCLK_HDCP_NOC			488
+#define HCLK_HDCP22			489
+#define HCLK_VCODEC			490
+#define HCLK_VCODEC_NOC			491
+#define HCLK_VDU			492
+#define HCLK_VDU_NOC			493
+#define HCLK_SDIO			494
+#define HCLK_SDIO_NOC			495
+#define HCLK_SDIOAUDIO_NOC		496
+
+#define CLK_NR_CLKS			(HCLK_SDIOAUDIO_NOC + 1)
+
+/* pmu-clocks indices */
+
+#define PLL_PPLL			1
+
+#define SCLK_32K_SUSPEND_PMU		2
+#define SCLK_SPI3_PMU			3
+#define SCLK_TIMER12_PMU		4
+#define SCLK_TIMER13_PMU		5
+#define SCLK_UART4_PMU			6
+#define SCLK_PVTM_PMU			7
+#define SCLK_WIFI_PMU			8
+#define SCLK_I2C0_PMU			9
+#define SCLK_I2C4_PMU			10
+#define SCLK_I2C8_PMU			11
+
+#define PCLK_SRC_PMU			19
+#define PCLK_PMU			20
+#define PCLK_PMUGRF_PMU			21
+#define PCLK_INTMEM1_PMU		22
+#define PCLK_GPIO0_PMU			23
+#define PCLK_GPIO1_PMU			24
+#define PCLK_SGRF_PMU			25
+#define PCLK_NOC_PMU			26
+#define PCLK_I2C0_PMU			27
+#define PCLK_I2C4_PMU			28
+#define PCLK_I2C8_PMU			29
+#define PCLK_RKPWM_PMU			30
+#define PCLK_SPI3_PMU			31
+#define PCLK_TIMER_PMU			32
+#define PCLK_MAILBOX_PMU		33
+#define PCLK_UART4_PMU			34
+#define PCLK_WDT_M0_PMU			35
+
+#define FCLK_CM0S_SRC_PMU		44
+#define FCLK_CM0S_PMU			45
+#define SCLK_CM0S_PMU			46
+#define HCLK_CM0S_PMU			47
+#define DCLK_CM0S_PMU			48
+#define PCLK_INTR_ARB_PMU		49
+#define HCLK_NOC_PMU			50
+
+#define CLKPMU_NR_CLKS			(HCLK_NOC_PMU + 1)
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_CORE_L0			0
+#define SRST_CORE_B0			1
+#define SRST_CORE_PO_L0			2
+#define SRST_CORE_PO_B0			3
+#define SRST_L2_L			4
+#define SRST_L2_B			5
+#define SRST_ADB_L			6
+#define SRST_ADB_B			7
+#define SRST_A_CCI			8
+#define SRST_A_CCIM0_NOC		9
+#define SRST_A_CCIM1_NOC		10
+#define SRST_DBG_NOC			11
+
+/* cru_softrst_con1 */
+#define SRST_CORE_L0_T			16
+#define SRST_CORE_L1			17
+#define SRST_CORE_L2			18
+#define SRST_CORE_L3			19
+#define SRST_CORE_PO_L0_T		20
+#define SRST_CORE_PO_L1			21
+#define SRST_CORE_PO_L2			22
+#define SRST_CORE_PO_L3			23
+#define SRST_A_ADB400_GIC2COREL		24
+#define SRST_A_ADB400_COREL2GIC		25
+#define SRST_P_DBG_L			26
+#define SRST_L2_L_T			28
+#define SRST_ADB_L_T			29
+#define SRST_A_RKPERF_L			30
+#define SRST_PVTM_CORE_L		31
+
+/* cru_softrst_con2 */
+#define SRST_CORE_B0_T			32
+#define SRST_CORE_B1			33
+#define SRST_CORE_PO_B0_T		36
+#define SRST_CORE_PO_B1			37
+#define SRST_A_ADB400_GIC2COREB		40
+#define SRST_A_ADB400_COREB2GIC		41
+#define SRST_P_DBG_B			42
+#define SRST_L2_B_T			43
+#define SRST_ADB_B_T			45
+#define SRST_A_RKPERF_B			46
+#define SRST_PVTM_CORE_B		47
+
+/* cru_softrst_con3 */
+#define SRST_A_CCI_T			50
+#define SRST_A_CCIM0_NOC_T		51
+#define SRST_A_CCIM1_NOC_T		52
+#define SRST_A_ADB400M_PD_CORE_B_T	53
+#define SRST_A_ADB400M_PD_CORE_L_T	54
+#define SRST_DBG_NOC_T			55
+#define SRST_DBG_CXCS			56
+#define SRST_CCI_TRACE			57
+#define SRST_P_CCI_GRF			58
+
+/* cru_softrst_con4 */
+#define SRST_A_CENTER_MAIN_NOC		64
+#define SRST_A_CENTER_PERI_NOC		65
+#define SRST_P_CENTER_MAIN		66
+#define SRST_P_DDRMON			67
+#define SRST_P_CIC			68
+#define SRST_P_CENTER_SGRF		69
+#define SRST_DDR0_MSCH			70
+#define SRST_DDRCFG0_MSCH		71
+#define SRST_DDR0			72
+#define SRST_DDRPHY0			73
+#define SRST_DDR1_MSCH			74
+#define SRST_DDRCFG1_MSCH		75
+#define SRST_DDR1			76
+#define SRST_DDRPHY1			77
+#define SRST_DDR_CIC			78
+#define SRST_PVTM_DDR			79
+
+/* cru_softrst_con5 */
+#define SRST_A_VCODEC_NOC		80
+#define SRST_A_VCODEC			81
+#define SRST_H_VCODEC_NOC		82
+#define SRST_H_VCODEC			83
+#define SRST_A_VDU_NOC			88
+#define SRST_A_VDU			89
+#define SRST_H_VDU_NOC			90
+#define SRST_H_VDU			91
+#define SRST_VDU_CORE			92
+#define SRST_VDU_CA			93
+
+/* cru_softrst_con6 */
+#define SRST_A_IEP_NOC			96
+#define SRST_A_VOP_IEP			97
+#define SRST_A_IEP			98
+#define SRST_H_IEP_NOC			99
+#define SRST_H_IEP			100
+#define SRST_A_RGA_NOC			102
+#define SRST_A_RGA			103
+#define SRST_H_RGA_NOC			104
+#define SRST_H_RGA			105
+#define SRST_RGA_CORE			106
+#define SRST_EMMC_NOC			108
+#define SRST_EMMC			109
+#define SRST_EMMC_GRF			110
+
+/* cru_softrst_con7 */
+#define SRST_A_PERIHP_NOC		112
+#define SRST_P_PERIHP_GRF		113
+#define SRST_H_PERIHP_NOC		114
+#define SRST_USBHOST0			115
+#define SRST_HOSTC0_AUX			116
+#define SRST_HOST0_ARB			117
+#define SRST_USBHOST1			118
+#define SRST_HOSTC1_AUX			119
+#define SRST_HOST1_ARB			120
+#define SRST_SDIO0			121
+#define SRST_SDMMC			122
+#define SRST_HSIC			123
+#define SRST_HSIC_AUX			124
+#define SRST_AHB1TOM			125
+#define SRST_P_PERIHP_NOC		126
+#define SRST_HSICPHY			127
+
+/* cru_softrst_con8 */
+#define SRST_A_PCIE			128
+#define SRST_P_PCIE			129
+#define SRST_PCIE_CORE			130
+#define SRST_PCIE_MGMT			131
+#define SRST_PCIE_MGMT_STICKY		132
+#define SRST_PCIE_PIPE			133
+#define SRST_PCIE_PM			134
+#define SRST_PCIEPHY			135
+#define SRST_A_GMAC_NOC			136
+#define SRST_A_GMAC			137
+#define SRST_P_GMAC_NOC			138
+#define SRST_P_GMAC_GRF			140
+#define SRST_HSICPHY_POR		142
+#define SRST_HSICPHY_UTMI		143
+
+/* cru_softrst_con9 */
+#define SRST_USB2PHY0_POR		144
+#define SRST_USB2PHY0_UTMI_PORT0	145
+#define SRST_USB2PHY0_UTMI_PORT1	146
+#define SRST_USB2PHY0_EHCIPHY		147
+#define SRST_UPHY0_PIPE_L00		148
+#define SRST_UPHY0			149
+#define SRST_UPHY0_TCPDPWRUP		150
+#define SRST_USB2PHY1_POR		152
+#define SRST_USB2PHY1_UTMI_PORT0	153
+#define SRST_USB2PHY1_UTMI_PORT1	154
+#define SRST_USB2PHY1_EHCIPHY		155
+#define SRST_UPHY1_PIPE_L00		156
+#define SRST_UPHY1			157
+#define SRST_UPHY1_TCPDPWRUP		158
+
+/* cru_softrst_con10 */
+#define SRST_A_PERILP0_NOC		160
+#define SRST_A_DCF			161
+#define SRST_GIC500			162
+#define SRST_DMAC0_PERILP0		163
+#define SRST_DMAC1_PERILP0		164
+#define SRST_TZMA			165
+#define SRST_INTMEM			166
+#define SRST_ADB400_MST0		167
+#define SRST_ADB400_MST1		168
+#define SRST_ADB400_SLV0		169
+#define SRST_ADB400_SLV1		170
+#define SRST_H_PERILP0			171
+#define SRST_H_PERILP0_NOC		172
+#define SRST_ROM			173
+#define SRST_CRYPTO_S			174
+#define SRST_CRYPTO_M			175
+
+/* cru_softrst_con11 */
+#define SRST_P_DCF			176
+#define SRST_CM0S_NOC			177
+#define SRST_CM0S			178
+#define SRST_CM0S_DBG			179
+#define SRST_CM0S_PO			180
+#define SRST_CRYPTO			181
+#define SRST_P_PERILP1_SGRF		182
+#define SRST_P_PERILP1_GRF		183
+#define SRST_CRYPTO1_S			184
+#define SRST_CRYPTO1_M			185
+#define SRST_CRYPTO1			186
+#define SRST_GIC_NOC			188
+#define SRST_SD_NOC			189
+#define SRST_SDIOAUDIO_BRG		190
+
+/* cru_softrst_con12 */
+#define SRST_H_PERILP1			192
+#define SRST_H_PERILP1_NOC		193
+#define SRST_H_I2S0_8CH			194
+#define SRST_H_I2S1_8CH			195
+#define SRST_H_I2S2_8CH			196
+#define SRST_H_SPDIF_8CH		197
+#define SRST_P_PERILP1_NOC		198
+#define SRST_P_EFUSE_1024		199
+#define SRST_P_EFUSE_1024S		200
+#define SRST_P_I2C0			201
+#define SRST_P_I2C1			202
+#define SRST_P_I2C2			203
+#define SRST_P_I2C3			204
+#define SRST_P_I2C4			205
+#define SRST_P_I2C5			206
+#define SRST_P_MAILBOX0			207
+
+/* cru_softrst_con13 */
+#define SRST_P_UART0			208
+#define SRST_P_UART1			209
+#define SRST_P_UART2			210
+#define SRST_P_UART3			211
+#define SRST_P_SARADC			212
+#define SRST_P_TSADC			213
+#define SRST_P_SPI0			214
+#define SRST_P_SPI1			215
+#define SRST_P_SPI2			216
+#define SRST_P_SPI3			217
+#define SRST_P_SPI4			218
+#define SRST_SPI0			219
+#define SRST_SPI1			220
+#define SRST_SPI2			221
+#define SRST_SPI3			222
+#define SRST_SPI4			223
+
+/* cru_softrst_con14 */
+#define SRST_I2S0_8CH			224
+#define SRST_I2S1_8CH			225
+#define SRST_I2S2_8CH			226
+#define SRST_SPDIF_8CH			227
+#define SRST_UART0			228
+#define SRST_UART1			229
+#define SRST_UART2			230
+#define SRST_UART3			231
+#define SRST_TSADC			232
+#define SRST_I2C0			233
+#define SRST_I2C1			234
+#define SRST_I2C2			235
+#define SRST_I2C3			236
+#define SRST_I2C4			237
+#define SRST_I2C5			238
+#define SRST_SDIOAUDIO_NOC		239
+
+/* cru_softrst_con15 */
+#define SRST_A_VIO_NOC			240
+#define SRST_A_HDCP_NOC			241
+#define SRST_A_HDCP			242
+#define SRST_H_HDCP_NOC			243
+#define SRST_H_HDCP			244
+#define SRST_P_HDCP_NOC			245
+#define SRST_P_HDCP			246
+#define SRST_P_HDMI_CTRL		247
+#define SRST_P_DP_CTRL			248
+#define SRST_S_DP_CTRL			249
+#define SRST_C_DP_CTRL			250
+#define SRST_P_MIPI_DSI0		251
+#define SRST_P_MIPI_DSI1		252
+#define SRST_DP_CORE			253
+#define SRST_DP_I2S			254
+
+/* cru_softrst_con16 */
+#define SRST_GASKET			256
+#define SRST_VIO_GRF			258
+#define SRST_DPTX_SPDIF_REC		259
+#define SRST_HDMI_CTRL			260
+#define SRST_HDCP_CTRL			261
+#define SRST_A_ISP0_NOC			262
+#define SRST_A_ISP1_NOC			263
+#define SRST_H_ISP0_NOC			266
+#define SRST_H_ISP1_NOC			267
+#define SRST_H_ISP0			268
+#define SRST_H_ISP1			269
+#define SRST_ISP0			270
+#define SRST_ISP1			271
+
+/* cru_softrst_con17 */
+#define SRST_A_VOP0_NOC			272
+#define SRST_A_VOP1_NOC			273
+#define SRST_A_VOP0			274
+#define SRST_A_VOP1			275
+#define SRST_H_VOP0_NOC			276
+#define SRST_H_VOP1_NOC			277
+#define SRST_H_VOP0			278
+#define SRST_H_VOP1			279
+#define SRST_D_VOP0			280
+#define SRST_D_VOP1			281
+#define SRST_VOP0_PWM			282
+#define SRST_VOP1_PWM			283
+#define SRST_P_EDP_NOC			284
+#define SRST_P_EDP_CTRL			285
+
+/* cru_softrst_con18 */
+#define SRST_A_GPU			288
+#define SRST_A_GPU_NOC			289
+#define SRST_A_GPU_GRF			290
+#define SRST_PVTM_GPU			291
+#define SRST_A_USB3_NOC			292
+#define SRST_A_USB3_OTG0		293
+#define SRST_A_USB3_OTG1		294
+#define SRST_A_USB3_GRF			295
+#define SRST_PMU			296
+
+/* cru_softrst_con19 */
+#define SRST_P_TIMER0_5			304
+#define SRST_TIMER0			305
+#define SRST_TIMER1			306
+#define SRST_TIMER2			307
+#define SRST_TIMER3			308
+#define SRST_TIMER4			309
+#define SRST_TIMER5			310
+#define SRST_P_TIMER6_11		311
+#define SRST_TIMER6			312
+#define SRST_TIMER7			313
+#define SRST_TIMER8			314
+#define SRST_TIMER9			315
+#define SRST_TIMER10			316
+#define SRST_TIMER11			317
+#define SRST_P_INTR_ARB_PMU		318
+#define SRST_P_ALIVE_SGRF		319
+
+/* cru_softrst_con20 */
+#define SRST_P_GPIO2			320
+#define SRST_P_GPIO3			321
+#define SRST_P_GPIO4			322
+#define SRST_P_GRF			323
+#define SRST_P_ALIVE_NOC		324
+#define SRST_P_WDT0			325
+#define SRST_P_WDT1			326
+#define SRST_P_INTR_ARB			327
+#define SRST_P_UPHY0_DPTX		328
+#define SRST_P_UPHY0_APB		330
+#define SRST_P_UPHY0_TCPHY		332
+#define SRST_P_UPHY1_TCPHY		333
+#define SRST_P_UPHY0_TCPDCTRL		334
+#define SRST_P_UPHY1_TCPDCTRL		335
+
+/* pmu soft-reset indices */
+
+/* pmu_cru_softrst_con0 */
+#define SRST_P_NOC			0
+#define SRST_P_INTMEM			1
+#define SRST_H_CM0S			2
+#define SRST_H_CM0S_NOC			3
+#define SRST_DBG_CM0S			4
+#define SRST_PO_CM0S			5
+#define SRST_P_SPI6			6
+#define SRST_SPI6			7
+#define SRST_P_TIMER_0_1		8
+#define SRST_P_TIMER_0			9
+#define SRST_P_TIMER_1			10
+#define SRST_P_UART4			11
+#define SRST_UART4			12
+#define SRST_P_WDT			13
+
+/* pmu_cru_softrst_con1 */
+#define SRST_P_I2C6			16
+#define SRST_P_I2C7			17
+#define SRST_P_I2C8			18
+#define SRST_P_MAILBOX			19
+#define SRST_P_RKPWM			20
+#define SRST_P_PMUGRF			21
+#define SRST_P_SGRF			22
+#define SRST_P_GPIO0			23
+#define SRST_P_GPIO1			24
+#define SRST_P_CRU			25
+#define SRST_P_INTR			26
+#define SRST_PVTM			27
+#define SRST_I2C6			28
+#define SRST_I2C7			29
+#define SRST_I2C8			30
+
+#endif
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 6f45aea49e4f..bd3530e56d46 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -126,7 +126,7 @@
 /* 104 */
 /* 105 */
 #define TEGRA210_CLK_D_AUDIO 106
-/* 107 ( affects abp -> ape) */
+#define TEGRA210_CLK_APB2APE 107
 /* 108 */
 /* 109 */
 /* 110 */
@@ -346,7 +346,7 @@
 #define TEGRA210_CLK_PLL_P_OUT_HSIO 316
 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317
 #define TEGRA210_CLK_XUSB_SSP_SRC 318
-/* 319 */
+#define TEGRA210_CLK_PLL_RE_OUT1 319
 /* 320 */
 /* 321 */
 /* 322 */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 56c16aaea112..45997750c8a0 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -194,7 +194,11 @@
 #define VF610_PLL7_BYPASS		181
 #define VF610_CLK_SNVS			182
 #define VF610_CLK_DAP			183
-#define VF610_CLK_OCOTP         184
-#define VF610_CLK_END			185
+#define VF610_CLK_OCOTP			184
+#define VF610_CLK_DDRMC			185
+#define VF610_CLK_WKPU			186
+#define VF610_CLK_TCON0			187
+#define VF610_CLK_TCON1			188
+#define VF610_CLK_END			189
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h
new file mode 100644
index 000000000000..58654fd7aa1e
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-gxbb-gpio.h
@@ -0,0 +1,154 @@
+/*
+ * GPIO definitions for Amlogic Meson GXBB SoCs
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
+#define _DT_BINDINGS_MESON_GXBB_GPIO_H
+
+#define	GPIOAO_0	0
+#define	GPIOAO_1	1
+#define	GPIOAO_2	2
+#define	GPIOAO_3	3
+#define	GPIOAO_4	4
+#define	GPIOAO_5	5
+#define	GPIOAO_6	6
+#define	GPIOAO_7	7
+#define	GPIOAO_8	8
+#define	GPIOAO_9	9
+#define	GPIOAO_10	10
+#define	GPIOAO_11	11
+#define	GPIOAO_12	12
+#define	GPIOAO_13	13
+
+#define	GPIOZ_0		0
+#define	GPIOZ_1		1
+#define	GPIOZ_2		2
+#define	GPIOZ_3		3
+#define	GPIOZ_4		4
+#define	GPIOZ_5		5
+#define	GPIOZ_6		6
+#define	GPIOZ_7		7
+#define	GPIOZ_8		8
+#define	GPIOZ_9		9
+#define	GPIOZ_10	10
+#define	GPIOZ_11	11
+#define	GPIOZ_12	12
+#define	GPIOZ_13	13
+#define	GPIOZ_14	14
+#define	GPIOZ_15	15
+#define	GPIOH_0		16
+#define	GPIOH_1		17
+#define	GPIOH_2		18
+#define	GPIOH_3		19
+#define	BOOT_0		20
+#define	BOOT_1		21
+#define	BOOT_2		22
+#define	BOOT_3		23
+#define	BOOT_4		24
+#define	BOOT_5		25
+#define	BOOT_6		26
+#define	BOOT_7		27
+#define	BOOT_8		28
+#define	BOOT_9		29
+#define	BOOT_10		30
+#define	BOOT_11		31
+#define	BOOT_12		32
+#define	BOOT_13		33
+#define	BOOT_14		34
+#define	BOOT_15		35
+#define	BOOT_16		36
+#define	BOOT_17		37
+#define	CARD_0		38
+#define	CARD_1		39
+#define	CARD_2		40
+#define	CARD_3		41
+#define	CARD_4		42
+#define	CARD_5		43
+#define	CARD_6		44
+#define	GPIODV_0	45
+#define	GPIODV_1	46
+#define	GPIODV_2	47
+#define	GPIODV_3	48
+#define	GPIODV_4	49
+#define	GPIODV_5	50
+#define	GPIODV_6	51
+#define	GPIODV_7	52
+#define	GPIODV_8	53
+#define	GPIODV_9	54
+#define	GPIODV_10	55
+#define	GPIODV_11	56
+#define	GPIODV_12	57
+#define	GPIODV_13	58
+#define	GPIODV_14	59
+#define	GPIODV_15	60
+#define	GPIODV_16	61
+#define	GPIODV_17	62
+#define	GPIODV_18	63
+#define	GPIODV_19	64
+#define	GPIODV_20	65
+#define	GPIODV_21	66
+#define	GPIODV_22	67
+#define	GPIODV_23	68
+#define	GPIODV_24	69
+#define	GPIODV_25	70
+#define	GPIODV_26	71
+#define	GPIODV_27	72
+#define	GPIODV_28	73
+#define	GPIODV_29	74
+#define	GPIOY_0		75
+#define	GPIOY_1		76
+#define	GPIOY_2		77
+#define	GPIOY_3		78
+#define	GPIOY_4		79
+#define	GPIOY_5		80
+#define	GPIOY_6		81
+#define	GPIOY_7		82
+#define	GPIOY_8		83
+#define	GPIOY_9		84
+#define	GPIOY_10	85
+#define	GPIOY_11	86
+#define	GPIOY_12	87
+#define	GPIOY_13	88
+#define	GPIOY_14	89
+#define	GPIOY_15	90
+#define	GPIOY_16	91
+#define	GPIOX_0		92
+#define	GPIOX_1		93
+#define	GPIOX_2		94
+#define	GPIOX_3		95
+#define	GPIOX_4		96
+#define	GPIOX_5		97
+#define	GPIOX_6		98
+#define	GPIOX_7		99
+#define	GPIOX_8		100
+#define	GPIOX_9		101
+#define	GPIOX_10	102
+#define	GPIOX_11	103
+#define	GPIOX_12	104
+#define	GPIOX_13	105
+#define	GPIOX_14	106
+#define	GPIOX_15	107
+#define	GPIOX_16	108
+#define	GPIOX_17	109
+#define	GPIOX_18	110
+#define	GPIOX_19	111
+#define	GPIOX_20	112
+#define	GPIOX_21	113
+#define	GPIOX_22	114
+#define	GPIOCLK_0	115
+#define	GPIOCLK_1	116
+#define	GPIOCLK_2	117
+#define	GPIOCLK_3	118
+#define	GPIO_TEST_N	119
+
+#endif
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 197dc28b676e..a1c09e88e80b 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -12,40 +12,40 @@
 
 #include <dt-bindings/gpio/gpio.h>
 
-#define TEGRA_GPIO_BANK_ID_A 0
-#define TEGRA_GPIO_BANK_ID_B 1
-#define TEGRA_GPIO_BANK_ID_C 2
-#define TEGRA_GPIO_BANK_ID_D 3
-#define TEGRA_GPIO_BANK_ID_E 4
-#define TEGRA_GPIO_BANK_ID_F 5
-#define TEGRA_GPIO_BANK_ID_G 6
-#define TEGRA_GPIO_BANK_ID_H 7
-#define TEGRA_GPIO_BANK_ID_I 8
-#define TEGRA_GPIO_BANK_ID_J 9
-#define TEGRA_GPIO_BANK_ID_K 10
-#define TEGRA_GPIO_BANK_ID_L 11
-#define TEGRA_GPIO_BANK_ID_M 12
-#define TEGRA_GPIO_BANK_ID_N 13
-#define TEGRA_GPIO_BANK_ID_O 14
-#define TEGRA_GPIO_BANK_ID_P 15
-#define TEGRA_GPIO_BANK_ID_Q 16
-#define TEGRA_GPIO_BANK_ID_R 17
-#define TEGRA_GPIO_BANK_ID_S 18
-#define TEGRA_GPIO_BANK_ID_T 19
-#define TEGRA_GPIO_BANK_ID_U 20
-#define TEGRA_GPIO_BANK_ID_V 21
-#define TEGRA_GPIO_BANK_ID_W 22
-#define TEGRA_GPIO_BANK_ID_X 23
-#define TEGRA_GPIO_BANK_ID_Y 24
-#define TEGRA_GPIO_BANK_ID_Z 25
-#define TEGRA_GPIO_BANK_ID_AA 26
-#define TEGRA_GPIO_BANK_ID_BB 27
-#define TEGRA_GPIO_BANK_ID_CC 28
-#define TEGRA_GPIO_BANK_ID_DD 29
-#define TEGRA_GPIO_BANK_ID_EE 30
-#define TEGRA_GPIO_BANK_ID_FF 31
+#define TEGRA_GPIO_PORT_A 0
+#define TEGRA_GPIO_PORT_B 1
+#define TEGRA_GPIO_PORT_C 2
+#define TEGRA_GPIO_PORT_D 3
+#define TEGRA_GPIO_PORT_E 4
+#define TEGRA_GPIO_PORT_F 5
+#define TEGRA_GPIO_PORT_G 6
+#define TEGRA_GPIO_PORT_H 7
+#define TEGRA_GPIO_PORT_I 8
+#define TEGRA_GPIO_PORT_J 9
+#define TEGRA_GPIO_PORT_K 10
+#define TEGRA_GPIO_PORT_L 11
+#define TEGRA_GPIO_PORT_M 12
+#define TEGRA_GPIO_PORT_N 13
+#define TEGRA_GPIO_PORT_O 14
+#define TEGRA_GPIO_PORT_P 15
+#define TEGRA_GPIO_PORT_Q 16
+#define TEGRA_GPIO_PORT_R 17
+#define TEGRA_GPIO_PORT_S 18
+#define TEGRA_GPIO_PORT_T 19
+#define TEGRA_GPIO_PORT_U 20
+#define TEGRA_GPIO_PORT_V 21
+#define TEGRA_GPIO_PORT_W 22
+#define TEGRA_GPIO_PORT_X 23
+#define TEGRA_GPIO_PORT_Y 24
+#define TEGRA_GPIO_PORT_Z 25
+#define TEGRA_GPIO_PORT_AA 26
+#define TEGRA_GPIO_PORT_BB 27
+#define TEGRA_GPIO_PORT_CC 28
+#define TEGRA_GPIO_PORT_DD 29
+#define TEGRA_GPIO_PORT_EE 30
+#define TEGRA_GPIO_PORT_FF 31
 
-#define TEGRA_GPIO(bank, offset) \
-	((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+#define TEGRA_GPIO(port, offset) \
+	((TEGRA_GPIO_PORT_##port * 8) + offset)
 
 #endif
diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h
new file mode 100644
index 000000000000..38001c7023f1
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra186-gpio.h
@@ -0,0 +1,56 @@
+/*
+ * This header provides constants for binding nvidia,tegra186-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_MAIN_GPIO_PORT_A 0
+#define TEGRA_MAIN_GPIO_PORT_B 1
+#define TEGRA_MAIN_GPIO_PORT_C 2
+#define TEGRA_MAIN_GPIO_PORT_D 3
+#define TEGRA_MAIN_GPIO_PORT_E 4
+#define TEGRA_MAIN_GPIO_PORT_F 5
+#define TEGRA_MAIN_GPIO_PORT_G 6
+#define TEGRA_MAIN_GPIO_PORT_H 7
+#define TEGRA_MAIN_GPIO_PORT_I 8
+#define TEGRA_MAIN_GPIO_PORT_J 9
+#define TEGRA_MAIN_GPIO_PORT_K 10
+#define TEGRA_MAIN_GPIO_PORT_L 11
+#define TEGRA_MAIN_GPIO_PORT_M 12
+#define TEGRA_MAIN_GPIO_PORT_N 13
+#define TEGRA_MAIN_GPIO_PORT_O 14
+#define TEGRA_MAIN_GPIO_PORT_P 15
+#define TEGRA_MAIN_GPIO_PORT_Q 16
+#define TEGRA_MAIN_GPIO_PORT_R 17
+#define TEGRA_MAIN_GPIO_PORT_T 18
+#define TEGRA_MAIN_GPIO_PORT_X 19
+#define TEGRA_MAIN_GPIO_PORT_Y 20
+#define TEGRA_MAIN_GPIO_PORT_BB 21
+#define TEGRA_MAIN_GPIO_PORT_CC 22
+
+#define TEGRA_MAIN_GPIO(port, offset) \
+	((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_AON_GPIO_PORT_S 0
+#define TEGRA_AON_GPIO_PORT_U 1
+#define TEGRA_AON_GPIO_PORT_V 2
+#define TEGRA_AON_GPIO_PORT_W 3
+#define TEGRA_AON_GPIO_PORT_Z 4
+#define TEGRA_AON_GPIO_PORT_AA 5
+#define TEGRA_AON_GPIO_PORT_EE 6
+#define TEGRA_AON_GPIO_PORT_FF 7
+
+#define TEGRA_AON_GPIO(port, offset) \
+	((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
diff --git a/include/dt-bindings/iio/adc/fsl-imx25-gcq.h b/include/dt-bindings/iio/adc/fsl-imx25-gcq.h
new file mode 100644
index 000000000000..87abdd4a7674
--- /dev/null
+++ b/include/dt-bindings/iio/adc/fsl-imx25-gcq.h
@@ -0,0 +1,18 @@
+/*
+ * This header provides constants for configuring the I.MX25 ADC
+ */
+
+#ifndef _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H
+#define _DT_BINDINGS_IIO_ADC_FS_IMX25_GCQ_H
+
+#define MX25_ADC_REFP_YP	0 /* YP voltage reference */
+#define MX25_ADC_REFP_XP	1 /* XP voltage reference */
+#define MX25_ADC_REFP_EXT	2 /* External voltage reference */
+#define MX25_ADC_REFP_INT	3 /* Internal voltage reference */
+
+#define MX25_ADC_REFN_XN	0 /* XN ground reference */
+#define MX25_ADC_REFN_YN	1 /* YN ground reference */
+#define MX25_ADC_REFN_NGND	2 /* Internal ground reference */
+#define MX25_ADC_REFN_NGND2	3 /* External ground reference */
+
+#endif
diff --git a/include/dt-bindings/iio/adi,ad5592r.h b/include/dt-bindings/iio/adi,ad5592r.h
new file mode 100644
index 000000000000..c48aca1dcade
--- /dev/null
+++ b/include/dt-bindings/iio/adi,ad5592r.h
@@ -0,0 +1,16 @@
+
+#ifndef _DT_BINDINGS_ADI_AD5592R_H
+#define _DT_BINDINGS_ADI_AD5592R_H
+
+#define CH_MODE_UNUSED			0
+#define CH_MODE_ADC			1
+#define CH_MODE_DAC			2
+#define CH_MODE_DAC_AND_ADC		3
+#define CH_MODE_GPIO			8
+
+#define CH_OFFSTATE_PULLDOWN		0
+#define CH_OFFSTATE_OUT_LOW		1
+#define CH_OFFSTATE_OUT_HIGH		2
+#define CH_OFFSTATE_OUT_TRISTATE	3
+
+#endif /* _DT_BINDINGS_ADI_AD5592R_H */
diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
index 87cf351bab03..d6d071fc3c56 100644
--- a/include/dt-bindings/input/linux-event-codes.h
+++ b/include/dt-bindings/input/linux-event-codes.h
@@ -611,6 +611,37 @@
 #define KEY_KBDINPUTASSIST_ACCEPT		0x264
 #define KEY_KBDINPUTASSIST_CANCEL		0x265
 
+/* Diagonal movement keys */
+#define KEY_RIGHT_UP			0x266
+#define KEY_RIGHT_DOWN			0x267
+#define KEY_LEFT_UP			0x268
+#define KEY_LEFT_DOWN			0x269
+
+#define KEY_ROOT_MENU			0x26a /* Show Device's Root Menu */
+/* Show Top Menu of the Media (e.g. DVD) */
+#define KEY_MEDIA_TOP_MENU		0x26b
+#define KEY_NUMERIC_11			0x26c
+#define KEY_NUMERIC_12			0x26d
+/*
+ * Toggle Audio Description: refers to an audio service that helps blind and
+ * visually impaired consumers understand the action in a program. Note: in
+ * some countries this is referred to as "Video Description".
+ */
+#define KEY_AUDIO_DESC			0x26e
+#define KEY_3D_MODE			0x26f
+#define KEY_NEXT_FAVORITE		0x270
+#define KEY_STOP_RECORD			0x271
+#define KEY_PAUSE_RECORD		0x272
+#define KEY_VOD				0x273 /* Video on Demand */
+#define KEY_UNMUTE			0x274
+#define KEY_FASTREVERSE			0x275
+#define KEY_SLOWREVERSE			0x276
+/*
+ * Control a data application associated with the currently viewed channel,
+ * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
+ */
+#define KEY_DATA			0x275
+
 #define BTN_TRIGGER_HAPPY		0x2c0
 #define BTN_TRIGGER_HAPPY1		0x2c0
 #define BTN_TRIGGER_HAPPY2		0x2c1
@@ -749,6 +780,7 @@
 #define SW_ROTATE_LOCK		0x0c  /* set = rotate locked/disabled */
 #define SW_LINEIN_INSERT	0x0d  /* set = inserted */
 #define SW_MUTE_DEVICE		0x0e  /* set = device disabled */
+#define SW_PEN_INSERTED		0x0f  /* set = pen inserted */
 #define SW_MAX			0x0f
 #define SW_CNT			(SW_MAX+1)
 
diff --git a/include/dt-bindings/media/tvp5150.h b/include/dt-bindings/media/tvp5150.h
new file mode 100644
index 000000000000..c852a35e916e
--- /dev/null
+++ b/include/dt-bindings/media/tvp5150.h
@@ -0,0 +1,35 @@
+/*
+    tvp5150.h - definition for tvp5150 inputs
+
+    Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef _DT_BINDINGS_MEDIA_TVP5150_H
+#define _DT_BINDINGS_MEDIA_TVP5150_H
+
+/* TVP5150 HW inputs */
+#define TVP5150_COMPOSITE0 0
+#define TVP5150_COMPOSITE1 1
+#define TVP5150_SVIDEO     2
+
+#define TVP5150_INPUT_NUM  3
+
+/* TVP5150 HW outputs */
+#define TVP5150_NORMAL       0
+#define TVP5150_BLACK_SCREEN 1
+
+#endif /* _DT_BINDINGS_MEDIA_TVP5150_H */
diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h
new file mode 100644
index 000000000000..5fef5d1f8f82
--- /dev/null
+++ b/include/dt-bindings/memory/mt8173-larb-port.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DTS_IOMMU_PORT_MT8173_H
+#define __DTS_IOMMU_PORT_MT8173_H
+
+#define MTK_M4U_ID(larb, port)		(((larb) << 5) | (port))
+/* Local arbiter ID */
+#define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x7)
+/* PortID within the local arbiter */
+#define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
+
+#define M4U_LARB0_ID			0
+#define M4U_LARB1_ID			1
+#define M4U_LARB2_ID			2
+#define M4U_LARB3_ID			3
+#define M4U_LARB4_ID			4
+#define M4U_LARB5_ID			5
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0		MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OD_R		MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_OD_W		MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WDMA		MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB0_ID, 7)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT		MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT		MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_UFO_EXT	MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_VLD2_EXT	MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_HW_VDEC_TILE		MTK_M4U_ID(M4U_LARB1_ID, 9)
+
+/* larb2 */
+#define M4U_PORT_IMGO			MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_RRZO			MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_AAO			MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_LCSO			MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_ESFKO			MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_IMGO_D			MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_LSCI			MTK_M4U_ID(M4U_LARB2_ID, 6)
+#define M4U_PORT_LSCI_D			MTK_M4U_ID(M4U_LARB2_ID, 7)
+#define M4U_PORT_BPCI			MTK_M4U_ID(M4U_LARB2_ID, 8)
+#define M4U_PORT_BPCI_D			MTK_M4U_ID(M4U_LARB2_ID, 9)
+#define M4U_PORT_UFDI			MTK_M4U_ID(M4U_LARB2_ID, 10)
+#define M4U_PORT_IMGI			MTK_M4U_ID(M4U_LARB2_ID, 11)
+#define M4U_PORT_IMG2O			MTK_M4U_ID(M4U_LARB2_ID, 12)
+#define M4U_PORT_IMG3O			MTK_M4U_ID(M4U_LARB2_ID, 13)
+#define M4U_PORT_VIPI			MTK_M4U_ID(M4U_LARB2_ID, 14)
+#define M4U_PORT_VIP2I			MTK_M4U_ID(M4U_LARB2_ID, 15)
+#define M4U_PORT_VIP3I			MTK_M4U_ID(M4U_LARB2_ID, 16)
+#define M4U_PORT_LCEI			MTK_M4U_ID(M4U_LARB2_ID, 17)
+#define M4U_PORT_RB			MTK_M4U_ID(M4U_LARB2_ID, 18)
+#define M4U_PORT_RP			MTK_M4U_ID(M4U_LARB2_ID, 19)
+#define M4U_PORT_WR			MTK_M4U_ID(M4U_LARB2_ID, 20)
+
+/* larb3 */
+#define M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_VENC_REC		MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_VENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_VENC_SV_COMV		MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_JPGENC_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_JPGENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_JPGDEC_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_JPGDEC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 8)
+#define M4U_PORT_VENC_CUR_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 9)
+#define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 10)
+#define M4U_PORT_VENC_REF_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 11)
+#define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 12)
+#define M4U_PORT_VENC_NBM_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 13)
+#define M4U_PORT_VENC_NBM_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 14)
+
+/* larb4 */
+#define M4U_PORT_DISP_OVL1		MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_DISP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_DISP_RDMA2		MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_DISP_WDMA1		MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_MDP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_MDP_WROT1		MTK_M4U_ID(M4U_LARB4_ID, 5)
+
+/* larb5 */
+#define M4U_PORT_VENC_RCPU_SET2		MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_VENC_REC_FRM_SET2	MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_VENC_REF_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_VENC_REC_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_VENC_BSDMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_VENC_CUR_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_VENC_CUR_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_VENC_RD_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_VENC_SV_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 8)
+
+#endif
diff --git a/include/dt-bindings/mfd/arizona.h b/include/dt-bindings/mfd/arizona.h
index c40f665e2712..dedf46ffdb53 100644
--- a/include/dt-bindings/mfd/arizona.h
+++ b/include/dt-bindings/mfd/arizona.h
@@ -110,4 +110,9 @@
 #define ARIZONA_ACCDET_MODE_HPM 4
 #define ARIZONA_ACCDET_MODE_ADC 7
 
+#define ARIZONA_GPSW_OPEN           0
+#define ARIZONA_GPSW_CLOSED         1
+#define ARIZONA_GPSW_CLAMP_ENABLED  2
+#define ARIZONA_GPSW_CLAMP_DISABLED 3
+
 #endif
diff --git a/include/dt-bindings/mfd/max77620.h b/include/dt-bindings/mfd/max77620.h
new file mode 100644
index 000000000000..b911a0720ccd
--- /dev/null
+++ b/include/dt-bindings/mfd/max77620.h
@@ -0,0 +1,39 @@
+/*
+ * This header provides macros for MAXIM MAX77620 device bindings.
+ *
+ * Copyright (c) 2016, NVIDIA Corporation.
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ */
+
+#ifndef _DT_BINDINGS_MFD_MAX77620_H
+#define _DT_BINDINGS_MFD_MAX77620_H
+
+/* MAX77620 interrupts */
+#define MAX77620_IRQ_TOP_GLBL		0 /* Low-Battery */
+#define MAX77620_IRQ_TOP_SD		1 /* SD power fail */
+#define MAX77620_IRQ_TOP_LDO		2 /* LDO power fail */
+#define MAX77620_IRQ_TOP_GPIO		3 /* GPIO internal int to MAX77620 */
+#define MAX77620_IRQ_TOP_RTC		4 /* RTC */
+#define MAX77620_IRQ_TOP_32K		5 /* 32kHz oscillator */
+#define MAX77620_IRQ_TOP_ONOFF		6 /* ON/OFF oscillator */
+#define MAX77620_IRQ_LBT_MBATLOW	7 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM1	8 /* Thermal alarm status, > 120C */
+#define MAX77620_IRQ_LBT_TJALRM2	9 /* Thermal alarm status, > 140C */
+
+/* FPS event source */
+#define MAX77620_FPS_EVENT_SRC_EN0		0
+#define MAX77620_FPS_EVENT_SRC_EN1		1
+#define MAX77620_FPS_EVENT_SRC_SW		2
+
+/* Device state when FPS event LOW  */
+#define MAX77620_FPS_INACTIVE_STATE_SLEEP	0
+#define MAX77620_FPS_INACTIVE_STATE_LOW_POWER	1
+
+/* FPS source */
+#define MAX77620_FPS_SRC_0			0
+#define MAX77620_FPS_SRC_1			1
+#define MAX77620_FPS_SRC_2			2
+#define MAX77620_FPS_SRC_NONE			3
+#define MAX77620_FPS_SRC_DEF			4
+
+#endif
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
new file mode 100644
index 000000000000..38f1ea879ea1
--- /dev/null
+++ b/include/dt-bindings/pinctrl/hisi.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for hisilicon pinctrl bindings.
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ * Copyright (c) 2015 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_HISI_H
+#define _DT_BINDINGS_PINCTRL_HISI_H
+
+/* iomg bit definition */
+#define MUX_M0		0
+#define MUX_M1		1
+#define MUX_M2		2
+#define MUX_M3		3
+#define MUX_M4		4
+#define MUX_M5		5
+#define MUX_M6		6
+#define MUX_M7		7
+
+/* iocg bit definition */
+#define PULL_MASK	(3)
+#define PULL_DIS	(0)
+#define PULL_UP		(1 << 0)
+#define PULL_DOWN	(1 << 1)
+
+/* drive strength definition */
+#define DRIVE_MASK	(7 << 4)
+#define DRIVE1_02MA	(0 << 4)
+#define DRIVE1_04MA	(1 << 4)
+#define DRIVE1_08MA	(2 << 4)
+#define DRIVE1_10MA	(3 << 4)
+#define DRIVE2_02MA	(0 << 4)
+#define DRIVE2_04MA	(1 << 4)
+#define DRIVE2_08MA	(2 << 4)
+#define DRIVE2_10MA	(3 << 4)
+#define DRIVE3_04MA	(0 << 4)
+#define DRIVE3_08MA	(1 << 4)
+#define DRIVE3_12MA	(2 << 4)
+#define DRIVE3_16MA	(3 << 4)
+#define DRIVE3_20MA	(4 << 4)
+#define DRIVE3_24MA	(5 << 4)
+#define DRIVE3_32MA	(6 << 4)
+#define DRIVE3_40MA	(7 << 4)
+#define DRIVE4_02MA	(0 << 4)
+#define DRIVE4_04MA	(2 << 4)
+#define DRIVE4_08MA	(4 << 4)
+#define DRIVE4_10MA	(6 << 4)
+
+#endif
diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
new file mode 100644
index 000000000000..2f00bdc42442
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
@@ -0,0 +1,520 @@
+#ifndef __DTS_MT7623_PINFUNC_H
+#define __DTS_MT7623_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
+#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
+
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
+#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
+
+#define MT7623_PIN_2_PWRAP_INT_FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT7623_PIN_2_PWRAP_INT_FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
+
+#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
+
+#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
+
+#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
+
+#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
+
+#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
+
+#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
+#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
+
+#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
+#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
+
+#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
+
+#define MT7623_PIN_11_WATCHDOG_FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT7623_PIN_11_WATCHDOG_FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
+
+#define MT7623_PIN_12_SRCLKENA_FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT7623_PIN_12_SRCLKENA_FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
+
+#define MT7623_PIN_13_SRCLKENAI_FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT7623_PIN_13_SRCLKENAI_FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
+
+#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1)
+#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
+
+#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
+#define MT7623_PIN_15_GPIO15_FUNC_URXD2 (MTK_PIN_NO(15) | 2)
+
+#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
+#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6)
+
+#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
+#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6)
+
+#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
+#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
+#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6)
+
+#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
+#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
+#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6)
+
+#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
+#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2)
+
+#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1)
+#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2)
+
+#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
+#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2)
+
+#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1)
+
+#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
+#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
+
+#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1)
+#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
+
+#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
+#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
+
+#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1)
+#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
+#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6)
+
+#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
+#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6)
+
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
+#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6)
+
+#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
+#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6)
+
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
+#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6)
+
+#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
+
+#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1)
+
+#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1)
+
+#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1)
+
+#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1)
+
+#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1)
+#define MT7623_PIN_43_NCLE_FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
+
+#define MT7623_PIN_44_NCEB1_FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT7623_PIN_44_NCEB1_FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
+#define MT7623_PIN_44_NCEB1_FUNC_IDDIG (MTK_PIN_NO(44) | 2)
+
+#define MT7623_PIN_45_NCEB0_FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT7623_PIN_45_NCEB0_FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
+#define MT7623_PIN_45_NCEB0_FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
+
+#define MT7623_PIN_46_IR_FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT7623_PIN_46_IR_FUNC_IR (MTK_PIN_NO(46) | 1)
+
+#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1)
+
+#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1)
+
+#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
+#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6)
+
+#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
+#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5)
+
+#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
+
+#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
+#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
+#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
+#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5)
+
+#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
+#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+
+#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1)
+
+#define MT7623_PIN_61_GPIO61_FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT7623_PIN_61_GPIO61_FUNC_TEST_FD (MTK_PIN_NO(61) | 1)
+
+#define MT7623_PIN_62_GPIO62_FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT7623_PIN_62_GPIO62_FUNC_TEST_FC (MTK_PIN_NO(62) | 1)
+
+#define MT7623_PIN_63_WB_SCLK_FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK (MTK_PIN_NO(63) | 1)
+
+#define MT7623_PIN_64_WB_SDATA_FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA (MTK_PIN_NO(64) | 1)
+
+#define MT7623_PIN_65_WB_SEN_FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT7623_PIN_65_WB_SEN_FUNC_WB_SEN (MTK_PIN_NO(65) | 1)
+
+#define MT7623_PIN_66_WB_CRTL0_FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1)
+
+#define MT7623_PIN_67_WB_CRTL1_FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1)
+
+#define MT7623_PIN_68_WB_CRTL2_FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1)
+
+#define MT7623_PIN_69_WB_CRTL3_FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1)
+
+#define MT7623_PIN_70_WB_CRTL4_FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1)
+
+#define MT7623_PIN_71_WB_CRTL5_FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1)
+
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PWM0 (MTK_PIN_NO(72) | 4)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
+#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_AP_I2S_DI (MTK_PIN_NO(72) | 6)
+
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
+#define MT7623_PIN_73_I2S0_LRCK_FUNC_AP_I2S_LRCK (MTK_PIN_NO(73) | 6)
+
+#define MT7623_PIN_74_I2S0_BCK_FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
+#define MT7623_PIN_74_I2S0_BCK_FUNC_AP_I2S_BCK (MTK_PIN_NO(74) | 6)
+
+#define MT7623_PIN_75_SDA0_FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT7623_PIN_75_SDA0_FUNC_SDA0 (MTK_PIN_NO(75) | 1)
+
+#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+
+#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
+
+#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
+
+#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1)
+
+#define MT7623_PIN_96_MIPI_TCP_FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT7623_PIN_96_MIPI_TCP_FUNC_TCP (MTK_PIN_NO(96) | 1)
+
+#define MT7623_PIN_97_MIPI_TDN1_FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1 (MTK_PIN_NO(97) | 1)
+
+#define MT7623_PIN_98_MIPI_TDP1_FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1 (MTK_PIN_NO(98) | 1)
+
+#define MT7623_PIN_99_MIPI_TDN0_FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0 (MTK_PIN_NO(99) | 1)
+
+#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1)
+
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3)
+#define MT7623_PIN_105_MSDC1_CMD_FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
+
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_SCL1 (MTK_PIN_NO(106) | 3)
+#define MT7623_PIN_106_MSDC1_CLK_FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
+
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
+#define MT7623_PIN_107_MSDC1_DAT0_FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
+
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM0 (MTK_PIN_NO(108) | 3)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_URXD0 (MTK_PIN_NO(108) | 5)
+#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM1 (MTK_PIN_NO(108) | 6)
+
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_SDA2 (MTK_PIN_NO(109) | 3)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
+#define MT7623_PIN_109_MSDC1_DAT2_FUNC_PWM2 (MTK_PIN_NO(109) | 6)
+
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_SCL2 (MTK_PIN_NO(110) | 3)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_URXD1 (MTK_PIN_NO(110) | 5)
+#define MT7623_PIN_110_MSDC1_DAT3_FUNC_PWM3 (MTK_PIN_NO(110) | 6)
+
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
+#define MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7 (MTK_PIN_NO(111) | 4)
+
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
+#define MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6 (MTK_PIN_NO(112) | 4)
+
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
+#define MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5 (MTK_PIN_NO(113) | 4)
+
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
+#define MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4 (MTK_PIN_NO(114) | 4)
+
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
+#define MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8 (MTK_PIN_NO(115) | 4)
+
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
+#define MT7623_PIN_116_MSDC0_CMD_FUNC_NALE (MTK_PIN_NO(116) | 4)
+
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB (MTK_PIN_NO(117) | 4)
+
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
+#define MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3 (MTK_PIN_NO(118) | 4)
+
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
+#define MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2 (MTK_PIN_NO(119) | 4)
+
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
+#define MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1 (MTK_PIN_NO(120) | 4)
+
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0 (MTK_PIN_NO(121) | 4)
+#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
+
+#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT7623_PIN_122_GPIO122_FUNC_TEST (MTK_PIN_NO(122) | 1)
+#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
+#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
+
+#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1)
+#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+
+#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)
+#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4)
+#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5)
+
+#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT7623_PIN_125_GPIO125_FUNC_TEST (MTK_PIN_NO(125) | 1)
+#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4)
+#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5)
+
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
+#define MT7623_PIN_126_I2S0_MCLK_FUNC_AP_I2S_MCLK (MTK_PIN_NO(126) | 6)
+
+#define MT7623_PIN_199_SPI1_CK_FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
+
+#define MT7623_PIN_200_URXD2_FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT7623_PIN_200_URXD2_FUNC_URXD2 (MTK_PIN_NO(200) | 6)
+
+#define MT7623_PIN_201_UTXD2_FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT7623_PIN_201_UTXD2_FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
+
+#define MT7623_PIN_203_PWM0_FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT7623_PIN_203_PWM0_FUNC_PWM0 (MTK_PIN_NO(203) | 1)
+#define MT7623_PIN_203_PWM0_FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
+
+#define MT7623_PIN_204_PWM1_FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT7623_PIN_204_PWM1_FUNC_PWM1 (MTK_PIN_NO(204) | 1)
+
+#define MT7623_PIN_205_PWM2_FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT7623_PIN_205_PWM2_FUNC_PWM2 (MTK_PIN_NO(205) | 1)
+
+#define MT7623_PIN_206_PWM3_FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT7623_PIN_206_PWM3_FUNC_PWM3 (MTK_PIN_NO(206) | 1)
+
+#define MT7623_PIN_207_PWM4_FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT7623_PIN_207_PWM4_FUNC_PWM4 (MTK_PIN_NO(207) | 1)
+
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PWM0 (MTK_PIN_NO(208) | 2)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 3)
+#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
+
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 3)
+#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PWM1 (MTK_PIN_NO(209) | 5)
+
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
+#define MT7623_PIN_236_EXT_SDIO3_FUNC_IDDIG (MTK_PIN_NO(236) | 2)
+
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
+#define MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
+
+#define MT7623_PIN_238_EXT_SDIO1_FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT7623_PIN_238_EXT_SDIO1_FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
+
+#define MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT7623_PIN_239_EXT_SDIO0_FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
+
+#define MT7623_PIN_240_EXT_XCS_FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT7623_PIN_240_EXT_XCS_FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
+
+#define MT7623_PIN_241_EXT_SCK_FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT7623_PIN_241_EXT_SCK_FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
+
+#define MT7623_PIN_242_URTS2_FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT7623_PIN_242_URTS2_FUNC_URTS2 (MTK_PIN_NO(242) | 1)
+#define MT7623_PIN_242_URTS2_FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
+#define MT7623_PIN_242_URTS2_FUNC_URXD3 (MTK_PIN_NO(242) | 3)
+#define MT7623_PIN_242_URTS2_FUNC_SCL1 (MTK_PIN_NO(242) | 4)
+
+#define MT7623_PIN_243_UCTS2_FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT7623_PIN_243_UCTS2_FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
+#define MT7623_PIN_243_UCTS2_FUNC_URXD3 (MTK_PIN_NO(243) | 2)
+#define MT7623_PIN_243_UCTS2_FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
+#define MT7623_PIN_243_UCTS2_FUNC_SDA1 (MTK_PIN_NO(243) | 4)
+
+#define MT7623_PIN_250_GPIO250_FUNC_GPIO250 (MTK_PIN_NO(250) | 0)
+#define MT7623_PIN_250_GPIO250_FUNC_TEST_MD7 (MTK_PIN_NO(250) | 1)
+#define MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 6)
+
+#define MT7623_PIN_251_GPIO251_FUNC_GPIO251 (MTK_PIN_NO(251) | 0)
+#define MT7623_PIN_251_GPIO251_FUNC_TEST_MD6 (MTK_PIN_NO(251) | 1)
+#define MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 6)
+
+#define MT7623_PIN_252_GPIO252_FUNC_GPIO252 (MTK_PIN_NO(252) | 0)
+#define MT7623_PIN_252_GPIO252_FUNC_TEST_MD5 (MTK_PIN_NO(252) | 1)
+#define MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 6)
+
+#define MT7623_PIN_253_GPIO253_FUNC_GPIO253 (MTK_PIN_NO(253) | 0)
+#define MT7623_PIN_253_GPIO253_FUNC_TEST_MD4 (MTK_PIN_NO(253) | 1)
+#define MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 6)
+
+#define MT7623_PIN_254_GPIO254_FUNC_GPIO254 (MTK_PIN_NO(254) | 0)
+#define MT7623_PIN_254_GPIO254_FUNC_TEST_MD3 (MTK_PIN_NO(254) | 1)
+#define MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 6)
+
+#define MT7623_PIN_255_GPIO255_FUNC_GPIO255 (MTK_PIN_NO(255) | 0)
+#define MT7623_PIN_255_GPIO255_FUNC_TEST_MD2 (MTK_PIN_NO(255) | 1)
+#define MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 6)
+
+#define MT7623_PIN_256_GPIO256_FUNC_GPIO256 (MTK_PIN_NO(256) | 0)
+#define MT7623_PIN_256_GPIO256_FUNC_TEST_MD1 (MTK_PIN_NO(256) | 1)
+
+#define MT7623_PIN_257_GPIO257_FUNC_GPIO257 (MTK_PIN_NO(257) | 0)
+#define MT7623_PIN_257_GPIO257_FUNC_TEST_MD0 (MTK_PIN_NO(257) | 1)
+
+#define MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT7623_PIN_261_MSDC1_INS_FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
+
+#define MT7623_PIN_262_G2_TXEN_FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
+#define MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
+
+#define MT7623_PIN_263_G2_TXD3_FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
+#define MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
+
+#define MT7623_PIN_264_G2_TXD2_FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
+#define MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
+
+#define MT7623_PIN_265_G2_TXD1_FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
+#define MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
+
+#define MT7623_PIN_266_G2_TXD0_FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
+#define MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
+
+#define MT7623_PIN_267_G2_TXCLK_FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
+#define MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
+
+#define MT7623_PIN_268_G2_RXCLK_FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
+#define MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
+
+#define MT7623_PIN_269_G2_RXD0_FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
+#define MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
+
+#define MT7623_PIN_270_G2_RXD1_FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
+#define MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
+
+#define MT7623_PIN_271_G2_RXD2_FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
+#define MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
+
+#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
+#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+
+#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
+#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
+
+#define MT7623_PIN_275_G2_MDC_FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
+#define MT7623_PIN_275_G2_MDC_FUNC_MDC (MTK_PIN_NO(275) | 1)
+
+#define MT7623_PIN_276_G2_MDIO_FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
+#define MT7623_PIN_276_G2_MDIO_FUNC_MDIO (MTK_PIN_NO(276) | 1)
+
+#define MT7623_PIN_278_JTAG_RESET_FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
+#define MT7623_PIN_278_JTAG_RESET_FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
+
+#endif /* __DTS_MT7623_PINFUNC_H */
diff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
new file mode 100644
index 000000000000..26f18798d949
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h
@@ -0,0 +1,1239 @@
+#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H
+#define _DT_BINDINGS_STM32F429_PINFUNC_H
+
+#define STM32F429_PA0_FUNC_GPIO 0x0
+#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
+#define STM32F429_PA0_FUNC_TIM5_CH1 0x3
+#define STM32F429_PA0_FUNC_TIM8_ETR 0x4
+#define STM32F429_PA0_FUNC_USART2_CTS 0x8
+#define STM32F429_PA0_FUNC_UART4_TX 0x9
+#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc
+#define STM32F429_PA0_FUNC_EVENTOUT 0x10
+#define STM32F429_PA0_FUNC_ANALOG 0x11
+
+#define STM32F429_PA1_FUNC_GPIO 0x100
+#define STM32F429_PA1_FUNC_TIM2_CH2 0x102
+#define STM32F429_PA1_FUNC_TIM5_CH2 0x103
+#define STM32F429_PA1_FUNC_USART2_RTS 0x108
+#define STM32F429_PA1_FUNC_UART4_RX 0x109
+#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c
+#define STM32F429_PA1_FUNC_EVENTOUT 0x110
+#define STM32F429_PA1_FUNC_ANALOG 0x111
+
+#define STM32F429_PA2_FUNC_GPIO 0x200
+#define STM32F429_PA2_FUNC_TIM2_CH3 0x202
+#define STM32F429_PA2_FUNC_TIM5_CH3 0x203
+#define STM32F429_PA2_FUNC_TIM9_CH1 0x204
+#define STM32F429_PA2_FUNC_USART2_TX 0x208
+#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c
+#define STM32F429_PA2_FUNC_EVENTOUT 0x210
+#define STM32F429_PA2_FUNC_ANALOG 0x211
+
+#define STM32F429_PA3_FUNC_GPIO 0x300
+#define STM32F429_PA3_FUNC_TIM2_CH4 0x302
+#define STM32F429_PA3_FUNC_TIM5_CH4 0x303
+#define STM32F429_PA3_FUNC_TIM9_CH2 0x304
+#define STM32F429_PA3_FUNC_USART2_RX 0x308
+#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b
+#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c
+#define STM32F429_PA3_FUNC_LCD_B5 0x30f
+#define STM32F429_PA3_FUNC_EVENTOUT 0x310
+#define STM32F429_PA3_FUNC_ANALOG 0x311
+
+#define STM32F429_PA4_FUNC_GPIO 0x400
+#define STM32F429_PA4_FUNC_SPI1_NSS 0x406
+#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407
+#define STM32F429_PA4_FUNC_USART2_CK 0x408
+#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d
+#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e
+#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f
+#define STM32F429_PA4_FUNC_EVENTOUT 0x410
+#define STM32F429_PA4_FUNC_ANALOG 0x411
+
+#define STM32F429_PA5_FUNC_GPIO 0x500
+#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502
+#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504
+#define STM32F429_PA5_FUNC_SPI1_SCK 0x506
+#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b
+#define STM32F429_PA5_FUNC_EVENTOUT 0x510
+#define STM32F429_PA5_FUNC_ANALOG 0x511
+
+#define STM32F429_PA6_FUNC_GPIO 0x600
+#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602
+#define STM32F429_PA6_FUNC_TIM3_CH1 0x603
+#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604
+#define STM32F429_PA6_FUNC_SPI1_MISO 0x606
+#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a
+#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e
+#define STM32F429_PA6_FUNC_LCD_G2 0x60f
+#define STM32F429_PA6_FUNC_EVENTOUT 0x610
+#define STM32F429_PA6_FUNC_ANALOG 0x611
+
+#define STM32F429_PA7_FUNC_GPIO 0x700
+#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702
+#define STM32F429_PA7_FUNC_TIM3_CH2 0x703
+#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704
+#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706
+#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a
+#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c
+#define STM32F429_PA7_FUNC_EVENTOUT 0x710
+#define STM32F429_PA7_FUNC_ANALOG 0x711
+
+#define STM32F429_PA8_FUNC_GPIO 0x800
+#define STM32F429_PA8_FUNC_MCO1 0x801
+#define STM32F429_PA8_FUNC_TIM1_CH1 0x802
+#define STM32F429_PA8_FUNC_I2C3_SCL 0x805
+#define STM32F429_PA8_FUNC_USART1_CK 0x808
+#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b
+#define STM32F429_PA8_FUNC_LCD_R6 0x80f
+#define STM32F429_PA8_FUNC_EVENTOUT 0x810
+#define STM32F429_PA8_FUNC_ANALOG 0x811
+
+#define STM32F429_PA9_FUNC_GPIO 0x900
+#define STM32F429_PA9_FUNC_TIM1_CH2 0x902
+#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905
+#define STM32F429_PA9_FUNC_USART1_TX 0x908
+#define STM32F429_PA9_FUNC_DCMI_D0 0x90e
+#define STM32F429_PA9_FUNC_EVENTOUT 0x910
+#define STM32F429_PA9_FUNC_ANALOG 0x911
+
+#define STM32F429_PA10_FUNC_GPIO 0xa00
+#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02
+#define STM32F429_PA10_FUNC_USART1_RX 0xa08
+#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b
+#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e
+#define STM32F429_PA10_FUNC_EVENTOUT 0xa10
+#define STM32F429_PA10_FUNC_ANALOG 0xa11
+
+#define STM32F429_PA11_FUNC_GPIO 0xb00
+#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02
+#define STM32F429_PA11_FUNC_USART1_CTS 0xb08
+#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a
+#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b
+#define STM32F429_PA11_FUNC_LCD_R4 0xb0f
+#define STM32F429_PA11_FUNC_EVENTOUT 0xb10
+#define STM32F429_PA11_FUNC_ANALOG 0xb11
+
+#define STM32F429_PA12_FUNC_GPIO 0xc00
+#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02
+#define STM32F429_PA12_FUNC_USART1_RTS 0xc08
+#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a
+#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b
+#define STM32F429_PA12_FUNC_LCD_R5 0xc0f
+#define STM32F429_PA12_FUNC_EVENTOUT 0xc10
+#define STM32F429_PA12_FUNC_ANALOG 0xc11
+
+#define STM32F429_PA13_FUNC_GPIO 0xd00
+#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01
+#define STM32F429_PA13_FUNC_EVENTOUT 0xd10
+#define STM32F429_PA13_FUNC_ANALOG 0xd11
+
+#define STM32F429_PA14_FUNC_GPIO 0xe00
+#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01
+#define STM32F429_PA14_FUNC_EVENTOUT 0xe10
+#define STM32F429_PA14_FUNC_ANALOG 0xe11
+
+#define STM32F429_PA15_FUNC_GPIO 0xf00
+#define STM32F429_PA15_FUNC_JTDI 0xf01
+#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02
+#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06
+#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07
+#define STM32F429_PA15_FUNC_EVENTOUT 0xf10
+#define STM32F429_PA15_FUNC_ANALOG 0xf11
+
+
+
+#define STM32F429_PB0_FUNC_GPIO 0x1000
+#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002
+#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003
+#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004
+#define STM32F429_PB0_FUNC_LCD_R3 0x100a
+#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b
+#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c
+#define STM32F429_PB0_FUNC_EVENTOUT 0x1010
+#define STM32F429_PB0_FUNC_ANALOG 0x1011
+
+#define STM32F429_PB1_FUNC_GPIO 0x1100
+#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102
+#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103
+#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104
+#define STM32F429_PB1_FUNC_LCD_R6 0x110a
+#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b
+#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c
+#define STM32F429_PB1_FUNC_EVENTOUT 0x1110
+#define STM32F429_PB1_FUNC_ANALOG 0x1111
+
+#define STM32F429_PB2_FUNC_GPIO 0x1200
+#define STM32F429_PB2_FUNC_EVENTOUT 0x1210
+#define STM32F429_PB2_FUNC_ANALOG 0x1211
+
+#define STM32F429_PB3_FUNC_GPIO 0x1300
+#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301
+#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302
+#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306
+#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
+#define STM32F429_PB3_FUNC_EVENTOUT 0x1310
+#define STM32F429_PB3_FUNC_ANALOG 0x1311
+
+#define STM32F429_PB4_FUNC_GPIO 0x1400
+#define STM32F429_PB4_FUNC_NJTRST 0x1401
+#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403
+#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406
+#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407
+#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408
+#define STM32F429_PB4_FUNC_EVENTOUT 0x1410
+#define STM32F429_PB4_FUNC_ANALOG 0x1411
+
+#define STM32F429_PB5_FUNC_GPIO 0x1500
+#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503
+#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505
+#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506
+#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507
+#define STM32F429_PB5_FUNC_CAN2_RX 0x150a
+#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b
+#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c
+#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d
+#define STM32F429_PB5_FUNC_DCMI_D10 0x150e
+#define STM32F429_PB5_FUNC_EVENTOUT 0x1510
+#define STM32F429_PB5_FUNC_ANALOG 0x1511
+
+#define STM32F429_PB6_FUNC_GPIO 0x1600
+#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603
+#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605
+#define STM32F429_PB6_FUNC_USART1_TX 0x1608
+#define STM32F429_PB6_FUNC_CAN2_TX 0x160a
+#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d
+#define STM32F429_PB6_FUNC_DCMI_D5 0x160e
+#define STM32F429_PB6_FUNC_EVENTOUT 0x1610
+#define STM32F429_PB6_FUNC_ANALOG 0x1611
+
+#define STM32F429_PB7_FUNC_GPIO 0x1700
+#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703
+#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705
+#define STM32F429_PB7_FUNC_USART1_RX 0x1708
+#define STM32F429_PB7_FUNC_FMC_NL 0x170d
+#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e
+#define STM32F429_PB7_FUNC_EVENTOUT 0x1710
+#define STM32F429_PB7_FUNC_ANALOG 0x1711
+
+#define STM32F429_PB8_FUNC_GPIO 0x1800
+#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803
+#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804
+#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805
+#define STM32F429_PB8_FUNC_CAN1_RX 0x180a
+#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c
+#define STM32F429_PB8_FUNC_SDIO_D4 0x180d
+#define STM32F429_PB8_FUNC_DCMI_D6 0x180e
+#define STM32F429_PB8_FUNC_LCD_B6 0x180f
+#define STM32F429_PB8_FUNC_EVENTOUT 0x1810
+#define STM32F429_PB8_FUNC_ANALOG 0x1811
+
+#define STM32F429_PB9_FUNC_GPIO 0x1900
+#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903
+#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904
+#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905
+#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906
+#define STM32F429_PB9_FUNC_CAN1_TX 0x190a
+#define STM32F429_PB9_FUNC_SDIO_D5 0x190d
+#define STM32F429_PB9_FUNC_DCMI_D7 0x190e
+#define STM32F429_PB9_FUNC_LCD_B7 0x190f
+#define STM32F429_PB9_FUNC_EVENTOUT 0x1910
+#define STM32F429_PB9_FUNC_ANALOG 0x1911
+
+#define STM32F429_PB10_FUNC_GPIO 0x1a00
+#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02
+#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05
+#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06
+#define STM32F429_PB10_FUNC_USART3_TX 0x1a08
+#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b
+#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c
+#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f
+#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10
+#define STM32F429_PB10_FUNC_ANALOG 0x1a11
+
+#define STM32F429_PB11_FUNC_GPIO 0x1b00
+#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02
+#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05
+#define STM32F429_PB11_FUNC_USART3_RX 0x1b08
+#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b
+#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c
+#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f
+#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10
+#define STM32F429_PB11_FUNC_ANALOG 0x1b11
+
+#define STM32F429_PB12_FUNC_GPIO 0x1c00
+#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02
+#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05
+#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06
+#define STM32F429_PB12_FUNC_USART3_CK 0x1c08
+#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a
+#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b
+#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c
+#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d
+#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10
+#define STM32F429_PB12_FUNC_ANALOG 0x1c11
+
+#define STM32F429_PB13_FUNC_GPIO 0x1d00
+#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02
+#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06
+#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08
+#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a
+#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b
+#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c
+#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10
+#define STM32F429_PB13_FUNC_ANALOG 0x1d11
+
+#define STM32F429_PB14_FUNC_GPIO 0x1e00
+#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02
+#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04
+#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06
+#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07
+#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08
+#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a
+#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d
+#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10
+#define STM32F429_PB14_FUNC_ANALOG 0x1e11
+
+#define STM32F429_PB15_FUNC_GPIO 0x1f00
+#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01
+#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02
+#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04
+#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06
+#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a
+#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d
+#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10
+#define STM32F429_PB15_FUNC_ANALOG 0x1f11
+
+
+
+#define STM32F429_PC0_FUNC_GPIO 0x2000
+#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b
+#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d
+#define STM32F429_PC0_FUNC_EVENTOUT 0x2010
+#define STM32F429_PC0_FUNC_ANALOG 0x2011
+
+#define STM32F429_PC1_FUNC_GPIO 0x2100
+#define STM32F429_PC1_FUNC_ETH_MDC 0x210c
+#define STM32F429_PC1_FUNC_EVENTOUT 0x2110
+#define STM32F429_PC1_FUNC_ANALOG 0x2111
+
+#define STM32F429_PC2_FUNC_GPIO 0x2200
+#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206
+#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207
+#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b
+#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c
+#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d
+#define STM32F429_PC2_FUNC_EVENTOUT 0x2210
+#define STM32F429_PC2_FUNC_ANALOG 0x2211
+
+#define STM32F429_PC3_FUNC_GPIO 0x2300
+#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306
+#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b
+#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c
+#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d
+#define STM32F429_PC3_FUNC_EVENTOUT 0x2310
+#define STM32F429_PC3_FUNC_ANALOG 0x2311
+
+#define STM32F429_PC4_FUNC_GPIO 0x2400
+#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c
+#define STM32F429_PC4_FUNC_EVENTOUT 0x2410
+#define STM32F429_PC4_FUNC_ANALOG 0x2411
+
+#define STM32F429_PC5_FUNC_GPIO 0x2500
+#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c
+#define STM32F429_PC5_FUNC_EVENTOUT 0x2510
+#define STM32F429_PC5_FUNC_ANALOG 0x2511
+
+#define STM32F429_PC6_FUNC_GPIO 0x2600
+#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603
+#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604
+#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606
+#define STM32F429_PC6_FUNC_USART6_TX 0x2609
+#define STM32F429_PC6_FUNC_SDIO_D6 0x260d
+#define STM32F429_PC6_FUNC_DCMI_D0 0x260e
+#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f
+#define STM32F429_PC6_FUNC_EVENTOUT 0x2610
+#define STM32F429_PC6_FUNC_ANALOG 0x2611
+
+#define STM32F429_PC7_FUNC_GPIO 0x2700
+#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703
+#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704
+#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707
+#define STM32F429_PC7_FUNC_USART6_RX 0x2709
+#define STM32F429_PC7_FUNC_SDIO_D7 0x270d
+#define STM32F429_PC7_FUNC_DCMI_D1 0x270e
+#define STM32F429_PC7_FUNC_LCD_G6 0x270f
+#define STM32F429_PC7_FUNC_EVENTOUT 0x2710
+#define STM32F429_PC7_FUNC_ANALOG 0x2711
+
+#define STM32F429_PC8_FUNC_GPIO 0x2800
+#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803
+#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804
+#define STM32F429_PC8_FUNC_USART6_CK 0x2809
+#define STM32F429_PC8_FUNC_SDIO_D0 0x280d
+#define STM32F429_PC8_FUNC_DCMI_D2 0x280e
+#define STM32F429_PC8_FUNC_EVENTOUT 0x2810
+#define STM32F429_PC8_FUNC_ANALOG 0x2811
+
+#define STM32F429_PC9_FUNC_GPIO 0x2900
+#define STM32F429_PC9_FUNC_MCO2 0x2901
+#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903
+#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904
+#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905
+#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906
+#define STM32F429_PC9_FUNC_SDIO_D1 0x290d
+#define STM32F429_PC9_FUNC_DCMI_D3 0x290e
+#define STM32F429_PC9_FUNC_EVENTOUT 0x2910
+#define STM32F429_PC9_FUNC_ANALOG 0x2911
+
+#define STM32F429_PC10_FUNC_GPIO 0x2a00
+#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07
+#define STM32F429_PC10_FUNC_USART3_TX 0x2a08
+#define STM32F429_PC10_FUNC_UART4_TX 0x2a09
+#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d
+#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e
+#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f
+#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10
+#define STM32F429_PC10_FUNC_ANALOG 0x2a11
+
+#define STM32F429_PC11_FUNC_GPIO 0x2b00
+#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06
+#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07
+#define STM32F429_PC11_FUNC_USART3_RX 0x2b08
+#define STM32F429_PC11_FUNC_UART4_RX 0x2b09
+#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d
+#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e
+#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10
+#define STM32F429_PC11_FUNC_ANALOG 0x2b11
+
+#define STM32F429_PC12_FUNC_GPIO 0x2c00
+#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07
+#define STM32F429_PC12_FUNC_USART3_CK 0x2c08
+#define STM32F429_PC12_FUNC_UART5_TX 0x2c09
+#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d
+#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e
+#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10
+#define STM32F429_PC12_FUNC_ANALOG 0x2c11
+
+#define STM32F429_PC13_FUNC_GPIO 0x2d00
+#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10
+#define STM32F429_PC13_FUNC_ANALOG 0x2d11
+
+#define STM32F429_PC14_FUNC_GPIO 0x2e00
+#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10
+#define STM32F429_PC14_FUNC_ANALOG 0x2e11
+
+#define STM32F429_PC15_FUNC_GPIO 0x2f00
+#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10
+#define STM32F429_PC15_FUNC_ANALOG 0x2f11
+
+
+
+#define STM32F429_PD0_FUNC_GPIO 0x3000
+#define STM32F429_PD0_FUNC_CAN1_RX 0x300a
+#define STM32F429_PD0_FUNC_FMC_D2 0x300d
+#define STM32F429_PD0_FUNC_EVENTOUT 0x3010
+#define STM32F429_PD0_FUNC_ANALOG 0x3011
+
+#define STM32F429_PD1_FUNC_GPIO 0x3100
+#define STM32F429_PD1_FUNC_CAN1_TX 0x310a
+#define STM32F429_PD1_FUNC_FMC_D3 0x310d
+#define STM32F429_PD1_FUNC_EVENTOUT 0x3110
+#define STM32F429_PD1_FUNC_ANALOG 0x3111
+
+#define STM32F429_PD2_FUNC_GPIO 0x3200
+#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203
+#define STM32F429_PD2_FUNC_UART5_RX 0x3209
+#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d
+#define STM32F429_PD2_FUNC_DCMI_D11 0x320e
+#define STM32F429_PD2_FUNC_EVENTOUT 0x3210
+#define STM32F429_PD2_FUNC_ANALOG 0x3211
+
+#define STM32F429_PD3_FUNC_GPIO 0x3300
+#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306
+#define STM32F429_PD3_FUNC_USART2_CTS 0x3308
+#define STM32F429_PD3_FUNC_FMC_CLK 0x330d
+#define STM32F429_PD3_FUNC_DCMI_D5 0x330e
+#define STM32F429_PD3_FUNC_LCD_G7 0x330f
+#define STM32F429_PD3_FUNC_EVENTOUT 0x3310
+#define STM32F429_PD3_FUNC_ANALOG 0x3311
+
+#define STM32F429_PD4_FUNC_GPIO 0x3400
+#define STM32F429_PD4_FUNC_USART2_RTS 0x3408
+#define STM32F429_PD4_FUNC_FMC_NOE 0x340d
+#define STM32F429_PD4_FUNC_EVENTOUT 0x3410
+#define STM32F429_PD4_FUNC_ANALOG 0x3411
+
+#define STM32F429_PD5_FUNC_GPIO 0x3500
+#define STM32F429_PD5_FUNC_USART2_TX 0x3508
+#define STM32F429_PD5_FUNC_FMC_NWE 0x350d
+#define STM32F429_PD5_FUNC_EVENTOUT 0x3510
+#define STM32F429_PD5_FUNC_ANALOG 0x3511
+
+#define STM32F429_PD6_FUNC_GPIO 0x3600
+#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
+#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607
+#define STM32F429_PD6_FUNC_USART2_RX 0x3608
+#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d
+#define STM32F429_PD6_FUNC_DCMI_D10 0x360e
+#define STM32F429_PD6_FUNC_LCD_B2 0x360f
+#define STM32F429_PD6_FUNC_EVENTOUT 0x3610
+#define STM32F429_PD6_FUNC_ANALOG 0x3611
+
+#define STM32F429_PD7_FUNC_GPIO 0x3700
+#define STM32F429_PD7_FUNC_USART2_CK 0x3708
+#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d
+#define STM32F429_PD7_FUNC_EVENTOUT 0x3710
+#define STM32F429_PD7_FUNC_ANALOG 0x3711
+
+#define STM32F429_PD8_FUNC_GPIO 0x3800
+#define STM32F429_PD8_FUNC_USART3_TX 0x3808
+#define STM32F429_PD8_FUNC_FMC_D13 0x380d
+#define STM32F429_PD8_FUNC_EVENTOUT 0x3810
+#define STM32F429_PD8_FUNC_ANALOG 0x3811
+
+#define STM32F429_PD9_FUNC_GPIO 0x3900
+#define STM32F429_PD9_FUNC_USART3_RX 0x3908
+#define STM32F429_PD9_FUNC_FMC_D14 0x390d
+#define STM32F429_PD9_FUNC_EVENTOUT 0x3910
+#define STM32F429_PD9_FUNC_ANALOG 0x3911
+
+#define STM32F429_PD10_FUNC_GPIO 0x3a00
+#define STM32F429_PD10_FUNC_USART3_CK 0x3a08
+#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d
+#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f
+#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10
+#define STM32F429_PD10_FUNC_ANALOG 0x3a11
+
+#define STM32F429_PD11_FUNC_GPIO 0x3b00
+#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08
+#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d
+#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10
+#define STM32F429_PD11_FUNC_ANALOG 0x3b11
+
+#define STM32F429_PD12_FUNC_GPIO 0x3c00
+#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03
+#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08
+#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d
+#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10
+#define STM32F429_PD12_FUNC_ANALOG 0x3c11
+
+#define STM32F429_PD13_FUNC_GPIO 0x3d00
+#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03
+#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d
+#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10
+#define STM32F429_PD13_FUNC_ANALOG 0x3d11
+
+#define STM32F429_PD14_FUNC_GPIO 0x3e00
+#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03
+#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d
+#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10
+#define STM32F429_PD14_FUNC_ANALOG 0x3e11
+
+#define STM32F429_PD15_FUNC_GPIO 0x3f00
+#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03
+#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d
+#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10
+#define STM32F429_PD15_FUNC_ANALOG 0x3f11
+
+
+
+#define STM32F429_PE0_FUNC_GPIO 0x4000
+#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003
+#define STM32F429_PE0_FUNC_UART8_RX 0x4009
+#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d
+#define STM32F429_PE0_FUNC_DCMI_D2 0x400e
+#define STM32F429_PE0_FUNC_EVENTOUT 0x4010
+#define STM32F429_PE0_FUNC_ANALOG 0x4011
+
+#define STM32F429_PE1_FUNC_GPIO 0x4100
+#define STM32F429_PE1_FUNC_UART8_TX 0x4109
+#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d
+#define STM32F429_PE1_FUNC_DCMI_D3 0x410e
+#define STM32F429_PE1_FUNC_EVENTOUT 0x4110
+#define STM32F429_PE1_FUNC_ANALOG 0x4111
+
+#define STM32F429_PE2_FUNC_GPIO 0x4200
+#define STM32F429_PE2_FUNC_TRACECLK 0x4201
+#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206
+#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207
+#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c
+#define STM32F429_PE2_FUNC_FMC_A23 0x420d
+#define STM32F429_PE2_FUNC_EVENTOUT 0x4210
+#define STM32F429_PE2_FUNC_ANALOG 0x4211
+
+#define STM32F429_PE3_FUNC_GPIO 0x4300
+#define STM32F429_PE3_FUNC_TRACED0 0x4301
+#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307
+#define STM32F429_PE3_FUNC_FMC_A19 0x430d
+#define STM32F429_PE3_FUNC_EVENTOUT 0x4310
+#define STM32F429_PE3_FUNC_ANALOG 0x4311
+
+#define STM32F429_PE4_FUNC_GPIO 0x4400
+#define STM32F429_PE4_FUNC_TRACED1 0x4401
+#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406
+#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407
+#define STM32F429_PE4_FUNC_FMC_A20 0x440d
+#define STM32F429_PE4_FUNC_DCMI_D4 0x440e
+#define STM32F429_PE4_FUNC_LCD_B0 0x440f
+#define STM32F429_PE4_FUNC_EVENTOUT 0x4410
+#define STM32F429_PE4_FUNC_ANALOG 0x4411
+
+#define STM32F429_PE5_FUNC_GPIO 0x4500
+#define STM32F429_PE5_FUNC_TRACED2 0x4501
+#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504
+#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506
+#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507
+#define STM32F429_PE5_FUNC_FMC_A21 0x450d
+#define STM32F429_PE5_FUNC_DCMI_D6 0x450e
+#define STM32F429_PE5_FUNC_LCD_G0 0x450f
+#define STM32F429_PE5_FUNC_EVENTOUT 0x4510
+#define STM32F429_PE5_FUNC_ANALOG 0x4511
+
+#define STM32F429_PE6_FUNC_GPIO 0x4600
+#define STM32F429_PE6_FUNC_TRACED3 0x4601
+#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604
+#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606
+#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607
+#define STM32F429_PE6_FUNC_FMC_A22 0x460d
+#define STM32F429_PE6_FUNC_DCMI_D7 0x460e
+#define STM32F429_PE6_FUNC_LCD_G1 0x460f
+#define STM32F429_PE6_FUNC_EVENTOUT 0x4610
+#define STM32F429_PE6_FUNC_ANALOG 0x4611
+
+#define STM32F429_PE7_FUNC_GPIO 0x4700
+#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702
+#define STM32F429_PE7_FUNC_UART7_RX 0x4709
+#define STM32F429_PE7_FUNC_FMC_D4 0x470d
+#define STM32F429_PE7_FUNC_EVENTOUT 0x4710
+#define STM32F429_PE7_FUNC_ANALOG 0x4711
+
+#define STM32F429_PE8_FUNC_GPIO 0x4800
+#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802
+#define STM32F429_PE8_FUNC_UART7_TX 0x4809
+#define STM32F429_PE8_FUNC_FMC_D5 0x480d
+#define STM32F429_PE8_FUNC_EVENTOUT 0x4810
+#define STM32F429_PE8_FUNC_ANALOG 0x4811
+
+#define STM32F429_PE9_FUNC_GPIO 0x4900
+#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902
+#define STM32F429_PE9_FUNC_FMC_D6 0x490d
+#define STM32F429_PE9_FUNC_EVENTOUT 0x4910
+#define STM32F429_PE9_FUNC_ANALOG 0x4911
+
+#define STM32F429_PE10_FUNC_GPIO 0x4a00
+#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02
+#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d
+#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10
+#define STM32F429_PE10_FUNC_ANALOG 0x4a11
+
+#define STM32F429_PE11_FUNC_GPIO 0x4b00
+#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02
+#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06
+#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d
+#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f
+#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10
+#define STM32F429_PE11_FUNC_ANALOG 0x4b11
+
+#define STM32F429_PE12_FUNC_GPIO 0x4c00
+#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02
+#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06
+#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d
+#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f
+#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10
+#define STM32F429_PE12_FUNC_ANALOG 0x4c11
+
+#define STM32F429_PE13_FUNC_GPIO 0x4d00
+#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02
+#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06
+#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d
+#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f
+#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10
+#define STM32F429_PE13_FUNC_ANALOG 0x4d11
+
+#define STM32F429_PE14_FUNC_GPIO 0x4e00
+#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02
+#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06
+#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d
+#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f
+#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10
+#define STM32F429_PE14_FUNC_ANALOG 0x4e11
+
+#define STM32F429_PE15_FUNC_GPIO 0x4f00
+#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02
+#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d
+#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f
+#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10
+#define STM32F429_PE15_FUNC_ANALOG 0x4f11
+
+
+
+#define STM32F429_PF0_FUNC_GPIO 0x5000
+#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005
+#define STM32F429_PF0_FUNC_FMC_A0 0x500d
+#define STM32F429_PF0_FUNC_EVENTOUT 0x5010
+#define STM32F429_PF0_FUNC_ANALOG 0x5011
+
+#define STM32F429_PF1_FUNC_GPIO 0x5100
+#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105
+#define STM32F429_PF1_FUNC_FMC_A1 0x510d
+#define STM32F429_PF1_FUNC_EVENTOUT 0x5110
+#define STM32F429_PF1_FUNC_ANALOG 0x5111
+
+#define STM32F429_PF2_FUNC_GPIO 0x5200
+#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205
+#define STM32F429_PF2_FUNC_FMC_A2 0x520d
+#define STM32F429_PF2_FUNC_EVENTOUT 0x5210
+#define STM32F429_PF2_FUNC_ANALOG 0x5211
+
+#define STM32F429_PF3_FUNC_GPIO 0x5300
+#define STM32F429_PF3_FUNC_FMC_A3 0x530d
+#define STM32F429_PF3_FUNC_EVENTOUT 0x5310
+#define STM32F429_PF3_FUNC_ANALOG 0x5311
+
+#define STM32F429_PF4_FUNC_GPIO 0x5400
+#define STM32F429_PF4_FUNC_FMC_A4 0x540d
+#define STM32F429_PF4_FUNC_EVENTOUT 0x5410
+#define STM32F429_PF4_FUNC_ANALOG 0x5411
+
+#define STM32F429_PF5_FUNC_GPIO 0x5500
+#define STM32F429_PF5_FUNC_FMC_A5 0x550d
+#define STM32F429_PF5_FUNC_EVENTOUT 0x5510
+#define STM32F429_PF5_FUNC_ANALOG 0x5511
+
+#define STM32F429_PF6_FUNC_GPIO 0x5600
+#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604
+#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606
+#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607
+#define STM32F429_PF6_FUNC_UART7_RX 0x5609
+#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d
+#define STM32F429_PF6_FUNC_EVENTOUT 0x5610
+#define STM32F429_PF6_FUNC_ANALOG 0x5611
+
+#define STM32F429_PF7_FUNC_GPIO 0x5700
+#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704
+#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706
+#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707
+#define STM32F429_PF7_FUNC_UART7_TX 0x5709
+#define STM32F429_PF7_FUNC_FMC_NREG 0x570d
+#define STM32F429_PF7_FUNC_EVENTOUT 0x5710
+#define STM32F429_PF7_FUNC_ANALOG 0x5711
+
+#define STM32F429_PF8_FUNC_GPIO 0x5800
+#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806
+#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807
+#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a
+#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d
+#define STM32F429_PF8_FUNC_EVENTOUT 0x5810
+#define STM32F429_PF8_FUNC_ANALOG 0x5811
+
+#define STM32F429_PF9_FUNC_GPIO 0x5900
+#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906
+#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907
+#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a
+#define STM32F429_PF9_FUNC_FMC_CD 0x590d
+#define STM32F429_PF9_FUNC_EVENTOUT 0x5910
+#define STM32F429_PF9_FUNC_ANALOG 0x5911
+
+#define STM32F429_PF10_FUNC_GPIO 0x5a00
+#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d
+#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e
+#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f
+#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10
+#define STM32F429_PF10_FUNC_ANALOG 0x5a11
+
+#define STM32F429_PF11_FUNC_GPIO 0x5b00
+#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06
+#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d
+#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e
+#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10
+#define STM32F429_PF11_FUNC_ANALOG 0x5b11
+
+#define STM32F429_PF12_FUNC_GPIO 0x5c00
+#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d
+#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10
+#define STM32F429_PF12_FUNC_ANALOG 0x5c11
+
+#define STM32F429_PF13_FUNC_GPIO 0x5d00
+#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d
+#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10
+#define STM32F429_PF13_FUNC_ANALOG 0x5d11
+
+#define STM32F429_PF14_FUNC_GPIO 0x5e00
+#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d
+#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10
+#define STM32F429_PF14_FUNC_ANALOG 0x5e11
+
+#define STM32F429_PF15_FUNC_GPIO 0x5f00
+#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d
+#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10
+#define STM32F429_PF15_FUNC_ANALOG 0x5f11
+
+
+
+#define STM32F429_PG0_FUNC_GPIO 0x6000
+#define STM32F429_PG0_FUNC_FMC_A10 0x600d
+#define STM32F429_PG0_FUNC_EVENTOUT 0x6010
+#define STM32F429_PG0_FUNC_ANALOG 0x6011
+
+#define STM32F429_PG1_FUNC_GPIO 0x6100
+#define STM32F429_PG1_FUNC_FMC_A11 0x610d
+#define STM32F429_PG1_FUNC_EVENTOUT 0x6110
+#define STM32F429_PG1_FUNC_ANALOG 0x6111
+
+#define STM32F429_PG2_FUNC_GPIO 0x6200
+#define STM32F429_PG2_FUNC_FMC_A12 0x620d
+#define STM32F429_PG2_FUNC_EVENTOUT 0x6210
+#define STM32F429_PG2_FUNC_ANALOG 0x6211
+
+#define STM32F429_PG3_FUNC_GPIO 0x6300
+#define STM32F429_PG3_FUNC_FMC_A13 0x630d
+#define STM32F429_PG3_FUNC_EVENTOUT 0x6310
+#define STM32F429_PG3_FUNC_ANALOG 0x6311
+
+#define STM32F429_PG4_FUNC_GPIO 0x6400
+#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d
+#define STM32F429_PG4_FUNC_EVENTOUT 0x6410
+#define STM32F429_PG4_FUNC_ANALOG 0x6411
+
+#define STM32F429_PG5_FUNC_GPIO 0x6500
+#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d
+#define STM32F429_PG5_FUNC_EVENTOUT 0x6510
+#define STM32F429_PG5_FUNC_ANALOG 0x6511
+
+#define STM32F429_PG6_FUNC_GPIO 0x6600
+#define STM32F429_PG6_FUNC_FMC_INT2 0x660d
+#define STM32F429_PG6_FUNC_DCMI_D12 0x660e
+#define STM32F429_PG6_FUNC_LCD_R7 0x660f
+#define STM32F429_PG6_FUNC_EVENTOUT 0x6610
+#define STM32F429_PG6_FUNC_ANALOG 0x6611
+
+#define STM32F429_PG7_FUNC_GPIO 0x6700
+#define STM32F429_PG7_FUNC_USART6_CK 0x6709
+#define STM32F429_PG7_FUNC_FMC_INT3 0x670d
+#define STM32F429_PG7_FUNC_DCMI_D13 0x670e
+#define STM32F429_PG7_FUNC_LCD_CLK 0x670f
+#define STM32F429_PG7_FUNC_EVENTOUT 0x6710
+#define STM32F429_PG7_FUNC_ANALOG 0x6711
+
+#define STM32F429_PG8_FUNC_GPIO 0x6800
+#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806
+#define STM32F429_PG8_FUNC_USART6_RTS 0x6809
+#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c
+#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d
+#define STM32F429_PG8_FUNC_EVENTOUT 0x6810
+#define STM32F429_PG8_FUNC_ANALOG 0x6811
+
+#define STM32F429_PG9_FUNC_GPIO 0x6900
+#define STM32F429_PG9_FUNC_USART6_RX 0x6909
+#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d
+#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e
+#define STM32F429_PG9_FUNC_EVENTOUT 0x6910
+#define STM32F429_PG9_FUNC_ANALOG 0x6911
+
+#define STM32F429_PG10_FUNC_GPIO 0x6a00
+#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a
+#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d
+#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e
+#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f
+#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10
+#define STM32F429_PG10_FUNC_ANALOG 0x6a11
+
+#define STM32F429_PG11_FUNC_GPIO 0x6b00
+#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c
+#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d
+#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e
+#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f
+#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10
+#define STM32F429_PG11_FUNC_ANALOG 0x6b11
+
+#define STM32F429_PG12_FUNC_GPIO 0x6c00
+#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06
+#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09
+#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a
+#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d
+#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f
+#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10
+#define STM32F429_PG12_FUNC_ANALOG 0x6c11
+
+#define STM32F429_PG13_FUNC_GPIO 0x6d00
+#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06
+#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09
+#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c
+#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d
+#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10
+#define STM32F429_PG13_FUNC_ANALOG 0x6d11
+
+#define STM32F429_PG14_FUNC_GPIO 0x6e00
+#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06
+#define STM32F429_PG14_FUNC_USART6_TX 0x6e09
+#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c
+#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d
+#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10
+#define STM32F429_PG14_FUNC_ANALOG 0x6e11
+
+#define STM32F429_PG15_FUNC_GPIO 0x6f00
+#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09
+#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d
+#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e
+#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10
+#define STM32F429_PG15_FUNC_ANALOG 0x6f11
+
+
+
+#define STM32F429_PH0_FUNC_GPIO 0x7000
+#define STM32F429_PH0_FUNC_EVENTOUT 0x7010
+#define STM32F429_PH0_FUNC_ANALOG 0x7011
+
+#define STM32F429_PH1_FUNC_GPIO 0x7100
+#define STM32F429_PH1_FUNC_EVENTOUT 0x7110
+#define STM32F429_PH1_FUNC_ANALOG 0x7111
+
+#define STM32F429_PH2_FUNC_GPIO 0x7200
+#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c
+#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d
+#define STM32F429_PH2_FUNC_LCD_R0 0x720f
+#define STM32F429_PH2_FUNC_EVENTOUT 0x7210
+#define STM32F429_PH2_FUNC_ANALOG 0x7211
+
+#define STM32F429_PH3_FUNC_GPIO 0x7300
+#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c
+#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d
+#define STM32F429_PH3_FUNC_LCD_R1 0x730f
+#define STM32F429_PH3_FUNC_EVENTOUT 0x7310
+#define STM32F429_PH3_FUNC_ANALOG 0x7311
+
+#define STM32F429_PH4_FUNC_GPIO 0x7400
+#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405
+#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b
+#define STM32F429_PH4_FUNC_EVENTOUT 0x7410
+#define STM32F429_PH4_FUNC_ANALOG 0x7411
+
+#define STM32F429_PH5_FUNC_GPIO 0x7500
+#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505
+#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506
+#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d
+#define STM32F429_PH5_FUNC_EVENTOUT 0x7510
+#define STM32F429_PH5_FUNC_ANALOG 0x7511
+
+#define STM32F429_PH6_FUNC_GPIO 0x7600
+#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605
+#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606
+#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a
+#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c
+#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d
+#define STM32F429_PH6_FUNC_DCMI_D8 0x760e
+#define STM32F429_PH6_FUNC_EVENTOUT 0x7610
+#define STM32F429_PH6_FUNC_ANALOG 0x7611
+
+#define STM32F429_PH7_FUNC_GPIO 0x7700
+#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705
+#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706
+#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c
+#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d
+#define STM32F429_PH7_FUNC_DCMI_D9 0x770e
+#define STM32F429_PH7_FUNC_EVENTOUT 0x7710
+#define STM32F429_PH7_FUNC_ANALOG 0x7711
+
+#define STM32F429_PH8_FUNC_GPIO 0x7800
+#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805
+#define STM32F429_PH8_FUNC_FMC_D16 0x780d
+#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e
+#define STM32F429_PH8_FUNC_LCD_R2 0x780f
+#define STM32F429_PH8_FUNC_EVENTOUT 0x7810
+#define STM32F429_PH8_FUNC_ANALOG 0x7811
+
+#define STM32F429_PH9_FUNC_GPIO 0x7900
+#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905
+#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a
+#define STM32F429_PH9_FUNC_FMC_D17 0x790d
+#define STM32F429_PH9_FUNC_DCMI_D0 0x790e
+#define STM32F429_PH9_FUNC_LCD_R3 0x790f
+#define STM32F429_PH9_FUNC_EVENTOUT 0x7910
+#define STM32F429_PH9_FUNC_ANALOG 0x7911
+
+#define STM32F429_PH10_FUNC_GPIO 0x7a00
+#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03
+#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d
+#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e
+#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f
+#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10
+#define STM32F429_PH10_FUNC_ANALOG 0x7a11
+
+#define STM32F429_PH11_FUNC_GPIO 0x7b00
+#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03
+#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d
+#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e
+#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f
+#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10
+#define STM32F429_PH11_FUNC_ANALOG 0x7b11
+
+#define STM32F429_PH12_FUNC_GPIO 0x7c00
+#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03
+#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d
+#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e
+#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f
+#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10
+#define STM32F429_PH12_FUNC_ANALOG 0x7c11
+
+#define STM32F429_PH13_FUNC_GPIO 0x7d00
+#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04
+#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a
+#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d
+#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f
+#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10
+#define STM32F429_PH13_FUNC_ANALOG 0x7d11
+
+#define STM32F429_PH14_FUNC_GPIO 0x7e00
+#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04
+#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d
+#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e
+#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f
+#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10
+#define STM32F429_PH14_FUNC_ANALOG 0x7e11
+
+#define STM32F429_PH15_FUNC_GPIO 0x7f00
+#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04
+#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d
+#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e
+#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f
+#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10
+#define STM32F429_PH15_FUNC_ANALOG 0x7f11
+
+
+
+#define STM32F429_PI0_FUNC_GPIO 0x8000
+#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003
+#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006
+#define STM32F429_PI0_FUNC_FMC_D24 0x800d
+#define STM32F429_PI0_FUNC_DCMI_D13 0x800e
+#define STM32F429_PI0_FUNC_LCD_G5 0x800f
+#define STM32F429_PI0_FUNC_EVENTOUT 0x8010
+#define STM32F429_PI0_FUNC_ANALOG 0x8011
+
+#define STM32F429_PI1_FUNC_GPIO 0x8100
+#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106
+#define STM32F429_PI1_FUNC_FMC_D25 0x810d
+#define STM32F429_PI1_FUNC_DCMI_D8 0x810e
+#define STM32F429_PI1_FUNC_LCD_G6 0x810f
+#define STM32F429_PI1_FUNC_EVENTOUT 0x8110
+#define STM32F429_PI1_FUNC_ANALOG 0x8111
+
+#define STM32F429_PI2_FUNC_GPIO 0x8200
+#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204
+#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206
+#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207
+#define STM32F429_PI2_FUNC_FMC_D26 0x820d
+#define STM32F429_PI2_FUNC_DCMI_D9 0x820e
+#define STM32F429_PI2_FUNC_LCD_G7 0x820f
+#define STM32F429_PI2_FUNC_EVENTOUT 0x8210
+#define STM32F429_PI2_FUNC_ANALOG 0x8211
+
+#define STM32F429_PI3_FUNC_GPIO 0x8300
+#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304
+#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306
+#define STM32F429_PI3_FUNC_FMC_D27 0x830d
+#define STM32F429_PI3_FUNC_DCMI_D10 0x830e
+#define STM32F429_PI3_FUNC_EVENTOUT 0x8310
+#define STM32F429_PI3_FUNC_ANALOG 0x8311
+
+#define STM32F429_PI4_FUNC_GPIO 0x8400
+#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404
+#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d
+#define STM32F429_PI4_FUNC_DCMI_D5 0x840e
+#define STM32F429_PI4_FUNC_LCD_B4 0x840f
+#define STM32F429_PI4_FUNC_EVENTOUT 0x8410
+#define STM32F429_PI4_FUNC_ANALOG 0x8411
+
+#define STM32F429_PI5_FUNC_GPIO 0x8500
+#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504
+#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d
+#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e
+#define STM32F429_PI5_FUNC_LCD_B5 0x850f
+#define STM32F429_PI5_FUNC_EVENTOUT 0x8510
+#define STM32F429_PI5_FUNC_ANALOG 0x8511
+
+#define STM32F429_PI6_FUNC_GPIO 0x8600
+#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604
+#define STM32F429_PI6_FUNC_FMC_D28 0x860d
+#define STM32F429_PI6_FUNC_DCMI_D6 0x860e
+#define STM32F429_PI6_FUNC_LCD_B6 0x860f
+#define STM32F429_PI6_FUNC_EVENTOUT 0x8610
+#define STM32F429_PI6_FUNC_ANALOG 0x8611
+
+#define STM32F429_PI7_FUNC_GPIO 0x8700
+#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704
+#define STM32F429_PI7_FUNC_FMC_D29 0x870d
+#define STM32F429_PI7_FUNC_DCMI_D7 0x870e
+#define STM32F429_PI7_FUNC_LCD_B7 0x870f
+#define STM32F429_PI7_FUNC_EVENTOUT 0x8710
+#define STM32F429_PI7_FUNC_ANALOG 0x8711
+
+#define STM32F429_PI8_FUNC_GPIO 0x8800
+#define STM32F429_PI8_FUNC_EVENTOUT 0x8810
+#define STM32F429_PI8_FUNC_ANALOG 0x8811
+
+#define STM32F429_PI9_FUNC_GPIO 0x8900
+#define STM32F429_PI9_FUNC_CAN1_RX 0x890a
+#define STM32F429_PI9_FUNC_FMC_D30 0x890d
+#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f
+#define STM32F429_PI9_FUNC_EVENTOUT 0x8910
+#define STM32F429_PI9_FUNC_ANALOG 0x8911
+
+#define STM32F429_PI10_FUNC_GPIO 0x8a00
+#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c
+#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d
+#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f
+#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10
+#define STM32F429_PI10_FUNC_ANALOG 0x8a11
+
+#define STM32F429_PI11_FUNC_GPIO 0x8b00
+#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b
+#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10
+#define STM32F429_PI11_FUNC_ANALOG 0x8b11
+
+#define STM32F429_PI12_FUNC_GPIO 0x8c00
+#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f
+#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10
+#define STM32F429_PI12_FUNC_ANALOG 0x8c11
+
+#define STM32F429_PI13_FUNC_GPIO 0x8d00
+#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f
+#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10
+#define STM32F429_PI13_FUNC_ANALOG 0x8d11
+
+#define STM32F429_PI14_FUNC_GPIO 0x8e00
+#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f
+#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10
+#define STM32F429_PI14_FUNC_ANALOG 0x8e11
+
+#define STM32F429_PI15_FUNC_GPIO 0x8f00
+#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f
+#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10
+#define STM32F429_PI15_FUNC_ANALOG 0x8f11
+
+
+
+#define STM32F429_PJ0_FUNC_GPIO 0x9000
+#define STM32F429_PJ0_FUNC_LCD_R1 0x900f
+#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010
+#define STM32F429_PJ0_FUNC_ANALOG 0x9011
+
+#define STM32F429_PJ1_FUNC_GPIO 0x9100
+#define STM32F429_PJ1_FUNC_LCD_R2 0x910f
+#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110
+#define STM32F429_PJ1_FUNC_ANALOG 0x9111
+
+#define STM32F429_PJ2_FUNC_GPIO 0x9200
+#define STM32F429_PJ2_FUNC_LCD_R3 0x920f
+#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210
+#define STM32F429_PJ2_FUNC_ANALOG 0x9211
+
+#define STM32F429_PJ3_FUNC_GPIO 0x9300
+#define STM32F429_PJ3_FUNC_LCD_R4 0x930f
+#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310
+#define STM32F429_PJ3_FUNC_ANALOG 0x9311
+
+#define STM32F429_PJ4_FUNC_GPIO 0x9400
+#define STM32F429_PJ4_FUNC_LCD_R5 0x940f
+#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410
+#define STM32F429_PJ4_FUNC_ANALOG 0x9411
+
+#define STM32F429_PJ5_FUNC_GPIO 0x9500
+#define STM32F429_PJ5_FUNC_LCD_R6 0x950f
+#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510
+#define STM32F429_PJ5_FUNC_ANALOG 0x9511
+
+#define STM32F429_PJ6_FUNC_GPIO 0x9600
+#define STM32F429_PJ6_FUNC_LCD_R7 0x960f
+#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610
+#define STM32F429_PJ6_FUNC_ANALOG 0x9611
+
+#define STM32F429_PJ7_FUNC_GPIO 0x9700
+#define STM32F429_PJ7_FUNC_LCD_G0 0x970f
+#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710
+#define STM32F429_PJ7_FUNC_ANALOG 0x9711
+
+#define STM32F429_PJ8_FUNC_GPIO 0x9800
+#define STM32F429_PJ8_FUNC_LCD_G1 0x980f
+#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810
+#define STM32F429_PJ8_FUNC_ANALOG 0x9811
+
+#define STM32F429_PJ9_FUNC_GPIO 0x9900
+#define STM32F429_PJ9_FUNC_LCD_G2 0x990f
+#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910
+#define STM32F429_PJ9_FUNC_ANALOG 0x9911
+
+#define STM32F429_PJ10_FUNC_GPIO 0x9a00
+#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f
+#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10
+#define STM32F429_PJ10_FUNC_ANALOG 0x9a11
+
+#define STM32F429_PJ11_FUNC_GPIO 0x9b00
+#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f
+#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10
+#define STM32F429_PJ11_FUNC_ANALOG 0x9b11
+
+#define STM32F429_PJ12_FUNC_GPIO 0x9c00
+#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f
+#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10
+#define STM32F429_PJ12_FUNC_ANALOG 0x9c11
+
+#define STM32F429_PJ13_FUNC_GPIO 0x9d00
+#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f
+#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10
+#define STM32F429_PJ13_FUNC_ANALOG 0x9d11
+
+#define STM32F429_PJ14_FUNC_GPIO 0x9e00
+#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f
+#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10
+#define STM32F429_PJ14_FUNC_ANALOG 0x9e11
+
+#define STM32F429_PJ15_FUNC_GPIO 0x9f00
+#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f
+#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10
+#define STM32F429_PJ15_FUNC_ANALOG 0x9f11
+
+
+
+#define STM32F429_PK0_FUNC_GPIO 0xa000
+#define STM32F429_PK0_FUNC_LCD_G5 0xa00f
+#define STM32F429_PK0_FUNC_EVENTOUT 0xa010
+#define STM32F429_PK0_FUNC_ANALOG 0xa011
+
+#define STM32F429_PK1_FUNC_GPIO 0xa100
+#define STM32F429_PK1_FUNC_LCD_G6 0xa10f
+#define STM32F429_PK1_FUNC_EVENTOUT 0xa110
+#define STM32F429_PK1_FUNC_ANALOG 0xa111
+
+#define STM32F429_PK2_FUNC_GPIO 0xa200
+#define STM32F429_PK2_FUNC_LCD_G7 0xa20f
+#define STM32F429_PK2_FUNC_EVENTOUT 0xa210
+#define STM32F429_PK2_FUNC_ANALOG 0xa211
+
+#define STM32F429_PK3_FUNC_GPIO 0xa300
+#define STM32F429_PK3_FUNC_LCD_B4 0xa30f
+#define STM32F429_PK3_FUNC_EVENTOUT 0xa310
+#define STM32F429_PK3_FUNC_ANALOG 0xa311
+
+#define STM32F429_PK4_FUNC_GPIO 0xa400
+#define STM32F429_PK4_FUNC_LCD_B5 0xa40f
+#define STM32F429_PK4_FUNC_EVENTOUT 0xa410
+#define STM32F429_PK4_FUNC_ANALOG 0xa411
+
+#define STM32F429_PK5_FUNC_GPIO 0xa500
+#define STM32F429_PK5_FUNC_LCD_B6 0xa50f
+#define STM32F429_PK5_FUNC_EVENTOUT 0xa510
+#define STM32F429_PK5_FUNC_ANALOG 0xa511
+
+#define STM32F429_PK6_FUNC_GPIO 0xa600
+#define STM32F429_PK6_FUNC_LCD_B7 0xa60f
+#define STM32F429_PK6_FUNC_EVENTOUT 0xa610
+#define STM32F429_PK6_FUNC_ANALOG 0xa611
+
+#define STM32F429_PK7_FUNC_GPIO 0xa700
+#define STM32F429_PK7_FUNC_LCD_DE 0xa70f
+#define STM32F429_PK7_FUNC_EVENTOUT 0xa710
+#define STM32F429_PK7_FUNC_ANALOG 0xa711
+
+#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */
diff --git a/include/dt-bindings/power/r8a7779-sysc.h b/include/dt-bindings/power/r8a7779-sysc.h
new file mode 100644
index 000000000000..183571da507e
--- /dev/null
+++ b/include/dt-bindings/power/r8a7779-sysc.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7779_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7779_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7779_PD_ARM1			 1
+#define R8A7779_PD_ARM2			 2
+#define R8A7779_PD_ARM3			 3
+#define R8A7779_PD_SGX			20
+#define R8A7779_PD_VDP			21
+#define R8A7779_PD_IMP			24
+
+/* Always-on power area */
+#define R8A7779_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7779_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7790-sysc.h b/include/dt-bindings/power/r8a7790-sysc.h
new file mode 100644
index 000000000000..6af4e9929bd0
--- /dev/null
+++ b/include/dt-bindings/power/r8a7790-sysc.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7790_PD_CA15_CPU0		 0
+#define R8A7790_PD_CA15_CPU1		 1
+#define R8A7790_PD_CA15_CPU2		 2
+#define R8A7790_PD_CA15_CPU3		 3
+#define R8A7790_PD_CA7_CPU0		 5
+#define R8A7790_PD_CA7_CPU1		 6
+#define R8A7790_PD_CA7_CPU2		 7
+#define R8A7790_PD_CA7_CPU3		 8
+#define R8A7790_PD_CA15_SCU		12
+#define R8A7790_PD_SH_4A		16
+#define R8A7790_PD_RGX			20
+#define R8A7790_PD_CA7_SCU		21
+#define R8A7790_PD_IMP			24
+
+/* Always-on power area */
+#define R8A7790_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7791-sysc.h b/include/dt-bindings/power/r8a7791-sysc.h
new file mode 100644
index 000000000000..1403baa0514f
--- /dev/null
+++ b/include/dt-bindings/power/r8a7791-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7791_PD_CA15_CPU0		 0
+#define R8A7791_PD_CA15_CPU1		 1
+#define R8A7791_PD_CA15_SCU		12
+#define R8A7791_PD_SH_4A		16
+#define R8A7791_PD_SGX			20
+
+/* Always-on power area */
+#define R8A7791_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7793-sysc.h b/include/dt-bindings/power/r8a7793-sysc.h
new file mode 100644
index 000000000000..b5693df3d830
--- /dev/null
+++ b/include/dt-bindings/power/r8a7793-sysc.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ *
+ * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
+ */
+
+#define R8A7793_PD_CA15_CPU0		 0
+#define R8A7793_PD_CA15_CPU1		 1
+#define R8A7793_PD_CA15_SCU		12
+#define R8A7793_PD_SH_4A		16
+#define R8A7793_PD_SGX			20
+
+/* Always-on power area */
+#define R8A7793_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7794-sysc.h b/include/dt-bindings/power/r8a7794-sysc.h
new file mode 100644
index 000000000000..862241c2d27b
--- /dev/null
+++ b/include/dt-bindings/power/r8a7794-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7794_PD_CA7_CPU0		 5
+#define R8A7794_PD_CA7_CPU1		 6
+#define R8A7794_PD_SH_4A		16
+#define R8A7794_PD_SGX			20
+#define R8A7794_PD_CA7_SCU		21
+
+/* Always-on power area */
+#define R8A7794_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h
new file mode 100644
index 000000000000..ee2e26ba605e
--- /dev/null
+++ b/include/dt-bindings/power/r8a7795-sysc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7795_PD_CA57_CPU0		 0
+#define R8A7795_PD_CA57_CPU1		 1
+#define R8A7795_PD_CA57_CPU2		 2
+#define R8A7795_PD_CA57_CPU3		 3
+#define R8A7795_PD_CA53_CPU0		 5
+#define R8A7795_PD_CA53_CPU1		 6
+#define R8A7795_PD_CA53_CPU2		 7
+#define R8A7795_PD_CA53_CPU3		 8
+#define R8A7795_PD_A3VP			 9
+#define R8A7795_PD_CA57_SCU		12
+#define R8A7795_PD_CR7			13
+#define R8A7795_PD_A3VC			14
+#define R8A7795_PD_3DG_A		17
+#define R8A7795_PD_3DG_B		18
+#define R8A7795_PD_3DG_C		19
+#define R8A7795_PD_3DG_D		20
+#define R8A7795_PD_CA53_SCU		21
+#define R8A7795_PD_3DG_E		22
+#define R8A7795_PD_A3IR			24
+#define R8A7795_PD_A2VC0		25
+#define R8A7795_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A7795_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
diff --git a/include/dt-bindings/power/rk3368-power.h b/include/dt-bindings/power/rk3368-power.h
new file mode 100644
index 000000000000..93633d57ed84
--- /dev/null
+++ b/include/dt-bindings/power/rk3368-power.h
@@ -0,0 +1,28 @@
+#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__
+#define __DT_BINDINGS_POWER_RK3368_POWER_H__
+
+/* VD_CORE */
+#define RK3368_PD_A53_L0	0
+#define RK3368_PD_A53_L1	1
+#define RK3368_PD_A53_L2	2
+#define RK3368_PD_A53_L3	3
+#define RK3368_PD_SCU_L		4
+#define RK3368_PD_A53_B0	5
+#define RK3368_PD_A53_B1	6
+#define RK3368_PD_A53_B2	7
+#define RK3368_PD_A53_B3	8
+#define RK3368_PD_SCU_B		9
+
+/* VD_LOGIC */
+#define RK3368_PD_BUS		10
+#define RK3368_PD_PERI		11
+#define RK3368_PD_VIO		12
+#define RK3368_PD_ALIVE		13
+#define RK3368_PD_VIDEO		14
+#define RK3368_PD_GPU_0		15
+#define RK3368_PD_GPU_1		16
+
+/* VD_PMU */
+#define RK3368_PD_PMU		17
+
+#endif
diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h
new file mode 100644
index 000000000000..168b3bfbd6f5
--- /dev/null
+++ b/include/dt-bindings/power/rk3399-power.h
@@ -0,0 +1,53 @@
+#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
+#define __DT_BINDINGS_POWER_RK3399_POWER_H__
+
+/* VD_CORE_L */
+#define RK3399_PD_A53_L0	0
+#define RK3399_PD_A53_L1	1
+#define RK3399_PD_A53_L2	2
+#define RK3399_PD_A53_L3	3
+#define RK3399_PD_SCU_L		4
+
+/* VD_CORE_B */
+#define RK3399_PD_A72_B0	5
+#define RK3399_PD_A72_B1	6
+#define RK3399_PD_SCU_B		7
+
+/* VD_LOGIC */
+#define RK3399_PD_TCPD0		8
+#define RK3399_PD_TCPD1		9
+#define RK3399_PD_CCI		10
+#define RK3399_PD_CCI0		11
+#define RK3399_PD_CCI1		12
+#define RK3399_PD_PERILP	13
+#define RK3399_PD_PERIHP	14
+#define RK3399_PD_VIO		15
+#define RK3399_PD_VO		16
+#define RK3399_PD_VOPB		17
+#define RK3399_PD_VOPL		18
+#define RK3399_PD_ISP0		19
+#define RK3399_PD_ISP1		20
+#define RK3399_PD_HDCP		21
+#define RK3399_PD_GMAC		22
+#define RK3399_PD_EMMC		23
+#define RK3399_PD_USB3		24
+#define RK3399_PD_EDP		25
+#define RK3399_PD_GIC		26
+#define RK3399_PD_SD		27
+#define RK3399_PD_SDIOAUDIO	28
+#define RK3399_PD_ALIVE		29
+
+/* VD_CENTER */
+#define RK3399_PD_CENTER	30
+#define RK3399_PD_VCODEC	31
+#define RK3399_PD_VDU		32
+#define RK3399_PD_RGA		33
+#define RK3399_PD_IEP		34
+
+/* VD_GPU */
+#define RK3399_PD_GPU		35
+
+/* VD_PMU */
+#define RK3399_PD_PMU		36
+
+#endif
diff --git a/include/dt-bindings/reset/pistachio-resets.h b/include/dt-bindings/reset/pistachio-resets.h
new file mode 100644
index 000000000000..60a189b1faef
--- /dev/null
+++ b/include/dt-bindings/reset/pistachio-resets.h
@@ -0,0 +1,36 @@
+/*
+ * This header provides constants for the reset controller
+ * present in the Pistachio SoC
+ */
+
+#ifndef _PISTACHIO_RESETS_H
+#define _PISTACHIO_RESETS_H
+
+#define PISTACHIO_RESET_I2C0		0
+#define PISTACHIO_RESET_I2C1		1
+#define PISTACHIO_RESET_I2C2		2
+#define PISTACHIO_RESET_I2C3		3
+#define PISTACHIO_RESET_I2S_IN		4
+#define PISTACHIO_RESET_PRL_OUT		5
+#define PISTACHIO_RESET_SPDIF_OUT	6
+#define PISTACHIO_RESET_SPI		7
+#define PISTACHIO_RESET_PWM_PDM		8
+#define PISTACHIO_RESET_UART0		9
+#define PISTACHIO_RESET_UART1		10
+#define PISTACHIO_RESET_QSPI		11
+#define PISTACHIO_RESET_MDC		12
+#define PISTACHIO_RESET_SDHOST		13
+#define PISTACHIO_RESET_ETHERNET	14
+#define PISTACHIO_RESET_IR		15
+#define PISTACHIO_RESET_HASH		16
+#define PISTACHIO_RESET_TIMER		17
+#define PISTACHIO_RESET_I2S_OUT		18
+#define PISTACHIO_RESET_SPDIF_IN	19
+#define PISTACHIO_RESET_EVT		20
+#define PISTACHIO_RESET_USB_H		21
+#define PISTACHIO_RESET_USB_PR		22
+#define PISTACHIO_RESET_USB_PHY_PR	23
+#define PISTACHIO_RESET_USB_PHY_PON	24
+#define PISTACHIO_RESET_MAX		24
+
+#endif
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
index 85aaf66690f9..729ab9fc325e 100644
--- a/include/dt-bindings/thermal/tegra124-soctherm.h
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -9,5 +9,6 @@
 #define TEGRA124_SOCTHERM_SENSOR_MEM 1
 #define TEGRA124_SOCTHERM_SENSOR_GPU 2
 #define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+#define TEGRA124_SOCTHERM_SENSOR_NUM 4
 
 #endif