diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 | 
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 | 
| commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
| tree | 4def12e759965de927d963ac65840d663ef9d1ea /include/llvm/CodeGen/MachineInstr.h | |
| parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
Notes
Diffstat (limited to 'include/llvm/CodeGen/MachineInstr.h')
| -rw-r--r-- | include/llvm/CodeGen/MachineInstr.h | 61 | 
1 files changed, 44 insertions, 17 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 05c9a9e0b079..8f1cb9b6f659 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -16,16 +16,13 @@  #ifndef LLVM_CODEGEN_MACHINEINSTR_H  #define LLVM_CODEGEN_MACHINEINSTR_H -#include "llvm/ADT/ArrayRef.h"  #include "llvm/ADT/DenseMapInfo.h"  #include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/StringRef.h"  #include "llvm/ADT/ilist.h"  #include "llvm/ADT/ilist_node.h"  #include "llvm/ADT/iterator_range.h"  #include "llvm/Analysis/AliasAnalysis.h"  #include "llvm/CodeGen/MachineOperand.h" -#include "llvm/IR/DebugInfo.h"  #include "llvm/IR/DebugLoc.h"  #include "llvm/IR/InlineAsm.h"  #include "llvm/MC/MCInstrDesc.h" @@ -34,10 +31,17 @@  namespace llvm { +class StringRef; +template <typename T> class ArrayRef;  template <typename T> class SmallVectorImpl; +class DILocalVariable; +class DIExpression;  class TargetInstrInfo;  class TargetRegisterClass;  class TargetRegisterInfo; +#ifdef LLVM_BUILD_GLOBAL_ISEL +class Type; +#endif  class MachineFunction;  class MachineMemOperand; @@ -102,6 +106,13 @@ private:    DebugLoc debugLoc;                    // Source line information. +#ifdef LLVM_BUILD_GLOBAL_ISEL +  /// Type of the instruction in case of a generic opcode. +  /// \invariant This must be nullptr is getOpcode() is not +  /// in the range of generic opcodes. +  Type *Ty; +#endif +    MachineInstr(const MachineInstr&) = delete;    void operator=(const MachineInstr&) = delete;    // Use MachineFunction::DeleteMachineInstr() instead. @@ -176,6 +187,11 @@ public:      Flags &= ~((uint8_t)Flag);    } +  /// Set the type of the instruction. +  /// \pre getOpcode() is in the range of the generic opcodes. +  void setType(Type *Ty); +  Type *getType() const; +    /// Return true if MI is in a bundle (but not the first MI in a bundle).    ///    /// A bundle looks like this before it's finalized: @@ -248,17 +264,11 @@ public:    /// Return the debug variable referenced by    /// this DBG_VALUE instruction. -  const DILocalVariable *getDebugVariable() const { -    assert(isDebugValue() && "not a DBG_VALUE"); -    return cast<DILocalVariable>(getOperand(2).getMetadata()); -  } +  const DILocalVariable *getDebugVariable() const;    /// Return the complex address expression referenced by    /// this DBG_VALUE instruction. -  const DIExpression *getDebugExpression() const { -    assert(isDebugValue() && "not a DBG_VALUE"); -    return cast<DIExpression>(getOperand(3).getMetadata()); -  } +  const DIExpression *getDebugExpression() const;    /// Emit an error referring to the source location of this instruction.    /// This should only be used for inline assembly that is somehow @@ -343,6 +353,14 @@ public:      return make_range(operands_begin() + getDesc().getNumDefs(),                        operands_end());    } +  iterator_range<mop_iterator> explicit_uses() { +    return make_range(operands_begin() + getDesc().getNumDefs(), +                      operands_begin() + getNumExplicitOperands() ); +  } +  iterator_range<const_mop_iterator> explicit_uses() const { +    return make_range(operands_begin() + getDesc().getNumDefs(), +                      operands_begin() + getNumExplicitOperands() ); +  }    /// Returns the number of the operand iterator \p I points to.    unsigned getOperandNo(const_mop_iterator I) const { @@ -508,6 +526,11 @@ public:    /// Convergent instructions can not be made control-dependent on any    /// additional values.    bool isConvergent(QueryType Type = AnyInBundle) const { +    if (isInlineAsm()) { +      unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); +      if (ExtraInfo & InlineAsm::Extra_IsConvergent) +        return true; +    }      return hasProperty(MCID::Convergent, Type);    } @@ -713,7 +736,7 @@ public:    /// Return true if this instruction is identical to (same    /// opcode and same operands as) the specified instruction. -  bool isIdenticalTo(const MachineInstr *Other, +  bool isIdenticalTo(const MachineInstr &Other,                       MICheckType Check = CheckDefs) const;    /// Unlink 'this' from the containing basic block, and return it without @@ -899,6 +922,10 @@ public:      return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;    } +  /// Returns true if the MachineInstr has an implicit-use operand of exactly +  /// the given register (not considering sub/super-registers). +  bool hasRegisterImplicitUseOperand(unsigned Reg) const; +    /// Returns the operand index that is a use of the specific register or -1    /// if it is not found. It further tightens the search criteria to a use    /// that kills the register if isKill is true. @@ -1054,8 +1081,8 @@ public:                           const TargetRegisterInfo *RegInfo,                           bool AddIfNotFound = false); -  /// Clear all kill flags affecting Reg.  If RegInfo is -  /// provided, this includes super-register kills. +  /// Clear all kill flags affecting Reg.  If RegInfo is provided, this includes +  /// all aliasing registers.    void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);    /// We have determined MI defined a register without a use. @@ -1125,7 +1152,7 @@ public:    /// Copy implicit register operands from specified    /// instruction to this instruction. -  void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI); +  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);    //    // Debugging support @@ -1168,7 +1195,7 @@ public:      assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");    } -  /// Erase an operand  from an instruction, leaving it with one +  /// Erase an operand from an instruction, leaving it with one    /// fewer operand than it started with.    void RemoveOperand(unsigned i); @@ -1268,7 +1295,7 @@ struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {      if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||          LHS == getEmptyKey() || LHS == getTombstoneKey())        return LHS == RHS; -    return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs); +    return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);    }  };  | 
