diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-17 20:22:39 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-17 20:22:39 +0000 |
| commit | 7af96fb3afd6725a2824a0a5ca5dad34e5e0b056 (patch) | |
| tree | 6661ffbabf869009597684462f5a3df3beccc952 /lib/CodeGen/TargetRegisterInfo.cpp | |
| parent | 6b3f41ed88e8e440e11a4fbf20b6600529f80049 (diff) | |
Notes
Diffstat (limited to 'lib/CodeGen/TargetRegisterInfo.cpp')
| -rw-r--r-- | lib/CodeGen/TargetRegisterInfo.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/CodeGen/TargetRegisterInfo.cpp b/lib/CodeGen/TargetRegisterInfo.cpp index f6e4c17d514c..41ec082a24cf 100644 --- a/lib/CodeGen/TargetRegisterInfo.cpp +++ b/lib/CodeGen/TargetRegisterInfo.cpp @@ -50,8 +50,7 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef<MCPhysReg> Exceptions) const { // Check that all super registers of reserved regs are reserved as well. BitVector Checked(getNumRegs()); - for (int Reg = RegisterSet.find_first(); Reg>=0; - Reg = RegisterSet.find_next(Reg)) { + for (unsigned Reg : RegisterSet.set_bits()) { if (Checked[Reg]) continue; for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { |