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| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-16 19:46:52 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-16 19:46:52 +0000 |
| commit | 6b3f41ed88e8e440e11a4fbf20b6600529f80049 (patch) | |
| tree | 928b056f24a634d628c80238dbbf10d41b1a71d5 /lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | |
| parent | c46e6a5940c50058e00c0c5f9123fd82e338d29a (diff) | |
| download | src-test2-e60cb5ab119b9a563b017aa95a500a9455152421.tar.gz src-test2-e60cb5ab119b9a563b017aa95a500a9455152421.zip | |
Diffstat (limited to 'lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 8867ed689a31..a7eac080f885 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -127,9 +127,9 @@ bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const { .add(I.getOperand(1)) .add(I.getOperand(0)) .addImm(0) - .addImm(0) .addImm(0); + // Now that we selected an opcode, we need to constrain the register // operands to use appropriate classes. bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI); @@ -393,7 +393,6 @@ bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const { .add(I.getOperand(0)) .addReg(PtrReg) .addImm(0) - .addImm(0) .addImm(0); bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI); |