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authorDimitry Andric <dim@FreeBSD.org>2010-10-07 16:32:35 +0000
committerDimitry Andric <dim@FreeBSD.org>2010-10-07 16:32:35 +0000
commit49011b52fcba02a6051957b84705159f52fae4e4 (patch)
tree99654a7bec5100d4946dd9006e41d4718e0f14bd /lib/Target/ARM/ARMBaseInstrInfo.cpp
parentd39c594d39df7f283c2fb8a704a3f31c501180d9 (diff)
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.cpp')
-rw-r--r--lib/Target/ARM/ARMBaseInstrInfo.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 3a8bebe0dd24..e4f10f93fb74 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1389,7 +1389,8 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
// Check that CPSR isn't set between the comparison instruction and the one we
// want to change.
- MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
+ MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
+ B = MI->getParent()->begin();
--I;
for (; I != E; --I) {
const MachineInstr &Instr = *I;
@@ -1403,6 +1404,10 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
if (MO.getReg() == ARM::CPSR)
return false;
}
+
+ if (I == B)
+ // The 'and' is below the comparison instruction.
+ return false;
}
// Set the "zero" bit in CPSR.