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authorEd Schouten <ed@FreeBSD.org>2009-06-23 14:50:01 +0000
committerEd Schouten <ed@FreeBSD.org>2009-06-23 14:50:01 +0000
commit0408e1d309a743aca4ed4592cf2c712a71537901 (patch)
tree6be075b410677415707e0987e3a49123130cef22 /lib/Target/ARM/ARMInstrInfo.cpp
parentb2f21fb044b6b5c52cff6227f9f79ca4ed42b18f (diff)
Notes
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.cpp')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index d19fb8eea87f..e8da9276243f 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -59,6 +59,8 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
return false;
case ARM::FCPYS:
case ARM::FCPYD:
+ case ARM::VMOVD:
+ case ARM::VMOVQ:
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
return true;
@@ -528,6 +530,8 @@ bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
else if (DestRC == ARM::DPRRegisterClass)
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
.addReg(SrcReg));
+ else if (DestRC == ARM::QPRRegisterClass)
+ BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
else
return false;
@@ -844,6 +848,10 @@ canFoldMemoryOperand(const MachineInstr *MI,
case ARM::FCPYS:
case ARM::FCPYD:
return true;
+
+ case ARM::VMOVD:
+ case ARM::VMOVQ:
+ return false; // FIXME
}
return false;