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authorRoman Divacky <rdivacky@FreeBSD.org>2010-04-03 07:51:10 +0000
committerRoman Divacky <rdivacky@FreeBSD.org>2010-04-03 07:51:10 +0000
commitb5efedaf2ab20d844d5a21cdef76b55acbf4f01c (patch)
treeba3309de92b14839b2ca6ca0c6d3b39714f95d4c /lib/Target/Alpha/AlphaISelLowering.cpp
parent104bd8179fb5f6551c65c94ebcd0a4918b060189 (diff)
Notes
Diffstat (limited to 'lib/Target/Alpha/AlphaISelLowering.cpp')
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 5d8310ec840b..94c6f80c0361 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -471,8 +471,7 @@ AlphaTargetLowering::LowerReturn(SDValue Chain,
SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr,
- DebugLoc::getUnknownLoc(),
- MVT::i64),
+ DebugLoc(), MVT::i64),
SDValue());
switch (Outs.size()) {
default:
@@ -740,8 +739,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SA2, NULL, 0, MVT::i32, false, false, 0);
}
case ISD::RETURNADDR:
- return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
- MVT::i64);
+ return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc(), MVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
}