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authorDimitry Andric <dim@FreeBSD.org>2017-06-10 13:44:06 +0000
committerDimitry Andric <dim@FreeBSD.org>2017-06-10 13:44:06 +0000
commit7ab83427af0f77b59941ceba41d509d7d097b065 (patch)
treecc41c05b1db454e3d802f34df75e636ee922ad87 /lib/Target/Hexagon/HexagonGenMux.cpp
parentd288ef4c1788d3a951a7558c68312c2d320612b1 (diff)
Diffstat (limited to 'lib/Target/Hexagon/HexagonGenMux.cpp')
-rw-r--r--lib/Target/Hexagon/HexagonGenMux.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/Hexagon/HexagonGenMux.cpp b/lib/Target/Hexagon/HexagonGenMux.cpp
index 85222944c77c..3c37d9ebb0eb 100644
--- a/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -40,8 +40,8 @@
#include "llvm/Pass.h"
#include "llvm/Support/MathExtras.h"
#include <algorithm>
-#include <limits>
#include <iterator>
+#include <limits>
#include <utility>
using namespace llvm;
@@ -235,8 +235,11 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
unsigned DR = MI->getOperand(0).getReg();
if (isRegPair(DR))
continue;
+ MachineOperand &PredOp = MI->getOperand(1);
+ if (PredOp.isUndef())
+ continue;
- unsigned PR = MI->getOperand(1).getReg();
+ unsigned PR = PredOp.getReg();
unsigned Idx = I2X.lookup(MI);
CondsetMap::iterator F = CM.find(DR);
bool IfTrue = HII->isPredicatedTrue(Opc);