diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2015-01-18 16:17:27 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-01-18 16:17:27 +0000 |
| commit | 67c32a98315f785a9ec9d531c1f571a0196c7463 (patch) | |
| tree | 4abb9cbeecc7901726dd0b4a37369596c852e9ef /lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp | |
| parent | 9f61947910e6ab40de38e6b4034751ef1513200f (diff) | |
Diffstat (limited to 'lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp b/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp index 9601090af469..a304e655f0b1 100644 --- a/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp +++ b/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp @@ -80,7 +80,7 @@ char HexagonSplitTFRCondSets::ID = 0; bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) { - const TargetInstrInfo *TII = QTM.getInstrInfo(); + const TargetInstrInfo *TII = QTM.getSubtargetImpl()->getInstrInfo(); // Loop over all of the basic blocks. for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end(); @@ -92,21 +92,19 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) { MachineInstr *MI = MII; int Opc1, Opc2; switch(MI->getOpcode()) { - case Hexagon::TFR_condset_rr: case Hexagon::TFR_condset_rr_f: case Hexagon::TFR_condset_rr64_f: { int DestReg = MI->getOperand(0).getReg(); int SrcReg1 = MI->getOperand(2).getReg(); int SrcReg2 = MI->getOperand(3).getReg(); - if (MI->getOpcode() == Hexagon::TFR_condset_rr || - MI->getOpcode() == Hexagon::TFR_condset_rr_f) { - Opc1 = Hexagon::TFR_cPt; - Opc2 = Hexagon::TFR_cNotPt; + if (MI->getOpcode() == Hexagon::TFR_condset_rr_f) { + Opc1 = Hexagon::A2_tfrt; + Opc2 = Hexagon::A2_tfrf; } else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { - Opc1 = Hexagon::TFR64_cPt; - Opc2 = Hexagon::TFR64_cNotPt; + Opc1 = Hexagon::A2_tfrpt; + Opc2 = Hexagon::A2_tfrpf; } // Minor optimization: do not emit the predicated copy if the source @@ -132,12 +130,12 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) { // is the same register. if (DestReg != SrcReg1) { BuildMI(*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::TFR_cPt), DestReg). + TII->get(Hexagon::A2_tfrt), DestReg). addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); } if (MI->getOpcode() == Hexagon::TFR_condset_ri ) { BuildMI(*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::TFRI_cNotPt), DestReg). + TII->get(Hexagon::C2_cmoveif), DestReg). addReg(MI->getOperand(1).getReg()). addImm(MI->getOperand(3).getImm()); } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) { @@ -158,7 +156,7 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) { if (MI->getOpcode() == Hexagon::TFR_condset_ir ) { BuildMI(*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::TFRI_cPt), DestReg). + TII->get(Hexagon::C2_cmoveit), DestReg). addReg(MI->getOperand(1).getReg()). addImm(MI->getOperand(2).getImm()); } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) { @@ -172,7 +170,7 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) { // the destination is the same register. if (DestReg != SrcReg2) { BuildMI(*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::TFR_cNotPt), DestReg). + TII->get(Hexagon::A2_tfrf), DestReg). addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); } MII = MBB->erase(MI); @@ -188,10 +186,10 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) { int Immed1 = MI->getOperand(2).getImm(); int Immed2 = MI->getOperand(3).getImm(); BuildMI(*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::TFRI_cPt), + TII->get(Hexagon::C2_cmoveit), DestReg).addReg(SrcReg1).addImm(Immed1); BuildMI(*MBB, MII, MI->getDebugLoc(), - TII->get(Hexagon::TFRI_cNotPt), + TII->get(Hexagon::C2_cmoveif), DestReg).addReg(SrcReg1).addImm(Immed2); } else if (MI->getOpcode() == Hexagon::TFR_condset_ii_f ) { BuildMI(*MBB, MII, MI->getDebugLoc(), |