diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
| commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
| tree | 4def12e759965de927d963ac65840d663ef9d1ea /lib/Target/PowerPC/PPCTargetMachine.h | |
| parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
Notes
Diffstat (limited to 'lib/Target/PowerPC/PPCTargetMachine.h')
| -rw-r--r-- | lib/Target/PowerPC/PPCTargetMachine.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index 6496339519a1..59b4f1e30c0e 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -21,7 +21,7 @@ namespace llvm { -/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets. +/// Common code between 32-bit and 64-bit PowerPC targets. /// class PPCTargetMachine : public LLVMTargetMachine { public: @@ -35,8 +35,9 @@ private: public: PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, - StringRef FS, const TargetOptions &Options, Reloc::Model RM, - CodeModel::Model CM, CodeGenOpt::Level OL); + StringRef FS, const TargetOptions &Options, + Optional<Reloc::Model> RM, CodeModel::Model CM, + CodeGenOpt::Level OL); ~PPCTargetMachine() override; @@ -57,25 +58,25 @@ public: }; }; -/// PPC32TargetMachine - PowerPC 32-bit target machine. +/// PowerPC 32-bit target machine. /// class PPC32TargetMachine : public PPCTargetMachine { virtual void anchor(); public: PPC32TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, CodeModel::Model CM, CodeGenOpt::Level OL); }; -/// PPC64TargetMachine - PowerPC 64-bit target machine. +/// PowerPC 64-bit target machine. /// class PPC64TargetMachine : public PPCTargetMachine { virtual void anchor(); public: PPC64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, CodeModel::Model CM, CodeGenOpt::Level OL); }; |
