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author | Dimitry Andric <dim@FreeBSD.org> | 2013-12-22 00:04:03 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2013-12-22 00:04:03 +0000 |
commit | f8af5cf600354830d4ccf59732403f0f073eccb9 (patch) | |
tree | 2ba0398b4c42ad4f55561327538044fd2c925a8b /lib/Target/R600/AMDGPURegisterInfo.cpp | |
parent | 59d6cff90eecf31cb3dd860c4e786674cfdd42eb (diff) | |
download | src-test2-f8af5cf600354830d4ccf59732403f0f073eccb9.tar.gz src-test2-f8af5cf600354830d4ccf59732403f0f073eccb9.zip |
Notes
Diffstat (limited to 'lib/Target/R600/AMDGPURegisterInfo.cpp')
-rw-r--r-- | lib/Target/R600/AMDGPURegisterInfo.cpp | 38 |
1 files changed, 15 insertions, 23 deletions
diff --git a/lib/Target/R600/AMDGPURegisterInfo.cpp b/lib/Target/R600/AMDGPURegisterInfo.cpp index fe994d2d05a1..47617a72990d 100644 --- a/lib/Target/R600/AMDGPURegisterInfo.cpp +++ b/lib/Target/R600/AMDGPURegisterInfo.cpp @@ -17,11 +17,9 @@ using namespace llvm; -AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm, - const TargetInstrInfo &tii) +AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm) : AMDGPUGenRegisterInfo(0), - TM(tm), - TII(tii) + TM(tm) { } //===----------------------------------------------------------------------===// @@ -48,27 +46,21 @@ unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const { return 0; } +unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const { + static const unsigned SubRegs[] = { + AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, + AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, + AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, + AMDGPU::sub15 + }; + + assert (Channel < array_lengthof(SubRegs)); + return SubRegs[Channel]; +} + unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const { - switch(IndirectIndex) { - case 0: return AMDGPU::sub0; - case 1: return AMDGPU::sub1; - case 2: return AMDGPU::sub2; - case 3: return AMDGPU::sub3; - case 4: return AMDGPU::sub4; - case 5: return AMDGPU::sub5; - case 6: return AMDGPU::sub6; - case 7: return AMDGPU::sub7; - case 8: return AMDGPU::sub8; - case 9: return AMDGPU::sub9; - case 10: return AMDGPU::sub10; - case 11: return AMDGPU::sub11; - case 12: return AMDGPU::sub12; - case 13: return AMDGPU::sub13; - case 14: return AMDGPU::sub14; - case 15: return AMDGPU::sub15; - default: llvm_unreachable("indirect index out of range"); - } + return getSubRegFromChannel(IndirectIndex); } #define GET_REGINFO_TARGET_DESC |