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author | Dimitry Andric <dim@FreeBSD.org> | 2019-08-20 20:50:12 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2019-08-20 20:50:12 +0000 |
commit | e6d1592492a3a379186bfb02bd0f4eda0669c0d5 (patch) | |
tree | 599ab169a01f1c86eda9adc774edaedde2f2db5b /lib/Target/RISCV/Disassembler | |
parent | 1a56a5ead7a2e84bee8240f5f6b033b5f1707154 (diff) | |
download | src-test2-e6d1592492a3a379186bfb02bd0f4eda0669c0d5.tar.gz src-test2-e6d1592492a3a379186bfb02bd0f4eda0669c0d5.zip |
Notes
Diffstat (limited to 'lib/Target/RISCV/Disassembler')
-rw-r--r-- | lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index eafa09d56315..36200c03f703 100644 --- a/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -1,9 +1,8 @@ //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -12,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/RISCVMCTargetDesc.h" +#include "TargetInfo/RISCVTargetInfo.h" #include "Utils/RISCVBaseInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" @@ -70,7 +70,13 @@ static const unsigned GPRDecoderTable[] = { static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - if (RegNo > sizeof(GPRDecoderTable)) + const FeatureBitset &FeatureBits = + static_cast<const MCDisassembler *>(Decoder) + ->getSubtargetInfo() + .getFeatureBits(); + bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; + + if (RegNo > array_lengthof(GPRDecoderTable) || (IsRV32E && RegNo > 15)) return MCDisassembler::Fail; // We must define our own mapping from RegNo to register identifier. @@ -95,7 +101,7 @@ static const unsigned FPR32DecoderTable[] = { static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - if (RegNo > sizeof(FPR32DecoderTable)) + if (RegNo > array_lengthof(FPR32DecoderTable)) return MCDisassembler::Fail; // We must define our own mapping from RegNo to register identifier. @@ -131,7 +137,7 @@ static const unsigned FPR64DecoderTable[] = { static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { - if (RegNo > sizeof(FPR64DecoderTable)) + if (RegNo > array_lengthof(FPR64DecoderTable)) return MCDisassembler::Fail; // We must define our own mapping from RegNo to register identifier. |