vendor/llvm/llvm-trunk-r321017

1 files changed, 12 insertions, 14 deletions

diff --git a/lib/Target/X86/X86InstrExtension.td b/lib/Target/X86/X86InstrExtension.td
index af43d9f53325..2a8ab0069b1e 100644
--- a/lib/Target/X86/X86InstrExtension.td
+++ b/lib/Target/X86/X86InstrExtension.td
@@ -12,32 +12,30 @@
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0 in {
-  let Defs = [AX], Uses = [AL] in
+  let Defs = [AX], Uses = [AL] in // AX = signext(AL)
   def CBW : I<0x98, RawFrm, (outs), (ins),
-              "{cbtw|cbw}", [], IIC_CBW>, OpSize16;  // AX = signext(AL)
-  let Defs = [EAX], Uses = [AX] in
+              "{cbtw|cbw}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+  let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
   def CWDE : I<0x98, RawFrm, (outs), (ins),
-              "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
+              "{cwtl|cwde}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
 
-  let Defs = [AX,DX], Uses = [AX] in
+  let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
   def CWD : I<0x99, RawFrm, (outs), (ins),
-              "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
-  let Defs = [EAX,EDX], Uses = [EAX] in
+              "{cwtd|cwd}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+  let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
   def CDQ : I<0x99, RawFrm, (outs), (ins),
-              "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
+              "{cltd|cdq}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
 
 
-  let Defs = [RAX], Uses = [EAX] in
+  let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
   def CDQE : RI<0x98, RawFrm, (outs), (ins),
-               "{cltq|cdqe}", [], IIC_CBW>;     // RAX = signext(EAX)
+               "{cltq|cdqe}", [], IIC_CBW>, Sched<[WriteALU]>;
 
-  let Defs = [RAX,RDX], Uses = [RAX] in
+  let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
   def CQO  : RI<0x99, RawFrm, (outs), (ins),
-                "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX)
+                "{cqto|cqo}", [], IIC_CBW>, Sched<[WriteALU]>;
 }
 
-
-
 // Sign/Zero extenders
 let hasSideEffects = 0 in {
 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),