diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-12-18 20:12:36 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-12-18 20:12:36 +0000 |
| commit | ef5d0b5e97ec8e6fa395d377b09aa7755e345b4f (patch) | |
| tree | 27916256fdeeb57d10d2f3d6948be5d71a703215 /packages/Python/lldbsuite/test/functionalities/register | |
| parent | 76e0736e7fcfeb179779e49c05604464b1ccd704 (diff) | |
Notes
Diffstat (limited to 'packages/Python/lldbsuite/test/functionalities/register')
| -rw-r--r-- | packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py | 55 |
1 files changed, 45 insertions, 10 deletions
diff --git a/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py b/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py index fe6ce2c25a3e..83cc48847c99 100644 --- a/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py +++ b/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py @@ -45,7 +45,7 @@ class RegisterCommandsTestCase(TestBase): self.runCmd("register read xmm0") self.runCmd("register read ymm15") # may be available self.runCmd("register read bnd0") # may be available - elif self.getArchitecture() in ['arm']: + elif self.getArchitecture() in ['arm', 'armv7', 'armv7k', 'arm64']: self.runCmd("register read s0") self.runCmd("register read q15") # may be available @@ -84,7 +84,10 @@ class RegisterCommandsTestCase(TestBase): if self.getArchitecture() in ['amd64', 'i386', 'x86_64']: gpr = "eax" vector = "xmm0" - elif self.getArchitecture() in ['arm']: + elif self.getArchitecture() in ['arm64', 'aarch64']: + gpr = "w0" + vector = "v0" + elif self.getArchitecture() in ['arm', 'armv7', 'armv7k']: gpr = "r0" vector = "q0" @@ -269,14 +272,18 @@ class RegisterCommandsTestCase(TestBase): target = self.dbg.CreateTarget(exe) self.assertTrue(target, VALID_TARGET) - lldbutil.run_break_set_by_symbol( - self, "main", num_expected_locations=-1) - - # Launch the process, and do not stop at the entry point. - process = target.LaunchSimple( - None, None, self.get_process_working_directory()) + # Launch the process, stop at the entry point. + error = lldb.SBError() + process = target.Launch( + lldb.SBListener(), + None, None, # argv, envp + None, None, None, # stdin/out/err + self.get_process_working_directory(), + 0, # launch flags + True, # stop at entry + error) + self.assertTrue(error.Success(), "Launch succeeds. Error is :" + str(error)) - process = target.GetProcess() self.assertTrue( process.GetState() == lldb.eStateStopped, PROCESS_STOPPED) @@ -317,7 +324,35 @@ class RegisterCommandsTestCase(TestBase): ("xmm15", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}", False)) - elif self.getArchitecture() in ['arm']: + elif self.getArchitecture() in ['arm64', 'aarch64']: + reg_list = [ + # reg value + # must-have + ("fpsr", "0xfbf79f9f", True), + ("s0", "1.25", True), + ("s31", "0.75", True), + ("d1", "123", True), + ("d17", "987", False), + ("v1", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}", True), + ("v14", + "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}", + False), + ] + elif self.getArchitecture() in ['armv7'] and self.platformIsDarwin(): + reg_list = [ + # reg value + # must-have + ("fpsr", "0xfbf79f9f", True), + ("s0", "1.25", True), + ("s31", "0.75", True), + ("d1", "123", True), + ("d17", "987", False), + ("q1", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}", True), + ("q14", + "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}", + False), + ] + elif self.getArchitecture() in ['arm', 'armv7k']: reg_list = [ # reg value # must-have |