4 files changed, 38 insertions, 82 deletions

diff --git a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
index 85bc4a61c9d4..6323889c2e09 100644
--- a/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
+++ b/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
@@ -1,9 +1,8 @@
 //===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -37,11 +36,9 @@ using namespace lldb_private;
 
 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
 
-//----------------------------------------------------------------------
 //
 // ITSession implementation
 //
-//----------------------------------------------------------------------
 
 static bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo &reg_info) {
   ::memset(&reg_info, 0, sizeof(RegisterInfo));
@@ -710,11 +707,9 @@ uint32_t ITSession::GetCond() {
 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
 #define VFPv2v3 (VFPv2 | VFPv3)
 
-//----------------------------------------------------------------------
 //
 // EmulateInstructionARM implementation
 //
-//----------------------------------------------------------------------
 
 void EmulateInstructionARM::Initialize() {
   PluginManager::RegisterPlugin(GetPluginNameStatic(),
@@ -740,21 +735,21 @@ EmulateInstructionARM::CreateInstance(const ArchSpec &arch,
   if (EmulateInstructionARM::SupportsEmulatingInstructionsOfTypeStatic(
           inst_type)) {
     if (arch.GetTriple().getArch() == llvm::Triple::arm) {
-      std::unique_ptr<EmulateInstructionARM> emulate_insn_ap(
+      std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
           new EmulateInstructionARM(arch));
 
-      if (emulate_insn_ap.get())
-        return emulate_insn_ap.release();
+      if (emulate_insn_up)
+        return emulate_insn_up.release();
     } else if (arch.GetTriple().getArch() == llvm::Triple::thumb) {
-      std::unique_ptr<EmulateInstructionARM> emulate_insn_ap(
+      std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
           new EmulateInstructionARM(arch));
 
-      if (emulate_insn_ap.get())
-        return emulate_insn_ap.release();
+      if (emulate_insn_up)
+        return emulate_insn_up.release();
     }
   }
 
-  return NULL;
+  return nullptr;
 }
 
 bool EmulateInstructionARM::SetTargetTriple(const ArchSpec &arch) {
@@ -10155,7 +10150,7 @@ bool EmulateInstructionARM::EmulateADDRegShift(const uint32_t opcode,
       shift_t = DecodeRegShift(Bits32(opcode, 6, 5));
 
       // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
-      if ((d == 15) || (m == 15) || (m == 15) || (s == 15))
+      if ((d == 15) || (n == 15) || (m == 15) || (s == 15))
         return false;
       break;
 
@@ -12853,9 +12848,7 @@ EmulateInstructionARM::ARMOpcode *
 EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
                                                   uint32_t arm_isa) {
   static ARMOpcode g_arm_opcodes[] = {
-      //----------------------------------------------------------------------
       // Prologue instructions
-      //----------------------------------------------------------------------
 
       // push register(s)
       {0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
@@ -12894,9 +12887,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
       {0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"},
 
-      //----------------------------------------------------------------------
       // Epilogue instructions
-      //----------------------------------------------------------------------
 
       {0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulatePOP, "pop <registers>"},
@@ -12907,15 +12898,11 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
       {0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"},
 
-      //----------------------------------------------------------------------
       // Supervisor Call (previously Software Interrupt)
-      //----------------------------------------------------------------------
       {0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateSVC, "svc #imm24"},
 
-      //----------------------------------------------------------------------
       // Branch instructions
-      //----------------------------------------------------------------------
       // To resolve ambiguity, "blx <label>" should come before "b #imm24" and
       // "bl <label>".
       {0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, No_VFP, eSize32,
@@ -12933,9 +12920,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
       {0x0ffffff0, 0x012fff20, ARMvAll, eEncodingA1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
 
-      //----------------------------------------------------------------------
       // Data-processing instructions
-      //----------------------------------------------------------------------
       // adc (immediate)
       {0x0fe00000, 0x02a00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"},
@@ -13099,9 +13084,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
        &EmulateInstructionARM::EmulateSUBSPcLrEtc,
        "<opc>S<c> PC,<Rn>,<Rm{,<shift>}"},
 
-      //----------------------------------------------------------------------
       // Load instructions
-      //----------------------------------------------------------------------
       {0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>"},
       {0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, No_VFP, eSize32,
@@ -13166,9 +13149,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
        &EmulateInstructionARM::EmulateVLD1SingleAll,
        "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
 
-      //----------------------------------------------------------------------
       // Store instructions
-      //----------------------------------------------------------------------
       {0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>"},
       {0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
@@ -13212,9 +13193,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
        &EmulateInstructionARM::EmulateVST1Single,
        "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
 
-      //----------------------------------------------------------------------
       // Other instructions
-      //----------------------------------------------------------------------
       {0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}"},
       {0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32,
@@ -13234,7 +13213,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
         (g_arm_opcodes[i].variants & arm_isa) != 0)
       return &g_arm_opcodes[i];
   }
-  return NULL;
+  return nullptr;
 }
 
 EmulateInstructionARM::ARMOpcode *
@@ -13242,9 +13221,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
                                                     uint32_t arm_isa) {
 
   static ARMOpcode g_thumb_opcodes[] = {
-      //----------------------------------------------------------------------
       // Prologue instructions
-      //----------------------------------------------------------------------
 
       // push register(s)
       {0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, No_VFP, eSize16,
@@ -13288,9 +13265,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
       {0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"},
 
-      //----------------------------------------------------------------------
       // Epilogue instructions
-      //----------------------------------------------------------------------
 
       {0xfffff800, 0x0000a800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
        &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"},
@@ -13307,15 +13282,11 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
       {0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"},
 
-      //----------------------------------------------------------------------
       // Supervisor Call (previously Software Interrupt)
-      //----------------------------------------------------------------------
       {0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, No_VFP, eSize16,
        &EmulateInstructionARM::EmulateSVC, "svc #imm8"},
 
-      //----------------------------------------------------------------------
       // If Then makes up to four following instructions conditional.
-      //----------------------------------------------------------------------
       // The next 5 opcode _must_ come before the if then instruction
       {0xffffffff, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16,
        &EmulateInstructionARM::EmulateNop, "nop"},
@@ -13330,9 +13301,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
       {0xffffff00, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16,
        &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"},
 
-      //----------------------------------------------------------------------
       // Branch instructions
-      //----------------------------------------------------------------------
       // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8".
       {0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, No_VFP, eSize16,
        &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"},
@@ -13367,9 +13336,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
       {0xfff0fff0, 0xe8d0f010, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"},
 
-      //----------------------------------------------------------------------
       // Data-processing instructions
-      //----------------------------------------------------------------------
       // adc (immediate)
       {0xfbe08000, 0xf1400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"},
@@ -13597,20 +13564,16 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
       {0xffffff00, 0xf3de8f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateSUBSPcLrEtc, "SUBS<c> PC, LR, #<imm8>"},
 
-      //----------------------------------------------------------------------
       // RFE instructions  *** IMPORTANT *** THESE MUST BE LISTED **BEFORE** THE
       // LDM.. Instructions in this table;
       // otherwise the wrong instructions will be selected.
-      //----------------------------------------------------------------------
 
       {0xffd0ffff, 0xe810c000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateRFE, "rfedb<c> <Rn>{!}"},
       {0xffd0ffff, 0xe990c000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
        &EmulateInstructionARM::EmulateRFE, "rfe{ia}<c> <Rn>{!}"},
 
-      //----------------------------------------------------------------------
       // Load instructions
-      //----------------------------------------------------------------------
       {0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
        &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>"},
       {0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
@@ -13718,9 +13681,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
        &EmulateInstructionARM::EmulateVLD1SingleAll,
        "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
 
-      //----------------------------------------------------------------------
       // Store instructions
-      //----------------------------------------------------------------------
       {0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
        &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>"},
       {0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
@@ -13777,9 +13738,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
        &EmulateInstructionARM::EmulateVST1Single,
        "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
 
-      //----------------------------------------------------------------------
       // Other instructions
-      //----------------------------------------------------------------------
       {0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16,
        &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>"},
       {0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, No_VFP, eSize32,
@@ -13804,7 +13763,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
         (g_thumb_opcodes[i].variants & arm_isa) != 0)
       return &g_thumb_opcodes[i];
   }
-  return NULL;
+  return nullptr;
 }
 
 bool EmulateInstructionARM::SetArchitecture(const ArchSpec &arch) {
@@ -14352,7 +14311,7 @@ bool EmulateInstructionARM::WriteFlags(Context &context, const uint32_t result,
 }
 
 bool EmulateInstructionARM::EvaluateInstruction(uint32_t evaluate_options) {
-  ARMOpcode *opcode_data = NULL;
+  ARMOpcode *opcode_data = nullptr;
 
   if (m_opcode_mode == eModeThumb)
     opcode_data =
@@ -14441,7 +14400,7 @@ bool EmulateInstructionARM::TestEmulation(Stream *out_stream, ArchSpec &arch,
   OptionValueSP value_sp = test_data->GetValueForKey(opcode_key);
 
   uint32_t test_opcode;
-  if ((value_sp.get() == NULL) ||
+  if ((value_sp.get() == nullptr) ||
       (value_sp->GetType() != OptionValue::eTypeUInt64)) {
     out_stream->Printf("TestEmulation: Error reading opcode from test file.\n");
     return false;
@@ -14467,7 +14426,7 @@ bool EmulateInstructionARM::TestEmulation(Stream *out_stream, ArchSpec &arch,
   EmulationStateARM after_state;
 
   value_sp = test_data->GetValueForKey(before_key);
-  if ((value_sp.get() == NULL) ||
+  if ((value_sp.get() == nullptr) ||
       (value_sp->GetType() != OptionValue::eTypeDictionary)) {
     out_stream->Printf("TestEmulation:  Failed to find 'before' state.\n");
     return false;
@@ -14480,7 +14439,7 @@ bool EmulateInstructionARM::TestEmulation(Stream *out_stream, ArchSpec &arch,
   }
 
   value_sp = test_data->GetValueForKey(after_key);
-  if ((value_sp.get() == NULL) ||
+  if ((value_sp.get() == nullptr) ||
       (value_sp->GetType() != OptionValue::eTypeDictionary)) {
     out_stream->Printf("TestEmulation:  Failed to find 'after' state.\n");
     return false;
diff --git a/source/Plugins/Instruction/ARM/EmulateInstructionARM.h b/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
index fb1867c6362a..13d7fc061bea 100644
--- a/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
+++ b/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
@@ -1,9 +1,8 @@
-//===-- lldb_EmulateInstructionARM.h ----------------------------*- C++ -*-===//
+//===-- EmulateInstructionARM.h ---------------------------------*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -46,7 +45,7 @@ private:
 
 class EmulateInstructionARM : public EmulateInstruction {
 public:
-  typedef enum {
+  enum ARMEncoding {
     eEncodingA1,
     eEncodingA2,
     eEncodingA3,
@@ -57,7 +56,7 @@ public:
     eEncodingT3,
     eEncodingT4,
     eEncodingT5
-  } ARMEncoding;
+  };
 
   static void Initialize();
 
@@ -292,7 +291,7 @@ public:
 protected:
   // Typedef for the callback function used during the emulation.
   // Pass along (ARMEncoding)encoding as the callback data.
-  typedef enum { eSize16, eSize32 } ARMInstrSize;
+  enum ARMInstrSize { eSize16, eSize32 };
 
   typedef struct {
     uint32_t mask;
diff --git a/source/Plugins/Instruction/ARM/EmulationStateARM.cpp b/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
index d770b3bdc52e..11c7677c201a 100644
--- a/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
+++ b/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
@@ -1,9 +1,8 @@
 //===-- EmulationStateARM.cpp -----------------------------------*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
@@ -285,14 +284,14 @@ bool EmulationStateARM::LoadStateFromDictionary(
 
   // Load memory, if present.
 
-  if (value_sp.get() != NULL) {
+  if (value_sp.get() != nullptr) {
     static ConstString address_key("address");
     static ConstString data_key("data");
     uint64_t start_address = 0;
 
     OptionValueDictionary *mem_dict = value_sp->GetAsDictionary();
     value_sp = mem_dict->GetValueForKey(address_key);
-    if (value_sp.get() == NULL)
+    if (value_sp.get() == nullptr)
       return false;
     else
       start_address = value_sp->GetUInt64Value();
@@ -307,7 +306,7 @@ bool EmulationStateARM::LoadStateFromDictionary(
 
     for (uint32_t i = 0; i < num_elts; ++i) {
       value_sp = mem_array->GetValueAtIndex(i);
-      if (value_sp.get() == NULL)
+      if (value_sp.get() == nullptr)
         return false;
       uint64_t value = value_sp->GetUInt64Value();
       StoreToPseudoAddress(address, value);
@@ -316,7 +315,7 @@ bool EmulationStateARM::LoadStateFromDictionary(
   }
 
   value_sp = test_data->GetValueForKey(registers_key);
-  if (value_sp.get() == NULL)
+  if (value_sp.get() == nullptr)
     return false;
 
   // Load General Registers
@@ -329,7 +328,7 @@ bool EmulationStateARM::LoadStateFromDictionary(
     sstr.Printf("r%d", i);
     ConstString reg_name(sstr.GetString());
     value_sp = reg_dict->GetValueForKey(reg_name);
-    if (value_sp.get() == NULL)
+    if (value_sp.get() == nullptr)
       return false;
     uint64_t reg_value = value_sp->GetUInt64Value();
     StorePseudoRegisterValue(dwarf_r0 + i, reg_value);
@@ -337,7 +336,7 @@ bool EmulationStateARM::LoadStateFromDictionary(
 
   static ConstString cpsr_name("cpsr");
   value_sp = reg_dict->GetValueForKey(cpsr_name);
-  if (value_sp.get() == NULL)
+  if (value_sp.get() == nullptr)
     return false;
   StorePseudoRegisterValue(dwarf_cpsr, value_sp->GetUInt64Value());
 
@@ -347,7 +346,7 @@ bool EmulationStateARM::LoadStateFromDictionary(
     sstr.Printf("s%d", i);
     ConstString reg_name(sstr.GetString());
     value_sp = reg_dict->GetValueForKey(reg_name);
-    if (value_sp.get() == NULL)
+    if (value_sp.get() == nullptr)
       return false;
     uint64_t reg_value = value_sp->GetUInt64Value();
     StorePseudoRegisterValue(dwarf_s0 + i, reg_value);
diff --git a/source/Plugins/Instruction/ARM/EmulationStateARM.h b/source/Plugins/Instruction/ARM/EmulationStateARM.h
index f27f4755a177..e5af37a21504 100644
--- a/source/Plugins/Instruction/ARM/EmulationStateARM.h
+++ b/source/Plugins/Instruction/ARM/EmulationStateARM.h
@@ -1,9 +1,8 @@
-//===-- lldb_EmulationStateARM.h --------------------------------*- C++ -*-===//
+//===-- EmulationStateARM.h -------------------------------------*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//