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authorEmmanuel Vadot <manu@FreeBSD.org>2017-03-07 12:41:06 +0000
committerEmmanuel Vadot <manu@FreeBSD.org>2017-03-07 12:41:06 +0000
commitff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e (patch)
tree5cd0b74d984dae06ea54b6b09998163538d3c162 /src/arm/sun9i-a80.dtsi
parentc7716441be3a4a48aa7b7cdf69a15625c1cd8ef5 (diff)
downloadsrc-test2-ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e.tar.gz
src-test2-ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e.zip
Notes
Diffstat (limited to 'src/arm/sun9i-a80.dtsi')
-rw-r--r--src/arm/sun9i-a80.dtsi28
1 files changed, 18 insertions, 10 deletions
diff --git a/src/arm/sun9i-a80.dtsi b/src/arm/sun9i-a80.dtsi
index f68b3242b33a..979ad1aacfb1 100644
--- a/src/arm/sun9i-a80.dtsi
+++ b/src/arm/sun9i-a80.dtsi
@@ -148,15 +148,14 @@
/*
* The 32k clock is from an external source, normally the
- * AC100 codec/RTC chip. This clock is by default enabled
- * and clocked at 32768 Hz, from the oscillator connected
- * to the AC100. It is configurable, but no such driver or
- * bindings exist yet.
+ * AC100 codec/RTC chip. This serves as a placeholder for
+ * board dts files to specify the source.
*/
osc32k: osc32k_clk {
#clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
+ compatible = "fixed-factor-clock";
+ clock-div = <1>;
+ clock-mult = <1>;
clock-output-names = "osc32k";
};
@@ -679,7 +678,8 @@
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 5>;
+ clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -701,6 +701,14 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ mmc1_pins: mmc1 {
+ allwinner,pins = "PG0", "PG1" ,"PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc2_8bit_pins: mmc2_8bit {
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
@@ -895,12 +903,12 @@
reg = <0x08002c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apbs_gates 0>;
+ clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
resets = <&apbs_rst 0>;
gpio-controller;
interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
+ #interrupt-cells = <3>;
#gpio-cells = <3>;
r_ir_pins: r_ir {