diff options
author | Emmanuel Vadot <manu@FreeBSD.org> | 2020-04-14 16:56:11 +0000 |
---|---|---|
committer | Emmanuel Vadot <manu@FreeBSD.org> | 2020-04-14 16:56:11 +0000 |
commit | 937eaf8bbdcf7e2cd3231b71940f9221e6857210 (patch) | |
tree | f35da0d4b9188f1cb082442854ce86fcca10b7b4 /src/arm64/qcom/sdm845.dtsi | |
parent | 995ee34fd27211af598f9adf111cb49609d1b3de (diff) | |
download | src-test2-937eaf8bbdcf7e2cd3231b71940f9221e6857210.tar.gz src-test2-937eaf8bbdcf7e2cd3231b71940f9221e6857210.zip |
Notes
Diffstat (limited to 'src/arm64/qcom/sdm845.dtsi')
-rw-r--r-- | src/arm64/qcom/sdm845.dtsi | 32 |
1 files changed, 21 insertions, 11 deletions
diff --git a/src/arm64/qcom/sdm845.dtsi b/src/arm64/qcom/sdm845.dtsi index ddb1f23c936f..d42302b8889b 100644 --- a/src/arm64/qcom/sdm845.dtsi +++ b/src/arm64/qcom/sdm845.dtsi @@ -1357,7 +1357,7 @@ }; }; - cache-controller@1100000 { + system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; @@ -1374,6 +1374,8 @@ lanes-per-direction = <2>; power-domains = <&gcc UFS_PHY_GDSC>; #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; iommus = <&apps_smmu 0x100 0xf>; @@ -1447,6 +1449,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 150>; + wakeup-parent = <&pdc_intc>; qspi_clk: qspi-clk { pinmux { @@ -2804,7 +2807,7 @@ }; }; - gpu@5000000 { + gpu: gpu@5000000 { compatible = "qcom,adreno-630.2", "qcom,adreno"; #stream-id-cells = <16>; @@ -2824,10 +2827,6 @@ qcom,gmu = <&gmu>; - zap_shader: zap-shader { - memory-region = <&gpu_mem>; - }; - gpu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2939,6 +2938,15 @@ #power-domain-cells = <1>; }; + pdc_intc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + pdc_reset: reset-controller@b2e0000 { compatible = "qcom,sdm845-pdc-global"; reg = <0 0x0b2e0000 0 0x20000>; @@ -2950,8 +2958,9 @@ reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <13>; - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -2960,8 +2969,9 @@ reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <8>; - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow"; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -3191,7 +3201,7 @@ <0 0x17a60000 0 0x100000>; /* GICR * 8 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - gic-its@17a40000 { + msi-controller@17a40000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; |