2 files changed, 970 insertions, 0 deletions

diff --git a/sys/dev/firewire/firewire.h b/sys/dev/firewire/firewire.h
new file mode 100644
index 000000000000..c41bb33abaff
--- /dev/null
+++ b/sys/dev/firewire/firewire.h
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the acknowledgement as bellow:
+ *
+ *    This product includes software developed by K. Kobayashi and H. Shimokawa
+ *
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _FIREWIRE_H
+#define _FIREWIRE_H 1
+
+#define	DEV_DEF  0
+#define	DEV_DV   2
+
+struct dv_data{
+	u_int32_t n_write;
+	u_int32_t a_write;
+	u_int32_t k_write;
+	u_int32_t write_done;
+	u_int32_t write_len[16];
+	u_int32_t write_off[16];
+	u_int32_t n_read;
+	u_int32_t a_read;
+	u_int32_t k_read;
+	u_int32_t read_done;
+	u_int32_t read_len[16];
+	u_int32_t read_off[16];
+};
+
+struct dv_data_req_t {
+	unsigned long index;
+	unsigned long len;
+	unsigned long off;
+};
+
+struct fw_isochreq {
+	unsigned char	ch:6,
+			tag:2;
+};
+
+struct fw_isobufreq {
+	struct {
+		unsigned int nchunk;
+		unsigned int npacket;
+		unsigned int psize;
+	} tx, rx;
+};
+
+struct fw_addr{
+	unsigned long hi;
+	unsigned long lo;
+};
+
+struct fw_asybindreq {
+	struct fw_addr start;
+	unsigned long len;
+};
+
+struct fw_reg_req_t{
+	unsigned long addr;
+	unsigned long data;
+};
+
+#define FWPMAX_S400 (2048 + 20)	/* MAXREC plus space for control data */
+#define FWMAXQUEUE 128
+
+#define	FWLOCALBUS	0xffc0
+
+#define FWTCODE_WREQQ	0
+#define FWTCODE_WREQB	1
+#define FWTCODE_WRES	2
+#define FWTCODE_RREQQ	4
+#define FWTCODE_RREQB	5
+#define FWTCODE_RRESQ	6
+#define FWTCODE_RRESB	7
+#define FWTCODE_CYCS	8
+#define FWTCODE_LREQ	9
+#define FWTCODE_STREAM	0xa
+#define FWTCODE_LRES	0xb
+#define FWTCODE_PHY	0xe
+
+#define	FWRETRY_1	0
+#define	FWRETRY_X	1
+#define	FWRETRY_A	2
+#define	FWRETRY_B	3
+
+#define FWRCODE_COMPLETE	0
+#define FWRCODE_ER_CONFL	4
+#define FWRCODE_ER_DATA		5
+#define FWRCODE_ER_TYPE		6
+#define FWRCODE_ER_ADDR		7
+
+#define FWSPD_S100	0
+#define FWSPD_S200	1
+#define FWSPD_S400	2
+
+#define	FWP_TL_VALID (1 << 7)
+
+struct fw_isohdr{
+	u_int32_t hdr[1];
+};
+struct fw_asyhdr{
+	u_int32_t hdr[4];
+};
+#define FWPHYSIDSUBS(SID) (((SID) >> 23) & 1)
+#define FWPHYSIDNODE(SID) (((SID) >> 24) & 0x3f)
+#define FWPHYSIDLINK(SID) (((SID) >> 22) & 1)
+#define FWPHYSIDGAP(SID) (((SID) >> 16) & 0x3f)
+#define FWPHYSIDSPD(SID) (((SID) >> 14) & 0x3)
+#define FWPHYSIDDEL(SID) (((SID) >> 12) & 0x3)
+#define FWPHYSIDCON(SID) (((SID) >> 11) & 1)
+#define FWPHYSIDPWR(SID) (((SID) >> 8) & 0x7)
+#define FWPHYSIDP0(SID) (((SID) >> 6) & 0x3)
+#define FWPHYSIDP1(SID) (((SID) >> 4) & 0x3)
+#define FWPHYSIDP2(SID) (((SID) >> 2) & 0x3)
+#define FWPHYSIDIR(SID) (((SID) >> 1) & 1)
+#define FWPHYSIDMORE(SID) ((SID) & 1)
+#define FWPHYSIDSEQ(SID) (((SID) >> 20) & 0x7)
+#define FWPHYSIDPA(SID) (((SID) >> 16) & 0x3)
+#define FWPHYSIDPB(SID) (((SID) >> 14) & 0x3)
+#define FWPHYSIDPC(SID) (((SID) >> 12) & 0x3)
+#define FWPHYSIDPD(SID) (((SID) >> 10) & 0x3)
+#define FWPHYSIDPE(SID) (((SID) >> 8) & 0x3)
+#define FWPHYSIDPF(SID) (((SID) >> 6) & 0x3)
+#define FWPHYSIDPG(SID) (((SID) >> 4) & 0x3)
+#define FWPHYSIDPH(SID) (((SID) >> 2) & 0x3)
+struct fw_pkt{
+#if BYTE_ORDER == LITTLE_ENDIAN
+	union{
+		u_int32_t ld[0];
+		struct {
+			u_int32_t :28,
+				  tcode:4;
+		}common;
+		struct {
+			u_int16_t len;
+			u_int8_t chtag;
+			u_int8_t sy:4,
+				 tcode:4;
+			u_int32_t payload[0];
+		}stream;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+		}hdr;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t dest_hi;
+			u_int32_t dest_lo;
+		}rreqq;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t res1:4,
+				  rtcode:4,
+				  res2:8;
+			u_int32_t res3;
+		}wres;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t dest_hi;
+			u_int32_t dest_lo;
+			u_int16_t len;
+			u_int16_t extcode:16;
+		}rreqb;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t dest_hi:16;
+			u_int32_t dest_lo;
+			u_int32_t data;
+		}wreqq;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t dest_hi;
+			u_int32_t dest_lo;
+			u_int32_t data;
+		}cyc;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t res1:4,
+				  rtcode:4,
+				  res2:8;
+			u_int32_t res3;
+			u_int32_t data;
+		}rresq;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t dest_hi;
+			u_int32_t dest_lo;
+			u_int16_t len;
+			u_int16_t extcode;
+			u_int32_t payload[0];
+		}wreqb;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t dest_hi;
+			u_int32_t dest_lo;
+			u_int16_t len;
+			u_int16_t extcode;
+#define FW_LREQ_MSKSWAP	1
+#define FW_LREQ_CMPSWAP	2
+#define FW_LREQ_FTADD	3
+#define FW_LREQ_LTADD	4
+#define FW_LREQ_BDADD	5
+#define FW_LREQ_WRADD	6
+			u_int32_t payload[0];
+		}lreq;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t res1:4,
+				  rtcode:4,
+				  res2:8;
+			u_int32_t res3;
+			u_int16_t len;
+			u_int16_t extcode;
+			u_int32_t payload[0];
+		}rresb;
+		struct {
+			u_int16_t dst;
+			u_int8_t tlrt;
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int16_t src;
+			u_int16_t res1:4,
+				  rtcode:4,
+				  res2:8;
+			u_int32_t res3;
+			u_int16_t len;
+			u_int16_t extcode;
+			u_int32_t payload[0];
+		}lres;
+	}mode;
+#else
+	union{
+		u_int32_t ld[0];
+		struct {
+			u_int32_t :4,
+				  tcode:4,
+				  :24;
+		}common;
+		struct {
+			u_int8_t sy:4,
+				 tcode:4;
+			u_int8_t chtag;
+			u_int16_t len;
+			u_int32_t payload[0];
+		}stream;
+		struct {
+			u_int32_t pri:4,
+				  tcode:4,
+				  tlrt:8,
+				  dst:16;
+			u_int32_t :16,
+				  src:16;
+		}hdr;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t dest_hi;
+			u_int16_t src;
+			u_int32_t dest_lo;
+		}rreqq;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t res1:12,
+				  rtcode:4;
+			u_int16_t src;
+			u_int32_t res3;
+		}wres;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t dest_hi;
+			u_int16_t src;
+			u_int32_t dest_lo;
+			u_int16_t extcode:16;
+			u_int16_t len;
+		}rreqb;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t dest_hi:16;
+			u_int16_t src;
+			u_int32_t dest_lo;
+			u_int32_t data;
+		}wreqq;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t dest_hi;
+			u_int16_t src;
+			u_int32_t dest_lo;
+			u_int32_t data;
+		}cyc;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t res1:12,
+				  rtcode:4;
+			u_int16_t src;
+			u_int32_t res3;
+			u_int32_t data;
+		}rresq;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t dest_hi;
+			u_int16_t src;
+			u_int32_t dest_lo;
+			u_int16_t extcode;
+			u_int16_t len;
+			u_int32_t payload[0];
+		}wreqb;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t dest_hi;
+			u_int16_t src;
+			u_int32_t dest_lo;
+			u_int16_t extcode;
+			u_int16_t len;
+#define FW_LREQ_MSKSWAP	1
+#define FW_LREQ_CMPSWAP	2
+#define FW_LREQ_FTADD	3
+#define FW_LREQ_LTADD	4
+#define FW_LREQ_BDADD	5
+#define FW_LREQ_WRADD	6
+			u_int32_t payload[0];
+		}lreq;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t res1:12,
+				  rtcode:4;
+			u_int16_t src;
+			u_int32_t res3;
+			u_int16_t extcode;
+			u_int16_t len;
+			u_int32_t payload[0];
+		}rresb;
+		struct {
+			u_int8_t pri:4,
+				 tcode:4;
+			u_int8_t tlrt;
+			u_int16_t dst;
+			u_int16_t res1:12,
+				  rtcode:4;
+			u_int16_t src;
+			u_int32_t res3;
+			u_int16_t extcode;
+			u_int16_t len;
+			u_int32_t payload[0];
+		}lres;
+	}mode;
+#endif
+};
+struct fw_eui64 {
+	u_int32_t hi, lo;
+};
+struct fw_asyreq {
+	struct fw_asyreq_t{
+		unsigned char sped;
+		unsigned int type;
+#define FWASREQNODE	0
+#define FWASREQEUI	1
+#define FWASRESTL	2
+#define FWASREQSTREAM	3
+		unsigned short len;
+		union {
+			struct fw_eui64 eui;
+		}dst;
+	}req;
+	struct fw_pkt pkt;
+	u_int32_t data[512];
+};
+struct fw_devlstreq {
+	int n;
+	struct fw_eui64 eui[64];
+	u_int16_t dst[64];
+	u_int16_t status[64];
+};
+#define FW_SELF_ID_PORT_CONNECTED_TO_CHILD 3
+#define FW_SELF_ID_PORT_CONNECTED_TO_PARENT 2
+#define FW_SELF_ID_PORT_NOT_CONNECTED 1
+#define FW_SELF_ID_PORT_NOT_EXISTS 0
+union fw_self_id {
+	struct {
+		u_int32_t more_packets:1,
+			  initiated_reset:1,
+			  port2:2,
+			  port1:2,
+			  port0:2,
+			  power_class:3,
+			  contender:1,
+			  phy_delay:2,
+			  phy_speed:2,
+			  gap_count:6,
+			  link_active:1,
+			  sequel:1,
+			  phy_id:6,
+			  id:2;
+	} p0;
+	struct {
+		u_int32_t more_packets:1,
+			  reserved1:1,
+			  porth:2,
+			  portg:2,
+			  portf:2,
+			  porte:2,
+			  portd:2,
+			  portc:2,
+			  portb:2,
+			  porta:2,
+			  reserved2:2,
+			  sequence_num:3,
+			  sequel:1,
+			  phy_id:6,
+			  id:2;
+	} p1;
+};
+struct fw_topology_map {
+	u_int32_t crc:16,
+		  crc_len:16;
+	u_int32_t generation;
+	u_int32_t self_id_count:16,
+		  node_count:16;
+	union fw_self_id self_id[4*64];
+};
+struct fw_speed_map {
+	u_int32_t crc:16,
+		  crc_len:16;
+	u_int32_t generation;
+	u_int8_t  speed[64][64];
+};
+struct fw_map_buf {
+	int len;
+	void *ptr;
+};
+struct fw_crom_buf {
+	struct fw_eui64 eui;
+	int len;
+	void *ptr;
+};
+#define FWSTMAXCHUNK 16
+/*
+ * Firewire specific system requests.
+ */
+#define	FW_SSTDV	_IOWR('S', 85, unsigned int)
+#define	FW_SSTBUF	_IOWR('S', 86, struct fw_isobufreq)
+#define	FW_GSTBUF	_IOWR('S', 87, struct fw_isobufreq)
+#define	FW_SRSTREAM	_IOWR('S', 88, struct fw_isochreq)
+#define	FW_GRSTREAM	_IOWR('S', 89, struct fw_isochreq)
+#define	FW_STSTREAM	_IOWR('S', 90, struct fw_isochreq)
+#define	FW_GTSTREAM	_IOWR('S', 91, struct fw_isochreq)
+
+#define	FW_ASYREQ	_IOWR('S', 92, struct fw_asyreq)
+#define FW_IBUSRST	_IOR('S', 1, unsigned int)
+#define FW_GDEVLST	_IOWR('S', 2, struct fw_devlstreq)
+#define	FW_SBINDADDR	_IOWR('S', 3, struct fw_asybindreq)
+#define	FW_CBINDADDR	_IOWR('S', 4, struct fw_asybindreq)
+#define	FW_GTPMAP	_IOR('S', 5, struct fw_topology_map)
+#define	FW_GSPMAP	_IOW('S', 6, struct fw_speed_map *)
+#define	FW_GCROM	_IOWR('S', 7, struct fw_crom_buf)
+
+#define FWOHCI_RDREG	_IOWR('S', 80, struct fw_reg_req_t)
+#define FWOHCI_WRREG	_IOWR('S', 81, struct fw_reg_req_t)
+
+#define DUMPDMA		_IOWR('S', 82, u_int32_t)
+
+#ifdef _KERNEL
+
+#define FWMAXNDMA 0x100 /* 8 bits DMA channel id. in device No. */
+
+#if __FreeBSD_version < 500000
+#define dev2unit(x)	((minor(x) & 0xff) | (minor(x) >> 8))
+#define unit2minor(x)	(((x) & 0xff) | (((x) << 8) & ~0xffff))
+#endif
+
+#define UNIT2MIN(x)	(((x) & 0xff) << 8)
+#define DEV2UNIT(x)	((dev2unit(x) & 0xff00) >> 8)
+#define DEV2DMACH(x)	(dev2unit(x) & 0xff)
+
+#define FWMEM_FLAG	0x10000
+#define DEV_FWMEM(x)	(dev2unit(x) & FWMEM_FLAG)
+#endif
+#endif
diff --git a/sys/dev/firewire/fwohcireg.h b/sys/dev/firewire/fwohcireg.h
new file mode 100644
index 000000000000..cbc556d50c01
--- /dev/null
+++ b/sys/dev/firewire/fwohcireg.h
@@ -0,0 +1,399 @@
+/*
+ * Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the acknowledgement as bellow:
+ *
+ *    This product includes software developed by K. Kobayashi and H. Shimokawa
+ *
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * $FreeBSD$
+ *
+ */
+#define		PCI_CBMEM		0x10
+
+#define		FW_VENDORID_NEC		0x1033
+#define		FW_VENDORID_TI		0x104c
+#define		FW_VENDORID_SONY	0x104d
+#define		FW_VENDORID_VIA		0x1106
+#define		FW_VENDORID_RICOH	0x1180
+#define		FW_VENDORID_APPLE	0x106b
+#define		FW_VENDORID_LUCENT	0x11c1
+
+#define		FW_DEVICE_UPD861	0x0063
+#define		FW_DEVICE_TITSB22	0x8009
+#define		FW_DEVICE_TITSB23	0x8019
+#define		FW_DEVICE_TITSB26	0x8020
+#define		FW_DEVICE_TITSB43	0x8021
+#define		FW_DEVICE_CX3022	0x8039
+#define		FW_DEVICE_VT6306	0x3044
+#define		FW_DEVICE_R5C552	0x1180
+#define		FW_DEVICE_PANGEA	0x0030
+#define		FW_DEVICE_UNINORTH	0x0031
+#define		FW_DEVICE_FW322		0x5811
+
+#define PCI_INTERFACE_OHCI	0x10
+
+#define FW_OHCI_BASE_REG	0x10
+
+#define		OHCI_DMA_ITCH		0x20
+#define		OHCI_DMA_IRCH		0x20
+
+#define		OHCI_MAX_DMA_CH		(0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
+
+
+typedef volatile u_int32_t 	fwohcireg_t;
+
+struct fwohcidb {
+	union {
+		struct {
+			volatile u_int32_t cmd;
+			volatile u_int32_t addr;
+			volatile u_int32_t depend;
+			volatile u_int32_t count:16,
+					   status:16;
+		} desc;
+		volatile u_int32_t immed[4];
+	} db;
+#define OHCI_OUTPUT_MORE	(0 << 28)
+#define OHCI_OUTPUT_LAST	(1 << 28)
+#define OHCI_INPUT_MORE		(2 << 28)
+#define OHCI_INPUT_LAST		(3 << 28)
+#define OHCI_STORE_QUAD		(4 << 28)
+#define OHCI_LOAD_QUAD		(5 << 28)
+#define OHCI_NOP		(6 << 28)
+#define OHCI_STOP		(7 << 28)
+#define OHCI_STORE		(8 << 28)
+#define OHCI_CMD_MASK		(0xf << 28)
+
+#define	OHCI_UPDATE		(1 << 27)
+
+#define OHCI_KEY_ST0		(0 << 24)
+#define OHCI_KEY_ST1		(1 << 24)
+#define OHCI_KEY_ST2		(2 << 24)
+#define OHCI_KEY_ST3		(3 << 24)
+#define OHCI_KEY_REGS		(5 << 24)
+#define OHCI_KEY_SYS		(6 << 24)
+#define OHCI_KEY_DEVICE		(7 << 24)
+#define OHCI_KEY_MASK		(7 << 24)
+
+#define OHCI_INTERRUPT_NEVER	(0 << 20)
+#define OHCI_INTERRUPT_TRUE	(1 << 20)
+#define OHCI_INTERRUPT_FALSE	(2 << 20)
+#define OHCI_INTERRUPT_ALWAYS	(3 << 20)
+
+#define OHCI_BRANCH_NEVER	(0 << 18)
+#define OHCI_BRANCH_TRUE	(1 << 18)
+#define OHCI_BRANCH_FALSE	(2 << 18)
+#define OHCI_BRANCH_ALWAYS	(3 << 18)
+#define OHCI_BRANCH_MASK	(3 << 18)
+
+#define OHCI_WAIT_NEVER		(0 << 16)
+#define OHCI_WAIT_TRUE		(1 << 16)
+#define OHCI_WAIT_FALSE		(2 << 16)
+#define OHCI_WAIT_ALWAYS	(3 << 16)
+};
+
+#define OHCI_SPD_S100 0x4
+#define OHCI_SPD_S200 0x1
+#define OHCI_SPD_S400 0x2
+
+
+#define FWOHCIEV_NOSTAT 0
+#define FWOHCIEV_LONGP 2
+#define FWOHCIEV_MISSACK 3
+#define FWOHCIEV_UNDRRUN 4
+#define FWOHCIEV_OVRRUN 5
+#define FWOHCIEV_DESCERR 6
+#define FWOHCIEV_DTRDERR 7
+#define FWOHCIEV_DTWRERR 8
+#define FWOHCIEV_BUSRST 9
+#define FWOHCIEV_TIMEOUT 0xa
+#define FWOHCIEV_TCODERR 0xb
+#define FWOHCIEV_UNKNOWN 0xe
+#define FWOHCIEV_FLUSHED 0xf
+#define FWOHCIEV_ACKCOMPL 0x11
+#define FWOHCIEV_ACKPEND 0x12
+#define FWOHCIEV_ACKBSX 0x14
+#define FWOHCIEV_ACKBSA 0x15
+#define FWOHCIEV_ACKBSB 0x16
+#define FWOHCIEV_ACKTARD 0x1b
+#define FWOHCIEV_ACKDERR 0x1d
+#define FWOHCIEV_ACKTERR 0x1e
+
+#define FWOHCIEV_MASK 0x1f
+
+struct ohci_registers {
+	fwohcireg_t	ver;		/* Version No. 0x0 */
+	fwohcireg_t	guid;		/* GUID_ROM No. 0x4 */
+	fwohcireg_t	retry;		/* AT retries 0x8 */
+#define FWOHCI_RETRY	0x8
+	fwohcireg_t	csr_data;	/* CSR data   0xc */
+	fwohcireg_t	csr_cmp;	/* CSR compare 0x10 */
+	fwohcireg_t	csr_cntl;	/* CSR compare 0x14 */
+	fwohcireg_t	rom_hdr;	/* config ROM ptr. 0x18 */
+	fwohcireg_t	bus_id;		/* BUS_ID 0x1c */
+	fwohcireg_t	bus_opt;	/* BUS option 0x20 */
+#define	FWOHCIGUID_H	0x24
+#define	FWOHCIGUID_L	0x28
+	fwohcireg_t	guid_hi;	/* GUID hi 0x24 */
+	fwohcireg_t	guid_lo;	/* GUID lo 0x28 */
+	fwohcireg_t	dummy0[2];	/* dummy 0x2c-0x30 */
+	fwohcireg_t	config_rom;	/* config ROM map 0x34 */
+	fwohcireg_t	post_wr_lo;	/* post write addr lo 0x38 */
+	fwohcireg_t	post_wr_hi;	/* post write addr hi 0x3c */
+	fwohcireg_t	vender;		/* vender ID 0x40 */
+	fwohcireg_t	dummy1[3];	/* dummy 0x44-0x4c */
+	fwohcireg_t	hcc_cntl_set;	/* HCC control set 0x50 */
+	fwohcireg_t	hcc_cntl_clr;	/* HCC control clr 0x54 */
+#define	OHCI_HCC_BIGEND	(1 << 30)
+#define	OHCI_HCC_PRPHY	(1 << 23)
+#define	OHCI_HCC_PHYEN	(1 << 22)
+#define	OHCI_HCC_LPS	(1 << 19)
+#define	OHCI_HCC_POSTWR	(1 << 18)
+#define	OHCI_HCC_LINKEN	(1 << 17)
+#define	OHCI_HCC_RESET	(1 << 16)
+	fwohcireg_t	dummy2[2];	/* dummy 0x58-0x5c */
+	fwohcireg_t	dummy3[1];	/* dummy 0x60 */
+	fwohcireg_t	sid_buf;	/* self id buffer 0x64 */
+	fwohcireg_t	sid_cnt;	/* self id count 0x68 */
+	fwohcireg_t	dummy4[1];	/* dummy 0x6c */
+	fwohcireg_t	ir_mask_hi_set;	/* ir mask hi set 0x70 */
+	fwohcireg_t	ir_mask_hi_clr;	/* ir mask hi set 0x74 */
+	fwohcireg_t	ir_mask_lo_set;	/* ir mask hi set 0x78 */
+	fwohcireg_t	ir_mask_lo_clr;	/* ir mask hi set 0x7c */
+#define	FWOHCI_INTSTAT		0x80
+#define	FWOHCI_INTSTATCLR	0x84
+#define	FWOHCI_INTMASK		0x88
+#define	FWOHCI_INTMASKCLR	0x8c
+	fwohcireg_t	int_stat;   /*       0x80 */
+	fwohcireg_t	int_clear;  /*       0x84 */
+	fwohcireg_t	int_mask;   /*       0x88 */
+	fwohcireg_t	int_mask_clear;   /*       0x8c */
+	fwohcireg_t	it_int_stat;   /*       0x90 */
+	fwohcireg_t	it_int_clear;  /*       0x94 */
+	fwohcireg_t	it_int_mask;   /*       0x98 */
+	fwohcireg_t	it_mask_clear;   /*       0x9c */
+	fwohcireg_t	ir_int_stat;   /*       0xa0 */
+	fwohcireg_t	ir_int_clear;  /*       0xa4 */
+	fwohcireg_t	ir_int_mask;   /*       0xa8 */
+	fwohcireg_t	ir_mask_clear;   /*       0xac */
+	fwohcireg_t	dummy5[11];	/* dummy 0xb0-d8 */
+	fwohcireg_t	fairness;   /* fairness control      0xdc */
+	fwohcireg_t	link_cntl;		/* Chip control 0xe0*/
+	fwohcireg_t	link_cntl_clr;	/* Chip control clear 0xe4*/
+#define FWOHCI_NODEID	0xe8
+	fwohcireg_t	node;		/* Node ID 0xe8 */
+#define	OHCI_NODE_VALID	(1 << 31)
+#define	OHCI_NODE_ROOT	(1 << 30)
+
+#define	OHCI_ASYSRCBUS	1
+
+	fwohcireg_t	phy_access;	/* PHY cntl 0xec */
+#define	PHYDEV_RDDONE		(1<<31)
+#define	PHYDEV_RDCMD		(1<<15)
+#define	PHYDEV_WRCMD		(1<<14)
+#define	PHYDEV_REGADDR		8
+#define	PHYDEV_WRDATA		0
+#define	PHYDEV_RDADDR		24
+#define	PHYDEV_RDDATA		16
+
+	fwohcireg_t	cycle_timer;	/* Cycle Timer 0xf0 */
+	fwohcireg_t	dummy6[3];	/* dummy 0xf4-fc */
+	fwohcireg_t	areq_hi;	/* Async req. filter hi 0x100 */
+	fwohcireg_t	areq_hi_clr;	/* Async req. filter hi 0x104 */
+	fwohcireg_t	areq_lo;	/* Async req. filter lo 0x108 */
+	fwohcireg_t	areq_lo_clr;	/* Async req. filter lo 0x10c */
+	fwohcireg_t	preq_hi;	/* Async req. filter hi 0x110 */
+	fwohcireg_t	preq_hi_clr;	/* Async req. filter hi 0x114 */
+	fwohcireg_t	preq_lo;	/* Async req. filter lo 0x118 */
+	fwohcireg_t	preq_lo_clr;	/* Async req. filter lo 0x11c */
+
+	fwohcireg_t	pys_upper;	/* Physical Upper bound 0x120 */
+
+	fwohcireg_t	dummy7[23];	/* dummy 0x124-0x17c */
+	
+	struct ohci_dma{
+		fwohcireg_t	cntl;
+
+#define	OHCI_CNTL_CYCMATCH_S	(0x1 << 31)
+
+#define	OHCI_CNTL_BUFFIL	(0x1 << 31)
+#define	OHCI_CNTL_ISOHDR	(0x1 << 30)
+#define	OHCI_CNTL_CYCMATCH_R	(0x1 << 29)
+#define	OHCI_CNTL_MULTICH	(0x1 << 28)
+
+#define	OHCI_CNTL_DMA_RUN	(0x1 << 15)
+#define	OHCI_CNTL_DMA_WAKE	(0x1 << 12)
+#define	OHCI_CNTL_DMA_DEAD	(0x1 << 11)
+#define	OHCI_CNTL_DMA_ACTIVE	(0x1 << 10)
+#define	OHCI_CNTL_DMA_BT	(0x1 << 8)
+#define	OHCI_CNTL_DMA_BAD	(0x1 << 7)
+#define	OHCI_CNTL_DMA_STAT	(0xff)
+
+		fwohcireg_t	cntl_clr;
+		fwohcireg_t	dummy0;
+		fwohcireg_t	cmd;
+		fwohcireg_t	match;
+		fwohcireg_t	dummy1;
+		fwohcireg_t	dummy2;
+		fwohcireg_t	dummy3;
+	};
+	/*       0x180, 0x184, 0x188, 0x18c */
+	/*       0x190, 0x194, 0x198, 0x19c */
+	/*       0x1a0, 0x1a4, 0x1a8, 0x1ac */
+	/*       0x1b0, 0x1b4, 0x1b8, 0x1bc */
+	/*       0x1c0, 0x1c4, 0x1c8, 0x1cc */
+	/*       0x1d0, 0x1d4, 0x1d8, 0x1dc */
+	/*       0x1e0, 0x1e4, 0x1e8, 0x1ec */
+	/*       0x1f0, 0x1f4, 0x1f8, 0x1fc */
+	struct ohci_dma dma_ch[0x4];
+
+	/*       0x200, 0x204, 0x208, 0x20c */
+	/*       0x210, 0x204, 0x208, 0x20c */
+	struct ohci_itdma{
+		fwohcireg_t	cntl;
+		fwohcireg_t	cntl_clr;
+		fwohcireg_t	dummy0;
+		fwohcireg_t	cmd;
+	};
+	struct ohci_itdma dma_itch[0x20];
+
+	/*       0x400, 0x404, 0x408, 0x40c */
+	/*       0x410, 0x404, 0x408, 0x40c */
+
+	struct ohci_dma dma_irch[0x20];
+};
+
+struct fwohcidb_tr{
+	STAILQ_ENTRY(fwohcidb_tr) link;
+	struct fw_xfer *xfer;
+	volatile struct fwohcidb *db;
+	caddr_t buf;
+	caddr_t dummy;
+	int dbcnt;
+};
+
+/*
+ * OHCI info structure.
+ */
+#if 0
+struct fwohci_softc {
+	struct fw_softc fc;
+	volatile struct ohci_registers *base;
+	int		init;
+#define	SIDPHASE	1
+	u_int32_t	flags;
+	struct 		fwohcidb_tr *db_tr[OHCI_MAX_DMA_CH];
+	struct 		fwohcidb_tr *db_first[OHCI_MAX_DMA_CH];
+	struct 		fwohcidb_tr *db_last[OHCI_MAX_DMA_CH];
+        struct {
+		int		tail;
+		struct fwohcidb_tr *db_tr;
+		struct fwohcidb *db;
+        }dbdvtx[MAX_DVFRAME], dbdvrx[MAX_DVFRAME];
+	int		ndb[OHCI_MAX_DMA_CH];
+        u_int32_t	isohdr[OHCI_MAX_DMA_CH];
+        int		queued[OHCI_MAX_DMA_CH];
+        int		dma_ch[OHCI_MAX_DMA_CH];
+};
+#endif
+struct fwohci_txpkthdr{
+	union{
+		u_int32_t ld[4];
+		struct {
+			u_int32_t res3:4,
+				  tcode:4,
+				  res2:8,
+				  spd:3,
+				  res1:13;
+		}common;
+		struct {
+			u_int32_t res3:4,
+				 tcode:4,
+				 tlrt:8,
+				 spd:3,
+				 res2:4,
+				 srcbus:1,
+				 res1:8;
+		  	u_int32_t res4:16,
+				 dst:16;
+		}asycomm;
+		struct {
+			u_int32_t sy:4,
+				  tcode:4,
+				  chtag:8,
+			          spd:3,
+				  res1:13;
+			u_int32_t res2:16,
+				  len:16;
+		}stream;
+	}mode;
+};
+struct fwohci_trailer{
+	u_int32_t time:16,
+		  stat:16;
+};
+
+#define	OHCI_CNTL_CYCSRC	(0x1 << 22)
+#define	OHCI_CNTL_CYCMTR	(0x1 << 21)
+#define	OHCI_CNTL_CYCTIMER	(0x1 << 20)
+#define	OHCI_CNTL_PHYPKT	(0x1 << 10)
+#define	OHCI_CNTL_SID		(0x1 << 9)
+
+#define OHCI_INT_DMA_ATRQ	(0x1 << 0)
+#define OHCI_INT_DMA_ATRS	(0x1 << 1)
+#define OHCI_INT_DMA_ARRQ	(0x1 << 2)
+#define OHCI_INT_DMA_ARRS	(0x1 << 3)
+#define OHCI_INT_DMA_PRRQ	(0x1 << 4)
+#define OHCI_INT_DMA_PRRS	(0x1 << 5)
+#define OHCI_INT_DMA_IT	(0x1 << 6)
+#define OHCI_INT_DMA_IR	(0x1 << 7)
+#define OHCI_INT_PW_ERR	(0x1 << 8)
+#define OHCI_INT_LR_ERR	(0x1 << 9)
+
+#define OHCI_INT_PHY_SID	(0x1 << 16)
+#define OHCI_INT_PHY_BUS_R	(0x1 << 17)
+
+#define OHCI_INT_PHY_INT	(0x1 << 19)
+#define OHCI_INT_CYC_START	(0x1 << 20)
+#define OHCI_INT_CYC_64SECOND	(0x1 << 21)
+#define OHCI_INT_CYC_LOST	(0x1 << 22)
+#define OHCI_INT_CYC_ERR	(0x1 << 23)
+
+#define OHCI_INT_ERR		(0x1 << 24)
+#define OHCI_INT_CYC_LONG	(0x1 << 25)
+#define OHCI_INT_PHY_REG	(0x1 << 26)
+
+#define OHCI_INT_EN		(0x1 << 31)
+
+#define IP_CHANNELS             0x0234
+#define FWOHCI_MAXREC		2048
+
+#define	OHCI_ISORA		0x02
+#define	OHCI_ISORB		0x04
+
+#define FWOHCITCODE_PHY		0xe