2 files changed, 208 insertions, 103 deletions

diff --git a/sys/dev/ata/ata-chipset.c b/sys/dev/ata/ata-chipset.c
index 334e787ad903..f9746d0c2e05 100644
--- a/sys/dev/ata/ata-chipset.c
+++ b/sys/dev/ata/ata-chipset.c
@@ -102,7 +102,8 @@ static int ata_intel_31244_status(device_t dev);
 static void ata_intel_31244_tf_write(struct ata_request *request);
 static void ata_intel_31244_reset(device_t dev);
 static int ata_ite_chipinit(device_t dev);
-static void ata_ite_setmode(device_t dev, int mode);
+static void ata_ite_8213_setmode(device_t dev, int mode);
+static void ata_ite_821x_setmode(device_t dev, int mode);
 static int ata_jmicron_chipinit(device_t dev);
 static int ata_jmicron_allocate(device_t dev);
 static void ata_jmicron_reset(device_t dev);
@@ -1762,58 +1763,66 @@ ata_intel_ident(device_t dev)
 {
     struct ata_pci_controller *ctlr = device_get_softc(dev);
     static struct ata_chip_id ids[] =
-    {{ ATA_I82371FB,     0,    0, 0x00, ATA_WDMA2, "PIIX" },
-     { ATA_I82371SB,     0,    0, 0x00, ATA_WDMA2, "PIIX3" },
-     { ATA_I82371AB,     0,    0, 0x00, ATA_UDMA2, "PIIX4" },
-     { ATA_I82443MX,     0,    0, 0x00, ATA_UDMA2, "PIIX4" },
-     { ATA_I82451NX,     0,    0, 0x00, ATA_UDMA2, "PIIX4" },
-     { ATA_I82801AB,     0,    0, 0x00, ATA_UDMA2, "ICH0" },
-     { ATA_I82801AA,     0,    0, 0x00, ATA_UDMA4, "ICH" },
-     { ATA_I82372FB,     0,    0, 0x00, ATA_UDMA4, "ICH" },
-     { ATA_I82801BA,     0,    0, 0x00, ATA_UDMA5, "ICH2" },
-     { ATA_I82801BA_1,   0,    0, 0x00, ATA_UDMA5, "ICH2" },
-     { ATA_I82801CA,     0,    0, 0x00, ATA_UDMA5, "ICH3" },
-     { ATA_I82801CA_1,   0,    0, 0x00, ATA_UDMA5, "ICH3" },
-     { ATA_I82801DB,     0,    0, 0x00, ATA_UDMA5, "ICH4" },
-     { ATA_I82801DB_1,   0,    0, 0x00, ATA_UDMA5, "ICH4" },
-     { ATA_I82801EB,     0,    0, 0x00, ATA_UDMA5, "ICH5" },
-     { ATA_I82801EB_S1,  0,    0, 0x00, ATA_SA150, "ICH5" },
-     { ATA_I82801EB_R1,  0,    0, 0x00, ATA_SA150, "ICH5" },
-     { ATA_I6300ESB,     0,    0, 0x00, ATA_UDMA5, "6300ESB" },
-     { ATA_I6300ESB_S1,  0,    0, 0x00, ATA_SA150, "6300ESB" },
-     { ATA_I6300ESB_R1,  0,    0, 0x00, ATA_SA150, "6300ESB" },
-     { ATA_I82801FB,     0,    0, 0x00, ATA_UDMA5, "ICH6" },
-     { ATA_I82801FB_S1,  0, AHCI, 0x00, ATA_SA150, "ICH6" },
-     { ATA_I82801FB_R1,  0, AHCI, 0x00, ATA_SA150, "ICH6" },
-     { ATA_I82801FBM,    0, AHCI, 0x00, ATA_SA150, "ICH6M" },
-     { ATA_I82801GB,     0,    0, 0x00, ATA_UDMA5, "ICH7" },
-     { ATA_I82801GB_S1,  0, AHCI, 0x00, ATA_SA300, "ICH7" },
-     { ATA_I82801GB_R1,  0, AHCI, 0x00, ATA_SA300, "ICH7" },
-     { ATA_I82801GB_AH,  0, AHCI, 0x00, ATA_SA300, "ICH7" },
-     { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
-     { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
-     { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
-     { ATA_I63XXESB2,    0,    0, 0x00, ATA_UDMA5, "63XXESB2" },
-     { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
-     { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
-     { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
-     { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
-     { ATA_I82801HB_S1,  0, AHCI, 0x00, ATA_SA300, "ICH8" },
-     { ATA_I82801HB_S2,  0, AHCI, 0x00, ATA_SA300, "ICH8" },
-     { ATA_I82801HB_R1,  0, AHCI, 0x00, ATA_SA300, "ICH8" },
-     { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
-     { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
-     { ATA_I82801HBM,    0,    0, 0x00, ATA_UDMA5, "ICH8M" },
-     { ATA_I82801HBM_S1, 0,    0, 0x00, ATA_SA150, "ICH8M" },
-     { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
-     { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
-     { ATA_I82801IB_S1,  0, AHCI, 0x00, ATA_SA300, "ICH9" },
-     { ATA_I82801IB_S2,  0, AHCI, 0x00, ATA_SA300, "ICH9" },
-     { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
-     { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
-     { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
-     { ATA_I82801IB_R1,  0, AHCI, 0x00, ATA_SA300, "ICH9" },
-     { ATA_I31244,       0,    0, 0x00, ATA_SA150, "31244" },
+    {{ ATA_I82371FB,     0,    0, 2, ATA_WDMA2, "PIIX" },
+     { ATA_I82371SB,     0,    0, 2, ATA_WDMA2, "PIIX3" },
+     { ATA_I82371AB,     0,    0, 2, ATA_UDMA2, "PIIX4" },
+     { ATA_I82443MX,     0,    0, 2, ATA_UDMA2, "PIIX4" },
+     { ATA_I82451NX,     0,    0, 2, ATA_UDMA2, "PIIX4" },
+     { ATA_I82801AB,     0,    0, 2, ATA_UDMA2, "ICH0" },
+     { ATA_I82801AA,     0,    0, 2, ATA_UDMA4, "ICH" },
+     { ATA_I82372FB,     0,    0, 2, ATA_UDMA4, "ICH" },
+     { ATA_I82801BA,     0,    0, 2, ATA_UDMA5, "ICH2" },
+     { ATA_I82801BA_1,   0,    0, 2, ATA_UDMA5, "ICH2" },
+     { ATA_I82801CA,     0,    0, 2, ATA_UDMA5, "ICH3" },
+     { ATA_I82801CA_1,   0,    0, 2, ATA_UDMA5, "ICH3" },
+     { ATA_I82801DB,     0,    0, 2, ATA_UDMA5, "ICH4" },
+     { ATA_I82801DB_1,   0,    0, 2, ATA_UDMA5, "ICH4" },
+     { ATA_I82801EB,     0,    0, 2, ATA_UDMA5, "ICH5" },
+     { ATA_I82801EB_S1,  0,    0, 2, ATA_SA150, "ICH5" },
+     { ATA_I82801EB_R1,  0,    0, 2, ATA_SA150, "ICH5" },
+     { ATA_I6300ESB,     0,    0, 2, ATA_UDMA5, "6300ESB" },
+     { ATA_I6300ESB_S1,  0,    0, 2, ATA_SA150, "6300ESB" },
+     { ATA_I6300ESB_R1,  0,    0, 2, ATA_SA150, "6300ESB" },
+     { ATA_I82801FB,     0,    0, 2, ATA_UDMA5, "ICH6" },
+     { ATA_I82801FB_S1,  0, AHCI, 0, ATA_SA150, "ICH6" },
+     { ATA_I82801FB_R1,  0, AHCI, 0, ATA_SA150, "ICH6" },
+     { ATA_I82801FBM,    0, AHCI, 0, ATA_SA150, "ICH6M" },
+     { ATA_I82801GB,     0,    0, 1, ATA_UDMA5, "ICH7" },
+     { ATA_I82801GB_S1,  0, AHCI, 0, ATA_SA300, "ICH7" },
+     { ATA_I82801GB_R1,  0, AHCI, 0, ATA_SA300, "ICH7" },
+     { ATA_I82801GB_AH,  0, AHCI, 0, ATA_SA300, "ICH7" },
+     { ATA_I82801GBM_S1, 0, AHCI, 0, ATA_SA300, "ICH7M" },
+     { ATA_I82801GBM_R1, 0, AHCI, 0, ATA_SA300, "ICH7M" },
+     { ATA_I82801GBM_AH, 0, AHCI, 0, ATA_SA300, "ICH7M" },
+     { ATA_I63XXESB2,    0,    0, 1, ATA_UDMA5, "63XXESB2" },
+     { ATA_I63XXESB2_S1, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
+     { ATA_I63XXESB2_S2, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
+     { ATA_I63XXESB2_R1, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
+     { ATA_I63XXESB2_R2, 0, AHCI, 0, ATA_SA300, "63XXESB2" },
+     { ATA_I82801HB_S1,  0, AHCI, 0, ATA_SA300, "ICH8" },
+     { ATA_I82801HB_S2,  0, AHCI, 0, ATA_SA300, "ICH8" },
+     { ATA_I82801HB_R1,  0, AHCI, 0, ATA_SA300, "ICH8" },
+     { ATA_I82801HB_AH4, 0, AHCI, 0, ATA_SA300, "ICH8" },
+     { ATA_I82801HB_AH6, 0, AHCI, 0, ATA_SA300, "ICH8" },
+     { ATA_I82801HBM,    0,    0, 1, ATA_UDMA5, "ICH8M" },
+     { ATA_I82801HBM_S1, 0, AHCI, 0, ATA_SA300, "ICH8M" },
+     { ATA_I82801HBM_S2, 0, AHCI, 0, ATA_SA300, "ICH8M" },
+     { ATA_I82801HBM_S3, 0, AHCI, 0, ATA_SA300, "ICH8M" },
+     { ATA_I82801IB_S1,  0, AHCI, 0, ATA_SA300, "ICH9" },
+     { ATA_I82801IB_S2,  0, AHCI, 0, ATA_SA300, "ICH9" },
+     { ATA_I82801IB_AH2, 0, AHCI, 0, ATA_SA300, "ICH9" },
+     { ATA_I82801IB_AH4, 0, AHCI, 0, ATA_SA300, "ICH9" },
+     { ATA_I82801IB_AH6, 0, AHCI, 0, ATA_SA300, "ICH9" },
+     { ATA_I82801IB_R1,  0, AHCI, 0, ATA_SA300, "ICH9" },
+     { ATA_I82801JIB_S1, 0, AHCI, 0, ATA_SA300, "ICH10" },
+     { ATA_I82801JIB_AH, 0, AHCI, 0, ATA_SA300, "ICH10" },
+     { ATA_I82801JIB_R1, 0, AHCI, 0, ATA_SA300, "ICH10" },
+     { ATA_I82801JIB_S2, 0, AHCI, 0, ATA_SA300, "ICH10" },
+     { ATA_I82801JD_S1,  0, AHCI, 0, ATA_SA300, "ICH10" },
+     { ATA_I82801JD_AH,  0, AHCI, 0, ATA_SA300, "ICH10" },
+     { ATA_I82801JD_R1,  0, AHCI, 0, ATA_SA300, "ICH10" },
+     { ATA_I82801JD_S2,  0, AHCI, 0, ATA_SA300, "ICH10" },
+     { ATA_I31244,       0,    0, 2, ATA_SA150, "31244" },
      { 0, 0, 0, 0, 0, 0}};
 
     if (!(ctlr->chip = ata_match_chip(dev, ids)))
@@ -1855,6 +1864,7 @@ ata_intel_chipinit(device_t dev)
 
     /* non SATA intel chips goes here */
     else if (ctlr->chip->max_dma < ATA_SA150) {
+	ctlr->channels = ctlr->chip->cfg2;
 	ctlr->allocate = ata_intel_allocate;
 	ctlr->setmode = ata_intel_new_setmode;
     }
@@ -1988,52 +1998,54 @@ ata_intel_new_setmode(device_t dev, int mode)
 	device_printf(dev, "%ssetting %s on %s chip\n",
 		      (error) ? "FAILURE " : "",
 		      ata_mode2str(mode), ctlr->chip->text);
-    if (error)
-	return;
+    if (!error) {
+	if (mode >= ATA_UDMA0) {
+	    u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
 
-    if (mode >= ATA_UDMA0) {
-	pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
-	pci_write_config(gparent, 0x4a,
-			 (reg4a & ~(0x3 << (devno << 2))) |
-			 ((0x01 + !(mode & 0x01)) << (devno << 2)), 2);
-    }
-    else {
-	pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
-	pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2);
-    }
-    reg54 |= 0x0400;
-    if (mode >= ATA_UDMA2)
-	pci_write_config(gparent, 0x54, reg54 | (0x1 << devno), 2);
-    else
-	pci_write_config(gparent, 0x54, reg54 & ~(0x1 << devno), 2);
+	    pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
+	    pci_write_config(gparent, 0x4a,
+			     (reg4a & ~(0x3 << (devno << 2))) |
+			     (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
+	}
+	else {
+	    pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
+	    pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
+	}
+	reg54 |= 0x0400;
+	if (mode >= ATA_UDMA2)
+	    reg54 |= (0x1 << devno);
+	else
+	    reg54 &= ~(0x1 << devno);
+	if (mode >= ATA_UDMA5)
+	    reg54 |= (0x1000 << devno);
+	else 
+	    reg54 &= ~(0x1000 << devno);
 
-    if (mode >= ATA_UDMA5)
-	pci_write_config(gparent, 0x54, reg54 | (0x1000 << devno), 2);
-    else 
-	pci_write_config(gparent, 0x54, reg54 & ~(0x1000 << devno), 2);
+	pci_write_config(gparent, 0x54, reg54, 2);
 
-    reg40 &= ~0x00ff00ff;
-    reg40 |= 0x40774077;
+	reg40 &= ~0x00ff00ff;
+	reg40 |= 0x40774077;
 
-    if (atadev->unit == ATA_MASTER) {
-	mask40 = 0x3300;
-	new40 = timings[ata_mode2idx(mode)] << 8;
-    }
-    else {
-	mask44 = 0x0f;
-	new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
-		(timings[ata_mode2idx(mode)] & 0x03);
-    }
-    if (ch->unit) {
-	mask40 <<= 16;
-	new40 <<= 16;
-	mask44 <<= 4;
-	new44 <<= 4;
-    }
-    pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
-    pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
+	if (atadev->unit == ATA_MASTER) {
+	    mask40 = 0x3300;
+	    new40 = timings[ata_mode2idx(mode)] << 8;
+	}
+	else {
+	    mask44 = 0x0f;
+	    new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
+		    (timings[ata_mode2idx(mode)] & 0x03);
+	}
+	if (ch->unit) {
+	    mask40 <<= 16;
+	    new40 <<= 16;
+	    mask44 <<= 4;
+	    new44 <<= 4;
+	}
+	pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
+	pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
 
-    atadev->mode = mode;
+	atadev->mode = mode;
+    }
 }
 
 static void
@@ -2193,7 +2205,8 @@ ata_ite_ident(device_t dev)
 {
     struct ata_pci_controller *ctlr = device_get_softc(dev);
     static struct ata_chip_id ids[] =
-    {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
+    {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" },
+     { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
      { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
      { 0, 0, 0, 0, 0, 0}};
 
@@ -2213,19 +2226,28 @@ ata_ite_chipinit(device_t dev)
     if (ata_setup_interrupt(dev))
 	return ENXIO;
 
-    ctlr->setmode = ata_ite_setmode;
+    if (ctlr->chip->chipid == ATA_IT8213F) {
+	/* the ITE 8213F only has one channel */
+	ctlr->channels = 1;
 
-    /* set PCI mode and 66Mhz reference clock */
-    pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
+	ctlr->setmode = ata_ite_8213_setmode;
+    }
+    else {
+	/* set PCI mode and 66Mhz reference clock */
+	pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
+
+	/* set default active & recover timings */
+	pci_write_config(dev, 0x54, 0x31, 1);
+	pci_write_config(dev, 0x56, 0x31, 1);
+
+	ctlr->setmode = ata_ite_821x_setmode;
+    }
 
-    /* set default active & recover timings */
-    pci_write_config(dev, 0x54, 0x31, 1);
-    pci_write_config(dev, 0x56, 0x31, 1);
     return 0;
 }
  
 static void
-ata_ite_setmode(device_t dev, int mode)
+ata_ite_821x_setmode(device_t dev, int mode)
 {
     device_t gparent = GRANDPARENT(dev);
     struct ata_channel *ch = device_get_softc(device_get_parent(dev));
@@ -2285,6 +2307,80 @@ ata_ite_setmode(device_t dev, int mode)
     }
 }
 
+static void
+ata_ite_8213_setmode(device_t dev, int mode)
+{
+    device_t gparent = GRANDPARENT(dev);
+    struct ata_pci_controller *ctlr = device_get_softc(gparent);
+    struct ata_device *atadev = device_get_softc(dev);
+    u_int16_t reg40 = pci_read_config(gparent, 0x40, 2);
+    u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
+    u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
+    u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
+    u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
+    u_int16_t mask40 = 0, new40 = 0;
+    u_int8_t mask44 = 0, new44 = 0;
+    int devno = atadev->unit;
+    int error;
+    u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
+			   0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
+
+    mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
+
+    if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
+	ata_print_cable(dev, "controller");
+	mode = ATA_UDMA2;
+    }
+
+    error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
+
+    if (bootverbose)
+	device_printf(dev, "%ssetting %s on %s chip\n",
+		      (error) ? "FAILURE " : "",
+		      ata_mode2str(mode), ctlr->chip->text);
+    if (!error) {
+	if (mode >= ATA_UDMA0) {
+	    u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
+
+	    pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
+	    pci_write_config(gparent, 0x4a,
+			     (reg4a & ~(0x3 << (devno << 2))) |
+			     (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
+	}
+	else {
+	    pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
+	    pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
+	}
+	if (mode >= ATA_UDMA2)
+	    reg54 |= (0x1 << devno);
+	else
+	    reg54 &= ~(0x1 << devno);
+	if (mode >= ATA_UDMA5)
+	    reg54 |= (0x1000 << devno);
+	else 
+	    reg54 &= ~(0x1000 << devno);
+	pci_write_config(gparent, 0x54, reg54, 2);
+
+	reg40 &= 0xff00;
+	reg40 |= 0x4033;
+	if (atadev->unit == ATA_MASTER) {
+	    reg40 |= (ata_atapi(dev) ? 0x04 : 0x00);
+	    mask40 = 0x3300;
+	    new40 = timings[ata_mode2idx(mode)] << 8;
+	}
+	else {
+	    reg40 |= (ata_atapi(dev) ? 0x40 : 0x00);
+	    mask44 = 0x0f;
+	    new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
+		    (timings[ata_mode2idx(mode)] & 0x03);
+	}
+	pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
+	pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
+
+	atadev->mode = mode;
+    }
+}
+
 
 /*
  * JMicron chipset support functions
@@ -4517,7 +4613,7 @@ ata_sii_chipinit(device_t dev)
 	ctlr->r_type2 = SYS_RES_MEMORY;
 	ctlr->r_rid2 = PCIR_BAR(5);
 	if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
-						    &ctlr->r_rid2, RF_ACTIVE))) {
+						    &ctlr->r_rid2, RF_ACTIVE))){
 	    if (ctlr->chip->chipid != ATA_SII0680 ||
 			    (pci_read_config(dev, 0x8a, 1) & 1))
 		return ENXIO;
diff --git a/sys/dev/ata/ata-pci.h b/sys/dev/ata/ata-pci.h
index 89ec2862fc7b..34ecbbbfa811 100644
--- a/sys/dev/ata/ata-pci.h
+++ b/sys/dev/ata/ata-pci.h
@@ -180,11 +180,20 @@ struct ata_connect_task {
 #define ATA_I82801IB_AH4        0x29238086
 #define ATA_I82801IB_R1         0x29258086
 #define ATA_I82801IB_S2         0x29268086
+#define ATA_I82801JIB_S1        0x3a208086
+#define ATA_I82801JIB_AH        0x3a228086
+#define ATA_I82801JIB_R1        0x3a258086
+#define ATA_I82801JIB_S2        0x3a268086
+#define ATA_I82801JD_S1         0x3a008086
+#define ATA_I82801JD_AH         0x3a028086
+#define ATA_I82801JD_R1         0x3a058086
+#define ATA_I82801JD_S2         0x3a068086
 #define ATA_I31244              0x32008086
 
 #define ATA_ITE_ID              0x1283
 #define ATA_IT8211F             0x82111283
 #define ATA_IT8212F             0x82121283
+#define ATA_IT8213F             0x82131283
 
 #define ATA_JMICRON_ID          0x197b
 #define ATA_JMB360              0x2360197b