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| author | Dimitry Andric <dim@FreeBSD.org> | 2018-07-28 10:51:19 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-07-28 10:51:19 +0000 |
| commit | eb11fae6d08f479c0799db45860a98af528fa6e7 (patch) | |
| tree | 44d492a50c8c1a7eb8e2d17ea3360ec4d066f042 /test/CodeGen/AArch64/zext-logic-shift-load.ll | |
| parent | b8a2042aa938069e862750553db0e4d82d25822c (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/AArch64/zext-logic-shift-load.ll')
| -rw-r--r-- | test/CodeGen/AArch64/zext-logic-shift-load.ll | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/zext-logic-shift-load.ll b/test/CodeGen/AArch64/zext-logic-shift-load.ll new file mode 100644 index 000000000000..a75862cfc3b3 --- /dev/null +++ b/test/CodeGen/AArch64/zext-logic-shift-load.ll @@ -0,0 +1,14 @@ +; RUN: llc -mtriple=aarch64-linux-gnu < %s -o - | FileCheck %s + +define i32 @test1(i8* %p) { +; CHECK: ldrb +; CHECK-NEXT: ubfx +; CHECK-NEXT: ret + + %1 = load i8, i8* %p + %2 = lshr i8 %1, 1 + %3 = and i8 %2, 1 + %4 = zext i8 %3 to i32 + ret i32 %4 +} + |