vendor/llvm/llvm-trunk-r321017

author: Dimitry Andric <dim@FreeBSD.org> 2017-12-18 20:10:56 +0000
committer: Dimitry Andric <dim@FreeBSD.org> 2017-12-18 20:10:56 +0000
commit: 044eb2f6afba375a914ac9d8024f8f5142bb912e (patch)
tree: 1475247dc9f9fe5be155ebd4c9069c75aadf8c20 /test/CodeGen/AArch64
parent: eb70dddbd77e120e5d490bd8fbe7ff3f8fa81c6b (diff)
209 files changed, 14293 insertions, 4586 deletions
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
index a70cee0efcb6..40f65b3774ed 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
@@ -4,14 +4,14 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-apple-ios9.0"
 
 ; CHECK-LABEL: name: test_varargs
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: [[D_ONE:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
-; CHECK: [[TWELVE:%[0-9]+]](s64) = G_CONSTANT i64 12
-; CHECK: [[THREE:%[0-9]+]](s8) = G_CONSTANT i8 3
-; CHECK: [[ONE:%[0-9]+]](s16) = G_CONSTANT i16 1
-; CHECK: [[FOUR:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[F_ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-; CHECK: [[TWO:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[D_ONE:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+; CHECK: [[TWELVE:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+; CHECK: [[THREE:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
+; CHECK: [[ONE:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+; CHECK: [[FOUR:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
 
 ; CHECK: %w0 = COPY [[ANSWER]]
 ; CHECK: %d0 = COPY [[D_ONE]]
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
index 59b9bb49f0ee..3888628fd1ed 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
@@ -4,14 +4,14 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-linux-gnu"
 
 ; CHECK-LABEL: name: args_i32
-; CHECK: %[[ARG0:[0-9]+]](s32) = COPY %w0
-; CHECK: %{{[0-9]+}}(s32) = COPY %w1
-; CHECK: %{{[0-9]+}}(s32) = COPY %w2
-; CHECK: %{{[0-9]+}}(s32) = COPY %w3
-; CHECK: %{{[0-9]+}}(s32) = COPY %w4
-; CHECK: %{{[0-9]+}}(s32) = COPY %w5
-; CHECK: %{{[0-9]+}}(s32) = COPY %w6
-; CHECK: %{{[0-9]+}}(s32) = COPY %w7
+; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY %w0
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w1
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w2
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w3
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w4
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w5
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w6
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w7
 ; CHECK: %w0 = COPY %[[ARG0]]
 
 define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
@@ -20,14 +20,14 @@ define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
 }
 
 ; CHECK-LABEL: name: args_i64
-; CHECK: %[[ARG0:[0-9]+]](s64) = COPY %x0
-; CHECK: %{{[0-9]+}}(s64) = COPY %x1
-; CHECK: %{{[0-9]+}}(s64) = COPY %x2
-; CHECK: %{{[0-9]+}}(s64) = COPY %x3
-; CHECK: %{{[0-9]+}}(s64) = COPY %x4
-; CHECK: %{{[0-9]+}}(s64) = COPY %x5
-; CHECK: %{{[0-9]+}}(s64) = COPY %x6
-; CHECK: %{{[0-9]+}}(s64) = COPY %x7
+; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %x0
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x1
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x2
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x3
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x4
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x5
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x6
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x7
 ; CHECK: %x0 = COPY %[[ARG0]]
 define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
                      i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
@@ -36,14 +36,14 @@ define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
 
 
 ; CHECK-LABEL: name: args_ptrs
-; CHECK: %[[ARG0:[0-9]+]](p0) = COPY %x0
-; CHECK: %{{[0-9]+}}(p0) = COPY %x1
-; CHECK: %{{[0-9]+}}(p0) = COPY %x2
-; CHECK: %{{[0-9]+}}(p0) = COPY %x3
-; CHECK: %{{[0-9]+}}(p0) = COPY %x4
-; CHECK: %{{[0-9]+}}(p0) = COPY %x5
-; CHECK: %{{[0-9]+}}(p0) = COPY %x6
-; CHECK: %{{[0-9]+}}(p0) = COPY %x7
+; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY %x0
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x1
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x2
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x3
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x4
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x5
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x6
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x7
 ; CHECK: %x0 = COPY %[[ARG0]]
 define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3,
                       [3 x float]* %x4, double* %x5, i8* %x6, i8* %x7) {
@@ -51,27 +51,29 @@ define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3,
 }
 
 ; CHECK-LABEL: name: args_arr
-; CHECK: %[[ARG0:[0-9]+]](s64) = COPY %d0
+; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %d0
 ; CHECK: %d0 = COPY %[[ARG0]]
 define [1 x double] @args_arr([1 x double] %d0) {
   ret [1 x double] %d0
 }
 
 ; CHECK-LABEL: name: test_varargs
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: [[D_ONE:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
-; CHECK: [[TWELVE:%[0-9]+]](s64) = G_CONSTANT i64 12
-; CHECK: [[THREE:%[0-9]+]](s8) = G_CONSTANT i8 3
-; CHECK: [[ONE:%[0-9]+]](s16) = G_CONSTANT i16 1
-; CHECK: [[FOUR:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[F_ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-; CHECK: [[TWO:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[D_ONE:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+; CHECK: [[TWELVE:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+; CHECK: [[THREE:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
+; CHECK: [[ONE:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+; CHECK: [[FOUR:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
 
 ; CHECK: %w0 = COPY [[ANSWER]]
 ; CHECK: %d0 = COPY [[D_ONE]]
 ; CHECK: %x1 = COPY [[TWELVE]]
-; CHECK: %w2 = COPY [[THREE]](s8)
-; CHECK: %w3 = COPY [[ONE]](s16)
+; CHECK: [[THREE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[THREE]]
+; CHECK: %w2 = COPY [[THREE_TMP]](s32)
+; CHECK: [[ONE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[ONE]]
+; CHECK: %w3 = COPY [[ONE_TMP]](s32)
 ; CHECK: %w4 = COPY [[FOUR]](s32)
 ; CHECK: %s1 = COPY [[F_ONE]](s32)
 ; CHECK: %d2 = COPY [[TWO]](s64)
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index 48f500eb36b5..86ac5507a407 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -3,6 +3,7 @@
 ; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
 ; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
 ; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
+; RUN: not llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN
 ; This file checks that the fallback path to selection dag works.
 ; The test is fragile in the sense that it must be updated to expose
 ; something that fails with global-isel.
@@ -12,6 +13,8 @@
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--"
 
+; BIG-ENDIAN: unable to translate in big endian mode
+
 ; We use __fixunstfti as the common denominator for __fixunstfti on Linux and
 ; ___fixunstfti on iOS
 ; ERROR: unable to lower arguments: i128 (i128)* (in function: ABIi128)
@@ -43,7 +46,7 @@ define [1 x double] @constant() {
   ; The key problem here is that we may fail to create an MBB referenced by a
   ; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things
   ; happen.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %vreg5, %vreg2; mem:ST4[%addr] GPR:%vreg5,%vreg2 (in function: pending_phis)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %6(s32), %2(p0); mem:ST4[%addr] GPR:%6,%2 (in function: pending_phis)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for pending_phis
 ; FALLBACK-WITH-REPORT-OUT-LABEL: pending_phis:
 define i32 @pending_phis(i1 %tst, i32 %val, i32* %addr) {
@@ -63,37 +66,21 @@ false:
 }
 
   ; General legalizer inability to handle types whose size wasn't a power of 2.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(s42) = G_LOAD %vreg0; mem:LD6[%addr](align=8) (in function: odd_type)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1(s42), %0(p0); mem:ST6[%addr](align=8) (in function: odd_type)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type
 ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type:
 define void @odd_type(i42* %addr) {
   %val42 = load i42, i42* %addr
+  store i42 %val42, i42* %addr
   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(<7 x s32>) = G_LOAD %vreg0; mem:LD28[%addr](align=32) (in function: odd_vector)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1(<7 x s32>), %0(p0); mem:ST28[%addr](align=32) (in function: odd_vector)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector
 ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector:
 define void @odd_vector(<7 x i32>* %addr) {
   %vec = load <7 x i32>, <7 x i32>* %addr
-  ret void
-}
-
-  ; RegBankSelect crashed when given invalid mappings, and AArch64's
-  ; implementation produce valid-but-nonsense mappings for G_SEQUENCE.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
-; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_mapping
-; FALLBACK-WITH-REPORT-OUT-LABEL: sequence_mapping:
-define void @sequence_mapping([2 x i64] %in) {
-  ret void
-}
-
-  ; Legalizer was asserting when it enountered an unexpected default action.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
-; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for legal_default
-; FALLBACK-WITH-REPORT-LABEL: legal_default:
-define void @legal_default([8 x i8] %in) {
-  insertvalue { [4 x i8], [8 x i8], [4 x i8] } undef, [8 x i8] %in, 1
+  store <7 x i32> %vec, <7 x i32>* %addr
   ret void
 }
 
@@ -107,7 +94,7 @@ define i128 @sequence_sizes([8 x i8] %in) {
 }
 
 ; Just to make sure we don't accidentally emit a normal load/store.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: %vreg2<def>(s64) = G_LOAD %vreg0; mem:LD8[%addr] GPR:%vreg2,%vreg0 (in function: atomic_ops)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: %2:gpr(s64) = G_LOAD %0(p0); mem:LD8[%addr] GPR:%2,%0 (in function: atomic_ops)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for atomic_ops
 ; FALLBACK-WITH-REPORT-LABEL: atomic_ops:
 define i64 @atomic_ops(i64* %addr) {
@@ -148,14 +135,14 @@ continue:
 }
 
 ; Check that we fallback on invoke translation failures.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(s128) = G_FCONSTANT quad 2
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0:_(s128) = G_FCONSTANT quad 2
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_quad_dump
 ; FALLBACK-WITH-REPORT-OUT-LABEL: test_quad_dump:
 define fp128 @test_quad_dump() {
   ret fp128 0xL00000000000000004000000000000000
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg2; (in function: vector_of_pointers_extractelement)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0:_(p0) = G_EXTRACT_VECTOR_ELT %1(<2 x p0>), %2(s32); (in function: vector_of_pointers_extractelement)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement
 ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement:
 @var = global <2 x i16*> zeroinitializer
@@ -164,6 +151,7 @@ define void @vector_of_pointers_extractelement() {
 
 block:
   %dummy = extractelement <2 x i16*> %vec, i32 0
+  store i16* %dummy, i16** undef
   ret void
 
 end:
@@ -171,7 +159,7 @@ end:
   br label %block
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(<2 x p0>) = G_INSERT_VECTOR_ELT %vreg1, %vreg2, %vreg3; (in function: vector_of_pointers_insertelement
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0(<2 x p0>), %4(p0); mem:ST16[undef] (in function: vector_of_pointers_insertelement)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
 ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
 define void @vector_of_pointers_insertelement() {
@@ -179,9 +167,82 @@ define void @vector_of_pointers_insertelement() {
 
 block:
   %dummy = insertelement <2 x i16*> %vec, i16* null, i32 0
+  store <2 x i16*> %dummy, <2 x i16*>* undef
   ret void
 
 end:
   %vec = load <2 x i16*>, <2 x i16*>* undef
   br label %block
 }
+
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1(s96), %3(p0); mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_insertvalue_narrowing
+; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_insertvalue_narrowing:
+%struct96 = type { float, float, float }
+define void @nonpow2_insertvalue_narrowing(float %a) {
+  %dummy = insertvalue %struct96 undef, float %a, 0
+  store %struct96 %dummy, %struct96* undef
+  ret void
+}
+
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_add_narrowing
+; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_add_narrowing:
+define void @nonpow2_add_narrowing() {
+  %a = add i128 undef, undef
+  %b = trunc i128 %a to i96
+  %dummy = add i96 %b, %b
+  store i96 %dummy, i96* undef
+  ret void
+}
+
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_or_narrowing
+; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_or_narrowing:
+define void @nonpow2_or_narrowing() {
+  %a = add i128 undef, undef
+  %b = trunc i128 %a to i96
+  %dummy = or i96 %b, %b
+  store i96 %dummy, i96* undef
+  ret void
+}
+
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0, %1; mem:ST12[undef](align=16) (in function: nonpow2_load_narrowing)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_load_narrowing
+; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_load_narrowing:
+define void @nonpow2_load_narrowing() {
+  %dummy = load i96, i96* undef
+  store i96 %dummy, i96* undef
+  ret void
+}
+
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3(s96), %0(p0); mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_store_narrowing
+; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_store_narrowing:
+define void @nonpow2_store_narrowing(i96* %c) {
+  %a = add i128 undef, undef
+  %b = trunc i128 %a to i96
+  store i96 %b, i96* %c
+  ret void
+}
+
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0(s96), %1(p0); mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_constant_narrowing
+; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_constant_narrowing:
+define void @nonpow2_constant_narrowing() {
+  store i96 0, i96* undef
+  ret void
+}
+
+; Currently can't handle vector lengths that aren't an exact multiple of
+; natively supported vector lengths. Test that the fall-back works for those.
+; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: <unknown>:0:0: unable to legalize instruction: %1(<7 x s64>) = G_ADD %0, %0; (in function: nonpow2_vector_add_fewerelements
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s64) = G_EXTRACT_VECTOR_ELT %1(<7 x s64>), %3(s64); (in function: nonpow2_vector_add_fewerelements)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_vector_add_fewerelements
+; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_vector_add_fewerelements:
+define void @nonpow2_vector_add_fewerelements() {
+  %dummy = add <7 x i64> undef, undef
+  %ex = extractelement <7 x i64> %dummy, i64 0
+  store i64 %ex, i64* undef
+  ret void
+}
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
index cd3ea9715e0f..62abf3d81d58 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
@@ -7,8 +7,8 @@
 ; CHECK:  - { id: 0, name: StackGuardSlot,  type: default, offset: 0, size: 8, alignment: 8,
 ; CHECK-NOT: id: 1
 
-; CHECK: [[GUARD_SLOT:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
-; CHECK: [[GUARD:%[0-9]+]](p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
+; CHECK: [[GUARD_SLOT:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
+; CHECK: [[GUARD:%[0-9]+]]:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
 ; CHECK: G_STORE [[GUARD]](p0), [[GUARD_SLOT]](p0) :: (volatile store 8 into %stack.0.StackGuardSlot)
 declare void @llvm.stackprotector(i8*, i8**)
 define void @test_stack_guard_remat2() {
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 10ce87c2a187..e78683279754 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -7,20 +7,20 @@ target triple = "aarch64--"
 
 ; Tests for add.
 ; CHECK-LABEL: name: addi64
-; CHECK:      [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_ADD [[ARG1]], [[ARG2]]
+; CHECK:      [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
-; CHECK-NEXT: RET_ReallyLR implicit %x0 
+; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @addi64(i64 %arg1, i64 %arg2) {
   %res = add i64 %arg1, %arg2
   ret i64 %res
 }
 
 ; CHECK-LABEL: name: muli64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_MUL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_MUL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @muli64(i64 %arg1, i64 %arg2) {
@@ -32,16 +32,19 @@ define i64 @muli64(i64 %arg1, i64 %arg2) {
 ; CHECK-LABEL: name: allocai64
 ; CHECK: stack:
 ; CHECK-NEXT:   - { id: 0, name: ptr1, type: default, offset: 0, size: 8, alignment: 8,
-; CHECK-NEXT:       callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT:       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+; CHECK-NEXT: di-variable: '', di-expression: '', di-location: '' }
 ; CHECK-NEXT:   - { id: 1, name: ptr2, type: default, offset: 0, size: 8, alignment: 1,
-; CHECK-NEXT:       callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT:       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+; CHECK-NEXT:       di-variable: '', di-expression: '', di-location: '' }
 ; CHECK-NEXT:   - { id: 2, name: ptr3, type: default, offset: 0, size: 128, alignment: 8,
-; CHECK-NEXT:       callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT:       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+; CHECK-NEXT:       di-variable: '', di-expression: '', di-location: '' }
 ; CHECK-NEXT:   - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8,
-; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.0.ptr1
-; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.1.ptr2
-; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.2.ptr3
-; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.3.ptr4
+; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.ptr1
+; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.1.ptr2
+; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.2.ptr3
+; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.3.ptr4
 define void @allocai64() {
   %ptr1 = alloca i64
   %ptr2 = alloca i64, align 1
@@ -55,19 +58,19 @@ define void @allocai64() {
 ; CHECK: body:
 ;
 ; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+}}.entry:
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
 ;
 ; Make sure we have one successor and only one.
-; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+.bb2]](0x80000000)
+; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+]](0x80000000)
 ;
 ; Check that we emit the correct branch.
 ; CHECK: G_BR %[[BB2]]
 ;
 ; Check that end contains the return instruction.
-; CHECK: [[END:bb.[0-9]+.end]]:
+; CHECK: [[END:bb.[0-9]+]].{{[a-zA-Z0-9.]+}}:
 ; CHECK-NEXT: RET_ReallyLR
 ;
-; CHECK: {{bb.[0-9]+}}.bb2:
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
 ; CHECK-NEXT: successors: %[[END]](0x80000000)
 ; CHECK: G_BR %[[END]]
 define void @uncondbr() {
@@ -81,11 +84,11 @@ bb2:
 
 ; CHECK-LABEL: name: uncondbr_fallthrough
 ; CHECK: body:
-; CHECK: {{bb.[0-9]+}}.entry:
-; CHECK-NEXT: successors: %[[END:bb.[0-9]+.end]](0x80000000)
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
 ; We don't emit a branch here, as we can fallthrough to the successor.
 ; CHECK-NOT: G_BR
-; CHECK: [[END]]:
+; CHECK: [[END]].{{[a-zA-Z0-9.]+}}:
 ; CHECK-NEXT: RET_ReallyLR
 define void @uncondbr_fallthrough() {
 entry:
@@ -99,22 +102,22 @@ end:
 ; CHECK: body:
 ;
 ; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}):
+; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
 ; Make sure we have two successors
-; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000),
-; CHECK:                  %[[FALSE:bb.[0-9]+.false]](0x40000000)
+; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
+; CHECK:                  %[[FALSE:bb.[0-9]+]](0x40000000)
 ;
-; CHECK: [[ADDR:%.*]](p0) = COPY %x0
+; CHECK: [[ADDR:%.*]]:_(p0) = COPY %x0
 ;
 ; Check that we emit the correct branch.
-; CHECK: [[TST:%.*]](s1) = G_LOAD [[ADDR]](p0)
+; CHECK: [[TST:%.*]]:_(s1) = G_LOAD [[ADDR]](p0)
 ; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
 ; CHECK: G_BR %[[FALSE]]
 ;
 ; Check that each successor contains the return instruction.
-; CHECK: [[TRUE]]:
+; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:
 ; CHECK-NEXT: RET_ReallyLR
-; CHECK: [[FALSE]]:
+; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:
 ; CHECK-NEXT: RET_ReallyLR
 define void @condbr(i1* %tstaddr) {
   %tst = load i1, i1* %tstaddr
@@ -130,44 +133,44 @@ false:
 ; CHECK-LABEL: name: switch
 ; CHECK: body:
 ;
-; CHECK: {{bb.[0-9]+.entry}}:
-; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+.case100]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
-; CHECK: %0(s32) = COPY %w0
-; CHECK: %[[reg100:[0-9]+]](s32) = G_CONSTANT i32 100
-; CHECK: %[[reg200:[0-9]+]](s32) = G_CONSTANT i32 200
-; CHECK: %[[reg0:[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: %[[reg1:[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: %[[reg2:[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: %[[regicmp100:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg100]](s32), %0
+; CHECK: bb.{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+]](0x40000000)
+; CHECK: %0:_(s32) = COPY %w0
+; CHECK: %[[reg100:[0-9]+]]:_(s32) = G_CONSTANT i32 100
+; CHECK: %[[reg200:[0-9]+]]:_(s32) = G_CONSTANT i32 200
+; CHECK: %[[reg0:[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: %[[reg1:[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: %[[reg2:[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: %[[regicmp100:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg100]](s32), %0
 ; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]]
 ; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]]
 ;
-; CHECK: [[BB_NOTCASE100_CHECKNEXT]]:
-; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
-; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
+; CHECK: [[BB_NOTCASE100_CHECKNEXT]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+]](0x40000000)
+; CHECK: %[[regicmp200:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
 ; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]]
 ; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]]
 ;
-; CHECK: [[BB_NOTCASE200_CHECKNEXT]]:
-; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+.default]](0x80000000)
+; CHECK: [[BB_NOTCASE200_CHECKNEXT]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+]](0x80000000)
 ; CHECK: G_BR %[[BB_DEFAULT]]
 ;
-; CHECK: [[BB_DEFAULT]]:
-; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
-; CHECK: %[[regretdefault:[0-9]+]](s32) = G_ADD %0, %[[reg0]]
+; CHECK: [[BB_DEFAULT]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000)
+; CHECK: %[[regretdefault:[0-9]+]]:_(s32) = G_ADD %0, %[[reg0]]
 ; CHECK: G_BR %[[BB_RET]]
 ;
-; CHECK: [[BB_CASE100]]:
-; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
-; CHECK: %[[regretc100:[0-9]+]](s32) = G_ADD %0, %[[reg1]]
+; CHECK: [[BB_CASE100]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000)
+; CHECK: %[[regretc100:[0-9]+]]:_(s32) = G_ADD %0, %[[reg1]]
 ; CHECK: G_BR %[[BB_RET]]
 ;
-; CHECK: [[BB_CASE200]]:
+; CHECK: [[BB_CASE200]].{{[a-zA-Z0-9.]+}}:
 ; CHECK-NEXT: successors: %[[BB_RET]](0x80000000)
-; CHECK: %[[regretc200:[0-9]+]](s32) = G_ADD %0, %[[reg2]]
+; CHECK: %[[regretc200:[0-9]+]]:_(s32) = G_ADD %0, %[[reg2]]
 ;
-; CHECK: [[BB_RET]]:
-; CHECK-NEXT: %[[regret:[0-9]+]](s32) = PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
+; CHECK: [[BB_RET]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: %[[regret:[0-9]+]]:_(s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
 ; CHECK:  %w0 = COPY %[[regret]](s32)
 ; CHECK:  RET_ReallyLR implicit %w0
 ;
@@ -199,16 +202,16 @@ return:
   ; %entry block is no longer a predecessor for the phi instruction. We need to
   ; use the correct lowered MachineBasicBlock instead.
 ; CHECK-LABEL: name: test_cfg_remap
-; CHECK: {{bb.[0-9]+.entry}}:
-; CHECK-NEXT: successors: %{{bb.[0-9]+.next}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+.entry]](0x40000000)
-; CHECK: [[NOTCASE1_BLOCK]]:
-; CHECK-NEXT: successors: %{{bb.[0-9]+.other}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]](0x40000000)
-; CHECK: [[NOTCASE57_BLOCK]]:
-; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+.phi.block]](0x80000000)
+; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %{{bb.[0-9]+}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+]](0x40000000)
+; CHECK: [[NOTCASE1_BLOCK]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %{{bb.[0-9]+}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+]](0x40000000)
+; CHECK: [[NOTCASE57_BLOCK]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+]](0x80000000)
 ; CHECK: G_BR %[[PHI_BLOCK]]
 ;
-; CHECK: [[PHI_BLOCK]]:
-; CHECK-NEXT: PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32),
+; CHECK: [[PHI_BLOCK]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: G_PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+]], %{{.*}}(s32),
 ;
 define i32 @test_cfg_remap(i32 %in) {
 entry:
@@ -227,7 +230,7 @@ phi.block:
 }
 
 ; CHECK-LABEL: name: test_cfg_remap_multiple_preds
-; CHECK: PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}.entry, [[ENTRY]](s32), %bb.{{[0-9]+}}.entry
+; CHECK: G_PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}, [[ENTRY]](s32), %bb.{{[0-9]+}}
 define i32 @test_cfg_remap_multiple_preds(i32 %in) {
 entry:
   switch i32 %in, label %odd [i32 1, label %next
@@ -253,19 +256,19 @@ phi.block:
 ; CHECK: body:
 ;
 ; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+.entry}}:
+; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:
 ; Make sure we have one successor
-; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+.L1]](0x80000000)
+; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000)
 ; CHECK-NOT: G_BR
 ;
 ; Check basic block L1 has 2 successors: BBL1 and BBL2
-; CHECK: [[BB_L1]] (address-taken):
+; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (address-taken):
 ; CHECK-NEXT: successors: %[[BB_L1]](0x40000000),
-; CHECK:                  %[[BB_L2:bb.[0-9]+.L2]](0x40000000)
+; CHECK:                  %[[BB_L2:bb.[0-9]+]](0x40000000)
 ; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0)
 ;
 ; Check basic block L2 is the return basic block
-; CHECK: [[BB_L2]] (address-taken):
+; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (address-taken):
 ; CHECK-NEXT: RET_ReallyLR
 
 @indirectbr.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@indirectbr, %L1), i8* blockaddress(@indirectbr, %L2), i8* null], align 8
@@ -286,9 +289,9 @@ L2:                                               ; preds = %L1
 
 ; Tests for or.
 ; CHECK-LABEL: name: ori64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_OR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_OR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @ori64(i64 %arg1, i64 %arg2) {
@@ -297,9 +300,9 @@ define i64 @ori64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: ori32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_OR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_OR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @ori32(i32 %arg1, i32 %arg2) {
@@ -309,9 +312,9 @@ define i32 @ori32(i32 %arg1, i32 %arg2) {
 
 ; Tests for xor.
 ; CHECK-LABEL: name: xori64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_XOR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_XOR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @xori64(i64 %arg1, i64 %arg2) {
@@ -320,9 +323,9 @@ define i64 @xori64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: xori32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_XOR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_XOR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @xori32(i32 %arg1, i32 %arg2) {
@@ -332,9 +335,9 @@ define i32 @xori32(i32 %arg1, i32 %arg2) {
 
 ; Tests for and.
 ; CHECK-LABEL: name: andi64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_AND [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_AND [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @andi64(i64 %arg1, i64 %arg2) {
@@ -343,9 +346,9 @@ define i64 @andi64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: andi32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_AND [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_AND [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @andi32(i32 %arg1, i32 %arg2) {
@@ -355,9 +358,9 @@ define i32 @andi32(i32 %arg1, i32 %arg2) {
 
 ; Tests for sub.
 ; CHECK-LABEL: name: subi64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_SUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @subi64(i64 %arg1, i64 %arg2) {
@@ -366,9 +369,9 @@ define i64 @subi64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: subi32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @subi32(i32 %arg1, i32 %arg2) {
@@ -377,8 +380,8 @@ define i32 @subi32(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: ptrtoint
-; CHECK: [[ARG1:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[ARG1]]
+; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[ARG1]]
 ; CHECK: %x0 = COPY [[RES]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64 @ptrtoint(i64* %a) {
@@ -387,8 +390,8 @@ define i64 @ptrtoint(i64* %a) {
 }
 
 ; CHECK-LABEL: name: inttoptr
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[RES:%[0-9]+]](p0) = G_INTTOPTR [[ARG1]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[RES:%[0-9]+]]:_(p0) = G_INTTOPTR [[ARG1]]
 ; CHECK: %x0 = COPY [[RES]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64* @inttoptr(i64 %a) {
@@ -397,7 +400,7 @@ define i64* @inttoptr(i64 %a) {
 }
 
 ; CHECK-LABEL: name: trivial_bitcast
-; CHECK: [[ARG1:%[0-9]+]](p0) = COPY %x0
+; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY %x0
 ; CHECK: %x0 = COPY [[ARG1]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64* @trivial_bitcast(i8* %a) {
@@ -406,13 +409,13 @@ define i64* @trivial_bitcast(i8* %a) {
 }
 
 ; CHECK-LABEL: name: trivial_bitcast_with_copy
-; CHECK:     [[A:%[0-9]+]](p0) = COPY %x0
-; CHECK:     G_BR %[[CAST:bb\.[0-9]+.cast]]
+; CHECK:     [[A:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK:     G_BR %[[CAST:bb\.[0-9]+]]
 
-; CHECK: [[END:bb\.[0-9]+.end]]:
+; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}:
 
-; CHECK: [[CAST]]:
-; CHECK:     {{%[0-9]+}}(p0) = COPY [[A]]
+; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}:
+; CHECK:     {{%[0-9]+}}:_(p0) = COPY [[A]]
 ; CHECK:     G_BR %[[END]]
 define i64* @trivial_bitcast_with_copy(i8* %a) {
   br label %cast
@@ -426,9 +429,9 @@ cast:
 }
 
 ; CHECK-LABEL: name: bitcast
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[RES1:%[0-9]+]](<2 x s32>) = G_BITCAST [[ARG1]]
-; CHECK: [[RES2:%[0-9]+]](s64) = G_BITCAST [[RES1]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[RES1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(s64) = G_BITCAST [[RES1]]
 ; CHECK: %x0 = COPY [[RES2]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64 @bitcast(i64 %a) {
@@ -438,10 +441,10 @@ define i64 @bitcast(i64 %a) {
 }
 
 ; CHECK-LABEL: name: trunc
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_LOAD
-; CHECK: [[RES1:%[0-9]+]](s8) = G_TRUNC [[ARG1]]
-; CHECK: [[RES2:%[0-9]+]](<4 x s16>) = G_TRUNC [[VEC]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_LOAD
+; CHECK: [[RES1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[VEC]]
 define void @trunc(i64 %a) {
   %vecptr = alloca <4 x i32>
   %vec = load <4 x i32>, <4 x i32>* %vecptr
@@ -451,13 +454,13 @@ define void @trunc(i64 %a) {
 }
 
 ; CHECK-LABEL: name: load
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[ADDR42:%[0-9]+]](p42) = COPY %x1
-; CHECK: [[VAL1:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16)
-; CHECK: [[VAL2:%[0-9]+]](s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42)
-; CHECK: [[SUM2:%.*]](s64) = G_ADD [[VAL1]], [[VAL2]]
-; CHECK: [[VAL3:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
-; CHECK: [[SUM3:%[0-9]+]](s64) = G_ADD [[SUM2]], [[VAL3]]
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
+; CHECK: [[VAL1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16)
+; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42)
+; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]
+; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
+; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]
 ; CHECK: %x0 = COPY [[SUM3]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) {
@@ -472,10 +475,10 @@ define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) {
 }
 
 ; CHECK-LABEL: name: store
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[ADDR42:%[0-9]+]](p42) = COPY %x1
-; CHECK: [[VAL1:%[0-9]+]](s64) = COPY %x2
-; CHECK: [[VAL2:%[0-9]+]](s64) = COPY %x3
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
+; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY %x2
+; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY %x3
 ; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 16)
 ; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store 8 into %ir.addr42)
 ; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store 8 into %ir.addr)
@@ -489,12 +492,12 @@ define void @store(i64* %addr, i64 addrspace(42)* %addr42, i64 %val1, i64 %val2)
 }
 
 ; CHECK-LABEL: name: intrinsics
-; CHECK: [[CUR:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[BITS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[CREG:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[PTR:%[0-9]+]](p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]]
-; CHECK: [[PTR_VEC:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.ptr.vec
-; CHECK: [[VEC:%[0-9]+]](<8 x s8>) = G_LOAD [[PTR_VEC]]
+; CHECK: [[CUR:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[BITS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[CREG:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]]
+; CHECK: [[PTR_VEC:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr.vec
+; CHECK: [[VEC:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[PTR_VEC]]
 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x s8>), [[VEC]](<8 x s8>), [[PTR]](p0)
 ; CHECK: RET_ReallyLR
 declare i8* @llvm.returnaddress(i32)
@@ -509,16 +512,16 @@ define void @intrinsics(i32 %cur, i32 %bits) {
 }
 
 ; CHECK-LABEL: name: test_phi
-; CHECK:     G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+.true]]
-; CHECK:     G_BR %[[FALSE:bb\.[0-9]+.false]]
+; CHECK:     G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+]]
+; CHECK:     G_BR %[[FALSE:bb\.[0-9]+]]
 
-; CHECK: [[TRUE]]:
-; CHECK:     [[RES1:%[0-9]+]](s32) = G_LOAD
+; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:
+; CHECK:     [[RES1:%[0-9]+]]:_(s32) = G_LOAD
 
-; CHECK: [[FALSE]]:
-; CHECK:     [[RES2:%[0-9]+]](s32) = G_LOAD
+; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:
+; CHECK:     [[RES2:%[0-9]+]]:_(s32) = G_LOAD
 
-; CHECK:     [[RES:%[0-9]+]](s32) = PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
+; CHECK:     [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
 ; CHECK:     %w0 = COPY [[RES]]
 define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
   br i1 %tst, label %true, label %false
@@ -548,13 +551,13 @@ define void @unreachable(i32 %a) {
   ; It's important that constants are after argument passing, but before the
   ; rest of the entry block.
 ; CHECK-LABEL: name: constant_int
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[ONE:%[0-9]+]](s32) = G_CONSTANT i32 1
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
 
-; CHECK: {{bb.[0-9]+}}.next:
-; CHECK: [[SUM1:%[0-9]+]](s32) = G_ADD [[IN]], [[ONE]]
-; CHECK: [[SUM2:%[0-9]+]](s32) = G_ADD [[IN]], [[ONE]]
-; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[SUM1]], [[SUM2]]
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
+; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
+; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]
 ; CHECK: %w0 = COPY [[RES]]
 
 define i32 @constant_int(i32 %in) {
@@ -568,24 +571,24 @@ next:
 }
 
 ; CHECK-LABEL: name: constant_int_start
-; CHECK: [[TWO:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[TWO]], [[ANSWER]]
+; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[TWO]], [[ANSWER]]
 define i32 @constant_int_start() {
   %res = add i32 2, 42
   ret i32 %res
 }
 
 ; CHECK-LABEL: name: test_undef
-; CHECK: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
+; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
 ; CHECK: %w0 = COPY [[UNDEF]]
 define i32 @test_undef() {
   ret i32 undef
 }
 
 ; CHECK-LABEL: name: test_constant_inttoptr
-; CHECK: [[ONE:%[0-9]+]](s64) = G_CONSTANT i64 1
-; CHECK: [[PTR:%[0-9]+]](p0) = G_INTTOPTR [[ONE]]
+; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ONE]]
 ; CHECK: %x0 = COPY [[PTR]]
 define i8* @test_constant_inttoptr() {
   ret i8* inttoptr(i64 1 to i8*)
@@ -594,15 +597,15 @@ define i8* @test_constant_inttoptr() {
   ; This failed purely because the Constant -> VReg map was kept across
   ; functions, so reuse the "i64 1" from above.
 ; CHECK-LABEL: name: test_reused_constant
-; CHECK: [[ONE:%[0-9]+]](s64) = G_CONSTANT i64 1
+; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
 ; CHECK: %x0 = COPY [[ONE]]
 define i64 @test_reused_constant() {
   ret i64 1
 }
 
 ; CHECK-LABEL: name: test_sext
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RES:%[0-9]+]](s64) = G_SEXT [[IN]]
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SEXT [[IN]]
 ; CHECK: %x0 = COPY [[RES]]
 define i64 @test_sext(i32 %in) {
   %res = sext i32 %in to i64
@@ -610,8 +613,8 @@ define i64 @test_sext(i32 %in) {
 }
 
 ; CHECK-LABEL: name: test_zext
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RES:%[0-9]+]](s64) = G_ZEXT [[IN]]
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ZEXT [[IN]]
 ; CHECK: %x0 = COPY [[RES]]
 define i64 @test_zext(i32 %in) {
   %res = zext i32 %in to i64
@@ -619,9 +622,9 @@ define i64 @test_zext(i32 %in) {
 }
 
 ; CHECK-LABEL: name: test_shl
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SHL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SHL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_shl(i32 %arg1, i32 %arg2) {
@@ -631,9 +634,9 @@ define i32 @test_shl(i32 %arg1, i32 %arg2) {
 
 
 ; CHECK-LABEL: name: test_lshr
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_LSHR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_LSHR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_lshr(i32 %arg1, i32 %arg2) {
@@ -642,9 +645,9 @@ define i32 @test_lshr(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_ashr
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_ASHR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_ASHR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_ashr(i32 %arg1, i32 %arg2) {
@@ -653,9 +656,9 @@ define i32 @test_ashr(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_sdiv
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
@@ -664,9 +667,9 @@ define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_udiv
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_udiv(i32 %arg1, i32 %arg2) {
@@ -675,9 +678,9 @@ define i32 @test_udiv(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_srem
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_srem(i32 %arg1, i32 %arg2) {
@@ -686,9 +689,9 @@ define i32 @test_srem(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_urem
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_urem(i32 %arg1, i32 %arg2) {
@@ -697,15 +700,15 @@ define i32 @test_urem(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_constant_null
-; CHECK: [[NULL:%[0-9]+]](p0) = G_CONSTANT i64 0
+; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
 ; CHECK: %x0 = COPY [[NULL]]
 define i8* @test_constant_null() {
   ret i8* null
 }
 
 ; CHECK-LABEL: name: test_struct_memops
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (load 8 from  %ir.addr, align 4)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from  %ir.addr, align 4)
 ; CHECK: G_STORE [[VAL]](s64), [[ADDR]](p0) :: (store 8 into  %ir.addr, align 4)
 define void @test_struct_memops({ i8, i32 }* %addr) {
   %val = load { i8, i32 }, { i8, i32 }* %addr
@@ -714,8 +717,8 @@ define void @test_struct_memops({ i8, i32 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_i1_memops
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s1) = G_LOAD [[ADDR]](p0) :: (load 1 from  %ir.addr)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s1) = G_LOAD [[ADDR]](p0) :: (load 1 from  %ir.addr)
 ; CHECK: G_STORE [[VAL]](s1), [[ADDR]](p0) :: (store 1 into  %ir.addr)
 define void @test_i1_memops(i1* %addr) {
   %val = load i1, i1* %addr
@@ -724,10 +727,10 @@ define void @test_i1_memops(i1* %addr) {
 }
 
 ; CHECK-LABEL: name: int_comparison
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
 define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
   %res = icmp ne i32 %a, %b
@@ -736,10 +739,10 @@ define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
 }
 
 ; CHECK-LABEL: name: ptr_comparison
-; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
 define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
   %res = icmp eq i8* %a, %b
@@ -748,9 +751,9 @@ define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
 }
 
 ; CHECK-LABEL: name: test_fadd
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FADD [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FADD [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_fadd(float %arg1, float %arg2) {
@@ -759,9 +762,9 @@ define float @test_fadd(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_fsub
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FSUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FSUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_fsub(float %arg1, float %arg2) {
@@ -770,9 +773,9 @@ define float @test_fsub(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_fmul
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FMUL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FMUL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_fmul(float %arg1, float %arg2) {
@@ -781,9 +784,9 @@ define float @test_fmul(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_fdiv
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_fdiv(float %arg1, float %arg2) {
@@ -792,9 +795,9 @@ define float @test_fdiv(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_frem
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_frem(float %arg1, float %arg2) {
@@ -803,13 +806,13 @@ define float @test_frem(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_sadd_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SADDO [[LHS]], [[RHS]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SADDO [[LHS]], [[RHS]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
 define void @test_sadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
@@ -819,14 +822,14 @@ define void @test_sadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_uadd_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[ZERO:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
 define void @test_uadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
@@ -836,13 +839,13 @@ define void @test_uadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_ssub_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SSUBO [[LHS]], [[RHS]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SSUBO [[LHS]], [[RHS]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)
 define void @test_ssub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
@@ -852,14 +855,14 @@ define void @test_ssub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
 }
 
 ; CHECK-LABEL: name: test_usub_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[ZERO:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)
 define void @test_usub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
@@ -869,13 +872,13 @@ define void @test_usub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
 }
 
 ; CHECK-LABEL: name: test_smul_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SMULO [[LHS]], [[RHS]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SMULO [[LHS]], [[RHS]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
 define void @test_smul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
@@ -885,13 +888,13 @@ define void @test_smul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_umul_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UMULO [[LHS]], [[RHS]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UMULO [[LHS]], [[RHS]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
 define void @test_umul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
@@ -901,8 +904,8 @@ define void @test_umul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_extractvalue
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
-; CHECK: [[RES:%[0-9]+]](s32) = G_EXTRACT [[STRUCT]](s128), 64
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT [[STRUCT]](s128), 64
 ; CHECK: %w0 = COPY [[RES]]
 %struct.nested = type {i8, { i8, i32 }, i32}
 define i32 @test_extractvalue(%struct.nested* %addr) {
@@ -912,8 +915,8 @@ define i32 @test_extractvalue(%struct.nested* %addr) {
 }
 
 ; CHECK-LABEL: name: test_extractvalue_agg
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
-; CHECK: [[RES:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 32
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 32
 ; CHECK: G_STORE [[RES]]
 define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
   %struct = load %struct.nested, %struct.nested* %addr
@@ -923,9 +926,9 @@ define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
 }
 
 ; CHECK-LABEL: name: test_insertvalue
-; CHECK: [[VAL:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
-; CHECK: [[NEWSTRUCT:%[0-9]+]](s128) = G_INSERT [[STRUCT]], [[VAL]](s32), 64
+; CHECK: [[VAL:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
+; CHECK: [[NEWSTRUCT:%[0-9]+]]:_(s128) = G_INSERT [[STRUCT]], [[VAL]](s32), 64
 ; CHECK: G_STORE [[NEWSTRUCT]](s128),
 define void @test_insertvalue(%struct.nested* %addr, i32 %val) {
   %struct = load %struct.nested, %struct.nested* %addr
@@ -936,9 +939,9 @@ define void @test_insertvalue(%struct.nested* %addr, i32 %val) {
 
 define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {
 ; CHECK-LABEL: name: test_trivial_insert
-; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[RES:%[0-9]+]](s64) = COPY [[VAL]](s64)
+; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY [[VAL]](s64)
 ; CHECK: %x0 = COPY [[RES]]
   %res = insertvalue [1 x i64] %s, i64 %val, 0
   ret [1 x i64] %res
@@ -946,18 +949,18 @@ define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {
 
 define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) {
 ; CHECK-LABEL: name: test_trivial_insert_ptr
-; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[VAL]](p0)
+; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[VAL]](p0)
 ; CHECK: %x0 = COPY [[RES]]
   %res = insertvalue [1 x i8*] %s, i8* %val, 0
   ret [1 x i8*] %res
 }
 
 ; CHECK-LABEL: name: test_insertvalue_agg
-; CHECK: [[SMALLSTRUCT:%[0-9]+]](s64) = G_LOAD
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
-; CHECK: [[RES:%[0-9]+]](s128) = G_INSERT [[STRUCT]], [[SMALLSTRUCT]](s64), 32
+; CHECK: [[SMALLSTRUCT:%[0-9]+]]:_(s64) = G_LOAD
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
+; CHECK: [[RES:%[0-9]+]]:_(s128) = G_INSERT [[STRUCT]], [[SMALLSTRUCT]](s64), 32
 ; CHECK: G_STORE [[RES]](s128)
 define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
   %smallstruct = load {i8, i32}, {i8, i32}* %addr2
@@ -968,10 +971,11 @@ define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
 }
 
 ; CHECK-LABEL: name: test_select
-; CHECK: [[TST:%[0-9]+]](s1) = COPY %w0
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w2
-; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w2
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
 ; CHECK: %w0 = COPY [[RES]]
 define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
   %res = select i1 %tst, i32 %lhs, i32 %rhs
@@ -979,10 +983,11 @@ define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
 }
 
 ; CHECK-LABEL: name: test_select_ptr
-; CHECK: [[TST:%[0-9]+]](s1) = COPY %w0
-; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[RES:%[0-9]+]](p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
 ; CHECK: %x0 = COPY [[RES]]
 define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) {
   %res = select i1 %tst, i8* %lhs, i8* %rhs
@@ -990,10 +995,11 @@ define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) {
 }
 
 ; CHECK-LABEL: name: test_select_vec
-; CHECK: [[TST:%[0-9]+]](s1) = COPY %w0
-; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q0
-; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q1
-; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY %q0
+; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY %q1
+; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
 ; CHECK: %q0 = COPY [[RES]]
 define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
   %res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs
@@ -1001,11 +1007,11 @@ define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
 }
 
 ; CHECK-LABEL: name: test_vselect_vec
-; CHECK: [[TST32:%[0-9]+]](<4 x s32>) = COPY %q0
-; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q1
-; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q2
-; CHECK: [[TST:%[0-9]+]](<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
-; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
+; CHECK: [[TST32:%[0-9]+]]:_(<4 x s32>) = COPY %q0
+; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY %q1
+; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY %q2
+; CHECK: [[TST:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
+; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
 ; CHECK: %q0 = COPY [[RES]]
 define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %rhs) {
   %tst = trunc <4 x i32> %tst32 to <4 x i1>
@@ -1014,9 +1020,9 @@ define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %
 }
 
 ; CHECK-LABEL: name: test_fptosi
-; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0)
-; CHECK: [[RES:%[0-9]+]](s64) = G_FPTOSI [[FP]](s32)
+; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOSI [[FP]](s32)
 ; CHECK: %x0 = COPY [[RES]]
 define i64 @test_fptosi(float* %fp.addr) {
   %fp = load float, float* %fp.addr
@@ -1025,9 +1031,9 @@ define i64 @test_fptosi(float* %fp.addr) {
 }
 
 ; CHECK-LABEL: name: test_fptoui
-; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0)
-; CHECK: [[RES:%[0-9]+]](s64) = G_FPTOUI [[FP]](s32)
+; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOUI [[FP]](s32)
 ; CHECK: %x0 = COPY [[RES]]
 define i64 @test_fptoui(float* %fp.addr) {
   %fp = load float, float* %fp.addr
@@ -1036,9 +1042,9 @@ define i64 @test_fptoui(float* %fp.addr) {
 }
 
 ; CHECK-LABEL: name: test_sitofp
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[FP:%[0-9]+]](s64) = G_SITOFP [[IN]](s32)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[FP:%[0-9]+]]:_(s64) = G_SITOFP [[IN]](s32)
 ; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
 define void @test_sitofp(double* %addr, i32 %in) {
   %fp = sitofp i32 %in to double
@@ -1047,9 +1053,9 @@ define void @test_sitofp(double* %addr, i32 %in) {
 }
 
 ; CHECK-LABEL: name: test_uitofp
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[FP:%[0-9]+]](s64) = G_UITOFP [[IN]](s32)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[FP:%[0-9]+]]:_(s64) = G_UITOFP [[IN]](s32)
 ; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
 define void @test_uitofp(double* %addr, i32 %in) {
   %fp = uitofp i32 %in to double
@@ -1058,8 +1064,8 @@ define void @test_uitofp(double* %addr, i32 %in) {
 }
 
 ; CHECK-LABEL: name: test_fpext
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s64) = G_FPEXT [[IN]](s32)
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPEXT [[IN]](s32)
 ; CHECK: %d0 = COPY [[RES]]
 define double @test_fpext(float %in) {
   %res = fpext float %in to double
@@ -1067,8 +1073,8 @@ define double @test_fpext(float %in) {
 }
 
 ; CHECK-LABEL: name: test_fptrunc
-; CHECK: [[IN:%[0-9]+]](s64) = COPY %d0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FPTRUNC [[IN]](s64)
+; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %d0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPTRUNC [[IN]](s64)
 ; CHECK: %s0 = COPY [[RES]]
 define float @test_fptrunc(double %in) {
   %res = fptrunc double %in to float
@@ -1076,8 +1082,8 @@ define float @test_fptrunc(double %in) {
 }
 
 ; CHECK-LABEL: name: test_constant_float
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT float 1.500000e+00
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[TMP:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+00
 ; CHECK: G_STORE [[TMP]](s32), [[ADDR]](p0)
 define void @test_constant_float(float* %addr) {
   store float 1.5, float* %addr
@@ -1085,12 +1091,12 @@ define void @test_constant_float(float* %addr) {
 }
 
 ; CHECK-LABEL: name: float_comparison
-; CHECK: [[LHSADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[RHSADDR:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[BOOLADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[LHS:%[0-9]+]](s32) = G_LOAD [[LHSADDR]](p0)
-; CHECK: [[RHS:%[0-9]+]](s32) = G_LOAD [[RHSADDR]](p0)
-; CHECK: [[TST:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
+; CHECK: [[LHSADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[RHSADDR:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_LOAD [[LHSADDR]](p0)
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_LOAD [[RHSADDR]](p0)
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
 ; CHECK: G_STORE [[TST]](s1), [[BOOLADDR]](p0)
 define void @float_comparison(float* %a.addr, float* %b.addr, i1* %bool.addr) {
   %a = load float, float* %a.addr
@@ -1101,10 +1107,10 @@ define void @float_comparison(float* %a.addr, float* %b.addr, i1* %bool.addr) {
 }
 
 ; CHECK-LABEL: name: trivial_float_comparison
-; CHECK: [[ENTRY_R1:%[0-9]+]](s1) = G_CONSTANT i1 false
-; CHECK: [[ENTRY_R2:%[0-9]+]](s1) = G_CONSTANT i1 true
-; CHECK: [[R1:%[0-9]+]](s1) = COPY [[ENTRY_R1]](s1)
-; CHECK: [[R2:%[0-9]+]](s1) = COPY [[ENTRY_R2]](s1)
+; CHECK: [[ENTRY_R1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+; CHECK: [[ENTRY_R2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+; CHECK: [[R1:%[0-9]+]]:_(s1) = COPY [[ENTRY_R1]](s1)
+; CHECK: [[R2:%[0-9]+]]:_(s1) = COPY [[ENTRY_R2]](s1)
 ; CHECK: G_ADD [[R1]], [[R2]]
 define i1 @trivial_float_comparison(double %a, double %b) {
   %r1 = fcmp false double %a, %b
@@ -1117,7 +1123,7 @@ define i1 @trivial_float_comparison(double %a, double %b) {
 
 define i32* @test_global() {
 ; CHECK-LABEL: name: test_global
-; CHECK: [[TMP:%[0-9]+]](p0) = G_GLOBAL_VALUE @var{{$}}
+; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var{{$}}
 ; CHECK: %x0 = COPY [[TMP]](p0)
 
   ret i32* @var
@@ -1126,7 +1132,7 @@ define i32* @test_global() {
 @var1 = addrspace(42) global i32 0
 define i32 addrspace(42)* @test_global_addrspace() {
 ; CHECK-LABEL: name: test_global
-; CHECK: [[TMP:%[0-9]+]](p42) = G_GLOBAL_VALUE @var1{{$}}
+; CHECK: [[TMP:%[0-9]+]]:_(p42) = G_GLOBAL_VALUE @var1{{$}}
 ; CHECK: %x0 = COPY [[TMP]](p42)
 
   ret i32 addrspace(42)* @var1
@@ -1135,7 +1141,7 @@ define i32 addrspace(42)* @test_global_addrspace() {
 
 define void()* @test_global_func() {
 ; CHECK-LABEL: name: test_global_func
-; CHECK: [[TMP:%[0-9]+]](p0) = G_GLOBAL_VALUE @allocai64{{$}}
+; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @allocai64{{$}}
 ; CHECK: %x0 = COPY [[TMP]](p0)
 
   ret void()* @allocai64
@@ -1144,9 +1150,9 @@ define void()* @test_global_func() {
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile)
 define void @test_memcpy(i8* %dst, i8* %src, i64 %size) {
 ; CHECK-LABEL: name: test_memcpy
-; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
+; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
 ; CHECK: %x0 = COPY [[DST]]
 ; CHECK: %x1 = COPY [[SRC]]
 ; CHECK: %x2 = COPY [[SIZE]]
@@ -1158,9 +1164,9 @@ define void @test_memcpy(i8* %dst, i8* %src, i64 %size) {
 declare void @llvm.memmove.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile)
 define void @test_memmove(i8* %dst, i8* %src, i64 %size) {
 ; CHECK-LABEL: name: test_memmove
-; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
+; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
 ; CHECK: %x0 = COPY [[DST]]
 ; CHECK: %x1 = COPY [[SRC]]
 ; CHECK: %x2 = COPY [[SIZE]]
@@ -1172,11 +1178,13 @@ define void @test_memmove(i8* %dst, i8* %src, i64 %size) {
 declare void @llvm.memset.p0i8.i64(i8*, i8, i64, i32 %align, i1 %volatile)
 define void @test_memset(i8* %dst, i8 %val, i64 %size) {
 ; CHECK-LABEL: name: test_memset
-; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[SRC:%[0-9]+]](s8) = COPY %w1
-; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
+; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]]
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
 ; CHECK: %x0 = COPY [[DST]]
-; CHECK: %w1 = COPY [[SRC]]
+; CHECK: [[SRC_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[SRC]]
+; CHECK: %w1 = COPY [[SRC_TMP]]
 ; CHECK: %x2 = COPY [[SIZE]]
 ; CHECK: BL $memset, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %w1, implicit %x2
   call void @llvm.memset.p0i8.i64(i8* %dst, i8 %val, i64 %size, i32 1, i1 0)
@@ -1187,12 +1195,12 @@ declare i64 @llvm.objectsize.i64(i8*, i1)
 declare i32 @llvm.objectsize.i32(i8*, i1)
 define void @test_objectsize(i8* %addr0, i8* %addr1) {
 ; CHECK-LABEL: name: test_objectsize
-; CHECK: [[ADDR0:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[ADDR1:%[0-9]+]](p0) = COPY %x1
-; CHECK: {{%[0-9]+}}(s64) = G_CONSTANT i64 -1
-; CHECK: {{%[0-9]+}}(s64) = G_CONSTANT i64 0
-; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT i32 -1
-; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT i32 0
+; CHECK: [[ADDR0:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: {{%[0-9]+}}:_(s64) = G_CONSTANT i64 -1
+; CHECK: {{%[0-9]+}}:_(s64) = G_CONSTANT i64 0
+; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 -1
+; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 0
   %size64.0 = call i64 @llvm.objectsize.i64(i8* %addr0, i1 0)
   %size64.intmin = call i64 @llvm.objectsize.i64(i8* %addr0, i1 1)
   %size32.0 = call i32 @llvm.objectsize.i32(i8* %addr0, i1 0)
@@ -1202,8 +1210,8 @@ define void @test_objectsize(i8* %addr0, i8* %addr1) {
 
 define void @test_large_const(i128* %addr) {
 ; CHECK-LABEL: name: test_large_const
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s128) = G_CONSTANT i128 42
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s128) = G_CONSTANT i128 42
 ; CHECK: G_STORE [[VAL]](s128), [[ADDR]](p0)
   store i128 42, i128* %addr
   ret void
@@ -1216,9 +1224,9 @@ define void @test_large_const(i128* %addr) {
 define i8* @test_const_placement() {
 ; CHECK-LABEL: name: test_const_placement
 ; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
-; CHECK:   [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK:   [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
-; CHECK: {{bb.[0-9]+}}.next:
+; CHECK:   [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK:   [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32)
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
   br label %next
 
 next:
@@ -1237,7 +1245,7 @@ define void @test_va_end(i8* %list) {
 
 define void @test_va_arg(i8* %list) {
 ; CHECK-LABEL: test_va_arg
-; CHECK: [[LIST:%[0-9]+]](p0) = COPY %x0
+; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY %x0
 ; CHECK: G_VAARG [[LIST]](p0), 8
 ; CHECK: G_VAARG [[LIST]](p0), 1
 ; CHECK: G_VAARG [[LIST]](p0), 16
@@ -1251,9 +1259,9 @@ define void @test_va_arg(i8* %list) {
 declare float @llvm.pow.f32(float, float)
 define float @test_pow_intrin(float %l, float %r) {
 ; CHECK-LABEL: name: test_pow_intrin
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %s1
-; CHECK: [[RES:%[0-9]+]](s32) = G_FPOW [[LHS]], [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPOW [[LHS]], [[RHS]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.pow.f32(float %l, float %r)
   ret float %res
@@ -1262,10 +1270,10 @@ define float @test_pow_intrin(float %l, float %r) {
 declare float @llvm.fma.f32(float, float, float)
 define float @test_fma_intrin(float %a, float %b, float %c) {
 ; CHECK-LABEL: name: test_fma_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[B:%[0-9]+]](s32) = COPY %s1
-; CHECK: [[C:%[0-9]+]](s32) = COPY %s2
-; CHECK: [[RES:%[0-9]+]](s32) = G_FMA [[A]], [[B]], [[C]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[B:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK: [[C:%[0-9]+]]:_(s32) = COPY %s2
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FMA [[A]], [[B]], [[C]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.fma.f32(float %a, float %b, float %c)
   ret float %res
@@ -1274,8 +1282,8 @@ define float @test_fma_intrin(float %a, float %b, float %c) {
 declare float @llvm.exp.f32(float)
 define float @test_exp_intrin(float %a) {
 ; CHECK-LABEL: name: test_exp_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FEXP [[A]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP [[A]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.exp.f32(float %a)
   ret float %res
@@ -1284,8 +1292,8 @@ define float @test_exp_intrin(float %a) {
 declare float @llvm.exp2.f32(float)
 define float @test_exp2_intrin(float %a) {
 ; CHECK-LABEL: name: test_exp2_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FEXP2 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP2 [[A]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.exp2.f32(float %a)
   ret float %res
@@ -1294,8 +1302,8 @@ define float @test_exp2_intrin(float %a) {
 declare float @llvm.log.f32(float)
 define float @test_log_intrin(float %a) {
 ; CHECK-LABEL: name: test_log_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FLOG [[A]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG [[A]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.log.f32(float %a)
   ret float %res
@@ -1304,8 +1312,8 @@ define float @test_log_intrin(float %a) {
 declare float @llvm.log2.f32(float)
 define float @test_log2_intrin(float %a) {
 ; CHECK-LABEL: name: test_log2_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FLOG2 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG2 [[A]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.log2.f32(float %a)
   ret float %res
@@ -1323,12 +1331,12 @@ define void @test_lifetime_intrin() {
 
 define void @test_load_store_atomics(i8* %addr) {
 ; CHECK-LABEL: name: test_load_store_atomics
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[V0:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[V0:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr)
 ; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic 1 into %ir.addr)
-; CHECK: [[V1:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr)
+; CHECK: [[V1:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr)
 ; CHECK: G_STORE [[V1]](s8), [[ADDR]](p0) :: (store release 1 into %ir.addr)
-; CHECK: [[V2:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst 1 from %ir.addr)
+; CHECK: [[V2:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst 1 from %ir.addr)
 ; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic 1 into %ir.addr)
   %v0 = load atomic i8, i8* %addr unordered, align 1
   store atomic i8 %v0, i8* %addr monotonic, align 1
@@ -1344,8 +1352,8 @@ define void @test_load_store_atomics(i8* %addr) {
 
 define float @test_fneg_f32(float %x) {
 ; CHECK-LABEL: name: test_fneg_f32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FNEG [[ARG]]
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
 ; CHECK: %s0 = COPY [[RES]](s32)
   %neg = fsub float -0.000000e+00, %x
   ret float %neg
@@ -1353,8 +1361,8 @@ define float @test_fneg_f32(float %x) {
 
 define double @test_fneg_f64(double %x) {
 ; CHECK-LABEL: name: test_fneg_f64
-; CHECK: [[ARG:%[0-9]+]](s64) = COPY %d0
-; CHECK: [[RES:%[0-9]+]](s64) = G_FNEG [[ARG]]
+; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY %d0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
 ; CHECK: %d0 = COPY [[RES]](s64)
   %neg = fsub double -0.000000e+00, %x
   ret double %neg
@@ -1371,10 +1379,10 @@ define void @test_trivial_inlineasm() {
 
 define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){
 ; CHECK-LABEL: name: test_insertelement
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK: [[ELT:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[IDX:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[RES:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32)
 ; CHECK: %d0 = COPY [[RES]](<2 x s32>)
   %res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx
   ret <2 x i32> %res
@@ -1382,9 +1390,9 @@ define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){
 
 define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
 ; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK: [[IDX:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RES:%[0-9]+]](s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s32)
 ; CHECK: %w0 = COPY [[RES]](s32)
   %res = extractelement <2 x i32> %vec, i32 %idx
   ret i32 %res
@@ -1392,7 +1400,7 @@ define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
 
 define i32 @test_singleelementvector(i32 %elt){
 ; CHECK-LABEL: name: test_singleelementvector
-; CHECK: [[ELT:%[0-9]+]](s32) = COPY %w0
+; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY %w0
 ; CHECK-NOT: G_INSERT_VECTOR_ELT
 ; CHECK-NOT: G_EXTRACT_VECTOR_ELT
 ; CHECK: %w0 = COPY [[ELT]](s32)
@@ -1403,24 +1411,24 @@ define i32 @test_singleelementvector(i32 %elt){
 
 define <2 x i32> @test_constantaggzerovector_v2i32() {
 ; CHECK-LABEL: name: test_constantaggzerovector_v2i32
-; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
+; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   ret <2 x i32> zeroinitializer
 }
 
 define <2 x float> @test_constantaggzerovector_v2f32() {
 ; CHECK-LABEL: name: test_constantaggzerovector_v2f32
-; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float 0.000000e+00
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
+; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   ret <2 x float> zeroinitializer
 }
 
 define i32 @test_constantaggzerovector_v3i32() {
 ; CHECK-LABEL: name: test_constantaggzerovector_v3i32
-; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)
+; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
   %elt = extractelement <3 x i32> zeroinitializer, i32 1
   ret i32 %elt
@@ -1428,19 +1436,19 @@ define i32 @test_constantaggzerovector_v3i32() {
 
 define <2 x i32> @test_constantdatavector_v2i32() {
 ; CHECK-LABEL: name: test_constantdatavector_v2i32
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   ret <2 x i32> <i32 1, i32 2>
 }
 
 define i32 @test_constantdatavector_v3i32() {
 ; CHECK-LABEL: name: test_constantdatavector_v3i32
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32)
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
   %elt = extractelement <3 x i32> <i32 1, i32 2, i32 3>, i32 1
   ret i32 %elt
@@ -1448,28 +1456,28 @@ define i32 @test_constantdatavector_v3i32() {
 
 define <4 x i32> @test_constantdatavector_v4i32() {
 ; CHECK-LABEL: name: test_constantdatavector_v4i32
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
 ; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
   ret <4 x i32> <i32 1, i32 2, i32 3, i32 4>
 }
 
 define <2 x double> @test_constantdatavector_v2f64() {
 ; CHECK-LABEL: name: test_constantdatavector_v2f64
-; CHECK: [[FC1:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
-; CHECK: [[FC2:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
-; CHECK: [[VEC:%[0-9]+]](<2 x s64>) = G_MERGE_VALUES [[FC1]](s64), [[FC2]](s64)
+; CHECK: [[FC1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+; CHECK: [[FC2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s64>) = G_MERGE_VALUES [[FC1]](s64), [[FC2]](s64)
 ; CHECK: %q0 = COPY [[VEC]](<2 x s64>)
   ret <2 x double> <double 1.0, double 2.0>
 }
 
 define i32 @test_constantaggzerovector_v1s32(i32 %arg){
 ; CHECK-LABEL: name: test_constantaggzerovector_v1s32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
 ; CHECK-NOT: G_MERGE_VALUES
 ; CHECK: G_ADD [[ARG]], [[C0]]
   %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
@@ -1480,8 +1488,8 @@ define i32 @test_constantaggzerovector_v1s32(i32 %arg){
 
 define i32 @test_constantdatavector_v1s32(i32 %arg){
 ; CHECK-LABEL: name: test_constantdatavector_v1s32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
 ; CHECK-NOT: G_MERGE_VALUES
 ; CHECK: G_ADD [[ARG]], [[C1]]
   %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
@@ -1493,7 +1501,7 @@ define i32 @test_constantdatavector_v1s32(i32 %arg){
 declare ghccc float @different_call_conv_target(float %x)
 define float @test_different_call_conv_target(float %x) {
 ; CHECK-LABEL: name: test_different_call_conv
-; CHECK: [[X:%[0-9]+]](s32) = COPY %s0
+; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
 ; CHECK: %s8 = COPY [[X]]
 ; CHECK: BL @different_call_conv_target, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s8, implicit-def %s0
   %res = call ghccc float @different_call_conv_target(float %x)
@@ -1502,11 +1510,11 @@ define float @test_different_call_conv_target(float %x) {
 
 define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
 ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
   %res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
@@ -1515,10 +1523,10 @@ define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
 
 define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_s32
-; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[RES:%[0-9]+]](s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
 ; CHECK: %w0 = COPY [[RES]](s32)
   %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1>
   %res = extractelement <1 x i32> %vec, i32 0
@@ -1527,12 +1535,12 @@ define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
 
 define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32
-; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
   ret <2 x i32> %res
@@ -1540,12 +1548,12 @@ define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
 
 define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
-; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
-; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
   %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
   %res = extractelement <3 x i32> %vec, i32 0
@@ -1554,14 +1562,14 @@ define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
 
 define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
-; CHECK: [[ARG1:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK: [[ARG2:%[0-9]+]](<2 x s32>) = COPY %d1
-; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
-; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
+; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY %d1
+; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[MASK:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
 ; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
   %res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %res
@@ -1569,12 +1577,12 @@ define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg
 
 define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
 ; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
-; CHECK: [[ARG:%[0-9]+]](<4 x s32>) = COPY %q0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY %q0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   %res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
   ret <2 x i32> %res
@@ -1583,35 +1591,35 @@ define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
 
 define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
 ; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
-; CHECK: [[ARG1:%[0-9]+]](<8 x s8>) = COPY %d0
-; CHECK: [[ARG2:%[0-9]+]](<8 x s8>) = COPY %d1
-; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[C8:%[0-9]+]](s32) = G_CONSTANT i32 8
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C9:%[0-9]+]](s32) = G_CONSTANT i32 9
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[C10:%[0-9]+]](s32) = G_CONSTANT i32 10
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[C11:%[0-9]+]](s32) = G_CONSTANT i32 11
-; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[C12:%[0-9]+]](s32) = G_CONSTANT i32 12
-; CHECK: [[C5:%[0-9]+]](s32) = G_CONSTANT i32 5
-; CHECK: [[C13:%[0-9]+]](s32) = G_CONSTANT i32 13
-; CHECK: [[C6:%[0-9]+]](s32) = G_CONSTANT i32 6
-; CHECK: [[C14:%[0-9]+]](s32) = G_CONSTANT i32 14
-; CHECK: [[C7:%[0-9]+]](s32) = G_CONSTANT i32 7
-; CHECK: [[C15:%[0-9]+]](s32) = G_CONSTANT i32 15
-; CHECK: [[MASK:%[0-9]+]](<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
-; CHECK: [[VEC:%[0-9]+]](<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
+; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY %d0
+; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY %d1
+; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
+; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+; CHECK: [[MASK:%[0-9]+]]:_(<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
 ; CHECK: %q0 = COPY [[VEC]](<16 x s8>)
   %res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: test_constant_vector
-; CHECK: [[UNDEF:%[0-9]+]](s16) = G_IMPLICIT_DEF
-; CHECK: [[F:%[0-9]+]](s16) = G_FCONSTANT half 0xH3C00
-; CHECK: [[M:%[0-9]+]](<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
+; CHECK: [[UNDEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+; CHECK: [[F:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+; CHECK: [[M:%[0-9]+]]:_(<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
 ; CHECK: %d0 = COPY [[M]](<4 x s16>)
 define <4 x half> @test_constant_vector() {
   ret <4 x half> <half undef, half undef, half undef, half 0xH3C00>
@@ -1619,8 +1627,8 @@ define <4 x half> @test_constant_vector() {
 
 define i32 @test_target_mem_intrinsic(i32* %addr) {
 ; CHECK-LABEL: name: test_target_mem_intrinsic
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr)
 ; CHECK: G_TRUNC [[VAL]](s64)
   %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
   %trunc = trunc i64 %val to i32
@@ -1628,3 +1636,16 @@ define i32 @test_target_mem_intrinsic(i32* %addr) {
 }
 
 declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
+
+%zerosize_type = type {}
+
+define %zerosize_type @test_empty_load_store(%zerosize_type *%ptr, %zerosize_type %in) noinline optnone {
+; CHECK-LABEL: name: test_empty_load_store
+; CHECK-NOT: G_STORE
+; CHECK-NOT: G_LOAD
+; CHECK: RET_ReallyLR
+entry:
+  store %zerosize_type undef, %zerosize_type* undef, align 4
+  %val = load %zerosize_type, %zerosize_type* %ptr, align 4
+  ret %zerosize_type %in
+}
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index 296f65c041a1..a27cf2bea78c 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -66,6 +66,10 @@
   define void @bitcast_s64_fpr() { ret void }
   define void @bitcast_s64_gpr_fpr() { ret void }
   define void @bitcast_s64_fpr_gpr() { ret void }
+  define void @bitcast_s128() { ret void }
+  define void @copy_s128() { ret void }
+  define void @copy_s128_from_load() { ret void }
+  define void @copy_fp16() { ret void }
 
   define i64 @greedyWithChainOfComputation(i64 %arg1, <2 x i32>* %addr) {
     %varg1 = bitcast i64 %arg1 to <2 x i32>
@@ -89,6 +93,23 @@
     store double %vres, double* %addr
     ret void
   }
+
+  define void @fp16Ext32() { ret void }
+  define void @fp16Ext64() { ret void }
+  define void @fp32Ext64() { ret void }
+
+  define half @passFp16(half %p) {
+  entry:
+    ret half %p
+  }
+
+  define half @passFp16ViaAllocas(half %p) {
+  entry:
+    %p.addr = alloca half, align 2
+    store half %p, half* %p.addr, align 2
+    %0 = load half, half* %p.addr, align 2
+    ret half %0
+  }
 ...
 
 ---
@@ -96,17 +117,14 @@
 # Based on the type i32, this should be gpr.
 name:            defaultMapping
 legalized:       true
-# CHECK-LABEL: name: defaultMapping
-# CHECK:      registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0
-    ; CHECK:      %1(s32) = G_ADD %0
+    ; CHECK-LABEL: name: defaultMapping
+    ; CHECK:      %1:gpr(s32) = G_ADD %0
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
@@ -117,18 +135,15 @@ body: |
 # FPR is used for both floating point and vector registers.
 name:            defaultMappingVector
 legalized:       true
-# CHECK-LABEL: name: defaultMappingVector
-# CHECK:      registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %d0
-    ; CHECK:      %0(<2 x s32>) = COPY %d0
-    ; CHECK:      %1(<2 x s32>) = G_ADD %0
+    ; CHECK-LABEL: name: defaultMappingVector
+    ; CHECK:      %0:fpr(<2 x s32>) = COPY %d0
+    ; CHECK:      %1:fpr(<2 x s32>) = G_ADD %0
     %0(<2 x s32>) = COPY %d0
     %1(<2 x s32>) = G_ADD %0, %0
 ...
@@ -139,12 +154,6 @@ body: |
 # in FPR, but at the use, it should be GPR.
 name:            defaultMapping1Repair
 legalized:       true
-# CHECK-LABEL: name: defaultMapping1Repair
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -152,10 +161,11 @@ registers:
 body: |
   bb.0.entry:
     liveins: %s0, %x0
-    ; CHECK:           %0(s32) = COPY %s0
-    ; CHECK-NEXT:      %1(s32) = COPY %w0
-    ; CHECK-NEXT:      %3(s32) = COPY %0
-    ; CHECK-NEXT:      %2(s32) = G_ADD %3, %1
+    ; CHECK-LABEL: name: defaultMapping1Repair
+    ; CHECK:           %0:fpr(s32) = COPY %s0
+    ; CHECK-NEXT:      %1:gpr(s32) = COPY %w0
+    ; CHECK-NEXT:      %3:gpr(s32) = COPY %0
+    ; CHECK-NEXT:      %2:gpr(s32) = G_ADD %3, %1
     %0(s32) = COPY %s0
     %1(s32) = COPY %w0
     %2(s32) = G_ADD %0, %1
@@ -164,22 +174,17 @@ body: |
 # Check that we repair the assignment for %0 differently for both uses.
 name:            defaultMapping2Repairs
 legalized:       true
-# CHECK-LABEL: name: defaultMapping2Repairs
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %s0, %x0
-    ; CHECK:           %0(s32) = COPY %s0
-    ; CHECK-NEXT:      %2(s32) = COPY %0
-    ; CHECK-NEXT:      %3(s32) = COPY %0
-    ; CHECK-NEXT:      %1(s32) = G_ADD %2, %3
+    ; CHECK-LABEL: name: defaultMapping2Repairs
+    ; CHECK:           %0:fpr(s32) = COPY %s0
+    ; CHECK-NEXT:      %2:gpr(s32) = COPY %0
+    ; CHECK-NEXT:      %3:gpr(s32) = COPY %0
+    ; CHECK-NEXT:      %1:gpr(s32) = G_ADD %2, %3
     %0(s32) = COPY %s0
     %1(s32) = G_ADD %0, %0
 ...
@@ -191,20 +196,16 @@ body: |
 # fixes that.
 name:            defaultMappingDefRepair
 legalized:       true
-# CHECK-LABEL: name: defaultMappingDefRepair
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: fpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: fpr }
 body: |
   bb.0.entry:
     liveins: %w0
-    ; CHECK:           %0(s32) = COPY %w0
-    ; CHECK-NEXT:      %2(s32) = G_ADD %0, %0
-    ; CHECK-NEXT:      %1(s32) = COPY %2
+    ; CHECK-LABEL: name: defaultMappingDefRepair
+    ; CHECK:           %0:gpr(s32) = COPY %w0
+    ; CHECK-NEXT:      %2:gpr(s32) = G_ADD %0, %0
+    ; CHECK-NEXT:      %1:fpr(s32) = COPY %2
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
@@ -252,12 +253,6 @@ body: |
 # Make sure we can repair physical register uses as well.
 name:            defaultMappingUseRepairPhysReg
 legalized:       true
-# CHECK-LABEL: name: defaultMappingUseRepairPhysReg
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: fpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -265,10 +260,11 @@ registers:
 body: |
   bb.0.entry:
     liveins: %w0, %s0
-    ; CHECK:           %0(s32) = COPY %w0
-    ; CHECK-NEXT:      %1(s32) = COPY %s0
-    ; CHECK-NEXT:      %3(s32) = COPY %1
-    ; CHECK-NEXT:      %2(s32) = G_ADD %0, %3
+    ; CHECK-LABEL: name: defaultMappingUseRepairPhysReg
+    ; CHECK:           %0:gpr(s32) = COPY %w0
+    ; CHECK-NEXT:      %1:fpr(s32) = COPY %s0
+    ; CHECK-NEXT:      %3:gpr(s32) = COPY %1
+    ; CHECK-NEXT:      %2:gpr(s32) = G_ADD %0, %3
     %0(s32) = COPY %w0
     %1(s32) = COPY %s0
     %2(s32) = G_ADD %0, %1
@@ -278,18 +274,15 @@ body: |
 # Make sure we can repair physical register defs.
 name:            defaultMappingDefRepairPhysReg
 legalized:       true
-# CHECK-LABEL: name: defaultMappingDefRepairPhysReg
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %w0
-    ; CHECK:           %0(s32) = COPY %w0
-    ; CHECK-NEXT:      %1(s32) = G_ADD %0, %0
+    ; CHECK-LABEL: name: defaultMappingDefRepairPhysReg
+    ; CHECK:           %0:gpr(s32) = COPY %w0
+    ; CHECK-NEXT:      %1:gpr(s32) = G_ADD %0, %0
     ; CHECK-NEXT:      %s0 = COPY %1
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
@@ -301,21 +294,6 @@ body: |
 # G_OR instruction from fpr to gpr.
 name:            greedyMappingOr
 legalized:       true
-# CHECK-LABEL: name: greedyMappingOr
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-
-# Fast mode maps vector instruction on FPR.
-# FAST-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
-# Fast mode needs two extra copies.
-# FAST-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
-
-# Greedy mode coalesce the computation on the GPR register
-# because it is the cheapest.
-# GREEDY-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -323,20 +301,19 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1
-    ; CHECK: %0(<2 x s32>) = COPY %x0
-    ; CHECK-NEXT: %1(<2 x s32>) = COPY %x1
-
+    ; CHECK: %0:gpr(<2 x s32>) = COPY %x0
+    ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
 
     ; Fast mode tries to reuse the source of the copy for the destination.
     ; Now, the default mapping says that %0 and %1 need to be in FPR.
     ; The repairing code insert two copies to materialize that.
-    ; FAST-NEXT: %3(<2 x s32>) = COPY %0
-    ; FAST-NEXT: %4(<2 x s32>) = COPY %1
+    ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
+    ; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1
     ; The mapping of G_OR is on FPR.
-    ; FAST-NEXT: %2(<2 x s32>) = G_OR %3, %4
+    ; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4
 
     ; Greedy mode remapped the instruction on the GPR bank.
-    ; GREEDY-NEXT: %2(<2 x s32>) = G_OR %0, %1
+    ; GREEDY-NEXT: %2:gpr(<2 x s32>) = G_OR %0, %1
     %0(<2 x s32>) = COPY %x0
     %1(<2 x s32>) = COPY %x1
     %2(<2 x s32>) = G_OR %0, %1
@@ -348,21 +325,6 @@ body: |
 # %2 constraint.
 name:            greedyMappingOrWithConstraints
 legalized:       true
-# CHECK-LABEL: name: greedyMappingOrWithConstraints
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
-
-# Fast mode maps vector instruction on FPR.
-# Fast mode needs two extra copies.
-# FAST-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
-
-# Greedy mode coalesce the computation on the GPR register because it
-# is the cheapest, but will need one extra copy to materialize %2 into a FPR.
-# GREEDY-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -370,22 +332,23 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1
-    ; CHECK: %0(<2 x s32>) = COPY %x0
-    ; CHECK-NEXT: %1(<2 x s32>) = COPY %x1
+    ; CHECK-LABEL: name: greedyMappingOrWithConstraints
 
+    ; CHECK: %0:gpr(<2 x s32>) = COPY %x0
+    ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
 
     ; Fast mode tries to reuse the source of the copy for the destination.
     ; Now, the default mapping says that %0 and %1 need to be in FPR.
     ; The repairing code insert two copies to materialize that.
-    ; FAST-NEXT: %3(<2 x s32>) = COPY %0
-    ; FAST-NEXT: %4(<2 x s32>) = COPY %1
+    ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
+    ; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1
     ; The mapping of G_OR is on FPR.
-    ; FAST-NEXT: %2(<2 x s32>) = G_OR %3, %4
+    ; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4
 
     ; Greedy mode remapped the instruction on the GPR bank.
-    ; GREEDY-NEXT: %3(<2 x s32>) = G_OR %0, %1
+    ; GREEDY-NEXT: %3:gpr(<2 x s32>) = G_OR %0, %1
     ; We need to keep %2 into FPR because we do not know anything about it.
-    ; GREEDY-NEXT: %2(<2 x s32>) = COPY %3
+    ; GREEDY-NEXT: %2:fpr(<2 x s32>) = COPY %3
     %0(<2 x s32>) = COPY %x0
     %1(<2 x s32>) = COPY %x1
     %2(<2 x s32>) = G_OR %0, %1
@@ -405,8 +368,8 @@ body: |
   bb.0:
     liveins: %x0
 
-    ; CHECK: %0 = COPY %x0
-    ; CHECK-NEXT: %1 = ADDXrr %0, %0
+    ; CHECK: %0:gpr64 = COPY %x0
+    ; CHECK-NEXT: %1:gpr64 = ADDXrr %0, %0
     ; CHECK-NEXT: %x0 = COPY %1
     ; CHECK-NEXT: RET_ReallyLR implicit %x0
 
@@ -441,8 +404,8 @@ registers:
   - { id: 1, class: _ }
 
 # CHECK:  body:
-# CHECK:    %0(s32) = COPY %w0
-# CHECK:    %1(s32) = G_BITCAST %0
+# CHECK:    %0:gpr(s32) = COPY %w0
+# CHECK:    %1:gpr(s32) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %w0
@@ -464,8 +427,8 @@ registers:
   - { id: 1, class: _ }
 
 # CHECK:  body:
-# CHECK:    %0(<2 x s16>) = COPY %s0
-# CHECK:    %1(<2 x s16>) = G_BITCAST %0
+# CHECK:    %0:fpr(<2 x s16>) = COPY %s0
+# CHECK:    %1:fpr(<2 x s16>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %s0
@@ -488,8 +451,9 @@ registers:
   - { id: 1, class: _ }
 
 # CHECK:  body:
-# CHECK:    %0(s32) = COPY %w0
-# CHECK:    %1(<2 x s16>) = G_BITCAST %0
+# CHECK:    %0:gpr(s32) = COPY %w0
+# FAST:     %1:fpr(<2 x s16>) = G_BITCAST %0
+# GREEDY:   %1:gpr(<2 x s16>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %w0
@@ -502,18 +466,13 @@ body:             |
 # CHECK-LABEL: name: bitcast_s32_fpr_gpr
 name:            bitcast_s32_fpr_gpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# GREEDY-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-
 # CHECK:  body:
-# CHECK:    %0(<2 x s16>) = COPY %s0
-# CHECK:    %1(s32) = G_BITCAST %0
+# CHECK:    %0:fpr(<2 x s16>) = COPY %s0
+# FAST:     %1:gpr(s32) = G_BITCAST %0
+# GREEDY:   %1:fpr(s32) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %s0
@@ -526,17 +485,12 @@ body:             |
 # CHECK-LABEL: name: bitcast_s64_gpr
 name:            bitcast_s64_gpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-
 # CHECK:  body:
-# CHECK:    %0(s64) = COPY %x0
-# CHECK:    %1(s64) = G_BITCAST %0
+# CHECK:    %0:gpr(s64) = COPY %x0
+# CHECK:    %1:gpr(s64) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %x0
@@ -549,17 +503,12 @@ body:             |
 # CHECK-LABEL: name: bitcast_s64_fpr
 name:            bitcast_s64_fpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-
 # CHECK:  body:
-# CHECK:    %0(<2 x s32>) = COPY %d0
-# CHECK:    %1(<2 x s32>) = G_BITCAST %0
+# CHECK:    %0:fpr(<2 x s32>) = COPY %d0
+# CHECK:    %1:fpr(<2 x s32>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %d0
@@ -572,17 +521,13 @@ body:             |
 # CHECK-LABEL: name: bitcast_s64_gpr_fpr
 name:            bitcast_s64_gpr_fpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
-# GREEDY-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 # CHECK:  body:
-# CHECK:    %0(s64) = COPY %x0
-# CHECK:    %1(<2 x s32>) = G_BITCAST %0
+# CHECK:    %0:gpr(s64) = COPY %x0
+# FAST:     %1:fpr(<2 x s32>) = G_BITCAST %0
+# GREEDY:   %1:gpr(<2 x s32>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %x0
@@ -595,18 +540,13 @@ body:             |
 # CHECK-LABEL: name: bitcast_s64_fpr_gpr
 name:            bitcast_s64_fpr_gpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# GREEDY-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-
 # CHECK:  body:
-# CHECK:    %0(<2 x s32>) = COPY %d0
-# CHECK:    %1(s64) = G_BITCAST %0
+# CHECK:    %0:fpr(<2 x s32>) = COPY %d0
+# FAST:     %1:gpr(s64) = G_BITCAST %0
+# GREEDY:   %1:fpr(s64) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %d0
@@ -616,23 +556,124 @@ body:             |
 ...
 
 ---
+# CHECK-LABEL: name: bitcast_s128
+name:            bitcast_s128
+legalized: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _}
+  - { id: 1, class: _}
+  - { id: 2, class: _}
+  - { id: 3, class: _}
+# CHECK: %3:fpr(s128) = G_MERGE_VALUES
+# CHECK: %2:fpr(<2 x s64>) = G_BITCAST %3(s128)
+body:             |
+  bb.1:
+    liveins: %x0, %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
+    %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
+    %2(<2 x s64>) = G_BITCAST %3(s128)
+    %q0 = COPY %2(<2 x s64>)
+    RET_ReallyLR implicit %q0
+
+...
+
+---
+# CHECK-LABEL: name: copy_s128
+# This test checks that we issue the proper mapping
+# for copy of size > 64.
+# The mapping should be the same as G_BITCAST.
+name:            copy_s128
+legalized: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _}
+  - { id: 1, class: _}
+  - { id: 2, class: _}
+  - { id: 3, class: _}
+  - { id: 4, class: _}
+# CHECK: %3:fpr(s128) = G_MERGE_VALUES
+# CHECK: %4:fpr(s128) = COPY %3(s128)
+# CHECK-NEXT: %2:fpr(<2 x s64>) = G_BITCAST %4(s128)
+body:             |
+  bb.1:
+    liveins: %x0, %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
+    %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
+    %4(s128) = COPY %3(s128)
+    %2(<2 x s64>) = G_BITCAST %4(s128)
+    %q0 = COPY %2(<2 x s64>)
+    RET_ReallyLR implicit %q0
+
+...
+
+---
+# CHECK-LABEL: name: copy_s128_from_load
+# This test checks that we issue the proper mapping
+# for copy of size > 64 when the input is neither
+# a physcal register nor a generic register.
+# This used to crash when we moved to the statically
+# computed mapping, because we were assuming non-physregs
+# were generic registers and thus have a type, whereas
+# it is not necessarily the case.
+name:            copy_s128_from_load
+legalized: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr128}
+  - { id: 1, class: _}
+# CHECK: registers:
+# CHECK:  - { id: 0, class: fpr128, preferred-register: '' }
+# CHECK:  - { id: 1, class: fpr, preferred-register: '' }
+# CHECK: %1:fpr(s128) = COPY %0
+body:             |
+  bb.1:
+    liveins: %x0
+    %0 = LDRQui killed %x0, 0
+    %1(s128) = COPY %0
+    %q0 = COPY %1(s128)
+    RET_ReallyLR implicit %q0
+
+...
+
+---
+# CHECK-LABEL: name: copy_fp16
+# This test checks that we issue the proper mapping
+# for copy of size == 16 when the destination is a fpr
+# physical register and the source a gpr.
+# We used to crash because we thought that mapping couldn't
+# exist in a copy.
+name:            copy_fp16
+legalized: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _}
+  - { id: 1, class: _}
+# CHECK: registers:
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK: %0:gpr(s32) = COPY %w0
+# CHECK-NEXT: %1:gpr(s16) = G_TRUNC %0(s32)
+body:             |
+  bb.1:
+    liveins: %w0
+    %0(s32) = COPY %w0
+    %1(s16) = G_TRUNC %0(s32)
+    %h0 = COPY %1(s16)
+    RET_ReallyLR implicit %h0
+
+...
+
+
+---
 # Make sure the greedy mode is able to take advantage of the
 # alternative mappings of G_LOAD to coalesce the whole chain
 # of computation on GPR.
 # CHECK-LABEL: name: greedyWithChainOfComputation
 name:            greedyWithChainOfComputation
 legalized:       true
-
-# CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# FAST-NEXT:   - { id: 2, class: fpr, preferred-register: '' }
-# FAST-NEXT:   - { id: 3, class: fpr, preferred-register: '' }
-# FAST-NEXT:   - { id: 4, class: fpr, preferred-register: '' }
-# GREEDY-NEXT: - { id: 2, class: gpr, preferred-register: '' }
-# GREEDY-NEXT: - { id: 3, class: gpr, preferred-register: '' }
-# GREEDY-NEXT: - { id: 4, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -640,17 +681,18 @@ registers:
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
-
 # No repairing should be necessary for both modes.
-# CHECK:         %0(s64) = COPY %x0
-# CHECK-NEXT:    %1(p0) = COPY %x1
-# CHECK-NEXT:    %2(<2 x s32>) = G_BITCAST %0(s64)
-# CHECK-NEXT:    %3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
-# CHECK-NEXT:    %4(<2 x s32>) = G_OR %2, %3
-# CHECK-NEXT:    %5(s64) = G_BITCAST %4(<2 x s32>)
+# CHECK:         %0:gpr(s64) = COPY %x0
+# CHECK-NEXT:    %1:gpr(p0) = COPY %x1
+# FAST-NEXT:     %2:fpr(<2 x s32>) = G_BITCAST %0(s64)
+# FAST-NEXT:     %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
+# FAST-NEXT:     %4:fpr(<2 x s32>) = G_OR %2, %3
+# GREEDY-NEXT:   %2:gpr(<2 x s32>) = G_BITCAST %0(s64)
+# GREEDY-NEXT:   %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
+# GREEDY-NEXT:   %4:gpr(<2 x s32>) = G_OR %2, %3
+# CHECK-NEXT:    %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
 # CHECK-NEXT:    %x0 = COPY %5(s64)
 # CHECK-NEXT:    RET_ReallyLR implicit %x0
-
 body:             |
   bb.0:
     liveins: %x0, %x1
@@ -686,12 +728,12 @@ registers:
   - { id: 3, class: _ }
 
 # No repairing should be necessary for both modes.
-# CHECK:         %0(s64) = COPY %x0
-# CHECK-NEXT:    %1(p0) = COPY %x1
-# CHECK-NEXT:    %2(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
+# CHECK:         %0:gpr(s64) = COPY %x0
+# CHECK-NEXT:    %1:gpr(p0) = COPY %x1
+# CHECK-NEXT:    %2:fpr(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
 # %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT:    %4(s64) = COPY %0
-# CHECK-NEXT:    %3(s64) = G_FADD %4, %2
+# CHECK-NEXT:    %4:fpr(s64) = COPY %0
+# CHECK-NEXT:    %3:fpr(s64) = G_FADD %4, %2
 # CHECK-NEXT:    %x0 = COPY %3(s64)
 # CHECK-NEXT:    RET_ReallyLR implicit %x0
 
@@ -726,12 +768,12 @@ registers:
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 
-# CHECK:         %0(s64) = COPY %x0
-# CHECK-NEXT:    %1(p0) = COPY %x1
+# CHECK:         %0:gpr(s64) = COPY %x0
+# CHECK-NEXT:    %1:gpr(p0) = COPY %x1
 # %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT:    %3(s64) = COPY %0
-# CHECK-NEXT:    %4(s64) = COPY %0
-# CHECK-NEXT:    %2(s64) = G_FADD %3, %4
+# CHECK-NEXT:    %3:fpr(s64) = COPY %0
+# CHECK-NEXT:    %4:fpr(s64) = COPY %0
+# CHECK-NEXT:    %2:fpr(s64) = G_FADD %3, %4
 # CHECK-NEXT:    G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
 # CHECK-NEXT:    RET_ReallyLR
 
@@ -746,3 +788,169 @@ body:             |
     RET_ReallyLR
 
 ...
+
+---
+# Make sure we map FPEXT on FPR register bank.
+# CHECK-LABEL: name: fp16Ext32
+name:            fp16Ext32
+alignment:       2
+legalized:       true
+# CHECK: registers:
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: fpr, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+# CHECK:         %1:gpr(s32) = COPY %w0
+# CHECK-NEXT:    %0:gpr(s16) = G_TRUNC %1
+# %0 has been mapped to GPR, we need to repair to match FPR.
+# CHECK-NEXT:    %3:fpr(s16) = COPY %0
+# CHECK-NEXT:    %2:fpr(s32) = G_FPEXT %3
+# CHECK-NEXT:    %s0 = COPY %2
+# CHECK-NEXT:    RET_ReallyLR
+
+body:             |
+  bb.1:
+    liveins: %w0
+
+    %1(s32) = COPY %w0
+    %0(s16) = G_TRUNC %1(s32)
+    %2(s32) = G_FPEXT %0(s16)
+    %s0 = COPY %2(s32)
+    RET_ReallyLR implicit %s0
+
+...
+
+---
+# Make sure we map FPEXT on FPR register bank.
+# CHECK-LABEL: name: fp16Ext64
+name:            fp16Ext64
+alignment:       2
+legalized:       true
+# CHECK: registers:
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 3, class: fpr, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+# CHECK:         %1:gpr(s32) = COPY %w0
+# CHECK-NEXT:    %0:gpr(s16) = G_TRUNC %1
+# %0 has been mapped to GPR, we need to repair to match FPR.
+# CHECK-NEXT:    %3:fpr(s16) = COPY %0
+# CHECK-NEXT:    %2:fpr(s64) = G_FPEXT %3
+# CHECK-NEXT:    %d0 = COPY %2
+# CHECK-NEXT:    RET_ReallyLR
+
+body:             |
+  bb.1:
+    liveins: %w0
+
+    %1(s32) = COPY %w0
+    %0(s16) = G_TRUNC %1(s32)
+    %2(s64) = G_FPEXT %0(s16)
+    %d0 = COPY %2(s64)
+    RET_ReallyLR implicit %d0
+
+...
+
+---
+# Make sure we map FPEXT on FPR register bank.
+# CHECK-LABEL: name: fp32Ext64
+name:            fp32Ext64
+alignment:       2
+legalized:       true
+# CHECK: registers:
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 2, class: fpr, preferred-register: '' }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+# CHECK:         %0:gpr(s32) = COPY %w0
+# %0 has been mapped to GPR, we need to repair to match FPR.
+# CHECK-NEXT:    %2:fpr(s32) = COPY %0
+# CHECK-NEXT:    %1:fpr(s64) = G_FPEXT %2
+# CHECK-NEXT:    %d0 = COPY %1
+# CHECK-NEXT:    RET_ReallyLR
+body:             |
+  bb.1:
+    liveins: %w0
+
+    %0(s32) = COPY %w0
+    %1(s64) = G_FPEXT %0(s32)
+    %d0 = COPY %1(s64)
+    RET_ReallyLR implicit %d0
+
+...
+
+---
+# Make sure we map FP16 ABI on FPR register bank.
+# CHECK-LABEL: name: passFp16
+# CHECK: registers:
+# CHECK:  - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:  %0:fpr(s16) = COPY %h0
+# CHECK-NEXT: %h0 = COPY %0(s16)
+name:            passFp16
+alignment:       2
+legalized:       true
+registers:
+  - { id: 0, class: _ }
+body:             |
+  bb.1.entry:
+    liveins: %h0
+
+    %0(s16) = COPY %h0
+    %h0 = COPY %0(s16)
+    RET_ReallyLR implicit %h0
+
+...
+---
+# Make sure we properly detect fp types through copies.
+# In that example, the copy comes from an ABI lowering of a fp type.
+# CHECK-LABEL: name: passFp16ViaAllocas
+# CHECK: registers:
+# CHECK:  - { id: 0, class: fpr, preferred-register: '' }
+# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 2, class: fpr, preferred-register: '' }
+#
+# CHECK:  %0:fpr(s16) = COPY %h0
+# CHECK-NEXT: %1:gpr(p0) = G_FRAME_INDEX %stack.0.p.addr
+# If we didn't look through the copy for %0, the default mapping
+# would have been on GPR and we would have to insert a copy to move
+# the value away from FPR (h0).
+# CHECK-NEXT: G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p.addr)
+# If we didn't look through the copy for %2, the default mapping
+# would have been on GPR and we would have to insert a copy to move
+# the value to FPR (h0).
+# CHECK-NEXT: %2:fpr(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
+# CHECK-NEXT: %h0 = COPY %2(s16)
+name:            passFp16ViaAllocas
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+frameInfo:
+  maxAlignment:    2
+stack:
+  - { id: 0, name: p.addr, size: 2, alignment: 2, stack-id: 0 }
+body:             |
+  bb.1.entry:
+    liveins: %h0
+
+    %0(s16) = COPY %h0
+    %1(p0) = G_FRAME_INDEX %stack.0.p.addr
+    G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p.addr)
+    %2(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
+    %h0 = COPY %2(s16)
+    RET_ReallyLR implicit %h0
+
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll b/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
index 38a90bbfbbd9..4b6fab704da1 100644
--- a/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
+++ b/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
@@ -5,12 +5,12 @@
 ; CHECK: fixedStack:
 ; CHECK-DAG:  - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
 ; CHECK-DAG:  - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
-; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; CHECK: [[LHS:%[0-9]+]](s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
-; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; CHECK: [[RHS:%[0-9]+]](s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
-; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[LHS]], [[RHS]]
-; CHECK: [[SUM32:%[0-9]+]](s32) = G_SEXT [[SUM]](s8)
+; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; CHECK: [[LHS:%[0-9]+]]:_(s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
+; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; CHECK: [[RHS:%[0-9]+]]:_(s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
+; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[LHS]], [[RHS]]
+; CHECK: [[SUM32:%[0-9]+]]:_(s32) = G_SEXT [[SUM]](s8)
 ; CHECK: %w0 = COPY [[SUM32]](s32)
 define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
   %sum = add i8 %lhs, %rhs
@@ -18,18 +18,77 @@ define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs)
 }
 
 ; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C42:%[0-9]+]](s8) = G_CONSTANT i8 42
-; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
-; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
+; CHECK: [[C42:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
+; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
 ; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store 1 into stack, align 0)
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[C12_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 1
-; CHECK: [[C12_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
 ; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1, align 0)
 ; CHECK: BL @test_stack_slots
 define void @test_call_stack() {
   call signext i8 @test_stack_slots([8 x i64] undef, i8 signext 42, i8 signext 12)
   ret void
 }
+
+; CHECK-LABEL: name: test_128bit_struct
+; CHECK: %x0 = COPY
+; CHECK: %x1 = COPY
+; CHECK: %x2 = COPY
+; CHECK: BL @take_128bit_struct
+define void @test_128bit_struct([2 x i64]* %ptr) {
+  %struct = load [2 x i64], [2 x i64]* %ptr
+  call void @take_128bit_struct([2 x i64]* null, [2 x i64] %struct)
+  ret void
+}
+
+; CHECK-LABEL: name: take_128bit_struct
+; CHECK: {{%.*}}:_(p0) = COPY %x0
+; CHECK: {{%.*}}:_(s64) = COPY %x1
+; CHECK: {{%.*}}:_(s64) = COPY %x2
+define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
+  store [2 x i64] %in, [2 x i64]* %ptr
+  ret void
+}
+
+; CHECK-LABEL: name: test_split_struct
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD {{.*}}(p0)
+; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
+; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
+
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
+; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
+
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
+; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)
+define void @test_split_struct([2 x i64]* %ptr) {
+  %struct = load [2 x i64], [2 x i64]* %ptr
+  call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
+                               i64 4, i64 5, i64 6,
+                               [2 x i64] %struct)
+  ret void
+}
+
+; CHECK-LABEL: name: take_split_struct
+; CHECK: fixedStack:
+; CHECK-DAG:   - { id: [[LO_FRAME:[0-9]+]], type: default, offset: 0, size: 8
+; CHECK-DAG:   - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
+
+; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
+; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
+
+; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
+; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
+define void @take_split_struct([2 x i64]* %ptr, i64, i64, i64,
+                               i64, i64, i64,
+                               [2 x i64] %in) {
+  store [2 x i64] %in, [2 x i64]* %ptr
+  ret void
+}
diff --git a/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/test/CodeGen/AArch64/GlobalISel/call-translator.ll
index 8fba8e09f9ff..23a39a336fa3 100644
--- a/test/CodeGen/AArch64/GlobalISel/call-translator.ll
+++ b/test/CodeGen/AArch64/GlobalISel/call-translator.ll
@@ -12,7 +12,7 @@ define void @test_trivial_call() {
 
 ; CHECK-LABEL: name: test_simple_return
 ; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit-def %x0
-; CHECK: [[RES:%[0-9]+]](s64) = COPY %x0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY %x0
 ; CHECK: %x0 = COPY [[RES]]
 ; CHECK: RET_ReallyLR implicit %x0
 declare i64 @simple_return_callee()
@@ -22,7 +22,7 @@ define i64 @test_simple_return() {
 }
 
 ; CHECK-LABEL: name: test_simple_arg
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
 ; CHECK: %w0 = COPY [[IN]]
 ; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
 ; CHECK: RET_ReallyLR
@@ -36,7 +36,7 @@ define void @test_simple_arg(i32 %in) {
 ; CHECK: registers:
 ; Make sure the register feeding the indirect call is properly constrained.
 ; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64, preferred-register: '' }
-; CHECK: %[[FUNC]](p0) = COPY %x0
+; CHECK: %[[FUNC]]:gpr64(p0) = COPY %x0
 ; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def %lr, implicit %sp
 ; CHECK: RET_ReallyLR
 define void @test_indirect_call(void()* %func) {
@@ -45,8 +45,8 @@ define void @test_indirect_call(void()* %func) {
 }
 
 ; CHECK-LABEL: name: test_multiple_args
-; CHECK: [[IN:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
+; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
 ; CHECK: %w0 = COPY [[ANSWER]]
 ; CHECK: %x1 = COPY [[IN]]
 ; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit %x1
@@ -59,16 +59,17 @@ define void @test_multiple_args(i64 %in) {
 
 
 ; CHECK-LABEL: name: test_struct_formal
-; CHECK: [[DBL:%[0-9]+]](s64) = COPY %d0
-; CHECK: [[I64:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[I8:%[0-9]+]](s8) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
+; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY %d0
+; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[I8:%[0-9]+]]:_(s8) = G_TRUNC [[I8_C]]
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
 
-; CHECK: [[UNDEF:%[0-9]+]](s192) = G_IMPLICIT_DEF
-; CHECK: [[ARG0:%[0-9]+]](s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
-; CHECK: [[ARG1:%[0-9]+]](s192) = G_INSERT [[ARG0]], [[I64]](s64), 64
-; CHECK: [[ARG2:%[0-9]+]](s192) = G_INSERT [[ARG1]], [[I8]](s8), 128
-; CHECK: [[ARG:%[0-9]+]](s192) = COPY [[ARG2]]
+; CHECK: [[UNDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
+; CHECK: [[ARG0:%[0-9]+]]:_(s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
+; CHECK: [[ARG1:%[0-9]+]]:_(s192) = G_INSERT [[ARG0]], [[I64]](s64), 64
+; CHECK: [[ARG2:%[0-9]+]]:_(s192) = G_INSERT [[ARG1]], [[I8]](s8), 128
+; CHECK: [[ARG:%[0-9]+]]:_(s192) = COPY [[ARG2]]
 
 ; CHECK: G_STORE [[ARG]](s192), [[ADDR]](p0)
 ; CHECK: RET_ReallyLR
@@ -79,12 +80,12 @@ define void @test_struct_formal({double, i64, i8} %in, {double, i64, i8}* %addr)
 
 
 ; CHECK-LABEL: name: test_struct_return
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s192) = G_LOAD [[ADDR]](p0)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s192) = G_LOAD [[ADDR]](p0)
 
-; CHECK: [[DBL:%[0-9]+]](s64) = G_EXTRACT [[VAL]](s192), 0
-; CHECK: [[I64:%[0-9]+]](s64) = G_EXTRACT [[VAL]](s192), 64
-; CHECK: [[I32:%[0-9]+]](s32) = G_EXTRACT [[VAL]](s192), 128
+; CHECK: [[DBL:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 0
+; CHECK: [[I64:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 64
+; CHECK: [[I32:%[0-9]+]]:_(s32) = G_EXTRACT [[VAL]](s192), 128
 
 ; CHECK: %d0 = COPY [[DBL]](s64)
 ; CHECK: %x0 = COPY [[I64]](s64)
@@ -97,23 +98,23 @@ define {double, i64, i32} @test_struct_return({double, i64, i32}* %addr) {
 
 ; CHECK-LABEL: name: test_arr_call
 ; CHECK: hasCalls: true
-; CHECK: [[ARG:%[0-9]+]](s256) = G_LOAD
+; CHECK: [[ARG:%[0-9]+]]:_(s256) = G_LOAD
 
-; CHECK: [[E0:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 0
-; CHECK: [[E1:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 64
-; CHECK: [[E2:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 128
-; CHECK: [[E3:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 192
+; CHECK: [[E0:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 0
+; CHECK: [[E1:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 64
+; CHECK: [[E2:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 128
+; CHECK: [[E3:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 192
 
 ; CHECK: %x0 = COPY [[E0]](s64)
 ; CHECK: %x1 = COPY [[E1]](s64)
 ; CHECK: %x2 = COPY [[E2]](s64)
 ; CHECK: %x3 = COPY [[E3]](s64)
 ; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2, implicit %x3, implicit-def %x0, implicit-def %x1, implicit-def %x2, implicit-def %x3
-; CHECK: [[E0:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[E1:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[E2:%[0-9]+]](s64) = COPY %x2
-; CHECK: [[E3:%[0-9]+]](s64) = COPY %x3
-; CHECK: [[RES:%[0-9]+]](s256) = G_MERGE_VALUES [[E0]](s64), [[E1]](s64), [[E2]](s64), [[E3]](s64)
+; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY %x2
+; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY %x3
+; CHECK: [[RES:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[E0]](s64), [[E1]](s64), [[E2]](s64), [[E3]](s64)
 ; CHECK: G_EXTRACT [[RES]](s256), 64
 declare [4 x i64] @arr_callee([4 x i64])
 define i64 @test_arr_call([4 x i64]* %addr) {
@@ -125,13 +126,14 @@ define i64 @test_arr_call([4 x i64]* %addr) {
 
 
 ; CHECK-LABEL: name: test_abi_exts_call
-; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
-; CHECK: %w0 = COPY [[VAL]]
+; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
+; CHECK: [[VAL_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[VAL]]
+; CHECK: %w0 = COPY [[VAL_TMP]]
 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
-; CHECK: [[SVAL:%[0-9]+]](s32) = G_SEXT [[VAL]](s8)
+; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
 ; CHECK: %w0 = COPY [[SVAL]](s32)
 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
-; CHECK: [[ZVAL:%[0-9]+]](s32) = G_ZEXT [[VAL]](s8)
+; CHECK: [[ZVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
 ; CHECK: %w0 = COPY [[ZVAL]](s32)
 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
 declare void @take_char(i8)
@@ -144,8 +146,8 @@ define void @test_abi_exts_call(i8* %addr) {
 }
 
 ; CHECK-LABEL: name: test_abi_sext_ret
-; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
-; CHECK: [[SVAL:%[0-9]+]](s32) = G_SEXT [[VAL]](s8)
+; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
+; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
 ; CHECK: %w0 = COPY [[SVAL]](s32)
 ; CHECK: RET_ReallyLR implicit %w0
 define signext i8 @test_abi_sext_ret(i8* %addr) {
@@ -154,8 +156,8 @@ define signext i8 @test_abi_sext_ret(i8* %addr) {
 }
 
 ; CHECK-LABEL: name: test_abi_zext_ret
-; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
-; CHECK: [[SVAL:%[0-9]+]](s32) = G_ZEXT [[VAL]](s8)
+; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
+; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
 ; CHECK: %w0 = COPY [[SVAL]](s32)
 ; CHECK: RET_ReallyLR implicit %w0
 define zeroext i8 @test_abi_zext_ret(i8* %addr) {
@@ -168,13 +170,13 @@ define zeroext i8 @test_abi_zext_ret(i8* %addr) {
 ; CHECK-DAG:  - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8,
 ; CHECK-DAG:  - { id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8,
 ; CHECK-DAG:  - { id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 8,
-; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; CHECK: [[LHS:%[0-9]+]](s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
-; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; CHECK: [[RHS:%[0-9]+]](s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
-; CHECK: [[ADDR_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
-; CHECK: [[ADDR:%[0-9]+]](p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0)
-; CHECK: [[SUM:%[0-9]+]](s64) = G_ADD [[LHS]], [[RHS]]
+; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; CHECK: [[LHS:%[0-9]+]]:_(s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
+; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; CHECK: [[RHS:%[0-9]+]]:_(s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
+; CHECK: [[ADDR_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0)
+; CHECK: [[SUM:%[0-9]+]]:_(s64) = G_ADD [[LHS]], [[RHS]]
 ; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0)
 define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
   %sum = add i64 %lhs, %rhs
@@ -183,21 +185,21 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
 }
 
 ; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42
-; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
-; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
+; CHECK: [[C42:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
 ; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def %sp, implicit %sp
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
-; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
 ; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 0)
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[C12_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 8
-; CHECK: [[C12_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
 ; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 0)
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[PTR_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 16
-; CHECK: [[PTR_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[PTR_OFFS]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[PTR_OFFS]](s64)
 ; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store 8 into stack + 16, align 0)
 ; CHECK: BL @test_stack_slots
 ; CHECK: ADJCALLSTACKUP 24, 0, implicit-def %sp, implicit %sp
@@ -208,9 +210,69 @@ define void @test_call_stack() {
 
 ; CHECK-LABEL: name: test_mem_i1
 ; CHECK: fixedStack:
-; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
-; CHECK: [[ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
-; CHECK: {{%[0-9]+}}(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
+; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
+; CHECK-NEXT: isImmutable: true,
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
+; CHECK: {{%[0-9]+}}:_(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
 define void @test_mem_i1([8 x i64], i1 %in) {
   ret void
 }
+
+; CHECK-LABEL: name: test_128bit_struct
+; CHECK: %x0 = COPY
+; CHECK: %x1 = COPY
+; CHECK: %x2 = COPY
+; CHECK: BL @take_128bit_struct
+define void @test_128bit_struct([2 x i64]* %ptr) {
+  %struct = load [2 x i64], [2 x i64]* %ptr
+  call void @take_128bit_struct([2 x i64]* null, [2 x i64] %struct)
+  ret void
+}
+
+; CHECK-LABEL: name: take_128bit_struct
+; CHECK: {{%.*}}:_(p0) = COPY %x0
+; CHECK: {{%.*}}:_(s64) = COPY %x1
+; CHECK: {{%.*}}:_(s64) = COPY %x2
+define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
+  store [2 x i64] %in, [2 x i64]* %ptr
+  ret void
+}
+
+; CHECK-LABEL: name: test_split_struct
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD {{.*}}(p0)
+; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
+; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
+
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
+; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
+
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
+; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)
+define void @test_split_struct([2 x i64]* %ptr) {
+  %struct = load [2 x i64], [2 x i64]* %ptr
+  call void @take_split_struct([2 x i64]* null, i64 1, i64 2, i64 3,
+                               i64 4, i64 5, i64 6,
+                               [2 x i64] %struct)
+  ret void
+}
+
+; CHECK-LABEL: name: take_split_struct
+; CHECK: fixedStack:
+; CHECK-DAG:   - { id: [[LO_FRAME:[0-9]+]], type: default, offset: 0, size: 8
+; CHECK-DAG:   - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
+
+; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
+; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
+
+; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
+; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
+define void @take_split_struct([2 x i64]* %ptr, i64, i64, i64,
+                               i64, i64, i64,
+                               [2 x i64] %in) {
+  store [2 x i64] %in, [2 x i64]* %ptr
+  ret void
+}
diff --git a/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir b/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir
new file mode 100644
index 000000000000..339adf51451b
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir
@@ -0,0 +1,42 @@
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  
+  define void @test_anyext_crash() {
+  entry:
+    br label %block2
+  
+  block2:
+    %0 = trunc i16 0 to i8
+    %1 = uitofp i8 %0 to double
+    br label %block2
+  }
+  
+
+...
+---
+name:            test_anyext_crash
+alignment:       2
+legalized:       false
+registers:       
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+body:             |
+  bb.1:
+   ; Check we don't crash due to trying to legalize a dead instruction.
+   ; CHECK-LABEL: test_anyext_crash
+   ; CHECK-LABEL: bb.1:
+    successors: %bb.2
+  
+    %0(s16) = G_CONSTANT i16 0
+  
+  bb.2:
+    successors: %bb.2
+  
+    %1(s8) = G_TRUNC %0(s16)
+    %2(s64) = G_UITOFP %1(s8)
+    G_BR %bb.2
+
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/debug-insts.ll b/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
index e832ba953241..be510b5f7e3b 100644
--- a/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
+++ b/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
@@ -3,42 +3,43 @@
 
 ; CHECK-LABEL: name: debug_declare
 ; CHECK: stack:
-; CHECK:    - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}}, 
-; CHECK-NEXT: callee-saved-register: '', di-variable: '!11', di-expression: '!12',
-; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !12, debug-location !13
+; CHECK:    - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
+; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
+; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
+; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !11, !DIExpression(), debug-location !12
 define void @debug_declare(i32 %in) #0 !dbg !7 {
 entry:
   %in.addr = alloca i32, align 4
   store i32 %in, i32* %in.addr, align 4
-  call void @llvm.dbg.declare(metadata i32* %in.addr, metadata !11, metadata !12), !dbg !13
-  call void @llvm.dbg.declare(metadata i32 %in, metadata !11, metadata !12), !dbg !13
-  ret void, !dbg !13
+  call void @llvm.dbg.declare(metadata i32* %in.addr, metadata !11, metadata !DIExpression()), !dbg !12
+  call void @llvm.dbg.declare(metadata i32 %in, metadata !11, metadata !DIExpression()), !dbg !12
+  ret void, !dbg !12
 }
 
 ; CHECK-LABEL: name: debug_declare_vla
-; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use _, !15, !12, debug-location !16
-define void @debug_declare_vla(i32 %in) #0 !dbg !14 {
+; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use %noreg, !14, !DIExpression(), debug-location !15
+define void @debug_declare_vla(i32 %in) #0 !dbg !13 {
 entry:
   %vla.addr = alloca i32, i32 %in
-  call void @llvm.dbg.declare(metadata i32* %vla.addr, metadata !15, metadata !12), !dbg !16
-  ret void, !dbg !16
+  call void @llvm.dbg.declare(metadata i32* %vla.addr, metadata !14, metadata !DIExpression()), !dbg !15
+  ret void, !dbg !15
 }
 
 ; CHECK-LABEL: name: debug_value
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
-define void @debug_value(i32 %in) #0 !dbg !17 {
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
+define void @debug_value(i32 %in) #0 !dbg !16 {
   %addr = alloca i32
-; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use _, !18, !12, debug-location !19
-  call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !18, metadata !12), !dbg !19
+; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use %noreg, !17, !DIExpression(), debug-location !18
+  call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
   store i32 %in, i32* %addr
-; CHECK: DBG_VALUE debug-use %1(p0), debug-use _, !18, !20, debug-location !19
-  call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !18, metadata !20), !dbg !19
-; CHECK: DBG_VALUE 123, 0, !18, !12, debug-location !19
-  call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !18, metadata !12), !dbg !19
-; CHECK: DBG_VALUE float 1.000000e+00, 0, !18, !12, debug-location !19
-  call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !18, metadata !12), !dbg !19
-; CHECK: DBG_VALUE _, 0, !18, !12, debug-location !19
-  call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !18, metadata !12), !dbg !19
+; CHECK: DBG_VALUE debug-use %1(p0), debug-use %noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
+  call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18
+; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18
+  call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
+; CHECK: DBG_VALUE float 1.000000e+00, 0, !17, !DIExpression(), debug-location !18
+  call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
+; CHECK: DBG_VALUE %noreg, 0, !17, !DIExpression(), debug-location !18
+  call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
   ret void
 }
 
@@ -62,12 +63,10 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
 !9 = !{null, !10}
 !10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
 !11 = !DILocalVariable(name: "in", arg: 1, scope: !7, file: !1, line: 1, type: !10)
-!12 = !DIExpression()
-!13 = !DILocation(line: 1, column: 14, scope: !7)
-!14 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
-!15 = !DILocalVariable(name: "in", arg: 1, scope: !14, file: !1, line: 1, type: !10)
-!16 = !DILocation(line: 1, column: 14, scope: !14)
-!17 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
-!18 = !DILocalVariable(name: "in", arg: 1, scope: !17, file: !1, line: 1, type: !10)
-!19 = !DILocation(line: 1, column: 14, scope: !17)
-!20 = !DIExpression(DW_OP_deref)
+!12 = !DILocation(line: 1, column: 14, scope: !7)
+!13 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+!14 = !DILocalVariable(name: "in", arg: 1, scope: !13, file: !1, line: 1, type: !10)
+!15 = !DILocation(line: 1, column: 14, scope: !13)
+!16 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+!17 = !DILocalVariable(name: "in", arg: 1, scope: !16, file: !1, line: 1, type: !10)
+!18 = !DILocation(line: 1, column: 14, scope: !16)
diff --git a/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll b/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
index 196910e96ce3..62aceaa81308 100644
--- a/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
+++ b/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
@@ -1,15 +1,15 @@
 ; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=irtranslator | FileCheck %s
 
 ; CHECK-LABEL: name: test_simple_alloca
-; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -1
-; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
-; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
-; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
-; CHECK: [[ALIGNED_ALLOC:%[0-9]+]](p0) = G_PTR_MASK [[ALLOC]], 4
+; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
+; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
+; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
+; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 4
 ; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
-; CHECK: [[ALLOC:%[0-9]+]](p0) = COPY [[ALIGNED_ALLOC]]
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
 ; CHECK: %x0 = COPY [[ALLOC]]
 define i8* @test_simple_alloca(i32 %numelts) {
   %addr = alloca i8, i32 %numelts
@@ -17,15 +17,15 @@ define i8* @test_simple_alloca(i32 %numelts) {
 }
 
 ; CHECK-LABEL: name: test_aligned_alloca
-; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -1
-; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
-; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
-; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
-; CHECK: [[ALIGNED_ALLOC:%[0-9]+]](p0) = G_PTR_MASK [[ALLOC]], 5
+; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
+; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
+; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
+; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 5
 ; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
-; CHECK: [[ALLOC:%[0-9]+]](p0) = COPY [[ALIGNED_ALLOC]]
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
 ; CHECK: %x0 = COPY [[ALLOC]]
 define i8* @test_aligned_alloca(i32 %numelts) {
   %addr = alloca i8, i32 %numelts, align 32
@@ -33,14 +33,14 @@ define i8* @test_aligned_alloca(i32 %numelts) {
 }
 
 ; CHECK-LABEL: name: test_natural_alloca
-; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -16
-; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
-; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
-; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
+; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
+; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
+; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
+; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
 ; CHECK: %sp = COPY [[ALLOC]]
-; CHECK: [[ALLOC_TMP:%[0-9]+]](p0) = COPY [[ALLOC]]
+; CHECK: [[ALLOC_TMP:%[0-9]+]]:_(p0) = COPY [[ALLOC]]
 ; CHECK: %x0 = COPY [[ALLOC_TMP]]
 define i128* @test_natural_alloca(i32 %numelts) {
   %addr = alloca i128, i32 %numelts
diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
index 8d1b02216ea7..70dddeb45859 100644
--- a/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
+++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
@@ -23,7 +23,7 @@ define i32 @test_bitcast_invalid_vreg() {
   %tmp15 = add i32 30, 30
 
 ; At this point we mapped 46 values. The 'i32 100' constant will grow the map.
-; CHECK:  %46(s32) = G_CONSTANT i32 100
+; CHECK:  %46:_(s32) = G_CONSTANT i32 100
 ; CHECK:  %w0 = COPY %46(s32)
   %res = bitcast i32 100 to i32
   ret i32 %res
diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index d9fec0ec7d46..827fdd261082 100644
--- a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -9,30 +9,30 @@ declare i32 @llvm.eh.typeid.for(i8*)
 ; CHECK-LABEL: name: bar
 ; CHECK: body:
 ; CHECK-NEXT:   bb.1 (%ir-block.0):
-; CHECK:     successors: %[[GOOD:bb.[0-9]+.continue]]{{.*}}%[[BAD:bb.[0-9]+.broken]]
+; CHECK:     successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
 ; CHECK:     EH_LABEL
 ; CHECK:     %w0 = COPY
 ; CHECK:     BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
-; CHECK:     {{%[0-9]+}}(s32) = COPY %w0
+; CHECK:     {{%[0-9]+}}:_(s32) = COPY %w0
 ; CHECK:     EH_LABEL
 ; CHECK:     G_BR %[[GOOD]]
 
-; CHECK:   [[BAD]] (landing-pad):
+; CHECK:   [[BAD]].{{[a-z]+}} (landing-pad):
 ; CHECK:     EH_LABEL
-; CHECK:     [[UNDEF:%[0-9]+]](s128) = G_IMPLICIT_DEF
-; CHECK:     [[PTR:%[0-9]+]](p0) = COPY %x0
-; CHECK:     [[VAL_WITH_PTR:%[0-9]+]](s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
-; CHECK:     [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
-; CHECK:     [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
-; CHECK:     [[PTR_SEL:%[0-9]+]](s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
-; CHECK:     [[PTR_RET:%[0-9]+]](s64) = G_EXTRACT [[PTR_SEL]](s128), 0
-; CHECK:     [[SEL_RET:%[0-9]+]](s32) = G_EXTRACT [[PTR_SEL]](s128), 64
+; CHECK:     [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
+; CHECK:     [[PTR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK:     [[VAL_WITH_PTR:%[0-9]+]]:_(s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
+; CHECK:     [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK:     [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
+; CHECK:     [[PTR_SEL:%[0-9]+]]:_(s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
+; CHECK:     [[PTR_RET:%[0-9]+]]:_(s64) = G_EXTRACT [[PTR_SEL]](s128), 0
+; CHECK:     [[SEL_RET:%[0-9]+]]:_(s32) = G_EXTRACT [[PTR_SEL]](s128), 64
 ; CHECK:     %x0 = COPY [[PTR_RET]]
 ; CHECK:     %w1 = COPY [[SEL_RET]]
 
-; CHECK:   [[GOOD]]:
-; CHECK:     [[SEL:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK:     {{%[0-9]+}}(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64
+; CHECK:   [[GOOD]].{{[a-z]+}}:
+; CHECK:     [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK:     {{%[0-9]+}}:_(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64
 
 define { i8*, i32 } @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
   %res32 = invoke i32 @foo(i32 42) to label %continue unwind label %broken
@@ -49,7 +49,7 @@ continue:
 }
 
 ; CHECK-LABEL: name: test_invoke_indirect
-; CHECK: [[CALLEE:%[0-9]+]](p0) = COPY %x0
+; CHECK: [[CALLEE:%[0-9]+]]:gpr64(p0) = COPY %x0
 ; CHECK: BLR [[CALLEE]]
 define void @test_invoke_indirect(void()* %callee) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
   invoke void %callee() to label %continue unwind label %broken
@@ -64,20 +64,20 @@ continue:
 
 ; CHECK-LABEL: name: test_invoke_varargs
 
-; CHECK: [[NULL:%[0-9]+]](p0) = G_CONSTANT i64 0
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: [[ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.0
+; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.0
 
 ; CHECK: %x0 = COPY [[NULL]]
 
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 0
-; CHECK: [[SLOT:%[0-9]+]](p0) = G_GEP [[SP]], [[OFFSET]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
 ; CHECK: G_STORE [[ANSWER]](s32), [[SLOT]]
 
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 8
-; CHECK: [[SLOT:%[0-9]+]](p0) = G_GEP [[SP]], [[OFFSET]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
 ; CHECK: G_STORE [[ONE]](s32), [[SLOT]]
 
 ; CHECK: BL @printf
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index 9b27198b961a..99b37d0925b7 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -7,6 +8,10 @@
   entry:
     ret void
   }
+  define void @test_scalar_add_big_nonpow2() {
+  entry:
+    ret void
+  }
   define void @test_scalar_add_small() {
   entry:
     ret void
@@ -15,10 +20,43 @@
   entry:
     ret void
   }
+  define void @test_vector_add_nonpow2() {
+  entry:
+    ret void
+  }
 ...
 
 ---
 name:            test_scalar_add_big
+body: |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+
+    ; CHECK-LABEL: name: test_scalar_add_big
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
+    ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
+    ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
+    ; CHECK: %x0 = COPY [[UADDE]](s64)
+    ; CHECK: %x1 = COPY [[UADDE2]](s64)
+    %0:_(s64) = COPY %x0
+    %1:_(s64) = COPY %x1
+    %2:_(s64) = COPY %x2
+    %3:_(s64) = COPY %x3
+    %4:_(s128) = G_MERGE_VALUES %0, %1
+    %5:_(s128) = G_MERGE_VALUES %2, %3
+    %6:_(s128) = G_ADD %4, %5
+    %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
+    %x0 = COPY %7
+    %x1 = COPY %8
+...
+
+---
+name:            test_scalar_add_big_nonpow2
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -29,62 +67,88 @@ registers:
   - { id: 6, class: _ }
   - { id: 7, class: _ }
   - { id: 8, class: _ }
+  - { id: 9, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    ; CHECK-LABEL: name: test_scalar_add_big
+    ; CHECK-LABEL: name: test_scalar_add_big_nonpow2
     ; CHECK-NOT: G_MERGE_VALUES
     ; CHECK-NOT: G_UNMERGE_VALUES
-    ; CHECK-DAG: [[CARRY0_32:%.*]](s32) = G_CONSTANT i32 0
-    ; CHECK-DAG: [[CARRY0:%[0-9]+]](s1) = G_TRUNC [[CARRY0_32]]
-    ; CHECK: [[RES_LO:%.*]](s64), [[CARRY:%.*]](s1) = G_UADDE %0, %2, [[CARRY0]]
-    ; CHECK: [[RES_HI:%.*]](s64), {{%.*}}(s1) = G_UADDE %1, %3, [[CARRY]]
+    ; CHECK-DAG: [[CARRY0_32:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK-DAG: [[CARRY0:%[0-9]+]]:_(s1) = G_TRUNC [[CARRY0_32]]
+    ; CHECK: [[RES_LO:%[0-9]+]]:_(s64), [[CARRY1:%[0-9]+]]:_(s1) = G_UADDE %0, %1, [[CARRY0]]
+    ; CHECK: [[RES_MI:%[0-9]+]]:_(s64), [[CARRY2:%[0-9]+]]:_(s1) = G_UADDE %1, %2, [[CARRY1]]
+    ; CHECK: [[RES_HI:%[0-9]+]]:_(s64), {{%.*}}(s1) = G_UADDE %2, %3, [[CARRY2]]
     ; CHECK-NOT: G_MERGE_VALUES
     ; CHECK-NOT: G_UNMERGE_VALUES
     ; CHECK: %x0 = COPY [[RES_LO]]
-    ; CHECK: %x1 = COPY [[RES_HI]]
+    ; CHECK: %x1 = COPY [[RES_MI]]
+    ; CHECK: %x2 = COPY [[RES_HI]]
 
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = COPY %x2
     %3(s64) = COPY %x3
-    %4(s128) = G_MERGE_VALUES %0, %1
-    %5(s128) = G_MERGE_VALUES %2, %3
-    %6(s128) = G_ADD %4, %5
-    %7(s64), %8(s64) = G_UNMERGE_VALUES %6
+    %4(s192) = G_MERGE_VALUES %0, %1, %2
+    %5(s192) = G_MERGE_VALUES %1, %2, %3
+    %6(s192) = G_ADD %4, %5
+    %7(s64), %8(s64), %9(s64) = G_UNMERGE_VALUES %6
     %x0 = COPY %7
     %x1 = COPY %8
+    %x2 = COPY %9
 ...
 
 ---
 name:            test_scalar_add_small
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
-  - { id: 5, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    ; CHECK-LABEL: name: test_scalar_add_small
-    ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8)
-    ; CHECK: [[RES32:%.*]](s32) = G_ADD [[OP0]], [[OP1]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
 
-    %0(s64) = COPY %x0
-    %1(s64) = COPY %x1
-    %2(s8) = G_TRUNC %0
-    %3(s8) = G_TRUNC %1
-    %4(s8) = G_ADD %2, %3
-    %5(s64) = G_ANYEXT %4
+    ; CHECK-LABEL: name: test_scalar_add_small
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
+    ; CHECK: %x0 = COPY [[ANYEXT]](s64)
+    %0:_(s64) = COPY %x0
+    %1:_(s64) = COPY %x1
+    %2:_(s8) = G_TRUNC %0
+    %3:_(s8) = G_TRUNC %1
+    %4:_(s8) = G_ADD %2, %3
+    %5:_(s64) = G_ANYEXT %4
     %x0 = COPY %5
 ...
 
 ---
 name:            test_vector_add
+body: |
+  bb.0.entry:
+    liveins: %q0, %q1, %q2, %q3
+
+    ; CHECK-LABEL: name: test_vector_add
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY %q0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY %q1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY %q2
+    ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY %q3
+    ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
+    ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
+    ; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
+    ; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
+    %0:_(<2 x s64>) = COPY %q0
+    %1:_(<2 x s64>) = COPY %q1
+    %2:_(<2 x s64>) = COPY %q2
+    %3:_(<2 x s64>) = COPY %q3
+    %4:_(<4 x s64>) = G_MERGE_VALUES %0, %1
+    %5:_(<4 x s64>) = G_MERGE_VALUES %2, %3
+    %6:_(<4 x s64>) = G_ADD %4, %5
+    %7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6
+    %q0 = COPY %7
+    %q1 = COPY %8
+...
+---
+name:            test_vector_add_nonpow2
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -95,27 +159,31 @@ registers:
   - { id: 6, class: _ }
   - { id: 7, class: _ }
   - { id: 8, class: _ }
+  - { id: 9, class: _ }
 body: |
   bb.0.entry:
     liveins: %q0, %q1, %q2, %q3
-    ; CHECK-LABEL: name: test_vector_add
+    ; CHECK-LABEL: name: test_vector_add_nonpow2
     ; CHECK-NOT: G_EXTRACT
     ; CHECK-NOT: G_SEQUENCE
-    ; CHECK: [[RES_LO:%.*]](<2 x s64>) = G_ADD %0, %2
-    ; CHECK: [[RES_HI:%.*]](<2 x s64>) = G_ADD %1, %3
+    ; CHECK: [[RES_LO:%[0-9]+]]:_(<2 x s64>) = G_ADD %0, %1
+    ; CHECK: [[RES_MI:%[0-9]+]]:_(<2 x s64>) = G_ADD %1, %2
+    ; CHECK: [[RES_HI:%[0-9]+]]:_(<2 x s64>) = G_ADD %2, %3
     ; CHECK-NOT: G_EXTRACT
     ; CHECK-NOT: G_SEQUENCE
     ; CHECK: %q0 = COPY [[RES_LO]]
-    ; CHECK: %q1 = COPY [[RES_HI]]
+    ; CHECK: %q1 = COPY [[RES_MI]]
+    ; CHECK: %q2 = COPY [[RES_HI]]
 
     %0(<2 x s64>) = COPY %q0
     %1(<2 x s64>) = COPY %q1
     %2(<2 x s64>) = COPY %q2
     %3(<2 x s64>) = COPY %q3
-    %4(<4 x s64>) = G_MERGE_VALUES %0, %1
-    %5(<4 x s64>) = G_MERGE_VALUES %2, %3
-    %6(<4 x s64>) = G_ADD %4, %5
-    %7(<2 x s64>), %8(<2 x s64>) = G_UNMERGE_VALUES %6
+    %4(<6 x s64>) = G_MERGE_VALUES %0, %1, %2
+    %5(<6 x s64>) = G_MERGE_VALUES %1, %2, %3
+    %6(<6 x s64>) = G_ADD %4, %5
+    %7(<2 x s64>), %8(<2 x s64>), %9(<2 x s64>) = G_UNMERGE_VALUES %6
     %q0 = COPY %7
     %q1 = COPY %8
+    %q2 = COPY %9
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index 75e1d5163532..b2f24a738be2 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -18,20 +19,28 @@ registers:
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
+  - { id: 6, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    ; CHECK-LABEL: name: test_scalar_and_small
-    ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8)
-    ; CHECK: [[RES32:%.*]](s32) = G_AND [[OP0]], [[OP1]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
 
+    ; CHECK-LABEL: name: test_scalar_and_small
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
+    ; CHECK: %w0 = COPY [[COPY2]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: %x0 = COPY [[COPY3]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_AND %2, %3
+    %6(s32) = G_ANYEXT %4
+    %w0 = COPY %6
     %5(s64) = G_ANYEXT %2
     %x0 = COPY %5
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir b/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
new file mode 100644
index 000000000000..b77d5e9a1d6d
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=legalizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @cmpxchg_i8(i8* %addr) { ret void }
+  define void @cmpxchg_i16(i16* %addr) { ret void }
+  define void @cmpxchg_i32(i32* %addr) { ret void }
+  define void @cmpxchg_i64(i64* %addr) { ret void }
+...
+
+---
+name:            cmpxchg_i8
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i8
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[CST2:%[0-9]+]]:_(s8) = G_TRUNC [[CST]]
+    ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 1 on %ir.addr)
+    ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
+    ; CHECK: %w0 = COPY [[RES2]]
+    %0:_(p0) = COPY %x0
+    %1:_(s8) = G_CONSTANT i8 1
+    %2:_(s8) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 1 on %ir.addr)
+    %3:_(s32) = G_ANYEXT %2
+    %w0 = COPY %3(s32)
+...
+
+---
+name:            cmpxchg_i16
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i16
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[CST2:%[0-9]+]]:_(s16) = G_TRUNC [[CST]]
+    ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 2 on %ir.addr)
+    ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
+    ; CHECK: %w0 = COPY [[RES2]]
+    %0:_(p0) = COPY %x0
+    %1:_(s16) = G_CONSTANT i16 1
+    %2:_(s16) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 2 on %ir.addr)
+    %3:_(s32) = G_ANYEXT %2
+    %w0 = COPY %3(s32)
+...
+
+---
+name:            cmpxchg_i32
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i32
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 4 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:_(p0) = COPY %x0
+    %1:_(s32) = G_CONSTANT i32 1
+    %2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 4 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            cmpxchg_i64
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i64
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 8 on %ir.addr)
+    ; CHECK: %x0 = COPY [[RES]]
+    %0:_(p0) = COPY %x0
+    %1:_(s64) = G_CONSTANT i64 1
+    %2:_(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
+    %x0 = COPY %2(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
index 29f83b362895..dba2ba8d6836 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -23,23 +24,48 @@ registers:
   - { id: 8, class: _ }
   - { id: 9, class: _ }
   - { id: 10, class: _ }
+  - { id: 11, class: _ }
+  - { id: 12, class: _ }
+  - { id: 13, class: _ }
+  - { id: 14, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
+    ; CHECK-LABEL: name: test_icmp
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; CHECK: %w0 = COPY [[COPY2]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
+    ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; CHECK: %w0 = COPY [[COPY3]](s32)
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; CHECK: %w0 = COPY [[COPY4]](s32)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x0
 
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
 
-    ; CHECK: %4(s1) = G_ICMP intpred(sge), %0(s64), %1
     %4(s1) = G_ICMP intpred(sge), %0, %1
+    %11(s32) = G_ANYEXT %4
+    %w0 = COPY %11
 
-    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2
-    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3
-    ; CHECK: %8(s1) = G_ICMP intpred(ult), [[LHS32]](s32), [[RHS32]]
     %8(s1) = G_ICMP intpred(ult), %2, %3
+    %12(s32) = G_ANYEXT %8
+    %w0 = COPY %12
 
     %9(p0) = G_INTTOPTR %0(s64)
     %10(s1) = G_ICMP intpred(eq), %9(p0), %9(p0)
+    %14(s32) = G_ANYEXT %10
+    %w0 = COPY %14
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir b/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
new file mode 100644
index 000000000000..633033670cc9
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
@@ -0,0 +1,59 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=legalizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @cmpxchg_i32(i64* %addr) { ret void }
+  define void @cmpxchg_i64(i64* %addr) { ret void }
+...
+
+---
+name:            cmpxchg_i32
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i32
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
+    ; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s32), [[CMP]]
+    ; CHECK: [[SRES32:%[0-9]+]]:_(s32) = COPY [[SRES]]
+    ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[RES]], [[SRES32]]
+    ; CHECK: %w0 = COPY [[MUL]]
+    %0:_(p0) = COPY %x0
+    %1:_(s32) = G_CONSTANT i32 0
+    %2:_(s32) = G_CONSTANT i32 1
+    %3:_(s32), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
+    %5:_(s32) = G_ANYEXT %4
+    %6:_(s32) = G_MUL %3, %5
+    %w0 = COPY %6(s32)
+...
+
+---
+name:            cmpxchg_i64
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i64
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
+    ; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s64), [[CMP]]
+    ; CHECK: [[SRES64:%[0-9]+]]:_(s64) = G_ANYEXT [[SRES]]
+    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[RES]], [[SRES64]]
+    ; CHECK: %x0 = COPY [[MUL]]
+    %0:_(p0) = COPY %x0
+    %1:_(s64) = G_CONSTANT i64 0
+    %2:_(s64) = G_CONSTANT i64 1
+    %3:_(s64), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
+    %5:_(s64) = G_ANYEXT %4
+    %6:_(s64) = G_MUL %3, %5
+    %x0 = COPY %6(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir b/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
new file mode 100644
index 000000000000..898cd12d1180
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=legalizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @cmpxchg_i8(i8* %addr) { ret void }
+  define void @cmpxchg_i16(i16* %addr) { ret void }
+  define void @cmpxchg_i32(i32* %addr) { ret void }
+  define void @cmpxchg_i64(i64* %addr) { ret void }
+...
+
+---
+name:            cmpxchg_i8
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i8
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[CMPT:%[0-9]+]]:_(s8) = G_TRUNC [[CMP]]
+    ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[CSTT:%[0-9]+]]:_(s8) = G_TRUNC [[CST]]
+    ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 1 on %ir.addr)
+    ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s8)
+    ; CHECK: %w0 = COPY [[RES2]]
+    %0:_(p0) = COPY %x0
+    %1:_(s8) = G_CONSTANT i8 0
+    %2:_(s8) = G_CONSTANT i8 1
+    %3:_(s8) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 1 on %ir.addr)
+    %4:_(s32) = G_ANYEXT %3
+    %w0 = COPY %4(s32)
+...
+
+---
+name:            cmpxchg_i16
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i16
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[CMPT:%[0-9]+]]:_(s16) = G_TRUNC [[CMP]]
+    ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[CSTT:%[0-9]+]]:_(s16) = G_TRUNC [[CST]]
+    ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 2 on %ir.addr)
+    ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s16)
+    ; CHECK: %w0 = COPY [[RES2]]
+    %0:_(p0) = COPY %x0
+    %1:_(s16) = G_CONSTANT i16 0
+    %2:_(s16) = G_CONSTANT i16 1
+    %3:_(s16) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 2 on %ir.addr)
+    %4:_(s32) = G_ANYEXT %3
+    %w0 = COPY %4(s32)
+...
+
+---
+name:            cmpxchg_i32
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i32
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 4 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:_(p0) = COPY %x0
+    %1:_(s32) = G_CONSTANT i32 0
+    %2:_(s32) = G_CONSTANT i32 1
+    %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 4 on %ir.addr)
+    %w0 = COPY %3(s32)
+...
+
+---
+name:            cmpxchg_i64
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i64
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
+    ; CHECK: %x0 = COPY [[RES]]
+    %0:_(p0) = COPY %x0
+    %1:_(s64) = G_CONSTANT i64 0
+    %2:_(s64) = G_CONSTANT i64 1
+    %3:_(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
+    %x0 = COPY %3(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir b/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
index fbacc28d7434..9cf0f8fd0e71 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -7,7 +8,6 @@
   define void @test_combines_3() { ret void }
   define void @test_combines_4() { ret void }
   define void @test_combines_5() { ret void }
-  define void @test_combines_6() { ret void }
 ...
 
 ---
@@ -16,17 +16,22 @@ body: |
   bb.0:
     liveins: %w0
 
+    ; Here the types don't match.
+    ; CHECK-LABEL: name: test_combines_2
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s1) = G_EXTRACT [[MV]](s64), 0
+    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[MV]](s64), 0
     %0:_(s32) = COPY %w0
 
-      ; Similarly, here the types don't match.
-    ; CHECK-LABEL: name: test_combines_2
-    ; CHECK: %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
-    ; CHECK: %3(s1) = G_EXTRACT %2(s64), 0
-    ; CHECK: %4(s64) = G_EXTRACT %2(s64), 0
     %1:_(s32) = G_ADD %0, %0
     %2:_(s64) = G_MERGE_VALUES %0, %1
     %3:_(s1) = G_EXTRACT %2, 0
+    %5:_(s32) = G_ANYEXT %3
+    %w0 = COPY %5
     %4:_(s64) = G_EXTRACT %2, 0
+    %x0 = COPY %4
 ...
 
 ---
@@ -35,17 +40,17 @@ body: |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: test_combines_3
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
     %0:_(s32) = COPY %w0
 
-    ; CHECK-LABEL: name: test_combines_3
-    ; CHECK: %1(s32) = G_ADD %0, %0
-    ; CHECK-NOT: G_SEQUENCE
-    ; CHECK-NOT: G_EXTRACT
-    ; CHECK: %5(s32) = G_ADD %0, %1
     %1:_(s32) = G_ADD %0, %0
     %2:_(s64) = G_MERGE_VALUES %0, %1
     %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
     %5:_(s32) = G_ADD %3, %4
+    %w0 = COPY %5
 ...
 
 ---
@@ -54,14 +59,16 @@ body: |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: test_combines_4
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY1]]
     %0:_(s64) = COPY %x0
 
-    ; CHECK-LABEL: name: test_combines_4
-    ; CHECK: %2(s64) = COPY %0(s64)
-    ; CHECK: %3(s64) = G_ADD %2, %2
     %1:_(s128) = G_MERGE_VALUES %0, %0
     %2:_(s64) = G_EXTRACT %1, 0
     %3:_(s64) = G_ADD %2, %2
+    %w0 = COPY %3
 ...
 
 ---
@@ -70,35 +77,15 @@ body: |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: test_combines_5
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
     %0:_(s32) = COPY %w0
 
-    ; CHECK-LABEL: name: test_combines_5
-    ; CHECK-NOT: G_MERGE_VALUES
-    ; CHECK-NOT: G_EXTRACT
-    ; CHECK: %5(s32) = G_ADD %0, %1
     %1:_(s32) = G_ADD %0, %0
     %2:_(s64) = G_MERGE_VALUES %0, %1
     %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
     %5:_(s32) = G_ADD %3, %4
-...
-
----
-name:            test_combines_6
-body: |
-  bb.0:
-    liveins: %w0
-
-    ; CHECK-LABEL: name: test_combines_6
-    ; CHECK: %0(s32) = COPY %w0
-    %0:_(s32) = COPY %w0
-
-    ; Check that we replace all the uses of a G_EXTRACT.
-    ; CHECK-NOT: G_MERGE_VALUES
-    ; CHECK-NOT: G_EXTRACT
-    ; CHECK: %3(s32) = G_MUL %0, %0
-    ; CHECK: %4(s32) = G_ADD %0, %3
-    %1:_(s32) = G_MERGE_VALUES %0
-    %2:_(s32) = G_UNMERGE_VALUES %1
-    %3:_(s32) = G_MUL %2, %2
-    %4:_(s32) = G_ADD %2, %3
+    %w0 = COPY %5
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
index 16d9e59698fe..4ed84ed79bba 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -26,23 +27,38 @@ registers:
   - { id: 5, class: _ }
 body: |
   bb.0.entry:
-    ; CHECK-LABEL: name: test_constant
-    ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; CHECK: %0(s1) = G_TRUNC [[TMP]]
-    ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 42
-    ; CHECK: %1(s8) = G_TRUNC [[TMP]]
-    ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 -1
-    ; CHECK: %2(s16) = G_TRUNC [[TMP]]
-    ; CHECK: %3(s32) = G_CONSTANT i32 -1
-    ; CHECK: %4(s64) = G_CONSTANT i64 1
-    ; CHECK: %5(s64) = G_CONSTANT i64 0
 
+    ; CHECK-LABEL: name: test_constant
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: %w0 = COPY [[COPY]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: %w0 = COPY [[COPY1]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: %w0 = COPY [[COPY2]](s32)
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: %w0 = COPY [[C3]](s32)
+    ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK: %x0 = COPY [[C4]](s64)
+    ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK: %x0 = COPY [[C5]](s64)
     %0(s1) = G_CONSTANT i1 0
+    %6:_(s32) = G_ANYEXT %0
+    %w0 = COPY %6
     %1(s8) = G_CONSTANT i8 42
+    %7:_(s32) = G_ANYEXT %1
+    %w0 = COPY %7
     %2(s16) = G_CONSTANT i16 65535
+    %8:_(s32) = G_ANYEXT %2
+    %w0 = COPY %8
     %3(s32) = G_CONSTANT i32 -1
+    %w0 = COPY %3
     %4(s64) = G_CONSTANT i64 1
+    %x0 = COPY %4
     %5(s64) = G_CONSTANT i64 0
+    %x0 = COPY %5
 ...
 
 ---
@@ -53,15 +69,23 @@ registers:
   - { id: 2, class: _ }
 body: |
   bb.0.entry:
-    ; CHECK-LABEL: name: test_fconstant
-    ; CHECK: %0(s32) = G_FCONSTANT  float 1.000000e+00
-    ; CHECK: %1(s64) = G_FCONSTANT  double 2.000000e+00
-    ; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000
-    ; CHECK: %2(s16) = G_FPTRUNC [[TMP]]
 
+    ; CHECK-LABEL: name: test_fconstant
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK: %w0 = COPY [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+    ; CHECK: %x0 = COPY [[C1]](s64)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT half 0xH0000
+    ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C2]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
+    ; CHECK: %w0 = COPY [[ANYEXT]](s32)
     %0(s32) = G_FCONSTANT float 1.0
+    %w0 = COPY %0
     %1(s64) = G_FCONSTANT double 2.0
+    %x0 = COPY %1
     %2(s16) = G_FCONSTANT half 0.0
+    %3:_(s32) = G_ANYEXT %2
+    %w0 = COPY %3
 ...
 
 ---
@@ -70,8 +94,12 @@ registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
-    ; CHECK-LABEL: name: test_global
-    ; CHECK: %0(p0) = G_GLOBAL_VALUE @var
 
+    ; CHECK-LABEL: name: test_global
+    ; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[GV]](p0)
+    ; CHECK: %x0 = COPY [[PTRTOINT]](s64)
     %0(p0) = G_GLOBAL_VALUE @var
+    %1:_(s64) = G_PTRTOINT %0
+    %x0 = COPY %1
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-div.mir b/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
index c6e0aabfd2c0..38be3a950e15 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -21,22 +22,42 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
+    ; CHECK-LABEL: name: test_div
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]]
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+    ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
+    ; CHECK: %w0 = COPY [[COPY2]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
+    ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
+    ; CHECK: %w0 = COPY [[COPY3]](s32)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
 
 
-    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %2
-    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %3
-    ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]]
-    ; CHECK: [[RES:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
     %4(s8) = G_SDIV %2, %3
+    %6:_(s32) = G_ANYEXT %4
+    %w0 = COPY %6
+
 
-    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2
-    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3
-    ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_UDIV [[LHS32]], [[RHS32]]
-    ; CHECK: [[RES:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
     %5(s8) = G_UDIV %2, %3
+    %7:_(s32) = G_ANYEXT %5
+    %w0 = COPY %7
 
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
index 42ca367e122b..01f955bc1d10 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
@@ -10,23 +10,23 @@ declare void @_Unwind_Resume(i8*)
 ; CHECK: name: bar
 ; CHECK: body:
 ; CHECK-NEXT:   bb.1 (%ir-block.0):
-; CHECK:     successors: %{{bb.[0-9]+.continue.*}}%[[LP:bb.[0-9]+.cleanup]]
+; CHECK:     successors: %{{bb.[0-9]+.*}}%[[LP:bb.[0-9]+]]
 
-; CHECK:   [[LP]] (landing-pad):
+; CHECK:   [[LP]].{{[a-z]+}} (landing-pad):
 ; CHECK:     EH_LABEL
 
-; CHECK:     [[PTR:%[0-9]+]](p0) = COPY %x0
-; CHECK:     [[STRUCT_PTR:%[0-9]+]](s64) = G_PTRTOINT [[PTR]](p0)
+; CHECK:     [[PTR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK:     [[STRUCT_PTR:%[0-9]+]]:_(s64) = G_PTRTOINT [[PTR]](p0)
 
-; CHECK:     [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
-; CHECK:     [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
-; CHECK:     [[STRUCT_SEL:%[0-9]+]](s64) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 0
+; CHECK:     [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK:     [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
+; CHECK:     [[STRUCT_SEL:%[0-9]+]]:_(s64) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 0
 
-; CHECK:     [[PTR:%[0-9]+]](p0) = G_INTTOPTR [[STRUCT_PTR]](s64)
+; CHECK:     [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[STRUCT_PTR]](s64)
 ; CHECK:     G_STORE [[PTR]](p0), {{%[0-9]+}}(p0)
 
-; CHECK:     [[SEL_TMP:%[0-9]+]](s32) = G_EXTRACT [[STRUCT_SEL]](s64), 0
-; CHECK:     [[SEL:%[0-9]+]](s32) = COPY [[SEL_TMP]]
+; CHECK:     [[SEL_TMP:%[0-9]+]]:_(s32) = G_EXTRACT [[STRUCT_SEL]](s64), 0
+; CHECK:     [[SEL:%[0-9]+]]:_(s32) = COPY [[SEL_TMP]]
 ; CHECK:     G_STORE [[SEL]](s32), {{%[0-9]+}}(p0)
 
 define void @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
index 70b55e4ebc66..1bd25bdae74e 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -34,46 +35,109 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
+    ; CHECK-LABEL: name: test_ext
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[TRUNC]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[TRUNC1]](s32)
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[TRUNC2]](s32)
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[TRUNC3]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: %x0 = COPY [[COPY1]](s64)
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
+    ; CHECK: %x0 = COPY [[AND]](s64)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: %x0 = COPY [[COPY3]](s64)
+    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY4]], [[C1]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]]
+    ; CHECK: %x0 = COPY [[ASHR]](s64)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[C2]]
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C2]]
+    ; CHECK: %w0 = COPY [[ASHR1]](s32)
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C3]]
+    ; CHECK: %w0 = COPY [[AND1]](s32)
+    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[TRUNC6]](s32)
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC7]], [[C4]]
+    ; CHECK: %w0 = COPY [[AND2]](s32)
+    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[TRUNC8]](s32)
+    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC9]], [[C5]]
+    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C5]]
+    ; CHECK: %w0 = COPY [[ASHR2]](s32)
+    ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[TRUNC3]]4(s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]]1, [[TRUNC3]]2
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[TRUNC3]]3(s32)
+    ; CHECK: %w0 = COPY [[COPY6]](s32)
+    ; CHECK: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[TRUNC11]](s32)
+    ; CHECK: [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[TRUNC12]](s32)
+    ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
+    ; CHECK: %x0 = COPY [[FPEXT]](s64)
     %0(s64) = COPY %x0
 
-    ; CHECK: %1(s1) = G_TRUNC %0
-    ; CHECK: %2(s8) = G_TRUNC %0
-    ; CHECK: %3(s16) = G_TRUNC %0
-    ; CHECK: %4(s32) = G_TRUNC %0
     %1(s1) = G_TRUNC %0
+    %19:_(s32) = G_ANYEXT %1
+    %w0 = COPY %19
     %2(s8) = G_TRUNC %0
+    %20:_(s32) = G_ANYEXT %2
+    %w0 = COPY %20
     %3(s16) = G_TRUNC %0
+    %21:_(s32) = G_ANYEXT %3
+    %w0 = COPY %21
     %4(s32) = G_TRUNC %0
+    %w0 = COPY %4
 
-    ; CHECK: %5(s64) = G_ANYEXT %1
-    ; CHECK: %6(s64) = G_ZEXT %2
-    ; CHECK: %7(s64) = G_ANYEXT %3
-    ; CHECK: %8(s64) = G_SEXT %4
     %5(s64) = G_ANYEXT %1
+    %x0 = COPY %5
     %6(s64) = G_ZEXT %2
+    %x0 = COPY %6
     %7(s64) = G_ANYEXT %3
+    %x0 = COPY %7
     %8(s64) = G_SEXT %4
+    %x0 = COPY %8
 
-    ; CHECK: %9(s32) = G_SEXT %1
-    ; CHECK: %10(s32) = G_ZEXT %2
-    ; CHECK: %11(s32) = G_ANYEXT %3
     %9(s32) = G_SEXT %1
+    %w0 = COPY %9
     %10(s32) = G_ZEXT %2
+    %w0 = COPY %10
     %11(s32) = G_ANYEXT %3
+    %w0 = COPY %11
 
-    ; CHECK: %12(s32) = G_ZEXT %1
-    ; CHECK: %13(s32) = G_ANYEXT %2
-    ; CHECK: %14(s32) = G_SEXT %3
     %12(s32) = G_ZEXT %1
+    %w0 = COPY %12
     %13(s32) = G_ANYEXT %2
+    %w0 = COPY %13
     %14(s32) = G_SEXT %3
+    %w0 = COPY %14
 
-    ; CHECK: %15(s8) = G_ZEXT %1
-    ; CHECK: %16(s16) = G_ANYEXT %2
     %15(s8) = G_ZEXT %1
+    %22:_(s32) = G_ANYEXT %15
+    %w0 = COPY %22
     %16(s16) = G_ANYEXT %2
+    %23:_(s32) = G_ANYEXT %16
+    %w0 = COPY %23
 
-    ; CHECK: %18(s64) = G_FPEXT %17
     %17(s32) = G_TRUNC  %0
+    %w0 = COPY %17
     %18(s64) = G_FPEXT %17
+    %x0 = COPY %18
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir b/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
index dc6b59b24a9a..94a403271797 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 ---
@@ -10,10 +11,14 @@ body: |
     ; value stored is forwarded directly from first load.
 
     ; CHECK-LABEL: name: test_extracts_1
-    ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: {{%[0-9]+}}(s64) = G_LOAD
-    ; CHECK: [[VAL:%[0-9]+]](s64) = COPY [[LO]]
-    ; CHECK: G_STORE [[VAL]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x2
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 16)
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 16)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
+    ; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store 8)
+    ; CHECK: RET_ReallyLR
     %0:_(s64) = COPY %x0
     %1:_(s32) = COPY %w1
     %2:_(p0) = COPY %x2
@@ -31,13 +36,17 @@ body: |
 
       ; Low extraction wipes takes whole low register. High extraction is real.
     ; CHECK-LABEL: name: test_extracts_2
-    ; CHECK: [[LO_TMP:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[LO:%[0-9]+]](s64) = COPY [[LO_TMP]]
-    ; CHECK: [[NEWHI_TMP:%[0-9]+]](s32) = G_EXTRACT [[HI]](s64), 0
-    ; CHECK: [[NEWHI:%[0-9]+]](s32) = COPY [[NEWHI_TMP]]
-    ; CHECK: G_STORE [[LO]]
-    ; CHECK: G_STORE [[NEWHI]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x2
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 16)
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 16)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD1]](s64), 0
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
+    ; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store 8)
+    ; CHECK: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 4)
+    ; CHECK: RET_ReallyLR
     %0:_(s64) = COPY %x0
     %1:_(s32) = COPY %w1
     %2:_(p0) = COPY %x2
@@ -57,13 +66,18 @@ body: |
 
 
     ; CHECK-LABEL: name: test_extracts_3
-    ; CHECK: [[LO:%[0-9]+]](s32) = G_EXTRACT %0(s64), 32
-    ; CHECK: [[HI:%[0-9]+]](s32) = G_EXTRACT %1(s64), 0
-    ; CHECK: %3(s64) = G_MERGE_VALUES [[LO]](s32), [[HI]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
+    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
+    ; CHECK: %x0 = COPY [[MV]](s64)
+    ; CHECK: RET_ReallyLR
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
     %2:_(s128) = G_MERGE_VALUES %0, %1
     %3:_(s64) = G_EXTRACT %2, 32
+    %x0 = COPY %3
     RET_ReallyLR
 ...
 
@@ -75,11 +89,15 @@ body: |
 
 
     ; CHECK-LABEL: name: test_extracts_4
-    ; CHECK: [[LO_TMP:%[0-9]+]](s32) = G_EXTRACT %0(s64), 32
-    ; CHECK: %3(s32) = COPY [[LO_TMP]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
+    ; CHECK: %w0 = COPY [[COPY1]](s32)
+    ; CHECK: RET_ReallyLR
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
     %2:_(s128) = G_MERGE_VALUES %0, %1
     %3:_(s32) = G_EXTRACT %2, 32
+    %w0 = COPY %3
     RET_ReallyLR
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
index 8cdc7b78b1e9..1c0c183e2db4 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -18,18 +19,29 @@ registers:
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
+  - { id: 6, class: _ }
+  - { id: 7, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
+    ; CHECK-LABEL: name: test_icmp
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), [[COPY]](s64), [[COPY1]]
+    ; CHECK: %w0 = COPY [[FCMP]](s32)
+    ; CHECK: [[FCMP1:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[TRUNC]](s32), [[TRUNC1]]
+    ; CHECK: %w0 = COPY [[FCMP1]](s32)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x0
 
     %2(s32) = G_TRUNC %0
     %3(s32) = G_TRUNC %1
 
-    ; CHECK: %4(s1) = G_FCMP floatpred(oge), %0(s64), %1
-    %4(s1) = G_FCMP floatpred(oge), %0, %1
+    %4(s32) = G_FCMP floatpred(oge), %0, %1
+    %w0 = COPY %4
 
-    ; CHECK: %5(s1) = G_FCMP floatpred(uno), %2(s32), %3
-    %5(s1) = G_FCMP floatpred(uno), %2, %3
+    %5(s32) = G_FCMP floatpred(uno), %2, %3
+    %w0 = COPY %5
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
index 8b5cbdfa55e3..e7dc314f034f 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -21,10 +22,10 @@ body:             |
   bb.1:
     liveins: %s0
     ; CHECK-LABEL: name: test_fneg_f32
-    ; CHECK: [[VAR:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float -0.000000e+00
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_FSUB [[ZERO]], [[VAR]]
-    ; CHECK: %s0 = COPY [[RES]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %s0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -0.000000e+00
+    ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[C]], [[COPY]]
+    ; CHECK: %s0 = COPY [[FSUB]](s32)
     %0(s32) = COPY %s0
     %1(s32) = G_FNEG %0
     %s0 = COPY %1(s32)
@@ -38,10 +39,10 @@ body:             |
   bb.1:
     liveins: %d0
     ; CHECK-LABEL: name: test_fneg_f64
-    ; CHECK: [[VAR:%[0-9]+]](s64) = COPY %d0
-    ; CHECK: [[ZERO:%[0-9]+]](s64) = G_FCONSTANT double -0.000000e+00
-    ; CHECK: [[RES:%[0-9]+]](s64) = G_FSUB [[ZERO]], [[VAR]]
-    ; CHECK: %d0 = COPY [[RES]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %d0
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -0.000000e+00
+    ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[C]], [[COPY]]
+    ; CHECK: %d0 = COPY [[FSUB]](s64)
     %0(s64) = COPY %d0
     %1(s64) = G_FNEG %0
     %d0 = COPY %1(s64)
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
index f79d0382ea7c..c03c190486f5 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -29,11 +30,13 @@ name:            test_fptosi_s32_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_fptosi_s32_s32
-    ; CHECK: %1(s32) = G_FPTOSI %0
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[DEF]](s32)
+    ; CHECK: %w0 = COPY [[FPTOSI]](s32)
+    %0:_(s32) = G_IMPLICIT_DEF
     %1:_(s32) = G_FPTOSI %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -41,11 +44,13 @@ name:            test_fptoui_s32_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_fptoui_s32_s32
-    ; CHECK: %1(s32) = G_FPTOUI %0
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[DEF]](s32)
+    ; CHECK: %w0 = COPY [[FPTOUI]](s32)
+    %0:_(s32) = G_IMPLICIT_DEF
     %1:_(s32) = G_FPTOUI %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -53,11 +58,13 @@ name:            test_fptosi_s32_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_fptosi_s32_s64
-    ; CHECK: %1(s32) = G_FPTOSI %0
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[DEF]](s32)
+    ; CHECK: %w0 = COPY [[FPTOSI]](s32)
+    %0:_(s32) = G_IMPLICIT_DEF
     %1:_(s32) = G_FPTOSI %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -65,11 +72,13 @@ name:            test_fptoui_s32_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_fptoui_s32_s64
-    ; CHECK: %1(s32) = G_FPTOUI %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+    ; CHECK: %w0 = COPY [[FPTOUI]](s32)
+    %0:_(s64) = COPY %x0
     %1:_(s32) = G_FPTOUI %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -77,11 +86,13 @@ name:            test_fptosi_s64_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_fptosi_s64_s32
-    ; CHECK: %1(s64) = G_FPTOSI %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s32)
+    ; CHECK: %x0 = COPY [[FPTOSI]](s64)
+    %0:_(s32) = COPY %w0
     %1:_(s64) = G_FPTOSI %0
+    %x0 = COPY %1
 ...
 
 ---
@@ -89,11 +100,13 @@ name:            test_fptoui_s64_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_fptoui_s64_s32
-    ; CHECK: %1(s64) = G_FPTOUI %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s32)
+    ; CHECK: %x0 = COPY [[FPTOUI]](s64)
+    %0:_(s32) = COPY %w0
     %1:_(s64) = G_FPTOUI %0
+    %x0 = COPY %1
 ...
 
 ---
@@ -101,11 +114,13 @@ name:            test_fptosi_s64_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_fptosi_s64_s64
-    ; CHECK: %1(s64) = G_FPTOSI %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s64)
+    ; CHECK: %x0 = COPY [[FPTOSI]](s64)
+    %0:_(s64) = COPY %x0
     %1:_(s64) = G_FPTOSI %0
+    %x0 = COPY %1
 ...
 
 ---
@@ -113,11 +128,13 @@ name:            test_fptoui_s64_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_fptoui_s64_s64
-    ; CHECK: %1(s64) = G_FPTOUI %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s64)
+    ; CHECK: %x0 = COPY [[FPTOUI]](s64)
+    %0:_(s64) = COPY %x0
     %1:_(s64) = G_FPTOUI %0
+    %x0 = COPY %1
 ...
 
 
@@ -127,12 +144,14 @@ name:            test_fptosi_s1_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_fptosi_s1_s32
-    ; CHECK: %2(s32) = G_FPTOSI %0
-    ; CHECK: %1(s1) = G_TRUNC %2
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
+    ; CHECK: %x0 = COPY [[TRUNC]](s1)
+    %0:_(s32) = COPY %w0
     %1:_(s1) = G_FPTOSI %0
+    %x0 = COPY %1
 ...
 
 ---
@@ -140,12 +159,15 @@ name:            test_fptoui_s1_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_fptoui_s1_s32
-    ; CHECK: %2(s32) = G_FPTOUI %0
-    ; CHECK: %1(s1) = G_TRUNC %2
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
+    ; CHECK: %w0 = COPY [[COPY1]](s32)
+    %0:_(s32) = COPY %w0
     %1:_(s1) = G_FPTOUI %0
+    %2:_(s32) = G_ANYEXT %1
+    %w0 = COPY %2
 ...
 
 ---
@@ -153,12 +175,15 @@ name:            test_fptosi_s8_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_fptosi_s8_s64
-    ; CHECK: %2(s32) = G_FPTOSI %0
-    ; CHECK: %1(s8) = G_TRUNC %2
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
+    ; CHECK: %w0 = COPY [[COPY1]](s32)
+    %0:_(s64) = COPY %x0
     %1:_(s8) = G_FPTOSI %0
+    %2:_(s32) = G_ANYEXT %1
+    %w0 = COPY %2
 ...
 
 ---
@@ -166,12 +191,15 @@ name:            test_fptoui_s8_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_fptoui_s8_s64
-    ; CHECK: %2(s32) = G_FPTOUI %0
-    ; CHECK: %1(s8) = G_TRUNC %2
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
+    ; CHECK: %w0 = COPY [[COPY1]](s32)
+    %0:_(s64) = COPY %x0
     %1:_(s8) = G_FPTOUI %0
+    %2:_(s32) = G_ANYEXT %1
+    %w0 = COPY %2
 ...
 
 ---
@@ -179,12 +207,15 @@ name:            test_fptosi_s16_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_fptosi_s16_s32
-    ; CHECK: %2(s32) = G_FPTOSI %0
-    ; CHECK: %1(s16) = G_TRUNC %2
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
+    ; CHECK: %w0 = COPY [[COPY1]](s32)
+    %0:_(s32) = COPY %w0
     %1:_(s16) = G_FPTOSI %0
+    %2:_(s32) = G_ANYEXT %1
+    %w0 = COPY %2
 ...
 
 ---
@@ -192,10 +223,13 @@ name:            test_fptoui_s16_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_fptoui_s16_s32
-    ; CHECK: %2(s32) = G_FPTOUI %0
-    ; CHECK: %1(s16) = G_TRUNC %2
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
+    ; CHECK: %w0 = COPY [[COPY1]](s32)
+    %0:_(s32) = COPY %w0
     %1:_(s16) = G_FPTOUI %0
+    %2:_(s32) = G_ANYEXT %1
+    %w0 = COPY %2
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir b/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
index d6ec983c2067..67310d10336e 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -19,10 +20,16 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    ; CHECK-LABEL: name: test_gep_small
-    ; CHECK: [[OFFSET_EXT:%[0-9]+]](s64) = G_SEXT %2(s8)
-    ; CHECK: %3(p0) = G_GEP %0, [[OFFSET_EXT]](s64)
 
+    ; CHECK-LABEL: name: test_gep_small
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[ASHR]](s64)
+    ; CHECK: %x0 = COPY [[GEP]](p0)
     %0(p0) = COPY %x0
     %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %1
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir b/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
index 43aa06ba3d90..b0de3fc8092a 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -14,10 +15,10 @@ registers:
 body: |
   bb.0:
     liveins: %x0
-    ; CHECK-LABEL: name: test_copy
-    ; CHECK: %0(s64) = COPY %x0
-    ; CHECK-NEXT: %x0 = COPY %0
 
+    ; CHECK-LABEL: name: test_copy
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: %x0 = COPY [[COPY]](s64)
     %0(s64) = COPY %x0
     %x0 = COPY %0
 ...
@@ -26,8 +27,8 @@ body: |
 name:            test_targetspecific
 body: |
   bb.0:
+
     ; CHECK-LABEL: name: test_targetspecific
     ; CHECK: RET_ReallyLR
-
     RET_ReallyLR
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index 917f181099ec..d430eb91ea52 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -9,6 +9,7 @@
   define void @test_inserts_4() { ret void }
   define void @test_inserts_5() { ret void }
   define void @test_inserts_6() { ret void }
+  define void @test_inserts_nonpow2() { ret void }
 ...
 
 ---
@@ -21,8 +22,8 @@ body: |
       ; forwarded to the G_STORE. Hi part is unchanged so (split) G_LOAD gets
       ; forwarded.
     ; CHECK-LABEL: name: test_inserts_1
-    ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
+    ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD
     ; CHECK: G_STORE %0(s64)
     ; CHECK: G_STORE [[HI]]
     %0:_(s64) = COPY %x0
@@ -43,9 +44,9 @@ body: |
       ; Low insertion wipes out the old register entirely, so %0 gets forwarded
       ; to the G_STORE again. Second insertion is real.
     ; CHECK-LABEL: name: test_inserts_2
-    ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[NEWHI:%[0-9]+]](s64) = G_INSERT [[HI]], %1(s32), 0
+    ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[NEWHI:%[0-9]+]]:_(s64) = G_INSERT [[HI]], %1(s32), 0
     ; CHECK: G_STORE %0(s64)
     ; CHECK: G_STORE [[NEWHI]]
     %0:_(s64) = COPY %x0
@@ -68,9 +69,9 @@ body: |
       ; certainly better than the alternative of directly forwarding the value
       ; which would cause a nasty type mismatch.
     ; CHECK-LABEL: name: test_inserts_3
-    ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[NEWLO:%[0-9]+]](s64) = G_PTRTOINT %0(p0)
+    ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[NEWLO:%[0-9]+]]:_(s64) = G_PTRTOINT %0(p0)
     ; CHECK: G_STORE [[NEWLO]](s64)
     ; CHECK: G_STORE [[HI]]
     %0:_(p0) = COPY %x0
@@ -90,11 +91,13 @@ body: |
 
       ; A narrow insert gets surrounded by a G_ANYEXT/G_TRUNC pair.
     ; CHECK-LABEL: name: test_inserts_4
-    ; CHECK: [[VALEXT:%[0-9]+]](s32) = G_ANYEXT %1(s8)
-    ; CHECK: [[VAL:%[0-9]+]](s32) = G_INSERT [[VALEXT]], %0(s1), 0
-    ; CHECK: %3(s8) = G_TRUNC [[VAL]](s32)
-    %0:_(s1) = COPY %w0
-    %1:_(s8) = COPY %w1
+    ; CHECK: [[VALEXT:%[0-9]+]]:_(s32) = COPY %2(s32)
+    ; CHECK: [[VAL:%[0-9]+]]:_(s32) = G_INSERT [[VALEXT]], %1(s1), 0
+    ; CHECK: %5:_(s8) = G_TRUNC [[VAL]](s32)
+    %4:_(s32) = COPY %w0
+    %0:_(s1) = G_TRUNC %4
+    %5:_(s32) = COPY %w1
+    %1:_(s8) = G_TRUNC %5
     %2:_(p0) = COPY %x2
     %3:_(s8) = G_INSERT %1(s8), %0(s1), 0
     G_STORE %3(s8), %2(p0) :: (store 1)
@@ -109,16 +112,18 @@ body: |
 
 
     ; CHECK-LABEL: name: test_inserts_5
-    ; CHECK: [[INS_LO:%[0-9]+]](s32) = G_EXTRACT %2(s64), 0
-    ; CHECK: [[VAL_LO:%[0-9]+]](s64) = G_INSERT %0, [[INS_LO]](s32), 32
-    ; CHECK: [[INS_HI:%[0-9]+]](s32) = G_EXTRACT %2(s64), 32
-    ; CHECK: [[VAL_HI:%[0-9]+]](s64) = G_INSERT %1, [[INS_HI]](s32), 0
-    ; CHECK: %4(s128) = G_MERGE_VALUES [[VAL_LO]](s64), [[VAL_HI]](s64)
+    ; CHECK: [[INS_LO:%[0-9]+]]:_(s32) = G_EXTRACT %2(s64), 0
+    ; CHECK: [[VAL_LO:%[0-9]+]]:_(s64) = G_INSERT %0, [[INS_LO]](s32), 32
+    ; CHECK: [[INS_HI:%[0-9]+]]:_(s32) = G_EXTRACT %2(s64), 32
+    ; CHECK: [[VAL_HI:%[0-9]+]]:_(s64) = G_INSERT %1, [[INS_HI]](s32), 0
+    ; CHECK: %4:_(s128) = G_MERGE_VALUES [[VAL_LO]](s64), [[VAL_HI]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
     %2:_(s64) = COPY %x2
     %3:_(s128) = G_MERGE_VALUES %0, %1
     %4:_(s128) = G_INSERT %3, %2, 32
+    %5:_(s64) = G_TRUNC %4
+    %x0 = COPY %5
     RET_ReallyLR
 ...
 
@@ -130,12 +135,35 @@ body: |
 
 
     ; CHECK-LABEL: name: test_inserts_6
-    ; CHECK: [[VAL_LO:%[0-9]+]](s64) = G_INSERT %0, %2(s32), 32
-    ; CHECK: %4(s128) = G_MERGE_VALUES [[VAL_LO]](s64), %1(s64)
+    ; CHECK: [[VAL_LO:%[0-9]+]]:_(s64) = G_INSERT %0, %2(s32), 32
+    ; CHECK: %4:_(s128) = G_MERGE_VALUES [[VAL_LO]](s64), %1(s64)
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
     %2:_(s32) = COPY %w2
     %3:_(s128) = G_MERGE_VALUES %0, %1
     %4:_(s128) = G_INSERT %3, %2, 32
+    %5:_(s64) = G_TRUNC %4
+    %x0 = COPY %5
+    RET_ReallyLR
+...
+
+---
+name:            test_inserts_nonpow2
+body: |
+  bb.0:
+    liveins: %x0, %x1, %x2
+
+
+    ; CHECK-LABEL: name: test_inserts_nonpow2
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = COPY %x3
+    ; CHECK: %x0 = COPY [[C]]
+    %0:_(s64) = COPY %x0
+    %1:_(s64) = COPY %x1
+    %2:_(s64) = COPY %x2
+    %3:_(s64) = COPY %x3
+    %4:_(s192) = G_MERGE_VALUES %0, %1, %2
+    %5:_(s192) = G_INSERT %4, %3, 0
+    %6:_(s64), %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %5
+    %x0 = COPY %6
     RET_ReallyLR
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
index 69e72bcb1f38..af9fb5d70d61 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -29,11 +30,12 @@ name:            test_sitofp_s32_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_sitofp_s32_s32
-    ; CHECK: %1(s32) = G_SITOFP %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
+    %0:_(s32) = COPY %w0
     %1:_(s32) = G_SITOFP %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -41,11 +43,12 @@ name:            test_uitofp_s32_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_uitofp_s32_s32
-    ; CHECK: %1(s32) = G_UITOFP %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s32)
+    %0:_(s32) = COPY %w0
     %1:_(s32) = G_UITOFP %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -53,11 +56,12 @@ name:            test_sitofp_s32_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_sitofp_s32_s64
-    ; CHECK: %1(s32) = G_SITOFP %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64)
+    %0:_(s64) = COPY %x0
     %1:_(s32) = G_SITOFP %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -65,11 +69,12 @@ name:            test_uitofp_s32_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_uitofp_s32_s64
-    ; CHECK: %1(s32) = G_UITOFP %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s64)
+    %0:_(s64) = COPY %x0
     %1:_(s32) = G_UITOFP %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -77,11 +82,12 @@ name:            test_sitofp_s64_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_sitofp_s64_s32
-    ; CHECK: %1(s64) = G_SITOFP %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
+    %0:_(s32) = COPY %w0
     %1:_(s64) = G_SITOFP %0
+    %w0 = COPY %1
 ...
 
 ---
@@ -89,11 +95,12 @@ name:            test_uitofp_s64_s32
 body: |
   bb.0:
     liveins: %w0
-    %0:_(s32) = COPY %w0
-
     ; CHECK-LABEL: name: test_uitofp_s64_s32
-    ; CHECK: %1(s64) = G_UITOFP %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s32)
+    %0:_(s32) = COPY %w0
     %1:_(s64) = G_UITOFP %0
+    %x0 = COPY %1
 ...
 
 ---
@@ -101,11 +108,12 @@ name:            test_sitofp_s64_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_sitofp_s64_s64
-    ; CHECK: %1(s64) = G_SITOFP %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s64)
+    %0:_(s64) = COPY %x0
     %1:_(s64) = G_SITOFP %0
+    %x0 = COPY %1
 ...
 
 ---
@@ -113,11 +121,12 @@ name:            test_uitofp_s64_s64
 body: |
   bb.0:
     liveins: %x0
-    %0:_(s64) = COPY %x0
-
     ; CHECK-LABEL: name: test_uitofp_s64_s64
-    ; CHECK: %1(s64) = G_UITOFP %0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s64)
+    %0:_(s64) = COPY %x0
     %1:_(s64) = G_UITOFP %0
+    %x0 = COPY %1
 ...
 
 
@@ -126,13 +135,17 @@ name:            test_sitofp_s32_s1
 body: |
   bb.0:
     liveins: %w0
+    ; CHECK-LABEL: name: test_sitofp_s32_s1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s1) = G_TRUNC %0
-
-    ; CHECK-LABEL: name: test_sitofp_s32_s1
-    ; CHECK: %3(s32) = G_SEXT %1
-    ; CHECK: %2(s32) = G_SITOFP %3
     %2:_(s32) = G_SITOFP %1
+    %w0 = COPY %2
 ...
 
 ---
@@ -140,13 +153,16 @@ name:            test_uitofp_s32_s1
 body: |
   bb.0:
     liveins: %w0
+    ; CHECK-LABEL: name: test_uitofp_s32_s1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s1) = G_TRUNC %0
-
-    ; CHECK-LABEL: name: test_uitofp_s32_s1
-    ; CHECK: %3(s32) = G_ZEXT %1
-    ; CHECK: %2(s32) = G_UITOFP %3
     %2:_(s32) = G_UITOFP %1
+    %w0 = COPY %2
 ...
 
 ---
@@ -154,13 +170,17 @@ name:            test_sitofp_s64_s8
 body: |
   bb.0:
     liveins: %w0
+    ; CHECK-LABEL: name: test_sitofp_s64_s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s8) = G_TRUNC %0
-
-    ; CHECK-LABEL: name: test_sitofp_s64_s8
-    ; CHECK: %3(s32) = G_SEXT %1
-    ; CHECK: %2(s64) = G_SITOFP %3
     %2:_(s64) = G_SITOFP %1
+    %x0 = COPY %2
 ...
 
 ---
@@ -168,13 +188,16 @@ name:            test_uitofp_s64_s8
 body: |
   bb.0:
     liveins: %w0
+    ; CHECK-LABEL: name: test_uitofp_s64_s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s8) = G_TRUNC %0
-
-    ; CHECK-LABEL: name: test_uitofp_s64_s8
-    ; CHECK: %3(s32) = G_ZEXT %1
-    ; CHECK: %2(s64) = G_UITOFP %3
     %2:_(s64) = G_UITOFP %1
+    %x0 = COPY %2
 ...
 
 ---
@@ -182,13 +205,17 @@ name:            test_sitofp_s32_s16
 body: |
   bb.0:
     liveins: %w0
+    ; CHECK-LABEL: name: test_sitofp_s32_s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s16) = G_TRUNC %0
-
-    ; CHECK-LABEL: name: test_sitofp_s32_s16
-    ; CHECK: %3(s32) = G_SEXT %1
-    ; CHECK: %2(s32) = G_SITOFP %3
     %2:_(s32) = G_SITOFP %1
+    %w0 = COPY %2
 ...
 
 ---
@@ -196,11 +223,14 @@ name:            test_uitofp_s32_s16
 body: |
   bb.0:
     liveins: %w0
+    ; CHECK-LABEL: name: test_uitofp_s32_s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s16) = G_TRUNC %0
-
-    ; CHECK-LABEL: name: test_uitofp_s32_s16
-    ; CHECK: %3(s32) = G_ZEXT %1
-    ; CHECK: %2(s32) = G_UITOFP %3
     %2:_(s32) = G_UITOFP %1
+    %w0 = COPY %2
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index ce913d211ae2..6e775da9e802 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -31,34 +31,45 @@ body: |
     ; CHECK-LABEL: name: test_load
     %0(p0) = COPY %x0
 
-    ; CHECK: [[BIT8:%[0-9]+]](s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
-    ; CHECK: %1(s1) = G_TRUNC [[BIT8]]
     %1(s1) = G_LOAD %0 :: (load 1 from %ir.addr)
+    %9:_(s32) = G_ANYEXT %1
+    %w0 = COPY %9
 
-    ; CHECK: %2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
+    ; CHECK: %2:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
     %2(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+    %10:_(s32) = G_ANYEXT %2
+    %w0 = COPY %10
 
-    ; CHECK: %3(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr)
+    ; CHECK: %3:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr)
     %3(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+    %11:_(s32) = G_ANYEXT %3
+    %w0 = COPY %11
 
-    ; CHECK: %4(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr)
+    ; CHECK: %4:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr)
     %4(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
+    %w0 = COPY %4
 
-    ; CHECK: %5(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+    ; CHECK: %5:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
     %5(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
+    %x0 = COPY %5
 
-    ; CHECK: %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
     %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+    %12:_(s64) = G_PTRTOINT %6
+    %x0 = COPY %12
 
-    ; CHECK: %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+    ; CHECK: %7:_(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
     %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+    %13:_(s64) = G_BITCAST %7
+    %x0 = COPY %13
 
-    ; CHECK: [[LOAD0:%[0-9]+]](s64) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
-    ; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64)
-    ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr)
-    ; CHECK: %8(s128) = G_MERGE_VALUES [[LOAD0]](s64), [[LOAD1]](s64)
+    ; CHECK: [[LOAD0:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
+    ; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[OFFSET1]](s64)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr)
+    ; CHECK: %8:_(s128) = G_MERGE_VALUES [[LOAD0]](s64), [[LOAD1]](s64)
     %8(s128) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
+    %14:_(s64) = G_TRUNC %8
+    %x0 = COPY %14
 ...
 
 ---
@@ -80,7 +91,13 @@ body: |
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
 
-    ; CHECK: [[BIT8:%[0-9]+]](s8) = G_ZEXT %2(s1)
+    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[B:%.*]]:_(s32) = COPY %1(s32)
+    ; CHECK: [[COPY_C1:%.*]]:_(s32) = COPY [[C1]]
+    ; CHECK: [[AND:%.*]]:_(s32) = G_AND [[B]], [[COPY_C1]]
+    ; CHECK: [[BIT8:%.*]]:_(s8) = G_TRUNC [[AND]]
+
+
     ; CHECK: G_STORE [[BIT8]](s8), %0(p0) :: (store 1 into %ir.addr)
     %2(s1) = G_TRUNC %1
     G_STORE %2, %0 :: (store 1 into %ir.addr)
@@ -104,8 +121,8 @@ body: |
     G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
 
     ; CHECK: G_STORE %5(s64), %0(p0) :: (store 16 into %ir.addr)
-    ; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64)
+    ; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[OFFSET1]](s64)
     ; CHECK: G_STORE %6(s64), [[GEP1]](p0) :: (store 16 into %ir.addr)
     %6(s64) = G_PTRTOINT %0(p0)
     %7(s128) = G_MERGE_VALUES %5, %6
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir b/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
new file mode 100644
index 000000000000..e6171380344e
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
@@ -0,0 +1,30 @@
+# RUN: llc -O0 -run-pass=legalizer -global-isel -global-isel-abort=0 -pass-remarks-missed='gisel*' %s -o - 2>&1 | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  define void @test_merge_s4() {
+    ret void
+  }
+...
+
+---
+name:            test_merge_s4
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+body: |
+  bb.0:
+    %0(s64) = G_CONSTANT i64 0
+    %1(s4) = G_TRUNC %0(s64)
+    ; Previously, LegalizerInfo was assuming all G_MERGE_VALUES and G_UNMERGE_VALUES
+    ; instructions are legal. Make sure that is no longer happening.
+    ; CHECK: unable to legalize instruction: {{.*}} G_MERGE_VALUES
+    %2(s8) = G_MERGE_VALUES %1(s4), %1(s4)
+    %3(s8) = COPY %2(s8)
+    %4(s64) = G_ANYEXT %3(s8)
+    %x0 = COPY %4(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index 1ea6e9c292f5..c94d73920ca3 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -22,18 +23,21 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    ; CHECK-LABEL: name: test_scalar_mul_small
-    ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8)
-    ; CHECK: [[RES32:%.*]](s32) = G_MUL [[OP0]], [[OP1]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
 
+    ; CHECK-LABEL: name: test_scalar_mul_small
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
+    ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_MUL %2, %3
-    %5(s64) = G_ANYEXT %2
+    %5(s64) = G_ANYEXT %4
     %x0 = COPY %5
 ...
 
@@ -44,14 +48,21 @@ body: |
   bb.0:
     liveins: %x0, %x1, %w2, %w3
 
+    ; CHECK-LABEL: name: test_mul_overflow
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
+    ; CHECK: [[SMULH:%[0-9]+]]:_(s64) = G_SMULH [[COPY]], [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[C]]
+    ; CHECK: %x0 = COPY [[MUL]](s64)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; CHECK: %w0 = COPY [[COPY2]](s32)
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
-
-    ; CHECK-LABEL: name: test_mul_overflow
-    ; CHECK: %2(s64) = G_MUL %0, %1
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_SMULH %0, %1
-    ; CHECK: [[ZERO:%[0-9]+]](s64) = G_CONSTANT i64 0
-    ; CHECK: %3(s1) = G_ICMP intpred(ne), [[HI]](s64), [[ZERO]]
     %2:_(s64), %3:_(s1) = G_SMULO %0, %1
+    %x0 = COPY %2
+    %4:_(s32) = G_ANYEXT %3
+    %w0 = COPY %4
 
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir b/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
index 9928ea54d2c9..168e1df02775 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
@@ -1,29 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
-  define void @test_legalize_merge_v3s32() {
+  define void @test_legalize_merge_v3s64() {
     ret void
   }
 ...
 ---
-name:            test_legalize_merge_v3s32
+name:            test_legalize_merge_v3s64
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
 body: |
   bb.0:
-    liveins: %w0, %w1, %w2
-    ; CHECK-LABEL: name: test_legalize_merge_v3s32
-    ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %w1
-    ; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %w2
-    ; CHECK: (<3 x s32>) = G_MERGE_VALUES [[ARG1]](s32), [[ARG2]](s32), [[ARG3]](s32)
-    %0(s32) = COPY %w0
-    %1(s32) = COPY %w1
-    %2(s32) = COPY %w2
-    %3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32)
+    liveins: %w0
+    ; CHECK-LABEL: name: test_legalize_merge_v3s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[MV:%[0-9]+]]:_(<3 x s64>) = G_MERGE_VALUES [[COPY]](s64), [[COPY]](s64), [[COPY]](s64)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s64>) = COPY [[MV]](<3 x s64>)
+    ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<3 x s64>)
+    ; CHECK: %x0 = COPY [[UV]](s64)
+    %0(s64) = COPY %x0
+    %1(<3 x s64>) = G_MERGE_VALUES %0(s64), %0(s64), %0(s64)
+    %2(<3 x s64>) = COPY %1(<3 x s64>)
+    %3(s64), %4(s64), %5(s64) = G_UNMERGE_VALUES %2(<3 x s64>)
+    %x0 = COPY %3(s64)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index e8b850982460..9dbade2c193a 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -1,37 +1,55 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
-
---- |
-  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64--"
-  define void @test_scalar_or_small() {
-  entry:
-    ret void
-  }
-...
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 ---
 name:            test_scalar_or_small
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
-  - { id: 5, class: _ }
 body: |
-  bb.0.entry:
+  bb.0:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_scalar_or_small
-    ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8)
-    ; CHECK: [[RES32:%.*]](s32) = G_OR [[OP0]], [[OP1]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
+    ; CHECK: %x0 = COPY [[TRUNC2]](s8)
+    %0:_(s64) = COPY %x0
+    %1:_(s64) = COPY %x1
+    %2:_(s8) = G_TRUNC %0
+    %3:_(s8) = G_TRUNC %1
+    %4:_(s8) = G_OR %2, %3
+    %x0 = COPY %4
+...
+
+---
+name:            test_big_scalar_power_of_2
+body: |
+  bb.0:
+    liveins: %x0, %x1, %x2, %x3
+    ; We have a temporary G_MERGE_VALUES in the legalizer that gets
+    ; cleaned up with the G_UNMERGE_VALUES, so we end up directly
+    ; copying the results of the G_OR ops.
 
-    %0(s64) = COPY %x0
-    %1(s64) = COPY %x1
-    %2(s8) = G_TRUNC %0
-    %3(s8) = G_TRUNC %1
-    %4(s8) = G_OR %2, %3
-    %5(s64) = G_ANYEXT %2
-    %x0 = COPY %5
+    ; CHECK-LABEL: name: test_big_scalar_power_of_2
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
+    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY2]]
+    ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY1]], [[COPY3]]
+    ; CHECK: %x0 = COPY [[OR]](s64)
+    ; CHECK: %x1 = COPY [[OR1]](s64)
+    ; CHECK: RET_ReallyLR implicit %x0, implicit %x1
+    %0:_(s64) = COPY %x0
+    %1:_(s64) = COPY %x1
+    %2:_(s64) = COPY %x2
+    %3:_(s64) = COPY %x3
+    %4:_(s128) = G_MERGE_VALUES %0, %1
+    %5:_(s128) = G_MERGE_VALUES %2, %3
+    %6:_(s128) = G_OR %4, %5
+    %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
+    %x0 = COPY %7
+    %x1 = COPY %8
+    RET_ReallyLR implicit %x0, implicit %x1
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
new file mode 100644
index 000000000000..807c2320058a
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -0,0 +1,605 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+  ; ModuleID = '/tmp/test.ll'
+  source_filename = "/tmp/test.ll"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-unknown-unknown"
+
+  define i32 @legalize_phi(i32 %argc) {
+  entry:
+    ret i32 0
+  }
+
+  define i64* @legalize_phi_ptr(i64* %a, i64* %b, i1 %cond) {
+  entry:
+    ret i64* null
+  }
+
+  define i32 @legalize_phi_empty(i32 %argc) {
+  entry:
+    ret i32 0
+  }
+
+  define i32 @legalize_phi_loop(i32 %argc) {
+  entry:
+    ret i32 0
+  }
+
+  define i32 @legalize_phi_cycle(i32 %argc) {
+  entry:
+    ret i32 0
+  }
+  define i32 @legalize_phi_same_bb(i32 %argc) {
+  entry:
+    ret i32 0
+  }
+
+  define i32 @legalize_phi_diff_bb(i32 %argc, i32 %argc2) {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+name:            legalize_phi
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+  - { id: 6, class: _, preferred-register: '' }
+  - { id: 7, class: _, preferred-register: '' }
+  - { id: 8, class: _, preferred-register: '' }
+  - { id: 9, class: _, preferred-register: '' }
+  - { id: 10, class: _, preferred-register: '' }
+liveins:
+body:             |
+  ; CHECK-LABEL: name: legalize_phi
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: %w0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+  ; CHECK:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+  ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK:   G_BR %bb.3
+  ; CHECK: bb.2:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+  ; CHECK: bb.3:
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+  ; CHECK:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+  ; CHECK:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+  ; CHECK:   %w0 = COPY [[AND]](s32)
+  ; CHECK:   RET_ReallyLR implicit %w0
+  bb.0:
+   ; Test that we insert legalization artifacts(Truncs here) into the correct BBs
+   ; while legalizing the G_PHI to s16.
+
+
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: %w0
+
+    %0(s32) = COPY %w0
+    %1(s32) = G_CONSTANT i32 0
+    %3(s32) = G_CONSTANT i32 1
+    %6(s32) = G_CONSTANT i32 2
+    %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.2
+
+  bb.1:
+    successors: %bb.3(0x80000000)
+
+    %4(s32) = G_ADD %0, %3
+    %5(s1) = G_TRUNC %4(s32)
+    G_BR %bb.3
+
+  bb.2:
+    successors: %bb.3(0x80000000)
+
+    %7(s32) = G_ADD %0, %6
+    %8(s1) = G_TRUNC %7(s32)
+
+  bb.3:
+    %9(s1) = G_PHI %5(s1), %bb.1, %8(s1), %bb.2
+    %10(s32) = G_ZEXT %9(s1)
+    %w0 = COPY %10(s32)
+    RET_ReallyLR implicit %w0
+
+...
+---
+name:            legalize_phi_ptr
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+liveins:
+body:             |
+  ; CHECK-LABEL: name: legalize_phi_ptr
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: %w2, %x0, %x1
+  ; CHECK:   [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(p0) = COPY %x1
+  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY %w2
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
+  ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK: bb.2:
+  ; CHECK:   [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
+  ; CHECK:   %x0 = COPY [[PHI]](p0)
+  ; CHECK:   RET_ReallyLR implicit %x0
+  bb.1:
+
+    successors: %bb.2, %bb.3
+    liveins: %w2, %x0, %x1
+
+    %0(p0) = COPY %x0
+    %1(p0) = COPY %x1
+    %4(s32) = COPY %w2
+    %2(s1) = G_TRUNC %4(s32)
+    G_BRCOND %2(s1), %bb.2
+    G_BR %bb.3
+
+  bb.2:
+    successors: %bb.3
+
+  bb.3:
+    %3(p0) = G_PHI %0(p0), %bb.1, %1(p0), %bb.2
+    %x0 = COPY %3(p0)
+    RET_ReallyLR implicit %x0
+
+...
+---
+name:            legalize_phi_empty
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+  - { id: 6, class: _, preferred-register: '' }
+  - { id: 7, class: _, preferred-register: '' }
+  - { id: 8, class: _, preferred-register: '' }
+  - { id: 9, class: _, preferred-register: '' }
+  - { id: 10, class: _, preferred-register: '' }
+liveins:
+body:             |
+  ; CHECK-LABEL: name: legalize_phi_empty
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: %w0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+  ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+  ; CHECK:   G_BR %bb.3
+  ; CHECK: bb.2:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK: bb.3:
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+  ; CHECK:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+  ; CHECK:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+  ; CHECK:   %w0 = COPY [[AND]](s32)
+  ; CHECK:   RET_ReallyLR implicit %w0
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: %w0
+   ; Test that we properly legalize a phi with a predecessor that's empty
+
+
+
+
+    %0(s32) = COPY %w0
+    %1(s32) = G_CONSTANT i32 0
+    %3(s32) = G_CONSTANT i32 3
+    %6(s32) = G_CONSTANT i32 1
+    %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
+    %4(s32) = G_ADD %0, %3
+    %5(s1) = G_TRUNC %4(s32)
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.2
+
+  bb.1:
+    successors: %bb.3(0x80000000)
+
+    %7(s32) = G_ADD %0, %6
+    %8(s1) = G_TRUNC %7(s32)
+    G_BR %bb.3
+
+  bb.2:
+    successors: %bb.3(0x80000000)
+
+
+  bb.3:
+    %9(s1) = G_PHI %8(s1), %bb.1, %5(s1), %bb.2
+    %10(s32) = G_ZEXT %9(s1)
+    %w0 = COPY %10(s32)
+    RET_ReallyLR implicit %w0
+
+...
+---
+name:            legalize_phi_loop
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+  - { id: 6, class: _, preferred-register: '' }
+  - { id: 7, class: _, preferred-register: '' }
+liveins:
+body:             |
+  ; CHECK-LABEL: name: legalize_phi_loop
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: %w0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, %14(s16), %bb.1
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[COPY1]]
+  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
+  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+  ; CHECK:   [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+  ; CHECK:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
+  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+  ; CHECK:   [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK:   G_BRCOND [[TRUNC2]](s1), %bb.1
+  ; CHECK: bb.2:
+  ; CHECK:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+  ; CHECK:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+  ; CHECK:   %w0 = COPY [[AND1]](s32)
+  ; CHECK:   RET_ReallyLR implicit %w0
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: %w0
+   ; Test that we properly legalize a phi that uses a value from the same BB
+
+    %0(s32) = COPY %w0
+    %2(s8) = G_CONSTANT i8 1
+    %7(s8) = G_CONSTANT i8 0
+
+  bb.1:
+    successors: %bb.1(0x40000000), %bb.3(0x40000000)
+
+    %1(s8) = G_PHI %7(s8), %bb.0, %3(s8), %bb.1
+    %3(s8) = G_ADD %1, %2
+    %4(s32) = G_ZEXT %3(s8)
+    %5(s1) = G_ICMP intpred(ugt), %4(s32), %0
+    G_BRCOND %5(s1), %bb.1
+
+  bb.3:
+    %6(s32) = G_ZEXT %3(s8)
+    %w0 = COPY %6(s32)
+    RET_ReallyLR implicit %w0
+
+...
+---
+name:            legalize_phi_cycle
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+liveins:
+body:             |
+  ; CHECK-LABEL: name: legalize_phi_cycle
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: %w0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, %8(s16), %bb.1
+  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[PHI]](s16)
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+  ; CHECK:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+  ; CHECK:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
+  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
+  ; CHECK:   G_BRCOND [[TRUNC2]](s1), %bb.1
+  ; CHECK: bb.2:
+  ; CHECK:   %w0 = COPY [[AND]](s32)
+  ; CHECK:   RET_ReallyLR implicit %w0
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: %w0
+   ; Test that we properly legalize a phi that uses itself
+
+
+    %0(s32) = COPY %w0
+    %4(s8) = G_CONSTANT i8 0
+
+  bb.1:
+    successors: %bb.1(0x40000000), %bb.3(0x40000000)
+
+    %1(s8) = G_PHI %4(s8), %bb.0, %1(s8), %bb.1
+    %2(s32) = G_ZEXT %1(s8)
+    %3(s1) = G_ICMP intpred(ugt), %2(s32), %0
+    G_BRCOND %3(s1), %bb.1
+
+  bb.3:
+    %w0 = COPY %2(s32)
+    RET_ReallyLR implicit %w0
+
+...
+---
+name:            legalize_phi_same_bb
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+  - { id: 6, class: _, preferred-register: '' }
+  - { id: 7, class: _, preferred-register: '' }
+  - { id: 8, class: _, preferred-register: '' }
+  - { id: 9, class: _, preferred-register: '' }
+  - { id: 10, class: _, preferred-register: '' }
+  - { id: 11, class: _, preferred-register: '' }
+  - { id: 12, class: _, preferred-register: '' }
+  - { id: 13, class: _, preferred-register: '' }
+  - { id: 14, class: _, preferred-register: '' }
+liveins:
+body:             |
+  ; CHECK-LABEL: name: legalize_phi_same_bb
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: %w0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+  ; CHECK:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+  ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+  ; CHECK:   G_BR %bb.3
+  ; CHECK: bb.2:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C3]](s32)
+  ; CHECK:   [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK: bb.3:
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC4]](s16), %bb.2
+  ; CHECK:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC3]](s16), %bb.2
+  ; CHECK:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+  ; CHECK:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
+  ; CHECK:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+  ; CHECK:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
+  ; CHECK:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]]
+  ; CHECK:   [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[C]]1, [[C]]2
+  ; CHECK:   %w0 = COPY [[C]]3(s32)
+  ; CHECK:   RET_ReallyLR implicit %w0
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: %w0
+   ; Make sure that we correctly insert the new legalized G_PHI at the
+   ; correct location (ie make sure G_PHIs are the first insts in the BB).
+
+
+
+
+    %0(s32) = COPY %w0
+    %1(s32) = G_CONSTANT i32 0
+    %3(s32) = G_CONSTANT i32 3
+    %6(s32) = G_CONSTANT i32 1
+    %14(s8) = G_CONSTANT i8 42
+    %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
+    %4(s32) = G_ADD %0, %3
+    %5(s8) = G_TRUNC %4(s32)
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.2
+
+  bb.1:
+    successors: %bb.3(0x80000000)
+
+    %7(s32) = G_ADD %0, %6
+    %8(s8) = G_TRUNC %7(s32)
+    G_BR %bb.3
+
+  bb.2:
+    successors: %bb.3(0x80000000)
+
+
+  bb.3:
+    %9(s8) = G_PHI %8(s8), %bb.1, %5(s8), %bb.2
+    %10(s8) = G_PHI %8(s8), %bb.1, %14(s8), %bb.2
+    %11(s32) = G_ZEXT %9(s8)
+    %12(s32) = G_ZEXT %10(s8)
+    %13(s32) = G_ADD %11, %12
+    %w0 = COPY %13(s32)
+    RET_ReallyLR implicit %w0
+
+...
+---
+name:            legalize_phi_diff_bb
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+  - { id: 6, class: _, preferred-register: '' }
+  - { id: 7, class: _, preferred-register: '' }
+  - { id: 8, class: _, preferred-register: '' }
+  - { id: 9, class: _, preferred-register: '' }
+  - { id: 10, class: _, preferred-register: '' }
+  - { id: 11, class: _, preferred-register: '' }
+  - { id: 12, class: _, preferred-register: '' }
+  - { id: 13, class: _, preferred-register: '' }
+  - { id: 14, class: _, preferred-register: '' }
+  - { id: 15, class: _, preferred-register: '' }
+liveins:
+body:             |
+  ; CHECK-LABEL: name: legalize_phi_diff_bb
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: %w0, %w1
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
+  ; CHECK:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 43
+  ; CHECK:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+  ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.0, [[C]]2(s16), %bb.1
+  ; CHECK:   [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[PHI]](s16)
+  ; CHECK:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+  ; CHECK:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C5]]
+  ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
+  ; CHECK:   [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]]
+  ; CHECK:   [[TRUNC4:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
+  ; CHECK:   [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
+  ; CHECK:   G_BRCOND [[TRUNC4]](s1), %bb.2
+  ; CHECK:   G_BR %bb.1
+  ; CHECK: bb.2:
+  ; CHECK:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[COPY1]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
+  ; CHECK:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+  ; CHECK:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
+  ; CHECK:   [[AND1:%[0-9]+]]:_(s32) = G_AND [[C]]8, [[C]]7
+  ; CHECK:   %w0 = COPY [[AND1]](s32)
+  ; CHECK:   RET_ReallyLR implicit %w0
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.3(0x40000000)
+    liveins: %w0, %w1
+   ; Make sure that we correctly legalize PHIs sharing common defs
+   ; in different BBs.
+
+
+
+    %0(s32) = COPY %w0
+    %1(s32) = COPY %w1
+    %2(s32) = G_CONSTANT i32 0
+    %4(s32) = G_CONSTANT i32 3
+    %9(s32) = G_CONSTANT i32 1
+    %11(s32) = G_CONSTANT i32 44
+    %15(s8) = G_CONSTANT i8 43
+    %3(s1) = G_ICMP intpred(ugt), %0(s32), %2
+    %5(s32) = G_ADD %0, %4
+    %6(s8) = G_TRUNC %5(s32)
+    G_BRCOND %3(s1), %bb.1
+    G_BR %bb.3
+
+  bb.1:
+    successors: %bb.3(0x40000000), %bb.1(0x40000000)
+
+    %7(s8) = G_PHI %6(s8), %bb.0, %15(s8), %bb.1
+    %8(s32) = G_ZEXT %7(s8)
+    %10(s32) = G_ADD %8, %9
+    %12(s1) = G_ICMP intpred(ugt), %10(s32), %11
+    G_BRCOND %12(s1), %bb.3
+    G_BR %bb.1
+
+  bb.3:
+    %13(s8) = G_PHI %7(s8), %bb.1, %6(s8), %bb.0
+    %14(s32) = G_ZEXT %13(s8)
+    %w0 = COPY %14(s32)
+    RET_ReallyLR implicit %w0
+
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir b/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
index 2becc2e134b5..be3485919973 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
@@ -26,13 +26,15 @@ body: |
     ; CHECK: %d0 = COPY %0
     ; CHECK: %d1 = COPY %1
     ; CHECK: BL $pow, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
-    ; CHECK: %4(s64) = COPY %d0
+    ; CHECK: %4:_(s64) = COPY %d0
     %4:_(s64) = G_FPOW %0, %1
+    %x0 = COPY %4
 
     ; CHECK: %s0 = COPY %2
     ; CHECK: %s1 = COPY %3
     ; CHECK: BL $powf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
-    ; CHECK: %5(s32) = COPY %s0
+    ; CHECK: %5:_(s32) = COPY %s0
     %5:_(s32) = G_FPOW %2, %3
+    %w0 = COPY %5
 
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir b/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
index 50a4d93cbe20..7303a9c26fc9 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
@@ -1,73 +1,159 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
-  define void @test_rem() {
+  define void @test_urem_64() {
+  entry:
+    ret void
+  }
+  define void @test_srem_32() {
+  entry:
+    ret void
+  }
+  define void @test_srem_8() {
+  entry:
+    ret void
+  }
+  define void @test_frem() {
   entry:
     ret void
   }
 ...
 
 ---
-name:            test_rem
+name:            test_urem_64
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+
+    ; CHECK-LABEL: name: test_urem_64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
+    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
+    ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
+    ; CHECK: %x0 = COPY [[SUB]](s64)
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
+    %2(s64) = G_UREM %0, %1
+    %x0 = COPY %2
+
+
+...
+---
+name:            test_srem_32
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
-  - { id: 6, class: _ }
-  - { id: 7, class: _ }
-  - { id: 8, class: _ }
-  - { id: 9, class: _ }
-  - { id: 10, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
 
-    ; CHECK: [[QUOT:%[0-9]+]](s64) = G_UDIV %0, %1
-    ; CHECK: [[PROD:%[0-9]+]](s64) = G_MUL [[QUOT]], %1
-    ; CHECK: [[RES:%[0-9]+]](s64) = G_SUB %0, [[PROD]]
+    ; CHECK-LABEL: name: test_srem_32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
+    ; CHECK: %w0 = COPY [[SUB]](s32)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
-    %2(s64) = G_UREM %0, %1
-
-    ; CHECK: [[QUOT:%[0-9]+]](s32) = G_SDIV %3, %4
-    ; CHECK: [[PROD:%[0-9]+]](s32) = G_MUL [[QUOT]], %4
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_SUB %3, [[PROD]]
     %3(s32) = G_TRUNC %0
     %4(s32) = G_TRUNC %1
     %5(s32) = G_SREM %3, %4
+    %w0 = COPY %5
 
-    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %6
-    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %7
-    ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]]
-    ; CHECK: [[QUOT:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
+...
+---
+name:            test_srem_8
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 6, class: _ }
+  - { id: 7, class: _ }
+  - { id: 8, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
 
-    ; CHECK: [[QUOT32_2:%.*]](s32) = G_ANYEXT [[QUOT]](s8)
-    ; CHECK: [[RHS32_2:%.*]](s32) = G_ANYEXT %7(s8)
-    ; CHECK: [[PROD32:%.*]](s32) = G_MUL [[QUOT32_2]], [[RHS32_2]]
-    ; CHECK: [[PROD:%.*]](s8) = G_TRUNC [[PROD32]](s32)
 
-    ; CHECK: [[LHS32_2:%.*]](s32) = G_ANYEXT %6(s8)
-    ; CHECK: [[PROD32_2:%.*]](s32) = G_ANYEXT [[PROD]](s8)
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_SUB [[LHS32_2]], [[PROD32_2]]
+    ; CHECK-LABEL: name: test_srem_8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]]
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+    ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[TRUNC2]]
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[COPY3]]
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+    ; CHECK: %w0 = COPY [[COPY4]](s32)
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %6(s8) = G_TRUNC %0
     %7(s8) = G_TRUNC %1
     %8(s8) = G_SREM %6, %7
+    %9:_(s32) = G_ANYEXT %8
+    %w0 = COPY %9
+...
+---
+name:            test_frem
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+body: |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
 
-    ; CHECK: %d0 = COPY %0
-    ; CHECK: %d1 = COPY %1
+    ; CHECK-LABEL: name: test_frem
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
+    ; CHECK: %d0 = COPY [[COPY]](s64)
+    ; CHECK: %d1 = COPY [[COPY1]](s64)
     ; CHECK: BL $fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
-    ; CHECK: %9(s64) = COPY %d0
-    %9(s64) = G_FREM %0, %1
-
-    ; CHECK: %s0 = COPY %3
-    ; CHECK: %s1 = COPY %4
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %d0
+    ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
+    ; CHECK: %x0 = COPY [[COPY2]](s64)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
+    ; CHECK: %s0 = COPY [[TRUNC]](s32)
+    ; CHECK: %s1 = COPY [[TRUNC1]](s32)
     ; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
-    ; CHECK: %10(s32) = COPY %s0
-    %10(s32) = G_FREM %3, %4
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY %s0
+    ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
+    ; CHECK: %w0 = COPY [[COPY3]](s32)
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
+    %2(s64) = G_FREM %0, %1
+    %x0 = COPY %2
 
-...
+    %3(s32) = G_TRUNC %0
+    %4(s32) = G_TRUNC %1
+    %5(s32) = G_FREM %3, %4
+    %w0 = COPY %5
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
index f75a2982a3f2..7c84902f3b4e 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -22,26 +23,49 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
+    ; CHECK-LABEL: name: test_shift
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]]
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[ASHR1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
+    ; CHECK: %w0 = COPY [[COPY2]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]]
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: %w0 = COPY [[COPY3]](s32)
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY1]]0, [[COPY1]]1
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]]2(s32)
+    ; CHECK: %w0 = COPY [[COPY4]](s32)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
 
-    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %2
-    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %3
-    ; CHECK: [[RES32:%[0-9]+]](s32) = G_ASHR [[LHS32]], [[RHS32]]
-    ; CHECK: %4(s8) = G_TRUNC [[RES32]]
     %4(s8) = G_ASHR %2, %3
+    %7:_(s32) = G_ANYEXT %4
+    %w0 = COPY %7
+
 
-    ; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2
-    ; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3
-    ; CHECK: [[RES32:%[0-9]+]](s32) = G_LSHR [[LHS32]], [[RHS32]]
-    ; CHECK: %5(s8) = G_TRUNC [[RES32]]
     %5(s8) = G_LSHR %2, %3
+    %8:_(s32) = G_ANYEXT %5
+    %w0 = COPY %8
 
-    ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8)
-    ; CHECK: [[RES32:%.*]](s32) = G_SHL [[OP0]], [[OP1]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
     %6(s8) = G_SHL %2, %3
+    %9:_(s32) = G_ANYEXT %6
+    %w0 = COPY %9
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index cd24bccfe771..a7329916ea83 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -9,6 +10,15 @@
   next:
     ret void
   }
+  define void @bitcast128() {
+    ret void
+  }
+  define void @testExtOfCopyOfTrunc() {
+    ret void
+  }
+  define void @testExtOf2CopyOfTrunc() {
+    ret void
+  }
 ...
 
 ---
@@ -32,6 +42,46 @@ registers:
   - { id: 15, class: _ }
   - { id: 16, class: _ }
 body: |
+  ; CHECK-LABEL: name: test_simple
+  ; CHECK: bb.0.{{[a-zA-Z0-9]+}}:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+  ; CHECK:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
+  ; CHECK:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+  ; CHECK:   [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
+  ; CHECK:   %x0 = COPY [[PTRTOINT]](s64)
+  ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK: bb.1.{{[a-zA-Z0-9]+}}:
+  ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK:   [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+  ; CHECK:   %w0 = COPY [[COPY1]](s32)
+  ; CHECK:   [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK:   [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK:   [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
+  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
+  ; CHECK:   %w0 = COPY [[COPY2]](s32)
+  ; CHECK:   [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK:   [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK:   [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
+  ; CHECK:   [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
+  ; CHECK:   %w0 = COPY [[COPY3]](s32)
+  ; CHECK:   [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
+  ; CHECK:   [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
+  ; CHECK:   %x0 = COPY [[SELECT4]](s64)
+  ; CHECK:   [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](s64)
+  ; CHECK:   [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[BITCAST]](<2 x s32>)
+  ; CHECK:   %x0 = COPY [[BITCAST1]](s64)
+  ; CHECK:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[SELECT3]](s32)
+  ; CHECK:   %w0 = COPY [[BITCAST2]](s32)
+  ; CHECK:   [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[COPY]](s64)
+  ; CHECK:   [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST3]](<4 x s8>)
+  ; CHECK:   %w0 = COPY [[BITCAST4]](s32)
+  ; CHECK:   [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY]](s64)
+  ; CHECK:   [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST5]](<2 x s16>)
+  ; CHECK:   %w0 = COPY [[BITCAST6]](s32)
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     %0(s64) = COPY %x0
@@ -41,46 +91,119 @@ body: |
     %3(s16) = G_TRUNC %0
     %4(s32) = G_TRUNC %0
 
-    ; CHECK-LABEL: name: test_simple
-    ; CHECK: %5(p0) = G_INTTOPTR %0
-    ; CHECK: %6(s64) = G_PTRTOINT %5
     %5(p0) = G_INTTOPTR %0
     %6(s64) = G_PTRTOINT %5
+    %x0 = COPY %6
 
-    ; CHECK: G_BRCOND %1(s1), %bb.1.next
-    G_BRCOND %1, %bb.1.next
+    G_BRCOND %1, %bb.1
 
   bb.1.next:
 
-    ; CHECK: [[LHS:%[0-9]+]](s32) = G_ANYEXT %1(s1)
-    ; CHECK: [[RHS:%[0-9]+]](s32) = G_ANYEXT %1(s1)
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
-    ; CHECK: %7(s1) = G_TRUNC [[RES]](s32)
     %7(s1) = G_SELECT %1, %1, %1
+    %21:_(s32) = G_ANYEXT %7
+    %w0 = COPY %21
 
-    ; CHECK: [[LHS:%[0-9]+]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[RHS:%[0-9]+]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
-    ; CHECK: %8(s8) = G_TRUNC [[RES]](s32)
     %8(s8) = G_SELECT %1, %2, %2
+    %20:_(s32) = G_ANYEXT %8
+    %w0 = COPY %20
 
-    ; CHECK: [[LHS:%[0-9]+]](s32) = G_ANYEXT %3(s16)
-    ; CHECK: [[RHS:%[0-9]+]](s32) = G_ANYEXT %3(s16)
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
-    ; CHECK: %9(s16) = G_TRUNC [[RES]](s32)
     %9(s16) = G_SELECT %1, %3, %3
+    %19:_(s32) = G_ANYEXT %9
+    %w0 = COPY %19
 
     %10(s32) = G_SELECT %1, %4, %4
     %11(s64) = G_SELECT %1, %0, %0
+    %x0 = COPY %11
 
-    ; CHECK: %12(<2 x s32>) = G_BITCAST %0
-    ; CHECK: %13(s64) = G_BITCAST %12
-    ; CHECK: %14(s32) = G_BITCAST %10
-    ; CHECK: %15(<4 x s8>) = G_BITCAST %0
-    ; CHECK: %16(<2 x s16>) = G_BITCAST %0
     %12(<2 x s32>) = G_BITCAST %0
     %13(s64) = G_BITCAST %12
+    %x0 = COPY %13
     %14(s32) = G_BITCAST %10
+    %w0 = COPY %14
     %15(<4 x s8>) = G_BITCAST %0
+    %17:_(s32) = G_BITCAST %15
+    %w0 = COPY %17
     %16(<2 x s16>) = G_BITCAST %0
+    %18:_(s32) = G_BITCAST %16
+    %w0 = COPY %18
+...
+
+---
+name:            bitcast128
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _}
+  - { id: 1, class: _}
+  - { id: 2, class: _}
+  - { id: 3, class: _}
+body:             |
+  bb.1:
+    liveins: %x0, %x1
+    ; This is legal and shouldn't be changed.
+    ; CHECK-LABEL: name: bitcast128
+    ; CHECK: liveins: %x0, %x1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+    ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[MV]](s128)
+    ; CHECK: %q0 = COPY [[BITCAST]](<2 x s64>)
+    ; CHECK: RET_ReallyLR implicit %q0
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
+    %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
+    %2(<2 x s64>) = G_BITCAST %3(s128)
+    %q0 = COPY %2(<2 x s64>)
+    RET_ReallyLR implicit %q0
+
+...
+---
+name:            testExtOfCopyOfTrunc
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _}
+  - { id: 1, class: _}
+  - { id: 2, class: _}
+  - { id: 3, class: _}
+body:             |
+  bb.1:
+    liveins: %x0
+    ; CHECK-LABEL: name: testExtOfCopyOfTrunc
+    ; CHECK: liveins: %x0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: %x0 = COPY [[COPY1]](s64)
+    ; CHECK: RET_ReallyLR implicit %x0
+    %0(s64) = COPY %x0
+    %1(s1) = G_TRUNC %0
+    %2(s1) = COPY %1
+    %3(s64) = G_ANYEXT %2
+    %x0 = COPY %3
+    RET_ReallyLR implicit %x0
+
+...
+---
+name:            testExtOf2CopyOfTrunc
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _}
+  - { id: 1, class: _}
+  - { id: 2, class: _}
+  - { id: 3, class: _}
+body:             |
+  bb.1:
+    liveins: %x0
+    ; CHECK-LABEL: name: testExtOf2CopyOfTrunc
+    ; CHECK: liveins: %x0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: %x0 = COPY [[COPY1]](s64)
+    ; CHECK: RET_ReallyLR implicit %x0
+    %0(s64) = COPY %x0
+    %1(s1) = G_TRUNC %0
+    %2(s1) = COPY %1
+    %4:_(s1) = COPY %2
+    %3(s64) = G_ANYEXT %4
+    %x0 = COPY %3
+    RET_ReallyLR implicit %x0
+
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
index 82a1dd09c1a1..4baab17f464f 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -21,17 +22,20 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    ; CHECK-LABEL: name: test_scalar_sub_small
-    ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8)
-    ; CHECK: [[RES32:%.*]](s32) = G_SUB [[OP0]], [[OP1]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
 
+    ; CHECK-LABEL: name: test_scalar_sub_small
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
+    ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_SUB %2, %3
-    %5(s64) = G_ANYEXT %2
+    %5(s64) = G_ANYEXT %4
     %x0 = COPY %5
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir b/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
index e7cf59b3394e..6342fe373efd 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 ---
@@ -6,10 +7,12 @@ registers:
 body: |
   bb.0.entry:
     liveins:
-    ; CHECK-LABEL: name: test_implicit_def
-    ; CHECK: [[LO:%[0-9]+]](s64) = G_IMPLICIT_DEF
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_IMPLICIT_DEF
-    ; CHECK: %0(s128) = G_MERGE_VALUES [[LO]](s64), [[HI]](s64)
 
+    ; CHECK-LABEL: name: test_implicit_def
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+    ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
     %0:_(s128) = G_IMPLICIT_DEF
+    %1:_(s64) = G_TRUNC %0
+    %x0 = COPY %1
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir b/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
new file mode 100644
index 000000000000..85b65e945486
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
@@ -0,0 +1,28 @@
+# RUN: llc -O0 -run-pass=legalizer -global-isel -global-isel-abort=0 -pass-remarks-missed='gisel*' %s -o - 2>&1 | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64--"
+  define void @test_unmerge_s4() {
+    ret void
+  }
+...
+
+---
+name:            test_unmerge_s4
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body: |
+  bb.0:
+    %0(s8) = G_CONSTANT i8 0
+    ; Previously, LegalizerInfo was assuming all G_MERGE_VALUES and G_UNMERGE_VALUES
+    ; instructions are legal. Make sure that is no longer happening.
+    ; CHECK: unable to legalize instruction: {{.*}} G_UNMERGE_VALUES
+    %1(s4), %2(s4)= G_UNMERGE_VALUES %0(s8)
+    %3(s64) = G_ANYEXT %1(s4)
+    %x0 = COPY %3(s64)
+
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir b/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
index 8bda08d0a1d1..72dbf083192a 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -10,30 +11,28 @@
 name:            test_vaarg
 body: |
   bb.0:
+    ; CHECK-LABEL: name: test_vaarg
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD]], [[C]](s64)
+    ; CHECK: G_STORE [[GEP]](p0), [[COPY]](p0) :: (store 8)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
+    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[LOAD1]], [[C1]](s64)
+    ; CHECK: G_STORE [[GEP1]](p0), [[COPY]](p0) :: (store 8)
+    ; CHECK: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
+    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
+    ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[LOAD2]], [[C2]](s64)
+    ; CHECK: [[PTR_MASK:%[0-9]+]]:_(p0) = G_PTR_MASK [[GEP2]], 4
+    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[PTR_MASK]], [[C3]](s64)
+    ; CHECK: G_STORE [[GEP3]](p0), [[COPY]](p0) :: (store 8)
     %0:_(p0) = COPY %x0
 
-    ; CHECK-LABEL: name: test_vaarg
-    ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8)
-    ; CHECK: %1(s8) = G_LOAD [[LIST]](p0) :: (load 1, align 8)
-    ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
-    ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
     %1:_(s8) = G_VAARG %0(p0), 1
 
-    ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8)
-    ; CHECK: %2(s64) = G_LOAD [[LIST]](p0) :: (load 8)
-    ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
-    ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
     %2:_(s64) = G_VAARG %0(p0), 8
 
-    ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8)
-    ; CHECK: [[ALIGNM1:%[0-9]+]](s64) = G_CONSTANT i64 15
-    ; CHECK: [[ALIGNTMP:%[0-9]+]](p0) = G_GEP [[LIST]], [[ALIGNM1]](s64)
-    ; CHECK: [[LIST:%[0-9]+]](p0) = G_PTR_MASK [[ALIGNTMP]], 4
-    ; CHECK: %3(s64) = G_LOAD [[LIST]](p0) :: (load 8, align 16)
-    ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
-    ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
     %3:_(s64) = G_VAARG %0(p0), 16
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index 460b3d16f1c0..32cc63028f58 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -21,17 +22,20 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    ; CHECK-LABEL: name: test_scalar_xor_small
-    ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8)
-    ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8)
-    ; CHECK: [[RES32:%.*]](s32) = G_XOR [[OP0]], [[OP1]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
 
+    ; CHECK-LABEL: name: test_scalar_xor_small
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[XOR]](s32)
+    ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_XOR %2, %3
-    %5(s64) = G_ANYEXT %2
+    %5(s64) = G_ANYEXT %4
     %x0 = COPY %5
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir b/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
index 28c926b5d062..d4ed70fa5316 100644
--- a/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
+++ b/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
@@ -9,16 +9,16 @@
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
-  
+
   define float @foo(float %arg, i1 %cond) {
     br i1 %cond, label %true, label %false
-  
+
   true:                                             ; preds = %0
     br label %end
-  
+
   false:                                            ; preds = %0
     br label %end
-  
+
   end:                                              ; preds = %false, %true
     %val = phi float [ 1.000000e+00, %true ], [ 2.000000e+00, %false ]
     %res = fadd float %arg, %val
@@ -41,54 +41,57 @@ registers:
 # CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
 # CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
 # CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 6, class: gpr, preferred-register: '' }
 # The localizer will create two new values to materialize the constants.
-# OPTNONE-NEXT:  - { id: 6, class: fpr, preferred-register: '' }
 # OPTNONE-NEXT:  - { id: 7, class: fpr, preferred-register: '' }
+# OPTNONE-NEXT:  - { id: 8, class: fpr, preferred-register: '' }
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
   - { id: 2, class: fpr }
   - { id: 3, class: fpr }
   - { id: 4, class: fpr }
   - { id: 5, class: fpr }
+  - { id: 6, class: gpr }
 
 # First block remains untouched
 # CHECK: body
-# CHECK:   %4(s32) = G_FCONSTANT float 1.000000e+00
-# CHECK:   %5(s32) = G_FCONSTANT float 2.000000e+00
+# CHECK:   %4:fpr(s32) = G_FCONSTANT float 1.000000e+00
+# CHECK:   %5:fpr(s32) = G_FCONSTANT float 2.000000e+00
 
 # Second block will get the constant 1.0 when the localizer is enabled.
-# CHECK: bb.1.true:
+# CHECK: bb.1.{{[a-zA-Z0-9]+}}:
 # OPT-NOT: G_FCONSTANT
-# OPTNONE: [[FONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-# CHECK: G_BR %bb.3.end
+# OPTNONE: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+# CHECK: G_BR %bb.3
 
 # Thrid block will get the constant 2.0 when the localizer is enabled.
-# CHECK: bb.2.false:
+# CHECK: bb.2.{{[a-zA-Z0-9]+}}:
 # OPT-NOT: G_FCONSTANT
-# OPTNONE: [[FTWO:%[0-9]+]](s32) = G_FCONSTANT float 2.000000e+00
+# OPTNONE: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
 
 # CHECK: bb.3.end
-# OPTNONE: %2(s32) = PHI [[FONE]](s32), %bb.1.true, [[FTWO]](s32), %bb.2.false
-# OPT: %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
+# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1, [[FTWO]](s32), %bb.2
+# OPT: %2:fpr(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
 # CHECK-NEXT: G_FADD %0, %2
 body:             |
   bb.0 (%ir-block.0):
     liveins: %s0, %w0
 
     %0(s32) = COPY %s0
-    %1(s1) = COPY %w0
+    %6(s32) = COPY %w0
+    %1(s1) = G_TRUNC %6
     %4(s32) = G_FCONSTANT float 1.000000e+00
     %5(s32) = G_FCONSTANT float 2.000000e+00
-    G_BRCOND %1(s1), %bb.1.true
-    G_BR %bb.2.false
-  
+    G_BRCOND %1(s1), %bb.1
+    G_BR %bb.2
+
   bb.1.true:
-    G_BR %bb.3.end
-  
+    G_BR %bb.3
+
   bb.2.false:
-  
+
   bb.3.end:
-    %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
+    %2(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
     %3(s32) = G_FADD %0, %2
     %s0 = COPY %3(s32)
     RET_ReallyLR implicit %s0
diff --git a/test/CodeGen/AArch64/GlobalISel/localizer.mir b/test/CodeGen/AArch64/GlobalISel/localizer.mir
index afe2c13f025d..5de006a7d3fa 100644
--- a/test/CodeGen/AArch64/GlobalISel/localizer.mir
+++ b/test/CodeGen/AArch64/GlobalISel/localizer.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=localizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK
 
 # Test the localizer.
@@ -13,349 +14,290 @@
   define void @non_local_phi_use_followed_by_use_fi() { ret void }
   define void @float_non_local_phi_use_followed_by_use_fi() { ret void }
   define void @non_local_phi() { ret void }
+  define void @non_local_label() { ret void }
 ...
 
 ---
-# CHECK-LABEL: name: local_use
 name:            local_use
 legalized:       true
 regBankSelected: true
-
-# CHECK:      registers:
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0(s32) = G_CONSTANT 1
-# CHECK-NEXT: %1(s32) = G_ADD %0, %0
 body:             |
   bb.0:
-    %0(s32) = G_CONSTANT 1
-    %1(s32) = G_ADD %0, %0
+    ; CHECK-LABEL: name: local_use
+    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+    ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: non_local_1use
 name:            non_local_1use
 legalized:       true
 regBankSelected: true
+body:             |
+  ; CHECK-LABEL: name: non_local_1use
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+  ; CHECK: bb.1:
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[ADD]]
 
-# CHECK:      registers:
-# Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0(s32) = G_CONSTANT 1
-# CHECK-NEXT: %1(s32) = G_ADD %0, %0
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
 
-# CHECK: bb.1:
-# CHECK: %3(s32) = G_CONSTANT 1
-# CHECK-NEXT: %2(s32) = G_ADD %3, %1
-body:             |
   bb.0:
     successors: %bb.1
 
-    %0(s32) = G_CONSTANT 1
-    %1(s32) = G_ADD %0, %0
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
-    %2(s32) = G_ADD %0, %1
+    %2:gpr(s32) = G_ADD %0, %1
 ...
 
-
 ---
-# CHECK-LABEL: name: non_local_2uses
 name:            non_local_2uses
 legalized:       true
 regBankSelected: true
+body:             |
+  ; CHECK-LABEL: name: non_local_2uses
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+  ; CHECK: bb.1:
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[C1]]
 
-# CHECK:      registers:
-# Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0(s32) = G_CONSTANT 1
-# CHECK-NEXT: %1(s32) = G_ADD %0, %0
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
 
-# CHECK: bb.1:
-# CHECK: %3(s32) = G_CONSTANT 1
-# CHECK-NEXT: %2(s32) = G_ADD %3, %3
-body:             |
   bb.0:
     successors: %bb.1
 
-    %0(s32) = G_CONSTANT 1
-    %1(s32) = G_ADD %0, %0
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
-    %2(s32) = G_ADD %0, %0
+    %2:gpr(s32) = G_ADD %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: non_local_phi_use
 name:            non_local_phi_use
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: non_local_phi_use
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK: bb.2:
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]
 
-# CHECK:      registers:
-# Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
-# The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
-
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0(s32) = G_CONSTANT 1
-# CHECK-NEXT: %1(s32) = G_ADD %0, %0
-
-# CHECK: bb.1:
-# CHECK: %5(s32) = G_CONSTANT 1
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
 
-# CHECK: bb.2:
-# CHECK: %3(s32) = PHI %5(s32), %bb.1
-body:             |
   bb.0:
     successors: %bb.1
 
-    %0(s32) = G_CONSTANT 1
-    %1(s32) = G_ADD %0, %0
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
     successors: %bb.2
 
   bb.2:
-    %3(s32) = PHI %0(s32), %bb.1
-    %2(s32) = G_ADD %3, %3
+    %3:gpr(s32) = PHI %0(s32), %bb.1
+    %2:gpr(s32) = G_ADD %3, %3
 ...
 
 ---
-# CHECK-LABEL: name: non_local_phi_use_followed_by_use
 name:            non_local_phi_use_followed_by_use
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: non_local_phi_use_followed_by_use
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK: bb.2:
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1
+  ; CHECK:   [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[C2]]
 
-# CHECK:      registers:
-# Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
-# The newly created regs should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 6, class: gpr, preferred-register: '' }
-
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0(s32) = G_CONSTANT 1
-# CHECK-NEXT: %1(s32) = G_ADD %0, %0
-
-# CHECK: bb.1:
-# CHECK: %5(s32) = G_CONSTANT 1
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
 
-# CHECK: bb.2:
-# CHECK: %3(s32) = PHI %5(s32), %bb.1
-# CHECK-NEXT: %6(s32) = G_CONSTANT 1
-# CHECK-NEXT: %2(s32) = G_ADD %3, %6
-body:             |
   bb.0:
     successors: %bb.1
 
-    %0(s32) = G_CONSTANT 1
-    %1(s32) = G_ADD %0, %0
+    %0:gpr(s32) = G_CONSTANT 1
+    %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
     successors: %bb.2
 
   bb.2:
-    %3(s32) = PHI %0(s32), %bb.1
-    %2(s32) = G_ADD %3, %0
+    %3:gpr(s32) = PHI %0(s32), %bb.1
+    %2:gpr(s32) = G_ADD %3, %0
 ...
 
 ---
-# CHECK-LABEL: name: non_local_phi_use_followed_by_use_fi
 name:            non_local_phi_use_followed_by_use_fi
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: non_local_phi_use_followed_by_use_fi
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[FRAME_INDEX]], [[FRAME_INDEX]]
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
+  ; CHECK: bb.2:
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI [[FRAME_INDEX1]](s32), %bb.1
+  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[FRAME_INDEX2]]
 
-# CHECK:      registers:
-# Existing registers should be left untouched
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
-# The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 6, class: gpr, preferred-register: '' }
-
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0(s32) = G_FRAME_INDEX 1
-# CHECK-NEXT: %1(s32) = G_ADD %0, %0
-
-# CHECK: bb.1:
-# CHECK: %5(s32) = G_FRAME_INDEX 1
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
 
-# CHECK: bb.2:
-# CHECK: %3(s32) = PHI %5(s32), %bb.1
-# CHECK-NEXT: %6(s32) = G_FRAME_INDEX 1
-# CHECK-NEXT: %2(s32) = G_ADD %3, %6
-body:             |
   bb.0:
     successors: %bb.1
 
-    %0(s32) = G_FRAME_INDEX 1
-    %1(s32) = G_ADD %0, %0
+    %0:gpr(s32) = G_FRAME_INDEX 1
+    %1:gpr(s32) = G_ADD %0, %0
 
   bb.1:
     successors: %bb.2
 
   bb.2:
-    %3(s32) = PHI %0(s32), %bb.1
-    %2(s32) = G_ADD %3, %0
+    %3:gpr(s32) = PHI %0(s32), %bb.1
+    %2:gpr(s32) = G_ADD %3, %0
 ...
 
 ---
-# CHECK-LABEL: name: float_non_local_phi_use_followed_by_use_fi
 name:            float_non_local_phi_use_followed_by_use_fi
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: float_non_local_phi_use_followed_by_use_fi
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK: bb.2:
+  ; CHECK:   [[PHI:%[0-9]+]]:fpr(s32) = PHI [[C1]](s32), %bb.1
+  ; CHECK:   [[C2:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[C2]]
 
-# CHECK:      registers:
-# Existing registers should be left untouched
-# CHECK:  - { id: 0, class: fpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
-# The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 5, class: fpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 6, class: fpr, preferred-register: '' }
-
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
-  - { id: 4, class: fpr }
-
-# CHECK:  body:
-# CHECK:    %0(s32) = G_FCONSTANT float 1.0
-# CHECK-NEXT: %1(s32) = G_FADD %0, %0
-
-# CHECK: bb.1:
-# CHECK: %5(s32) = G_FCONSTANT float 1.0
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
 
-# CHECK: bb.2:
-# CHECK: %3(s32) = PHI %5(s32), %bb.1
-# CHECK-NEXT: %6(s32) = G_FCONSTANT float 1.0
-# CHECK-NEXT: %2(s32) = G_FADD %3, %6
-body:             |
   bb.0:
     successors: %bb.1
 
-    %0(s32) = G_FCONSTANT float 1.0
-    %1(s32) = G_FADD %0, %0
+    %0:fpr(s32) = G_FCONSTANT float 1.0
+    %1:fpr(s32) = G_FADD %0, %0
 
   bb.1:
     successors: %bb.2
 
   bb.2:
-    %3(s32) = PHI %0(s32), %bb.1
-    %2(s32) = G_FADD %3, %0
+    %3:fpr(s32) = PHI %0(s32), %bb.1
+    %2:fpr(s32) = G_FADD %3, %0
 ...
 
 ---
 # Make sure we don't insert a constant before PHIs.
 # This used to happen for loops of one basic block.
-# CHECK-LABEL: name: non_local_phi
 name:            non_local_phi
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: non_local_phi
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[PHI:%[0-9]+]]:fpr(s32) = PHI [[FADD]](s32), %bb.0, %4(s32), %bb.1
+  ; CHECK:   [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[FADD]]
+  ; CHECK:   G_BR %bb.1
 
-# CHECK:      registers:
-# Existing registers should be left untouched
-# CHECK:  - { id: 0, class: fpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
-#CHECK-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
-# The newly created reg should be on the same regbank/regclass as its origin.
-#CHECK-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
+
+  bb.0:
+    successors: %bb.1
 
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: fpr }
+    %0:fpr(s32) = G_FCONSTANT float 1.0
+    %1:fpr(s32) = G_FADD %0, %0
 
-# CHECK:  body:
-# CHECK:    %0(s32) = G_FCONSTANT float 1.0
-# CHECK-NEXT: %1(s32) = G_FADD %0, %0
+  bb.1:
+    successors: %bb.1
 
-# CHECK: bb.1:
-# CHECK: %3(s32) = PHI %1(s32), %bb.0, %4(s32), %bb.1
-# CHECK: %4(s32) = G_FCONSTANT float 1.0
+    %3:fpr(s32) = PHI %1(s32), %bb.0, %0(s32), %bb.1
+    %2:fpr(s32) = G_FADD %3, %1
+    G_BR %bb.1
+...
 
-# CHECK-NEXT: %2(s32) = G_FADD %3, %1
+---
+# Make sure we don't insert a constant before EH_LABELs.
+name:            non_local_label
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
 body:             |
+  ; CHECK-LABEL: name: non_local_label
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: %s0
+  ; CHECK:   [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+  ; CHECK:   [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   EH_LABEL 1
+  ; CHECK:   [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[COPY]], [[C1]]
+  ; CHECK:   G_BR %bb.1
+
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
+
   bb.0:
+    liveins: %s0
     successors: %bb.1
 
-    %0(s32) = G_FCONSTANT float 1.0
-    %1(s32) = G_FADD %0, %0
+    %0:fpr(s32) = COPY %s0
+    %1:fpr(s32) = G_FCONSTANT float 1.0
 
   bb.1:
     successors: %bb.1
 
-    %3(s32) = PHI %1(s32), %bb.0, %0(s32), %bb.1
-    %2(s32) = G_FADD %3, %1
+    EH_LABEL 1
+    %2:fpr(s32) = G_FADD %0, %1
     G_BR %bb.1
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/no-regclass.mir b/test/CodeGen/AArch64/GlobalISel/no-regclass.mir
index 741d76b830c1..8732274fe034 100644
--- a/test/CodeGen/AArch64/GlobalISel/no-regclass.mir
+++ b/test/CodeGen/AArch64/GlobalISel/no-regclass.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s
 
 # We run the legalizer to combine the trivial EXTRACT_SEQ pair, leaving %1 and
@@ -10,21 +11,21 @@
   define void @unused_reg() { ret void }
 
 ---
-# CHECK-LABEL: name: unused_reg
 name:            unused_reg
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 
-# CHECK:      body:
-# CHECK:  %0 = COPY %w0
-# CHECK:  %w0 = COPY %0
 
 body:             |
   bb.0:
     liveins: %w0
+    ; CHECK-LABEL: name: unused_reg
+    ; CHECK: liveins: %w0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
+    ; CHECK: %w0 = COPY [[COPY]]
     %0:gpr(s32) = COPY %w0
-    %1:gpr(s32) = G_MERGE_VALUES %0(s32)
-    %2:gpr(s32) = G_UNMERGE_VALUES %1(s32)
+    %1:gpr(s64) = G_MERGE_VALUES %0(s32), %0(s32)
+    %2:gpr(s32), %3:gpr(s32) = G_UNMERGE_VALUES %1(s64)
     %w0 = COPY %2(s32)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir b/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
new file mode 100644
index 000000000000..b675389fd5b3
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=aarch64 -global-isel -run-pass=regbankselect -o - %s | FileCheck %s
+---
+name:            test_large_merge
+legalized:       true
+registers:
+body: |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2
+
+    ; CHECK-LABEL: name: test_large_merge
+    ; CHECK: registers:
+    ; CHECK:       - { id: 0, class: gpr
+    ; CHECK:       - { id: 1, class: gpr
+    ; CHECK:       - { id: 2, class: gpr
+    ; CHECK:       - { id: 3, class: fpr
+    %0:_(s64) = COPY %x0
+    %1:_(s64) = COPY %x1
+    %2:_(p0) = COPY %x2
+    %3:_(s128) = G_MERGE_VALUES %0, %1
+    %4:_(s64) = G_TRUNC %3
+    %d0 = COPY %4
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
index c8a8266e8b28..201565c675af 100644
--- a/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
+++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
@@ -5,7 +5,7 @@
 
   define void @test_dbg_value() !dbg !5 {
     ; Keep the dbg metadata live by referencing it in the IR.
-    call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !9), !dbg !10
+    call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
     ret void
   }
 
@@ -23,8 +23,7 @@
   !6 = !DISubroutineType(types: !2)
   !7 = !DILocalVariable(name: "in", arg: 1, scope: !5, file: !1, line: 1, type: !8)
   !8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
-  !9 = !DIExpression()
-  !10 = !DILocation(line: 1, column: 1, scope: !5)
+  !9 = !DILocation(line: 1, column: 1, scope: !5)
 ...
 
 ---
@@ -37,9 +36,9 @@ body: |
   bb.0:
     liveins: %w0
     %0:_(s32) = COPY %w0
-    ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !7, !9, debug-location !10
-    DBG_VALUE debug-use %0(s32), debug-use _, !7, !9, debug-location !10
+    ; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
+    DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
 
-    ; CHECK: DBG_VALUE _, 0, !7, !9, debug-location !10
-    DBG_VALUE _, 0, !7, !9, debug-location !10
+    ; CHECK: DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
+    DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index b8468d8cf55f..df40a7f659ac 100644
--- a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s
 
 # Check the default mappings for various instructions.
@@ -66,805 +67,742 @@
 
   define void @test_fptosi_s64_s32() { ret void }
   define void @test_fptoui_s32_s64() { ret void }
+
+  define void @test_gphi_ptr() { ret void }
+
 ...
 
 ---
-# CHECK-LABEL: name: test_add_s32
 name:            test_add_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_ADD %0, %0
+    ; CHECK-LABEL: name: test_add_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_add_v4s32
 name:            test_add_v4s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
-    ; CHECK:      %0(<4 x s32>) = COPY %q0
-    ; CHECK:      %1(<4 x s32>) = G_ADD %0, %0
+    ; CHECK-LABEL: name: test_add_v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[ADD:%[0-9]+]]:fpr(<4 x s32>) = G_ADD [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_ADD %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_sub_s32
 name:            test_sub_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_SUB %0, %0
+    ; CHECK-LABEL: name: test_sub_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SUB:%[0-9]+]]:gpr(s32) = G_SUB [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_SUB %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_sub_v4s32
 name:            test_sub_v4s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
-    ; CHECK:      %0(<4 x s32>) = COPY %q0
-    ; CHECK:      %1(<4 x s32>) = G_SUB %0, %0
+    ; CHECK-LABEL: name: test_sub_v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[SUB:%[0-9]+]]:fpr(<4 x s32>) = G_SUB [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_SUB %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_mul_s32
 name:            test_mul_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_MUL %0, %0
+    ; CHECK-LABEL: name: test_mul_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[MUL:%[0-9]+]]:gpr(s32) = G_MUL [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_MUL %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_mul_v4s32
 name:            test_mul_v4s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
-    ; CHECK:      %0(<4 x s32>) = COPY %q0
-    ; CHECK:      %1(<4 x s32>) = G_MUL %0, %0
+    ; CHECK-LABEL: name: test_mul_v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[MUL:%[0-9]+]]:fpr(<4 x s32>) = G_MUL [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_MUL %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_and_s32
 name:            test_and_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_AND %0, %0
+    ; CHECK-LABEL: name: test_and_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_AND %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_and_v4s32
 name:            test_and_v4s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
-    ; CHECK:      %0(<4 x s32>) = COPY %q0
-    ; CHECK:      %1(<4 x s32>) = G_AND %0, %0
+    ; CHECK-LABEL: name: test_and_v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[AND:%[0-9]+]]:fpr(<4 x s32>) = G_AND [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_AND %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_or_s32
 name:            test_or_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_OR %0, %0
+    ; CHECK-LABEL: name: test_or_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[OR:%[0-9]+]]:gpr(s32) = G_OR [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_OR %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_or_v4s32
 name:            test_or_v4s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
-    ; CHECK:      %0(<4 x s32>) = COPY %q0
-    ; CHECK:      %1(<4 x s32>) = G_OR %0, %0
+    ; CHECK-LABEL: name: test_or_v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[OR:%[0-9]+]]:fpr(<4 x s32>) = G_OR [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_OR %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_xor_s32
 name:            test_xor_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_XOR %0, %0
+    ; CHECK-LABEL: name: test_xor_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[XOR:%[0-9]+]]:gpr(s32) = G_XOR [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_XOR %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_xor_v4s32
 name:            test_xor_v4s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
-    ; CHECK:      %0(<4 x s32>) = COPY %q0
-    ; CHECK:      %1(<4 x s32>) = G_XOR %0, %0
+    ; CHECK-LABEL: name: test_xor_v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[XOR:%[0-9]+]]:fpr(<4 x s32>) = G_XOR [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_XOR %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_shl_s32
 name:            test_shl_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_SHL %0, %0
+    ; CHECK-LABEL: name: test_shl_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SHL:%[0-9]+]]:gpr(s32) = G_SHL [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_SHL %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_shl_v4s32
 name:            test_shl_v4s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %q0
-    ; CHECK:      %0(<4 x s32>) = COPY %q0
-    ; CHECK:      %1(<4 x s32>) = G_SHL %0, %0
+    ; CHECK-LABEL: name: test_shl_v4s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[SHL:%[0-9]+]]:fpr(<4 x s32>) = G_SHL [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_SHL %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_lshr_s32
 name:            test_lshr_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_LSHR %0, %0
+    ; CHECK-LABEL: name: test_lshr_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[LSHR:%[0-9]+]]:gpr(s32) = G_LSHR [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_LSHR %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_ashr_s32
 name:            test_ashr_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_ASHR %0, %0
+    ; CHECK-LABEL: name: test_ashr_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ASHR:%[0-9]+]]:gpr(s32) = G_ASHR [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_ASHR %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_sdiv_s32
 name:            test_sdiv_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_SDIV %0, %0
+    ; CHECK-LABEL: name: test_sdiv_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SDIV:%[0-9]+]]:gpr(s32) = G_SDIV [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_SDIV %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_udiv_s32
 name:            test_udiv_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s32) = G_UDIV %0, %0
+    ; CHECK-LABEL: name: test_udiv_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[UDIV:%[0-9]+]]:gpr(s32) = G_UDIV [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_UDIV %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_anyext_s64_s32
 name:            test_anyext_s64_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s64) = G_ANYEXT %0
+    ; CHECK-LABEL: name: test_anyext_s64_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ANYEXT:%[0-9]+]]:gpr(s64) = G_ANYEXT [[COPY]](s32)
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
 ...
 
 ---
-# CHECK-LABEL: name: test_sext_s64_s32
 name:            test_sext_s64_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s64) = G_SEXT %0
+    ; CHECK-LABEL: name: test_sext_s64_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SEXT:%[0-9]+]]:gpr(s64) = G_SEXT [[COPY]](s32)
     %0(s32) = COPY %w0
     %1(s64) = G_SEXT %0
 ...
 
 ---
-# CHECK-LABEL: name: test_zext_s64_s32
 name:            test_zext_s64_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s64) = G_ZEXT %0
+    ; CHECK-LABEL: name: test_zext_s64_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ZEXT:%[0-9]+]]:gpr(s64) = G_ZEXT [[COPY]](s32)
     %0(s32) = COPY %w0
     %1(s64) = G_ZEXT %0
 ...
 
 ---
-# CHECK-LABEL: name: test_trunc_s32_s64
 name:            test_trunc_s32_s64
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
-    ; CHECK:      %0(s64) = COPY %x0
-    ; CHECK:      %1(s32) = G_TRUNC %0
+    ; CHECK-LABEL: name: test_trunc_s32_s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
+    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s32) = G_TRUNC [[COPY]](s64)
     %0(s64) = COPY %x0
     %1(s32) = G_TRUNC %0
 ...
 
 ---
-# CHECK-LABEL: name: test_constant_s32
 name:            test_constant_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
-    ; CHECK:      %0(s32) = G_CONSTANT 123
+    ; CHECK-LABEL: name: test_constant_s32
+    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 123
     %0(s32) = G_CONSTANT 123
 ...
 
 ---
-# CHECK-LABEL: name: test_constant_p0
 name:            test_constant_p0
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
-    ; CHECK:      %0(p0) = G_CONSTANT 0
+    ; CHECK-LABEL: name: test_constant_p0
+    ; CHECK: [[C:%[0-9]+]]:gpr(p0) = G_CONSTANT 0
     %0(p0) = G_CONSTANT 0
 ...
 
 ---
-# CHECK-LABEL: name: test_icmp_s32
 name:            test_icmp_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
+  - { id: 2, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s1) = G_ICMP intpred(ne), %0(s32), %0
+    ; CHECK-LABEL: name: test_icmp_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
     %0(s32) = COPY %w0
-    %1(s1) = G_ICMP intpred(ne), %0, %0
+    %1(s32) = G_ICMP intpred(ne), %0, %0
+    %2(s1) = G_TRUNC %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: test_icmp_p0
 name:            test_icmp_p0
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
+  - { id: 2, class: _ }
 body: |
   bb.0:
     liveins: %x0
-    ; CHECK:      %0(p0) = COPY %x0
-    ; CHECK:      %1(s1) = G_ICMP intpred(ne), %0(p0), %0
+    ; CHECK-LABEL: name: test_icmp_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+    ; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
     %0(p0) = COPY %x0
-    %1(s1) = G_ICMP intpred(ne), %0, %0
+    %1(s32) = G_ICMP intpred(ne), %0, %0
+    %2(s1) = G_TRUNC %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: test_frame_index_p0
 name:            test_frame_index_p0
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 body: |
   bb.0:
-    ; CHECK:      %0(p0) = G_FRAME_INDEX %stack.0.ptr0
+    ; CHECK-LABEL: name: test_frame_index_p0
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0.ptr0
     %0(p0) = G_FRAME_INDEX %stack.0.ptr0
 ...
 
 ---
-# CHECK-LABEL: name: test_ptrtoint_s64_p0
 name:            test_ptrtoint_s64_p0
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
-    ; CHECK:      %0(p0) = COPY %x0
-    ; CHECK:      %1(s64) = G_PTRTOINT %0
+    ; CHECK-LABEL: name: test_ptrtoint_s64_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:gpr(s64) = G_PTRTOINT [[COPY]](p0)
     %0(p0) = COPY %x0
     %1(s64) = G_PTRTOINT %0
 ...
 
 ---
-# CHECK-LABEL: name: test_inttoptr_p0_s64
 name:            test_inttoptr_p0_s64
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
-    ; CHECK:      %0(s64) = COPY %x0
-    ; CHECK:      %1(p0) = G_INTTOPTR %0
+    ; CHECK-LABEL: name: test_inttoptr_p0_s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[COPY]](s64)
     %0(s64) = COPY %x0
     %1(p0) = G_INTTOPTR %0
 ...
 
 ---
-# CHECK-LABEL: name: test_load_s32_p0
 name:            test_load_s32_p0
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
-    ; CHECK:      %0(p0) = COPY %x0
-    ; CHECK:      %1(s32) = G_LOAD %0
+    ; CHECK-LABEL: name: test_load_s32_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+    ; CHECK: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4)
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD %0 :: (load 4)
 ...
 
 ---
-# CHECK-LABEL: name: test_store_s32_p0
 name:            test_store_s32_p0
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0, %w1
-    ; CHECK:      %0(p0) = COPY %x0
-    ; CHECK:      %1(s32) = COPY %w1
-    ; CHECK:      G_STORE %1(s32), %0(p0)
+    ; CHECK-LABEL: name: test_store_s32_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %w1
+    ; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store 4)
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
     G_STORE %1, %0 :: (store 4)
 ...
 
 ---
-# CHECK-LABEL: name: test_fadd_s32
 name:            test_fadd_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
-    ; CHECK:      %0(s32) = COPY %s0
-    ; CHECK:      %1(s32) = G_FADD %0, %0
+    ; CHECK-LABEL: name: test_fadd_s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[COPY]], [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_FADD %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_fsub_s32
 name:            test_fsub_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
-    ; CHECK:      %0(s32) = COPY %s0
-    ; CHECK:      %1(s32) = G_FSUB %0, %0
+    ; CHECK-LABEL: name: test_fsub_s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FSUB:%[0-9]+]]:fpr(s32) = G_FSUB [[COPY]], [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_FSUB %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_fmul_s32
 name:            test_fmul_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
-    ; CHECK:      %0(s32) = COPY %s0
-    ; CHECK:      %1(s32) = G_FMUL %0, %0
+    ; CHECK-LABEL: name: test_fmul_s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FMUL:%[0-9]+]]:fpr(s32) = G_FMUL [[COPY]], [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_FMUL %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_fdiv_s32
 name:            test_fdiv_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
-    ; CHECK:      %0(s32) = COPY %s0
-    ; CHECK:      %1(s32) = G_FDIV %0, %0
+    ; CHECK-LABEL: name: test_fdiv_s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FDIV:%[0-9]+]]:fpr(s32) = G_FDIV [[COPY]], [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_FDIV %0, %0
 ...
 
 ---
-# CHECK-LABEL: name: test_fpext_s64_s32
 name:            test_fpext_s64_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
-    ; CHECK:      %0(s32) = COPY %s0
-    ; CHECK:      %1(s64) = G_FPEXT %0
+    ; CHECK-LABEL: name: test_fpext_s64_s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FPEXT:%[0-9]+]]:fpr(s64) = G_FPEXT [[COPY]](s32)
     %0(s32) = COPY %s0
     %1(s64) = G_FPEXT %0
 ...
 
 ---
-# CHECK-LABEL: name: test_fptrunc_s32_s64
 name:            test_fptrunc_s32_s64
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %d0
-    ; CHECK:      %0(s64) = COPY %d0
-    ; CHECK:      %1(s32) = G_FPTRUNC %0
+    ; CHECK-LABEL: name: test_fptrunc_s32_s64
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %d0
+    ; CHECK: [[FPTRUNC:%[0-9]+]]:fpr(s32) = G_FPTRUNC [[COPY]](s64)
     %0(s64) = COPY %d0
     %1(s32) = G_FPTRUNC %0
 ...
 
 ---
-# CHECK-LABEL: name: test_fconstant_s32
 name:            test_fconstant_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
-    ; CHECK:      %0(s32) = G_FCONSTANT float 1.0
+    ; CHECK-LABEL: name: test_fconstant_s32
+    ; CHECK: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
     %0(s32) = G_FCONSTANT float 1.0
 ...
 
 ---
-# CHECK-LABEL: name: test_fcmp_s32
 name:            test_fcmp_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
+  - { id: 2, class: _ }
 body: |
   bb.0:
     liveins: %s0
-    ; CHECK:      %0(s32) = COPY %s0
-    ; CHECK:      %1(s1) = G_FCMP floatpred(olt), %0(s32), %0
+    ; CHECK-LABEL: name: test_fcmp_s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(olt), [[COPY]](s32), [[COPY]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[FCMP]](s32)
     %0(s32) = COPY %s0
-    %1(s1) = G_FCMP floatpred(olt), %0, %0
+    %1(s32) = G_FCMP floatpred(olt), %0, %0
+    %2(s1) = G_TRUNC %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: test_sitofp_s64_s32
 name:            test_sitofp_s64_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; CHECK:      %0(s32) = COPY %w0
-    ; CHECK:      %1(s64) = G_SITOFP %0
+    ; CHECK-LABEL: name: test_sitofp_s64_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SITOFP:%[0-9]+]]:fpr(s64) = G_SITOFP [[COPY]](s32)
     %0(s32) = COPY %w0
     %1(s64) = G_SITOFP %0
 ...
 
 ---
-# CHECK-LABEL: name: test_uitofp_s32_s64
 name:            test_uitofp_s32_s64
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %x0
-    ; CHECK:      %0(s64) = COPY %x0
-    ; CHECK:      %1(s32) = G_UITOFP %0
+    ; CHECK-LABEL: name: test_uitofp_s32_s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
+    ; CHECK: [[UITOFP:%[0-9]+]]:fpr(s32) = G_UITOFP [[COPY]](s64)
     %0(s64) = COPY %x0
     %1(s32) = G_UITOFP %0
 ...
 
 ---
-# CHECK-LABEL: name: test_fptosi_s64_s32
 name:            test_fptosi_s64_s32
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %s0
-    ; CHECK:      %0(s32) = COPY %s0
-    ; CHECK:      %1(s64) = G_FPTOSI %0
+    ; CHECK-LABEL: name: test_fptosi_s64_s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:gpr(s64) = G_FPTOSI [[COPY]](s32)
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOSI %0
 ...
 
 ---
-# CHECK-LABEL: name: test_fptoui_s32_s64
 name:            test_fptoui_s32_s64
 legalized:       true
-# CHECK: registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0:
     liveins: %d0
-    ; CHECK:      %0(s64) = COPY %d0
-    ; CHECK:      %1(s32) = G_FPTOUI %0
+    ; CHECK-LABEL: name: test_fptoui_s32_s64
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %d0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:gpr(s32) = G_FPTOUI [[COPY]](s64)
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOUI %0
 ...
+
+---
+name:            test_gphi_ptr
+legalized:       true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: _, preferred-register: '' }
+  - { id: 3, class: _, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+body:             |
+  ; CHECK-LABEL: name: test_gphi_ptr
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: %w2, %x0, %x1
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr(p0) = COPY %x1
+  ; CHECK:   [[COPY2:%[0-9]+]]:gpr(s32) = COPY %w2
+  ; CHECK:   [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY2]](s32)
+  ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
+  ; CHECK:   G_BR %bb.2
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK: bb.2:
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
+  ; CHECK:   %x0 = COPY [[PHI]](p0)
+  ; CHECK:   RET_ReallyLR implicit %x0
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: %w2, %x0, %x1
+
+    %0(p0) = COPY %x0
+    %1(p0) = COPY %x1
+    %4(s32) = COPY %w2
+    %2(s1) = G_TRUNC %4(s32)
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.2
+
+  bb.1:
+    successors: %bb.2
+
+
+  bb.2:
+    %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
+    %x0 = COPY %3(p0)
+    RET_ReallyLR implicit %x0
+
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir b/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
new file mode 100644
index 000000000000..cab5489ab6f4
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
@@ -0,0 +1,238 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @atomicrmw_xchg_i64(i64* %addr) { ret void }
+  define void @atomicrmw_add_i64(i64* %addr) { ret void }
+  define void @atomicrmw_add_i32(i64* %addr) { ret void }
+  define void @atomicrmw_sub_i32(i64* %addr) { ret void }
+  define void @atomicrmw_and_i32(i64* %addr) { ret void }
+  ; nand isn't legal
+  define void @atomicrmw_or_i32(i64* %addr) { ret void }
+  define void @atomicrmw_xor_i32(i64* %addr) { ret void }
+  define void @atomicrmw_min_i32(i64* %addr) { ret void }
+  define void @atomicrmw_max_i32(i64* %addr) { ret void }
+  define void @atomicrmw_umin_i32(i64* %addr) { ret void }
+  define void @atomicrmw_umax_i32(i64* %addr) { ret void }
+...
+
+---
+name:            atomicrmw_xchg_i64
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_xchg_i64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr64 = SWPX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
+    ; CHECK: %x0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s64) = G_CONSTANT i64 1
+    %2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr)
+    %x0 = COPY %2(s64)
+...
+---
+name:            atomicrmw_add_i64
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_add_i64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr64 = LDADDX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
+    ; CHECK: %x0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s64) = G_CONSTANT i64 1
+    %2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
+    %x0 = COPY %2(s64)
+...
+---
+name:            atomicrmw_add_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_add_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            atomicrmw_sub_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_sub_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            atomicrmw_and_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_and_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[CST2:%[0-9]+]]:gpr32 = ORNWrr %wzr, [[CST]]
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDCLRAW [[CST2]], [[COPY]] :: (load store acquire 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            atomicrmw_or_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_or_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSETLW [[CST]], [[COPY]] :: (load store release 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            atomicrmw_xor_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_xor_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDEORALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            atomicrmw_min_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_min_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMINALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            atomicrmw_max_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_max_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMAXALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            atomicrmw_umin_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_umin_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMINALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            atomicrmw_umax_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: atomicrmw_umax_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMAXALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 1
+    %2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 8 on %ir.addr)
+    %w0 = COPY %2(s32)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/test/CodeGen/AArch64/GlobalISel/select-binop.mir
index 70cda516d5f1..1badcf35492d 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -58,28 +59,24 @@
 ---
 # Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.
 # Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: add_s32_gpr
 name:            add_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = ADDWrr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: add_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[ADDWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_ADD %0, %1
@@ -88,28 +85,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for 64-bit operations.
-# CHECK-LABEL: name: add_s64_gpr
 name:            add_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = ADDXrr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: add_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[ADDXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_ADD %0, %1
@@ -117,27 +110,23 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: add_imm_s32_gpr
 name:            add_imm_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32sp, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %2 = ADDWri %0, 1, 0
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: add_imm_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
+    ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
+    ; CHECK: %w0 = COPY [[ADDWri]]
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i32 1
     %2(s32) = G_ADD %0, %1
@@ -145,27 +134,23 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: add_imm_s64_gpr
 name:            add_imm_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64sp, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %2 = ADDXri %0, 1, 0
 body:             |
   bb.0:
     liveins: %x0, %w1
 
+    ; CHECK-LABEL: name: add_imm_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
+    ; CHECK: %x0 = COPY [[ADDXri]]
     %0(s64) = COPY %x0
     %1(s64) = G_CONSTANT i32 1
     %2(s64) = G_ADD %0, %1
@@ -173,25 +158,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: add_imm_s32_gpr_bb
 name:            add_imm_s32_gpr_bb
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32sp, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:  bb.1:
-# CHECK:    %2 = ADDWri %0, 1, 0
 body:             |
+  ; CHECK-LABEL: name: add_imm_s32_gpr_bb
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
+  ; CHECK:   %w0 = COPY [[ADDWri]]
   bb.0:
     liveins: %w0, %w1
     successors: %bb.1
@@ -207,28 +191,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for G_SUB operations.
-# CHECK-LABEL: name: sub_s32_gpr
 name:            sub_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = SUBSWrr %0, %1, implicit-def %nzcv
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: sub_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def %nzcv
+    ; CHECK: %w0 = COPY [[SUBSWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_SUB %0, %1
@@ -237,28 +217,24 @@ body:             |
 
 ---
 # Same as add_s64_gpr, for G_SUB operations.
-# CHECK-LABEL: name: sub_s64_gpr
 name:            sub_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = SUBSXrr %0, %1, implicit-def %nzcv
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: sub_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def %nzcv
+    ; CHECK: %x0 = COPY [[SUBSXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_SUB %0, %1
@@ -267,28 +243,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for G_OR operations.
-# CHECK-LABEL: name: or_s32_gpr
 name:            or_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = ORRWrr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: or_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[ORRWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_OR %0, %1
@@ -297,28 +269,24 @@ body:             |
 
 ---
 # Same as add_s64_gpr, for G_OR operations.
-# CHECK-LABEL: name: or_s64_gpr
 name:            or_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = ORRXrr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: or_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[ORRXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_OR %0, %1
@@ -327,30 +295,26 @@ body:             |
 
 ---
 # 64-bit G_OR on vector registers.
-# CHECK-LABEL: name: or_v2s32_fpr
 name:            or_v2s32_fpr
 legalized:       true
 regBankSelected: true
 #
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %d1
 # The actual OR does not matter as long as it is operating
 # on 64-bit width vector.
-# CHECK:    %2 = ORRv8i8 %0, %1
 body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: or_v2s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
+    ; CHECK: %d0 = COPY [[ORRv8i8_]]
       %0(<2 x s32>) = COPY %d0
       %1(<2 x s32>) = COPY %d1
       %2(<2 x s32>) = G_OR %0, %1
@@ -359,28 +323,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for G_AND operations.
-# CHECK-LABEL: name: and_s32_gpr
 name:            and_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = ANDWrr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: and_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[ANDWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_AND %0, %1
@@ -389,28 +349,24 @@ body:             |
 
 ---
 # Same as add_s64_gpr, for G_AND operations.
-# CHECK-LABEL: name: and_s64_gpr
 name:            and_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = ANDXrr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: and_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[ANDXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_AND %0, %1
@@ -419,28 +375,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for G_SHL operations.
-# CHECK-LABEL: name: shl_s32_gpr
 name:            shl_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = LSLVWr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: shl_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[LSLVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_SHL %0, %1
@@ -449,28 +401,24 @@ body:             |
 
 ---
 # Same as add_s64_gpr, for G_SHL operations.
-# CHECK-LABEL: name: shl_s64_gpr
 name:            shl_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = LSLVXr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: shl_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[LSLVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_SHL %0, %1
@@ -479,28 +427,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for G_LSHR operations.
-# CHECK-LABEL: name: lshr_s32_gpr
 name:            lshr_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = LSRVWr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: lshr_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[LSRVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_LSHR %0, %1
@@ -509,28 +453,24 @@ body:             |
 
 ---
 # Same as add_s64_gpr, for G_LSHR operations.
-# CHECK-LABEL: name: lshr_s64_gpr
 name:            lshr_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = LSRVXr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: lshr_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[LSRVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_LSHR %0, %1
@@ -539,28 +479,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for G_ASHR operations.
-# CHECK-LABEL: name: ashr_s32_gpr
 name:            ashr_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = ASRVWr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: ashr_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[ASRVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_ASHR %0, %1
@@ -569,28 +505,24 @@ body:             |
 
 ---
 # Same as add_s64_gpr, for G_ASHR operations.
-# CHECK-LABEL: name: ashr_s64_gpr
 name:            ashr_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = ASRVXr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: ashr_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[ASRVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_ASHR %0, %1
@@ -600,28 +532,24 @@ body:             |
 ---
 # Check that we select s32 GPR G_MUL. This is trickier than other binops because
 # there is only MADDWrrr, and we have to use the WZR physreg.
-# CHECK-LABEL: name: mul_s32_gpr
 name:            mul_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = MADDWrrr %0, %1, %wzr
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: mul_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], %wzr
+    ; CHECK: %w0 = COPY [[MADDWrrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_MUL %0, %1
@@ -630,28 +558,24 @@ body:             |
 
 ---
 # Same as mul_s32_gpr for the s64 type.
-# CHECK-LABEL: name: mul_s64_gpr
 name:            mul_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = MADDXrrr %0, %1, %xzr
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: mul_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], %xzr
+    ; CHECK: %x0 = COPY [[MADDXrrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_MUL %0, %1
@@ -660,26 +584,22 @@ body:             |
 
 ---
 # Same as mul_s32_gpr for the s64 type.
-# CHECK-LABEL: name: mulh_s64_gpr
 name:            mulh_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr64, preferred-register: '' }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = SMULHrr %0, %1
-# CHECK:    %3 = UMULHrr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: mulh_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]
+    ; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[SMULHrr]]
+    ; CHECK: %x0 = COPY [[UMULHrr]]
     %0:gpr(s64) = COPY %x0
     %1:gpr(s64) = COPY %x1
     %2:gpr(s64) = G_SMULH %0, %1
@@ -690,28 +610,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for G_SDIV operations.
-# CHECK-LABEL: name: sdiv_s32_gpr
 name:            sdiv_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = SDIVWr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: sdiv_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[SDIVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_SDIV %0, %1
@@ -720,28 +636,24 @@ body:             |
 
 ---
 # Same as add_s64_gpr, for G_SDIV operations.
-# CHECK-LABEL: name: sdiv_s64_gpr
 name:            sdiv_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = SDIVXr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: sdiv_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[SDIVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_SDIV %0, %1
@@ -750,28 +662,24 @@ body:             |
 
 ---
 # Same as add_s32_gpr, for G_UDIV operations.
-# CHECK-LABEL: name: udiv_s32_gpr
 name:            udiv_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = UDIVWr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: udiv_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[UDIVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_UDIV %0, %1
@@ -780,28 +688,24 @@ body:             |
 
 ---
 # Same as add_s64_gpr, for G_UDIV operations.
-# CHECK-LABEL: name: udiv_s64_gpr
 name:            udiv_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = UDIVXr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: udiv_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[UDIVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_UDIV %0, %1
@@ -810,28 +714,24 @@ body:             |
 
 ---
 # Check that we select a s32 FPR G_FADD into FADDSrr.
-# CHECK-LABEL: name: fadd_s32_fpr
 name:            fadd_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = COPY %s1
-# CHECK:    %2 = FADDSrr %0, %1
 body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: fadd_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[COPY1]]
+    ; CHECK: %s0 = COPY [[FADDSrr]]
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FADD %0, %1
@@ -839,28 +739,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: fadd_s64_fpr
 name:            fadd_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %d1
-# CHECK:    %2 = FADDDrr %0, %1
 body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: fadd_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[COPY1]]
+    ; CHECK: %d0 = COPY [[FADDDrr]]
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FADD %0, %1
@@ -868,28 +764,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: fsub_s32_fpr
 name:            fsub_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = COPY %s1
-# CHECK:    %2 = FSUBSrr %0, %1
 body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: fsub_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY]], [[COPY1]]
+    ; CHECK: %s0 = COPY [[FSUBSrr]]
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FSUB %0, %1
@@ -897,28 +789,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: fsub_s64_fpr
 name:            fsub_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %d1
-# CHECK:    %2 = FSUBDrr %0, %1
 body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: fsub_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY]], [[COPY1]]
+    ; CHECK: %d0 = COPY [[FSUBDrr]]
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FSUB %0, %1
@@ -926,28 +814,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: fmul_s32_fpr
 name:            fmul_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = COPY %s1
-# CHECK:    %2 = FMULSrr %0, %1
 body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: fmul_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY]], [[COPY1]]
+    ; CHECK: %s0 = COPY [[FMULSrr]]
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FMUL %0, %1
@@ -955,28 +839,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: fmul_s64_fpr
 name:            fmul_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %d1
-# CHECK:    %2 = FMULDrr %0, %1
 body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: fmul_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY]], [[COPY1]]
+    ; CHECK: %d0 = COPY [[FMULDrr]]
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FMUL %0, %1
@@ -984,28 +864,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: fdiv_s32_fpr
 name:            fdiv_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = COPY %s1
-# CHECK:    %2 = FDIVSrr %0, %1
 body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: fdiv_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY]], [[COPY1]]
+    ; CHECK: %s0 = COPY [[FDIVSrr]]
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FDIV %0, %1
@@ -1013,28 +889,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: fdiv_s64_fpr
 name:            fdiv_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %d1
-# CHECK:    %2 = FDIVDrr %0, %1
 body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: fdiv_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY]], [[COPY1]]
+    ; CHECK: %d0 = COPY [[FDIVDrr]]
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
     %2(s64) = G_FDIV %0, %1
diff --git a/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir b/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
new file mode 100644
index 000000000000..35d39c8c5d41
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
@@ -0,0 +1,19 @@
+# RUN: llc -O0 -mtriple=arm64eb-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+---
+name:            bitcast_v2f32_to_s64
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: bitcast_v2f32_to_s64
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; CHECK: [[REV:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY1]]
+    ; CHECK: %x0 = COPY [[REV]]
+    %0:fpr(<2 x s32>) = COPY %x0
+    %1:fpr(s64) = G_BITCAST %0
+    %x0 = COPY %1(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir b/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
index 5e4034d16242..e323aa310d5c 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -11,202 +12,224 @@
   define void @bitcast_s64_fpr() { ret void }
   define void @bitcast_s64_gpr_fpr() { ret void }
   define void @bitcast_s64_fpr_gpr() { ret void }
+  define void @bitcast_s64_v2f32_fpr() { ret void }
+  define void @bitcast_s64_v8i8_fpr() { ret void }
 ...
 
 ---
-# CHECK-LABEL: name: bitcast_s32_gpr
 name:            bitcast_s32_gpr
 legalized:       true
 regBankSelected: true
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: bitcast_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
+    ; CHECK: %w0 = COPY [[COPY1]]
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: bitcast_s32_fpr
 name:            bitcast_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %s0
 
+    ; CHECK-LABEL: name: bitcast_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
+    ; CHECK: %s0 = COPY [[COPY1]]
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
     %s0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: bitcast_s32_gpr_fpr
 name:            bitcast_s32_gpr_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: bitcast_s32_gpr_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
+    ; CHECK: %s0 = COPY [[COPY1]]
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
     %s0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: bitcast_s32_fpr_gpr
 name:            bitcast_s32_fpr_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %s0
 
+    ; CHECK-LABEL: name: bitcast_s32_fpr_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: %w0 = COPY [[COPY1]]
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: bitcast_s64_gpr
 name:            bitcast_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: bitcast_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
+    ; CHECK: %x0 = COPY [[COPY1]]
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: bitcast_s64_fpr
 name:            bitcast_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %d0
 
+    ; CHECK-LABEL: name: bitcast_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; CHECK: %d0 = COPY [[COPY1]]
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
     %d0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: bitcast_s64_gpr_fpr
 name:            bitcast_s64_gpr_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: bitcast_s64_gpr_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; CHECK: %d0 = COPY [[COPY1]]
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
     %d0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: bitcast_s64_fpr_gpr
 name:            bitcast_s64_fpr_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %d0
 
+    ; CHECK-LABEL: name: bitcast_s64_fpr_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; CHECK: %x0 = COPY [[COPY1]]
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
     %x0 = COPY %1(s64)
 ...
+
+---
+name:            bitcast_s64_v2f32_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %d0
+
+    ; CHECK-LABEL: name: bitcast_s64_v2f32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; CHECK: %x0 = COPY [[COPY1]]
+    %0(s64) = COPY %d0
+    %1(<2 x s32>) = G_BITCAST %0
+    %x0 = COPY %1(<2 x s32>)
+...
+
+---
+name:            bitcast_s64_v8i8_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %d0
+
+    ; CHECK-LABEL: name: bitcast_s64_v8i8_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; CHECK: %x0 = COPY [[COPY1]]
+    %0(s64) = COPY %d0
+    %1(<8 x s8>) = G_BITCAST %0
+    %x0 = COPY %1(<8 x s8>)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-br.mir b/test/CodeGen/AArch64/GlobalISel/select-br.mir
index f46f190260f6..0d6108fe322d 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-br.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-br.mir
@@ -33,6 +33,7 @@ regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:   bb.0:
@@ -41,7 +42,8 @@ registers:
 body:             |
   bb.0:
     successors: %bb.0, %bb.1
-    %0(s1) = COPY %w0
+    %1(s32) = COPY %w0
+    %0(s1) = G_TRUNC %1
     G_BRCOND %0(s1), %bb.1
     G_BR %bb.0
 
@@ -59,7 +61,7 @@ registers:
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %x0
+# CHECK:    %0:gpr64 = COPY %x0
 # CHECK:    BR %0
 body:             |
   bb.0:
diff --git a/test/CodeGen/AArch64/GlobalISel/select-bswap.mir b/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
new file mode 100644
index 000000000000..17394fe86d2c
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
@@ -0,0 +1,53 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @bswap_s32() { ret void }
+  define void @bswap_s64() { ret void }
+...
+
+---
+name:            bswap_s32
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+body:             |
+  bb.0:
+    liveins: %w0
+
+    ; CHECK-LABEL: name: bswap_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
+    ; CHECK: %w0 = COPY [[REVWr]]
+    %0(s32) = COPY %w0
+    %1(s32) = G_BSWAP %0
+    %w0 = COPY %1
+...
+
+---
+name:            bswap_s64
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: bswap_s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
+    ; CHECK: %x0 = COPY [[REVXr]]
+    %0(s64) = COPY %x0
+    %1(s64) = G_BSWAP %0
+    %x0 = COPY %1
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-cbz.mir b/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
index 2decb994b967..f8f0126bdc3d 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
@@ -15,7 +15,7 @@ regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %0:gpr32 = COPY %w0
 # CHECK:    CBZW %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
@@ -25,8 +25,9 @@ body:             |
 
     %0:gpr(s32) = COPY %w0
     %1:gpr(s32) = G_CONSTANT i32 0
-    %2:gpr(s1) = G_ICMP intpred(eq), %0, %1
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
+    %3:gpr(s1) = G_TRUNC %2(s32)
+    G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
@@ -40,7 +41,7 @@ regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %x0
+# CHECK:    %0:gpr64 = COPY %x0
 # CHECK:    CBZX %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
@@ -50,8 +51,9 @@ body:             |
 
     %0:gpr(s64) = COPY %x0
     %1:gpr(s64) = G_CONSTANT i64 0
-    %2:gpr(s1) = G_ICMP intpred(eq), %0, %1
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
+    %3:gpr(s1) = G_TRUNC %2(s32)
+    G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
@@ -65,7 +67,7 @@ regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %0:gpr32 = COPY %w0
 # CHECK:    CBNZW %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
@@ -75,8 +77,9 @@ body:             |
 
     %0:gpr(s32) = COPY %w0
     %1:gpr(s32) = G_CONSTANT i32 0
-    %2:gpr(s1) = G_ICMP intpred(ne), %0, %1
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
+    %3:gpr(s1) = G_TRUNC %2(s32)
+    G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
@@ -90,7 +93,7 @@ regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %x0
+# CHECK:    %0:gpr64 = COPY %x0
 # CHECK:    CBNZX %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
@@ -100,8 +103,9 @@ body:             |
 
     %0:gpr(s64) = COPY %x0
     %1:gpr(s64) = G_CONSTANT i64 0
-    %2:gpr(s1) = G_ICMP intpred(ne), %0, %1
-    G_BRCOND %2(s1), %bb.1
+    %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
+    %3:gpr(s1) = G_TRUNC %2(s32)
+    G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
diff --git a/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir b/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
new file mode 100644
index 000000000000..67ce28ba8590
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
@@ -0,0 +1,53 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @cmpxchg_i32(i64* %addr) { ret void }
+  define void @cmpxchg_i64(i64* %addr) { ret void }
+...
+
+---
+name:            cmpxchg_i32
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CMP:%[0-9]+]]:gpr32 = MOVi32imm 0
+    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr32 = CASW [[CMP]], [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
+    ; CHECK: %w0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s32) = G_CONSTANT i32 0
+    %2:gpr(s32) = G_CONSTANT i32 1
+    %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
+    %w0 = COPY %3(s32)
+...
+
+---
+name:            cmpxchg_i64
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: cmpxchg_i64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[CMP:%[0-9]+]]:gpr64 = MOVi64imm 0
+    ; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
+    ; CHECK: [[RES:%[0-9]+]]:gpr64 = CASX [[CMP]], [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
+    ; CHECK: %x0 = COPY [[RES]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s64) = G_CONSTANT i64 0
+    %2:gpr(s64) = G_CONSTANT i64 1
+    %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
+    %x0 = COPY %3(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index 1a5bac9fb7d6..fbe2ef1f2c8a 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -8,70 +9,104 @@
 
   define i32 @fconst_s32() { ret i32 42 }
   define i64 @fconst_s64() { ret i64 1234567890123 }
+  define float @fconst_s32_0() { ret float 0.0 }
+  define double @fconst_s64_0() { ret double 0.0 }
 ...
 
 ---
-# CHECK-LABEL: name: const_s32
 name:            const_s32
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = MOVi32imm 42
 body:             |
   bb.0:
+    ; CHECK-LABEL: name: const_s32
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+    ; CHECK: %w0 = COPY [[MOVi32imm]]
     %0(s32) = G_CONSTANT i32 42
     %w0 = COPY %0(s32)
 ...
 
 ---
-# CHECK-LABEL: name: const_s64
 name:            const_s64
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = MOVi64imm 1234567890123
 body:             |
   bb.0:
+    ; CHECK-LABEL: name: const_s64
+    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234567890123
+    ; CHECK: %x0 = COPY [[MOVi64imm]]
     %0(s64) = G_CONSTANT i64 1234567890123
     %x0 = COPY %0(s64)
 ...
 
 ---
-# CHECK-LABEL: name: fconst_s32
 name:            fconst_s32
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: fpr }
 
-# CHECK:  body:
-# CHECK: [[TMP:%[0-9]+]] = MOVi32imm 1080033280
-# CHECK: %0 = COPY [[TMP]]
 body:             |
   bb.0:
+    ; CHECK-LABEL: name: fconst_s32
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1080033280
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
+    ; CHECK: %s0 = COPY [[COPY]]
     %0(s32) = G_FCONSTANT float 3.5
     %s0 = COPY %0(s32)
 ...
 
 ---
-# CHECK-LABEL: name: fconst_s64
 name:            fconst_s64
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: fpr }
 
-# CHECK:  body:
-# CHECK: [[TMP:%[0-9]+]] = MOVi64imm 4607182418800017408
-# CHECK: %0 = COPY [[TMP]]
 body:             |
   bb.0:
+    ; CHECK-LABEL: name: fconst_s64
+    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 4607182418800017408
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVi64imm]]
+    ; CHECK: %d0 = COPY [[COPY]]
     %0(s64) = G_FCONSTANT double 1.0
     %d0 = COPY %0(s64)
 ...
+
+---
+name:            fconst_s32_0
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: fpr }
+
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: fconst_s32_0
+    ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+    ; CHECK: %s0 = COPY [[FMOVS0_]]
+    %0(s32) = G_FCONSTANT float 0.0
+    %s0 = COPY %0(s32)
+...
+
+---
+name:            fconst_s64_0
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: fpr }
+
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: fconst_s64_0
+    ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
+    ; CHECK: %x0 = COPY [[FMOVD0_]]
+    %0(s64) = G_FCONSTANT double 0.0
+    %x0 = COPY %0(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir b/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
index 790cd6517dd3..7396ae57f8fd 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple arm64-- -run-pass=instruction-select -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -5,12 +6,12 @@
 
   define void @test_dbg_value(i32 %a) !dbg !5 {
     %tmp0 = add i32 %a, %a
-    call void @llvm.dbg.value(metadata i32 %tmp0, i64 0, metadata !7, metadata !9), !dbg !10
+    call void @llvm.dbg.value(metadata i32 %tmp0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
     ret void
   }
 
-  define void @test_dbg_value_dead(i32 %a) !dbg !11 {
-    call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !12, metadata !9), !dbg !13
+  define void @test_dbg_value_dead(i32 %a) !dbg !10 {
+    call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !11, metadata !DIExpression()), !dbg !12
     ret void
   }
 
@@ -28,45 +29,40 @@
   !6 = !DISubroutineType(types: !2)
   !7 = !DILocalVariable(name: "in", arg: 1, scope: !5, file: !1, line: 1, type: !8)
   !8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
-  !9 = !DIExpression()
-  !10 = !DILocation(line: 1, column: 1, scope: !5)
-  !11 = distinct !DISubprogram(name: "test_dbg_value", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
-  !12 = !DILocalVariable(name: "in", arg: 1, scope: !11, file: !1, line: 1, type: !8)
-  !13 = !DILocation(line: 1, column: 1, scope: !11)
+  !9 = !DILocation(line: 1, column: 1, scope: !5)
+  !10 = distinct !DISubprogram(name: "test_dbg_value", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+  !11 = !DILocalVariable(name: "in", arg: 1, scope: !10, file: !1, line: 1, type: !8)
+  !12 = !DILocation(line: 1, column: 1, scope: !10)
 ...
 
 ---
-# CHECK-LABEL: name: test_dbg_value
 name:            test_dbg_value
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: %w0
+    ; CHECK-LABEL: name: test_dbg_value
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]]
+    ; CHECK: %w0 = COPY [[ADDWrr]]
+    ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use %noreg, !7, !DIExpression(), debug-location !9
     %0:gpr(s32) = COPY %w0
     %1:gpr(s32) = G_ADD %0, %0
     %w0 = COPY %1(s32)
-
-    ; CHECK:      %0 = COPY %w0
-    ; CHECK-NEXT: %1 = ADDWrr %0, %0
-    ; CHECK-NEXT: %w0 = COPY %1
-    ; CHECK-NEXT: DBG_VALUE debug-use %1, debug-use _, !7, !9, debug-location !10
-
-    DBG_VALUE debug-use %1(s32), debug-use _, !7, !9, debug-location !10
+    DBG_VALUE debug-use %1(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
 ...
 
 ---
-# CHECK-LABEL: name: test_dbg_value_dead
 name:            test_dbg_value_dead
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: %w0
-    %0:gpr(s32) = COPY %w0
-
+    ; CHECK-LABEL: name: test_dbg_value_dead
     ; CHECK-NOT: COPY
-    ; CHECK: DBG_VALUE debug-use _, debug-use _, !7, !9, debug-location !10
-
-    DBG_VALUE debug-use %0(s32), debug-use _, !7, !9, debug-location !10
+    ; CHECK: DBG_VALUE debug-use %noreg, debug-use %noreg, !7, !DIExpression(), debug-location !9
+    %0:gpr(s32) = COPY %w0
+    DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-fma.mir b/test/CodeGen/AArch64/GlobalISel/select-fma.mir
index 3b2f3746b587..3e8743c3ce80 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-fma.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-fma.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -7,35 +8,29 @@
 ...
 
 ---
-# CHECK-LABEL: name: FMADDSrrr_fpr
 name:            FMADDSrrr_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
   - { id: 2, class: fpr }
   - { id: 3, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = COPY %w2
-# CHECK:    %3 = FMADDSrrr %0, %1, %2
 body:             |
   bb.0:
     liveins: %w0, %w1, %w2
 
+    ; CHECK-LABEL: name: FMADDSrrr_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY %w2
+    ; CHECK: [[FMADDSrrr:%[0-9]+]]:fpr32 = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: %w0 = COPY [[FMADDSrrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = COPY %w2
     %3(s32) = G_FMA %0, %1, %2
-    %x0 = COPY %3
+    %w0 = COPY %3
 ...
-
diff --git a/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
index 34c3da3a5369..a163ba1db328 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
@@ -1,10 +1,16 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
-  define void @fptrunc() { ret void }
-  define void @fpext() { ret void }
+  define void @fptrunc_s16_s32_fpr() { ret void }
+  define void @fptrunc_s16_s64_fpr() { ret void }
+  define void @fptrunc_s32_s64_fpr() { ret void }
+
+  define void @fpext_s32_s16_fpr() { ret void }
+  define void @fpext_s64_s16_fpr() { ret void }
+  define void @fpext_s64_s32_fpr() { ret void }
 
   define void @sitofp_s32_s32_fpr() { ret void }
   define void @sitofp_s32_s64_fpr() { ret void }
@@ -28,450 +34,484 @@
 ...
 
 ---
-# CHECK-LABEL: name: fptrunc
-name:            fptrunc
+name:            fptrunc_s16_s32_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %s0
+
+    ; CHECK-LABEL: name: fptrunc_s16_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+    ; CHECK: %h0 = COPY [[FCVTHSr]]
+    %0(s32) = COPY %s0
+    %1(s16) = G_FPTRUNC %0
+    %h0 = COPY %1(s16)
+...
+
+---
+name:            fptrunc_s16_s64_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %d0
+
+    ; CHECK-LABEL: name: fptrunc_s16_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
+    ; CHECK: %h0 = COPY [[FCVTHDr]]
+    %0(s64) = COPY %d0
+    %1(s16) = G_FPTRUNC %0
+    %h0 = COPY %1(s16)
+...
+
+---
+name:            fptrunc_s32_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK: - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK: - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = FCVTSDr %0
 body:             |
   bb.0:
     liveins: %d0
 
+    ; CHECK-LABEL: name: fptrunc_s32_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = FCVTSDr [[COPY]]
+    ; CHECK: %s0 = COPY [[FCVTSDr]]
     %0(s64) = COPY %d0
     %1(s32) = G_FPTRUNC %0
     %s0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: fpext
-name:            fpext
+name:            fpext_s32_s16_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %h0
+
+    ; CHECK-LABEL: name: fpext_s32_s16_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
+    ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
+    ; CHECK: %s0 = COPY [[FCVTSHr]]
+    %0(s16) = COPY %h0
+    %1(s32) = G_FPEXT %0
+    %s0 = COPY %1(s32)
+...
+
+---
+name:            fpext_s64_s16_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %h0
+
+    ; CHECK-LABEL: name: fpext_s64_s16_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
+    ; CHECK: [[FCVTDHr:%[0-9]+]]:fpr64 = FCVTDHr [[COPY]]
+    ; CHECK: %d0 = COPY [[FCVTDHr]]
+    %0(s16) = COPY %h0
+    %1(s64) = G_FPEXT %0
+    %d0 = COPY %1(s64)
+...
+
+---
+name:            fpext_s64_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK: - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK: - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = FCVTDSr %0
 body:             |
   bb.0:
     liveins: %d0
 
+    ; CHECK-LABEL: name: fpext_s64_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = FCVTDSr [[COPY]]
+    ; CHECK: %d0 = COPY [[FCVTDSr]]
     %0(s32) = COPY %s0
     %1(s64) = G_FPEXT %0
     %d0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: sitofp_s32_s32_fpr
 name:            sitofp_s32_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = SCVTFUWSri %0
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: sitofp_s32_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = SCVTFUWSri [[COPY]]
+    ; CHECK: %s0 = COPY [[SCVTFUWSri]]
     %0(s32) = COPY %w0
     %1(s32) = G_SITOFP %0
     %s0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: sitofp_s32_s64_fpr
 name:            sitofp_s32_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = SCVTFUXSri %0
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: sitofp_s32_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[SCVTFUXSri:%[0-9]+]]:fpr32 = SCVTFUXSri [[COPY]]
+    ; CHECK: %s0 = COPY [[SCVTFUXSri]]
     %0(s64) = COPY %x0
     %1(s32) = G_SITOFP %0
     %s0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: sitofp_s64_s32_fpr
 name:            sitofp_s64_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = SCVTFUWDri %0
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: sitofp_s64_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY]]
+    ; CHECK: %d0 = COPY [[SCVTFUWDri]]
     %0(s32) = COPY %w0
     %1(s64) = G_SITOFP %0
     %d0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: sitofp_s64_s64_fpr
 name:            sitofp_s64_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = SCVTFUXDri %0
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: sitofp_s64_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[COPY]]
+    ; CHECK: %d0 = COPY [[SCVTFUXDri]]
     %0(s64) = COPY %x0
     %1(s64) = G_SITOFP %0
     %d0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: uitofp_s32_s32_fpr
 name:            uitofp_s32_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = UCVTFUWSri %0
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: uitofp_s32_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[UCVTFUWSri:%[0-9]+]]:fpr32 = UCVTFUWSri [[COPY]]
+    ; CHECK: %s0 = COPY [[UCVTFUWSri]]
     %0(s32) = COPY %w0
     %1(s32) = G_UITOFP %0
     %s0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: uitofp_s32_s64_fpr
 name:            uitofp_s32_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = UCVTFUXSri %0
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: uitofp_s32_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[UCVTFUXSri:%[0-9]+]]:fpr32 = UCVTFUXSri [[COPY]]
+    ; CHECK: %s0 = COPY [[UCVTFUXSri]]
     %0(s64) = COPY %x0
     %1(s32) = G_UITOFP %0
     %s0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: uitofp_s64_s32_fpr
 name:            uitofp_s64_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = UCVTFUWDri %0
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: uitofp_s64_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[UCVTFUWDri:%[0-9]+]]:fpr64 = UCVTFUWDri [[COPY]]
+    ; CHECK: %d0 = COPY [[UCVTFUWDri]]
     %0(s32) = COPY %w0
     %1(s64) = G_UITOFP %0
     %d0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: uitofp_s64_s64_fpr
 name:            uitofp_s64_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = UCVTFUXDri %0
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: uitofp_s64_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[UCVTFUXDri:%[0-9]+]]:fpr64 = UCVTFUXDri [[COPY]]
+    ; CHECK: %d0 = COPY [[UCVTFUXDri]]
     %0(s64) = COPY %x0
     %1(s64) = G_UITOFP %0
     %d0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: fptosi_s32_s32_gpr
 name:            fptosi_s32_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = FCVTZSUWSr %0
 body:             |
   bb.0:
     liveins: %s0
 
+    ; CHECK-LABEL: name: fptosi_s32_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = FCVTZSUWSr [[COPY]]
+    ; CHECK: %w0 = COPY [[FCVTZSUWSr]]
     %0(s32) = COPY %s0
     %1(s32) = G_FPTOSI %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: fptosi_s32_s64_gpr
 name:            fptosi_s32_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = FCVTZSUWDr %0
 body:             |
   bb.0:
     liveins: %d0
 
+    ; CHECK-LABEL: name: fptosi_s32_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = FCVTZSUWDr [[COPY]]
+    ; CHECK: %w0 = COPY [[FCVTZSUWDr]]
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOSI %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: fptosi_s64_s32_gpr
 name:            fptosi_s64_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = FCVTZSUXSr %0
 body:             |
   bb.0:
     liveins: %s0
 
+    ; CHECK-LABEL: name: fptosi_s64_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = FCVTZSUXSr [[COPY]]
+    ; CHECK: %x0 = COPY [[FCVTZSUXSr]]
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOSI %0
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: fptosi_s64_s64_gpr
 name:            fptosi_s64_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = FCVTZSUXDr %0
 body:             |
   bb.0:
     liveins: %d0
 
+    ; CHECK-LABEL: name: fptosi_s64_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = FCVTZSUXDr [[COPY]]
+    ; CHECK: %x0 = COPY [[FCVTZSUXDr]]
     %0(s64) = COPY %d0
     %1(s64) = G_FPTOSI %0
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: fptoui_s32_s32_gpr
 name:            fptoui_s32_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = FCVTZUUWSr %0
 body:             |
   bb.0:
     liveins: %s0
 
+    ; CHECK-LABEL: name: fptoui_s32_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = FCVTZUUWSr [[COPY]]
+    ; CHECK: %w0 = COPY [[FCVTZUUWSr]]
     %0(s32) = COPY %s0
     %1(s32) = G_FPTOUI %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: fptoui_s32_s64_gpr
 name:            fptoui_s32_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = FCVTZUUWDr %0
 body:             |
   bb.0:
     liveins: %d0
 
+    ; CHECK-LABEL: name: fptoui_s32_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = FCVTZUUWDr [[COPY]]
+    ; CHECK: %w0 = COPY [[FCVTZUUWDr]]
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOUI %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: fptoui_s64_s32_gpr
 name:            fptoui_s64_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = FCVTZUUXSr %0
 body:             |
   bb.0:
     liveins: %s0
 
+    ; CHECK-LABEL: name: fptoui_s64_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = FCVTZUUXSr [[COPY]]
+    ; CHECK: %x0 = COPY [[FCVTZUUXSr]]
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOUI %0
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: fptoui_s64_s64_gpr
 name:            fptoui_s64_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = FCVTZUUXDr %0
 body:             |
   bb.0:
     liveins: %d0
 
+    ; CHECK-LABEL: name: fptoui_s64_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = FCVTZUUXDr [[COPY]]
+    ; CHECK: %x0 = COPY [[FCVTZUUXDr]]
     %0(s64) = COPY %d0
     %1(s64) = G_FPTOUI %0
     %x0 = COPY %1(s64)
diff --git a/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/test/CodeGen/AArch64/GlobalISel/select-imm.mir
new file mode 100644
index 000000000000..28fb4b396531
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-imm.mir
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @imm_s32_gpr() { ret void }
+  define void @imm_s64_gpr() { ret void }
+
+...
+
+---
+# Check that we select a 32-bit immediate into a MOVi32imm.
+name:            imm_s32_gpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: gpr }
+
+body:             |
+  bb.0:
+    liveins: %w0, %w1
+
+    ; CHECK-LABEL: name: imm_s32_gpr
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1234
+    ; CHECK: %w0 = COPY [[MOVi32imm]]
+    %0(s32) = G_CONSTANT i32 -1234
+    %w0 = COPY %0(s32)
+...
+
+---
+# Check that we select a 64-bit immediate into a MOVi64imm.
+name:            imm_s64_gpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: gpr }
+
+body:             |
+  bb.0:
+    liveins: %w0, %w1
+
+    ; CHECK-LABEL: name: imm_s64_gpr
+    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234
+    ; CHECK: %x0 = COPY [[MOVi64imm]]
+    %0(s64) = G_CONSTANT i64 1234
+    %x0 = COPY %0(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir b/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
index 8604b2769ba3..7b65fe3bf7dc 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -7,23 +8,19 @@
 ...
 
 ---
-# CHECK-LABEL: name: implicit_def
 name:            implicit_def
 legalized:       true
 regBankSelected: true
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    [[DEF:%[0-9]+]] = IMPLICIT_DEF
-# CHECK:    [[ADD:%[0-9]+]] = ADDWrr [[DEF]], [[DEF]]
-# CHECK:    %w0 = COPY [[ADD]]
 body:             |
   bb.0:
+    ; CHECK-LABEL: name: implicit_def
+    ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[DEF]], [[DEF]]
+    ; CHECK: %w0 = COPY [[ADDWrr]]
     %0(s32) = G_IMPLICIT_DEF
     %1(s32) = G_ADD %0, %0
     %w0 = COPY %1(s32)
diff --git a/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir b/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
new file mode 100644
index 000000000000..33b483511065
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
@@ -0,0 +1,54 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+---
+# CHECK-LABEL: name: insert_gprs
+name:            insert_gprs
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    %0:gpr(s32) = COPY %w0
+
+    %1:gpr(s64) = G_IMPLICIT_DEF
+
+    ; CHECK:  body:
+    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
+    ; CHECK: %2:gpr64 = BFMXri %1, [[TMP]], 0, 31
+    %2:gpr(s64) = G_INSERT %1, %0, 0
+
+    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
+    ; CHECK: %3:gpr64 = BFMXri %1, [[TMP]], 51, 31
+    %3:gpr(s64) = G_INSERT %1, %0, 13
+
+    %x0 = COPY %2
+    %x1 = COPY %3
+...
+
+
+---
+# CHECK-LABEL: name: extract_gprs
+name:            extract_gprs
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    %0:gpr(s64) = COPY %x0
+
+    ; CHECK:  body:
+    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 0, 31
+    ; CHECK: %1:gpr32 = COPY [[TMP]].sub_32
+    %1:gpr(s32) = G_EXTRACT %0, 0
+
+    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 13, 44
+    ; CHECK: %2:gpr32 = COPY [[TMP]].sub_32
+    %2:gpr(s32) = G_EXTRACT %0, 13
+
+    %w0 = COPY %1
+    %w1 = COPY %2
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
index 5f29f8b62fab..bd75c4e661ea 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -18,257 +19,242 @@
 ...
 
 ---
-# CHECK-LABEL: name: anyext_s64_from_s32
 name:            anyext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64all, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
-# CHECK:    %1 = COPY %2
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: anyext_s64_from_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[SUBREG_TO_REG]]
+    ; CHECK: %x0 = COPY [[COPY1]]
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: anyext_s32_from_s8
 name:            anyext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    ; CHECK-LABEL: name: anyext_s32_from_s8
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[COPY2]]
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s32) = G_ANYEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: zext_s64_from_s32
 name:            zext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
-# CHECK:    %1 = UBFMXri %2, 0, 31
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: zext_s64_from_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; CHECK: %x0 = COPY [[UBFMXri]]
     %0(s32) = COPY %w0
     %1(s64) = G_ZEXT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: zext_s32_from_s16
 name:            zext_s32_from_s16
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = UBFMWri %0, 0, 15
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s16) = COPY %w0
+    ; CHECK-LABEL: name: zext_s32_from_s16
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15
+    ; CHECK: %w0 = COPY [[UBFMWri]]
+    %2:gpr(s32) = COPY %w0
+    %0(s16) = G_TRUNC %2
     %1(s32) = G_ZEXT %0
     %w0 = COPY %1
 ...
 
 ---
-# CHECK-LABEL: name: zext_s32_from_s8
 name:            zext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = UBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    ; CHECK-LABEL: name: zext_s32_from_s8
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15
+    ; CHECK: %w0 = COPY [[UBFMWri]]
+    %2:gpr(s32) = COPY %w0
+    %0(s16) = G_TRUNC %2
     %1(s32) = G_ZEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: zext_s16_from_s8
 name:            zext_s16_from_s8
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = UBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    ; CHECK-LABEL: name: zext_s16_from_s8
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
+    ; CHECK: %w0 = COPY [[COPY2]]
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s16) = G_ZEXT %0
-    %w0 = COPY %1(s16)
+    %3:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %3(s32)
 ...
 
 ---
-# CHECK-LABEL: name: sext_s64_from_s32
 name:            sext_s64_from_s32
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
-# CHECK:    %1 = SBFMXri %2, 0, 31
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: sext_s64_from_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
+    ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; CHECK: %x0 = COPY [[SBFMXri]]
     %0(s32) = COPY %w0
     %1(s64) = G_SEXT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: sext_s32_from_s16
 name:            sext_s32_from_s16
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = SBFMWri %0, 0, 15
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s16) = COPY %w0
+    ; CHECK-LABEL: name: sext_s32_from_s16
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 15
+    ; CHECK: %w0 = COPY [[SBFMWri]]
+    %2:gpr(s32) = COPY %w0
+    %0(s16) = G_TRUNC %2
     %1(s32) = G_SEXT %0
     %w0 = COPY %1
 ...
 
 ---
-# CHECK-LABEL: name: sext_s32_from_s8
 name:            sext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = SBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    ; CHECK-LABEL: name: sext_s32_from_s8
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7
+    ; CHECK: %w0 = COPY [[SBFMWri]]
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s32) = G_SEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: sext_s16_from_s8
 name:            sext_s16_from_s8
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = SBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    ; CHECK-LABEL: name: sext_s16_from_s8
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
+    ; CHECK: %w0 = COPY [[COPY2]]
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s16) = G_SEXT %0
-    %w0 = COPY %1(s16)
+    %3:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %3(s32)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
index b71a9a3d731e..405634a00aa7 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -12,139 +13,127 @@
 ...
 
 ---
-# CHECK-LABEL: name: inttoptr_p0_s64
 name:            inttoptr_p0_s64
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %x0
+    ; CHECK-LABEL: name: inttoptr_p0_s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
+    ; CHECK: %x0 = COPY [[COPY1]]
     %0(s64) = COPY %x0
     %1(p0) = G_INTTOPTR %0
     %x0 = COPY %1(p0)
 ...
 
 ---
-# CHECK-LABEL: name: ptrtoint_s64_p0
 name:            ptrtoint_s64_p0
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %x0
+    ; CHECK-LABEL: name: ptrtoint_s64_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; CHECK: %x0 = COPY [[COPY1]]
     %0(p0) = COPY %x0
     %1(s64) = G_PTRTOINT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: ptrtoint_s32_p0
 name:            ptrtoint_s32_p0
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
+    ; CHECK-LABEL: name: ptrtoint_s32_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: %w0 = COPY [[COPY1]]
     %0(p0) = COPY %x0
     %1(s32) = G_PTRTOINT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: ptrtoint_s16_p0
 name:            ptrtoint_s16_p0
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
+    ; CHECK-LABEL: name: ptrtoint_s16_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[COPY2]]
     %0(p0) = COPY %x0
     %1(s16) = G_PTRTOINT %0
-    %w0 = COPY %1(s16)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
-# CHECK-LABEL: name: ptrtoint_s8_p0
 name:            ptrtoint_s8_p0
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
+    ; CHECK-LABEL: name: ptrtoint_s8_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[COPY2]]
     %0(p0) = COPY %x0
     %1(s8) = G_PTRTOINT %0
-    %w0 = COPY %1(s8)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
-# CHECK-LABEL: name: ptrtoint_s1_p0
 name:            ptrtoint_s1_p0
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
+    ; CHECK-LABEL: name: ptrtoint_s1_p0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[COPY2]]
     %0(p0) = COPY %x0
     %1(s1) = G_PTRTOINT %0
-    %w0 = COPY %1(s1)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir b/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
new file mode 100644
index 000000000000..61eff7c02bfe
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
@@ -0,0 +1,29 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @hint() { ret void }
+...
+
+---
+# Check that we select a 'hint' intrinsic into a HINT instruction.
+# CHECK-LABEL: name: hint
+name:            hint
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+
+# CHECK:  body:
+# CHECK:    HINT 1
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s32) = G_CONSTANT i32 1
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.hint), %0
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir b/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
index 43e682c6b6ca..0387d7ab8ba4 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -9,28 +10,24 @@
 ---
 # Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.
 # Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: sdiv_s32_gpr
 name:            sdiv_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = SDIVWr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: sdiv_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[SDIVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
diff --git a/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir b/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
new file mode 100644
index 000000000000..fe457b8bffca
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+fuse-aes -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+---
+# Check that we select the aarch64_crypto_aesmc and aarch64_crypto_aese
+# intrinsics into an ARSMCrrTied and AESErr instruction sequence.
+name:            aesmc_aese
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %q0, %q1
+
+    ; CHECK-LABEL: name: aesmc_aese
+    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY %q0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY %q1
+    ; CHECK: [[T0:%[0-9]+]]:fpr128 = AESErr [[COPY]], [[COPY1]]
+    ; CHECK: [[T1:%[0-9]+]]:fpr128 = AESMCrrTied [[T0]]
+    ; CHECK: %q0 = COPY [[T1]]
+    %0:fpr(<16 x s8>) = COPY %q0
+    %1:fpr(<16 x s8>) = COPY %q1
+    %2:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %0, %1
+    %3:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %2
+    %q0 = COPY %3(<16 x s8>)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-load.mir b/test/CodeGen/AArch64/GlobalISel/select-load.mir
index d00b98d148be..5c030f931dde 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-load.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-load.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -28,117 +29,108 @@
   define void @load_gep_64_s16_fpr(i16* %addr) { ret void }
   define void @load_gep_32_s8_fpr(i8* %addr) { ret void }
 
+  define void @load_v2s32(i64 *%addr) { ret void }
+
+  define void @sextload_s32_from_s16(i16 *%addr) { ret void }
+  define void @zextload_s32_from_s16(i16 *%addr) { ret void }
+  define void @aextload_s32_from_s16(i16 *%addr) { ret void }
 ...
 
 ---
-# CHECK-LABEL: name: load_s64_gpr
 name:            load_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRXui %0, 0 :: (load 8 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr)
+    ; CHECK: %x0 = COPY [[LDRXui]]
     %0(p0) = COPY %x0
     %1(s64) = G_LOAD  %0 :: (load 8 from %ir.addr)
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: load_s32_gpr
 name:            load_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRWui %0, 0 :: (load 4 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr)
+    ; CHECK: %w0 = COPY [[LDRWui]]
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD  %0 :: (load 4 from %ir.addr)
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: load_s16_gpr
 name:            load_s16_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRHHui %0, 0 :: (load 2 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_s16_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
+    ; CHECK: %w0 = COPY [[LDRHHui]]
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
-    %w0 = COPY %1(s16)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
-# CHECK-LABEL: name: load_s8_gpr
 name:            load_s8_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRBBui %0, 0 :: (load 1 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_s8_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
+    ; CHECK: %w0 = COPY [[LDRBBui]]
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
-    %w0 = COPY %1(s8)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
-# CHECK-LABEL: name: load_fi_s64_gpr
 name:            load_fi_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
@@ -146,43 +138,37 @@ registers:
 stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 
-# CHECK:  body:
-# CHECK: %1 = LDRXui %stack.0.ptr0, 0 :: (load 8)
-# CHECK: %x0 = COPY %1
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_fi_s64_gpr
+    ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load 8)
+    ; CHECK: %x0 = COPY [[LDRXui]]
     %0(p0) = G_FRAME_INDEX %stack.0.ptr0
     %1(s64) = G_LOAD %0 :: (load 8)
     %x0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: load_gep_128_s64_gpr
 name:            load_gep_128_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %3 = LDRXui %0, 16 :: (load 8 from %ir.addr)
-# CHECK: %x0 = COPY %3
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_gep_128_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load 8 from %ir.addr)
+    ; CHECK: %x0 = COPY [[LDRXui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 128
     %2(p0) = G_GEP %0, %1
@@ -191,30 +177,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: load_gep_512_s32_gpr
 name:            load_gep_512_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %3 = LDRWui %0, 128 :: (load 4 from %ir.addr)
-# CHECK: %w0 = COPY %3
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_gep_512_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load 4 from %ir.addr)
+    ; CHECK: %w0 = COPY [[LDRWui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 512
     %2(p0) = G_GEP %0, %1
@@ -223,194 +203,166 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: load_gep_64_s16_gpr
 name:            load_gep_64_s16_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %3 = LDRHHui %0, 32 :: (load 2 from %ir.addr)
-# CHECK: %w0 = COPY %3
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_gep_64_s16_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr)
+    ; CHECK: %w0 = COPY [[LDRHHui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 64
     %2(p0) = G_GEP %0, %1
     %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr)
-    %w0 = COPY %3
+    %4:gpr(s32) = G_ANYEXT %3
+    %w0 = COPY %4
 ...
 
 ---
-# CHECK-LABEL: name: load_gep_1_s8_gpr
 name:            load_gep_1_s8_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %3 = LDRBBui %0, 1 :: (load 1 from %ir.addr)
-# CHECK: %w0 = COPY %3
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_gep_1_s8_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr)
+    ; CHECK: %w0 = COPY [[LDRBBui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 1
     %2(p0) = G_GEP %0, %1
     %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr)
-    %w0 = COPY %3
+    %4:gpr(s32) = G_ANYEXT %3
+    %w0 = COPY %4
 ...
 
 ---
-# CHECK-LABEL: name: load_s64_fpr
 name:            load_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
+    ; CHECK: %d0 = COPY [[LDRDui]]
     %0(p0) = COPY %x0
     %1(s64) = G_LOAD  %0 :: (load 8 from %ir.addr)
     %d0 = COPY %1(s64)
 ...
 
 ---
-# CHECK-LABEL: name: load_s32_fpr
 name:            load_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRSui %0, 0 :: (load 4 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load 4 from %ir.addr)
+    ; CHECK: %s0 = COPY [[LDRSui]]
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD  %0 :: (load 4 from %ir.addr)
     %s0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: load_s16_fpr
 name:            load_s16_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRHui %0, 0 :: (load 2 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_s16_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr)
+    ; CHECK: %h0 = COPY [[LDRHui]]
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
     %h0 = COPY %1(s16)
 ...
 
 ---
-# CHECK-LABEL: name: load_s8_fpr
 name:            load_s8_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = LDRBui %0, 0 :: (load 1 from %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_s8_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1 from %ir.addr)
+    ; CHECK: %b0 = COPY [[LDRBui]]
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
     %b0 = COPY %1(s8)
 ...
 
 ---
-# CHECK-LABEL: name: load_gep_8_s64_fpr
 name:            load_gep_8_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %3 = LDRDui %0, 1 :: (load 8 from %ir.addr)
-# CHECK: %d0 = COPY %3
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_gep_8_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load 8 from %ir.addr)
+    ; CHECK: %d0 = COPY [[LDRDui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 8
     %2(p0) = G_GEP %0, %1
@@ -419,30 +371,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: load_gep_16_s32_fpr
 name:            load_gep_16_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %3 = LDRSui %0, 4 :: (load 4 from %ir.addr)
-# CHECK: %s0 = COPY %3
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_gep_16_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load 4 from %ir.addr)
+    ; CHECK: %s0 = COPY [[LDRSui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 16
     %2(p0) = G_GEP %0, %1
@@ -451,30 +397,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: load_gep_64_s16_fpr
 name:            load_gep_64_s16_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: fpr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %3 = LDRHui %0, 32 :: (load 2 from %ir.addr)
-# CHECK: %h0 = COPY %3
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_gep_64_s16_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr)
+    ; CHECK: %h0 = COPY [[LDRHui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 64
     %2(p0) = G_GEP %0, %1
@@ -483,33 +423,104 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: load_gep_32_s8_fpr
 name:            load_gep_32_s8_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: fpr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %3 = LDRBui %0, 32 :: (load 1 from %ir.addr)
-# CHECK: %b0 = COPY %3
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: load_gep_32_s8_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load 1 from %ir.addr)
+    ; CHECK: %b0 = COPY [[LDRBui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 32
     %2(p0) = G_GEP %0, %1
     %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr)
     %b0 = COPY %3
 ...
+---
+name:            load_v2s32
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %x0
+
+    ; CHECK-LABEL: name: load_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
+    ; CHECK: %d0 = COPY [[LDRDui]]
+    %0(p0) = COPY %x0
+    %1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr)
+    %d0 = COPY %1(<2 x s32>)
+...
+---
+name:            sextload_s32_from_s16
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %w0
+
+    ; CHECK-LABEL: name: sextload_s32_from_s16
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRSHWui [[COPY]], 0 :: (load 2 from %ir.addr)
+    ; CHECK: %w0 = COPY [[T0]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+    %2:gpr(s32) = G_SEXT %1
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            zextload_s32_from_s16
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %w0
+
+    ; CHECK-LABEL: name: zextload_s32_from_s16
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
+    ; CHECK: %w0 = COPY [[T0]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+    %2:gpr(s32) = G_ZEXT %1
+    %w0 = COPY %2(s32)
+...
+
+---
+name:            aextload_s32_from_s16
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %w0
+
+    ; CHECK-LABEL: name: aextload_s32_from_s16
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
+    ; CHECK: %w0 = COPY [[T0]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-muladd.mir b/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
index cd7a79f17d95..0771504032c5 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -7,19 +8,10 @@
 ...
 
 ---
-# CHECK-LABEL: name: SMADDLrrr_gpr
 name:            SMADDLrrr_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 6, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
@@ -29,15 +21,16 @@ registers:
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = COPY %w2
-# CHECK:    %6 = SMADDLrrr %1, %2, %0
 body:             |
   bb.0:
     liveins: %x0, %w1, %w2
 
+    ; CHECK-LABEL: name: SMADDLrrr_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY %w2
+    ; CHECK: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: %x0 = COPY [[SMADDLrrr]]
     %0(s64) = COPY %x0
     %1(s32) = COPY %w1
     %2(s32) = COPY %w2
diff --git a/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir b/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
new file mode 100644
index 000000000000..def06daae0b4
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -mattr=+neon,+fullfp16 -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @vcvtfxu2fp_s64_fpr() { ret void }
+...
+
+---
+# Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.
+name:            vcvtfxu2fp_s64_fpr
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %d0
+
+    ; CHECK-LABEL: name: vcvtfxu2fp_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[UCVTFd:%[0-9]+]]:fpr64 = UCVTFd [[COPY]], 12
+    ; CHECK: %d1 = COPY [[UCVTFd]]
+    %0(s64) = COPY %d0
+    %1(s32) = G_CONSTANT i32 12
+    %2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, %1
+    %d1 = COPY %2(s64)
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-phi.mir b/test/CodeGen/AArch64/GlobalISel/select-phi.mir
new file mode 100644
index 000000000000..3454ffadcce0
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/select-phi.mir
@@ -0,0 +1,124 @@
+# RUN: llc -mtriple=aarch64-unknown-unknown -o - -global-isel -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s
+--- |
+  ; ModuleID = '/tmp/test.ll'
+  source_filename = "/tmp/test.ll"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-unknown-unknown"
+
+  define i32 @test_phi(i32 %argc) {
+  entry:
+    %cmp = icmp ugt i32 %argc, 0
+    br i1 %cmp, label %case1, label %case2
+
+  case1:                                            ; preds = %entry
+    %tmp1 = add i32 %argc, 1
+    br label %return
+
+  case2:                                            ; preds = %entry
+    %tmp2 = add i32 %argc, 2
+    br label %return
+
+  return:                                           ; preds = %case2, %case1
+    %res = phi i32 [ %tmp1, %case1 ], [ %tmp2, %case2 ]
+    ret i32 %res
+  }
+
+  define i64* @test_phi_ptr(i64* %a, i64* %b, i1 %cond) {
+  entry:
+    ret i64* null
+  }
+
+...
+---
+name:            test_phi
+alignment:       2
+exposesReturnsTwice: false
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr, preferred-register: '' }
+  - { id: 1, class: gpr, preferred-register: '' }
+  - { id: 2, class: gpr, preferred-register: '' }
+  - { id: 3, class: gpr, preferred-register: '' }
+  - { id: 4, class: gpr, preferred-register: '' }
+  - { id: 5, class: gpr, preferred-register: '' }
+  - { id: 6, class: gpr, preferred-register: '' }
+  - { id: 7, class: gpr, preferred-register: '' }
+  - { id: 8, class: gpr, preferred-register: '' }
+liveins:
+body:             |
+  bb.1.entry:
+    successors: %bb.2.case1(0x40000000), %bb.3.case2(0x40000000)
+    liveins: %w0
+    ; CHECK-LABEL: name: test_phi
+    ; CHECK: [[RES:%.*]]:gpr32 = PHI
+
+    %0(s32) = COPY %w0
+    %1(s32) = G_CONSTANT i32 0
+    %3(s32) = G_CONSTANT i32 1
+    %5(s32) = G_CONSTANT i32 2
+    %8(s32) = G_ICMP intpred(ugt), %0(s32), %1
+    %2(s1) = G_TRUNC %8(s32)
+    G_BRCOND %2(s1), %bb.2.case1
+    G_BR %bb.3.case2
+
+  bb.2.case1:
+    successors: %bb.4.return(0x80000000)
+
+    %4(s32) = G_ADD %0, %3
+    G_BR %bb.4.return
+
+  bb.3.case2:
+    successors: %bb.4.return(0x80000000)
+
+    %6(s32) = G_ADD %0, %5
+
+  bb.4.return:
+    %7(s32) = G_PHI %4(s32), %bb.2.case1, %6(s32), %bb.3.case2
+    %w0 = COPY %7(s32)
+    RET_ReallyLR implicit %w0
+
+...
+
+---
+name:            test_phi_ptr
+alignment:       2
+exposesReturnsTwice: false
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr, preferred-register: '' }
+  - { id: 1, class: gpr, preferred-register: '' }
+  - { id: 2, class: gpr, preferred-register: '' }
+  - { id: 3, class: gpr, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+liveins:
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: %w2, %x0, %x1
+    ; CHECK-LABEL: name: test_phi_ptr
+
+    %0(p0) = COPY %x0
+    %1(p0) = COPY %x1
+    %6:gpr(s32) = COPY %w2
+    %2(s1) = G_TRUNC %6
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.2
+
+  bb.1:
+    successors: %bb.2
+
+
+  bb.2:
+    ; CHECK: %{{[0-9]+}}:gpr64 = PHI %{{[0-9]+}}, %bb.0, %{{[0-9]+}}, %bb.1
+    %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
+    %x0 = COPY %3(p0)
+    RET_ReallyLR implicit %x0
+
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir b/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
index c35d1719f84c..5e0ead2dbdb3 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -5,11 +6,10 @@
   entry:
     ret i32 0
   }
-  
+
   declare i32 @printf(i8*, ...)
 ...
 ---
-# CHECK-LABEL: name: main
 name:            main
 alignment:       2
 exposesReturnsTwice: false
@@ -17,7 +17,7 @@ legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
@@ -34,7 +34,7 @@ registers:
   - { id: 13, class: gpr }
   - { id: 14, class: gpr }
   - { id: 15, class: gpr }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -48,13 +48,15 @@ frameInfo:
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
-# CHECK:     body:
-# CHECK:       %1 = COPY %w0
-# CHECK-NOT:   %2 = ORNWrr %wzr, %1
-# CHECK:       %4 = EONWrr %1, %3
 body:             |
   bb.1.entry:
     liveins: %w0
+    ; CHECK-LABEL: name: main
+    ; CHECK: liveins: %w0
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[EONWrr:%[0-9]+]]:gpr32 = EONWrr [[COPY]], [[MOVi32imm]]
+    ; CHECK: %w0 = COPY [[EONWrr]]
     %0(s32) = G_CONSTANT i32 -1
     %3(s32) = G_CONSTANT i32 1
     %1(s32) = COPY %w0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-store.mir b/test/CodeGen/AArch64/GlobalISel/select-store.mir
index 536e236c2738..11710031e21c 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -26,29 +27,27 @@
 
   define void @store_gep_8_s64_fpr(i64* %addr) { ret void }
   define void @store_gep_8_s32_fpr(i32* %addr) { ret void }
+
+  define void @store_v2s32(i64 *%addr) { ret void }
 ...
 
 ---
-# CHECK-LABEL: name: store_s64_gpr
 name:            store_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: STRXui %1, %0, 0 :: (store 8 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: store_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: STRXui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = COPY %x1
     G_STORE  %1, %0 :: (store 8 into %ir.addr)
@@ -56,26 +55,22 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_s32_gpr
 name:            store_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRWui %1, %0, 0 :: (store 4 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
+    ; CHECK-LABEL: name: store_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: STRWui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
     G_STORE  %1, %0 :: (store 4 into %ir.addr)
@@ -83,79 +78,71 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_s16_gpr
 name:            store_s16_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
+    ; CHECK-LABEL: name: store_s16_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
+    ; CHECK: STRHHui [[COPY2]], [[COPY]], 0 :: (store 2 into %ir.addr)
     %0(p0) = COPY %x0
-    %1(s16) = COPY %w1
+    %2:gpr(s32) = COPY %w1
+    %1(s16) = G_TRUNC %2
     G_STORE  %1, %0 :: (store 2 into %ir.addr)
 
 ...
 
 ---
-# CHECK-LABEL: name: store_s8_gpr
 name:            store_s8_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
+    ; CHECK-LABEL: name: store_s8_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
+    ; CHECK: STRBBui [[COPY2]], [[COPY]], 0 :: (store 1 into %ir.addr)
     %0(p0) = COPY %x0
-    %1(s8) = COPY %w1
+    %2:gpr(s32) = COPY %w1
+    %1(s8) = G_TRUNC %2
     G_STORE  %1, %0 :: (store 1 into %ir.addr)
 
 ...
 
 ---
-# CHECK-LABEL: name: store_zero_s64_gpr
 name:            store_zero_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: STRXui %xzr, %0, 0 :: (store 8 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: store_zero_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: STRXui %xzr, [[COPY]], 0 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 0
     G_STORE  %1, %0 :: (store 8 into %ir.addr)
@@ -163,25 +150,21 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_zero_s32_gpr
 name:            store_zero_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: STRWui %wzr, %0, 0 :: (store 4 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: store_zero_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: STRWui %wzr, [[COPY]], 0 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = G_CONSTANT i32 0
     G_STORE  %1, %0 :: (store 4 into %ir.addr)
@@ -189,14 +172,10 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_fi_s64_gpr
 name:            store_fi_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
@@ -204,43 +183,37 @@ registers:
 stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: STRXui %0, %stack.0.ptr0, 0 :: (store 8)
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: store_fi_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store 8)
     %0(p0) = COPY %x0
     %1(p0) = G_FRAME_INDEX %stack.0.ptr0
     G_STORE  %0, %1 :: (store 8)
 ...
 
 ---
-# CHECK-LABEL: name: store_gep_128_s64_gpr
 name:            store_gep_128_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %x1
-# CHECK: STRXui %1, %0, 16 :: (store 8 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: store_gep_128_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: STRXui [[COPY1]], [[COPY]], 16 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_CONSTANT i64 128
@@ -249,30 +222,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_gep_512_s32_gpr
 name:            store_gep_512_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRWui %1, %0, 128 :: (store 4 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
+    ; CHECK-LABEL: name: store_gep_512_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: STRWui [[COPY1]], [[COPY]], 128 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
     %2(s64) = G_CONSTANT i64 512
@@ -281,90 +248,78 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_gep_64_s16_gpr
 name:            store_gep_64_s16_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRHHui %1, %0, 32 :: (store 2 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
+    ; CHECK-LABEL: name: store_gep_64_s16_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
+    ; CHECK: STRHHui [[COPY2]], [[COPY]], 32 :: (store 2 into %ir.addr)
     %0(p0) = COPY %x0
-    %1(s16) = COPY %w1
+    %4:gpr(s32) = COPY %w1
+    %1(s16) = G_TRUNC %4
     %2(s64) = G_CONSTANT i64 64
     %3(p0) = G_GEP %0, %2
     G_STORE %1, %3 :: (store 2 into %ir.addr)
 ...
 
 ---
-# CHECK-LABEL: name: store_gep_1_s8_gpr
 name:            store_gep_1_s8_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
-# CHECK: STRBBui %1, %0, 1 :: (store 1 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
+    ; CHECK-LABEL: name: store_gep_1_s8_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
+    ; CHECK: STRBBui [[COPY2]], [[COPY]], 1 :: (store 1 into %ir.addr)
     %0(p0) = COPY %x0
-    %1(s8) = COPY %w1
+    %4:gpr(s32) = COPY %w1
+    %1(s8) = G_TRUNC %4
     %2(s64) = G_CONSTANT i64 1
     %3(p0) = G_GEP %0, %2
     G_STORE %1, %3 :: (store 1 into %ir.addr)
 ...
 
 ---
-# CHECK-LABEL: name: store_s64_fpr
 name:            store_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %d1
-# CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %d1
 
+    ; CHECK-LABEL: name: store_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = COPY %d1
     G_STORE  %1, %0 :: (store 8 into %ir.addr)
@@ -372,26 +327,22 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_s32_fpr
 name:            store_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %s1
-# CHECK: STRSui %1, %0, 0 :: (store 4 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %s1
 
+    ; CHECK-LABEL: name: store_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: STRSui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = COPY %s1
     G_STORE  %1, %0 :: (store 4 into %ir.addr)
@@ -399,30 +350,24 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_gep_8_s64_fpr
 name:            store_gep_8_s64_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %d1
-# CHECK: STRDui %1, %0, 1 :: (store 8 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %d1
 
+    ; CHECK-LABEL: name: store_gep_8_s64_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: STRDui [[COPY1]], [[COPY]], 1 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = COPY %d1
     %2(s64) = G_CONSTANT i64 8
@@ -431,33 +376,49 @@ body:             |
 ...
 
 ---
-# CHECK-LABEL: name: store_gep_8_s32_fpr
 name:            store_gep_8_s32_fpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %s1
-# CHECK: STRSui %1, %0, 2 :: (store 4 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %s1
 
+    ; CHECK-LABEL: name: store_gep_8_s32_fpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: STRSui [[COPY1]], [[COPY]], 2 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = COPY %s1
     %2(s64) = G_CONSTANT i64 8
     %3(p0) = G_GEP %0, %2
     G_STORE %1, %3 :: (store 4 into %ir.addr)
 ...
+---
+name:            store_v2s32
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: %x0, %d1
+
+    ; CHECK-LABEL: name: store_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
+    %0(p0) = COPY %x0
+    %1(<2 x s32>) = COPY %d1
+    G_STORE  %1, %0 :: (store 8 into %ir.addr)
+
+...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
index f43a9ab34ffd..421a676f7a43 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -9,73 +10,71 @@
 ...
 
 ---
-# CHECK-LABEL: name: trunc_s32_s64
 name:            trunc_s32_s64
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32sp, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: trunc_s32_s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
+    ; CHECK: %w0 = COPY [[COPY1]]
     %0(s64) = COPY %x0
     %1(s32) = G_TRUNC %0
     %w0 = COPY %1(s32)
 ...
 
 ---
-# CHECK-LABEL: name: trunc_s8_s64
 name:            trunc_s8_s64
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %1 = COPY %0.sub_32
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: trunc_s8_s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[COPY2]]
     %0(s64) = COPY %x0
     %1(s8) = G_TRUNC %0
-    %w0 = COPY %1(s8)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
-# CHECK-LABEL: name: trunc_s1_s32
 name:            trunc_s1_s32
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: trunc_s1_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[COPY2]]
     %0(s32) = COPY %w0
     %1(s1) = G_TRUNC %0
-    %w0 = COPY %1(s1)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/select-xor.mir b/test/CodeGen/AArch64/GlobalISel/select-xor.mir
index 7190fda15b8e..8f0b0dccca6e 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-xor.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-xor.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
@@ -14,28 +15,24 @@
 ---
 # Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
 # Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: xor_s32_gpr
 name:            xor_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %w1
-# CHECK:    %2 = EORWrr %0, %1
 body:             |
   bb.0:
     liveins: %w0, %w1
 
+    ; CHECK-LABEL: name: xor_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[COPY]], [[COPY1]]
+    ; CHECK: %w0 = COPY [[EORWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = G_XOR %0, %1
@@ -44,28 +41,24 @@ body:             |
 
 ---
 # Same as xor_s64_gpr, for 64-bit operations.
-# CHECK-LABEL: name: xor_s64_gpr
 name:            xor_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %x1
-# CHECK:    %2 = EORXrr %0, %1
 body:             |
   bb.0:
     liveins: %x0, %x1
 
+    ; CHECK-LABEL: name: xor_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[EORXrr:%[0-9]+]]:gpr64 = EORXrr [[COPY]], [[COPY1]]
+    ; CHECK: %x0 = COPY [[EORXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_XOR %0, %1
@@ -75,27 +68,23 @@ body:             |
 ---
 # Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
 # Also check that we constrain the register class of the COPY to GPR32.
-# CHECK-LABEL: name: xor_constant_n1_s32_gpr
 name:            xor_constant_n1_s32_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %2 = ORNWrr %wzr, %0
 body:             |
   bb.0:
     liveins: %w0
 
+    ; CHECK-LABEL: name: xor_constant_n1_s32_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr %wzr, [[COPY]]
+    ; CHECK: %w0 = COPY [[ORNWrr]]
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i32 -1
     %2(s32) = G_XOR %0, %1
@@ -104,27 +93,23 @@ body:             |
 
 ---
 # Same as xor_constant_n1_s64_gpr, for 64-bit operations.
-# CHECK-LABEL: name: xor_constant_n1_s64_gpr
 name:            xor_constant_n1_s64_gpr
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %2 = ORNXrr %xzr, %0
 body:             |
   bb.0:
     liveins: %x0
 
+    ; CHECK-LABEL: name: xor_constant_n1_s64_gpr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr %xzr, [[COPY]]
+    ; CHECK: %x0 = COPY [[ORNXrr]]
     %0(s64) = COPY %x0
     %1(s64) = G_CONSTANT i64 -1
     %2(s64) = G_XOR %0, %1
@@ -133,26 +118,25 @@ body:             |
 
 ---
 # Check that we can obtain constants from other basic blocks.
-# CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
 name:            xor_constant_n1_s32_gpr_2bb
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 
-# CHECK:  body:
-# CHECK:    B %bb.1
-# CHECK:    %0 = COPY %w0
-# CHECK:    %2 = ORNWrr %wzr, %0
 
 body:             |
+  ; CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+  ; CHECK:   [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr %wzr, [[COPY]]
+  ; CHECK:   %w0 = COPY [[ORNWrr]]
   bb.0:
     liveins: %w0, %w1
     successors: %bb.1
diff --git a/test/CodeGen/AArch64/GlobalISel/select.mir b/test/CodeGen/AArch64/GlobalISel/select.mir
index 5e52bc761a84..c13b27adbb18 100644
--- a/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -43,7 +43,7 @@ stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 
 # CHECK:  body:
-# CHECK: %0 = ADDXri %stack.0.ptr0, 0, 0
+# CHECK: %0:gpr64sp = ADDXri %stack.0.ptr0, 0, 0
 body:             |
   bb.0:
     %0(p0) = G_FRAME_INDEX %stack.0.ptr0
@@ -61,8 +61,8 @@ registers:
   - { id: 2, class: gpr }
 
 # CHECK:  body:
-# CHECK: %1 = MOVi64imm 42
-# CHECK: %2 = ADDXrr %0, %1
+# CHECK: %1:gpr64 = MOVi64imm 42
+# CHECK: %2:gpr64 = ADDXrr %0, %1
 body:             |
   bb.0:
       liveins: %x0
@@ -79,7 +79,7 @@ legalized:       true
 regBankSelected: true
 
 # CHECK:  body:
-# CHECK: %1 = ANDXri %0, 8060
+# CHECK: %1:gpr64sp = ANDXri %0, 8060
 body:             |
   bb.0:
       liveins: %x0
@@ -98,9 +98,9 @@ registers:
   - { id: 0, class: gpr }
 
 # CHECK:  body:
-# IOS: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
-# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
-# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_local
+# IOS: %0:gpr64 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
+# LINUX-DEFAULT: %0:gpr64 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
+# LINUX-PIC: %0:gpr64 = LOADgot target-flags(aarch64-got) @var_local
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @var_local
@@ -116,9 +116,9 @@ registers:
   - { id: 0, class: gpr }
 
 # CHECK:  body:
-# IOS: %0 = LOADgot target-flags(aarch64-got) @var_got
-# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got
-# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_got
+# IOS: %0:gpr64 = LOADgot target-flags(aarch64-got) @var_got
+# LINUX-DEFAULT: %0:gpr64 = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got
+# LINUX-PIC: %0:gpr64 = LOADgot target-flags(aarch64-got) @var_got
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @var_got
@@ -145,32 +145,44 @@ registers:
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
+  - { id: 8, class: gpr }
+  - { id: 9, class: gpr }
+  - { id: 10, class: gpr }
+  - { id: 11, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %wzr = SUBSWrr %0, %0, implicit-def %nzcv
-# CHECK:    %1 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
+# CHECK:    %1:gpr32 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
 
 # CHECK:    %xzr = SUBSXrr %2, %2, implicit-def %nzcv
-# CHECK:    %3 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
+# CHECK:    %3:gpr32 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
 
 # CHECK:    %xzr = SUBSXrr %4, %4, implicit-def %nzcv
-# CHECK:    %5 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
+# CHECK:    %5:gpr32 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
 
 body:             |
   bb.0:
     liveins: %w0, %x0
 
     %0(s32) = COPY %w0
-    %1(s1) = G_ICMP intpred(eq), %0, %0
-    %w0 = COPY %1(s1)
+    %1(s32) = G_ICMP intpred(eq), %0, %0
+    %6(s1) = G_TRUNC %1(s32)
+    %9(s32) = G_ANYEXT %6
+    %w0 = COPY %9(s32)
 
     %2(s64) = COPY %x0
-    %3(s1) = G_ICMP intpred(uge), %2, %2
-    %w0 = COPY %3(s1)
+    %3(s32) = G_ICMP intpred(uge), %2, %2
+    %7(s1) = G_TRUNC %3(s32)
+    %10(s32) = G_ANYEXT %7
+    %w0 = COPY %10(s32)
 
     %4(p0) = COPY %x0
-    %5(s1) = G_ICMP intpred(ne), %4, %4
-    %w0 = COPY %5(s1)
+    %5(s32) = G_ICMP intpred(ne), %4, %4
+    %8(s1) = G_TRUNC %5(s32)
+    %11(s32) = G_ANYEXT %8
+    %w0 = COPY %11(s32)
 ...
 
 ---
@@ -191,27 +203,35 @@ registers:
   - { id: 1, class: gpr }
   - { id: 2, class: fpr }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
 
 # CHECK:  body:
 # CHECK:    FCMPSrr %0, %0, implicit-def %nzcv
-# CHECK:    [[TST_MI:%[0-9]+]] = CSINCWr %wzr, %wzr, 5, implicit %nzcv
-# CHECK:    [[TST_GT:%[0-9]+]] = CSINCWr %wzr, %wzr, 13, implicit %nzcv
-# CHECK:    %1 = ORRWrr [[TST_MI]], [[TST_GT]]
+# CHECK:    [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr %wzr, %wzr, 5, implicit %nzcv
+# CHECK:    [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr %wzr, %wzr, 13, implicit %nzcv
+# CHECK:    %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
 
 # CHECK:    FCMPDrr %2, %2, implicit-def %nzcv
-# CHECK:    %3 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
+# CHECK:    %3:gpr32 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
 
 body:             |
   bb.0:
     liveins: %w0, %x0
 
     %0(s32) = COPY %s0
-    %1(s1) = G_FCMP floatpred(one), %0, %0
-    %w0 = COPY %1(s1)
+    %1(s32) = G_FCMP floatpred(one), %0, %0
+    %4(s1) = G_TRUNC %1(s32)
+    %6(s32) = G_ANYEXT %4
+    %w0 = COPY %6(s32)
 
     %2(s64) = COPY %d0
-    %3(s1) = G_FCMP floatpred(uge), %2, %2
-    %w0 = COPY %3(s1)
+    %3(s32) = G_FCMP floatpred(uge), %2, %2
+    %5(s1) = G_TRUNC %3(s32)
+    %7(s32) = G_ANYEXT %5
+    %w0 = COPY %7(s32)
 
 ...
 
@@ -233,14 +253,15 @@ registers:
 
 # CHECK:  body:
 # CHECK:    bb.1:
-# CHECK:      %2 = PHI %0, %bb.0, %2, %bb.1
+# CHECK:      %2:fpr32 = PHI %0, %bb.0, %2, %bb.1
 
 body:             |
   bb.0:
     liveins: %s0, %w0
     successors: %bb.1
     %0(s32) = COPY %s0
-    %1(s1) = COPY %w0
+    %3:gpr(s32) = COPY %w0
+    %1(s1) = G_TRUNC %3
 
   bb.1:
     successors: %bb.1, %bb.2
@@ -284,15 +305,16 @@ registers:
 
 # CHECK:  body:
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK:      %3 = CSELWr %1, %2, 1, implicit %nzcv
+# CHECK:      %3:gpr32 = CSELWr %1, %2, 1, implicit %nzcv
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK:      %6 = CSELXr %4, %5, 1, implicit %nzcv
+# CHECK:      %6:gpr64 = CSELXr %4, %5, 1, implicit %nzcv
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK:      %9 = CSELXr %7, %8, 1, implicit %nzcv
+# CHECK:      %9:gpr64 = CSELXr %7, %8, 1, implicit %nzcv
 body:             |
   bb.0:
     liveins: %w0, %w1, %w2
-    %0(s1) = COPY %w0
+    %10:gpr(s32) = COPY %w0
+    %0(s1) = G_TRUNC %10
 
     %1(s32) = COPY %w1
     %2(s32) = COPY %w2
diff --git a/test/CodeGen/AArch64/GlobalISel/translate-gep.ll b/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
index e4c18757418d..865315bbe0a3 100644
--- a/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
+++ b/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
@@ -4,9 +4,9 @@
 
 define %type* @first_offset_const(%type* %addr) {
 ; CHECK-LABEL: name: first_offset_const
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 32
-; CHECK: [[RES:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+; CHECK: [[RES:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET]](s64)
 ; CHECK: %x0 = COPY [[RES]](p0)
 
   %res = getelementptr %type, %type* %addr, i32 1
@@ -15,8 +15,8 @@ define %type* @first_offset_const(%type* %addr) {
 
 define %type* @first_offset_trivial(%type* %addr) {
 ; CHECK-LABEL: name: first_offset_trivial
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[TRIVIAL:%[0-9]+]](p0) = COPY [[BASE]](p0)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[TRIVIAL:%[0-9]+]]:_(p0) = COPY [[BASE]](p0)
 ; CHECK: %x0 = COPY [[TRIVIAL]](p0)
 
   %res = getelementptr %type, %type* %addr, i32 0
@@ -25,12 +25,12 @@ define %type* @first_offset_trivial(%type* %addr) {
 
 define %type* @first_offset_variable(%type* %addr, i64 %idx) {
 ; CHECK-LABEL: name: first_offset_variable
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 32
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]]
-; CHECK: [[STEP0:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64)
-; CHECK: [[RES:%[0-9]+]](p0) = COPY [[STEP0]](p0)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IDX:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_MUL [[SIZE]], [[IDX]]
+; CHECK: [[STEP0:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET]](s64)
+; CHECK: [[RES:%[0-9]+]]:_(p0) = COPY [[STEP0]](p0)
 ; CHECK: %x0 = COPY [[RES]](p0)
 
   %res = getelementptr %type, %type* %addr, i64 %idx
@@ -39,13 +39,13 @@ define %type* @first_offset_variable(%type* %addr, i64 %idx) {
 
 define %type* @first_offset_ext(%type* %addr, i32 %idx) {
 ; CHECK-LABEL: name: first_offset_ext
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IDX32:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 32
-; CHECK: [[IDX64:%[0-9]+]](s64) = G_SEXT [[IDX32]](s32)
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX64]]
-; CHECK: [[STEP0:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64)
-; CHECK: [[RES:%[0-9]+]](p0) = COPY [[STEP0]](p0)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IDX32:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+; CHECK: [[IDX64:%[0-9]+]]:_(s64) = G_SEXT [[IDX32]](s32)
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_MUL [[SIZE]], [[IDX64]]
+; CHECK: [[STEP0:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET]](s64)
+; CHECK: [[RES:%[0-9]+]]:_(p0) = COPY [[STEP0]](p0)
 ; CHECK: %x0 = COPY [[RES]](p0)
 
   %res = getelementptr %type, %type* %addr, i32 %idx
@@ -55,14 +55,14 @@ define %type* @first_offset_ext(%type* %addr, i32 %idx) {
 %type1 = type [4 x [4 x i32]]
 define i32* @const_then_var(%type1* %addr, i64 %idx) {
 ; CHECK-LABEL: name: const_then_var
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 272
-; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 4
-; CHECK: [[BASE1:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET1]](s64)
-; CHECK: [[OFFSET2:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]]
-; CHECK: [[BASE2:%[0-9]+]](p0) = G_GEP [[BASE1]], [[OFFSET2]](s64)
-; CHECK: [[RES:%[0-9]+]](p0) = COPY [[BASE2]](p0)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IDX:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 272
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+; CHECK: [[BASE1:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET1]](s64)
+; CHECK: [[OFFSET2:%[0-9]+]]:_(s64) = G_MUL [[SIZE]], [[IDX]]
+; CHECK: [[BASE2:%[0-9]+]]:_(p0) = G_GEP [[BASE1]], [[OFFSET2]](s64)
+; CHECK: [[RES:%[0-9]+]]:_(p0) = COPY [[BASE2]](p0)
 ; CHECK: %x0 = COPY [[RES]](p0)
 
   %res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx
@@ -71,13 +71,13 @@ define i32* @const_then_var(%type1* %addr, i64 %idx) {
 
 define i32* @var_then_const(%type1* %addr, i64 %idx) {
 ; CHECK-LABEL: name: var_then_const
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 64
-; CHECK: [[OFFSET2:%[0-9]+]](s64) = G_CONSTANT i64 40
-; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]]
-; CHECK: [[BASE1:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET1]](s64)
-; CHECK: [[BASE2:%[0-9]+]](p0) = G_GEP [[BASE1]], [[OFFSET2]](s64)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IDX:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+; CHECK: [[OFFSET2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
+; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_MUL [[SIZE]], [[IDX]]
+; CHECK: [[BASE1:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET1]](s64)
+; CHECK: [[BASE2:%[0-9]+]]:_(p0) = G_GEP [[BASE1]], [[OFFSET2]](s64)
 ; CHECK: %x0 = COPY [[BASE2]](p0)
 
   %res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2
diff --git a/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll b/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
index af0ab57b0b9f..f92a5721a4ee 100644
--- a/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
+++ b/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
@@ -6,8 +6,8 @@ define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64,
 ; CHECK: fixedStack:
 ; CHECK:   - { id: [[VARARGS_SLOT:[0-9]+]], type: default, offset: 8
 ; CHECK: body:
-; CHECK:   [[LIST:%[0-9]+]] = COPY %x0
-; CHECK:   [[VARARGS_AREA:%[0-9]+]] = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0
+; CHECK:   [[LIST:%[0-9]+]]:gpr64sp = COPY %x0
+; CHECK:   [[VARARGS_AREA:%[0-9]+]]:gpr64common = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0
 ; CHECK:   STRXui [[VARARGS_AREA]], [[LIST]], 0 :: (store 8 into %ir.list, align 0)
   call void @llvm.va_start(i8* %list)
   ret void
diff --git a/test/CodeGen/AArch64/GlobalISel/vastart.ll b/test/CodeGen/AArch64/GlobalISel/vastart.ll
index ae44e8fc5dea..1fb3eb55e677 100644
--- a/test/CodeGen/AArch64/GlobalISel/vastart.ll
+++ b/test/CodeGen/AArch64/GlobalISel/vastart.ll
@@ -5,7 +5,7 @@
 declare void @llvm.va_start(i8*)
 define void @test_va_start(i8* %list) {
 ; CHECK-LABEL: name: test_va_start
-; CHECK: [[LIST:%[0-9]+]](p0) = COPY %x0
+; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY %x0
 ; CHECK-IOS: G_VASTART [[LIST]](p0) :: (store 8 into %ir.list, align 0)
 ; CHECK-LINUX: G_VASTART [[LIST]](p0) :: (store 32 into %ir.list, align 0)
   call void @llvm.va_start(i8* %list)
diff --git a/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir b/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
index 9a2f7f7e54f8..94a9134072a3 100644
--- a/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
+++ b/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
@@ -9,8 +9,8 @@
 ...
 ---
 # CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function ***
-# CHECK: instruction: %vreg0<def>(s64) = COPY
-# CHECK: operand 0: %vreg0<def>
+# CHECK: instruction: %0:_(s64) = COPY
+# CHECK: operand 0: %0
 name:            test
 regBankSelected: true
 registers:
diff --git a/test/CodeGen/AArch64/GlobalISel/verify-selected.mir b/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
index 2149903d08a7..772233ec1038 100644
--- a/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
+++ b/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
@@ -22,11 +22,11 @@ body: |
    %0 = COPY %x0
 
    ; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function ***
-   ; CHECK: instruction: %vreg1<def> = G_ADD
+   ; CHECK: instruction: %1:gpr64 = G_ADD
    %1 = G_ADD %0, %0
 
    ; CHECK: *** Bad machine code: Generic virtual register invalid in a Selected function ***
-   ; CHECK: instruction: %vreg2<def>(s64) = COPY
-   ; CHECK: operand 0: %vreg2<def>
+   ; CHECK: instruction: %2:gpr(s64) = COPY
+   ; CHECK: operand 0: %2
    %2(s64) = COPY %x0
 ...
diff --git a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
index 29b71e042611..55f6c01cbd9f 100644
--- a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
+++ b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
@@ -296,7 +296,7 @@ declare double @hh(double) #1
 
 ; Check that we correctly deal with repeated operands.
 ; The following testcase creates:
-;   %D1<def> = FADDDrr %D0<kill>, %D0
+;   %d1 = FADDDrr killed %d0, %d0
 ; We'll get a crash if we naively look at the first operand, remove it
 ; from the substitution list then look at the second operand.
 
diff --git a/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir b/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
new file mode 100644
index 000000000000..630b34028162
--- /dev/null
+++ b/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
@@ -0,0 +1,82 @@
+# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 -enable-unsafe-fp-math %s | FileCheck --check-prefix=UNPROFITABLE %s
+# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=falkor -enable-unsafe-fp-math %s | FileCheck --check-prefix=PROFITABLE %s
+# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=exynosm1 -enable-unsafe-fp-math %s | FileCheck --check-prefix=PROFITABLE %s
+# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 -enable-unsafe-fp-math %s | FileCheck --check-prefix=PROFITABLE %s
+#
+name:            f1_2s
+registers:
+  - { id: 0, class: fpr64 }
+  - { id: 1, class: fpr64 }
+  - { id: 2, class: fpr64 }
+  - { id: 3, class: fpr64 }
+  - { id: 4, class: fpr64 }
+body:             |
+  bb.0.entry:
+    %2:fpr64 = COPY %d2
+    %1:fpr64 = COPY %d1
+    %0:fpr64 = COPY %d0
+    %3:fpr64 = FMULv2f32 %0, %1
+    %4:fpr64 = FSUBv2f32 killed %3, %2
+    %d0 = COPY %4
+    RET_ReallyLR implicit %d0
+
+...
+# UNPROFITABLE-LABEL: name: f1_2s
+# UNPROFITABLE: %3:fpr64 = FMULv2f32 %0, %1
+# UNPROFITABLE-NEXT: FSUBv2f32 killed %3, %2
+#
+# PROFITABLE-LABEL: name: f1_2s
+# PROFITABLE: %5:fpr64 = FNEGv2f32 %2
+# PROFITABLE-NEXT: FMLAv2f32 killed %5, %0, %1
+---
+name:            f1_4s
+registers:
+  - { id: 0, class: fpr128 }
+  - { id: 1, class: fpr128 }
+  - { id: 2, class: fpr128 }
+  - { id: 3, class: fpr128 }
+  - { id: 4, class: fpr128 }
+body:             |
+  bb.0.entry:
+    %2:fpr128 = COPY %q2
+    %1:fpr128 = COPY %q1
+    %0:fpr128 = COPY %q0
+    %3:fpr128 = FMULv4f32 %0, %1
+    %4:fpr128 = FSUBv4f32 killed %3, %2
+    %q0 = COPY %4
+    RET_ReallyLR implicit %q0
+
+...
+# UNPROFITABLE-LABEL: name: f1_4s
+# UNPROFITABLE: %3:fpr128 = FMULv4f32 %0, %1
+# UNPROFITABLE-NEXT: FSUBv4f32 killed %3, %2
+#
+# PROFITABLE-LABEL: name: f1_4s
+# PROFITABLE: %5:fpr128 = FNEGv4f32 %2
+# PROFITABLE-NEXT: FMLAv4f32 killed %5, %0, %1
+---
+name:            f1_2d
+registers:
+  - { id: 0, class: fpr128 }
+  - { id: 1, class: fpr128 }
+  - { id: 2, class: fpr128 }
+  - { id: 3, class: fpr128 }
+  - { id: 4, class: fpr128 }
+body:             |
+  bb.0.entry:
+    %2:fpr128 = COPY %q2
+    %1:fpr128 = COPY %q1
+    %0:fpr128 = COPY %q0
+    %3:fpr128 = FMULv2f64 %0, %1
+    %4:fpr128 = FSUBv2f64 killed %3, %2
+    %q0 = COPY %4
+    RET_ReallyLR implicit %q0
+
+...
+# UNPROFITABLE-LABEL: name: f1_2d
+# UNPROFITABLE: %3:fpr128 = FMULv2f64 %0, %1
+# UNPROFITABLE-NEXT: FSUBv2f64 killed %3, %2
+#
+# PROFITABLE-LABEL: name: f1_2d
+# PROFITABLE: %5:fpr128 = FNEGv2f64 %2
+# PROFITABLE-NEXT: FMLAv2f64 killed %5, %0, %1
diff --git a/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll b/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
index 51c32b409db5..eafb4126807f 100644
--- a/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
+++ b/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
@@ -508,12 +508,12 @@ block1:
 ; CHECK:	ldr
 ; CHECK-NEXT:	nop
 ; CHECK-NEXT:	.Ltmp
-; CHECK-NEXT: 	BB
+; CHECK-NEXT: 	%bb.
 ; CHECK-NEXT: 	madd
 ; CHECK-NOWORKAROUND-LABEL:	fall_through
 ; CHECK-NOWORKAROUND: 	ldr
 ; CHECK-NOWORKAROUND-NEXT:	.Ltmp
-; CHECK-NOWORKAROUND-NEXT:	BB
+; CHECK-NOWORKAROUND-NEXT:	%bb.
 ; CHECK-NOWORKAROUND-NEXT:	madd
 
 ; No checks for this, just check it doesn't crash
diff --git a/test/CodeGen/AArch64/aarch64-loop-gep-opt.ll b/test/CodeGen/AArch64/aarch64-loop-gep-opt.ll
index 2b4e438a13aa..1b2ed4b89521 100644
--- a/test/CodeGen/AArch64/aarch64-loop-gep-opt.ll
+++ b/test/CodeGen/AArch64/aarch64-loop-gep-opt.ll
@@ -19,9 +19,9 @@ entry:
 
 do.body.i:
 ; CHECK-LABEL: do.body.i:
-; CHECK:          %uglygep1 = getelementptr i8, i8* %uglygep, i64 %3
-; CHECK-NEXT:     %4 = bitcast i8* %uglygep1 to i32*
-; CHECK-NOT:      %uglygep1 = getelementptr i8, i8* %uglygep, i64 1032
+; CHECK:          %uglygep2 = getelementptr i8, i8* %uglygep, i64 %3
+; CHECK-NEXT:     %4 = bitcast i8* %uglygep2 to i32*
+; CHECK-NOT:      %uglygep2 = getelementptr i8, i8* %uglygep, i64 1032
 
 
   %0 = phi i32 [ 256, %entry ], [ %.be, %do.body.i.backedge ]
diff --git a/test/CodeGen/AArch64/aarch64-stp-cluster.ll b/test/CodeGen/AArch64/aarch64-stp-cluster.ll
index 25cf313b81e7..c6bdbe4f0322 100644
--- a/test/CodeGen/AArch64/aarch64-stp-cluster.ll
+++ b/test/CodeGen/AArch64/aarch64-stp-cluster.ll
@@ -2,13 +2,13 @@
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s
 
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: stp_i64_scale:BB#0
+; CHECK-LABEL: stp_i64_scale:%bb.0
 ; CHECK:Cluster ld/st SU(4) - SU(3)
 ; CHECK:Cluster ld/st SU(2) - SU(5)
-; CHECK:SU(4):   STRXui %vreg1, %vreg0, 1
-; CHECK:SU(3):   STRXui %vreg1, %vreg0, 2
-; CHECK:SU(2):   STRXui %vreg1, %vreg0, 3
-; CHECK:SU(5):   STRXui %vreg1, %vreg0, 4
+; CHECK:SU(4):   STRXui %1, %0, 1
+; CHECK:SU(3):   STRXui %1, %0, 2
+; CHECK:SU(2):   STRXui %1, %0, 3
+; CHECK:SU(5):   STRXui %1, %0, 4
 define i64 @stp_i64_scale(i64* nocapture %P, i64 %v) {
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %P, i64 3
@@ -23,13 +23,13 @@ entry:
 }
 
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: stp_i32_scale:BB#0
+; CHECK-LABEL: stp_i32_scale:%bb.0
 ; CHECK:Cluster ld/st SU(4) - SU(3)
 ; CHECK:Cluster ld/st SU(2) - SU(5)
-; CHECK:SU(4):   STRWui %vreg1, %vreg0, 1
-; CHECK:SU(3):   STRWui %vreg1, %vreg0, 2
-; CHECK:SU(2):   STRWui %vreg1, %vreg0, 3
-; CHECK:SU(5):   STRWui %vreg1, %vreg0, 4
+; CHECK:SU(4):   STRWui %1, %0, 1
+; CHECK:SU(3):   STRWui %1, %0, 2
+; CHECK:SU(2):   STRWui %1, %0, 3
+; CHECK:SU(5):   STRWui %1, %0, 4
 define i32 @stp_i32_scale(i32* nocapture %P, i32 %v) {
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %P, i32 3
@@ -44,13 +44,13 @@ entry:
 }
 
 ; CHECK:********** MI Scheduling **********
-; CHECK-LABEL:stp_i64_unscale:BB#0 entry
+; CHECK-LABEL:stp_i64_unscale:%bb.0 entry
 ; CHECK:Cluster ld/st SU(5) - SU(2)
 ; CHECK:Cluster ld/st SU(4) - SU(3)
-; CHECK:SU(5):   STURXi %vreg1, %vreg0, -32
-; CHECK:SU(2):   STURXi %vreg1, %vreg0, -24
-; CHECK:SU(4):   STURXi %vreg1, %vreg0, -16
-; CHECK:SU(3):   STURXi %vreg1, %vreg0, -8
+; CHECK:SU(5):   STURXi %1, %0, -32
+; CHECK:SU(2):   STURXi %1, %0, -24
+; CHECK:SU(4):   STURXi %1, %0, -16
+; CHECK:SU(3):   STURXi %1, %0, -8
 define void @stp_i64_unscale(i64* nocapture %P, i64 %v) #0 {
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %P, i64 -3
@@ -65,13 +65,13 @@ entry:
 }
 
 ; CHECK:********** MI Scheduling **********
-; CHECK-LABEL:stp_i32_unscale:BB#0 entry
+; CHECK-LABEL:stp_i32_unscale:%bb.0 entry
 ; CHECK:Cluster ld/st SU(5) - SU(2)
 ; CHECK:Cluster ld/st SU(4) - SU(3)
-; CHECK:SU(5):   STURWi %vreg1, %vreg0, -16
-; CHECK:SU(2):   STURWi %vreg1, %vreg0, -12
-; CHECK:SU(4):   STURWi %vreg1, %vreg0, -8
-; CHECK:SU(3):   STURWi %vreg1, %vreg0, -4
+; CHECK:SU(5):   STURWi %1, %0, -16
+; CHECK:SU(2):   STURWi %1, %0, -12
+; CHECK:SU(4):   STURWi %1, %0, -8
+; CHECK:SU(3):   STURWi %1, %0, -4
 define void @stp_i32_unscale(i32* nocapture %P, i32 %v) #0 {
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %P, i32 -3
@@ -86,13 +86,13 @@ entry:
 }
 
 ; CHECK:********** MI Scheduling **********
-; CHECK-LABEL:stp_double:BB#0
+; CHECK-LABEL:stp_double:%bb.0
 ; CHECK:Cluster ld/st SU(3) - SU(4)
 ; CHECK:Cluster ld/st SU(2) - SU(5)
-; CHECK:SU(3):   STRDui %vreg1, %vreg0, 1
-; CHECK:SU(4):   STRDui %vreg1, %vreg0, 2
-; CHECK:SU(2):   STRDui %vreg1, %vreg0, 3
-; CHECK:SU(5):   STRDui %vreg1, %vreg0, 4
+; CHECK:SU(3):   STRDui %1, %0, 1
+; CHECK:SU(4):   STRDui %1, %0, 2
+; CHECK:SU(2):   STRDui %1, %0, 3
+; CHECK:SU(5):   STRDui %1, %0, 4
 define void @stp_double(double* nocapture %P, double %v)  {
 entry:
   %arrayidx = getelementptr inbounds double, double* %P, i64 3
@@ -107,13 +107,13 @@ entry:
 }
 
 ; CHECK:********** MI Scheduling **********
-; CHECK-LABEL:stp_float:BB#0
+; CHECK-LABEL:stp_float:%bb.0
 ; CHECK:Cluster ld/st SU(3) - SU(4)
 ; CHECK:Cluster ld/st SU(2) - SU(5)
-; CHECK:SU(3):   STRSui %vreg1, %vreg0, 1
-; CHECK:SU(4):   STRSui %vreg1, %vreg0, 2
-; CHECK:SU(2):   STRSui %vreg1, %vreg0, 3
-; CHECK:SU(5):   STRSui %vreg1, %vreg0, 4
+; CHECK:SU(3):   STRSui %1, %0, 1
+; CHECK:SU(4):   STRSui %1, %0, 2
+; CHECK:SU(2):   STRSui %1, %0, 3
+; CHECK:SU(5):   STRSui %1, %0, 4
 define void @stp_float(float* nocapture %P, float %v)  {
 entry:
   %arrayidx = getelementptr inbounds float, float* %P, i64 3
@@ -128,12 +128,12 @@ entry:
 }
 
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: stp_volatile:BB#0
+; CHECK-LABEL: stp_volatile:%bb.0
 ; CHECK-NOT: Cluster ld/st
-; CHECK:SU(2):   STRXui %vreg1, %vreg0, 3; mem:Volatile
-; CHECK:SU(3):   STRXui %vreg1, %vreg0, 2; mem:Volatile
-; CHECK:SU(4):   STRXui %vreg1, %vreg0, 1; mem:Volatile
-; CHECK:SU(5):   STRXui %vreg1, %vreg0, 4; mem:Volatile
+; CHECK:SU(2):   STRXui %1, %0, 3; mem:Volatile
+; CHECK:SU(3):   STRXui %1, %0, 2; mem:Volatile
+; CHECK:SU(4):   STRXui %1, %0, 1; mem:Volatile
+; CHECK:SU(5):   STRXui %1, %0, 4; mem:Volatile
 define i64 @stp_volatile(i64* nocapture %P, i64 %v) {
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %P, i64 3
diff --git a/test/CodeGen/AArch64/analyze-branch.ll b/test/CodeGen/AArch64/analyze-branch.ll
index 932cd75052c1..4f902ef4fc83 100644
--- a/test/CodeGen/AArch64/analyze-branch.ll
+++ b/test/CodeGen/AArch64/analyze-branch.ll
@@ -18,7 +18,7 @@ define void @test_Bcc_fallthrough_taken(i32 %in) nounwind {
 ; CHECK: cmp {{w[0-9]+}}, #42
 
 ; CHECK: b.ne [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_true
 
 ; CHECK: [[FALSE]]:
@@ -41,7 +41,7 @@ define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind {
 ; CHECK: cmp {{w[0-9]+}}, #42
 
 ; CHECK: b.eq [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_false
 
 ; CHECK: [[TRUE]]:
@@ -62,7 +62,7 @@ define void @test_CBZ_fallthrough_taken(i32 %in) nounwind {
   br i1 %tst, label %true, label %false, !prof !0
 
 ; CHECK: cbnz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_true
 
 ; CHECK: [[FALSE]]:
@@ -83,7 +83,7 @@ define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind {
   br i1 %tst, label %true, label %false, !prof !1
 
 ; CHECK: cbz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_false
 
 ; CHECK: [[TRUE]]:
@@ -104,7 +104,7 @@ define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind {
   br i1 %tst, label %true, label %false, !prof !0
 
 ; CHECK: cbz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_true
 
 ; CHECK: [[FALSE]]:
@@ -125,7 +125,7 @@ define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind {
   br i1 %tst, label %true, label %false, !prof !1
 
 ; CHECK: cbnz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_false
 
 ; CHECK: [[TRUE]]:
@@ -147,7 +147,7 @@ define void @test_TBZ_fallthrough_taken(i32 %in) nounwind {
   br i1 %tst, label %true, label %false, !prof !0
 
 ; CHECK: tbnz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_true
 
 ; CHECK: [[FALSE]]:
@@ -169,7 +169,7 @@ define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind {
   br i1 %tst, label %true, label %false, !prof !1
 
 ; CHECK: tbz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_false
 
 ; CHECK: [[TRUE]]:
@@ -192,7 +192,7 @@ define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind {
   br i1 %tst, label %true, label %false, !prof !0
 
 ; CHECK: tbz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_true
 
 ; CHECK: [[FALSE]]:
@@ -214,7 +214,7 @@ define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind {
   br i1 %tst, label %true, label %false, !prof !1
 
 ; CHECK: tbnz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
 ; CHECK-NEXT: bl test_false
 
 ; CHECK: [[TRUE]]:
diff --git a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll
index bc55c1d9251f..294680a6d3a9 100644
--- a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll
+++ b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll
@@ -31,7 +31,7 @@ attributes #1 = { nounwind readnone }
 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, globals: !2)
 !1 = !DIFile(filename: "print.i", directory: "/Volumes/Ebi/echeng/radars/r9146594")
 !2 = !{!3}
-!3 = !DIGlobalVariableExpression(var: !4)
+!3 = !DIGlobalVariableExpression(var: !4, expr: !DIExpression())
 !4 = !DIGlobalVariable(name: "vsplive", scope: !5, file: !1, line: 617, type: !8, isLocal: true, isDefinition: true)
 !5 = distinct !DISubprogram(name: "drt_vsprintf", scope: !1, file: !1, line: 616, type: !6, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0)
 !6 = !DISubroutineType(types: !7)
diff --git a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
index ef8d6f3b4ef9..bd0028c74528 100644
--- a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
+++ b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=arm64-apple-ios -verify-machineinstrs | FileCheck %s
 
 ; LdStOpt bug created illegal instruction:
-;   %D1<def>, %D2<def> = LDPSi %X0, 1
+;   %d1, %d2 = LDPSi %x0, 1
 ; rdar://11512047
 
 %0 = type opaque
diff --git a/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll b/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
index 649bc25b7265..72e5ec6b89b5 100644
--- a/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
+++ b/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
@@ -17,7 +17,7 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
 ; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
 ; CHECK-NOOPT: fmov d0, [[COPY_REG3]]
 ; CHECK-OPT-NOT: fmov
-; CHECK: ins.d v0[1], [[COPY_REG2]]
+; CHECK: mov.d v0[1], [[COPY_REG2]]
 ; CHECK-NEXT: ret
 ;
 ; GENERIC-LABEL: bar:
@@ -29,7 +29,7 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
 ; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
 ; GENERIC-NOOPT: fmov d0, [[COPY_REG3]]
 ; GENERIC-OPT-NOT: fmov
-; GENERIC: ins v0.d[1], [[COPY_REG2]]
+; GENERIC: mov v0.d[1], [[COPY_REG2]]
 ; GENERIC-NEXT: ret
   %add = add <2 x i64> %a, %b
   %vgetq_lane = extractelement <2 x i64> %add, i32 0
diff --git a/test/CodeGen/AArch64/arm64-abi-varargs.ll b/test/CodeGen/AArch64/arm64-abi-varargs.ll
index 64a6b9b6b210..d6a1686d5663 100644
--- a/test/CodeGen/AArch64/arm64-abi-varargs.ll
+++ b/test/CodeGen/AArch64/arm64-abi-varargs.ll
@@ -101,9 +101,8 @@ define i32 @main() nounwind ssp {
 define void @foo(i8* %fmt, ...) nounwind {
 entry:
 ; CHECK-LABEL: foo:
-; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, #0x8
 ; CHECK: ldr {{w[0-9]+}}, [sp, #48]
-; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #15
+; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #23
 ; CHECK: and x[[ADDR:[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0
 ; CHECK: ldr {{q[0-9]+}}, [x[[ADDR]]]
   %fmt.addr = alloca i8*, align 8
@@ -142,9 +141,8 @@ entry:
 define void @foo2(i8* %fmt, ...) nounwind {
 entry:
 ; CHECK-LABEL: foo2:
-; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, #0x8
 ; CHECK: ldr {{w[0-9]+}}, [sp, #48]
-; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #15
+; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #23
 ; CHECK: and x[[ADDR:[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0
 ; CHECK: ldr {{q[0-9]+}}, [x[[ADDR]]]
   %fmt.addr = alloca i8*, align 8
diff --git a/test/CodeGen/AArch64/arm64-atomic.ll b/test/CodeGen/AArch64/arm64-atomic.ll
index 2c9a3bbaa500..db343e95a3de 100644
--- a/test/CodeGen/AArch64/arm64-atomic.ll
+++ b/test/CodeGen/AArch64/arm64-atomic.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck -enable-var-scope %s
 
 define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
 ; CHECK-LABEL: val_compare_and_swap:
@@ -22,16 +22,16 @@ define i32 @val_compare_and_swap_from_load(i32* %p, i32 %cmp, i32* %pnew) #0 {
 ; CHECK-LABEL: val_compare_and_swap_from_load:
 ; CHECK-NEXT: ldr    [[NEW:w[0-9]+]], [x2]
 ; CHECK-NEXT: [[TRYBB:.?LBB[0-9_]+]]:
-; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x0]
-; CHECK-NEXT: cmp    [[RESULT]], w1
+; CHECK-NEXT: ldaxr  w[[RESULT:[0-9]+]], [x0]
+; CHECK-NEXT: cmp    w[[RESULT]], w1
 ; CHECK-NEXT: b.ne   [[FAILBB:.?LBB[0-9_]+]]
 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0]
 ; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[TRYBB]]
-; CHECK-NEXT: mov    x0, x[[ADDR]]
+; CHECK-NEXT: mov    x0, x[[RESULT]]
 ; CHECK-NEXT: ret
 ; CHECK-NEXT: [[FAILBB]]:
 ; CHECK-NEXT: clrex
-; CHECK-NEXT: mov    x0, x[[ADDR]]
+; CHECK-NEXT: mov    x0, x[[RESULT]]
 ; CHECK-NEXT: ret
   %new = load i32, i32* %pnew
   %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
diff --git a/test/CodeGen/AArch64/arm64-build-vector.ll b/test/CodeGen/AArch64/arm64-build-vector.ll
index 4bf15ea2393e..9d3247350499 100644
--- a/test/CodeGen/AArch64/arm64-build-vector.ll
+++ b/test/CodeGen/AArch64/arm64-build-vector.ll
@@ -5,7 +5,7 @@
 define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
 ; CHECK-LABEL: one_lane:
 ; CHECK: dup.16b v[[REG:[0-9]+]], wzr
-; CHECK-NEXT: ins.b v[[REG]][0], w1
+; CHECK-NEXT: mov.b v[[REG]][0], w1
 ; v and q are aliases, and str is preferred against st.16b when possible
 ; rdar://11246289
 ; CHECK: str q[[REG]], [x0]
@@ -22,10 +22,10 @@ define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
 ; copy for lane zero.
 define <4 x float>  @foo(float %a, float %b, float %c, float %d) nounwind {
 ; CHECK-LABEL: foo:
-; CHECK-NOT: ins.s v0[0], v0[0]
-; CHECK: ins.s v0[1], v1[0]
-; CHECK: ins.s v0[2], v2[0]
-; CHECK: ins.s v0[3], v3[0]
+; CHECK-NOT: mov.s v0[0], v0[0]
+; CHECK: mov.s v0[1], v1[0]
+; CHECK: mov.s v0[2], v2[0]
+; CHECK: mov.s v0[3], v3[0]
 ; CHECK: ret
   %1 = insertelement <4 x float> undef, float %a, i32 0
   %2 = insertelement <4 x float> %1, float %b, i32 1
diff --git a/test/CodeGen/AArch64/arm64-ccmp.ll b/test/CodeGen/AArch64/arm64-ccmp.ll
index a910585e7f5d..b18e638a3a94 100644
--- a/test/CodeGen/AArch64/arm64-ccmp.ll
+++ b/test/CodeGen/AArch64/arm64-ccmp.ll
@@ -132,6 +132,7 @@ if.end:
 
 ; Floating point compare.
 ; CHECK: single_fcmp
+; CHECK: ; %bb.
 ; CHECK: cmp
 ; CHECK-NOT: b.
 ; CHECK: fccmp {{.*}}, #8, ge
@@ -448,7 +449,7 @@ define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) {
 ; Test the IR CCs that expand to two cond codes.
 
 ; CHECK-LABEL: select_and_olt_one:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d2, d3, #4, mi
 ; CHECK-NEXT: fccmp d2, d3, #1, ne
@@ -463,7 +464,7 @@ define i32 @select_and_olt_one(double %v0, double %v1, double %v2, double %v3, i
 }
 
 ; CHECK-LABEL: select_and_one_olt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d0, d1, #1, ne
 ; CHECK-NEXT: fccmp d2, d3, #0, vc
@@ -478,7 +479,7 @@ define i32 @select_and_one_olt(double %v0, double %v1, double %v2, double %v3, i
 }
 
 ; CHECK-LABEL: select_and_olt_ueq:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d2, d3, #0, mi
 ; CHECK-NEXT: fccmp d2, d3, #8, le
@@ -493,7 +494,7 @@ define i32 @select_and_olt_ueq(double %v0, double %v1, double %v2, double %v3, i
 }
 
 ; CHECK-LABEL: select_and_ueq_olt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d0, d1, #8, le
 ; CHECK-NEXT: fccmp d2, d3, #0, pl
@@ -508,7 +509,7 @@ define i32 @select_and_ueq_olt(double %v0, double %v1, double %v2, double %v3, i
 }
 
 ; CHECK-LABEL: select_or_olt_one:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d2, d3, #0, pl
 ; CHECK-NEXT: fccmp d2, d3, #8, le
@@ -523,7 +524,7 @@ define i32 @select_or_olt_one(double %v0, double %v1, double %v2, double %v3, i3
 }
 
 ; CHECK-LABEL: select_or_one_olt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d0, d1, #1, ne
 ; CHECK-NEXT: fccmp d2, d3, #8, vs
@@ -538,7 +539,7 @@ define i32 @select_or_one_olt(double %v0, double %v1, double %v2, double %v3, i3
 }
 
 ; CHECK-LABEL: select_or_olt_ueq:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d2, d3, #4, pl
 ; CHECK-NEXT: fccmp d2, d3, #1, ne
@@ -553,7 +554,7 @@ define i32 @select_or_olt_ueq(double %v0, double %v1, double %v2, double %v3, i3
 }
 
 ; CHECK-LABEL: select_or_ueq_olt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d0, d1, #8, le
 ; CHECK-NEXT: fccmp d2, d3, #8, mi
@@ -568,7 +569,7 @@ define i32 @select_or_ueq_olt(double %v0, double %v1, double %v2, double %v3, i3
 }
 
 ; CHECK-LABEL: select_or_olt_ogt_ueq:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d2, d3, #0, pl
 ; CHECK-NEXT: fccmp d4, d5, #4, le
@@ -586,7 +587,7 @@ define i32 @select_or_olt_ogt_ueq(double %v0, double %v1, double %v2, double %v3
 }
 
 ; CHECK-LABEL: select_or_olt_ueq_ogt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-NEXT: fcmp d0, d1
 ; CHECK-NEXT: fccmp d2, d3, #4, pl
 ; CHECK-NEXT: fccmp d2, d3, #1, ne
@@ -606,7 +607,7 @@ define i32 @select_or_olt_ueq_ogt(double %v0, double %v1, double %v2, double %v3
 ; Verify that we correctly promote f16.
 
 ; CHECK-LABEL: half_select_and_olt_oge:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-DAG:  fcvt [[S0:s[0-9]+]], h0
 ; CHECK-DAG:  fcvt [[S1:s[0-9]+]], h1
 ; CHECK-NEXT: fcmp [[S0]], [[S1]]
@@ -624,7 +625,7 @@ define i32 @half_select_and_olt_oge(half %v0, half %v1, half %v2, half %v3, i32
 }
 
 ; CHECK-LABEL: half_select_and_olt_one:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
 ; CHECK-DAG:  fcvt [[S0:s[0-9]+]], h0
 ; CHECK-DAG:  fcvt [[S1:s[0-9]+]], h1
 ; CHECK-NEXT: fcmp [[S0]], [[S1]]
diff --git a/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll b/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
index a104b65ea861..3d23dcd3cd29 100644
--- a/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
+++ b/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
@@ -1,6 +1,6 @@
-; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
-; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
-; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
+; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=DISABLE
 
 ; CodeGenPrepare should move the zext into the block with the load
 ; so that SelectionDAG can select it with the load.
@@ -81,8 +81,8 @@ false:
 ; #1 will not be removed as we do not know anything about %b.
 ; #2 may not be merged with the load because %t is used in a comparison.
 ; Since two extensions may be emitted in the end instead of one before the
-; transformation, the regular heuristic does not apply the optimization. 
-; 
+; transformation, the regular heuristic does not apply the optimization.
+;
 ; OPTALL-LABEL: @promoteTwoArgZext
 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
 ;
@@ -637,12 +637,12 @@ define i64 @doNotPromoteBecauseOfPairedLoad(i32* %p, i32 %cst) {
 define i64 @promoteZextShl(i1 %c, i16* %P) {
 entry:
 ; OPTALL-LABEL: promoteZextShl
-; OPTALL-LABEL: entry:
+; OPTALL: entry:
 ; OPT: %[[LD:.*]] = load i16, i16* %P
 ; OPT: %[[EXT:.*]] = zext i16 %[[LD]] to i64
-; OPT-LABEL: if.then:
+; OPT: if.then:
 ; OPT: shl nsw i64 %[[EXT]], 1
-; DISABLE-LABEL: if.then:
+; DISABLE: if.then:
 ; DISABLE: %r = sext i32 %shl2 to i64
   %ld = load i16, i16* %P
   br i1 %c, label %end, label %if.then
diff --git a/test/CodeGen/AArch64/arm64-complex-ret.ll b/test/CodeGen/AArch64/arm64-complex-ret.ll
index 250edac553c7..b4a38544ca1a 100644
--- a/test/CodeGen/AArch64/arm64-complex-ret.ll
+++ b/test/CodeGen/AArch64/arm64-complex-ret.ll
@@ -2,6 +2,7 @@
 
 define { i192, i192, i21, i192 } @foo(i192) {
 ; CHECK-LABEL: foo:
-; CHECK: stp xzr, xzr, [x8]
+; CHECK-DAG: str xzr, [x8, #16]
+; CHECK-DAG: str q0, [x8]
   ret { i192, i192, i21, i192 } {i192 0, i192 1, i21 2, i192 3}
 }
diff --git a/test/CodeGen/AArch64/arm64-csldst-mmo.ll b/test/CodeGen/AArch64/arm64-csldst-mmo.ll
index 37cc5411aa31..c69779add59b 100644
--- a/test/CodeGen/AArch64/arm64-csldst-mmo.ll
+++ b/test/CodeGen/AArch64/arm64-csldst-mmo.ll
@@ -10,8 +10,8 @@
 ;
 ; CHECK: Before post-MI-sched:
 ; CHECK-LABEL: # Machine code for function test1:
-; CHECK: SU(2):   STRWui %WZR
-; CHECK: SU(3):   %X21<def>, %X20<def> = LDPXi %SP
+; CHECK: SU(2):   STRWui %wzr
+; CHECK: SU(3):   %x21, %x20 = LDPXi %sp
 ; CHECK:  Predecessors:
 ; CHECK-NEXT:   SU(0): Out
 ; CHECK-NEXT:   SU(0): Out
diff --git a/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll b/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll
index 1bbcf50ba73c..d43efa7ee794 100644
--- a/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll
+++ b/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll
@@ -3,7 +3,7 @@
 ; Check that the dead register definition pass is considering implicit defs.
 ; When rematerializing through truncates, the coalescer may produce instructions
 ; with dead defs, but live implicit-defs of subregs:
-; E.g. %X1<def, dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32
+; E.g. dead %x1 = MOVi64imm 2, implicit-def %w1; %x1:GPR64, %w1:GPR32
 ; These instructions are live, and their definitions should not be rewritten.
 ;
 ; <rdar://problem/16492408>
diff --git a/test/CodeGen/AArch64/arm64-dup.ll b/test/CodeGen/AArch64/arm64-dup.ll
index 28df305f59e1..bcb91e83ea6f 100644
--- a/test/CodeGen/AArch64/arm64-dup.ll
+++ b/test/CodeGen/AArch64/arm64-dup.ll
@@ -261,7 +261,7 @@ entry:
 define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone  {
 ; CHECK-LABEL: f:
 ; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: ins.s v0[1], w1
+; CHECK-NEXT: mov.s v0[1], w1
 ; CHECK-NEXT: ret
   %vecinit = insertelement <2 x i32> undef, i32 %a, i32 0
   %vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1
@@ -271,9 +271,9 @@ define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone  {
 define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone  {
 ; CHECK-LABEL: g:
 ; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: ins.s v0[1], w1
-; CHECK-NEXT: ins.s v0[2], w1
-; CHECK-NEXT: ins.s v0[3], w0
+; CHECK-NEXT: mov.s v0[1], w1
+; CHECK-NEXT: mov.s v0[2], w1
+; CHECK-NEXT: mov.s v0[3], w0
 ; CHECK-NEXT: ret
   %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
   %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
@@ -285,7 +285,7 @@ define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone  {
 define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone  {
 ; CHECK-LABEL: h:
 ; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ins.d v0[1], x1
+; CHECK-NEXT: mov.d v0[1], x1
 ; CHECK-NEXT: ret
   %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
   %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
diff --git a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll
index 05aa96997b57..c26bfa8bcfeb 100644
--- a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll
+++ b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll
@@ -4,9 +4,9 @@
 
 ; CHECK-SSA-LABEL: Machine code for function t1
 
-; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
-; CHECK-SSA-NOT: [[QUOTREG]]<def> =
-; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
+; CHECK-SSA: [[QUOTREG:%[0-9]+]]:gpr32 = SDIVWr
+; CHECK-SSA-NOT: [[QUOTREG]] =
+; CHECK-SSA: {{%[0-9]+}}:gpr32 = MSUBWrrr killed [[QUOTREG]]
 
 ; CHECK-SSA-LABEL: Machine code for function t2
 
diff --git a/test/CodeGen/AArch64/arm64-fcmp-opt.ll b/test/CodeGen/AArch64/arm64-fcmp-opt.ll
index e8b1557bac66..5155d49cc3fa 100644
--- a/test/CodeGen/AArch64/arm64-fcmp-opt.ll
+++ b/test/CodeGen/AArch64/arm64-fcmp-opt.ll
@@ -41,7 +41,7 @@ entry:
 define float @fcmp_oeq(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_oeq
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], eq
 
@@ -53,7 +53,7 @@ define float @fcmp_oeq(float %a, float %b) nounwind ssp {
 define float @fcmp_ogt(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_ogt
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], gt
 
@@ -65,7 +65,7 @@ define float @fcmp_ogt(float %a, float %b) nounwind ssp {
 define float @fcmp_oge(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_oge
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ge
 
@@ -77,7 +77,7 @@ define float @fcmp_oge(float %a, float %b) nounwind ssp {
 define float @fcmp_olt(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_olt
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], mi
 
@@ -89,7 +89,7 @@ define float @fcmp_olt(float %a, float %b) nounwind ssp {
 define float @fcmp_ole(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_ole
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ls
 
@@ -101,7 +101,7 @@ define float @fcmp_ole(float %a, float %b) nounwind ssp {
 define float @fcmp_ord(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_ord
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vc
   %cmp = fcmp ord float %a, %b
@@ -112,7 +112,7 @@ define float @fcmp_ord(float %a, float %b) nounwind ssp {
 define float @fcmp_uno(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_uno
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vs
   %cmp = fcmp uno float %a, %b
@@ -123,7 +123,7 @@ define float @fcmp_uno(float %a, float %b) nounwind ssp {
 define float @fcmp_ugt(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_ugt
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], hi
   %cmp = fcmp ugt float %a, %b
@@ -134,7 +134,7 @@ define float @fcmp_ugt(float %a, float %b) nounwind ssp {
 define float @fcmp_uge(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_uge
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], pl
   %cmp = fcmp uge float %a, %b
@@ -145,7 +145,7 @@ define float @fcmp_uge(float %a, float %b) nounwind ssp {
 define float @fcmp_ult(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_ult
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], lt
   %cmp = fcmp ult float %a, %b
@@ -156,7 +156,7 @@ define float @fcmp_ult(float %a, float %b) nounwind ssp {
 define float @fcmp_ule(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_ule
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], le
   %cmp = fcmp ule float %a, %b
@@ -167,7 +167,7 @@ define float @fcmp_ule(float %a, float %b) nounwind ssp {
 define float @fcmp_une(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_une
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ne
   %cmp = fcmp une float %a, %b
@@ -180,7 +180,7 @@ define float @fcmp_une(float %a, float %b) nounwind ssp {
 define float @fcmp_one(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_one
 ;	fcmp	s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], mi
 ; CHECK: fcsel s0, s[[ONE]], [[TMP]], gt
@@ -194,7 +194,7 @@ define float @fcmp_one(float %a, float %b) nounwind ssp {
 define float @fcmp_ueq(float %a, float %b) nounwind ssp {
 ; CHECK-LABEL: @fcmp_ueq
 ; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ZERO:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
 ; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], eq
 ; CHECK: fcsel s0, s[[ONE]], [[TMP]], vs
diff --git a/test/CodeGen/AArch64/arm64-fp128.ll b/test/CodeGen/AArch64/arm64-fp128.ll
index 164351ec71db..3561d8fcdff9 100644
--- a/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/test/CodeGen/AArch64/arm64-fp128.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone -aarch64-enable-atomic-cfg-tidy=0 < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone -aarch64-enable-atomic-cfg-tidy=0 < %s | FileCheck -enable-var-scope %s
 
 @lhs = global fp128 zeroinitializer, align 16
 @rhs = global fp128 zeroinitializer, align 16
@@ -195,7 +195,7 @@ define i32 @test_br_cc() {
 
 iftrue:
   ret i32 42
-; CHECK-NEXT: BB#
+; CHECK-NEXT: %bb.
 ; CHECK-NEXT: mov w0, #42
 ; CHECK: ret
 iffalse:
@@ -211,7 +211,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
   store fp128 %val, fp128* @lhs, align 16
 ; CHECK: tst w0, #0x1
 ; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: BB#
+; CHECK-NEXT: %bb.
 ; CHECK-NEXT: mov v[[VAL:[0-9]+]].16b, v0.16b
 ; CHECK-NEXT: [[IFFALSE]]:
 ; CHECK: str q[[VAL]], [{{x[0-9]+}}, :lo12:lhs]
@@ -262,7 +262,7 @@ define void @test_extend() {
 }
 
 define fp128 @test_neg(fp128 %in) {
-; CHECK: [[MINUS0:.LCPI[0-9]+_0]]:
+; CHECK: [[$MINUS0:.LCPI[0-9]+_0]]:
 ; Make sure the weird hex constant below *is* -0.0
 ; CHECK-NEXT: fp128 -0
 
@@ -272,7 +272,7 @@ define fp128 @test_neg(fp128 %in) {
   ; sure that doesn't happen.
   %ret = fsub fp128 0xL00000000000000008000000000000000, %in
 ; CHECK: mov v1.16b, v0.16b
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:[[MINUS0]]]
+; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:[[$MINUS0]]]
 ; CHECK: bl __subtf3
 
   ret fp128 %ret
diff --git a/test/CodeGen/AArch64/arm64-icmp-opt.ll b/test/CodeGen/AArch64/arm64-icmp-opt.ll
index 12eae0e88fbe..1ed5c5ee135c 100644
--- a/test/CodeGen/AArch64/arm64-icmp-opt.ll
+++ b/test/CodeGen/AArch64/arm64-icmp-opt.ll
@@ -7,7 +7,7 @@
 
 define i32 @t1(i64 %a) {
 ; CHECK-LABEL: t1:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    lsr x8, x0, #63
 ; CHECK-NEXT:    eor w0, w8, #0x1
 ; CHECK-NEXT:    ret
diff --git a/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
index a502800923fd..b63e739f577d 100644
--- a/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
+++ b/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
@@ -6176,11 +6176,11 @@ define <2 x double> @test_v2f64_post_reg_ld1lane(double* %bar, double** %ptr, i6
 ; Check for dependencies between the vector and the scalar load.
 define <4 x float> @test_v4f32_post_reg_ld1lane_dep_vec_on_load(float* %bar, float** %ptr, i64 %inc, <4 x float>* %dep_ptr_1, <4 x float>* %dep_ptr_2, <4 x float> %vec) {
 ; CHECK-LABEL: test_v4f32_post_reg_ld1lane_dep_vec_on_load:
-; CHECK: BB#0:
+; CHECK: %bb.0:
 ; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]
 ; CHECK-NEXT: str q0, [x3]
 ; CHECK-NEXT: ldr q0, [x4]
-; CHECK-NEXT: ins.s v0[1], v[[LD]][0]
+; CHECK-NEXT: mov.s v0[1], v[[LD]][0]
 ; CHECK-NEXT: add [[POST:x[0-9]]], x0, x2, lsl #2
 ; CHECK-NEXT: str [[POST]], [x1]
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/AArch64/arm64-jumptable.ll b/test/CodeGen/AArch64/arm64-jumptable.ll
index c7f213fa8464..f5c2ee6da0bf 100644
--- a/test/CodeGen/AArch64/arm64-jumptable.ll
+++ b/test/CodeGen/AArch64/arm64-jumptable.ll
@@ -21,7 +21,7 @@ bb3:
   store i32 3, i32* %to
   br label %exit
 bb4:
-  store i32 4, i32* %to
+  store i32 5, i32* %to
   br label %exit
 exit:
   ret void
diff --git a/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/test/CodeGen/AArch64/arm64-ldp-cluster.ll
index 64e535ca7499..75b02b9d9134 100644
--- a/test/CodeGen/AArch64/arm64-ldp-cluster.ll
+++ b/test/CodeGen/AArch64/arm64-ldp-cluster.ll
@@ -4,15 +4,15 @@
 
 ; Test ldr clustering.
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldr_int:BB#0
+; CHECK-LABEL: ldr_int:%bb.0
 ; CHECK: Cluster ld/st SU(1) - SU(2)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(1):   %{{[0-9]+}}:gpr32 = LDRWui
+; CHECK: SU(2):   %{{[0-9]+}}:gpr32 = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldr_int:BB#0
+; EXYNOS-LABEL: ldr_int:%bb.0
 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(1):   %{{[0-9]+}}:gpr32 = LDRWui
+; EXYNOS: SU(2):   %{{[0-9]+}}:gpr32 = LDRWui
 define i32 @ldr_int(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 1
   %tmp1 = load i32, i32* %p1, align 2
@@ -24,15 +24,15 @@ define i32 @ldr_int(i32* %a) nounwind {
 
 ; Test ldpsw clustering
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldp_sext_int:BB#0
+; CHECK-LABEL: ldp_sext_int:%bb.0
 ; CHECK: Cluster ld/st SU(1) - SU(2)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRSWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(1):   %{{[0-9]+}}:gpr64 = LDRSWui
+; CHECK: SU(2):   %{{[0-9]+}}:gpr64 = LDRSWui
 ; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_sext_int:BB#0
+; EXYNOS-LABEL: ldp_sext_int:%bb.0
 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRSWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(1):   %{{[0-9]+}}:gpr64 = LDRSWui
+; EXYNOS: SU(2):   %{{[0-9]+}}:gpr64 = LDRSWui
 define i64 @ldp_sext_int(i32* %p) nounwind {
   %tmp = load i32, i32* %p, align 4
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
@@ -45,15 +45,15 @@ define i64 @ldp_sext_int(i32* %p) nounwind {
 
 ; Test ldur clustering.
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldur_int:BB#0
+; CHECK-LABEL: ldur_int:%bb.0
 ; CHECK: Cluster ld/st SU(2) - SU(1)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDURWi
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDURWi
+; CHECK: SU(1):   %{{[0-9]+}}:gpr32 = LDURWi
+; CHECK: SU(2):   %{{[0-9]+}}:gpr32 = LDURWi
 ; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldur_int:BB#0
+; EXYNOS-LABEL: ldur_int:%bb.0
 ; EXYNOS: Cluster ld/st SU(2) - SU(1)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDURWi
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDURWi
+; EXYNOS: SU(1):   %{{[0-9]+}}:gpr32 = LDURWi
+; EXYNOS: SU(2):   %{{[0-9]+}}:gpr32 = LDURWi
 define i32 @ldur_int(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 -1
   %tmp1 = load i32, i32* %p1, align 2
@@ -65,15 +65,15 @@ define i32 @ldur_int(i32* %a) nounwind {
 
 ; Test sext + zext clustering.
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldp_half_sext_zext_int:BB#0
+; CHECK-LABEL: ldp_half_sext_zext_int:%bb.0
 ; CHECK: Cluster ld/st SU(3) - SU(4)
-; CHECK: SU(3):   %vreg{{[0-9]+}}<def> = LDRSWui
-; CHECK: SU(4):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; CHECK: SU(3):   %{{[0-9]+}}:gpr64 = LDRSWui
+; CHECK: SU(4):   undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0
+; EXYNOS-LABEL: ldp_half_sext_zext_int:%bb.0
 ; EXYNOS: Cluster ld/st SU(3) - SU(4)
-; EXYNOS: SU(3):   %vreg{{[0-9]+}}<def> = LDRSWui
-; EXYNOS: SU(4):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; EXYNOS: SU(3):   %{{[0-9]+}}:gpr64 = LDRSWui
+; EXYNOS: SU(4):   undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
 define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
   %tmp0 = load i64, i64* %q, align 4
   %tmp = load i32, i32* %p, align 4
@@ -88,15 +88,15 @@ define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
 
 ; Test zext + sext clustering.
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldp_half_zext_sext_int:BB#0
+; CHECK-LABEL: ldp_half_zext_sext_int:%bb.0
 ; CHECK: Cluster ld/st SU(3) - SU(4)
-; CHECK: SU(3):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
-; CHECK: SU(4):   %vreg{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(3):   undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
+; CHECK: SU(4):   %{{[0-9]+}}:gpr64 = LDRSWui
 ; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0
+; EXYNOS-LABEL: ldp_half_zext_sext_int:%bb.0
 ; EXYNOS: Cluster ld/st SU(3) - SU(4)
-; EXYNOS: SU(3):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
-; EXYNOS: SU(4):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(3):   undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
+; EXYNOS: SU(4):   %{{[0-9]+}}:gpr64 = LDRSWui
 define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
   %tmp0 = load i64, i64* %q, align 4
   %tmp = load i32, i32* %p, align 4
@@ -111,15 +111,15 @@ define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
 
 ; Verify we don't cluster volatile loads.
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldr_int_volatile:BB#0
+; CHECK-LABEL: ldr_int_volatile:%bb.0
 ; CHECK-NOT: Cluster ld/st
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(1):   %{{[0-9]+}}:gpr32 = LDRWui
+; CHECK: SU(2):   %{{[0-9]+}}:gpr32 = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldr_int_volatile:BB#0
+; EXYNOS-LABEL: ldr_int_volatile:%bb.0
 ; EXYNOS-NOT: Cluster ld/st
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(1):   %{{[0-9]+}}:gpr32 = LDRWui
+; EXYNOS: SU(2):   %{{[0-9]+}}:gpr32 = LDRWui
 define i32 @ldr_int_volatile(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 1
   %tmp1 = load volatile i32, i32* %p1, align 2
@@ -131,12 +131,12 @@ define i32 @ldr_int_volatile(i32* %a) nounwind {
 
 ; Test ldq clustering (no clustering for Exynos).
 ; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldq_cluster:BB#0
+; CHECK-LABEL: ldq_cluster:%bb.0
 ; CHECK: Cluster ld/st SU(1) - SU(3)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRQui
-; CHECK: SU(3):   %vreg{{[0-9]+}}<def> = LDRQui
+; CHECK: SU(1):   %{{[0-9]+}}:fpr128 = LDRQui
+; CHECK: SU(3):   %{{[0-9]+}}:fpr128 = LDRQui
 ; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldq_cluster:BB#0
+; EXYNOS-LABEL: ldq_cluster:%bb.0
 ; EXYNOS-NOT: Cluster ld/st
 define <2 x i64> @ldq_cluster(i64* %p) {
   %a1 = bitcast i64* %p to <2 x i64>*
diff --git a/test/CodeGen/AArch64/arm64-ldp.ll b/test/CodeGen/AArch64/arm64-ldp.ll
index 998ff9e895fb..388f18bf801a 100644
--- a/test/CodeGen/AArch64/arm64-ldp.ll
+++ b/test/CodeGen/AArch64/arm64-ldp.ll
@@ -79,6 +79,16 @@ define double @ldp_double(double* %p) nounwind {
   ret double %add
 }
 
+; CHECK-LABEL: ldp_doublex2
+; CHECK: ldp
+define <2 x double> @ldp_doublex2(<2 x double>* %p) nounwind {
+  %tmp = load <2 x double>, <2 x double>* %p, align 16
+  %add.ptr = getelementptr inbounds <2 x double>, <2 x double>* %p, i64 1
+  %tmp1 = load <2 x double>, <2 x double>* %add.ptr, align 16
+  %add = fadd <2 x double> %tmp, %tmp1
+  ret <2 x double> %add
+}
+
 ; Test the load/store optimizer---combine ldurs into a ldp, if appropriate
 define i32 @ldur_int(i32* %a) nounwind {
 ; CHECK-LABEL: ldur_int
@@ -157,7 +167,7 @@ define i64 @ldur_long(i64* %a) nounwind ssp {
 define float @ldur_float(float* %a) {
 ; CHECK-LABEL: ldur_float
 ; CHECK: ldp     [[DST1:s[0-9]+]], [[DST2:s[0-9]+]], [x0, #-8]
-; CHECK-NEXT: add     s{{[0-9]+}}, [[DST2]], [[DST1]]
+; CHECK-NEXT: fadd    s{{[0-9]+}}, [[DST2]], [[DST1]]
 ; CHECK-NEXT: ret
   %p1 = getelementptr inbounds float, float* %a, i64 -1
   %tmp1 = load float, float* %p1, align 2
@@ -170,7 +180,7 @@ define float @ldur_float(float* %a) {
 define double @ldur_double(double* %a) {
 ; CHECK-LABEL: ldur_double
 ; CHECK: ldp     [[DST1:d[0-9]+]], [[DST2:d[0-9]+]], [x0, #-16]
-; CHECK-NEXT: add     d{{[0-9]+}}, [[DST2]], [[DST1]]
+; CHECK-NEXT: fadd    d{{[0-9]+}}, [[DST2]], [[DST1]]
 ; CHECK-NEXT: ret
   %p1 = getelementptr inbounds double, double* %a, i64 -1
   %tmp1 = load double, double* %p1, align 2
@@ -180,6 +190,19 @@ define double @ldur_double(double* %a) {
   ret double %tmp3
 }
 
+define <2 x double> @ldur_doublex2(<2 x double>* %a) {
+; CHECK-LABEL: ldur_doublex2
+; CHECK: ldp     q[[DST1:[0-9]+]], q[[DST2:[0-9]+]], [x0, #-32]
+; CHECK-NEXT: fadd    v{{[0-9]+}}.2d, v[[DST2]].2d, v[[DST1]].2d
+; CHECK-NEXT: ret
+  %p1 = getelementptr inbounds <2 x double>, <2 x double>* %a, i64 -1
+  %tmp1 = load <2 x double>, <2 x double>* %p1, align 2
+  %p2 = getelementptr inbounds <2 x double>, <2 x double>* %a, i64 -2
+  %tmp2 = load <2 x double>, <2 x double>* %p2, align 2
+  %tmp3 = fadd <2 x double> %tmp1, %tmp2
+  ret <2 x double> %tmp3
+}
+
 ; Now check some boundary conditions
 define i64 @pairUpBarelyIn(i64* %a) nounwind ssp {
 ; CHECK-LABEL: pairUpBarelyIn
diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
index 307d1ec1aa8c..07df9cb32dba 100644
--- a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
+++ b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
@@ -8,7 +8,7 @@
 ;
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: main
-; CHECK: *** Final schedule for BB#2 ***
+; CHECK: *** Final schedule for %bb.2 ***
 ; CHECK: MADDWrrr
 ; CHECK: ADDWri
 ; CHECK: ********** INTERVALS **********
@@ -83,8 +83,8 @@ for.end:                                          ; preds = %for.cond
 ; after it, this test checks to make sure there are more than one.
 ;
 ; CHECK: ********** MI Scheduling **********
-; CHECK: neon4xfloat:BB#0
-; CHECK: *** Final schedule for BB#0 ***
+; CHECK: neon4xfloat:%bb.0
+; CHECK: *** Final schedule for %bb.0 ***
 ; CHECK: FDIVv4f32
 ; CHECK: FADDv4f32
 ; CHECK: FADDv4f32
@@ -130,7 +130,7 @@ declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8*)
 ; are otherwise ready are jammed in the pending queue.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: testResourceConflict
-; CHECK: *** Final schedule for BB#0 ***
+; CHECK: *** Final schedule for %bb.0 ***
 ; CHECK: BRK
 ; CHECK: ********** INTERVALS **********
 define void @testResourceConflict(float* %ptr) {
@@ -178,7 +178,7 @@ declare void @llvm.trap()
 ; Resource contention on LDST.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: testLdStConflict
-; CHECK: *** Final schedule for BB#1 ***
+; CHECK: *** Final schedule for %bb.1 ***
 ; CHECK: LD4Fourv2d
 ; CHECK: STRQui
 ; CHECK: ********** INTERVALS **********
diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
index 82ba18ce72ca..711d2f7397b0 100644
--- a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
+++ b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
@@ -8,10 +8,10 @@
 ;
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ; CHECK: ********** MI Scheduling **********
-; CHECK: main:BB#2
+; CHECK: main:%bb.2
 ; CHECK: LDR
 ; CHECK: Latency : 4
-; CHECK: *** Final schedule for BB#2 ***
+; CHECK: *** Final schedule for %bb.2 ***
 ; CHECK: LDR
 ; CHECK: LDR
 ; CHECK-NOT: LDR
diff --git a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
index ad4feef7280f..bbb699bbb468 100644
--- a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
+++ b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
@@ -6,10 +6,10 @@
 ;
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: shiftable
-; CHECK: SU(2):   %vreg2<def> = SUBXri %vreg1, 20, 0
+; CHECK: SU(2):   %2:gpr64common = SUBXri %1, 20, 0
 ; CHECK:   Successors:
-; CHECK-NEXT:    SU(4): Data Latency=1 Reg=%vreg2
-; CHECK-NEXT:    SU(3): Data Latency=2 Reg=%vreg2
+; CHECK-NEXT:    SU(4): Data Latency=1 Reg=%2
+; CHECK-NEXT:    SU(3): Data Latency=2 Reg=%2
 ; CHECK: ********** INTERVALS **********
 define i64 @shiftable(i64 %A, i64 %B) {
         %tmp0 = sub i64 %B, 20
diff --git a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
index 9cbf0cb3803a..36de403a0c8f 100644
--- a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
+++ b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
@@ -4,16 +4,16 @@
 ; Test for bug in misched memory dependency calculation.
 ;
 ; CHECK: ********** MI Scheduling **********
-; CHECK: misched_bug:BB#0 entry
-; CHECK: SU(2):   %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0
+; CHECK: misched_bug:%bb.0 entry
+; CHECK: SU(2):   %2:gpr32 = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0
 ; CHECK:   Successors:
-; CHECK-NEXT:    SU(5): Data Latency=4 Reg=%vreg2
+; CHECK-NEXT:    SU(5): Data Latency=4 Reg=%2
 ; CHECK-NEXT:    SU(4): Ord  Latency=0
-; CHECK: SU(3):   STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
+; CHECK: SU(3):   STRWui %wzr, %0, 0; mem:ST4[%ptr1] GPR64common:%0
 ; CHECK:   Successors:
 ; CHECK: SU(4): Ord  Latency=0
-; CHECK: SU(4):   STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
-; CHECK: SU(5):   %W0<def> = COPY %vreg2; GPR32:%vreg2
+; CHECK: SU(4):   STRWui %wzr, %1, 0; mem:ST4[%ptr2] GPR64common:%1
+; CHECK: SU(5):   %w0 = COPY %2; GPR32:%2
 ; CHECK: ** ScheduleDAGMI::schedule picking next node
 define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
 entry:
diff --git a/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/test/CodeGen/AArch64/arm64-misched-multimmo.ll
index 75f45da0e48f..47f2ec790c7a 100644
--- a/test/CodeGen/AArch64/arm64-misched-multimmo.ll
+++ b/test/CodeGen/AArch64/arm64-misched-multimmo.ll
@@ -8,11 +8,11 @@
 ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
 ;
 ; CHECK-LABEL: # Machine code for function foo:
-; CHECK: SU(2):   %W{{[0-9]+}}<def>, %W{{[0-9]+}}<def> = LDPWi
+; CHECK: SU(2):   renamable %w{{[0-9]+}}, renamable %w{{[0-9]+}} = LDPWi
 ; CHECK: Successors:
 ; CHECK-NOT: ch SU(4)
 ; CHECK: SU(3)
-; CHECK: SU(4):   STRWui %WZR, %X{{[0-9]+}}
+; CHECK: SU(4):   STRWui %wzr, renamable %x{{[0-9]+}}
 define i32 @foo() {
 entry:
   %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
diff --git a/test/CodeGen/AArch64/arm64-narrow-st-merge.ll b/test/CodeGen/AArch64/arm64-narrow-st-merge.ll
index ec7c227e1699..b48f3b46cb46 100644
--- a/test/CodeGen/AArch64/arm64-narrow-st-merge.ll
+++ b/test/CodeGen/AArch64/arm64-narrow-st-merge.ll
@@ -19,7 +19,7 @@ entry:
 }
 
 ; CHECK-LABEL: Strh_zero_4
-; CHECK: stp wzr, wzr
+; CHECK: str xzr
 ; CHECK-STRICT-LABEL: Strh_zero_4
 ; CHECK-STRICT: strh wzr
 ; CHECK-STRICT: strh wzr
@@ -137,7 +137,7 @@ entry:
 }
 
 ; CHECK-LABEL: Sturh_zero_4
-; CHECK: stp wzr, wzr
+; CHECK: stur xzr
 ; CHECK-STRICT-LABEL: Sturh_zero_4
 ; CHECK-STRICT: sturh wzr
 ; CHECK-STRICT: sturh wzr
diff --git a/test/CodeGen/AArch64/arm64-neon-2velem.ll b/test/CodeGen/AArch64/arm64-neon-2velem.ll
index 7b2433099031..d22bfc76d1d5 100644
--- a/test/CodeGen/AArch64/arm64-neon-2velem.ll
+++ b/test/CodeGen/AArch64/arm64-neon-2velem.ll
@@ -3147,3 +3147,24 @@ entry:
 	%s = fsub <4 x float> %0, %1
   ret <4 x float> %s
 }
+
+define <2 x float> @test_vfma_lane_simdinstr_opt_pass_caching_a57(<2 x float> %a, <2 x float> %b, <2 x float> %v) "target-cpu"="cortex-a57" {
+; CHECK-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_a57:
+; CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
+; CHECK-NEXT: ret
+entry:
+  %lane = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 1, i32 1>
+  %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
+  ret <2 x float> %0
+}
+
+define <2 x float> @test_vfma_lane_simdinstr_opt_pass_caching_m1(<2 x float> %a, <2 x float> %b, <2 x float> %v) "target-cpu"="exynos-m1" {
+; CHECK-LABEL: test_vfma_lane_simdinstr_opt_pass_caching_m1:
+; CHECK: dup  [[x:v[0-9]+]].2s, {{v[0-9]+}}.s[1]
+; CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, [[x]].2s
+; CHECK-NEXT: ret
+entry:
+  %lane = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 1, i32 1>
+  %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %lane, <2 x float> %b, <2 x float> %a)
+  ret <2 x float> %0
+}
diff --git a/test/CodeGen/AArch64/arm64-neon-copy.ll b/test/CodeGen/AArch64/arm64-neon-copy.ll
index 16834b7e315b..84df9d6ac0cc 100644
--- a/test/CodeGen/AArch64/arm64-neon-copy.ll
+++ b/test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -3,56 +3,56 @@
 
 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
 ; CHECK-LABEL: ins16bw:
-; CHECK: ins {{v[0-9]+}}.b[15], {{w[0-9]+}}
+; CHECK: mov {{v[0-9]+}}.b[15], {{w[0-9]+}}
   %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15
   ret <16 x i8> %tmp3
 }
 
 define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {
 ; CHECK-LABEL: ins8hw:
-; CHECK: ins {{v[0-9]+}}.h[6], {{w[0-9]+}}
+; CHECK: mov {{v[0-9]+}}.h[6], {{w[0-9]+}}
   %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6
   ret <8 x i16> %tmp3
 }
 
 define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {
 ; CHECK-LABEL: ins4sw:
-; CHECK: ins {{v[0-9]+}}.s[2], {{w[0-9]+}}
+; CHECK: mov {{v[0-9]+}}.s[2], {{w[0-9]+}}
   %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2
   ret <4 x i32> %tmp3
 }
 
 define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {
 ; CHECK-LABEL: ins2dw:
-; CHECK: ins {{v[0-9]+}}.d[1], {{x[0-9]+}}
+; CHECK: mov {{v[0-9]+}}.d[1], {{x[0-9]+}}
   %tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1
   ret <2 x i64> %tmp3
 }
 
 define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {
 ; CHECK-LABEL: ins8bw:
-; CHECK: ins {{v[0-9]+}}.b[5], {{w[0-9]+}}
+; CHECK: mov {{v[0-9]+}}.b[5], {{w[0-9]+}}
   %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5
   ret <8 x i8> %tmp3
 }
 
 define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {
 ; CHECK-LABEL: ins4hw:
-; CHECK: ins {{v[0-9]+}}.h[3], {{w[0-9]+}}
+; CHECK: mov {{v[0-9]+}}.h[3], {{w[0-9]+}}
   %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3
   ret <4 x i16> %tmp3
 }
 
 define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {
 ; CHECK-LABEL: ins2sw:
-; CHECK: ins {{v[0-9]+}}.s[1], {{w[0-9]+}}
+; CHECK: mov {{v[0-9]+}}.s[1], {{w[0-9]+}}
   %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
   ret <2 x i32> %tmp3
 }
 
 define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
 ; CHECK-LABEL: ins16b16:
-; CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
+; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
   %tmp3 = extractelement <16 x i8> %tmp1, i32 2
   %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
   ret <16 x i8> %tmp4
@@ -60,7 +60,7 @@ define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
 
 define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
 ; CHECK-LABEL: ins8h8:
-; CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
+; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <8 x i16> %tmp1, i32 2
   %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
   ret <8 x i16> %tmp4
@@ -68,7 +68,7 @@ define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
 
 define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
 ; CHECK-LABEL: ins4s4:
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x i32> %tmp1, i32 2
   %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
   ret <4 x i32> %tmp4
@@ -76,7 +76,7 @@ define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
 
 define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
 ; CHECK-LABEL: ins2d2:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <2 x i64> %tmp1, i32 0
   %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
   ret <2 x i64> %tmp4
@@ -84,7 +84,7 @@ define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
 
 define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
 ; CHECK-LABEL: ins4f4:
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x float> %tmp1, i32 2
   %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
   ret <4 x float> %tmp4
@@ -92,7 +92,7 @@ define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
 
 define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
 ; CHECK-LABEL: ins2df2:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <2 x double> %tmp1, i32 0
   %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
   ret <2 x double> %tmp4
@@ -100,7 +100,7 @@ define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
 
 define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
 ; CHECK-LABEL: ins8b16:
-; CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
+; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
   %tmp3 = extractelement <8 x i8> %tmp1, i32 2
   %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
   ret <16 x i8> %tmp4
@@ -108,7 +108,7 @@ define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
 
 define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
 ; CHECK-LABEL: ins4h8:
-; CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
+; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <4 x i16> %tmp1, i32 2
   %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
   ret <8 x i16> %tmp4
@@ -116,7 +116,7 @@ define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
 
 define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
 ; CHECK-LABEL: ins2s4:
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
   %tmp3 = extractelement <2 x i32> %tmp1, i32 1
   %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
   ret <4 x i32> %tmp4
@@ -124,7 +124,7 @@ define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
 
 define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
 ; CHECK-LABEL: ins1d2:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <1 x i64> %tmp1, i32 0
   %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
   ret <2 x i64> %tmp4
@@ -132,7 +132,7 @@ define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
 
 define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
 ; CHECK-LABEL: ins2f4:
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
   %tmp3 = extractelement <2 x float> %tmp1, i32 1
   %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
   ret <4 x float> %tmp4
@@ -140,7 +140,7 @@ define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
 
 define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
 ; CHECK-LABEL: ins1f2:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
   %tmp3 = extractelement <1 x double> %tmp1, i32 0
   %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
   ret <2 x double> %tmp4
@@ -148,7 +148,7 @@ define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
 
 define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
 ; CHECK-LABEL: ins16b8:
-; CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
+; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
   %tmp3 = extractelement <16 x i8> %tmp1, i32 2
   %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
   ret <8 x i8> %tmp4
@@ -156,7 +156,7 @@ define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
 
 define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
 ; CHECK-LABEL: ins8h4:
-; CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
+; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <8 x i16> %tmp1, i32 2
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
   ret <4 x i16> %tmp4
@@ -164,7 +164,7 @@ define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
 
 define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
 ; CHECK-LABEL: ins4s2:
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x i32> %tmp1, i32 2
   %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
   ret <2 x i32> %tmp4
@@ -172,7 +172,7 @@ define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
 
 define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
 ; CHECK-LABEL: ins2d1:
-; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <2 x i64> %tmp1, i32 0
   %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
   ret <1 x i64> %tmp4
@@ -180,7 +180,7 @@ define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
 
 define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
 ; CHECK-LABEL: ins4f2:
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x float> %tmp1, i32 2
   %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
   ret <2 x float> %tmp4
@@ -188,7 +188,7 @@ define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
 
 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins2f1:
-; CHECK: mov {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+; CHECK: dup {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
   %tmp3 = extractelement <2 x double> %tmp1, i32 1
   %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
   ret <1 x double> %tmp4
@@ -196,7 +196,7 @@ define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
 
 define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
 ; CHECK-LABEL: ins8b8:
-; CHECK: ins {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
+; CHECK: mov {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
   %tmp3 = extractelement <8 x i8> %tmp1, i32 2
   %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
   ret <8 x i8> %tmp4
@@ -204,7 +204,7 @@ define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
 
 define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
 ; CHECK-LABEL: ins4h4:
-; CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
+; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
   %tmp3 = extractelement <4 x i16> %tmp1, i32 2
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
   ret <4 x i16> %tmp4
@@ -212,7 +212,7 @@ define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
 
 define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
 ; CHECK-LABEL: ins2s2:
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
   %tmp3 = extractelement <2 x i32> %tmp1, i32 0
   %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
   ret <2 x i32> %tmp4
@@ -220,7 +220,7 @@ define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
 
 define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
 ; CHECK-LABEL: ins1d1:
-; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
   %tmp3 = extractelement <1 x i64> %tmp1, i32 0
   %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
   ret <1 x i64> %tmp4
@@ -228,7 +228,7 @@ define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
 
 define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
 ; CHECK-LABEL: ins2f2:
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
   %tmp3 = extractelement <2 x float> %tmp1, i32 0
   %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
   ret <2 x float> %tmp4
@@ -236,7 +236,7 @@ define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
 
 define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins1df1:
-; CHECK-NOT: ins {{v[0-9]+}}
+; CHECK-NOT: mov {{v[0-9]+}}
   %tmp3 = extractelement <1 x double> %tmp1, i32 0
   %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
   ret <1 x double> %tmp4
@@ -388,28 +388,28 @@ define i64 @smovx2s(<2 x i32> %tmp1) {
 
 define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {
 ; CHECK-LABEL: test_vcopy_lane_s8:
-; CHECK: ins  {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
+; CHECK: mov  {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
   %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7>
   ret <8 x i8> %vset_lane
 }
 
 define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {
 ; CHECK-LABEL: test_vcopyq_laneq_s8:
-; CHECK: ins  {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
+; CHECK: mov  {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
   %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 22, i32 15>
   ret <16 x i8> %vset_lane
 }
 
 define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {
 ; CHECK-LABEL: test_vcopy_lane_swap_s8:
-; CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
+; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
   %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
   ret <8 x i8> %vset_lane
 }
 
 define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {
 ; CHECK-LABEL: test_vcopyq_laneq_swap_s8:
-; CHECK: ins {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
+; CHECK: mov {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
   %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %vset_lane
 }
@@ -907,9 +907,9 @@ define <8 x i8> @getl(<16 x i8> %x) #0 {
 ; CHECK-DAG: and [[MASKED_IDX:x[0-9]+]], x0, #0x7
 ; CHECK: bfi [[PTR:x[0-9]+]], [[MASKED_IDX]], #1, #3
 ; CHECK-DAG: ldr h[[R:[0-9]+]], {{\[}}[[PTR]]{{\]}}
-; CHECK-DAG: ins v[[R]].h[1], v0.h[1]
-; CHECK-DAG: ins v[[R]].h[2], v0.h[2]
-; CHECK-DAG: ins v[[R]].h[3], v0.h[3]
+; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
+; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
+; CHECK-DAG: mov v[[R]].h[3], v0.h[3]
 define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) {
   %tmp = extractelement <8 x i16> %x, i32 %idx
   %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0
@@ -927,9 +927,9 @@ define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) {
 ; CHECK: bfi x9, [[MASKED_IDX]], #1, #2
 ; CHECK: st1 { v0.h }[0], [x9]
 ; CHECK-DAG: ldr d[[R:[0-9]+]]
-; CHECK-DAG: ins v[[R]].h[1], v0.h[1]
-; CHECK-DAG: ins v[[R]].h[2], v0.h[2]
-; CHECK-DAG: ins v[[R]].h[3], v0.h[3]
+; CHECK-DAG: mov v[[R]].h[1], v0.h[1]
+; CHECK-DAG: mov v[[R]].h[2], v0.h[2]
+; CHECK-DAG: mov v[[R]].h[3], v0.h[3]
 define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {
   %tmp = extractelement <8 x i16> %x, i32 0
   %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx
@@ -1125,7 +1125,7 @@ define <2 x i32> @test_concat_diff_v1i32_v1i32(i32 %a, i32 %b) {
 ; CHECK-LABEL: test_concat_diff_v1i32_v1i32:
 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
-; CHECK: ins {{v[0-9]+}}.s[1], w{{[0-9]+}}
+; CHECK: mov {{v[0-9]+}}.s[1], w{{[0-9]+}}
 entry:
   %c = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a)
   %d = insertelement <2 x i32> undef, i32 %c, i32 0
@@ -1137,7 +1137,7 @@ entry:
 
 define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
   ret <16 x i8> %vecinit30
@@ -1145,7 +1145,7 @@ entry:
 
 define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <8 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
@@ -1169,7 +1169,7 @@ entry:
 
 define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <16 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
@@ -1208,7 +1208,7 @@ entry:
 
 define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <8 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
@@ -1247,7 +1247,7 @@ entry:
 
 define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
   ret <8 x i16> %vecinit14
@@ -1255,7 +1255,7 @@ entry:
 
 define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <4 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
@@ -1271,7 +1271,7 @@ entry:
 
 define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <8 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
@@ -1294,7 +1294,7 @@ entry:
 
 define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <4 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
@@ -1317,7 +1317,7 @@ entry:
 
 define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   ret <4 x i32> %vecinit6
@@ -1325,7 +1325,7 @@ entry:
 
 define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <2 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -1337,7 +1337,7 @@ entry:
 
 define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
@@ -1352,7 +1352,7 @@ entry:
 
 define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecinit6 = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %vecinit6
@@ -1389,7 +1389,7 @@ entry:
 
 define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {
 ; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
 entry:
   %vecext = extractelement <1 x i64> %x, i32 0
   %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
diff --git a/test/CodeGen/AArch64/arm64-neon-v8.1a.ll b/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
index ae087ab8cf05..63e5710eb169 100644
--- a/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
+++ b/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
@@ -1,6 +1,8 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V8a
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+rdm -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mcpu=falkor -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mcpu=saphira -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -mattr=+v8.1a -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-V81a-apple
 
 declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
diff --git a/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll b/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
index 7efb4bf6d596..f61f98a4d511 100644
--- a/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
+++ b/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
@@ -36,7 +36,9 @@
 ; HOTNESS-NOT: Executing Pass
 ; HOTNESS: block-frequency: empty_func
 ; HOTNESS-NOT: Executing Pass
-; HOTNESS: Executing Pass 'AArch64 Assembly Printer'
+; HOTNESS: Executing Pass 'MachineDominator Tree Construction'
+; HOTNESS-NEXT: Executing Pass 'Machine Natural Loop Construction'
+; HOTNESS-NEXT: Executing Pass 'AArch64 Assembly Printer'
 
 ; HOTNESS: arm64-summary-remarks.ll:5:0: 1 instructions in function (hotness: 33)
 
@@ -45,6 +47,8 @@
 ; NO_HOTNESS-NEXT:  Freeing Pass 'Implement the 'patchable-function' attribute'
 ; NO_HOTNESS-NEXT: Executing Pass 'Lazy Machine Block Frequency Analysis'
 ; NO_HOTNESS-NEXT: Executing Pass 'Machine Optimization Remark Emitter'
+; NO_HOTNESS-NEXT: Executing Pass 'MachineDominator Tree Construction'
+; NO_HOTNESS-NEXT: Executing Pass 'Machine Natural Loop Construction'
 ; NO_HOTNESS-NEXT: Executing Pass 'AArch64 Assembly Printer'
 
 ; NO_HOTNESS: arm64-summary-remarks.ll:5:0: 1 instructions in function{{$}}
diff --git a/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll b/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
index f68a9debd5f2..ccd12cdf6744 100644
--- a/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
+++ b/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
@@ -13,7 +13,6 @@
 define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen:
-; CHECK:       Lcfi
 ; CHECK:       str x{{.+}}, [sp]
 ; CHECK-NEXT:  mov  x0, x{{.+}}
 ; CHECK:       Ltmp
@@ -22,7 +21,6 @@ entry:
 ; CHECK:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen:
-; FAST:        Lcfi
 ; FAST:        str x{{.+}}, [sp]
 ; FAST:        Ltmp
 ; FAST-NEXT:   mov   x16, #281470681743360
@@ -40,7 +38,6 @@ entry:
 define i64 @jscall_patchpoint_codegen2(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen2:
-; CHECK:       Lcfi
 ; CHECK:       orr w[[REG:[0-9]+]], wzr, #0x6
 ; CHECK-NEXT:  str x[[REG]], [sp, #24]
 ; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x4
@@ -53,7 +50,6 @@ entry:
 ; CHECK-NEXT:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen2:
-; FAST:        Lcfi
 ; FAST:        orr [[REG1:x[0-9]+]], xzr, #0x2
 ; FAST-NEXT:   orr [[REG2:w[0-9]+]], wzr, #0x4
 ; FAST-NEXT:   orr [[REG3:x[0-9]+]], xzr, #0x6
@@ -74,7 +70,6 @@ entry:
 define i64 @jscall_patchpoint_codegen3(i64 %callee) {
 entry:
 ; CHECK-LABEL: jscall_patchpoint_codegen3:
-; CHECK:       Lcfi
 ; CHECK:       mov  w[[REG:[0-9]+]], #10
 ; CHECK-NEXT:  str x[[REG]], [sp, #48]
 ; CHECK-NEXT:  orr w[[REG:[0-9]+]], wzr, #0x8
@@ -91,7 +86,6 @@ entry:
 ; CHECK-NEXT:  movk  x16, #48879
 ; CHECK-NEXT:  blr x16
 ; FAST-LABEL:  jscall_patchpoint_codegen3:
-; FAST:        Lcfi
 ; FAST:        orr [[REG1:x[0-9]+]], xzr, #0x2
 ; FAST-NEXT:   orr [[REG2:w[0-9]+]], wzr, #0x4
 ; FAST-NEXT:   orr [[REG3:x[0-9]+]], xzr, #0x6
diff --git a/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir b/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
index 9ad47c721c3a..43d20394be45 100644
--- a/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
+++ b/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
@@ -1,5 +1,5 @@
 # RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s
-# CHECK: %1 = ANDWri {{.*}}
+# CHECK: %1:gpr32common = ANDWri {{.*}}
 # CHECK-NEXT: %wzr = SUBSWri {{.*}}
 --- |
   define i32 @test01() nounwind {
diff --git a/test/CodeGen/AArch64/arm64-scvt.ll b/test/CodeGen/AArch64/arm64-scvt.ll
index 4697e1feff4b..d886d7cd846d 100644
--- a/test/CodeGen/AArch64/arm64-scvt.ll
+++ b/test/CodeGen/AArch64/arm64-scvt.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s
+; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-neon-syntax=apple | FileCheck -enable-var-scope %s
+; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck -enable-var-scope --check-prefix=CHECK-A57 %s
 ; rdar://13082402
 
 define float @t1(i32* nocapture %src) nounwind ssp {
@@ -439,7 +439,7 @@ entry:
 define float @sfct3(i32* nocapture %sp0) {
 ; CHECK-LABEL: sfct3:
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 1
@@ -500,7 +500,7 @@ entry:
 define float @sfct7(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct7:
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 %offset
@@ -574,7 +574,7 @@ entry:
 define double @sfct12(i64* nocapture %sp0) {
 ; CHECK-LABEL: sfct12:
 ; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 1
@@ -634,7 +634,7 @@ entry:
 define double @sfct16(i64* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct16:
 ; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i64, i64* %sp0, i64 %offset
@@ -684,7 +684,7 @@ define float @sfct18(i16* nocapture %sp0) {
 define float @sfct19(i32* nocapture %sp0) {
 ; CHECK-LABEL: sfct19:
 ; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[REGNUM]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
@@ -765,7 +765,7 @@ define double @sfct23(i32* nocapture %sp0) {
 define double @sfct24(i64* nocapture %sp0) {
 ; CHECK-LABEL: sfct24:
 ; CHECK: ldur d[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
+; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[REGNUM]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
   %bitcast = ptrtoint i64* %sp0 to i64
   %add = add i64 %bitcast, 1
diff --git a/test/CodeGen/AArch64/arm64-smaxv.ll b/test/CodeGen/AArch64/arm64-smaxv.ll
index fc975f352365..4ead34f5a69f 100644
--- a/test/CodeGen/AArch64/arm64-smaxv.ll
+++ b/test/CodeGen/AArch64/arm64-smaxv.ll
@@ -68,7 +68,7 @@ entry:
 define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:
 ; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2)
@@ -80,7 +80,7 @@ entry:
 define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:
 ; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2)
@@ -92,7 +92,7 @@ entry:
 define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:
 ; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2)
@@ -103,7 +103,7 @@ entry:
 define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:
 ; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2)
@@ -115,7 +115,7 @@ entry:
 define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop:
 ; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2)
@@ -127,7 +127,7 @@ entry:
 define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop:
 ; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2)
diff --git a/test/CodeGen/AArch64/arm64-sminv.ll b/test/CodeGen/AArch64/arm64-sminv.ll
index c721b0d5f324..15f874e4b439 100644
--- a/test/CodeGen/AArch64/arm64-sminv.ll
+++ b/test/CodeGen/AArch64/arm64-sminv.ll
@@ -68,7 +68,7 @@ entry:
 define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vminv_s8_used_by_laneop:
 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
@@ -80,7 +80,7 @@ entry:
 define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vminv_s16_used_by_laneop:
 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
@@ -92,7 +92,7 @@ entry:
 define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vminv_s32_used_by_laneop:
 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
@@ -103,7 +103,7 @@ entry:
 define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
@@ -115,7 +115,7 @@ entry:
 define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
@@ -127,7 +127,7 @@ entry:
 define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
 ; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
diff --git a/test/CodeGen/AArch64/arm64-spill-remarks-treshold-hotness.ll b/test/CodeGen/AArch64/arm64-spill-remarks-treshold-hotness.ll
new file mode 100644
index 000000000000..fe22296320fc
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-spill-remarks-treshold-hotness.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -aarch64-neon-syntax=apple -pass-remarks-missed=regalloc \
+; RUN:       -pass-remarks-with-hotness 2>&1 | FileCheck %s
+
+; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -aarch64-neon-syntax=apple -pass-remarks-missed=regalloc \
+; RUN:       -pass-remarks-with-hotness -pass-remarks-hotness-threshold=1 \
+; RUN:       2>&1 | FileCheck -check-prefix=THRESHOLD %s
+
+; CHECK: remark: /tmp/kk.c:3:20: 1 spills 1 reloads generated in loop{{$}}
+; THRESHOLD-NOT: remark
+
+define void @fpr128(<4 x float>* %p) nounwind ssp {
+entry:
+  br label %loop, !dbg !8
+
+loop:
+  %i = phi i32 [ 0, %entry], [ %i.2, %end2 ]
+  br label %loop2, !dbg !9
+
+loop2:
+  %j = phi i32 [ 0, %loop], [ %j.2, %loop2 ]
+  call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind
+  %j.2 = add i32 %j, 1
+  %c2 = icmp slt i32 %j.2, 100
+  br i1 %c2, label %loop2, label %end2
+
+end2:
+  call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind
+  %i.2 = add i32 %i, 1
+  %c = icmp slt i32 %i.2, 100
+  br i1 %c, label %loop, label %end
+
+end:
+  br label %loop3
+
+loop3:
+  %k = phi i32 [ 0, %end], [ %k.2, %loop3 ]
+  call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind
+  %k.2 = add i32 %k, 1
+  %c3 = icmp slt i32 %k.2, 100
+  br i1 %c3, label %loop3, label %end3, !dbg !10
+
+end3:
+  ret void
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4}
+!llvm.ident = !{!5}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug, enums: !2)
+!1 = !DIFile(filename: "/tmp/kk.c", directory: "/tmp")
+!2 = !{}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !{i32 1, !"PIC Level", i32 2}
+!5 = !{!"clang version 3.9.0 "}
+!6 = distinct !DISubprogram(name: "success", scope: !1, file: !1, line: 1, type: !7, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !2)
+!7 = !DISubroutineType(types: !2)
+!8 = !DILocation(line: 1, column: 20, scope: !6)
+!9 = !DILocation(line: 2, column: 20, scope: !6)
+!10 = !DILocation(line: 3, column: 20, scope: !6)
diff --git a/test/CodeGen/AArch64/arm64-st1.ll b/test/CodeGen/AArch64/arm64-st1.ll
index 28ee8fcf46fc..cce5be8ff223 100644
--- a/test/CodeGen/AArch64/arm64-st1.ll
+++ b/test/CodeGen/AArch64/arm64-st1.ll
@@ -1,4 +1,6 @@
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m1 | FileCheck --check-prefix=EXYNOS %s
+; The instruction latencies of Exynos-M1 trigger the transform we see under the Exynos check.
 
 define void @st1lane_16b(<16 x i8> %A, i8* %D) {
 ; CHECK-LABEL: st1lane_16b
@@ -375,6 +377,10 @@ declare void @llvm.aarch64.neon.st4lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i
 define void @st2_8b(<8 x i8> %A, <8 x i8> %B, i8* %P) nounwind {
 ; CHECK-LABEL: st2_8b
 ; CHECK: st2.8b
+; EXYNOS-LABEL: st2_8b
+; EXYNOS: zip1.8b
+; EXYNOS: zip2.8b
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, i8* %P)
 	ret void
 }
@@ -389,6 +395,17 @@ define void @st3_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %P) nounwind {
 define void @st4_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %P) nounwind {
 ; CHECK-LABEL: st4_8b
 ; CHECK: st4.8b
+; EXYNOS-LABEL: st4_8b
+; EXYNOS: zip1.8b
+; EXYNOS: zip2.8b
+; EXYNOS: zip1.8b
+; EXYNOS: zip2.8b
+; EXYNOS: zip1.8b
+; EXYNOS: zip2.8b
+; EXYNOS: stp
+; EXYNOS: zip1.8b
+; EXYNOS: zip2.8b
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %P)
 	ret void
 }
@@ -400,6 +417,10 @@ declare void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x
 define void @st2_16b(<16 x i8> %A, <16 x i8> %B, i8* %P) nounwind {
 ; CHECK-LABEL: st2_16b
 ; CHECK: st2.16b
+; EXYNOS-LABEL: st2_16b
+; EXYNOS: zip1.16b
+; EXYNOS: zip2.16b
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st2.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, i8* %P)
 	ret void
 }
@@ -414,6 +435,17 @@ define void @st3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %P) nounwind
 define void @st4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %P) nounwind {
 ; CHECK-LABEL: st4_16b
 ; CHECK: st4.16b
+; EXYNOS-LABEL: st4_16b
+; EXYNOS: zip1.16b
+; EXYNOS: zip2.16b
+; EXYNOS: zip1.16b
+; EXYNOS: zip2.16b
+; EXYNOS: zip1.16b
+; EXYNOS: zip2.16b
+; EXYNOS: stp
+; EXYNOS: zip1.16b
+; EXYNOS: zip2.16b
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %P)
 	ret void
 }
@@ -425,6 +457,10 @@ declare void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>,
 define void @st2_4h(<4 x i16> %A, <4 x i16> %B, i16* %P) nounwind {
 ; CHECK-LABEL: st2_4h
 ; CHECK: st2.4h
+; EXYNOS-LABEL: st2_4h
+; EXYNOS: zip1.4h
+; EXYNOS: zip2.4h
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st2.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, i16* %P)
 	ret void
 }
@@ -439,6 +475,17 @@ define void @st3_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %P) nounwind
 define void @st4_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %P) nounwind {
 ; CHECK-LABEL: st4_4h
 ; CHECK: st4.4h
+; EXYNOS-LABEL: st4_4h
+; EXYNOS: zip1.4h
+; EXYNOS: zip2.4h
+; EXYNOS: zip1.4h
+; EXYNOS: zip2.4h
+; EXYNOS: zip1.4h
+; EXYNOS: zip2.4h
+; EXYNOS: stp
+; EXYNOS: zip1.4h
+; EXYNOS: zip2.4h
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %P)
 	ret void
 }
@@ -450,6 +497,10 @@ declare void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>,
 define void @st2_8h(<8 x i16> %A, <8 x i16> %B, i16* %P) nounwind {
 ; CHECK-LABEL: st2_8h
 ; CHECK: st2.8h
+; EXYNOS-LABEL: st2_8h
+; EXYNOS: zip1.8h
+; EXYNOS: zip2.8h
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st2.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, i16* %P)
 	ret void
 }
@@ -464,6 +515,17 @@ define void @st3_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %P) nounwind
 define void @st4_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %P) nounwind {
 ; CHECK-LABEL: st4_8h
 ; CHECK: st4.8h
+; EXYNOS-LABEL: st4_8h
+; EXYNOS: zip1.8h
+; EXYNOS: zip2.8h
+; EXYNOS: zip1.8h
+; EXYNOS: zip2.8h
+; EXYNOS: zip1.8h
+; EXYNOS: zip2.8h
+; EXYNOS: stp
+; EXYNOS: zip1.8h
+; EXYNOS: zip2.8h
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %P)
 	ret void
 }
@@ -475,6 +537,10 @@ declare void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>,
 define void @st2_2s(<2 x i32> %A, <2 x i32> %B, i32* %P) nounwind {
 ; CHECK-LABEL: st2_2s
 ; CHECK: st2.2s
+; EXYNOS-LABEL: st2_2s
+; EXYNOS: zip1.2s
+; EXYNOS: zip2.2s
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st2.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, i32* %P)
 	ret void
 }
@@ -489,6 +555,17 @@ define void @st3_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %P) nounwind
 define void @st4_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %P) nounwind {
 ; CHECK-LABEL: st4_2s
 ; CHECK: st4.2s
+; EXYNOS-LABEL: st4_2s
+; EXYNOS: zip1.2s
+; EXYNOS: zip2.2s
+; EXYNOS: zip1.2s
+; EXYNOS: zip2.2s
+; EXYNOS: zip1.2s
+; EXYNOS: zip2.2s
+; EXYNOS: stp
+; EXYNOS: zip1.2s
+; EXYNOS: zip2.2s
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %P)
 	ret void
 }
@@ -500,6 +577,10 @@ declare void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>,
 define void @st2_4s(<4 x i32> %A, <4 x i32> %B, i32* %P) nounwind {
 ; CHECK-LABEL: st2_4s
 ; CHECK: st2.4s
+; EXYNOS-LABEL: st2_4s
+; EXYNOS: zip1.4s
+; EXYNOS: zip2.4s
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, i32* %P)
 	ret void
 }
@@ -514,6 +595,17 @@ define void @st3_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %P) nounwind
 define void @st4_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %P) nounwind {
 ; CHECK-LABEL: st4_4s
 ; CHECK: st4.4s
+; EXYNOS-LABEL: st4_4s
+; EXYNOS: zip1.4s
+; EXYNOS: zip2.4s
+; EXYNOS: zip1.4s
+; EXYNOS: zip2.4s
+; EXYNOS: zip1.4s
+; EXYNOS: zip2.4s
+; EXYNOS: stp
+; EXYNOS: zip1.4s
+; EXYNOS: zip2.4s
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %P)
 	ret void
 }
@@ -551,6 +643,10 @@ declare void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>,
 define void @st2_2d(<2 x i64> %A, <2 x i64> %B, i64* %P) nounwind {
 ; CHECK-LABEL: st2_2d
 ; CHECK: st2.2d
+; EXYNOS-LABEL: st2_2d
+; EXYNOS: zip1.2d
+; EXYNOS: zip2.2d
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st2.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, i64* %P)
 	ret void
 }
@@ -565,6 +661,17 @@ define void @st3_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %P) nounwind
 define void @st4_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %P) nounwind {
 ; CHECK-LABEL: st4_2d
 ; CHECK: st4.2d
+; EXYNOS-LABEL: st4_2d
+; EXYNOS: zip1.2d
+; EXYNOS: zip2.2d
+; EXYNOS: zip1.2d
+; EXYNOS: zip2.2d
+; EXYNOS: zip1.2d
+; EXYNOS: zip2.2d
+; EXYNOS: stp
+; EXYNOS: zip1.2d
+; EXYNOS: zip2.2d
+; EXYNOS: stp
 	call void @llvm.aarch64.neon.st4.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %P)
 	ret void
 }
diff --git a/test/CodeGen/AArch64/arm64-storebytesmerge.ll b/test/CodeGen/AArch64/arm64-storebytesmerge.ll
new file mode 100644
index 000000000000..fb06131242d3
--- /dev/null
+++ b/test/CodeGen/AArch64/arm64-storebytesmerge.ll
@@ -0,0 +1,46 @@
+; RUN: llc  -mtriple=aarch64-linux-gnu -enable-misched=false < %s | FileCheck %s
+
+;target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+;target triple = "aarch64--linux-gnu"
+
+
+; CHECK-LABEL: test
+; CHECK: str     x30, [sp, #-16]!
+; CHECK: adrp    x8, q   
+; CHECK: ldr     x8, [x8, :lo12:q]
+; CHECK: stp     xzr, xzr, [x8] 
+; CHECK: bl f
+
+@q = external unnamed_addr global i16*, align 8
+
+; Function Attrs: nounwind
+define void @test() local_unnamed_addr #0 {
+entry:
+  br label %for.body453.i
+
+for.body453.i:                                    ; preds = %for.body453.i, %entry
+  br i1 undef, label %for.body453.i, label %for.end705.i
+
+for.end705.i:                                     ; preds = %for.body453.i
+  %0 = load i16*, i16** @q, align 8
+  %1 = getelementptr inbounds i16, i16* %0, i64 0
+  %2 = bitcast i16* %1 to <2 x i16>*
+  store <2 x i16> zeroinitializer, <2 x i16>* %2, align 2
+  %3 = getelementptr i16, i16* %1, i64 2
+  %4 = bitcast i16* %3 to <2 x i16>*
+  store <2 x i16> zeroinitializer, <2 x i16>* %4, align 2
+  %5 = getelementptr i16, i16* %1, i64 4
+  %6 = bitcast i16* %5 to <2 x i16>*
+  store <2 x i16> zeroinitializer, <2 x i16>* %6, align 2
+  %7 = getelementptr i16, i16* %1, i64 6
+  %8 = bitcast i16* %7 to <2 x i16>*
+  store <2 x i16> zeroinitializer, <2 x i16>* %8, align 2
+  call void @f() #2
+  unreachable
+}
+
+declare void @f() local_unnamed_addr #1
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+crc,+crypto,+fp-armv8,+neon" "unsafe-fp-math"="true" "use-soft-float"="false" }
+attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+crc,+crypto,+fp-armv8,+neon" "unsafe-fp-math"="true" "use-soft-float"="false" }
+attributes #2 = { nounwind }
diff --git a/test/CodeGen/AArch64/arm64-stp.ll b/test/CodeGen/AArch64/arm64-stp.ll
index cc4591c8aece..9239077c166b 100644
--- a/test/CodeGen/AArch64/arm64-stp.ll
+++ b/test/CodeGen/AArch64/arm64-stp.ll
@@ -36,6 +36,15 @@ define void @stp_double(double %a, double %b, double* nocapture %p) nounwind {
   ret void
 }
 
+; CHECK-LABEL: stp_doublex2
+; CHECK: stp q0, q1, [x0]
+define void @stp_doublex2(<2 x double> %a, <2 x double> %b, <2 x double>* nocapture %p) nounwind {
+  store <2 x double> %a, <2 x double>* %p, align 16
+  %add.ptr = getelementptr inbounds <2 x double>, <2 x double>* %p, i64 1
+  store <2 x double> %b, <2 x double>* %add.ptr, align 16
+  ret void
+}
+
 ; Test the load/store optimizer---combine ldurs into a ldp, if appropriate
 define void @stur_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
 ; CHECK-LABEL: stur_int
@@ -81,6 +90,17 @@ define void @stur_double(double %a, double %b, double* nocapture %p) nounwind {
   ret void
 }
 
+define void @stur_doublex2(<2 x double> %a, <2 x double> %b, <2 x double>* nocapture %p) nounwind {
+; CHECK-LABEL: stur_doublex2
+; CHECK: stp q{{[0-9]+}}, q{{[0-9]+}}, [x{{[0-9]+}}, #-32]
+; CHECK-NEXT: ret
+  %p1 = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -1
+  store <2 x double> %a, <2 x double>* %p1, align 2
+  %p2 = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -2
+  store <2 x double> %b, <2 x double>* %p2, align 2
+  ret void
+}
+
 define void @splat_v4i32(i32 %v, i32 *%p) {
 entry:
 
@@ -106,9 +126,9 @@ entry:
 ; CHECK-LABEL: nosplat_v4i32:
 ; CHECK: str w0,
 ; CHECK: ldr q[[REG1:[0-9]+]],
-; CHECK-DAG: ins v[[REG1]].s[1], w0
-; CHECK-DAG: ins v[[REG1]].s[2], w0
-; CHECK-DAG: ins v[[REG1]].s[3], w0
+; CHECK-DAG: mov v[[REG1]].s[1], w0
+; CHECK-DAG: mov v[[REG1]].s[2], w0
+; CHECK-DAG: mov v[[REG1]].s[3], w0
 ; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8
 ; CHECK: stp d[[REG1]], d[[REG2]], [x1]
 ; CHECK: ret
@@ -128,9 +148,9 @@ define void @nosplat2_v4i32(i32 %v, i32 *%p, <4 x i32> %vin) {
 entry:
 
 ; CHECK-LABEL: nosplat2_v4i32:
-; CHECK: ins v[[REG1]].s[1], w0
-; CHECK-DAG: ins v[[REG1]].s[2], w0
-; CHECK-DAG: ins v[[REG1]].s[3], w0
+; CHECK: mov v[[REG1]].s[1], w0
+; CHECK-DAG: mov v[[REG1]].s[2], w0
+; CHECK-DAG: mov v[[REG1]].s[3], w0
 ; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8
 ; CHECK: stp d[[REG1]], d[[REG2]], [x1]
 ; CHECK: ret
diff --git a/test/CodeGen/AArch64/arm64-umaxv.ll b/test/CodeGen/AArch64/arm64-umaxv.ll
index c60489364275..fb4124309f75 100644
--- a/test/CodeGen/AArch64/arm64-umaxv.ll
+++ b/test/CodeGen/AArch64/arm64-umaxv.ll
@@ -89,7 +89,7 @@ return:
 define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:
 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
@@ -101,7 +101,7 @@ entry:
 define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:
 ; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)
@@ -113,7 +113,7 @@ entry:
 define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:
 ; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)
@@ -124,7 +124,7 @@ entry:
 define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:
 ; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)
@@ -136,7 +136,7 @@ entry:
 define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop:
 ; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)
@@ -148,7 +148,7 @@ entry:
 define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop:
 ; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)
diff --git a/test/CodeGen/AArch64/arm64-uminv.ll b/test/CodeGen/AArch64/arm64-uminv.ll
index 124e7969f6be..3a70e76a3905 100644
--- a/test/CodeGen/AArch64/arm64-uminv.ll
+++ b/test/CodeGen/AArch64/arm64-uminv.ll
@@ -89,7 +89,7 @@ return:
 define <8 x i8> @test_vminv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vminv_u8_used_by_laneop:
 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
@@ -101,7 +101,7 @@ entry:
 define <4 x i16> @test_vminv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vminv_u16_used_by_laneop:
 ; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a2)
@@ -113,7 +113,7 @@ entry:
 define <2 x i32> @test_vminv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vminv_u32_used_by_laneop:
 ; CHECK: uminp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32> %a2)
@@ -124,7 +124,7 @@ entry:
 define <16 x i8> @test_vminvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vminvq_u8_used_by_laneop:
 ; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a2)
@@ -136,7 +136,7 @@ entry:
 define <8 x i16> @test_vminvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vminvq_u16_used_by_laneop:
 ; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a2)
@@ -148,7 +148,7 @@ entry:
 define <4 x i32> @test_vminvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vminvq_u32_used_by_laneop:
 ; CHECK: uminv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a2)
diff --git a/test/CodeGen/AArch64/arm64-vaddv.ll b/test/CodeGen/AArch64/arm64-vaddv.ll
index 55dbebf0c9fe..f5da79948316 100644
--- a/test/CodeGen/AArch64/arm64-vaddv.ll
+++ b/test/CodeGen/AArch64/arm64-vaddv.ll
@@ -14,7 +14,7 @@ entry:
 define <8 x i8> @test_vaddv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vaddv_s8_used_by_laneop:
 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2)
@@ -37,7 +37,7 @@ entry:
 define <4 x i16> @test_vaddv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vaddv_s16_used_by_laneop:
 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2)
@@ -60,7 +60,7 @@ entry:
 define <2 x i32> @test_vaddv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vaddv_s32_used_by_laneop:
 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2)
@@ -81,7 +81,7 @@ entry:
 define <2 x i64> @test_vaddv_s64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
 ; CHECK-LABEL: test_vaddv_s64_used_by_laneop:
 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2)
@@ -103,7 +103,7 @@ entry:
 define <8 x i8> @test_vaddv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vaddv_u8_used_by_laneop:
 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2)
@@ -137,7 +137,7 @@ entry:
 define <4 x i16> @test_vaddv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vaddv_u16_used_by_laneop:
 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a2)
@@ -171,7 +171,7 @@ entry:
 define <2 x i32> @test_vaddv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vaddv_u32_used_by_laneop:
 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a2)
@@ -220,7 +220,7 @@ entry:
 define <2 x i64> @test_vaddv_u64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
 ; CHECK-LABEL: test_vaddv_u64_used_by_laneop:
 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a2)
@@ -254,7 +254,7 @@ entry:
 define <16 x i8> @test_vaddvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vaddvq_s8_used_by_laneop:
 ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a2)
@@ -277,7 +277,7 @@ entry:
 define <8 x i16> @test_vaddvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vaddvq_s16_used_by_laneop:
 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a2)
@@ -299,7 +299,7 @@ entry:
 define <4 x i32> @test_vaddvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vaddvq_s32_used_by_laneop:
 ; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a2)
@@ -321,7 +321,7 @@ entry:
 define <16 x i8> @test_vaddvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vaddvq_u8_used_by_laneop:
 ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a2)
@@ -344,7 +344,7 @@ entry:
 define <8 x i16> @test_vaddvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vaddvq_u16_used_by_laneop:
 ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a2)
@@ -366,7 +366,7 @@ entry:
 define <4 x i32> @test_vaddvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vaddvq_u32_used_by_laneop:
 ; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a2)
diff --git a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
index 375877c51798..0f8f4c5d4a44 100644
--- a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
+++ b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
@@ -32,11 +32,9 @@ define void @test_simple(i32 %n, ...) {
 ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128
 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
 
-; CHECK: mov [[GR_OFFS:w[0-9]+]], #-56
-; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24]
-
-; CHECK: orr [[VR_OFFS:w[0-9]+]], wzr, #0xffffff80
-; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
+; CHECK: mov     [[GRVR:x[0-9]+]], #-545460846720
+; CHECK: movk    [[GRVR]], #65480
+; CHECK: str     [[GRVR]], [x[[VA_LIST]], #24]
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_start(i8* %addr)
@@ -70,11 +68,9 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
 ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112
 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
 
-; CHECK: mov [[GR_OFFS:w[0-9]+]], #-40
-; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24]
-
-; CHECK: mov [[VR_OFFS:w[0-9]+]], #-11
-; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28]
+; CHECK: mov  [[GRVR_OFFS:x[0-9]+]], #-40
+; CHECK: movk [[GRVR_OFFS]], #65424, lsl #32
+; CHECK: str  [[GRVR_OFFS]], [x[[VA_LIST]], #24]
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_start(i8* %addr)
@@ -113,7 +109,7 @@ declare void @llvm.va_end(i8*)
 
 define void @test_va_end() nounwind {
 ; CHECK-LABEL: test_va_end:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_end(i8* %addr)
diff --git a/test/CodeGen/AArch64/arm64-vcombine.ll b/test/CodeGen/AArch64/arm64-vcombine.ll
index 7e0b5803a951..c084ee22e975 100644
--- a/test/CodeGen/AArch64/arm64-vcombine.ll
+++ b/test/CodeGen/AArch64/arm64-vcombine.ll
@@ -6,7 +6,7 @@
 define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind {
 entry:
 ; CHECK-LABEL: test:
-; CHECK: ins.d v0[1], v1[0]
+; CHECK: mov.d v0[1], v1[0]
   %0 = bitcast <16 x i8> %q0 to <2 x i64>
   %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer
   %1 = bitcast <16 x i8> %q1 to <2 x i64>
diff --git a/test/CodeGen/AArch64/arm64-vector-insertion.ll b/test/CodeGen/AArch64/arm64-vector-insertion.ll
index b10af31d5e1f..7d72b489c3be 100644
--- a/test/CodeGen/AArch64/arm64-vector-insertion.ll
+++ b/test/CodeGen/AArch64/arm64-vector-insertion.ll
@@ -9,7 +9,7 @@ entry:
 
   ; CHECK-LABEL: test0f
   ; CHECK: movi.2d v[[TEMP:[0-9]+]], #0000000000000000
-  ; CHECK: ins.s v[[TEMP]][0], v{{[0-9]+}}[0]
+  ; CHECK: mov.s v[[TEMP]][0], v{{[0-9]+}}[0]
   ; CHECK: str q[[TEMP]], [x0]
   ; CHECK: ret
 
@@ -27,7 +27,7 @@ entry:
   ; CHECK-LABEL: test1f
   ; CHECK: fmov  s[[TEMP:[0-9]+]], #1.0000000
   ; CHECK: dup.4s  v[[TEMP2:[0-9]+]], v[[TEMP]][0]
-  ; CHECK: ins.s v[[TEMP2]][0], v0[0]
+  ; CHECK: mov.s v[[TEMP2]][0], v0[0]
   ; CHECK: str q[[TEMP2]], [x0]
   ; CHECK: ret
 }
diff --git a/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll b/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
index 24537477c4cc..4e1de87f5865 100644
--- a/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
+++ b/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
@@ -1,14 +1,42 @@
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mattr=-fullfp16 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK-FP16
 
 ;;; Float vectors
 
 %v2f32 = type <2 x float>
-; CHECK: test_v2f32.sqrt:
+%v4f16 = type <4 x half>
+%v8f16 = type <8 x half>
+
+; CHECK-LABEL: test_v2f32.sqrt:
 define %v2f32 @test_v2f32.sqrt(%v2f32 %a) {
   ; CHECK: fsqrt.2s
   %1 = call %v2f32 @llvm.sqrt.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
+define %v4f16 @test_v4f16.sqrt(%v4f16 %a) {
+; CHECK-LABEL: test_v4f16.sqrt:
+; CHECK:       fsqrt s{{.}}, s{{.}}
+; CHECK:       fsqrt s{{.}}, s{{.}}
+; CHECK:       fsqrt s{{.}}, s{{.}}
+; CHECK:       fsqrt s{{.}}, s{{.}}
+
+; CHECK-FP16-LABEL: test_v4f16.sqrt:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fsqrt.4h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v4f16 @llvm.sqrt.v4f16(%v4f16 %a)
+  ret %v4f16 %1
+}
+define %v8f16 @test_v8f16.sqrt(%v8f16 %a) {
+; Filechecks are unwieldy with 16 fcvt and 8 fsqrt tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_v8f16.sqrt:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fsqrt.8h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v8f16 @llvm.sqrt.v8f16(%v8f16 %a)
+  ret %v8f16 %1
+}
 ; CHECK: test_v2f32.powi:
 define %v2f32 @test_v2f32.powi(%v2f32 %a, i32 %b) {
   ; CHECK: pow
@@ -63,50 +91,217 @@ define %v2f32 @test_v2f32.log2(%v2f32 %a) {
   %1 = call %v2f32 @llvm.log2.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
-; CHECK: test_v2f32.fma:
+; CHECK-LABEL: test_v2f32.fma:
 define %v2f32 @test_v2f32.fma(%v2f32 %a, %v2f32 %b, %v2f32 %c) {
-  ; CHECK: fma
+  ; CHECK: fmla.2s
   %1 = call %v2f32 @llvm.fma.v2f32(%v2f32 %a, %v2f32 %b, %v2f32 %c)
   ret %v2f32 %1
 }
-; CHECK: test_v2f32.fabs:
+define %v4f16 @test_v4f16.fma(%v4f16 %a, %v4f16 %b, %v4f16 %c) {
+; CHECK-LABEL: test_v4f16.fma:
+; CHECK:       fmadd s{{.}}, s{{.}}, s{{.}}, s{{.}}
+; CHECK:       fmadd s{{.}}, s{{.}}, s{{.}}, s{{.}}
+; CHECK:       fmadd s{{.}}, s{{.}}, s{{.}}, s{{.}}
+; CHECK:       fmadd s{{.}}, s{{.}}, s{{.}}, s{{.}}
+
+; CHECK-FP16-LABEL: test_v4f16.fma:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fmla.4h
+  %1 = call %v4f16 @llvm.fma.v4f16(%v4f16 %a, %v4f16 %b, %v4f16 %c)
+  ret %v4f16 %1
+}
+define %v8f16 @test_v8f16.fma(%v8f16 %a, %v8f16 %b, %v8f16 %c) {
+; Filechecks are unwieldy with 16 fcvt and 8 fma tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_v8f16.fma:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fmla.8h
+  %1 = call %v8f16 @llvm.fma.v8f16(%v8f16 %a, %v8f16 %b, %v8f16 %c)
+  ret %v8f16 %1
+}
+; CHECK-LABEL: test_v2f32.fabs:
 define %v2f32 @test_v2f32.fabs(%v2f32 %a) {
-  ; CHECK: fabs
+  ; CHECK: fabs.2s
   %1 = call %v2f32 @llvm.fabs.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
-; CHECK: test_v2f32.floor:
+define %v4f16 @test_v4f16.fabs(%v4f16 %a) {
+; CHECK-LABEL: test_v4f16.fabs:
+; CHECK:       fabs s{{.}}, s{{.}}
+; CHECK:       fabs s{{.}}, s{{.}}
+; CHECK:       fabs s{{.}}, s{{.}}
+; CHECK:       fabs s{{.}}, s{{.}}
+
+; CHECK-FP16-LABEL: test_v4f16.fabs:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fabs.4h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v4f16 @llvm.fabs.v4f16(%v4f16 %a)
+  ret %v4f16 %1
+}
+define %v8f16 @test_v8f16.fabs(%v8f16 %a) {
+; Filechecks are unwieldy with 16 fcvt and 8 fabs tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_v8f16.fabs:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fabs.8h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v8f16 @llvm.fabs.v8f16(%v8f16 %a)
+  ret %v8f16 %1
+}
+; CHECK-LABEL: test_v2f32.floor:
 define %v2f32 @test_v2f32.floor(%v2f32 %a) {
   ; CHECK: frintm.2s
   %1 = call %v2f32 @llvm.floor.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
-; CHECK: test_v2f32.ceil:
+define %v4f16 @test_v4f16.floor(%v4f16 %a) {
+; CHECK-LABEL: test_v4f16.floor:
+; CHECK:       frintm s{{.}}, s{{.}}
+; CHECK:       frintm s{{.}}, s{{.}}
+; CHECK:       frintm s{{.}}, s{{.}}
+; CHECK:       frintm s{{.}}, s{{.}}
+
+; CHECK-FP16-LABEL: test_v4f16.floor:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       frintm.4h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v4f16 @llvm.floor.v4f16(%v4f16 %a)
+  ret %v4f16 %1
+}
+define %v8f16 @test_v8f16.floor(%v8f16 %a) {
+; Filechecks are unwieldy with 16 fcvt and 8 frintm tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_v8f16.floor:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       frintm.8h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v8f16 @llvm.floor.v8f16(%v8f16 %a)
+  ret %v8f16 %1
+}
+; CHECK-LABEL: test_v2f32.ceil:
 define %v2f32 @test_v2f32.ceil(%v2f32 %a) {
   ; CHECK: frintp.2s
   %1 = call %v2f32 @llvm.ceil.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
-; CHECK: test_v2f32.trunc:
+define %v4f16 @test_v4f16.ceil(%v4f16 %a) {
+; CHECK-LABEL: test_v4f16.ceil:
+; CHECK:       frintp s{{.}}, s{{.}}
+; CHECK:       frintp s{{.}}, s{{.}}
+; CHECK:       frintp s{{.}}, s{{.}}
+; CHECK:       frintp s{{.}}, s{{.}}
+
+; CHECK-FP16-LABEL: test_v4f16.ceil:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       frintp.4h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v4f16 @llvm.ceil.v4f16(%v4f16 %a)
+  ret %v4f16 %1
+}
+define %v8f16 @test_v8f16.ceil(%v8f16 %a) {
+; Filechecks are unwieldy with 16 fcvt and 8 frint tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_v8f16.ceil:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       frintp.8h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v8f16 @llvm.ceil.v8f16(%v8f16 %a)
+  ret %v8f16 %1
+}
+; CHECK-LABEL: test_v2f32.trunc:
 define %v2f32 @test_v2f32.trunc(%v2f32 %a) {
   ; CHECK: frintz.2s
   %1 = call %v2f32 @llvm.trunc.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
-; CHECK: test_v2f32.rint:
+define %v4f16 @test_v4f16.trunc(%v4f16 %a) {
+; CHECK-LABEL: test_v4f16.trunc:
+; CHECK:       frintz s{{.}}, s{{.}}
+; CHECK:       frintz s{{.}}, s{{.}}
+; CHECK:       frintz s{{.}}, s{{.}}
+; CHECK:       frintz s{{.}}, s{{.}}
+
+; CHECK-FP16-LABEL: test_v4f16.trunc:
+; CHECK-FP16:       frintz.4h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v4f16 @llvm.trunc.v4f16(%v4f16 %a)
+  ret %v4f16 %1
+}
+define %v8f16 @test_v8f16.trunc(%v8f16 %a) {
+; Filechecks are unwieldy with 16 fcvt and 8 frint tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_v8f16.trunc:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       frintz.8h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v8f16 @llvm.trunc.v8f16(%v8f16 %a)
+  ret %v8f16 %1
+}
+; CHECK-LABEL: test_v2f32.rint:
 define %v2f32 @test_v2f32.rint(%v2f32 %a) {
   ; CHECK: frintx.2s
   %1 = call %v2f32 @llvm.rint.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
-; CHECK: test_v2f32.nearbyint:
+define %v4f16 @test_v4f16.rint(%v4f16 %a) {
+; CHECK-LABEL: test_v4f16.rint:
+; CHECK:       frintx s{{.}}, s{{.}}
+; CHECK:       frintx s{{.}}, s{{.}}
+; CHECK:       frintx s{{.}}, s{{.}}
+; CHECK:       frintx s{{.}}, s{{.}}
+
+; CHECK-FP16-LABEL: test_v4f16.rint:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       frintx.4h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v4f16 @llvm.rint.v4f16(%v4f16 %a)
+  ret %v4f16 %1
+}
+define %v8f16 @test_v8f16.rint(%v8f16 %a) {
+; Filechecks are unwieldy with 16 fcvt and 8 frint tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_v8f16.rint:
+; CHECK-FP16:       frintx.8h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v8f16 @llvm.rint.v8f16(%v8f16 %a)
+  ret %v8f16 %1
+}
+; CHECK-LABEL: test_v2f32.nearbyint:
 define %v2f32 @test_v2f32.nearbyint(%v2f32 %a) {
   ; CHECK: frinti.2s
   %1 = call %v2f32 @llvm.nearbyint.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
+define %v4f16 @test_v4f16.nearbyint(%v4f16 %a) {
+; CHECK-LABEL: test_v4f16.nearbyint:
+; CHECK:       frinti s{{.}}, s{{.}}
+; CHECK:       frinti s{{.}}, s{{.}}
+; CHECK:       frinti s{{.}}, s{{.}}
+; CHECK:       frinti s{{.}}, s{{.}}
+
+; CHECK-FP16-LABEL: test_v4f16.nearbyint:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       frinti.4h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v4f16 @llvm.nearbyint.v4f16(%v4f16 %a)
+  ret %v4f16 %1
+}
+define %v8f16 @test_v8f16.nearbyint(%v8f16 %a) {
+; Filechecks are unwieldy with 16 fcvt and 8 frint tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_v8f16.nearbyint:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       frinti.8h
+; CHECK-FP16-NEXT:  ret
+  %1 = call %v8f16 @llvm.nearbyint.v8f16(%v8f16 %a)
+  ret %v8f16 %1
+}
 
 declare %v2f32 @llvm.sqrt.v2f32(%v2f32) #0
+declare %v4f16 @llvm.sqrt.v4f16(%v4f16) #0
+declare %v8f16 @llvm.sqrt.v8f16(%v8f16) #0
+
 declare %v2f32 @llvm.powi.v2f32(%v2f32, i32) #0
 declare %v2f32 @llvm.sin.v2f32(%v2f32) #0
 declare %v2f32 @llvm.cos.v2f32(%v2f32) #0
@@ -116,13 +311,34 @@ declare %v2f32 @llvm.exp2.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log10.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log2.v2f32(%v2f32) #0
+
 declare %v2f32 @llvm.fma.v2f32(%v2f32, %v2f32, %v2f32) #0
+declare %v4f16 @llvm.fma.v4f16(%v4f16, %v4f16, %v4f16) #0
+declare %v8f16 @llvm.fma.v8f16(%v8f16, %v8f16, %v8f16) #0
+
 declare %v2f32 @llvm.fabs.v2f32(%v2f32) #0
+declare %v4f16 @llvm.fabs.v4f16(%v4f16) #0
+declare %v8f16 @llvm.fabs.v8f16(%v8f16) #0
+
 declare %v2f32 @llvm.floor.v2f32(%v2f32) #0
+declare %v4f16 @llvm.floor.v4f16(%v4f16) #0
+declare %v8f16 @llvm.floor.v8f16(%v8f16) #0
+
 declare %v2f32 @llvm.ceil.v2f32(%v2f32) #0
+declare %v4f16 @llvm.ceil.v4f16(%v4f16) #0
+declare %v8f16 @llvm.ceil.v8f16(%v8f16) #0
+
 declare %v2f32 @llvm.trunc.v2f32(%v2f32) #0
+declare %v4f16 @llvm.trunc.v4f16(%v4f16) #0
+declare %v8f16 @llvm.trunc.v8f16(%v8f16) #0
+
 declare %v2f32 @llvm.rint.v2f32(%v2f32) #0
+declare %v4f16 @llvm.rint.v4f16(%v4f16) #0
+declare %v8f16 @llvm.rint.v8f16(%v8f16) #0
+
 declare %v2f32 @llvm.nearbyint.v2f32(%v2f32) #0
+declare %v4f16 @llvm.nearbyint.v4f16(%v4f16) #0
+declare %v8f16 @llvm.nearbyint.v8f16(%v8f16) #0
 
 ;;;
 
diff --git a/test/CodeGen/AArch64/arm64-xaluo.ll b/test/CodeGen/AArch64/arm64-xaluo.ll
index 8b212aa6c1da..fc167d2f34d4 100644
--- a/test/CodeGen/AArch64/arm64-xaluo.ll
+++ b/test/CodeGen/AArch64/arm64-xaluo.ll
@@ -282,6 +282,17 @@ entry:
   ret i32 %ret
 }
 
+define i1 @saddo.not.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL:  saddo.not.i32
+; CHECK:        cmn w0, w1
+; CHECK-NEXT:   cset w0, vc
+  %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
+  %obit = extractvalue {i32, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  saddo.select.i64
@@ -293,6 +304,17 @@ entry:
   ret i64 %ret
 }
 
+define i1 @saddo.not.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL:  saddo.not.i64
+; CHECK:        cmn x0, x1
+; CHECK-NEXT:   cset w0, vc
+  %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
+  %obit = extractvalue {i64, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.select.i32
@@ -304,6 +326,17 @@ entry:
   ret i32 %ret
 }
 
+define i1 @uaddo.not.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL:  uaddo.not.i32
+; CHECK:        cmn w0, w1
+; CHECK-NEXT:   cset w0, lo
+  %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
+  %obit = extractvalue {i32, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  uaddo.select.i64
@@ -315,6 +348,17 @@ entry:
   ret i64 %ret
 }
 
+define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL:  uaddo.not.i64
+; CHECK:        cmn x0, x1
+; CHECK-NEXT:   cset w0, lo
+  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
+  %obit = extractvalue {i64, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  ssubo.select.i32
@@ -326,6 +370,17 @@ entry:
   ret i32 %ret
 }
 
+define i1 @ssubo.not.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL:  ssubo.not.i32
+; CHECK:        cmp w0, w1
+; CHECK-NEXT:   cset w0, vc
+  %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
+  %obit = extractvalue {i32, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  ssubo.select.i64
@@ -337,6 +392,17 @@ entry:
   ret i64 %ret
 }
 
+define i1 @ssub.not.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL:  ssub.not.i64
+; CHECK:        cmp x0, x1
+; CHECK-NEXT:   cset w0, vc
+  %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
+  %obit = extractvalue {i64, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.select.i32
@@ -348,6 +414,17 @@ entry:
   ret i32 %ret
 }
 
+define i1 @usubo.not.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL:  usubo.not.i32
+; CHECK:        cmp w0, w1
+; CHECK-NEXT:   cset w0, hs
+  %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
+  %obit = extractvalue {i32, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  usubo.select.i64
@@ -359,6 +436,17 @@ entry:
   ret i64 %ret
 }
 
+define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL:  usubo.not.i64
+; CHECK:        cmp x0, x1
+; CHECK-NEXT:   cset w0, hs
+  %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
+  %obit = extractvalue {i64, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  smulo.select.i32
@@ -372,6 +460,19 @@ entry:
   ret i32 %ret
 }
 
+define i1 @smulo.not.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL:  smulo.not.i32
+; CHECK:        smull   x[[MREG:[0-9]+]], w0, w1
+; CHECK-NEXT:   lsr     x[[SREG:[0-9]+]], x[[MREG]], #32
+; CHECK-NEXT:   cmp     w[[SREG]], w[[MREG]], asr #31
+; CHECK-NEXT:   cset    w0, eq
+  %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
+  %obit = extractvalue {i32, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  smulo.select.i64
@@ -385,6 +486,19 @@ entry:
   ret i64 %ret
 }
 
+define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL:  smulo.not.i64
+; CHECK:        mul     [[MREG:x[0-9]+]], x0, x1
+; CHECK-NEXT:   smulh   [[HREG:x[0-9]+]], x0, x1
+; CHECK-NEXT:   cmp     [[HREG]], [[MREG]], asr #63
+; CHECK-NEXT:   cset    w0, eq
+  %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
+  %obit = extractvalue {i64, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
 entry:
 ; CHECK-LABEL:  umulo.select.i32
@@ -397,6 +511,18 @@ entry:
   ret i32 %ret
 }
 
+define i1 @umulo.not.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL:  umulo.not.i32
+; CHECK:        umull   [[MREG:x[0-9]+]], w0, w1
+; CHECK-NEXT:   cmp     xzr, [[MREG]], lsr #32
+; CHECK-NEXT:   cset    w0, eq
+  %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
+  %obit = extractvalue {i32, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
 entry:
 ; CHECK-LABEL:  umulo.select.i64
@@ -409,6 +535,18 @@ entry:
   ret i64 %ret
 }
 
+define i1 @umulo.not.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL:  umulo.not.i64
+; CHECK:        umulh   [[MREG:x[0-9]+]], x0, x1
+; CHECK-NEXT:   cmp     xzr, [[MREG]]
+; CHECK-NEXT:   cset    w0, eq
+  %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
+  %obit = extractvalue {i64, i1} %t, 1
+  %ret = xor i1 %obit, true
+  ret i1 %ret
+}
+
 
 ;
 ; Check the use of the overflow bit in combination with a branch instruction.
diff --git a/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll b/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
index 412651c55678..453334dce601 100644
--- a/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
+++ b/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
@@ -9,10 +9,10 @@ define void @t1() nounwind ssp {
 entry:
 ; ALL-LABEL: t1:
 ; ALL-NOT: fmov
-; CYCLONE: movi.2d v0, #0000000000000000
-; CYCLONE: movi.2d v1, #0000000000000000
-; CYCLONE: movi.2d v2, #0000000000000000
-; CYCLONE: movi.2d v3, #0000000000000000
+; CYCLONE: fmov d0, xzr
+; CYCLONE: fmov d1, xzr
+; CYCLONE: fmov d2, xzr
+; CYCLONE: fmov d3, xzr
 ; KRYO: movi v0.2d, #0000000000000000
 ; KRYO: movi v1.2d, #0000000000000000
 ; KRYO: movi v2.2d, #0000000000000000
@@ -48,8 +48,8 @@ entry:
 define void @t4() nounwind ssp {
 ; ALL-LABEL: t4:
 ; ALL-NOT: fmov
-; CYCLONE: movi.2d v0, #0000000000000000
-; CYCLONE: movi.2d v1, #0000000000000000
+; CYCLONE: fmov s0, wzr
+; CYCLONE: fmov s1, wzr
 ; KRYO: movi v0.2d, #0000000000000000
 ; KRYO: movi v1.2d, #0000000000000000
 ; FALKOR: movi v0.2d, #0000000000000000
diff --git a/test/CodeGen/AArch64/atomic-ops-lse.ll b/test/CodeGen/AArch64/atomic-ops-lse.ll
index a0c418bff573..49f716547b12 100644
--- a/test/CodeGen/AArch64/atomic-ops-lse.ll
+++ b/test/CodeGen/AArch64/atomic-ops-lse.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mattr=+lse < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mattr=+lse < %s | FileCheck %s --check-prefix=CHECK-REG
+; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mcpu=saphira < %s | FileCheck %s
 
 ; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created
 ; (i.e. reusing a register for status & data in store exclusive).
@@ -630,7 +631,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
-; CHECK: casalb w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
+; CHECK: casab w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
@@ -645,7 +646,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
-; CHECK: casalh w0, w1, [x[[ADDR]]]
+; CHECK: casah w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
@@ -660,7 +661,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
-; CHECK: casal w0, w1, [x[[ADDR]]]
+; CHECK: casa w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
@@ -675,7 +676,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
-; CHECK: casal x0, x1, [x[[ADDR]]]
+; CHECK: casa x0, x1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
@@ -842,3 +843,4045 @@ define void @test_atomic_load_and_i64_noret(i64 %offset) nounwind {
 ; CHECK-NOT: dmb
   ret void
 }
+
+define i8 @test_atomic_load_add_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i8_acq_rel:
+   %old = atomicrmw add i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_add_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i16_acq_rel:
+   %old = atomicrmw add i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_add_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_acq_rel:
+   %old = atomicrmw add i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_add_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_acq_rel:
+   %old = atomicrmw add i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_add_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_noret_acq_rel:
+   atomicrmw add i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_add_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_noret_acq_rel:
+   atomicrmw add i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_add_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i8_acquire:
+   %old = atomicrmw add i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_add_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i16_acquire:
+   %old = atomicrmw add i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_add_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_acquire:
+   %old = atomicrmw add i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldadda w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_add_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_acquire:
+   %old = atomicrmw add i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldadda x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_add_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_noret_acquire:
+   atomicrmw add i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldadda w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_add_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_noret_acquire:
+   atomicrmw add i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldadda x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_add_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i8_monotonic:
+   %old = atomicrmw add i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_add_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i16_monotonic:
+   %old = atomicrmw add i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_add_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_monotonic:
+   %old = atomicrmw add i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldadd w[[OLD:[0-9]+]], w[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_add_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_monotonic:
+   %old = atomicrmw add i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldadd x[[OLD:[0-9]+]], x[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_add_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_noret_monotonic:
+   atomicrmw add i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stadd w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_add_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_noret_monotonic:
+   atomicrmw add i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stadd x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_add_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i8_release:
+   %old = atomicrmw add i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_add_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i16_release:
+   %old = atomicrmw add i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_add_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_release:
+   %old = atomicrmw add i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_add_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_release:
+   %old = atomicrmw add i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_add_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_noret_release:
+   atomicrmw add i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: staddl w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_add_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_noret_release:
+   atomicrmw add i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: staddl x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_add_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i8_seq_cst:
+   %old = atomicrmw add i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_add_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i16_seq_cst:
+   %old = atomicrmw add i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_add_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_seq_cst:
+   %old = atomicrmw add i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_add_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_seq_cst:
+   %old = atomicrmw add i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_add_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i32_noret_seq_cst:
+   atomicrmw add i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_add_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_add_i64_noret_seq_cst:
+   atomicrmw add i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_and_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i8_acq_rel:
+  %old = atomicrmw and i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldclralb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_and_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i16_acq_rel:
+  %old = atomicrmw and i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldclralh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_and_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_acq_rel:
+  %old = atomicrmw and i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_and_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_acq_rel:
+  %old = atomicrmw and i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i64 %old
+}
+
+define void @test_atomic_load_and_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_noret_acq_rel:
+  atomicrmw and i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_and_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_noret_acq_rel:
+  atomicrmw and i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_and_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i8_acquire:
+  %old = atomicrmw and i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldclrab w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_and_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i16_acquire:
+  %old = atomicrmw and i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldclrah w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_and_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_acquire:
+  %old = atomicrmw and i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldclra w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_and_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_acquire:
+  %old = atomicrmw and i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldclra x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i64 %old
+}
+
+define void @test_atomic_load_and_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_noret_acquire:
+  atomicrmw and i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldclra w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_and_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_noret_acquire:
+  atomicrmw and i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldclra x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_and_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i8_monotonic:
+  %old = atomicrmw and i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldclrb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_and_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i16_monotonic:
+  %old = atomicrmw and i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldclrh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_and_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_monotonic:
+  %old = atomicrmw and i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldclr w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_and_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_monotonic:
+  %old = atomicrmw and i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldclr x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i64 %old
+}
+
+define void @test_atomic_load_and_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_noret_monotonic:
+  atomicrmw and i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stclr w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_and_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_noret_monotonic:
+  atomicrmw and i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stclr x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_and_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i8_release:
+  %old = atomicrmw and i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldclrlb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_and_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i16_release:
+  %old = atomicrmw and i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldclrlh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_and_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_release:
+  %old = atomicrmw and i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldclrl w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_and_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_release:
+  %old = atomicrmw and i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldclrl x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i64 %old
+}
+
+define void @test_atomic_load_and_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_noret_release:
+  atomicrmw and i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stclrl w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_and_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_noret_release:
+  atomicrmw and i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stclrl x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_and_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i8_seq_cst:
+  %old = atomicrmw and i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldclralb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_and_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i16_seq_cst:
+  %old = atomicrmw and i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldclralh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_and_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_seq_cst:
+  %old = atomicrmw and i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_and_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_seq_cst:
+  %old = atomicrmw and i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret i64 %old
+}
+
+define void @test_atomic_load_and_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i32_noret_seq_cst:
+  atomicrmw and i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_and_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_and_i64_noret_seq_cst:
+  atomicrmw and i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_cmpxchg_i8_acquire(i8 %wanted, i8 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i8_acquire:
+   %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
+   %old = extractvalue { i8, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: casab w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_cmpxchg_i16_acquire(i16 %wanted, i16 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i16_acquire:
+   %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new acquire acquire
+   %old = extractvalue { i16, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: casah w0, w1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_cmpxchg_i32_acquire(i32 %wanted, i32 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i32_acquire:
+   %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new acquire acquire
+   %old = extractvalue { i32, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: casa w0, w1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_cmpxchg_i64_acquire(i64 %wanted, i64 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i64_acquire:
+   %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new acquire acquire
+   %old = extractvalue { i64, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: casa x0, x1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define i8 @test_atomic_cmpxchg_i8_monotonic(i8 %wanted, i8 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i8_monotonic:
+   %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new monotonic monotonic
+   %old = extractvalue { i8, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: casb w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_cmpxchg_i16_monotonic(i16 %wanted, i16 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i16_monotonic:
+   %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new monotonic monotonic
+   %old = extractvalue { i16, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: cash w0, w1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_cmpxchg_i32_monotonic(i32 %wanted, i32 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i32_monotonic:
+   %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new monotonic monotonic
+   %old = extractvalue { i32, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: cas w0, w1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_cmpxchg_i64_monotonic(i64 %wanted, i64 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i64_monotonic:
+   %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic monotonic
+   %old = extractvalue { i64, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: cas x0, x1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define i8 @test_atomic_cmpxchg_i8_seq_cst(i8 %wanted, i8 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i8_seq_cst:
+   %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new seq_cst seq_cst
+   %old = extractvalue { i8, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: casalb w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_cmpxchg_i16_seq_cst(i16 %wanted, i16 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i16_seq_cst:
+   %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst seq_cst
+   %old = extractvalue { i16, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: casalh w0, w1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_cmpxchg_i32_seq_cst(i32 %wanted, i32 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i32_seq_cst:
+   %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new seq_cst seq_cst
+   %old = extractvalue { i32, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: casal w0, w1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_cmpxchg_i64_seq_cst(i64 %wanted, i64 %new) nounwind {
+; CHECK-LABEL: test_atomic_cmpxchg_i64_seq_cst:
+   %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new seq_cst seq_cst
+   %old = extractvalue { i64, i1 } %pair, 0
+
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: casal x0, x1, [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define i8 @test_atomic_load_max_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i8_acq_rel:
+   %old = atomicrmw max i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsmaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_max_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i16_acq_rel:
+   %old = atomicrmw max i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsmaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_max_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_acq_rel:
+   %old = atomicrmw max i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_max_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_acq_rel:
+   %old = atomicrmw max i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_max_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_noret_acq_rel:
+   atomicrmw max i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_max_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_noret_acq_rel:
+   atomicrmw max i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_max_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i8_acquire:
+   %old = atomicrmw max i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsmaxab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_max_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i16_acquire:
+   %old = atomicrmw max i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsmaxah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_max_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_acquire:
+   %old = atomicrmw max i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmaxa w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_max_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_acquire:
+   %old = atomicrmw max i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmaxa x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_max_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_noret_acquire:
+   atomicrmw max i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmaxa w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_max_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_noret_acquire:
+   atomicrmw max i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmaxa x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_max_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i8_monotonic:
+   %old = atomicrmw max i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsmaxb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_max_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i16_monotonic:
+   %old = atomicrmw max i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsmaxh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_max_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_monotonic:
+   %old = atomicrmw max i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmax w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_max_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_monotonic:
+   %old = atomicrmw max i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmax x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_max_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_noret_monotonic:
+   atomicrmw max i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stsmax w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_max_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_noret_monotonic:
+   atomicrmw max i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stsmax x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_max_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i8_release:
+   %old = atomicrmw max i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsmaxlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_max_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i16_release:
+   %old = atomicrmw max i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsmaxlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_max_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_release:
+   %old = atomicrmw max i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmaxl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_max_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_release:
+   %old = atomicrmw max i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmaxl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_max_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_noret_release:
+   atomicrmw max i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stsmaxl w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_max_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_noret_release:
+   atomicrmw max i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stsmaxl x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_max_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i8_seq_cst:
+   %old = atomicrmw max i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsmaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_max_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i16_seq_cst:
+   %old = atomicrmw max i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsmaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_max_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_seq_cst:
+   %old = atomicrmw max i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_max_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_seq_cst:
+   %old = atomicrmw max i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_max_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i32_noret_seq_cst:
+   atomicrmw max i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_max_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_max_i64_noret_seq_cst:
+   atomicrmw max i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_min_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i8_acq_rel:
+   %old = atomicrmw min i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_min_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i16_acq_rel:
+   %old = atomicrmw min i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_min_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_acq_rel:
+   %old = atomicrmw min i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_min_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_acq_rel:
+   %old = atomicrmw min i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_min_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_noret_acq_rel:
+   atomicrmw min i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_min_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_noret_acq_rel:
+   atomicrmw min i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_min_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i8_acquire:
+   %old = atomicrmw min i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsminab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_min_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i16_acquire:
+   %old = atomicrmw min i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsminah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_min_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_acquire:
+   %old = atomicrmw min i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmina w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_min_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_acquire:
+   %old = atomicrmw min i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmina x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_min_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_noret_acquire:
+   atomicrmw min i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmina w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_min_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_noret_acquire:
+   atomicrmw min i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmina x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_min_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i8_monotonic:
+   %old = atomicrmw min i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsminb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_min_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i16_monotonic:
+   %old = atomicrmw min i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsminh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_min_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_monotonic:
+   %old = atomicrmw min i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsmin w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_min_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_monotonic:
+   %old = atomicrmw min i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsmin x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_min_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_noret_monotonic:
+   atomicrmw min i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stsmin w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_min_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_noret_monotonic:
+   atomicrmw min i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stsmin x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_min_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i8_release:
+   %old = atomicrmw min i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsminlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_min_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i16_release:
+   %old = atomicrmw min i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsminlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_min_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_release:
+   %old = atomicrmw min i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsminl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_min_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_release:
+   %old = atomicrmw min i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsminl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_min_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_noret_release:
+   atomicrmw min i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stsminl w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_min_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_noret_release:
+   atomicrmw min i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stsminl x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_min_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i8_seq_cst:
+   %old = atomicrmw min i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_min_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i16_seq_cst:
+   %old = atomicrmw min i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_min_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_seq_cst:
+   %old = atomicrmw min i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_min_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_seq_cst:
+   %old = atomicrmw min i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_min_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i32_noret_seq_cst:
+   atomicrmw min i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_min_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_min_i64_noret_seq_cst:
+   atomicrmw min i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_or_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i8_acq_rel:
+   %old = atomicrmw or i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsetalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_or_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i16_acq_rel:
+   %old = atomicrmw or i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsetalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_or_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_acq_rel:
+   %old = atomicrmw or i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsetal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_or_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_acq_rel:
+   %old = atomicrmw or i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsetal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_or_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_noret_acq_rel:
+   atomicrmw or i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsetal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_or_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_noret_acq_rel:
+   atomicrmw or i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsetal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_or_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i8_acquire:
+   %old = atomicrmw or i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsetab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_or_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i16_acquire:
+   %old = atomicrmw or i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsetah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_or_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_acquire:
+   %old = atomicrmw or i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldseta w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_or_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_acquire:
+   %old = atomicrmw or i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldseta x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_or_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_noret_acquire:
+   atomicrmw or i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldseta w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_or_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_noret_acquire:
+   atomicrmw or i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldseta x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_or_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i8_monotonic:
+   %old = atomicrmw or i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsetb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_or_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i16_monotonic:
+   %old = atomicrmw or i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldseth w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_or_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_monotonic:
+   %old = atomicrmw or i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldset w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_or_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_monotonic:
+   %old = atomicrmw or i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldset x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_or_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_noret_monotonic:
+   atomicrmw or i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stset w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_or_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_noret_monotonic:
+   atomicrmw or i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stset x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_or_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i8_release:
+   %old = atomicrmw or i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsetlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_or_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i16_release:
+   %old = atomicrmw or i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsetlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_or_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_release:
+   %old = atomicrmw or i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsetl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_or_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_release:
+   %old = atomicrmw or i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsetl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_or_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_noret_release:
+   atomicrmw or i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stsetl w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_or_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_noret_release:
+   atomicrmw or i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stsetl x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_or_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i8_seq_cst:
+   %old = atomicrmw or i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldsetalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_or_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i16_seq_cst:
+   %old = atomicrmw or i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldsetalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_or_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_seq_cst:
+   %old = atomicrmw or i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsetal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_or_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_seq_cst:
+   %old = atomicrmw or i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsetal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_or_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i32_noret_seq_cst:
+   atomicrmw or i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldsetal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_or_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_or_i64_noret_seq_cst:
+   atomicrmw or i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldsetal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_sub_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i8_acq_rel:
+  %old = atomicrmw sub i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddalb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_sub_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i16_acq_rel:
+  %old = atomicrmw sub i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddalh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_sub_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_acq_rel:
+  %old = atomicrmw sub i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_sub_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_acq_rel:
+  %old = atomicrmw sub i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i64 %old
+}
+
+define void @test_atomic_load_sub_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_noret_acq_rel:
+  atomicrmw sub i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define void @test_atomic_load_sub_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_noret_acq_rel:
+  atomicrmw sub i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define i8 @test_atomic_load_sub_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i8_acquire:
+  %old = atomicrmw sub i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddab w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_sub_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i16_acquire:
+  %old = atomicrmw sub i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddah w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_sub_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_acquire:
+  %old = atomicrmw sub i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldadda w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_sub_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_acquire:
+  %old = atomicrmw sub i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldadda x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i64 %old
+}
+
+define void @test_atomic_load_sub_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_noret_acquire:
+  atomicrmw sub i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldadda w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define void @test_atomic_load_sub_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_noret_acquire:
+  atomicrmw sub i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldadda x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define i8 @test_atomic_load_sub_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i8_monotonic:
+  %old = atomicrmw sub i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_sub_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i16_monotonic:
+  %old = atomicrmw sub i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_sub_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_monotonic:
+  %old = atomicrmw sub i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldadd w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_sub_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_monotonic:
+  %old = atomicrmw sub i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldadd x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i64 %old
+}
+
+define void @test_atomic_load_sub_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_noret_monotonic:
+  atomicrmw sub i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stadd w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define void @test_atomic_load_sub_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_noret_monotonic:
+  atomicrmw sub i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stadd x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define i8 @test_atomic_load_sub_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i8_release:
+  %old = atomicrmw sub i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddlb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_sub_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i16_release:
+  %old = atomicrmw sub i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddlh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_sub_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_release:
+  %old = atomicrmw sub i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddl w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_sub_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_release:
+  %old = atomicrmw sub i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddl x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i64 %old
+}
+
+define void @test_atomic_load_sub_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_noret_release:
+  atomicrmw sub i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: staddl w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define void @test_atomic_load_sub_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_noret_release:
+  atomicrmw sub i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: staddl x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define i8 @test_atomic_load_sub_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i8_seq_cst:
+  %old = atomicrmw sub i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldaddalb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i8 %old
+}
+
+define i16 @test_atomic_load_sub_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i16_seq_cst:
+  %old = atomicrmw sub i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldaddalh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i16 %old
+}
+
+define i32 @test_atomic_load_sub_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_seq_cst:
+  %old = atomicrmw sub i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i32 %old
+}
+
+define i64 @test_atomic_load_sub_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_seq_cst:
+  %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret i64 %old
+}
+
+define void @test_atomic_load_sub_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i32_noret_seq_cst:
+  atomicrmw sub i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define void @test_atomic_load_sub_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_sub_i64_noret_seq_cst:
+  atomicrmw sub i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+  ret void
+}
+
+define i8 @test_atomic_load_xchg_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i8_acq_rel:
+   %old = atomicrmw xchg i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: swpalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xchg_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i16_acq_rel:
+   %old = atomicrmw xchg i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: swpalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xchg_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_acq_rel:
+   %old = atomicrmw xchg i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xchg_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_acq_rel:
+   %old = atomicrmw xchg i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xchg_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_noret_acq_rel:
+   atomicrmw xchg i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define void @test_atomic_load_xchg_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_noret_acq_rel:
+   atomicrmw xchg i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define i8 @test_atomic_load_xchg_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i8_acquire:
+   %old = atomicrmw xchg i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: swpab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xchg_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i16_acquire:
+   %old = atomicrmw xchg i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: swpah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xchg_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_acquire:
+   %old = atomicrmw xchg i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swpa w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xchg_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_acquire:
+   %old = atomicrmw xchg i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swpa x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xchg_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_noret_acquire:
+   atomicrmw xchg i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swpa w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define void @test_atomic_load_xchg_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_noret_acquire:
+   atomicrmw xchg i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swpa x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define i8 @test_atomic_load_xchg_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i8_monotonic:
+   %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: swpb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xchg_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i16_monotonic:
+   %old = atomicrmw xchg i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: swph w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xchg_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_monotonic:
+   %old = atomicrmw xchg i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swp w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xchg_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_monotonic:
+   %old = atomicrmw xchg i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swp x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xchg_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_noret_monotonic:
+   atomicrmw xchg i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swp w[[OLD:[0-9]+]], w[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define void @test_atomic_load_xchg_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_noret_monotonic:
+   atomicrmw xchg i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swp x[[OLD:[0-9]+]], x[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define i8 @test_atomic_load_xchg_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i8_release:
+   %old = atomicrmw xchg i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: swplb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xchg_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i16_release:
+   %old = atomicrmw xchg i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: swplh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xchg_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_release:
+   %old = atomicrmw xchg i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swpl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xchg_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_release:
+   %old = atomicrmw xchg i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swpl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xchg_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_noret_release:
+   atomicrmw xchg i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swpl w[[OLD:[0-9]+]], w[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define void @test_atomic_load_xchg_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_noret_release:
+   atomicrmw xchg i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swpl x[[OLD:[0-9]+]], x[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define i8 @test_atomic_load_xchg_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i8_seq_cst:
+   %old = atomicrmw xchg i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: swpalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xchg_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i16_seq_cst:
+   %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: swpalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xchg_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_seq_cst:
+   %old = atomicrmw xchg i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xchg_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_seq_cst:
+   %old = atomicrmw xchg i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xchg_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i32_noret_seq_cst:
+   atomicrmw xchg i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define void @test_atomic_load_xchg_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xchg_i64_noret_seq_cst:
+   atomicrmw xchg i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret void
+}
+
+define i8 @test_atomic_load_umax_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i8_acq_rel:
+   %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldumaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umax_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i16_acq_rel:
+   %old = atomicrmw umax i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldumaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umax_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_acq_rel:
+   %old = atomicrmw umax i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umax_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_acq_rel:
+   %old = atomicrmw umax i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umax_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_noret_acq_rel:
+   atomicrmw umax i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umax_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_noret_acq_rel:
+   atomicrmw umax i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umax_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i8_acquire:
+   %old = atomicrmw umax i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldumaxab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umax_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i16_acquire:
+   %old = atomicrmw umax i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldumaxah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umax_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_acquire:
+   %old = atomicrmw umax i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumaxa w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umax_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_acquire:
+   %old = atomicrmw umax i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumaxa x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umax_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_noret_acquire:
+   atomicrmw umax i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumaxa w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umax_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_noret_acquire:
+   atomicrmw umax i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumaxa x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umax_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i8_monotonic:
+   %old = atomicrmw umax i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldumaxb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umax_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i16_monotonic:
+   %old = atomicrmw umax i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldumaxh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umax_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_monotonic:
+   %old = atomicrmw umax i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumax w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umax_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_monotonic:
+   %old = atomicrmw umax i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumax x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umax_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_noret_monotonic:
+   atomicrmw umax i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stumax w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umax_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_noret_monotonic:
+   atomicrmw umax i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stumax x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umax_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i8_release:
+   %old = atomicrmw umax i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldumaxlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umax_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i16_release:
+   %old = atomicrmw umax i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldumaxlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umax_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_release:
+   %old = atomicrmw umax i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumaxl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umax_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_release:
+   %old = atomicrmw umax i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumaxl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umax_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_noret_release:
+   atomicrmw umax i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stumaxl w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umax_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_noret_release:
+   atomicrmw umax i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stumaxl x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umax_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i8_seq_cst:
+   %old = atomicrmw umax i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldumaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umax_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i16_seq_cst:
+   %old = atomicrmw umax i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldumaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umax_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_seq_cst:
+   %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umax_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_seq_cst:
+   %old = atomicrmw umax i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umax_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i32_noret_seq_cst:
+   atomicrmw umax i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umax_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umax_i64_noret_seq_cst:
+   atomicrmw umax i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umin_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i8_acq_rel:
+   %old = atomicrmw umin i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: lduminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umin_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i16_acq_rel:
+   %old = atomicrmw umin i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: lduminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umin_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_acq_rel:
+   %old = atomicrmw umin i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: lduminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umin_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_acq_rel:
+   %old = atomicrmw umin i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: lduminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umin_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_noret_acq_rel:
+   atomicrmw umin i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: lduminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umin_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_noret_acq_rel:
+   atomicrmw umin i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: lduminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umin_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i8_acquire:
+   %old = atomicrmw umin i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: lduminab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umin_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i16_acquire:
+   %old = atomicrmw umin i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: lduminah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umin_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_acquire:
+   %old = atomicrmw umin i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumina w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umin_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_acquire:
+   %old = atomicrmw umin i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumina x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umin_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_noret_acquire:
+   atomicrmw umin i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumina w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umin_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_noret_acquire:
+   atomicrmw umin i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumina x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umin_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i8_monotonic:
+   %old = atomicrmw umin i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: lduminb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umin_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i16_monotonic:
+   %old = atomicrmw umin i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: lduminh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umin_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_monotonic:
+   %old = atomicrmw umin i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldumin w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umin_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_monotonic:
+   %old = atomicrmw umin i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldumin x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umin_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_noret_monotonic:
+   atomicrmw umin i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stumin w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umin_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_noret_monotonic:
+   atomicrmw umin i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stumin x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umin_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i8_release:
+   %old = atomicrmw umin i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: lduminlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umin_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i16_release:
+   %old = atomicrmw umin i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: lduminlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umin_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_release:
+   %old = atomicrmw umin i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: lduminl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umin_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_release:
+   %old = atomicrmw umin i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: lduminl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umin_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_noret_release:
+   atomicrmw umin i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: stuminl w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umin_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_noret_release:
+   atomicrmw umin i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: stuminl x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_umin_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i8_seq_cst:
+   %old = atomicrmw umin i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: lduminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_umin_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i16_seq_cst:
+   %old = atomicrmw umin i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: lduminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_umin_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_seq_cst:
+   %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: lduminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_umin_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_seq_cst:
+   %old = atomicrmw umin i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: lduminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_umin_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i32_noret_seq_cst:
+   atomicrmw umin i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: lduminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_umin_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_umin_i64_noret_seq_cst:
+   atomicrmw umin i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: lduminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_xor_i8_acq_rel(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i8_acq_rel:
+   %old = atomicrmw xor i8* @var8, i8 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldeoralb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xor_i16_acq_rel(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i16_acq_rel:
+   %old = atomicrmw xor i16* @var16, i16 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldeoralh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xor_i32_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_acq_rel:
+   %old = atomicrmw xor i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldeoral w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xor_i64_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_acq_rel:
+   %old = atomicrmw xor i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldeoral x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xor_i32_noret_acq_rel(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_noret_acq_rel:
+   atomicrmw xor i32* @var32, i32 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldeoral w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_xor_i64_noret_acq_rel(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_noret_acq_rel:
+   atomicrmw xor i64* @var64, i64 %offset acq_rel
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldeoral x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_xor_i8_acquire(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i8_acquire:
+   %old = atomicrmw xor i8* @var8, i8 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldeorab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xor_i16_acquire(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i16_acquire:
+   %old = atomicrmw xor i16* @var16, i16 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldeorah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xor_i32_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_acquire:
+   %old = atomicrmw xor i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldeora w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xor_i64_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_acquire:
+   %old = atomicrmw xor i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldeora x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xor_i32_noret_acquire(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_noret_acquire:
+   atomicrmw xor i32* @var32, i32 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldeora w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_xor_i64_noret_acquire(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_noret_acquire:
+   atomicrmw xor i64* @var64, i64 %offset acquire
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldeora x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_xor_i8_monotonic(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i8_monotonic:
+   %old = atomicrmw xor i8* @var8, i8 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldeorb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xor_i16_monotonic(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i16_monotonic:
+   %old = atomicrmw xor i16* @var16, i16 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldeorh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xor_i32_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_monotonic:
+   %old = atomicrmw xor i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldeor w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xor_i64_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_monotonic:
+   %old = atomicrmw xor i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldeor x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xor_i32_noret_monotonic(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_noret_monotonic:
+   atomicrmw xor i32* @var32, i32 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: steor w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_xor_i64_noret_monotonic(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_noret_monotonic:
+   atomicrmw xor i64* @var64, i64 %offset monotonic
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: steor x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_xor_i8_release(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i8_release:
+   %old = atomicrmw xor i8* @var8, i8 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldeorlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xor_i16_release(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i16_release:
+   %old = atomicrmw xor i16* @var16, i16 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldeorlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xor_i32_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_release:
+   %old = atomicrmw xor i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldeorl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xor_i64_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_release:
+   %old = atomicrmw xor i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldeorl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xor_i32_noret_release(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_noret_release:
+   atomicrmw xor i32* @var32, i32 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: steorl w0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_xor_i64_noret_release(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_noret_release:
+   atomicrmw xor i64* @var64, i64 %offset release
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: steorl x0, [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define i8 @test_atomic_load_xor_i8_seq_cst(i8 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i8_seq_cst:
+   %old = atomicrmw xor i8* @var8, i8 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
+
+; CHECK: ldeoralb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i8 %old
+}
+
+define i16 @test_atomic_load_xor_i16_seq_cst(i16 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i16_seq_cst:
+   %old = atomicrmw xor i16* @var16, i16 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
+
+; CHECK: ldeoralh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i16 %old
+}
+
+define i32 @test_atomic_load_xor_i32_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_seq_cst:
+   %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldeoral w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i32 %old
+}
+
+define i64 @test_atomic_load_xor_i64_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_seq_cst:
+   %old = atomicrmw xor i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldeoral x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+
+   ret i64 %old
+}
+
+define void @test_atomic_load_xor_i32_noret_seq_cst(i32 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i32_noret_seq_cst:
+   atomicrmw xor i32* @var32, i32 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
+
+; CHECK: ldeoral w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+define void @test_atomic_load_xor_i64_noret_seq_cst(i64 %offset) nounwind {
+; CHECK-LABEL: test_atomic_load_xor_i64_noret_seq_cst:
+   atomicrmw xor i64* @var64, i64 %offset seq_cst
+; CHECK-NOT: dmb
+; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
+; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
+
+; CHECK: ldeoral x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
+; CHECK-NOT: dmb
+  ret void
+}
+
+
diff --git a/test/CodeGen/AArch64/bics.ll b/test/CodeGen/AArch64/bics.ll
index 53aa28ad913f..244aacbc0df3 100644
--- a/test/CodeGen/AArch64/bics.ll
+++ b/test/CodeGen/AArch64/bics.ll
@@ -2,7 +2,7 @@
 
 define i1 @andn_cmp(i32 %x, i32 %y) {
 ; CHECK-LABEL: andn_cmp:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    bics wzr, w1, w0
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
@@ -15,7 +15,7 @@ define i1 @andn_cmp(i32 %x, i32 %y) {
 
 define i1 @and_cmp(i32 %x, i32 %y) {
 ; CHECK-LABEL: and_cmp:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    bics wzr, w1, w0
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
@@ -27,7 +27,7 @@ define i1 @and_cmp(i32 %x, i32 %y) {
 
 define i1 @and_cmp_const(i32 %x) {
 ; CHECK-LABEL: and_cmp_const:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #43
 ; CHECK-NEXT:    bics wzr, w8, w0
 ; CHECK-NEXT:    cset w0, eq
diff --git a/test/CodeGen/AArch64/bitreverse.ll b/test/CodeGen/AArch64/bitreverse.ll
index 85496ab03214..139dd858b2e2 100644
--- a/test/CodeGen/AArch64/bitreverse.ll
+++ b/test/CodeGen/AArch64/bitreverse.ll
@@ -11,7 +11,7 @@ define <2 x i16> @f(<2 x i16> %a) {
 ; CHECK-DAG: fmov s0, [[REG2]]
 ; CHECK-DAG: mov [[REG3:w[0-9]+]], v0.s[1]
 ; CHECK-DAG: rbit [[REG4:w[0-9]+]], [[REG3]]
-; CHECK-DAG: ins v0.s[1], [[REG4]]
+; CHECK-DAG: mov v0.s[1], [[REG4]]
 ; CHECK-DAG: ushr v0.2s, v0.2s, #16
   %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
   ret <2 x i16> %b
diff --git a/test/CodeGen/AArch64/branch-relax-cbz.ll b/test/CodeGen/AArch64/branch-relax-cbz.ll
index d13c0f677bcb..cddecbd9babb 100644
--- a/test/CodeGen/AArch64/branch-relax-cbz.ll
+++ b/test/CodeGen/AArch64/branch-relax-cbz.ll
@@ -4,7 +4,7 @@
 ; CHECK: cmn x{{[0-9]+}}, #5
 ; CHECK-NEXT: b.le [[B2:LBB[0-9]+_[0-9]+]]
 
-; CHECK-NEXT: ; BB#1: ; %b3
+; CHECK-NEXT: ; %bb.1: ; %b3
 ; CHECK: ldr [[LOAD:w[0-9]+]]
 ; CHECK: cbnz [[LOAD]], [[B8:LBB[0-9]+_[0-9]+]]
 ; CHECK-NEXT: b [[B7:LBB[0-9]+_[0-9]+]]
diff --git a/test/CodeGen/AArch64/cfi_restore.mir b/test/CodeGen/AArch64/cfi_restore.mir
new file mode 100644
index 000000000000..92351f99cd28
--- /dev/null
+++ b/test/CodeGen/AArch64/cfi_restore.mir
@@ -0,0 +1,37 @@
+# RUN: llc -mtriple=aarch64-- -start-after prologepilog -o - %s | FileCheck %s
+---
+name:            fun
+# CHECK: .cfi_startproc
+tracksRegLiveness: true
+frameInfo:
+  stackSize:       16
+  maxAlignment:    8
+  hasCalls:        true
+stack:
+  - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: 0,
+      callee-saved-register: '%lr' }
+  - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 8, stack-id: 0,
+      callee-saved-register: '%fp' }
+body:             |
+  bb.0:
+    liveins: %fp, %lr
+
+    %sp = frame-setup SUBXri %sp, 16, 0
+    frame-setup STRXui killed %fp, %sp, 0 :: (store 8 into %stack.1)
+    frame-setup CFI_INSTRUCTION offset %w29, -16
+    ; CHECK: .cfi_offset w29, -16
+    frame-setup STRXui killed %lr, %sp, 1 :: (store 8 into %stack.0)
+    frame-setup CFI_INSTRUCTION offset %w30, -8
+    ; CHECK: .cfi_offset w30, -8
+    %fp = frame-setup ADDXri %sp, 0, 0
+    frame-setup CFI_INSTRUCTION def_cfa %w29, 16
+    %lr = LDRXui %sp, 1 :: (load 8 from %stack.0)
+    CFI_INSTRUCTION restore %w30
+    ; CHECK: .cfi_restore w30
+    %fp = LDRXui %sp, 0 :: (load 8 from %stack.1)
+    CFI_INSTRUCTION restore %w29
+    ; CHECK: .cfi_restore w29
+    %sp = ADDXri %sp, 16, 0
+    RET_ReallyLR
+    ; CHECK: .cfi_endproc
+...
diff --git a/test/CodeGen/AArch64/cmpxchg-idioms.ll b/test/CodeGen/AArch64/cmpxchg-idioms.ll
index 0c008c269794..da0f7073acef 100644
--- a/test/CodeGen/AArch64/cmpxchg-idioms.ll
+++ b/test/CodeGen/AArch64/cmpxchg-idioms.ll
@@ -91,3 +91,63 @@ end:
 
 declare void @bar()
 declare void @baz()
+
+define i1 @test_conditional2(i32 %a, i32 %b, i32* %c) {
+; CHECK-LABEL: test_conditional2:
+; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
+; CHECK: ldaxr [[LOADED:w[0-9]+]], [x19]
+; CHECK: cmp [[LOADED]], w21
+; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
+
+; CHECK: stlxr [[STATUS:w[0-9]+]], w20, [x19]
+; CHECK: cbnz [[STATUS]], [[LOOP]]
+; CHECK: orr [[STATUS]], wzr, #0x1
+; CHECK: b [[PH:LBB[0-9]+_[0-9]+]]
+
+; CHECK: [[FAILED]]:
+; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
+
+; verify the preheader is simplified by simplifycfg.
+; CHECK: [[PH]]:
+; CHECK: orr w22, wzr, #0x2
+; CHECK-NOT: orr w22, wzr, #0x4
+; CHECK-NOT: cmn w22, #4
+; CHECK: b [[LOOP2:LBB[0-9]+_[0-9]+]]
+; CHECK-NOT: b.ne [[LOOP2]]
+; CHECK-NOT: b {{LBB[0-9]+_[0-9]+}}
+; CHECK: bl _foo
+entry:
+  %pair = cmpxchg i32* %c, i32 %a, i32 %b seq_cst seq_cst
+  %success = extractvalue { i32, i1 } %pair, 1
+  br label %for.cond
+
+for.cond:                                         ; preds = %if.end, %entry
+  %i.0 = phi i32 [ 2, %entry ], [ %dec, %if.end ]
+  %changed.0.off0 = phi i1 [ %success, %entry ], [ %changed.1.off0, %if.end ]
+  %dec = add nsw i32 %i.0, -1
+  %tobool = icmp eq i32 %i.0, 0
+  br i1 %tobool, label %for.cond.cleanup, label %for.body
+
+for.cond.cleanup:                                 ; preds = %for.cond
+  %changed.0.off0.lcssa = phi i1 [ %changed.0.off0, %for.cond ]
+  ret i1 %changed.0.off0.lcssa
+
+for.body:                                         ; preds = %for.cond
+  %or = or i32 %a, %b
+  %idxprom = sext i32 %dec to i64
+  %arrayidx = getelementptr inbounds i32, i32* %c, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
+  %cmp = icmp eq i32 %or, %0
+  br i1 %cmp, label %if.end, label %if.then
+
+if.then:                                          ; preds = %for.body
+  store i32 %or, i32* %arrayidx, align 4
+  tail call void @foo()
+  br label %if.end
+
+if.end:                                           ; preds = %for.body, %if.then
+  %changed.1.off0 = phi i1 [ false, %if.then ], [ %changed.0.off0, %for.body ]
+  br label %for.cond
+}
+
+declare void @foo()
diff --git a/test/CodeGen/AArch64/concat_vector-scalar-combine.ll b/test/CodeGen/AArch64/concat_vector-scalar-combine.ll
index 3abb14241ea0..ce3b1f5e6b7b 100644
--- a/test/CodeGen/AArch64/concat_vector-scalar-combine.ll
+++ b/test/CodeGen/AArch64/concat_vector-scalar-combine.ll
@@ -38,9 +38,9 @@ entry:
 define <8 x i8> @test_concat_scalars_2x_v2i8_to_v8i8(i32 %x, i32 %y) #0 {
 entry:
 ; CHECK-LABEL: test_concat_scalars_2x_v2i8_to_v8i8:
-; CHECK-NEXT: fmov  s0, w0
-; CHECK-NEXT: ins.h v0[1], w1
-; CHECK-NEXT: ins.h v0[3], w1
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: mov.h v0[1], w1
+; CHECK-NEXT: mov.h v0[3], w1
 ; CHECK-NEXT: ret
   %tx = trunc i32 %x to i16
   %ty = trunc i32 %y to i16
@@ -54,7 +54,7 @@ define <8 x i8> @test_concat_scalars_2x_v4i8_to_v8i8_dup(i32 %x, i32 %y) #0 {
 entry:
 ; CHECK-LABEL: test_concat_scalars_2x_v4i8_to_v8i8_dup:
 ; CHECK-NEXT: fmov s0, w1
-; CHECK-NEXT: ins.s v0[1], w0
+; CHECK-NEXT: mov.s v0[1], w0
 ; CHECK-NEXT: ret
   %bx = bitcast i32 %x to <4 x i8>
   %by = bitcast i32 %y to <4 x i8>
@@ -66,9 +66,9 @@ define <8 x i16> @test_concat_scalars_2x_v2i16_to_v8i16_dup(i32 %x, i32 %y) #0 {
 entry:
 ; CHECK-LABEL: test_concat_scalars_2x_v2i16_to_v8i16_dup:
 ; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: ins.s v0[1], w1
-; CHECK-NEXT: ins.s v0[2], w1
-; CHECK-NEXT: ins.s v0[3], w0
+; CHECK-NEXT: mov.s v0[1], w1
+; CHECK-NEXT: mov.s v0[2], w1
+; CHECK-NEXT: mov.s v0[3], w0
 ; CHECK-NEXT: ret
   %bx = bitcast i32 %x to <2 x i16>
   %by = bitcast i32 %y to <2 x i16>
@@ -85,9 +85,9 @@ entry:
 ; CHECK-LABEL: test_concat_scalars_mixed_2x_v2i8_to_v8i8:
 ; CHECK-NEXT: fmov s[[X:[0-9]+]], w0
 ; CHECK-NEXT: mov.16b v0, v[[X]]
-; CHECK-NEXT: ins.h v0[1], v1[0]
-; CHECK-NEXT: ins.h v0[2], v[[X]][0]
-; CHECK-NEXT: ins.h v0[3], v1[0]
+; CHECK-NEXT: mov.h v0[1], v1[0]
+; CHECK-NEXT: mov.h v0[2], v[[X]][0]
+; CHECK-NEXT: mov.h v0[3], v1[0]
 ; CHECK-NEXT: ret
   %t = trunc i32 %x to i16
   %0 = bitcast i16 %t to <2 x i8>
@@ -100,9 +100,9 @@ define <2 x float> @test_concat_scalars_fp_2x_v2i8_to_v8i8(float %dummy, half %x
 entry:
 ; CHECK-LABEL: test_concat_scalars_fp_2x_v2i8_to_v8i8:
 ; CHECK-NEXT: mov.16b v0, v1
-; CHECK-NEXT: ins.h v0[1], v2[0]
-; CHECK-NEXT: ins.h v0[2], v1[0]
-; CHECK-NEXT: ins.h v0[3], v2[0]
+; CHECK-NEXT: mov.h v0[1], v2[0]
+; CHECK-NEXT: mov.h v0[2], v1[0]
+; CHECK-NEXT: mov.h v0[3], v2[0]
 ; CHECK-NEXT: ret
   %0 = bitcast half %x to <2 x i8>
   %y0 = bitcast half %y to <2 x i8>
diff --git a/test/CodeGen/AArch64/cpus.ll b/test/CodeGen/AArch64/cpus.ll
index f65144def245..5c8ac87f58b0 100644
--- a/test/CodeGen/AArch64/cpus.ll
+++ b/test/CodeGen/AArch64/cpus.ll
@@ -4,13 +4,16 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a55 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a75 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m2 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=falkor 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=saphira 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
diff --git a/test/CodeGen/AArch64/dllexport.ll b/test/CodeGen/AArch64/dllexport.ll
new file mode 100644
index 000000000000..287c545610c0
--- /dev/null
+++ b/test/CodeGen/AArch64/dllexport.ll
@@ -0,0 +1,74 @@
+; RUN: llc -mtriple aarch64-windows-gnu -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-GNU
+; RUN: llc -mtriple aarch64-windows-msvc -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-MSVC
+
+define void @f() {
+  ret void
+}
+
+define dllexport void @g() {
+  ret void
+}
+
+define dllexport void @h() unnamed_addr {
+  ret void
+}
+
+declare dllexport void @i()
+
+define linkonce_odr dllexport void @j() {
+  ret void
+}
+
+define linkonce_odr dllexport void @k() alwaysinline {
+  ret void
+}
+
+define weak_odr dllexport void @l() {
+  ret void
+}
+
+@m = dllexport global i32 0, align 4
+@n = dllexport unnamed_addr constant i32 0
+@o = common dllexport global i32 0, align 4
+@p = weak_odr dllexport global i32 0, align 4
+@q = weak_odr dllexport unnamed_addr constant i32 0
+
+@r = dllexport alias void (), void () * @f
+@s = dllexport alias void (), void () * @g
+@t = dllexport alias void (), void () * @f
+@u = weak_odr dllexport alias void (), void () * @g
+
+; CHECK: .section .drectve
+; CHECK-GNU-NOT: -export:f
+; CHECK-GNU: -export:g
+; CHECK-GNU-SAME: -export:h
+; CHECK-GNU-NOT: -export:i
+; CHECK-GNU-SAME: -export:j
+; CHECK-GNU-SAME: -export:k
+; CHECK-GNU-SAME: -export:l
+; CHECK-GNU-SAME: -export:m,data
+; CHECK-GNU-SAME: -export:n,data
+; CHECK-GNU-SAME: -export:o,data
+; CHECK-GNU-SAME: -export:p,data
+; CHECK-GNU-SAME: -export:q,data
+; CHECK-GNU-SAME: -export:r
+; CHECK-GNU-SAME: -export:s
+; CHECK-GNU-SAME: -export:t
+; CHECK-GNU-SAME: -export:u
+; CHECK-MSVC-NOT: /EXPORT:f
+; CHECK-MSVC: /EXPORT:g
+; CHECK-MSVC-SAME: /EXPORT:h
+; CHECK-MSVC-NOT: /EXPORT:i
+; CHECK-MSVC-SAME: /EXPORT:j
+; CHECK-MSVC-SAME: /EXPORT:k
+; CHECK-MSVC-SAME: /EXPORT:l
+; CHECK-MSVC-SAME: /EXPORT:m,DATA
+; CHECK-MSVC-SAME: /EXPORT:n,DATA
+; CHECK-MSVC-SAME: /EXPORT:o,DATA
+; CHECK-MSVC-SAME: /EXPORT:p,DATA
+; CHECK-MSVC-SAME: /EXPORT:q,DATA
+; CHECK-MSVC-SAME: /EXPORT:r
+; CHECK-MSVC-SAME: /EXPORT:s
+; CHECK-MSVC-SAME: /EXPORT:t
+; CHECK-MSVC-SAME: /EXPORT:u
+
diff --git a/test/CodeGen/AArch64/dllimport.ll b/test/CodeGen/AArch64/dllimport.ll
new file mode 100644
index 000000000000..fad049a54cd2
--- /dev/null
+++ b/test/CodeGen/AArch64/dllimport.ll
@@ -0,0 +1,54 @@
+; RUN: llc -mtriple aarch64-unknown-windows-msvc -filetype asm -o - %s | FileCheck %s
+
+@var = external dllimport global i32
+@ext = external global i32
+declare dllimport i32 @external()
+declare i32 @internal()
+
+define i32 @get_var() {
+  %1 = load i32, i32* @var, align 4
+  ret i32 %1
+}
+
+; CHECK-LABEL: get_var
+; CHECK: adrp x8, __imp_var
+; CHECK: ldr x8, [x8, __imp_var]
+; CHECK: ldr w0, [x8]
+; CHECK: ret
+
+define i32 @get_ext() {
+  %1 = load i32, i32* @ext, align 4
+  ret i32 %1
+}
+
+; CHECK-LABEL: get_ext
+; CHECK: adrp x8, ext
+; CHECK: ldr w0, [x8, ext]
+; CHECK: ret
+
+define i32* @get_var_pointer() {
+  ret i32* @var
+}
+
+; CHECK-LABEL: get_var_pointer
+; CHECK: adrp x0, __imp_var
+; CHECK: ldr x0, [x0, __imp_var]
+; CHECK: ret
+
+define i32 @call_external() {
+  %call = tail call i32 @external()
+  ret i32 %call
+}
+
+; CHECK-LABEL: call_external
+; CHECK: adrp x0, __imp_external
+; CHECK: ldr x0, [x0, __imp_external]
+; CHECK: br x0
+
+define i32 @call_internal() {
+  %call = tail call i32 @internal()
+  ret i32 %call
+}
+
+; CHECK-LABEL: call_internal
+; CHECK: b internal
diff --git a/test/CodeGen/AArch64/dwarf-cfi.ll b/test/CodeGen/AArch64/dwarf-cfi.ll
new file mode 100644
index 000000000000..a75bcd19c69c
--- /dev/null
+++ b/test/CodeGen/AArch64/dwarf-cfi.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple aarch64-windows-gnu -filetype=asm -o - %s | FileCheck %s
+
+define void @_Z1gv() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  invoke void @_Z1fv()
+          to label %try.cont unwind label %lpad
+
+lpad:
+  %0 = landingpad { i8*, i32 }
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  %2 = tail call i8* @__cxa_begin_catch(i8* %1) #2
+  tail call void @__cxa_end_catch()
+  br label %try.cont
+
+try.cont:
+  ret void
+}
+
+declare void @_Z1fv()
+
+declare i32 @__gxx_personality_v0(...)
+
+declare i8* @__cxa_begin_catch(i8*)
+
+declare void @__cxa_end_catch()
+
+; CHECK-LABEL: _Z1gv:
+; CHECK:    .cfi_startproc
+; CHECK:    .cfi_personality 0, __gxx_personality_v0
+; CHECK:    .cfi_lsda 0, .Lexception0
+; CHECK:    str x30, [sp, #-16]!
+; CHECK:    .cfi_def_cfa_offset 16
+; CHECK:    .cfi_offset w30, -16
+; CHECK:    ldr x30, [sp], #16
+; CHECK:    .cfi_endproc
diff --git a/test/CodeGen/AArch64/emutls_generic.ll b/test/CodeGen/AArch64/emutls_generic.ll
index 03473cf80ee4..f205078ed411 100644
--- a/test/CodeGen/AArch64/emutls_generic.ll
+++ b/test/CodeGen/AArch64/emutls_generic.ll
@@ -4,6 +4,10 @@
 ; RUN:     | FileCheck -check-prefix=ARM_64 %s
 ; RUN: llc < %s -emulated-tls -mtriple=aarch64-linux-android -O3 \
 ; RUN:     | FileCheck -check-prefix=ARM_64 %s
+; RUN: llc < %s -emulated-tls -mtriple=aarch64-windows-gnu -O3 \
+; RUN:     | FileCheck -check-prefix=ARM_64 %s
+; RUN: llc < %s -emulated-tls -mtriple=aarch64-apple-darwin -O3 \
+; RUN:     | FileCheck -check-prefix=DARWIN %s
 
 ; Make sure that TLS symbols are emitted in expected order.
 
@@ -46,7 +50,7 @@ entry:
 ; ARM_64-NEXT:   .xword 0
 ; ARM_64-NEXT:   .xword __emutls_t.external_y
 ; ARM_64-NOT:    __emutls_v.external_x:
-; ARM_64:        .section .rodata,
+; ARM_64:        .section .r{{o?}}data,
 ; ARM_64-LABEL:  __emutls_t.external_y:
 ; ARM_64-NEXT:   .byte 7
 ; ARM_64:        .data{{$}}
@@ -57,6 +61,41 @@ entry:
 ; ARM_64-NEXT:   .xword 16
 ; ARM_64-NEXT:   .xword 0
 ; ARM_64-NEXT:   .xword __emutls_t.internal_y
-; ARM_64:        .section .rodata,
+; ARM_64:        .section .r{{o?}}data,
 ; ARM_64-LABEL:  __emutls_t.internal_y:
 ; ARM_64-NEXT:   .xword 9
+
+; DARWIN-LABEL:  _get_external_x:
+; DARWIN:        ___emutls_v.external_x
+; DARWIN:        ___emutls_get_address
+; DARWIN-LABEL:  _get_external_y:
+; DARWIN:        ___emutls_v.external_y
+; DARWIN:        ___emutls_get_address
+; DARWIN-LABEL:  _get_internal_y:
+; DARWIN:        ___emutls_v.internal_y
+; DARWIN:        ___emutls_get_address
+; DARWIN-NOT:    ___emutls_t.external_x
+; DARWIN-NOT:    ___emutls_v.external_x:
+; DARWIN:        .section __DATA,__data
+; DARWIN:        .globl ___emutls_v.external_y
+; DARWIN:        .p2align 3
+; DARWIN-LABEL:  ___emutls_v.external_y:
+; DARWIN-NEXT:   .quad 1
+; DARWIN-NEXT:   .quad 2
+; DARWIN-NEXT:   .quad 0
+; DARWIN-NEXT:   .quad ___emutls_t.external_y
+; DARWIN-NOT:    ___emutls_v.external_x:
+; DARWIN:        .section __TEXT,__const
+; DARWIN-LABEL:  ___emutls_t.external_y:
+; DARWIN-NEXT:   .byte 7
+; DARWIN:        .section __DATA,__data
+; DARWIN-NOT:    .globl ___emutls_v
+; DARWIN:        .p2align 3
+; DARWIN-LABEL:  ___emutls_v.internal_y:
+; DARWIN-NEXT:   .quad 8
+; DARWIN-NEXT:   .quad 16
+; DARWIN-NEXT:   .quad 0
+; DARWIN-NEXT:   .quad ___emutls_t.internal_y
+; DARWIN:        .section __TEXT,__const
+; DARWIN-LABEL:  ___emutls_t.internal_y:
+; DARWIN-NEXT:   .quad 9
diff --git a/test/CodeGen/AArch64/f16-imm.ll b/test/CodeGen/AArch64/f16-imm.ll
new file mode 100644
index 000000000000..84c27312d1e1
--- /dev/null
+++ b/test/CodeGen/AArch64/f16-imm.ll
@@ -0,0 +1,105 @@
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ILLEGAL
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+zcz | FileCheck %s --check-prefix=CHECK-ZCZ
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-NOFP16 --check-prefix=CHECK-ILLEGAL
+
+define half @Const0() {
+entry:
+  ret half 0xH0000
+}
+; CHECK-DAG-ILLEGAL-LABEL:  Const0:
+; CHECK-DAG-ILLEGAL-NEXT:   fmov  h0, wzr
+; CHECK-DAG-ILLEGAL-NEXT:   ret
+
+; CHECK-ZCZ-LABEL:  Const0:
+; CHECK-ZCZ:        movi  v0.2d, #0000000000000000
+; CHECK-ZCZ-NEXT:   ret
+
+define half @Const1() {
+entry:
+  ret half 0xH3C00
+}
+; CHECK-DAG-LABEL: Const1:
+; CHECK-DAG-NEXT:   fmov h0, #1.00000000
+; CHECK-DAG-NEXT:   ret
+
+; CHECK-NOFP16:        .[[LBL1:LCPI1_[0-9]]]:
+; CHECK-NOFP16-NEXT:   .hword  15360 // half 1
+; CHECK-NOFP16-LABEL:  Const1:
+; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL1]]
+; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL1]]]
+
+define half @Const2() {
+entry:
+  ret half 0xH3000
+}
+; CHECK-DAG-LABEL: Const2:
+; CHECK-DAG-NEXT:   fmov h0, #0.12500000
+; CHECK-DAG-NEXT:   ret
+
+; CHECK-NOFP16:        .[[LBL2:LCPI2_[0-9]]]:
+; CHECK-NOFP16-NEXT:   .hword  12288 // half 0.125
+; CHECK-NOFP16-LABEL:  Const2:
+; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL2]]
+; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL2]]]
+
+define half @Const3() {
+entry:
+  ret half 0xH4F80
+}
+; CHECK-DAG-LABEL: Const3:
+; CHECK-DAG-NEXT:   fmov h0, #30.00000000
+; CHECK-DAG-NEXT:   ret
+
+; CHECK-NOFP16:        .[[LBL3:LCPI3_[0-9]]]:
+; CHECK-NOFP16-NEXT:   .hword  20352 // half 30
+; CHECK-NOFP16-LABEL:  Const3:
+; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL3]]
+; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL3]]]
+
+
+define half @Const4() {
+entry:
+  ret half 0xH4FC0
+}
+; CHECK-DAG-LABEL: Const4:
+; CHECK-DAG-NEXT:  fmov h0, #31.00000000
+; CHECK-DAG-NEXT:  ret
+
+; CHECK-NOFP16:        .[[LBL4:LCPI4_[0-9]]]:
+; CHECK-NOFP16-NEXT:   .hword  20416                    // half 31
+; CHECK-NOFP16-LABEL:  Const4:
+; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL4]]
+; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL4]]]
+
+define half @Const5() {
+entry:
+  ret half 0xH2FF0
+}
+; CHECK-ILLEGAL:        .[[LBL5:LCPI5_[0-9]]]:
+; CHECK-ILLEGAL-NEXT:   .hword  12272                   // half 0.12402
+; CHECK-ILLEGAL-LABEL:  Const5:
+; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL5]]
+; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL5]]]
+
+define half @Const6() {
+entry:
+  ret half 0xH4FC1
+}
+; CHECK-ILLEGAL:        .[[LBL6:LCPI6_[0-9]]]:
+; CHECK-ILLEGAL-NEXT:   .hword  20417                   // half 31.016
+; CHECK-ILLEGAL-LABEL:  Const6:
+; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL6]]
+; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL6]]]
+
+
+define half @Const7() {
+entry:
+  ret half 0xH5000
+}
+; CHECK-ILLEGAL:        .[[LBL7:LCPI7_[0-9]]]:
+; CHECK-ILLEGAL-NEXT:   .hword  20480                   // half 32
+; CHECK-ILLEGAL-LABEL:  Const7:
+; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL7]]
+; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL7]]]
+
+
diff --git a/test/CodeGen/AArch64/f16-instructions.ll b/test/CodeGen/AArch64/f16-instructions.ll
index 613c71a558bd..1bec17f78adb 100644
--- a/test/CodeGen/AArch64/f16-instructions.ll
+++ b/test/CodeGen/AArch64/f16-instructions.ll
@@ -1,342 +1,481 @@
-; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -disable-fp-elim | FileCheck %s --check-prefix=CHECK-CVT --check-prefix=CHECK-COMMON
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -disable-fp-elim | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-FP16
 
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
-; CHECK-LABEL: test_fadd:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fadd s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fadd:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fadd s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fadd:
+; CHECK-FP16-NEXT:  fadd h0, h0, h1
+; CHECK-FP16-NEXT:  ret
+
 define half @test_fadd(half %a, half %b) #0 {
   %r = fadd half %a, %b
   ret half %r
 }
 
-; CHECK-LABEL: test_fsub:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fsub s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fsub:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fsub s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fsub:
+; CHECK-FP16-NEXT: fsub h0, h0, h1
+; CHECK-FP16-NEXT: ret
+
 define half @test_fsub(half %a, half %b) #0 {
   %r = fsub half %a, %b
   ret half %r
 }
 
-; CHECK-LABEL: test_fmul:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmul s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fmul:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fmul s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fmul:
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: ret
+
 define half @test_fmul(half %a, half %b) #0 {
   %r = fmul half %a, %b
   ret half %r
 }
 
-; CHECK-LABEL: test_fdiv:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fdiv s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fdiv:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fdiv s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fdiv:
+; CHECK-FP16-NEXT: fdiv	h0, h0, h1
+; CHECK-FP16-NEXT: ret
+
 define half @test_fdiv(half %a, half %b) #0 {
   %r = fdiv half %a, %b
   ret half %r
 }
 
-; CHECK-LABEL: test_frem:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: bl {{_?}}fmodf
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_frem:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: fcvt s1, h1
+; CHECK-COMMON-NEXT: bl {{_?}}fmodf
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_frem(half %a, half %b) #0 {
   %r = frem half %a, %b
   ret half %r
 }
 
-; CHECK-LABEL: test_store:
-; CHECK-NEXT: str  h0, [x0]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_store:
+; CHECK-COMMON-NEXT: str  h0, [x0]
+; CHECK-COMMON-NEXT: ret
 define void @test_store(half %a, half* %b) #0 {
   store half %a, half* %b
   ret void
 }
 
-; CHECK-LABEL: test_load:
-; CHECK-NEXT: ldr  h0, [x0]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_load:
+; CHECK-COMMON-NEXT: ldr  h0, [x0]
+; CHECK-COMMON-NEXT: ret
 define half @test_load(half* %a) #0 {
   %r = load half, half* %a
   ret half %r
 }
 
-
 declare half @test_callee(half %a, half %b) #0
 
-; CHECK-LABEL: test_call:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: bl {{_?}}test_callee
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_call:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: bl {{_?}}test_callee
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_call(half %a, half %b) #0 {
   %r = call half @test_callee(half %a, half %b)
   ret half %r
 }
 
-; CHECK-LABEL: test_call_flipped:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: mov.16b  v2, v0
-; CHECK-NEXT: mov.16b  v0, v1
-; CHECK-NEXT: mov.16b  v1, v2
-; CHECK-NEXT: bl {{_?}}test_callee
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_call_flipped:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: mov.16b  v2, v0
+; CHECK-COMMON-NEXT: mov.16b  v0, v1
+; CHECK-COMMON-NEXT: mov.16b  v1, v2
+; CHECK-COMMON-NEXT: bl {{_?}}test_callee
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_call_flipped(half %a, half %b) #0 {
   %r = call half @test_callee(half %b, half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_tailcall_flipped:
-; CHECK-NEXT: mov.16b  v2, v0
-; CHECK-NEXT: mov.16b  v0, v1
-; CHECK-NEXT: mov.16b  v1, v2
-; CHECK-NEXT: b {{_?}}test_callee
+; CHECK-COMMON-LABEL: test_tailcall_flipped:
+; CHECK-COMMON-NEXT: mov.16b  v2, v0
+; CHECK-COMMON-NEXT: mov.16b  v0, v1
+; CHECK-COMMON-NEXT: mov.16b  v1, v2
+; CHECK-COMMON-NEXT: b {{_?}}test_callee
 define half @test_tailcall_flipped(half %a, half %b) #0 {
   %r = tail call half @test_callee(half %b, half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_select:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: cmp  w0, #0
-; CHECK-NEXT: fcsel s0, s0, s1, ne
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_select:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: cmp  w0, #0
+; CHECK-CVT-NEXT: fcsel s0, s0, s1, ne
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_select:
+; CHECK-FP16-NEXT: cmp w0, #0
+; CHECK-FP16-NEXT: fcsel h0, h0, h1, ne
+; CHECK-FP16-NEXT: ret
+
 define half @test_select(half %a, half %b, i1 zeroext %c) #0 {
   %r = select i1 %c, half %a, half %b
   ret half %r
 }
 
-; CHECK-LABEL: test_select_cc:
-; CHECK-DAG: fcvt s3, h3
-; CHECK-DAG: fcvt s2, h2
-; CHECK-DAG: fcvt s1, h1
-; CHECK-DAG: fcvt s0, h0
-; CHECK-DAG: fcmp s2, s3
-; CHECK-DAG: cset [[CC:w[0-9]+]], ne
-; CHECK-DAG: cmp [[CC]], #0
-; CHECK-NEXT: fcsel s0, s0, s1, ne
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_select_cc:
+; CHECK-CVT-DAG: fcvt s3, h3
+; CHECK-CVT-DAG: fcvt s2, h2
+; CHECK-CVT-DAG: fcvt s1, h1
+; CHECK-CVT-DAG: fcvt s0, h0
+; CHECK-CVT-DAG: fcmp s2, s3
+; CHECK-CVT-DAG: cset [[CC:w[0-9]+]], ne
+; CHECK-CVT-DAG: cmp [[CC]], #0
+; CHECK-CVT-NEXT: fcsel s0, s0, s1, ne
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_select_cc:
+; CHECK-FP16-NEXT: fcmp h2, h3
+; CHECK-FP16-NEXT: fcsel h0, h0, h1, ne
+; CHECK-FP16-NEXT: ret
+
 define half @test_select_cc(half %a, half %b, half %c, half %d) #0 {
   %cc = fcmp une half %c, %d
   %r = select i1 %cc, half %a, half %b
   ret half %r
 }
 
-; CHECK-LABEL: test_select_cc_f32_f16:
-; CHECK-DAG:   fcvt s2, h2
-; CHECK-DAG:   fcvt s3, h3
-; CHECK-NEXT:  fcmp s2, s3
-; CHECK-NEXT:  fcsel s0, s0, s1, ne
-; CHECK-NEXT:  ret
+; CHECK-CVT-LABEL: test_select_cc_f32_f16:
+; CHECK-CVT-DAG:   fcvt s2, h2
+; CHECK-CVT-DAG:   fcvt s3, h3
+; CHECK-CVT-NEXT:  fcmp s2, s3
+; CHECK-CVT-NEXT:  fcsel s0, s0, s1, ne
+; CHECK-CVT-NEXT:  ret
+
+; CHECK-FP16-LABEL: test_select_cc_f32_f16:
+; CHECK-FP16-NEXT: fcmp	h2, h3
+; CHECK-FP16-NEXT: fcsel	s0, s0, s1, ne
+; CHECK-FP16-NEXT: ret
+
 define float @test_select_cc_f32_f16(float %a, float %b, half %c, half %d) #0 {
   %cc = fcmp une half %c, %d
   %r = select i1 %cc, float %a, float %b
   ret float %r
 }
 
-; CHECK-LABEL: test_select_cc_f16_f32:
-; CHECK-DAG:  fcvt s0, h0
-; CHECK-DAG:  fcvt s1, h1
-; CHECK-DAG:  fcmp s2, s3
-; CHECK-DAG:  cset w8, ne
-; CHECK-NEXT: cmp w8, #0
-; CHECK-NEXT: fcsel s0, s0, s1, ne
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_select_cc_f16_f32:
+; CHECK-CVT-DAG:  fcvt s0, h0
+; CHECK-CVT-DAG:  fcvt s1, h1
+; CHECK-CVT-DAG:  fcmp s2, s3
+; CHECK-CVT-DAG:  cset w8, ne
+; CHECK-CVT-NEXT: cmp w8, #0
+; CHECK-CVT-NEXT: fcsel s0, s0, s1, ne
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_select_cc_f16_f32:
+; CHECK-FP16-NEXT: fcmp	s2, s3
+; CHECK-FP16-NEXT: fcsel h0, h0, h1, ne
+; CHECK-FP16-NEXT: ret
+
 define half @test_select_cc_f16_f32(half %a, half %b, float %c, float %d) #0 {
   %cc = fcmp une float %c, %d
   %r = select i1 %cc, half %a, half %b
   ret half %r
 }
 
-; CHECK-LABEL: test_fcmp_une:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, ne
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_une:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, ne
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_une:
+; CHECK-FP16-NEXT: fcmp	h0, h1
+; CHECK-FP16-NEXT: cset w0, ne
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_une(half %a, half %b) #0 {
   %r = fcmp une half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_ueq:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset [[TRUE:w[0-9]+]], eq
-; CHECK-NEXT: csinc w0, [[TRUE]], wzr, vc
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ueq:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset [[TRUE:w[0-9]+]], eq
+; CHECK-CVT-NEXT: csinc w0, [[TRUE]], wzr, vc
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_ueq:
+; CHECK-FP16-NEXT: fcmp	h0, h1
+; CHECK-FP16-NEXT: cset [[TRUE:w[0-9]+]], eq
+; CHECK-FP16-NEXT: csinc w0, [[TRUE]], wzr, vc
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_ueq(half %a, half %b) #0 {
   %r = fcmp ueq half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_ugt:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, hi
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ugt:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, hi
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_ugt:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, hi
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_ugt(half %a, half %b) #0 {
   %r = fcmp ugt half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_uge:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, pl
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_uge:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, pl
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_uge:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, pl
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_uge(half %a, half %b) #0 {
   %r = fcmp uge half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_ult:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, lt
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ult:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, lt
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_ult:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, lt
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_ult(half %a, half %b) #0 {
   %r = fcmp ult half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_ule:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, le
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ule:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, le
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_ule:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, le
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_ule(half %a, half %b) #0 {
   %r = fcmp ule half %a, %b
   ret i1 %r
 }
 
+; CHECK-CVT-LABEL: test_fcmp_uno:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, vs
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_uno:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, vs
+; CHECK-FP16-NEXT: ret
 
-; CHECK-LABEL: test_fcmp_uno:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, vs
-; CHECK-NEXT: ret
 define i1 @test_fcmp_uno(half %a, half %b) #0 {
   %r = fcmp uno half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_one:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset [[TRUE:w[0-9]+]], mi
-; CHECK-NEXT: csinc w0, [[TRUE]], wzr, le
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_one:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset [[TRUE:w[0-9]+]], mi
+; CHECK-CVT-NEXT: csinc w0, [[TRUE]], wzr, le
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_one:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset [[TRUE:w[0-9]+]], mi
+; CHECK-FP16-NEXT: csinc w0, [[TRUE]], wzr, le
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_one(half %a, half %b) #0 {
   %r = fcmp one half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_oeq:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, eq
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_oeq:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, eq
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_oeq:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, eq
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_oeq(half %a, half %b) #0 {
   %r = fcmp oeq half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_ogt:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, gt
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ogt:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, gt
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_ogt:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, gt
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_ogt(half %a, half %b) #0 {
   %r = fcmp ogt half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_oge:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, ge
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_oge:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, ge
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_oge:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, ge
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_oge(half %a, half %b) #0 {
   %r = fcmp oge half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_olt:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, mi
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_olt:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, mi
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_olt:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, mi
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_olt(half %a, half %b) #0 {
   %r = fcmp olt half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_ole:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, ls
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ole:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, ls
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_ole:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, ls
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_ole(half %a, half %b) #0 {
   %r = fcmp ole half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_fcmp_ord:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: cset  w0, vc
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fcmp_ord:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: cset  w0, vc
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fcmp_ord:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: cset  w0, vc
+; CHECK-FP16-NEXT: ret
+
 define i1 @test_fcmp_ord(half %a, half %b) #0 {
   %r = fcmp ord half %a, %b
   ret i1 %r
 }
 
-; CHECK-LABEL: test_br_cc:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: b.mi [[BRCC_ELSE:.?LBB[0-9_]+]]
-; CHECK-NEXT: str  wzr, [x0]
-; CHECK-NEXT: ret
-; CHECK-NEXT: [[BRCC_ELSE]]:
-; CHECK-NEXT: str  wzr, [x1]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_br_cc:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: b.mi [[BRCC_ELSE:.?LBB[0-9_]+]]
+; CHECK-CVT-NEXT: str  wzr, [x0]
+; CHECK-CVT-NEXT: ret
+; CHECK-CVT-NEXT: [[BRCC_ELSE]]:
+; CHECK-CVT-NEXT: str  wzr, [x1]
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_br_cc:
+; CHECK-FP16-NEXT: fcmp h0, h1
+; CHECK-FP16-NEXT: b.mi [[BRCC_ELSE:.?LBB[0-9_]+]]
+; CHECK-FP16-NEXT: str  wzr, [x0]
+; CHECK-FP16-NEXT: ret
+; CHECK-FP16-NEXT: [[BRCC_ELSE]]:
+; CHECK-FP16-NEXT: str  wzr, [x1]
+; CHECK-FP16-NEXT: ret
+
 define void @test_br_cc(half %a, half %b, i32* %p1, i32* %p2) #0 {
   %c = fcmp uge half %a, %b
   br i1 %c, label %then, label %else
@@ -348,16 +487,16 @@ else:
   ret void
 }
 
-; CHECK-LABEL: test_phi:
-; CHECK: mov  x[[PTR:[0-9]+]], x0
-; CHECK: ldr  h[[AB:[0-9]+]], [x[[PTR]]]
-; CHECK: [[LOOP:LBB[0-9_]+]]:
-; CHECK: mov.16b  v[[R:[0-9]+]], v[[AB]]
-; CHECK: ldr  h[[AB]], [x[[PTR]]]
-; CHECK: mov  x0, x[[PTR]]
-; CHECK: bl {{_?}}test_dummy
-; CHECK: mov.16b  v0, v[[R]]
-; CHECK: ret
+; CHECK-COMMON-LABEL: test_phi:
+; CHECK-COMMON: mov  x[[PTR:[0-9]+]], x0
+; CHECK-COMMON: ldr  h[[AB:[0-9]+]], [x[[PTR]]]
+; CHECK-COMMON: [[LOOP:LBB[0-9_]+]]:
+; CHECK-COMMON: mov.16b  v[[R:[0-9]+]], v[[AB]]
+; CHECK-COMMON: ldr  h[[AB]], [x[[PTR]]]
+; CHECK-COMMON: mov  x0, x[[PTR]]
+; CHECK-COMMON: bl {{_?}}test_dummy
+; CHECK-COMMON: mov.16b  v0, v[[R]]
+; CHECK-COMMON: ret
 define half @test_phi(half* %p1) #0 {
 entry:
   %a = load half, half* %p1
@@ -370,153 +509,205 @@ loop:
 return:
   ret half %r
 }
+
 declare i1 @test_dummy(half* %p1) #0
 
-; CHECK-LABEL: test_fptosi_i32:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvtzs w0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fptosi_i32:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvtzs w0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fptosi_i32:
+; CHECK-FP16-NEXT: fcvtzs w0, h0
+; CHECK-FP16-NEXT: ret
+
 define i32 @test_fptosi_i32(half %a) #0 {
   %r = fptosi half %a to i32
   ret i32 %r
 }
 
-; CHECK-LABEL: test_fptosi_i64:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvtzs x0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fptosi_i64:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvtzs x0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fptosi_i64:
+; CHECK-FP16-NEXT: fcvtzs x0, h0
+; CHECK-FP16-NEXT: ret
+
 define i64 @test_fptosi_i64(half %a) #0 {
   %r = fptosi half %a to i64
   ret i64 %r
 }
 
-; CHECK-LABEL: test_fptoui_i32:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvtzu w0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fptoui_i32:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvtzu w0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fptoui_i32:
+; CHECK-FP16-NEXT: fcvtzu w0, h0
+; CHECK-FP16-NEXT: ret
+
 define i32 @test_fptoui_i32(half %a) #0 {
   %r = fptoui half %a to i32
   ret i32 %r
 }
 
-; CHECK-LABEL: test_fptoui_i64:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvtzu x0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fptoui_i64:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvtzu x0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fptoui_i64:
+; CHECK-FP16-NEXT: fcvtzu x0, h0
+; CHECK-FP16-NEXT: ret
+
 define i64 @test_fptoui_i64(half %a) #0 {
   %r = fptoui half %a to i64
   ret i64 %r
 }
 
-; CHECK-LABEL: test_uitofp_i32:
-; CHECK-NEXT: ucvtf s0, w0
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_uitofp_i32:
+; CHECK-CVT-NEXT: ucvtf s0, w0
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_uitofp_i32:
+; CHECK-FP16-NEXT: ucvtf h0, w0
+; CHECK-FP16-NEXT: ret
+
 define half @test_uitofp_i32(i32 %a) #0 {
   %r = uitofp i32 %a to half
   ret half %r
 }
 
-; CHECK-LABEL: test_uitofp_i64:
-; CHECK-NEXT: ucvtf s0, x0
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_uitofp_i64:
+; CHECK-CVT-NEXT: ucvtf s0, x0
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_uitofp_i64:
+; CHECK-FP16-NEXT: ucvtf h0, x0
+; CHECK-FP16-NEXT: ret
+
 define half @test_uitofp_i64(i64 %a) #0 {
   %r = uitofp i64 %a to half
   ret half %r
 }
 
-; CHECK-LABEL: test_sitofp_i32:
-; CHECK-NEXT: scvtf s0, w0
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_sitofp_i32:
+; CHECK-CVT-NEXT: scvtf s0, w0
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_sitofp_i32:
+; CHECK-FP16-NEXT: scvtf h0, w0
+; CHECK-FP16-NEXT: ret
+
 define half @test_sitofp_i32(i32 %a) #0 {
   %r = sitofp i32 %a to half
   ret half %r
 }
 
-; CHECK-LABEL: test_sitofp_i64:
-; CHECK-NEXT: scvtf s0, x0
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_sitofp_i64:
+; CHECK-CVT-NEXT: scvtf s0, x0
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_sitofp_i64:
+; CHECK-FP16-NEXT: scvtf h0, x0
+; CHECK-FP16-NEXT: ret
 define half @test_sitofp_i64(i64 %a) #0 {
   %r = sitofp i64 %a to half
   ret half %r
 }
 
-; CHECK-LABEL: test_uitofp_i32_fadd:
-; CHECK-NEXT: ucvtf s1, w0
-; CHECK-NEXT: fcvt h1, s1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fadd s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_uitofp_i32_fadd:
+; CHECK-CVT-NEXT: ucvtf s1, w0
+; CHECK-CVT-NEXT: fcvt h1, s1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fadd s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_uitofp_i32_fadd:
+; CHECK-FP16-NEXT: ucvtf h1, w0
+; CHECK-FP16-NEXT: fadd h0, h0, h1
+; CHECK-FP16-NEXT: ret
+
 define half @test_uitofp_i32_fadd(i32 %a, half %b) #0 {
   %c = uitofp i32 %a to half
   %r = fadd half %b, %c
   ret half %r
 }
 
-; CHECK-LABEL: test_sitofp_i32_fadd:
-; CHECK-NEXT: scvtf s1, w0
-; CHECK-NEXT: fcvt h1, s1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fadd s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_sitofp_i32_fadd:
+; CHECK-CVT-NEXT: scvtf s1, w0
+; CHECK-CVT-NEXT: fcvt h1, s1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fadd s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_sitofp_i32_fadd:
+; CHECK-FP16-NEXT: scvtf h1, w0
+; CHECK-FP16-NEXT: fadd h0, h0, h1
+; CHECK-FP16-NEXT: ret
+
 define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 {
   %c = sitofp i32 %a to half
   %r = fadd half %b, %c
   ret half %r
 }
 
-; CHECK-LABEL: test_fptrunc_float:
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_fptrunc_float:
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ret
 
 define half @test_fptrunc_float(float %a) #0 {
   %r = fptrunc float %a to half
   ret half %r
 }
 
-; CHECK-LABEL: test_fptrunc_double:
-; CHECK-NEXT: fcvt h0, d0
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_fptrunc_double:
+; CHECK-COMMON-NEXT: fcvt h0, d0
+; CHECK-COMMON-NEXT: ret
 define half @test_fptrunc_double(double %a) #0 {
   %r = fptrunc double %a to half
   ret half %r
 }
 
-; CHECK-LABEL: test_fpext_float:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_fpext_float:
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: ret
 define float @test_fpext_float(half %a) #0 {
   %r = fpext half %a to float
   ret float %r
 }
 
-; CHECK-LABEL: test_fpext_double:
-; CHECK-NEXT: fcvt d0, h0
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_fpext_double:
+; CHECK-COMMON-NEXT: fcvt d0, h0
+; CHECK-COMMON-NEXT: ret
 define double @test_fpext_double(half %a) #0 {
   %r = fpext half %a to double
   ret double %r
 }
 
 
-; CHECK-LABEL: test_bitcast_halftoi16:
-; CHECK-NEXT: fmov w0, s0
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_bitcast_halftoi16:
+; CHECK-COMMON-NEXT: fmov w0, s0
+; CHECK-COMMON-NEXT: ret
 define i16 @test_bitcast_halftoi16(half %a) #0 {
   %r = bitcast half %a to i16
   ret i16 %r
 }
 
-; CHECK-LABEL: test_bitcast_i16tohalf:
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_bitcast_i16tohalf:
+; CHECK-COMMON-NEXT: fmov s0, w0
+; CHECK-COMMON-NEXT: ret
 define half @test_bitcast_i16tohalf(i16 %a) #0 {
   %r = bitcast i16 %a to half
   ret half %r
@@ -546,209 +737,254 @@ declare half @llvm.nearbyint.f16(half %a) #0
 declare half @llvm.round.f16(half %a) #0
 declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0
 
-; CHECK-LABEL: test_sqrt:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fsqrt s0, s0
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_sqrt:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fsqrt s0, s0
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_sqrt:
+; CHECK-FP16-NEXT: fsqrt h0, h0
+; CHECK-FP16-NEXT: ret
+
 define half @test_sqrt(half %a) #0 {
   %r = call half @llvm.sqrt.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_powi:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: bl {{_?}}__powisf2
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_powi:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: bl {{_?}}__powisf2
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_powi(half %a, i32 %b) #0 {
   %r = call half @llvm.powi.f16(half %a, i32 %b)
   ret half %r
 }
 
-; CHECK-LABEL: test_sin:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: bl {{_?}}sinf
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_sin:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: bl {{_?}}sinf
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_sin(half %a) #0 {
   %r = call half @llvm.sin.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_cos:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: bl {{_?}}cosf
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_cos:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: bl {{_?}}cosf
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_cos(half %a) #0 {
   %r = call half @llvm.cos.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_pow:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: bl {{_?}}powf
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_pow:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: fcvt s1, h1
+; CHECK-COMMON-NEXT: bl {{_?}}powf
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_pow(half %a, half %b) #0 {
   %r = call half @llvm.pow.f16(half %a, half %b)
   ret half %r
 }
 
-; CHECK-LABEL: test_exp:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: bl {{_?}}expf
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_exp:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: bl {{_?}}expf
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_exp(half %a) #0 {
   %r = call half @llvm.exp.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_exp2:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: bl {{_?}}exp2f
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_exp2:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: bl {{_?}}exp2f
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_exp2(half %a) #0 {
   %r = call half @llvm.exp2.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_log:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: bl {{_?}}logf
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_log:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: bl {{_?}}logf
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_log(half %a) #0 {
   %r = call half @llvm.log.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_log10:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: bl {{_?}}log10f
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_log10:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: bl {{_?}}log10f
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_log10(half %a) #0 {
   %r = call half @llvm.log10.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_log2:
-; CHECK-NEXT: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov  x29, sp
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: bl {{_?}}log2f
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_log2:
+; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-COMMON-NEXT: mov  x29, sp
+; CHECK-COMMON-NEXT: fcvt s0, h0
+; CHECK-COMMON-NEXT: bl {{_?}}log2f
+; CHECK-COMMON-NEXT: fcvt h0, s0
+; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
+; CHECK-COMMON-NEXT: ret
 define half @test_log2(half %a) #0 {
   %r = call half @llvm.log2.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_fma:
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmadd s0, s0, s1, s2
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fma:
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fmadd s0, s0, s1, s2
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fma:
+; CHECK-FP16-NEXT: fmadd h0, h0, h1, h2
+; CHECK-FP16-NEXT: ret
+
 define half @test_fma(half %a, half %b, half %c) #0 {
   %r = call half @llvm.fma.f16(half %a, half %b, half %c)
   ret half %r
 }
 
-; CHECK-LABEL: test_fabs:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fabs s0, s0
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fabs:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fabs s0, s0
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fabs:
+; CHECK-FP16-NEXT: fabs h0, h0
+; CHECK-FP16-NEXT: ret
+
 define half @test_fabs(half %a) #0 {
   %r = call half @llvm.fabs.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_minnum:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_minnum:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fminnm s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_minnum:
+; CHECK-FP16-NEXT: fminnm h0, h0, h1
+; CHECK-FP16-NEXT: ret
+
 define half @test_minnum(half %a, half %b) #0 {
   %r = call half @llvm.minnum.f16(half %a, half %b)
   ret half %r
 }
 
-; CHECK-LABEL: test_maxnum:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_maxnum:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fmaxnm s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_maxnum:
+; CHECK-FP16-NEXT: fmaxnm h0, h0, h1
+; CHECK-FP16-NEXT: ret
+
 define half @test_maxnum(half %a, half %b) #0 {
   %r = call half @llvm.maxnum.f16(half %a, half %b)
   ret half %r
 }
 
-; CHECK-LABEL: test_copysign:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: movi.4s v2, #128, lsl #24
-; CHECK-NEXT: bit.16b v0, v1, v2
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_copysign:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: movi.4s v2, #128, lsl #24
+; CHECK-CVT-NEXT: bit.16b v0, v1, v2
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_copysign:
+; CHECK-FP16-NEXT: movi.8h v2, #128, lsl #8
+; CHECK-FP16-NEXT: bit.16b  v0, v1, v2
+; CHECK-FP16-NEXT: ret
+
 define half @test_copysign(half %a, half %b) #0 {
   %r = call half @llvm.copysign.f16(half %a, half %b)
   ret half %r
 }
 
-; CHECK-LABEL: test_copysign_f32:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: movi.4s v2, #128, lsl #24
-; CHECK-NEXT: bit.16b v0, v1, v2
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_copysign_f32:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: movi.4s v2, #128, lsl #24
+; CHECK-CVT-NEXT: bit.16b v0, v1, v2
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_copysign_f32:
+; CHECK-FP16-NEXT: fcvt h1, s1
+; CHECK-FP16-NEXT: movi.8h	v2, #128, lsl #8
+; CHECK-FP16-NEXT: bit.16b v0, v1, v2
+; CHECK-FP16-NEXT: ret
+
 define half @test_copysign_f32(half %a, float %b) #0 {
   %tb = fptrunc float %b to half
   %r = call half @llvm.copysign.f16(half %a, half %tb)
   ret half %r
 }
 
-; CHECK-LABEL: test_copysign_f64:
-; CHECK-NEXT: fcvt s1, d1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: movi.4s v2, #128, lsl #24
-; CHECK-NEXT: bit.16b v0, v1, v2
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_copysign_f64:
+; CHECK-CVT-NEXT: fcvt s1, d1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: movi.4s v2, #128, lsl #24
+; CHECK-CVT-NEXT: bit.16b v0, v1, v2
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_copysign_f64:
+; CHECK-FP16-NEXT: fcvt h1, d1
+; CHECK-FP16-NEXT: movi.8h v2, #128, lsl #8
+; CHECK-FP16-NEXT: bit.16b v0, v1, v2
+; CHECK-FP16-NEXT: ret
+
 define half @test_copysign_f64(half %a, double %b) #0 {
   %tb = fptrunc double %b to half
   %r = call half @llvm.copysign.f16(half %a, half %tb)
@@ -758,88 +994,131 @@ define half @test_copysign_f64(half %a, double %b) #0 {
 ; Check that the FP promotion will use a truncating FP_ROUND, so we can fold
 ; away the (fpext (fp_round <result>)) here.
 
-; CHECK-LABEL: test_copysign_extended:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: movi.4s v2, #128, lsl #24
-; CHECK-NEXT: bit.16b v0, v1, v2
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_copysign_extended:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: movi.4s v2, #128, lsl #24
+; CHECK-CVT-NEXT: bit.16b v0, v1, v2
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_copysign_extended:
+; CHECK-FP16-NEXT: movi.8h v2, #128, lsl #8
+; CHECK-FP16-NEXT: bit.16b v0, v1, v2
+; CHECK-FP16-NEXT: fcvt s0, h0
+; CHECK-FP16-NEXT: ret
+
 define float @test_copysign_extended(half %a, half %b) #0 {
   %r = call half @llvm.copysign.f16(half %a, half %b)
   %xr = fpext half %r to float
   ret float %xr
 }
 
-; CHECK-LABEL: test_floor:
-; CHECK-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
-; CHECK-NEXT: frintm [[INT32:s[0-9]+]], [[FLOAT32]]
-; CHECK-NEXT: fcvt h0, [[INT32]]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_floor:
+; CHECK-CVT-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
+; CHECK-CVT-NEXT: frintm [[INT32:s[0-9]+]], [[FLOAT32]]
+; CHECK-CVT-NEXT: fcvt h0, [[INT32]]
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_floor:
+; CHECK-FP16-NEXT: frintm h0, h0
+; CHECK-FP16-NEXT: ret
+
 define half @test_floor(half %a) #0 {
   %r = call half @llvm.floor.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_ceil:
-; CHECK-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
-; CHECK-NEXT: frintp [[INT32:s[0-9]+]], [[FLOAT32]]
-; CHECK-NEXT: fcvt h0, [[INT32]]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_ceil:
+; CHECK-CVT-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
+; CHECK-CVT-NEXT: frintp [[INT32:s[0-9]+]], [[FLOAT32]]
+; CHECK-CVT-NEXT: fcvt h0, [[INT32]]
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_ceil:
+; CHECK-FP16-NEXT: frintp h0, h0
+; CHECK-FP16-NEXT: ret
+
 define half @test_ceil(half %a) #0 {
   %r = call half @llvm.ceil.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_trunc:
-; CHECK-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
-; CHECK-NEXT: frintz [[INT32:s[0-9]+]], [[FLOAT32]]
-; CHECK-NEXT: fcvt h0, [[INT32]]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_trunc:
+; CHECK-CVT-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
+; CHECK-CVT-NEXT: frintz [[INT32:s[0-9]+]], [[FLOAT32]]
+; CHECK-CVT-NEXT: fcvt h0, [[INT32]]
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_trunc:
+; CHECK-FP16-NEXT: frintz h0, h0
+; CHECK-FP16-NEXT: ret
+
 define half @test_trunc(half %a) #0 {
   %r = call half @llvm.trunc.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_rint:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: frintx s0, s0
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_rint:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: frintx s0, s0
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_rint:
+; CHECK-FP16-NEXT: frintx h0, h0
+; CHECK-FP16-NEXT: ret
+
 define half @test_rint(half %a) #0 {
   %r = call half @llvm.rint.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_nearbyint:
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: frinti s0, s0
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_nearbyint:
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: frinti s0, s0
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_nearbyint:
+; CHECK-FP16-NEXT: frinti h0, h0
+; CHECK-FP16-NEXT: ret
+
 define half @test_nearbyint(half %a) #0 {
   %r = call half @llvm.nearbyint.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_round:
-; CHECK-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
-; CHECK-NEXT: frinta [[INT32:s[0-9]+]], [[FLOAT32]]
-; CHECK-NEXT: fcvt h0, [[INT32]]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_round:
+; CHECK-CVT-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
+; CHECK-CVT-NEXT: frinta [[INT32:s[0-9]+]], [[FLOAT32]]
+; CHECK-CVT-NEXT: fcvt h0, [[INT32]]
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_round:
+; CHECK-FP16-NEXT: frinta h0, h0
+; CHECK-FP16-NEXT: ret
+
 define half @test_round(half %a) #0 {
   %r = call half @llvm.round.f16(half %a)
   ret half %r
 }
 
-; CHECK-LABEL: test_fmuladd:
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmul s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fcvt s1, h2
-; CHECK-NEXT: fadd s0, s0, s1
-; CHECK-NEXT: fcvt h0, s0
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: test_fmuladd:
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fmul s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fcvt s1, h2
+; CHECK-CVT-NEXT: fadd s0, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s0
+; CHECK-CVT-NEXT: ret
+
+; CHECK-FP16-LABEL: test_fmuladd:
+; CHECK-FP16-NEXT: fmul h0, h0, h1
+; CHECK-FP16-NEXT: fadd h0, h0, h2
+; CHECK-FP16-NEXT: ret
+
 define half @test_fmuladd(half %a, half %b, half %c) #0 {
   %r = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
   ret half %r
diff --git a/test/CodeGen/AArch64/falkor-hwpf-fix.mir b/test/CodeGen/AArch64/falkor-hwpf-fix.mir
index 70da36cdb89a..38622ae0e49a 100644
--- a/test/CodeGen/AArch64/falkor-hwpf-fix.mir
+++ b/test/CodeGen/AArch64/falkor-hwpf-fix.mir
@@ -330,3 +330,26 @@ body: |
   bb.1:
     RET_ReallyLR
 ...
+---
+# Check that we treat sp based loads as non-prefetching.
+
+# CHECK-LABEL: name: hwpf_spbase
+# CHECK-NOT: ORRXrs %xzr
+# CHECK: LDRWui %x15
+# CHECK: LDRWui %sp
+name:            hwpf_spbase
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: %w0, %x15
+
+    %w1 = LDRWui %x15, 0 :: ("aarch64-strided-access" load 4)
+    %w17 = LDRWui %sp, 0
+
+    %w0 = SUBWri %w0, 1, 0
+    %wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
+    Bcc 9, %bb.0, implicit %nzcv
+
+  bb.1:
+    RET_ReallyLR
+...
diff --git a/test/CodeGen/AArch64/fast-isel-assume.ll b/test/CodeGen/AArch64/fast-isel-assume.ll
index d39a907407db..50f510a09b63 100644
--- a/test/CodeGen/AArch64/fast-isel-assume.ll
+++ b/test/CodeGen/AArch64/fast-isel-assume.ll
@@ -3,7 +3,7 @@
 ; Check that we ignore the assume intrinsic.
 
 ; CHECK-LABEL: test:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
 define void @test(i32 %a) {
   %tmp0 = icmp slt i32 %a, 0
diff --git a/test/CodeGen/AArch64/fast-isel-atomic.ll b/test/CodeGen/AArch64/fast-isel-atomic.ll
index 195b8befc8e1..ec612616ae2a 100644
--- a/test/CodeGen/AArch64/fast-isel-atomic.ll
+++ b/test/CodeGen/AArch64/fast-isel-atomic.ll
@@ -5,7 +5,7 @@
 ; currently match, so we might as well check both!  Feel free to remove SDAG.
 
 ; CHECK-LABEL: atomic_store_monotonic_8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  strb  w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_monotonic_8(i8* %p, i8 %val) #0 {
@@ -14,7 +14,7 @@ define void @atomic_store_monotonic_8(i8* %p, i8 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_monotonic_8_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  strb w1, [x0, #1]
 ; CHECK-NEXT:  ret
 define void @atomic_store_monotonic_8_off(i8* %p, i8 %val) #0 {
@@ -24,7 +24,7 @@ define void @atomic_store_monotonic_8_off(i8* %p, i8 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_monotonic_16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  strh  w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_monotonic_16(i16* %p, i16 %val) #0 {
@@ -33,7 +33,7 @@ define void @atomic_store_monotonic_16(i16* %p, i16 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_monotonic_16_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  strh w1, [x0, #2]
 ; CHECK-NEXT:  ret
 define void @atomic_store_monotonic_16_off(i16* %p, i16 %val) #0 {
@@ -43,7 +43,7 @@ define void @atomic_store_monotonic_16_off(i16* %p, i16 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_monotonic_32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  str  w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_monotonic_32(i32* %p, i32 %val) #0 {
@@ -52,7 +52,7 @@ define void @atomic_store_monotonic_32(i32* %p, i32 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_monotonic_32_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  str w1, [x0, #4]
 ; CHECK-NEXT:  ret
 define void @atomic_store_monotonic_32_off(i32* %p, i32 %val) #0 {
@@ -62,7 +62,7 @@ define void @atomic_store_monotonic_32_off(i32* %p, i32 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_monotonic_64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  str  x1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_monotonic_64(i64* %p, i64 %val) #0 {
@@ -71,7 +71,7 @@ define void @atomic_store_monotonic_64(i64* %p, i64 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_monotonic_64_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  str x1, [x0, #8]
 ; CHECK-NEXT:  ret
 define void @atomic_store_monotonic_64_off(i64* %p, i64 %val) #0 {
@@ -81,7 +81,7 @@ define void @atomic_store_monotonic_64_off(i64* %p, i64 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_release_8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  stlrb w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_release_8(i8* %p, i8 %val) #0 {
@@ -90,7 +90,7 @@ define void @atomic_store_release_8(i8* %p, i8 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_release_8_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  add x0, x0, #1
 ; CHECK-NEXT:  stlrb w1, [x0]
 ; CHECK-NEXT:  ret
@@ -101,7 +101,7 @@ define void @atomic_store_release_8_off(i8* %p, i8 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_release_16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  stlrh w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_release_16(i16* %p, i16 %val) #0 {
@@ -110,7 +110,7 @@ define void @atomic_store_release_16(i16* %p, i16 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_release_16_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  add x0, x0, #2
 ; CHECK-NEXT:  stlrh w1, [x0]
 ; CHECK-NEXT:  ret
@@ -121,7 +121,7 @@ define void @atomic_store_release_16_off(i16* %p, i16 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_release_32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  stlr w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_release_32(i32* %p, i32 %val) #0 {
@@ -130,7 +130,7 @@ define void @atomic_store_release_32(i32* %p, i32 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_release_32_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  add x0, x0, #4
 ; CHECK-NEXT:  stlr w1, [x0]
 ; CHECK-NEXT:  ret
@@ -141,7 +141,7 @@ define void @atomic_store_release_32_off(i32* %p, i32 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_release_64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  stlr x1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_release_64(i64* %p, i64 %val) #0 {
@@ -150,7 +150,7 @@ define void @atomic_store_release_64(i64* %p, i64 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_release_64_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  add x0, x0, #8
 ; CHECK-NEXT:  stlr x1, [x0]
 ; CHECK-NEXT:  ret
@@ -162,7 +162,7 @@ define void @atomic_store_release_64_off(i64* %p, i64 %val) #0 {
 
 
 ; CHECK-LABEL: atomic_store_seq_cst_8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  stlrb w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_seq_cst_8(i8* %p, i8 %val) #0 {
@@ -171,7 +171,7 @@ define void @atomic_store_seq_cst_8(i8* %p, i8 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_seq_cst_8_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  add x0, x0, #1
 ; CHECK-NEXT:  stlrb w1, [x0]
 ; CHECK-NEXT:  ret
@@ -182,7 +182,7 @@ define void @atomic_store_seq_cst_8_off(i8* %p, i8 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_seq_cst_16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  stlrh w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_seq_cst_16(i16* %p, i16 %val) #0 {
@@ -191,7 +191,7 @@ define void @atomic_store_seq_cst_16(i16* %p, i16 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_seq_cst_16_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  add x0, x0, #2
 ; CHECK-NEXT:  stlrh w1, [x0]
 ; CHECK-NEXT:  ret
@@ -202,7 +202,7 @@ define void @atomic_store_seq_cst_16_off(i16* %p, i16 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_seq_cst_32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  stlr w1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_seq_cst_32(i32* %p, i32 %val) #0 {
@@ -211,7 +211,7 @@ define void @atomic_store_seq_cst_32(i32* %p, i32 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_seq_cst_32_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  add x0, x0, #4
 ; CHECK-NEXT:  stlr w1, [x0]
 ; CHECK-NEXT:  ret
@@ -222,7 +222,7 @@ define void @atomic_store_seq_cst_32_off(i32* %p, i32 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_seq_cst_64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  stlr x1, [x0]
 ; CHECK-NEXT:  ret
 define void @atomic_store_seq_cst_64(i64* %p, i64 %val) #0 {
@@ -231,7 +231,7 @@ define void @atomic_store_seq_cst_64(i64* %p, i64 %val) #0 {
 }
 
 ; CHECK-LABEL: atomic_store_seq_cst_64_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT:  add x0, x0, #8
 ; CHECK-NEXT:  stlr x1, [x0]
 ; CHECK-NEXT:  ret
diff --git a/test/CodeGen/AArch64/fast-isel-cmp-vec.ll b/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
index 89b368fa19bb..d5b64c5363e1 100644
--- a/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
+++ b/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
@@ -8,9 +8,9 @@
 
 define <2 x i32> @icmp_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: icmp_v2i32:
-; CHECK:      ; BB#0:
+; CHECK:      ; %bb.0:
 ; CHECK-NEXT:  cmeq.2s [[CMP:v[0-9]+]], v0, #0
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.2s [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.8b v0, [[CMP]], [[MASK]]
 ; CHECK-NEXT:  ret
@@ -23,9 +23,9 @@ bb2:
 
 define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: icmp_constfold_v2i32:
-; CHECK:      ; BB#0:
+; CHECK:      ; %bb.0:
 ; CHECK-NEXT:  movi d[[CMP:[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.2s [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.8b v0, v[[CMP]], [[MASK]]
 ; CHECK-NEXT:  ret
@@ -38,10 +38,10 @@ bb2:
 
 define <4 x i32> @icmp_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: icmp_v4i32:
-; CHECK:      ; BB#0:
+; CHECK:      ; %bb.0:
 ; CHECK-NEXT:  cmeq.4s [[CMP:v[0-9]+]], v0, #0
 ; CHECK-NEXT:  xtn.4h [[CMPV4I16:v[0-9]+]], [[CMP]]
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]]
 ; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
@@ -55,9 +55,9 @@ bb2:
 
 define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: icmp_constfold_v4i32:
-; CHECK:      ; BB#0:
+; CHECK:      ; %bb.0:
 ; CHECK-NEXT:  movi d[[CMP:[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
 ; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
@@ -71,9 +71,9 @@ bb2:
 
 define <16 x i8> @icmp_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: icmp_v16i8:
-; CHECK:      ; BB#0:
+; CHECK:      ; %bb.0:
 ; CHECK-NEXT:  cmeq.16b [[CMP:v[0-9]+]], v0, #0
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.16b [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.16b v0, [[CMP]], [[MASK]]
 ; CHECK-NEXT:  ret
@@ -86,9 +86,9 @@ bb2:
 
 define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: icmp_constfold_v16i8:
-; CHECK:      ; BB#0:
+; CHECK:      ; %bb.0:
 ; CHECK-NEXT:  movi.2d [[CMP:v[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.16b [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.16b v0, [[CMP]], [[MASK]]
 ; CHECK-NEXT:  ret
diff --git a/test/CodeGen/AArch64/fast-isel-cmpxchg.ll b/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
index 7ef625abab20..f03955c4dcd3 100644
--- a/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
+++ b/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
@@ -6,7 +6,7 @@
 ; CHECK-NEXT:     ldaxr [[OLD:w[0-9]+]], [x0]
 ; CHECK-NEXT:     cmp [[OLD]], w1
 ; CHECK-NEXT:     b.ne [[DONE:.LBB[0-9_]+]]
-; CHECK-NEXT: // BB#2:
+; CHECK-NEXT: // %bb.2:
 ; CHECK-NEXT:     stlxr [[STATUS]], w2, [x0]
 ; CHECK-NEXT:     cbnz [[STATUS]], [[RETRY]]
 ; CHECK-NEXT: [[DONE]]:
@@ -25,14 +25,14 @@ define i32 @cmpxchg_monotonic_32(i32* %p, i32 %cmp, i32 %new, i32* %ps) #0 {
 }
 
 ; CHECK-LABEL: cmpxchg_acq_rel_32_load:
-; CHECK:      // BB#0:
+; CHECK:      // %bb.0:
 ; CHECK:     ldr [[NEW:w[0-9]+]], [x2]
 ; CHECK-NEXT: [[RETRY:.LBB[0-9_]+]]:
 ; CHECK-NEXT:     mov [[STATUS:w[0-9]+]], #0
 ; CHECK-NEXT:     ldaxr [[OLD:w[0-9]+]], [x0]
 ; CHECK-NEXT:     cmp [[OLD]], w1
 ; CHECK-NEXT:     b.ne [[DONE:.LBB[0-9_]+]]
-; CHECK-NEXT: // BB#2:
+; CHECK-NEXT: // %bb.2:
 ; CHECK-NEXT:     stlxr [[STATUS]], [[NEW]], [x0]
 ; CHECK-NEXT:     cbnz [[STATUS]], [[RETRY]]
 ; CHECK-NEXT: [[DONE]]:
@@ -57,7 +57,7 @@ define i32 @cmpxchg_acq_rel_32_load(i32* %p, i32 %cmp, i32* %pnew, i32* %ps) #0
 ; CHECK-NEXT:     ldaxr [[OLD:x[0-9]+]], [x0]
 ; CHECK-NEXT:     cmp [[OLD]], x1
 ; CHECK-NEXT:     b.ne [[DONE:.LBB[0-9_]+]]
-; CHECK-NEXT: // BB#2:
+; CHECK-NEXT: // %bb.2:
 ; CHECK-NEXT:     stlxr [[STATUS]], x2, [x0]
 ; CHECK-NEXT:     cbnz [[STATUS]], [[RETRY]]
 ; CHECK-NEXT: [[DONE]]:
diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll
index e52b601b1454..aeafc127494b 100644
--- a/test/CodeGen/AArch64/fcvt-int.ll
+++ b/test/CodeGen/AArch64/fcvt-int.ll
@@ -152,7 +152,7 @@ define double @test_bitcasti64todouble(i64 %in) {
 
 define double @bitcast_fabs(double %x) {
 ; CHECK-LABEL: bitcast_fabs:
-; CHECK:       ; BB#0:
+; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    fabs d0, d0
 ; CHECK-NEXT:    ret
 ;
@@ -164,7 +164,7 @@ define double @bitcast_fabs(double %x) {
 
 define float @bitcast_fneg(float %x) {
 ; CHECK-LABEL: bitcast_fneg:
-; CHECK:       ; BB#0:
+; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    fneg s0, s0
 ; CHECK-NEXT:    ret
 ;
diff --git a/test/CodeGen/AArch64/fold-constants.ll b/test/CodeGen/AArch64/fold-constants.ll
index c0fec4d171cd..719d3f46950f 100644
--- a/test/CodeGen/AArch64/fold-constants.ll
+++ b/test/CodeGen/AArch64/fold-constants.ll
@@ -19,9 +19,19 @@ entry:
 
 ; PR25763 - folding constant vector comparisons with sign-extended result
 define <8 x i16> @dotests_458() {
+; CHECK-LABEL: .LCPI1_0:
+; CHECK:       .hword  0                       // 0x0
+; CHECK-NEXT:  .hword  0                       // 0x0
+; CHECK-NEXT:  .hword  65535                   // 0xffff
+; CHECK-NEXT:  .hword  0                       // 0x0
+; CHECK-NEXT:  .hword  0                       // 0x0
+; CHECK-NEXT:  .hword  0                       // 0x0
+; CHECK-NEXT:  .hword  0                       // 0x0
+; CHECK-NEXT:  .hword  0                       // 0x0
+
 ; CHECK-LABEL: dotests_458
-; CHECK:       movi d0, #0x00000000ff0000
-; CHECK-NEXT:  sshll v0.8h, v0.8b, #0
+; CHECK:       adrp    x8, .LCPI1_0
+; CHECK-NEXT:  ldr     q0, [x8, :lo12:.LCPI1_0]
 ; CHECK-NEXT:  ret
 entry:
   %vclz_v.i = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> <i8 127, i8 38, i8 -1, i8 -128, i8 127, i8 0, i8 0, i8 0>, i1 false) #6
diff --git a/test/CodeGen/AArch64/fp-cond-sel.ll b/test/CodeGen/AArch64/fp-cond-sel.ll
index 4d9cb21ddc3d..f74e9c350942 100644
--- a/test/CodeGen/AArch64/fp-cond-sel.ll
+++ b/test/CodeGen/AArch64/fp-cond-sel.ll
@@ -12,7 +12,7 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
   %tst1 = icmp ugt i32 %lhs32, %rhs32
   %val1 = select i1 %tst1, float 0.0, float 1.0
   store float %val1, float* @varfloat
-; CHECK-DAG: movi v[[FLT0:[0-9]+]].2d, #0
+; CHECK-DAG: fmov s[[FLT0:[0-9]+]], wzr
 ; CHECK-DAG: fmov s[[FLT1:[0-9]+]], #1.0
 ; CHECK: fcsel {{s[0-9]+}}, s[[FLT0]], s[[FLT1]], hi
 
diff --git a/test/CodeGen/AArch64/fp16-v16-instructions.ll b/test/CodeGen/AArch64/fp16-v16-instructions.ll
index 1af2bd10912f..eafc5d9df7fb 100644
--- a/test/CodeGen/AArch64/fp16-v16-instructions.ll
+++ b/test/CodeGen/AArch64/fp16-v16-instructions.ll
@@ -11,8 +11,8 @@ define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
-; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
+; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
 
   %1 = sitofp <16 x i32> %a to <16 x half>
   ret <16 x half> %1
@@ -44,8 +44,8 @@ define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {
 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
-; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
+; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
 
   %1 = sitofp <16 x i64> %a to <16 x half>
   ret <16 x half> %1
@@ -62,8 +62,8 @@ define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {
 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
-; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
+; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
 
   %1 = uitofp <16 x i32> %a to <16 x half>
   ret <16 x half> %1
@@ -95,8 +95,8 @@ define <16 x half> @uitofp_i64(<16 x i64> %a) #0 {
 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
-; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
+; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
+; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
 
   %1 = uitofp <16 x i64> %a to <16 x half>
   ret <16 x half> %1
diff --git a/test/CodeGen/AArch64/fp16-v4-instructions.ll b/test/CodeGen/AArch64/fp16-v4-instructions.ll
index b39ff08db39a..fbdd8f984e8c 100644
--- a/test/CodeGen/AArch64/fp16-v4-instructions.ll
+++ b/test/CodeGen/AArch64/fp16-v4-instructions.ll
@@ -1,12 +1,17 @@
-; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-CVT --check-prefix=CHECK-COMMON
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK-FP16 --check-prefix=CHECK-COMMON
 
 define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
 entry:
-; CHECK-LABEL: add_h:
-; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
-; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
-; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
-; CHECK: fcvtn v0.4h, [[RES]]
+; CHECK-CVT-LABEL: add_h:
+; CHECK-CVT-DAG:   fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
+; CHECK-CVT-DAG:   fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
+; CHECK-CVT-NEXT:  fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
+; CHECK-CVT-NEXT:  fcvtn v0.4h, [[RES]]
+
+; CHECK-FP16-LABEL: add_h:
+; CHECK-FP16:       fadd  v0.4h, v0.4h, v1.4h
+; CHECK-FP16-NEXT:  ret
   %0 = fadd <4 x half> %a, %b
   ret <4 x half> %0
 }
@@ -14,20 +19,24 @@ entry:
 
 define <4 x half> @build_h4(<4 x half> %a) {
 entry:
-; CHECK-LABEL: build_h4:
-; CHECK: mov [[GPR:w[0-9]+]], #15565
-; CHECK: dup v0.4h, [[GPR]]
+; CHECK-COMMON-LABEL: build_h4:
+; CHECK-COMMON:       mov [[GPR:w[0-9]+]], #15565
+; CHECK-COMMON-NEXT:  dup v0.4h, [[GPR]]
   ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
 }
 
 
 define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
 entry:
-; CHECK-LABEL: sub_h:
-; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
-; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
-; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
-; CHECK: fcvtn v0.4h, [[RES]]
+; CHECK-CVT-LABEL: sub_h:
+; CHECK-CVT-DAG:   fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
+; CHECK-CVT-DAG:   fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
+; CHECK-CVT-NEXT:  fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
+; CHECK-CVT-NEXT:  fcvtn v0.4h, [[RES]]
+
+; CHECK-FP16-LABEL: sub_h:
+; CHECK-FP16:       fsub  v0.4h, v0.4h, v1.4h
+; CHECK-FP16-NEXT:  ret
   %0 = fsub <4 x half> %a, %b
   ret <4 x half> %0
 }
@@ -35,11 +44,15 @@ entry:
 
 define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) {
 entry:
-; CHECK-LABEL: mul_h:
-; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
-; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
-; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
-; CHECK: fcvtn v0.4h, [[RES]]
+; CHECK-CVT-LABEL: mul_h:
+; CHECK-CVT-DAG:   fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
+; CHECK-CVT-DAG:   fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
+; CHECK-CVT-NEXT:  fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
+; CHECK-CVT-NEXT:  fcvtn v0.4h, [[RES]]
+
+; CHECK-FP16-LABEL: mul_h:
+; CHECK-FP16:       fmul  v0.4h, v0.4h, v1.4h
+; CHECK-FP16-NEXT:  ret
   %0 = fmul <4 x half> %a, %b
   ret <4 x half> %0
 }
@@ -47,11 +60,15 @@ entry:
 
 define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) {
 entry:
-; CHECK-LABEL: div_h:
-; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
-; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
-; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
-; CHECK: fcvtn v0.4h, [[RES]]
+; CHECK-CVT-LABEL: div_h:
+; CHECK-CVT-DAG:   fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
+; CHECK-CVT-DAG:   fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
+; CHECK-CVT-NEXT:  fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
+; CHECK-CVT-NEXT:  fcvtn v0.4h, [[RES]]
+
+; CHECK-FP16-LABEL: div_h:
+; CHECK-FP16:       fdiv  v0.4h, v0.4h, v1.4h
+; CHECK-FP16-NEXT:  ret
   %0 = fdiv <4 x half> %a, %b
   ret <4 x half> %0
 }
@@ -59,8 +76,9 @@ entry:
 
 define <4 x half> @load_h(<4 x half>* %a) {
 entry:
-; CHECK-LABEL: load_h:
-; CHECK: ldr d0, [x0]
+; CHECK-COMMON-LABEL: load_h:
+; CHECK-COMMON:       ldr d0, [x0]
+; CHECK-COMMON-NEXT:  ret
   %0 = load <4 x half>, <4 x half>* %a, align 4
   ret <4 x half> %0
 }
@@ -68,476 +86,637 @@ entry:
 
 define void @store_h(<4 x half>* %a, <4 x half> %b) {
 entry:
-; CHECK-LABEL: store_h:
-; CHECK: str d0, [x0]
+; CHECK-COMMON-LABEL: store_h:
+; CHECK-COMMON:       str d0, [x0]
+; CHECK-COMMON-NEXT:  ret
   store <4 x half> %b, <4 x half>* %a, align 4
   ret void
 }
 
 define <4 x half> @s_to_h(<4 x float> %a) {
-; CHECK-LABEL: s_to_h:
-; CHECK: fcvtn v0.4h, v0.4s
+; CHECK-COMMON-LABEL: s_to_h:
+; CHECK-COMMON:       fcvtn v0.4h, v0.4s
+; CHECK-COMMON-NEXT:  ret
   %1 = fptrunc <4 x float> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @d_to_h(<4 x double> %a) {
 ; CHECK-LABEL: d_to_h:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: ins
-; CHECK-DAG: ins
-; CHECK-DAG: ins
-; CHECK-DAG: ins
+; CHECK-DAG: fcvt h
+; CHECK-DAG: fcvt h
+; CHECK-DAG: fcvt h
+; CHECK-DAG: fcvt h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
   %1 = fptrunc <4 x double> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x float> @h_to_s(<4 x half> %a) {
-; CHECK-LABEL: h_to_s:
-; CHECK: fcvtl v0.4s, v0.4h
+; CHECK-COMMON-LABEL: h_to_s:
+; CHECK-COMMON:       fcvtl v0.4s, v0.4h
+; CHECK-COMMON-NEXT:  ret
   %1 = fpext <4 x half> %a to <4 x float>
   ret <4 x float> %1
 }
 
 define <4 x double> @h_to_d(<4 x half> %a) {
 ; CHECK-LABEL: h_to_d:
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
-; CHECK-DAG: ins
-; CHECK-DAG: ins
-; CHECK-DAG: ins
-; CHECK-DAG: ins
   %1 = fpext <4 x half> %a to <4 x double>
   ret <4 x double> %1
 }
 
 define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
-; CHECK-LABEL: bitcast_i_to_h:
-; CHECK: mov v0.16b, v1.16b
+; CHECK-COMMON-LABEL: bitcast_i_to_h:
+; CHECK-COMMON:       mov v0.16b, v1.16b
+; CHECK-COMMON-NEXT:  ret
   %2 = bitcast <4 x i16> %a to <4 x half>
   ret <4 x half> %2
 }
 
 define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
-; CHECK-LABEL: bitcast_h_to_i:
-; CHECK: mov v0.16b, v1.16b
+; CHECK-COMMON-LABEL: bitcast_h_to_i:
+; CHECK-COMMON:       mov v0.16b, v1.16b
+; CHECK-COMMON-NEXT:  ret
   %2 = bitcast <4 x half> %a to <4 x i16>
   ret <4 x i16> %2
 }
 
 define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
-; CHECK-LABEL: sitofp_i8:
-; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
-; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
-; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
-; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
-; CHECK-NEXT: fcvtn v0.4h, [[OP4]]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: sitofp_i8:
+; CHECK-COMMON-NEXT:  shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
+; CHECK-COMMON-NEXT:  sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
+; CHECK-COMMON-NEXT:  sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
+; CHECK-COMMON-NEXT:  scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
+; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP4]]
+; CHECK-COMMON-NEXT:  ret
   %1 = sitofp <4 x i8> %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
-; CHECK-LABEL: sitofp_i16:
-; CHECK-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
-; CHECK-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
-; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: sitofp_i16:
+; CHECK-COMMON-NEXT:  sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
+; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
+; CHECK-COMMON-NEXT:  ret
   %1 = sitofp <4 x i16> %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {
-; CHECK-LABEL: sitofp_i32:
-; CHECK-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
-; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
+; CHECK-COMMON-LABEL: sitofp_i32:
+; CHECK-COMMON-NEXT:  scvtf [[OP1:v[0-9]+\.4s]], v0.4s
+; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP1]]
+; CHECK-COMMON-NEXT:  ret
   %1 = sitofp <4 x i32> %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {
-; CHECK-LABEL: sitofp_i64:
-; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
-; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
-; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
-; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
-; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
+; CHECK-COMMON-LABEL: sitofp_i64:
+; CHECK-COMMON-DAG:   scvtf [[OP1:v[0-9]+\.2d]], v0.2d
+; CHECK-COMMON-DAG:   scvtf [[OP2:v[0-9]+\.2d]], v1.2d
+; CHECK-COMMON-DAG:   fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
+; CHECK-COMMON-NEXT:  fcvtn2 [[OP3]].4s, [[OP2]]
+; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP3]].4s
+; CHECK-COMMON-NEXT:  ret
   %1 = sitofp <4 x i64> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
-; CHECK-LABEL: uitofp_i8:
-; CHECK-NEXT: bic v0.4h, #255, lsl #8
-; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
-; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
-; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: uitofp_i8:
+; CHECK-COMMON-NEXT:  bic v0.4h, #255, lsl #8
+; CHECK-COMMON-NEXT:  ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
+; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
+; CHECK-COMMON-NEXT:  ret
   %1 = uitofp <4 x i8> %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
-; CHECK-LABEL: uitofp_i16:
-; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
-; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
-; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: uitofp_i16:
+; CHECK-COMMON-NEXT:  ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
+; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
+; CHECK-COMMON-NEXT:  ret
   %1 = uitofp <4 x i16> %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {
-; CHECK-LABEL: uitofp_i32:
-; CHECK-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
-; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
+; CHECK-COMMON-LABEL: uitofp_i32:
+; CHECK-COMMON-NEXT:  ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
+; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP1]]
+; CHECK-COMMON-NEXT:  ret
   %1 = uitofp <4 x i32> %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
-; CHECK-LABEL: uitofp_i64:
-; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
-; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
-; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
-; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
-; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
+; CHECK-COMMON-LABEL: uitofp_i64:
+; CHECK-COMMON-DAG:   ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
+; CHECK-COMMON-DAG:   ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
+; CHECK-COMMON-DAG:   fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
+; CHECK-COMMON-NEXT:  fcvtn2 [[OP3]].4s, [[OP2]]
+; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP3]].4s
+; CHECK-COMMON-NEXT:  ret
   %1 = uitofp <4 x i64> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define void @test_insert_at_zero(half %a, <4 x half>* %b) #0 {
-; CHECK-LABEL: test_insert_at_zero:
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: test_insert_at_zero:
+; CHECK-COMMON-NEXT:  str d0, [x0]
+; CHECK-COMMON-NEXT:  ret
   %1 = insertelement <4 x half> undef, half %a, i64 0
   store <4 x half> %1, <4 x half>* %b, align 4
   ret void
 }
 
 define <4 x i8> @fptosi_i8(<4 x half> %a) #0 {
-; CHECK-LABEL: fptosi_i8:
-; CHECK-NEXT: fcvtl  [[REG1:v[0-9]+\.4s]], v0.4h
-; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
-; CHECK-NEXT: xtn    v0.4h, [[REG2]]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: fptosi_i8:
+; CHECK-COMMON-NEXT:  fcvtl  [[REG1:v[0-9]+\.4s]], v0.4h
+; CHECK-COMMON-NEXT:  fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
+; CHECK-COMMON-NEXT:  xtn    v0.4h, [[REG2]]
+; CHECK-COMMON-NEXT:  ret
   %1 = fptosi<4 x half> %a to <4 x i8>
   ret <4 x i8> %1
 }
 
 define <4 x i16> @fptosi_i16(<4 x half> %a) #0 {
-; CHECK-LABEL: fptosi_i16:
-; CHECK-NEXT: fcvtl  [[REG1:v[0-9]+\.4s]], v0.4h
-; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
-; CHECK-NEXT: xtn    v0.4h, [[REG2]]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: fptosi_i16:
+; CHECK-COMMON-NEXT:  fcvtl  [[REG1:v[0-9]+\.4s]], v0.4h
+; CHECK-COMMON-NEXT:  fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
+; CHECK-COMMON-NEXT:  xtn    v0.4h, [[REG2]]
+; CHECK-COMMON-NEXT:  ret
   %1 = fptosi<4 x half> %a to <4 x i16>
   ret <4 x i16> %1
 }
 
 define <4 x i8> @fptoui_i8(<4 x half> %a) #0 {
-; CHECK-LABEL: fptoui_i8:
-; CHECK-NEXT: fcvtl  [[REG1:v[0-9]+\.4s]], v0.4h
+; CHECK-COMMON-LABEL: fptoui_i8:
+; CHECK-COMMON-NEXT:  fcvtl  [[REG1:v[0-9]+\.4s]], v0.4h
 ; NOTE: fcvtzs selected here because the xtn shaves the sign bit
-; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
-; CHECK-NEXT: xtn    v0.4h, [[REG2]]
-; CHECK-NEXT: ret
+; CHECK-COMMON-NEXT:  fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
+; CHECK-COMMON-NEXT:  xtn    v0.4h, [[REG2]]
+; CHECK-COMMON-NEXT:  ret
   %1 = fptoui<4 x half> %a to <4 x i8>
   ret <4 x i8> %1
 }
 
 define <4 x i16> @fptoui_i16(<4 x half> %a) #0 {
-; CHECK-LABEL: fptoui_i16:
-; CHECK-NEXT: fcvtl  [[REG1:v[0-9]+\.4s]], v0.4h
-; CHECK-NEXT: fcvtzu [[REG2:v[0-9]+\.4s]], [[REG1]]
-; CHECK-NEXT: xtn    v0.4h, [[REG2]]
-; CHECK-NEXT: ret
+; CHECK-COMMON-LABEL: fptoui_i16:
+; CHECK-COMMON-NEXT:  fcvtl  [[REG1:v[0-9]+\.4s]], v0.4h
+; CHECK-COMMON-NEXT:  fcvtzu [[REG2:v[0-9]+\.4s]], [[REG1]]
+; CHECK-COMMON-NEXT:  xtn    v0.4h, [[REG2]]
+; CHECK-COMMON-NEXT:  ret
   %1 = fptoui<4 x half> %a to <4 x i16>
   ret <4 x i16> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_une:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, ne
-; CHECK-DAG: csetm {{.*}}, ne
-; CHECK-DAG: csetm {{.*}}, ne
-; CHECK-DAG: csetm {{.*}}, ne
 define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_une:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, ne
+; CHECK-CVT-DAG: csetm {{.*}}, ne
+; CHECK-CVT-DAG: csetm {{.*}}, ne
+; CHECK-CVT-DAG: csetm {{.*}}, ne
+
+; CHECK-FP16-LABEL: test_fcmp_une:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ne
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ne
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ne
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ne
+; CHECK-FP16:       ret
   %1 = fcmp une <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_ueq:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm [[REG1:w[0-9]+]], eq
-; CHECK-DAG: csetm [[REG2:w[0-9]+]], eq
-; CHECK-DAG: csetm [[REG3:w[0-9]+]], eq
-; CHECK-DAG: csetm [[REG4:w[0-9]+]], eq
-; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, vc
-; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, vc
-; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, vc
-; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, vc
 define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_ueq:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm [[REG1:w[0-9]+]], eq
+; CHECK-CVT-DAG: csetm [[REG2:w[0-9]+]], eq
+; CHECK-CVT-DAG: csetm [[REG3:w[0-9]+]], eq
+; CHECK-CVT-DAG: csetm [[REG4:w[0-9]+]], eq
+; CHECK-CVT-DAG: csinv {{.*}}, [[REG1]], wzr, vc
+; CHECK-CVT-DAG: csinv {{.*}}, [[REG2]], wzr, vc
+; CHECK-CVT-DAG: csinv {{.*}}, [[REG3]], wzr, vc
+; CHECK-CVT-DAG: csinv {{.*}}, [[REG4]], wzr, vc
+
+; CHECK-FP16-LABEL: test_fcmp_ueq:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, eq
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, eq
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, eq
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, eq
+; CHECK-FP16:       ret
   %1 = fcmp ueq <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_ugt:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, hi
-; CHECK-DAG: csetm {{.*}}, hi
-; CHECK-DAG: csetm {{.*}}, hi
-; CHECK-DAG: csetm {{.*}}, hi
 define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_ugt:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, hi
+; CHECK-CVT-DAG: csetm {{.*}}, hi
+; CHECK-CVT-DAG: csetm {{.*}}, hi
+; CHECK-CVT-DAG: csetm {{.*}}, hi
+
+; CHECK-FP16-LABEL: test_fcmp_ugt:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, hi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, hi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, hi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, hi
+; CHECK-FP16:       ret
   %1 = fcmp ugt <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_uge:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, pl
-; CHECK-DAG: csetm {{.*}}, pl
-; CHECK-DAG: csetm {{.*}}, pl
-; CHECK-DAG: csetm {{.*}}, pl
 define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_uge:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, pl
+; CHECK-CVT-DAG: csetm {{.*}}, pl
+; CHECK-CVT-DAG: csetm {{.*}}, pl
+; CHECK-CVT-DAG: csetm {{.*}}, pl
+
+; CHECK-FP16-LABEL: test_fcmp_uge:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, pl
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, pl
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, pl
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, pl
+; CHECK-FP16:       ret
   %1 = fcmp uge <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_ult:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, lt
-; CHECK-DAG: csetm {{.*}}, lt
-; CHECK-DAG: csetm {{.*}}, lt
-; CHECK-DAG: csetm {{.*}}, lt
 define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_ult:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, lt
+; CHECK-CVT-DAG: csetm {{.*}}, lt
+; CHECK-CVT-DAG: csetm {{.*}}, lt
+; CHECK-CVT-DAG: csetm {{.*}}, lt
+
+; CHECK-FP16-LABEL: test_fcmp_ult:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, lt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, lt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, lt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, lt
+; CHECK-FP16:       ret
   %1 = fcmp ult <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_ule:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, le
-; CHECK-DAG: csetm {{.*}}, le
-; CHECK-DAG: csetm {{.*}}, le
-; CHECK-DAG: csetm {{.*}}, le
 define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_ule:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, le
+; CHECK-CVT-DAG: csetm {{.*}}, le
+; CHECK-CVT-DAG: csetm {{.*}}, le
+; CHECK-CVT-DAG: csetm {{.*}}, le
+
+; CHECK-FP16-LABEL: test_fcmp_ule:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, le
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, le
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, le
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, le
+; CHECK-FP16:       ret
   %1 = fcmp ule <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_uno:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, vs
-; CHECK-DAG: csetm {{.*}}, vs
-; CHECK-DAG: csetm {{.*}}, vs
-; CHECK-DAG: csetm {{.*}}, vs
 define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_uno:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, vs
+; CHECK-CVT-DAG: csetm {{.*}}, vs
+; CHECK-CVT-DAG: csetm {{.*}}, vs
+; CHECK-CVT-DAG: csetm {{.*}}, vs
+
+; CHECK-FP16-LABEL: test_fcmp_uno:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, vs
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, vs
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, vs
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, vs
+; CHECK-FP16:       ret
   %1 = fcmp uno <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_one:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm [[REG1:w[0-9]+]], mi
-; CHECK-DAG: csetm [[REG2:w[0-9]+]], mi
-; CHECK-DAG: csetm [[REG3:w[0-9]+]], mi
-; CHECK-DAG: csetm [[REG4:w[0-9]+]], mi
-; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, le
-; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, le
-; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, le
-; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, le
-
 define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_one:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm [[REG1:w[0-9]+]], mi
+; CHECK-CVT-DAG: csetm [[REG2:w[0-9]+]], mi
+; CHECK-CVT-DAG: csetm [[REG3:w[0-9]+]], mi
+; CHECK-CVT-DAG: csetm [[REG4:w[0-9]+]], mi
+; CHECK-CVT-DAG: csinv {{.*}}, [[REG1]], wzr, le
+; CHECK-CVT-DAG: csinv {{.*}}, [[REG2]], wzr, le
+; CHECK-CVT-DAG: csinv {{.*}}, [[REG3]], wzr, le
+; CHECK-CVT-DAG: csinv {{.*}}, [[REG4]], wzr, le
+
+; CHECK-FP16-LABEL: test_fcmp_one:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, mi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, mi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, mi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, mi
+; CHECK-FP16:       ret
   %1 = fcmp one <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_oeq:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, eq
-; CHECK-DAG: csetm {{.*}}, eq
-; CHECK-DAG: csetm {{.*}}, eq
-; CHECK-DAG: csetm {{.*}}, eq
 define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_oeq:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, eq
+; CHECK-CVT-DAG: csetm {{.*}}, eq
+; CHECK-CVT-DAG: csetm {{.*}}, eq
+; CHECK-CVT-DAG: csetm {{.*}}, eq
+
+; CHECK-FP16-LABEL: test_fcmp_oeq:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, eq
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, eq
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, eq
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, eq
+; CHECK-FP16:       ret
   %1 = fcmp oeq <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_ogt:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, gt
-; CHECK-DAG: csetm {{.*}}, gt
-; CHECK-DAG: csetm {{.*}}, gt
-; CHECK-DAG: csetm {{.*}}, gt
 define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_ogt:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, gt
+; CHECK-CVT-DAG: csetm {{.*}}, gt
+; CHECK-CVT-DAG: csetm {{.*}}, gt
+; CHECK-CVT-DAG: csetm {{.*}}, gt
+
+; CHECK-FP16-LABEL: test_fcmp_ogt:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, gt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, gt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, gt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, gt
+; CHECK-FP16:       ret
   %1 = fcmp ogt <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_oge:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, ge
-; CHECK-DAG: csetm {{.*}}, ge
-; CHECK-DAG: csetm {{.*}}, ge
-; CHECK-DAG: csetm {{.*}}, ge
 define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_oge:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, ge
+; CHECK-CVT-DAG: csetm {{.*}}, ge
+; CHECK-CVT-DAG: csetm {{.*}}, ge
+; CHECK-CVT-DAG: csetm {{.*}}, ge
+
+; CHECK-FP16-LABEL: test_fcmp_oge:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ge
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ge
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ge
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ge
+; CHECK-FP16:       ret
   %1 = fcmp oge <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_olt:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, mi
-; CHECK-DAG: csetm {{.*}}, mi
-; CHECK-DAG: csetm {{.*}}, mi
-; CHECK-DAG: csetm {{.*}}, mi
 define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_olt:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, mi
+; CHECK-CVT-DAG: csetm {{.*}}, mi
+; CHECK-CVT-DAG: csetm {{.*}}, mi
+; CHECK-CVT-DAG: csetm {{.*}}, mi
+
+; CHECK-FP16-LABEL: test_fcmp_olt:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, mi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, mi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, mi
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, mi
+; CHECK-FP16:       ret
   %1 = fcmp olt <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_ole:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, ls
-; CHECK-DAG: csetm {{.*}}, ls
-; CHECK-DAG: csetm {{.*}}, ls
-; CHECK-DAG: csetm {{.*}}, ls
 define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_ole:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, ls
+; CHECK-CVT-DAG: csetm {{.*}}, ls
+; CHECK-CVT-DAG: csetm {{.*}}, ls
+; CHECK-CVT-DAG: csetm {{.*}}, ls
+
+; CHECK-FP16-LABEL: test_fcmp_ole:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ls
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ls
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ls
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, ls
+; CHECK-FP16:       ret
   %1 = fcmp ole <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
-; Function Attrs: nounwind readnone
-; CHECK-LABEL: test_fcmp_ord:
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: csetm {{.*}}, vc
-; CHECK-DAG: csetm {{.*}}, vc
-; CHECK-DAG: csetm {{.*}}, vc
-; CHECK-DAG: csetm {{.*}}, vc
 define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {
+; CHECK-CVT-LABEL: test_fcmp_ord:
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: csetm {{.*}}, vc
+; CHECK-CVT-DAG: csetm {{.*}}, vc
+; CHECK-CVT-DAG: csetm {{.*}}, vc
+; CHECK-CVT-DAG: csetm {{.*}}, vc
+
+; CHECK-FP16-LABEL: test_fcmp_ord:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, vc
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, vc
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, vc
+; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
+; CHECK-FP16:       csetm {{.*}}, vc
+; CHECK-FP16:       ret
   %1 = fcmp ord <4 x half> %a, %b
   ret <4 x i1> %1
 }
diff --git a/test/CodeGen/AArch64/fp16-v8-instructions.ll b/test/CodeGen/AArch64/fp16-v8-instructions.ll
index 2f70f3635d19..5215260c23a2 100644
--- a/test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ b/test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -1,40 +1,46 @@
-; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-CVT   --check-prefix=CHECK
+; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK-FP16  --check-prefix=CHECK
 
 define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) {
 entry:
-; CHECK-LABEL: add_h:
-; CHECK: fcvt
-; CHECK: fcvt
-; CHECK-DAG: fadd
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fadd
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fadd
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fadd
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fadd
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fadd
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fadd
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fadd
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK: fcvt
+; CHECK-CVT-LABEL: add_h:
+; CHECK-CVT:     fcvt
+; CHECK-CVT:     fcvt
+; CHECK-CVT-DAG: fadd
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fadd
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fadd
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fadd
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fadd
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fadd
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fadd
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fadd
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT-DAG: fcvt
+; CHECK-CVT:     fcvt
+
+; CHECK-FP16-LABEL: add_h:
+; CHECK-FP16:       fadd  v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT:  ret
+
   %0 = fadd <8 x half> %a, %b
   ret <8 x half> %0
 }
@@ -42,39 +48,44 @@ entry:
 
 define <8 x half> @sub_h(<8 x half> %a, <8 x half> %b) {
 entry:
-; CHECK-LABEL: sub_h:
-; CHECK: fcvt
-; CHECK: fcvt
-; CHECK-DAG: fsub
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fsub
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fsub
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fsub
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fsub
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fsub
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fsub
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fsub
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK: fcvt
+; CHECK-CVT-LABEL: sub_h:
+; CHECK-CVT:       fcvt
+; CHECK-CVT:       fcvt
+; CHECK-CVT-DAG:   fsub
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fsub
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fsub
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fsub
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fsub
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fsub
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fsub
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fsub
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT:       fcvt
+
+; CHECK-FP16-LABEL: sub_h:
+; CHECK-FP16:       fsub  v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT:  ret
+
   %0 = fsub <8 x half> %a, %b
   ret <8 x half> %0
 }
@@ -82,39 +93,44 @@ entry:
 
 define <8 x half> @mul_h(<8 x half> %a, <8 x half> %b) {
 entry:
-; CHECK-LABEL: mul_h:
-; CHECK: fcvt
-; CHECK: fcvt
-; CHECK-DAG: fmul
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fmul
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fmul
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fmul
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fmul
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fmul
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fmul
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fmul
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK: fcvt
+; CHECK-CVT-LABEL: mul_h:
+; CHECK-CVT:       fcvt
+; CHECK-CVT:       fcvt
+; CHECK-CVT-DAG:   fmul
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fmul
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fmul
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fmul
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fmul
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fmul
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fmul
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fmul
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT:       fcvt
+
+; CHECK-FP16-LABEL: mul_h:
+; CHECK-FP16:       fmul  v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT:  ret
+
   %0 = fmul <8 x half> %a, %b
   ret <8 x half> %0
 }
@@ -122,39 +138,44 @@ entry:
 
 define <8 x half> @div_h(<8 x half> %a, <8 x half> %b) {
 entry:
-; CHECK-LABEL: div_h:
-; CHECK: fcvt
-; CHECK: fcvt
-; CHECK-DAG: fdiv
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fdiv
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fdiv
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fdiv
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fdiv
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fdiv
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fdiv
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fdiv
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK-DAG: fcvt
-; CHECK: fcvt
+; CHECK-CVT-LABEL: div_h:
+; CHECK-CVT:       fcvt
+; CHECK-CVT:       fcvt
+; CHECK-CVT-DAG:   fdiv
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fdiv
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fdiv
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fdiv
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fdiv
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fdiv
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fdiv
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fdiv
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT-DAG:   fcvt
+; CHECK-CVT:       fcvt
+
+; CHECK-FP16-LABEL: div_h:
+; CHECK-FP16:       fdiv  v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT:  ret
+
   %0 = fdiv <8 x half> %a, %b
   ret <8 x half> %0
 }
@@ -181,7 +202,7 @@ define <8 x half> @s_to_h(<8 x float> %a) {
 ; CHECK-LABEL: s_to_h:
 ; CHECK-DAG: fcvtn v0.4h, v0.4s
 ; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s
-; CHECK: ins v0.d[1], [[REG]].d[0]
+; CHECK: mov v0.d[1], [[REG]].d[0]
   %1 = fptrunc <8 x float> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -200,14 +221,14 @@ define <8 x half> @d_to_h(<8 x double> %a) {
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
   %1 = fptrunc <8 x double> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -222,6 +243,13 @@ define <8 x float> @h_to_s(<8 x half> %a) {
 
 define <8 x double> @h_to_d(<8 x half> %a) {
 ; CHECK-LABEL: h_to_d:
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
+; CHECK-DAG: mov h{{[0-9]+}}, v0.h
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
@@ -230,10 +258,6 @@ define <8 x double> @h_to_d(<8 x half> %a) {
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
-; CHECK-DAG: ins
-; CHECK-DAG: ins
-; CHECK-DAG: ins
-; CHECK-DAG: ins
   %1 = fpext <8 x half> %a to <8 x double>
   ret <8 x double> %1
 }
@@ -263,7 +287,7 @@ define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = sitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -277,7 +301,7 @@ define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = sitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -289,7 +313,7 @@ define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
-; CHECK: ins v0.d[1], v[[REG]].d[0]
+; CHECK: mov v0.d[1], v[[REG]].d[0]
   %1 = sitofp <8 x i32> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -315,7 +339,7 @@ define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = uitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -329,7 +353,7 @@ define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = uitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -341,7 +365,7 @@ define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {
 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
-; CHECK: ins v0.d[1], v[[REG]].d[0]
+; CHECK: mov v0.d[1], v[[REG]].d[0]
   %1 = uitofp <8 x i32> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -421,86 +445,254 @@ define <8 x i16> @fptoui_i16(<8 x half> %a) #0 {
   ret <8 x i16> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_une:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp une <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 16 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_ueq:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp ueq <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_ugt:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp ugt <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_uge:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp uge <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_ult:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp ult <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_ule:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp ule <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_uno:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp uno <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_one:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp one <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_oeq:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp oeq <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_ogt:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp ogt <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_oge:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp oge <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_olt:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp olt <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_ole:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp ole <8 x half> %a, %b
   ret <8 x i1> %1
 }
 
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests.  Skipped.
 define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 {
+; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
+
+; CHECK-FP16-LABEL: test_fcmp_ord:
+; CHECK-FP16-NOT:   fcvt
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG:   fcmp  h{{[0-9]}}, h{{[0-9]}}
+
   %1 = fcmp ord <8 x half> %a, %b
   ret <8 x i1> %1
 }
diff --git a/test/CodeGen/AArch64/fp16-vector-shuffle.ll b/test/CodeGen/AArch64/fp16-vector-shuffle.ll
index 74d1b436e126..1f67ff4e938a 100644
--- a/test/CodeGen/AArch64/fp16-vector-shuffle.ll
+++ b/test/CodeGen/AArch64/fp16-vector-shuffle.ll
@@ -35,7 +35,7 @@ entry:
 ; }
 define <4 x half> @lane_64_64(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-LABEL: lane_64_64:
-; CHECK: ins
+; CHECK: mov v{{[0-9]+}}.h
 entry:
   %0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
   ret <4 x half> %0
@@ -46,7 +46,7 @@ entry:
 ; }
 define <8 x half> @lane_128_64(<8 x half> %a, <4 x half> %b) #0 {
 ; CHECK-LABEL: lane_128_64:
-; CHECK: ins
+; CHECK: mov v{{[0-9]+}}.h
 entry:
   %0 = bitcast <4 x half> %b to <4 x i16>
   %vget_lane = extractelement <4 x i16> %0, i32 2
@@ -61,7 +61,7 @@ entry:
 ; }
 define <4 x half> @lane_64_128(<4 x half> %a, <8 x half> %b) #0 {
 ; CHECK-LABEL: lane_64_128:
-; CHECK: ins
+; CHECK: mov v{{[0-9]+}}.h
 entry:
   %0 = bitcast <8 x half> %b to <8 x i16>
   %vgetq_lane = extractelement <8 x i16> %0, i32 5
@@ -76,7 +76,7 @@ entry:
 ; }
 define <8 x half> @lane_128_128(<8 x half> %a, <8 x half> %b) #0 {
 ; CHECK-LABEL: lane_128_128:
-; CHECK: ins
+; CHECK: mov v{{[0-9]+}}.h
 entry:
   %0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>
   ret <8 x half> %0
@@ -225,7 +225,7 @@ entry:
 define <8 x half> @vcombine(<4 x half> %a, <4 x half> %b) #0 {
 entry:
 ; CHECK-LABEL: vcombine:
-; CHECK: ins
+; CHECK: mov v0.d[1], v1.d[0]
   %shuffle.i = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x half> %shuffle.i
 }
@@ -253,7 +253,7 @@ entry:
 define <4 x half> @set_lane_64(<4 x half> %a, half %b) #0 {
 ; CHECK-LABEL: set_lane_64:
 ; CHECK: fmov
-; CHECK: ins
+; CHECK: mov v{{[0-9]+}}.h
 entry:
   %0 = bitcast half %b to i16
   %1 = bitcast <4 x half> %a to <4 x i16>
@@ -267,7 +267,7 @@ entry:
 define <8 x half> @set_lane_128(<8 x half> %a, half %b) #0 {
 ; CHECK-LABEL: set_lane_128:
 ; CHECK: fmov
-; CHECK: ins
+; CHECK: mov v{{[0-9]+}}.h
 entry:
   %0 = bitcast half %b to i16
   %1 = bitcast <8 x half> %a to <8 x i16>
diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll
index 40ed607b06cc..54d38a91c387 100644
--- a/test/CodeGen/AArch64/func-calls.ll
+++ b/test/CodeGen/AArch64/func-calls.ll
@@ -130,11 +130,11 @@ define void @check_i128_align() {
                                    i32 42, i128 %val)
 ; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
 ; CHECK: ldp [[I128LO:x[0-9]+]], [[I128HI:x[0-9]+]], [x[[VAR128]]]
-; CHECK: stp [[I128LO]], [[I128HI]], [sp, #16]
+; CHECK: stp [[I128HI]], {{x[0-9]+}}, [sp, #24]
 
 ; CHECK-NONEON: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
 ; CHECK-NONEON: ldp [[I128LO:x[0-9]+]], [[I128HI:x[0-9]+]], [x[[VAR128]]]
-; CHECK-NONEON: stp [[I128LO]], [[I128HI]], [sp, #16]
+; CHECK-NONEON: stp [[I128HI]], {{x[0-9]+}}, [sp, #24]
 ; CHECK: bl check_i128_stackalign
 
   call void @check_i128_regalign(i32 0, i128 42)
diff --git a/test/CodeGen/AArch64/ldst-opt.ll b/test/CodeGen/AArch64/ldst-opt.ll
index 2b98d3215e49..e416dcb0f16a 100644
--- a/test/CodeGen/AArch64/ldst-opt.ll
+++ b/test/CodeGen/AArch64/ldst-opt.ll
@@ -1531,7 +1531,7 @@ define void @merge_zr64_unalign(<2 x i64>* %p) {
 ; CHECK-LABEL: merge_zr64_unalign:
 ; CHECK: // %entry
 ; NOSTRICTALIGN-NEXT: stp xzr, xzr, [x{{[0-9]+}}]
-; STRICTALIGN: strb wzr,
+; STRICTALIGN: strb
 ; STRICTALIGN: strb
 ; STRICTALIGN: strb
 ; STRICTALIGN: strb
diff --git a/test/CodeGen/AArch64/local_vars.ll b/test/CodeGen/AArch64/local_vars.ll
index 6e33ab2d0beb..a479572d2a31 100644
--- a/test/CodeGen/AArch64/local_vars.ll
+++ b/test/CodeGen/AArch64/local_vars.ll
@@ -17,7 +17,7 @@ declare void @foo()
 
 define void @trivial_func() nounwind {
 ; CHECK-LABEL: trivial_func: // @trivial_func
-; CHECK-NEXT: // BB#0
+; CHECK-NEXT: // %bb.0
 ; CHECK-NEXT: ret
 
   ret void
diff --git a/test/CodeGen/AArch64/loh.mir b/test/CodeGen/AArch64/loh.mir
index 6e4bb5cfaee6..ee62c339cf08 100644
--- a/test/CodeGen/AArch64/loh.mir
+++ b/test/CodeGen/AArch64/loh.mir
@@ -22,14 +22,14 @@ tracksRegLiveness: true
 body: |
   bb.0:
     ; CHECK: Adding MCLOH_AdrpAdrp:
-    ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
-    ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g4
     ; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
-    ; CHECK-NEXT: %X1<def> = ADRP <ga:@g2>
-    ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g2
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
     ; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
-    ; CHECK-NEXT: %X0<def> = ADRP <ga:@g0>
-    ; CHECK-NEXT: %X0<def> = ADRP <ga:@g1>
+    ; CHECK-NEXT: %x0 = ADRP target-flags(aarch64-page) @g0
+    ; CHECK-NEXT: %x0 = ADRP target-flags(aarch64-page) @g1
     %x0 = ADRP target-flags(aarch64-page) @g0
     %x0 = ADRP target-flags(aarch64-page) @g1
     %x1 = ADRP target-flags(aarch64-page) @g2
@@ -38,11 +38,11 @@ body: |
 
   bb.1:
     ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
-    ; CHECK-NEXT: %X20<def> = ADRP <ga:@g0>
-    ; CHECK-NEXT: %X3<def> = ADDXri %X20, <ga:@g0>
+    ; CHECK-NEXT: %x20 = ADRP target-flags(aarch64-page) @g0
+    ; CHECK-NEXT: %x3 = ADDXri %x20, target-flags(aarch64-pageoff) @g0
     ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
-    ; CHECK-NEXT: %X1<def> = ADRP <ga:@g0>
-    ; CHECK-NEXT: %X1<def> = ADDXri %X1, <ga:@g0>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g0
+    ; CHECK-NEXT: %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0
     %x1 = ADRP target-flags(aarch64-page) @g0
     %x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation
     %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0
@@ -73,11 +73,11 @@ body: |
 
   bb.5:
     ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
-    ; CHECK-NEXT: %X5<def> = ADRP <ga:@g2>
-    ; CHECK-NEXT: %S6<def> = LDRSui %X5, <ga:@g2>
+    ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g2
+    ; CHECK-NEXT: %s6 = LDRSui %x5, target-flags(aarch64-pageoff) @g2
     ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
-    ; CHECK-NEXT: %X4<def> = ADRP <ga:@g2>
-    ; CHECK-NEXT: %X4<def> = LDRXui %X4, <ga:@g2>
+    ; CHECK-NEXT: %x4 = ADRP target-flags(aarch64-page) @g2
+    ; CHECK-NEXT: %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
     %x4 = ADRP target-flags(aarch64-page) @g2
     %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
     %x5 = ADRP target-flags(aarch64-page) @g2
@@ -85,11 +85,11 @@ body: |
 
   bb.6:
     ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
-    ; CHECK-NEXT: %X5<def> = ADRP <ga:@g2>
-    ; CHECK-NEXT: %X6<def> = LDRXui %X5, <ga:@g2>
+    ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
+    ; CHECK-NEXT: %x6 = LDRXui %x5, target-flags(aarch64-pageoff, aarch64-got) @g2
     ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
-    ; CHECK-NEXT: %X4<def> = ADRP <ga:@g2>
-    ; CHECK-NEXT: %X4<def> = LDRXui %X4, <ga:@g2>
+    ; CHECK-NEXT: %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
+    ; CHECK-NEXT: %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
     %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
     %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
     %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
@@ -104,24 +104,24 @@ body: |
 
   bb.8:
     ; CHECK-NEXT: Adding MCLOH_AdrpAddLdr:
-    ; CHECK-NEXT: %X7<def> = ADRP <ga:@g3>[TF=1]
-    ; CHECK-NEXT: %X8<def> = ADDXri %X7, <ga:@g3>
-    ; CHECK-NEXT: %D1<def> = LDRDui %X8, 8
+    ; CHECK-NEXT: %x7 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3
+    ; CHECK-NEXT: %d1 = LDRDui %x8, 8
     %x7 = ADRP target-flags(aarch64-page) @g3
     %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0
     %d1 = LDRDui %x8, 8
 
   bb.9:
     ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
-    ; CHECK-NEXT: %X3<def> = ADRP <ga:@g3>
-    ; CHECK-NEXT: %X3<def> = ADDXri %X3, <ga:@g3>
+    ; CHECK-NEXT: %x3 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x3 = ADDXri %x3, target-flags(aarch64-pageoff) @g3
     ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
-    ; CHECK-NEXT: %X5<def> = ADRP <ga:@g3>
-    ; CHECK-NEXT: %X2<def> = ADDXri %X5, <ga:@g3>
+    ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x2 = ADDXri %x5, target-flags(aarch64-pageoff) @g3
     ; CHECK-NEXT: Adding MCLOH_AdrpAddStr:
-    ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
-    ; CHECK-NEXT: %X1<def> = ADDXri %X1, <ga:@g3>
-    ; CHECK-NEXT: STRXui %XZR, %X1, 16
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3
+    ; CHECK-NEXT: STRXui %xzr, %x1, 16
     %x1 = ADRP target-flags(aarch64-page) @g3
     %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0
     STRXui %xzr, %x1, 16
@@ -138,12 +138,12 @@ body: |
 
   bb.10:
     ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
-    ; CHECK-NEXT: %X2<def> = ADRP <ga:@g3>
-    ; CHECK-NEXT: %X2<def> = LDRXui %X2, <ga:@g3>
+    ; CHECK-NEXT: %x2 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x2 = LDRXui %x2, target-flags(aarch64-pageoff) @g3
     ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr:
-    ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
-    ; CHECK-NEXT: %X1<def> = LDRXui %X1, <ga:@g4>
-    ; CHECK-NEXT: %X1<def> = LDRXui %X1, 24
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
+    ; CHECK-NEXT: %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
+    ; CHECK-NEXT: %x1 = LDRXui %x1, 24
     %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
     %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
     %x1 = LDRXui %x1, 24
@@ -154,12 +154,12 @@ body: |
 
   bb.11:
     ; CHECK-NEXT: Adding MCLOH_AdrpLdr
-    ; CHECK-NEXT: %X5<def> = ADRP <ga:@g1>
-    ; CHECK-NEXT: %X5<def> = LDRXui %X5, <ga:@g1>
+    ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g1
+    ; CHECK-NEXT: %x5 = LDRXui %x5, target-flags(aarch64-pageoff) @g1
     ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr:
-    ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
-    ; CHECK-NEXT: %X1<def> = LDRXui %X1, <ga:@g4>
-    ; CHECK-NEXT: STRXui %XZR, %X1, 32
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
+    ; CHECK-NEXT: %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
+    ; CHECK-NEXT: STRXui %xzr, %x1, 32
     %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
     %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
     STRXui %xzr, %x1, 32
@@ -171,9 +171,9 @@ body: |
   bb.12:
     ; CHECK-NOT: MCLOH_AdrpAdrp
     ; CHECK: Adding MCLOH_AdrpAddLdr
-    ; %X9<def> = ADRP <ga:@g4>
-    ; %X9<def> = ADDXri %X9, <ga:@g4>
-    ; %X5<def> = LDRXui %X9, 0
+    ; %x9 = ADRP @g4
+    ; %x9 = ADDXri %x9, @g4
+    ; %x5 = LDRXui %x9, 0
     %x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
     %x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0
     %x5 = LDRXui %x9, 0
diff --git a/test/CodeGen/AArch64/loop-micro-op-buffer-size-t99.ll b/test/CodeGen/AArch64/loop-micro-op-buffer-size-t99.ll
new file mode 100644
index 000000000000..d64b51509e16
--- /dev/null
+++ b/test/CodeGen/AArch64/loop-micro-op-buffer-size-t99.ll
@@ -0,0 +1,124 @@
+; REQUIRES: asserts
+; RUN: opt -mcpu=thunderx2t99 -loop-unroll --debug-only=loop-unroll -S -unroll-allow-partial < %s 2>&1 | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; CHECK: Loop Unroll: F[foo] Loop %loop.2.header
+; CHECK: Loop Size = 19
+; CHECK: Trip Count = 512
+; CHECK: Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.2.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: Loop Unroll: F[foo] Loop %loop.header
+; CHECK:   Loop Size = 18
+; CHECK:   Trip Count = 512
+; CHECK:   Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: %counter = phi i32 [ 0, %entry ], [ %inc.3, %loop.inc.3 ]
+; CHECK: %val = add nuw nsw i32 %counter, 5
+; CHECK: %val1 = add nuw nsw i32 %counter, 6
+; CHECK: %val2 = add nuw nsw i32 %counter, 7
+; CHECK: %val3 = add nuw nsw i32 %counter, 8
+; CHECK: %val4 = add nuw nsw i32 %counter, 9
+; CHECK: %val5 = add nuw nsw i32 %counter, 10
+; CHECK-NOT: %val = add i32 %counter, 5
+; CHECK-NOT: %val = add i32 %counter, 6
+; CHECK-NOT: %val = add i32 %counter, 7
+; CHECK-NOT: %val = add i32 %counter, 8
+; CHECK-NOT: %val = add i32 %counter, 9
+; CHECK-NOT: %val = add i32 %counter, 10
+; CHECK: %counter.2 = phi i32 [ 0, %exit.0 ], [ %inc.2.3, %loop.2.inc.3 ]
+
+define void @foo(i32 * %out) {
+entry:
+  %0 = alloca [1024 x i32]
+  %x0 = alloca [1024 x i32]
+  %x01 = alloca [1024 x i32]
+  %x02 = alloca [1024 x i32]
+  %x03 = alloca [1024 x i32]
+  %x04 = alloca [1024 x i32]
+  %x05 = alloca [1024 x i32]
+  %x06 = alloca [1024 x i32]
+  br label %loop.header
+
+loop.header:
+  %counter = phi i32 [0, %entry], [%inc, %loop.inc]
+  br label %loop.body
+
+loop.body:
+  %ptr = getelementptr [1024 x i32], [1024 x i32]* %0, i32 0, i32 %counter
+  store i32 %counter, i32* %ptr
+  %val = add i32 %counter, 5
+  %xptr = getelementptr [1024 x i32], [1024 x i32]* %x0, i32 0, i32 %counter
+  store i32 %val, i32* %xptr
+  %val1 = add i32 %counter, 6
+  %xptr1 = getelementptr [1024 x i32], [1024 x i32]* %x01, i32 0, i32 %counter
+  store i32 %val1, i32* %xptr1
+  %val2 = add i32 %counter, 7
+  %xptr2 = getelementptr [1024 x i32], [1024 x i32]* %x02, i32 0, i32 %counter
+  store i32 %val2, i32* %xptr2
+  %val3 = add i32 %counter, 8
+  %xptr3 = getelementptr [1024 x i32], [1024 x i32]* %x03, i32 0, i32 %counter
+  store i32 %val3, i32* %xptr3
+  %val4 = add i32 %counter, 9
+  %xptr4 = getelementptr [1024 x i32], [1024 x i32]* %x04, i32 0, i32 %counter
+  store i32 %val4, i32* %xptr4
+  %val5 = add i32 %counter, 10
+  %xptr5 = getelementptr [1024 x i32], [1024 x i32]* %x05, i32 0, i32 %counter
+  store i32 %val5, i32* %xptr5
+  br label %loop.inc
+
+loop.inc:
+  %inc = add i32 %counter, 2
+  %1 = icmp sge i32 %inc, 1023
+  br i1 %1, label  %exit.0, label %loop.header
+
+exit.0:
+  %2 = getelementptr [1024 x i32], [1024 x i32]* %0, i32 0, i32 5
+  %3 = load i32, i32* %2
+  store i32 %3, i32 * %out
+  br label %loop.2.header
+
+
+loop.2.header:
+  %counter.2 = phi i32 [0, %exit.0], [%inc.2, %loop.2.inc]
+  br label %loop.2.body
+
+loop.2.body:
+  %ptr.2 = getelementptr [1024 x i32], [1024 x i32]* %0, i32 0, i32 %counter.2
+  store i32 %counter.2, i32* %ptr.2
+  %val.2 = add i32 %counter.2, 5
+  %xptr.2 = getelementptr [1024 x i32], [1024 x i32]* %x0, i32 0, i32 %counter.2
+  store i32 %val.2, i32* %xptr.2
+  %val1.2 = add i32 %counter.2, 6
+  %xptr1.2 = getelementptr [1024 x i32], [1024 x i32]* %x01, i32 0, i32 %counter.2
+  store i32 %val1, i32* %xptr1.2
+  %val2.2 = add i32 %counter.2, 7
+  %xptr2.2 = getelementptr [1024 x i32], [1024 x i32]* %x02, i32 0, i32 %counter.2
+  store i32 %val2, i32* %xptr2.2
+  %val3.2 = add i32 %counter.2, 8
+  %xptr3.2 = getelementptr [1024 x i32], [1024 x i32]* %x03, i32 0, i32 %counter.2
+  store i32 %val3.2, i32* %xptr3.2
+  %val4.2 = add i32 %counter.2, 9
+  %xptr4.2 = getelementptr [1024 x i32], [1024 x i32]* %x04, i32 0, i32 %counter.2
+  store i32 %val4.2, i32* %xptr4.2
+  %val5.2 = add i32 %counter.2, 10
+  %xptr5.2 = getelementptr [1024 x i32], [1024 x i32]* %x05, i32 0, i32 %counter.2
+  store i32 %val5.2, i32* %xptr5.2
+  %xptr6.2 = getelementptr [1024 x i32], [1024 x i32]* %x06, i32 0, i32 %counter.2
+  store i32 %val5.2, i32* %xptr6.2
+  br label %loop.2.inc
+
+loop.2.inc:
+  %inc.2 = add i32 %counter.2, 2
+  %4 = icmp sge i32 %inc.2, 1023
+  br i1 %4, label  %exit.2, label %loop.2.header
+
+exit.2:
+  %x2 = getelementptr [1024 x i32], [1024 x i32]* %0, i32 0, i32 6
+  %x3 = load i32, i32* %x2
+  %out2 = getelementptr i32, i32 * %out, i32 1
+  store i32 %3, i32 * %out2
+  ret void
+}
diff --git a/test/CodeGen/AArch64/loopvectorize_pr33804_double.ll b/test/CodeGen/AArch64/loopvectorize_pr33804_double.ll
new file mode 100644
index 000000000000..c18fc0cb803f
--- /dev/null
+++ b/test/CodeGen/AArch64/loopvectorize_pr33804_double.ll
@@ -0,0 +1,114 @@
+; RUN: opt -loop-vectorize -S < %s | FileCheck %s
+
+; These tests check that we don't crash if vectorizer decides to cast
+; a double value to be stored into a pointer type or vice-versa.
+
+; This test checks when a double value is stored into a pointer type.
+
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+source_filename = "bugpoint-output-26dbd81.bc"
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+%struct.CvNode1D = type { double, %struct.CvNode1D* }
+
+; CHECK-LABEL: @cvCalcEMD2
+; CHECK: vector.body
+; CHECK: store <{{[0-9]+}} x %struct.CvNode1D*>
+define void @cvCalcEMD2() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  br label %for.body14.i.i
+
+for.body14.i.i:                                   ; preds = %for.body14.i.i, %entry
+  %i.1424.i.i = phi i32 [ %inc21.i.i, %for.body14.i.i ], [ 0, %entry ]
+  %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* undef, i32 %i.1424.i.i
+  %val.i.i = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* %arrayidx15.i.i1427, i32 0, i32 0
+  store double 0xC415AF1D80000000, double* %val.i.i, align 4
+  %next19.i.i = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* undef, i32 %i.1424.i.i, i32 1
+  store %struct.CvNode1D* undef, %struct.CvNode1D** %next19.i.i, align 4
+  %inc21.i.i = add nuw nsw i32 %i.1424.i.i, 1
+  %exitcond438.i.i = icmp eq i32 %inc21.i.i, 0
+  br i1 %exitcond438.i.i, label %for.end22.i.i, label %for.body14.i.i
+
+for.end22.i.i:                                    ; preds = %for.body14.i.i
+  unreachable
+}
+
+; This test checks when a pointer value is stored into a double type.
+
+%struct.CvNode1D2 = type { %struct.CvNode1D2*, double }
+
+; CHECK-LABEL: @cvCalcEMD2_2
+; CHECK: vector.body
+; CHECK: store <{{[0-9]+}} x double>
+define void @cvCalcEMD2_2() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  br label %for.body14.i.i
+
+for.body14.i.i:                                   ; preds = %for.body14.i.i, %entry
+  %i.1424.i.i = phi i32 [ %inc21.i.i, %for.body14.i.i ], [ 0, %entry ]
+  %next19.i.i = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* undef, i32 %i.1424.i.i, i32 0
+  store %struct.CvNode1D2* undef, %struct.CvNode1D2** %next19.i.i, align 4
+  %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* undef, i32 %i.1424.i.i
+  %val.i.i = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* %arrayidx15.i.i1427, i32 0, i32 1
+  store double 0xC415AF1D80000000, double* %val.i.i, align 4
+  %inc21.i.i = add nuw nsw i32 %i.1424.i.i, 1
+  %exitcond438.i.i = icmp eq i32 %inc21.i.i, 0
+  br i1 %exitcond438.i.i, label %for.end22.i.i, label %for.body14.i.i
+
+for.end22.i.i:                                    ; preds = %for.body14.i.i
+  unreachable
+}
+
+; This test check for integer to pointer casting with load instructions.
+
+; CHECK-LABEL: @cvCalcEMD3
+; CHECK: vector.body
+; CHECK: inttoptr <{{[0-9]+}} x i64>
+define void @cvCalcEMD3() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  br label %for.body14.i.i
+
+for.body14.i.i:                                   ; preds = %for.body14.i.i, %entry
+  %i.1424.i.i = phi i32 [ %inc21.i.i, %for.body14.i.i ], [ 0, %entry ]
+  %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* undef, i32 %i.1424.i.i
+  %val.i.i = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* %arrayidx15.i.i1427, i32 0, i32 0
+  %load_d = load double, double* %val.i.i, align 4
+  %next19.i.i = getelementptr inbounds %struct.CvNode1D, %struct.CvNode1D* undef, i32 %i.1424.i.i, i32 1
+  %load_p = load %struct.CvNode1D*, %struct.CvNode1D** %next19.i.i, align 4
+  %inc21.i.i = add nuw nsw i32 %i.1424.i.i, 1
+  %exitcond438.i.i = icmp eq i32 %inc21.i.i, 0
+  br i1 %exitcond438.i.i, label %for.end22.i.i, label %for.body14.i.i
+
+for.end22.i.i:                                    ; preds = %for.body14.i.i
+  unreachable
+}
+
+; This test check for pointer to integer casting with load instructions.
+
+; CHECK-LABEL: @cvCalcEMD3_2
+; CHECK: vector.body
+; CHECK: ptrtoint <{{[0-9]+}} x %struct.CvNode1D2*>
+define void @cvCalcEMD3_2() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  br label %for.body14.i.i
+
+for.body14.i.i:                                   ; preds = %for.body14.i.i, %entry
+  %i.1424.i.i = phi i32 [ %inc21.i.i, %for.body14.i.i ], [ 0, %entry ]
+  %next19.i.i = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* undef, i32 %i.1424.i.i, i32 0
+  %load_p = load %struct.CvNode1D2*, %struct.CvNode1D2** %next19.i.i, align 4
+  %arrayidx15.i.i1427 = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* undef, i32 %i.1424.i.i
+  %val.i.i = getelementptr inbounds %struct.CvNode1D2, %struct.CvNode1D2* %arrayidx15.i.i1427, i32 0, i32 1
+  %load_d = load double, double* %val.i.i, align 4
+  %inc21.i.i = add nuw nsw i32 %i.1424.i.i, 1
+  %exitcond438.i.i = icmp eq i32 %inc21.i.i, 0
+  br i1 %exitcond438.i.i, label %for.end22.i.i, label %for.body14.i.i
+
+for.end22.i.i:                                    ; preds = %for.body14.i.i
+  unreachable
+}
+
+declare i32 @__gxx_personality_v0(...)
+
+attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
diff --git a/test/CodeGen/AArch64/machine-combiner.ll b/test/CodeGen/AArch64/machine-combiner.ll
index 0bd416ad1721..358315d088db 100644
--- a/test/CodeGen/AArch64/machine-combiner.ll
+++ b/test/CodeGen/AArch64/machine-combiner.ll
@@ -1,5 +1,10 @@
 ; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=cortex-a57 -enable-unsafe-fp-math -disable-post-ra < %s | FileCheck %s
 
+; Incremental updates of the instruction depths should be enough for this test
+; case.
+; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=cortex-a57 -enable-unsafe-fp-math \
+; RUN:     -disable-post-ra -machine-combiner-inc-threshold=0 < %s | FileCheck %s
+
 ; Verify that the first two adds are independent regardless of how the inputs are
 ; commuted. The destination registers are used as source registers for the third add.
 
diff --git a/test/CodeGen/AArch64/machine-combiner.mir b/test/CodeGen/AArch64/machine-combiner.mir
new file mode 100644
index 000000000000..0f90ef70e4af
--- /dev/null
+++ b/test/CodeGen/AArch64/machine-combiner.mir
@@ -0,0 +1,48 @@
+# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a57 -enable-unsafe-fp-math \
+# RUN:     -run-pass machine-combiner -machine-combiner-inc-threshold=0 \
+# RUN:     -verify-machineinstrs  -o - %s | FileCheck %s
+---
+# Test incremental depth updates succeed when triggered after the removal of
+# the first instruction in a basic block.
+
+# CHECK-LABEL: name: inc_update_iterator_test
+name:            inc_update_iterator_test
+registers:
+  - { id: 0, class: fpr64 }
+  - { id: 1, class: gpr32 }
+  - { id: 2, class: gpr32 }
+  - { id: 3, class: gpr32 }
+  - { id: 4, class: gpr32 }
+  - { id: 5, class: gpr32 }
+  - { id: 6, class: gpr32 }
+  - { id: 7, class: fpr64 }
+  - { id: 8, class: fpr64 }
+  - { id: 9, class: fpr64 }
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.2
+
+    %3 = COPY %w2
+    %2 = COPY %w1
+    %1 = COPY %w0
+    %0 = COPY %d0
+    %4 = SUBSWrr %1, %2, implicit-def %nzcv
+    Bcc 13, %bb.2, implicit %nzcv
+    B %bb.1
+
+  bb.1:
+    ; CHECK: MADDWrrr %1, %2, %3
+    %5 = MADDWrrr %1, %2, %wzr
+    %6 = ADDWrr %3, killed %5
+    %7 = SCVTFUWDri killed %6
+    ; CHECK: FMADDDrrr %7, %7, %0
+    %8 = FMULDrr %7, %7
+    %9 = FADDDrr %0, killed %8
+    %d0 = COPY %9
+    RET_ReallyLR implicit %d0
+
+  bb.2:
+    %d0 = COPY %0
+    RET_ReallyLR implicit %d0
+
+...
diff --git a/test/CodeGen/AArch64/machine-copy-prop.ll b/test/CodeGen/AArch64/machine-copy-prop.ll
index 6bacf852907e..2ac87f000484 100644
--- a/test/CodeGen/AArch64/machine-copy-prop.ll
+++ b/test/CodeGen/AArch64/machine-copy-prop.ll
@@ -2,18 +2,18 @@
 
 ; This file check a bug in MachineCopyPropagation pass. The last COPY will be
 ; incorrectly removed if the machine instructions are as follows:
-;   %Q5_Q6<def> = COPY %Q2_Q3
-;   %D5<def> =
-;   %D3<def> =
-;   %D3<def> = COPY %D6
+;   %q5_q6 = COPY %q2_q3
+;   %d5 =
+;   %d3 =
+;   %d3 = COPY %d6
 ; This is caused by a bug in function SourceNoLongerAvailable(), which fails to
-; remove the relationship of D6 and "%Q5_Q6<def> = COPY %Q2_Q3".
+; remove the relationship of D6 and "%q5_q6 = COPY %q2_q3".
 
 @failed = internal unnamed_addr global i1 false
 
 ; CHECK-LABEL: foo:
 ; CHECK: ld2
-; CHECK-NOT: // kill: D{{[0-9]+}}<def> D{{[0-9]+}}<kill>
+; CHECK-NOT: // kill: def D{{[0-9]+}} killed D{{[0-9]+}}
 define void @foo(<2 x i32> %shuffle251, <8 x i8> %vtbl1.i, i8* %t2, <2 x i32> %vrsubhn_v2.i1364) {
 entry:
   %val0 = alloca [2 x i64], align 8
diff --git a/test/CodeGen/AArch64/machine-outliner-remarks.ll b/test/CodeGen/AArch64/machine-outliner-remarks.ll
new file mode 100644
index 000000000000..a5f131b5a0ca
--- /dev/null
+++ b/test/CodeGen/AArch64/machine-outliner-remarks.ll
@@ -0,0 +1,123 @@
+; RUN: llc %s -enable-machine-outliner -mtriple=aarch64-unknown-unknown -pass-remarks=machine-outliner -pass-remarks-missed=machine-outliner -o /dev/null 2>&1 | FileCheck %s
+; CHECK: machine-outliner-remarks.ll:5:9:
+; CHECK-SAME: Did not outline 2 instructions from 2 locations.
+; CHECK-SAME: Instructions from outlining all occurrences (9) >=
+; CHECK-SAME: Unoutlined instruction count (4)
+; CHECK-SAME: (Also found at: machine-outliner-remarks.ll:13:9)
+; CHECK: remark: <unknown>:0:0: Saved 5 instructions by outlining 7 instructions
+; CHECK-SAME: from 2 locations. (Found at: machine-outliner-remarks.ll:27:9,
+; CHECK-SAME: machine-outliner-remarks.ll:36:1)
+; RUN: llc %s -enable-machine-outliner -mtriple=aarch64-unknown-unknown -o /dev/null -pass-remarks-missed=machine-outliner -pass-remarks-output=%t.yaml
+; RUN: cat %t.yaml | FileCheck %s -check-prefix=YAML
+; YAML: --- !Missed
+; YAML-NEXT: Pass:            machine-outliner
+; YAML-NEXT: Name:            NotOutliningCheaper
+; YAML-NEXT: DebugLoc:        { File: machine-outliner-remarks.ll, Line: 5, Column: 9 }
+; YAML-NEXT: Function:        dog
+; YAML-NEXT: Args:            
+; YAML-NEXT:   - String:          'Did not outline '
+; YAML-NEXT:   - Length:          '2'
+; YAML-NEXT:   - String:          ' instructions'
+; YAML-NEXT:   - String:          ' from '
+; YAML-NEXT:   - NumOccurrences:  '2'
+; YAML-NEXT:   - String:          ' locations.'
+; YAML-NEXT:   - String:          ' Instructions from outlining all occurrences ('
+; YAML-NEXT:   - OutliningCost:   '9'
+; YAML-NEXT:   - String:          ')'
+; YAML-NEXT:   - String:          ' >= Unoutlined instruction count ('
+; YAML-NEXT:   - NotOutliningCost: '4'
+; YAML-NEXT:   - String:          ')'
+; YAML-NEXT:   - String:          ' (Also found at: '
+; YAML-NEXT:   - OtherStartLoc1:  'machine-outliner-remarks.ll:13:9'
+; YAML-NEXT:     DebugLoc:        { File: machine-outliner-remarks.ll, Line: 13, Column: 9 }
+; YAML-NEXT:   - String:          ')'
+; YAML: --- !Passed
+; YAML-NEXT: Pass:            machine-outliner
+; YAML-NEXT: Name:            OutlinedFunction
+; YAML-NEXT: Function:        OUTLINED_FUNCTION_0
+; YAML-NEXT: Args:            
+; YAML-NEXT:   - String:          'Saved '
+; YAML-NEXT:   - OutliningBenefit: '5'
+; YAML-NEXT:   - String:          ' instructions by '
+; YAML-NEXT:   - String:          'outlining '
+; YAML-NEXT:   - Length:          '7'
+; YAML-NEXT:   - String:          ' instructions '
+; YAML-NEXT:   - String:          'from '
+; YAML-NEXT:   - NumOccurrences:  '2'
+; YAML-NEXT:   - String:          ' locations. '
+; YAML-NEXT:   - String:          '(Found at: '
+; YAML-NEXT:   - StartLoc0:       'machine-outliner-remarks.ll:27:9'
+; YAML-NEXT:     DebugLoc:        { File: machine-outliner-remarks.ll, Line: 27, Column: 9 }
+; YAML-NEXT:   - String:          ', '
+; YAML-NEXT:   - StartLoc1:       'machine-outliner-remarks.ll:36:1'
+; YAML-NEXT:     DebugLoc:        { File: machine-outliner-remarks.ll, Line: 36, Column: 1 }
+; YAML-NEXT:   - String:          ')'
+
+define void @dog() #0 !dbg !8 {
+entry:
+  %x = alloca i32, align 4
+  %y = alloca i32, align 4
+  store i32 0, i32* %x, align 4
+  store i32 1, i32* %y, align 4, !dbg !12
+  ret void
+}
+
+define void @cat() #0 !dbg !14 {
+entry:
+  %x = alloca i32, align 4
+  %y = alloca i32, align 4
+  store i32 0, i32* %x, align 4
+  store i32 1, i32* %y, align 4, !dbg !16
+  ret void
+}
+
+define void @foo() #0 !dbg !18 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 1, i32* %2, align 4, !dbg !24
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4, !dbg !26
+  ret void
+}
+
+define void @bar() #0 !dbg !27 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 1, i32* %2, align 4, !dbg !33
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4, !dbg !35
+  ret void
+}
+
+attributes #0 = { noredzone nounwind ssp uwtable "no-frame-pointer-elim"="false" "target-cpu"="cyclone" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5, !6}
+!llvm.ident = !{!7}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+!1 = !DIFile(filename: "machine-outliner-remarks.ll", directory: "/tmp")
+!2 = !{}
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"wchar_size", i32 4}
+!6 = !{i32 7, !"PIC Level", i32 2}
+!7 = !{!""}
+!8 = distinct !DISubprogram(name: "dog", scope: !1, file: !1, line: 2, type: !9, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+!9 = !DISubroutineType(types: !10)
+!10 = !{null}
+!12 = !DILocation(line: 5, column: 9, scope: !8)
+!14 = distinct !DISubprogram(name: "cat", scope: !1, file: !1, line: 10, type: !9, isLocal: false, isDefinition: true, scopeLine: 11, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+!16 = !DILocation(line: 13, column: 9, scope: !14)
+!18 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 26, type: !9, isLocal: false, isDefinition: true, scopeLine: 26, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+!24 = !DILocation(line: 27, column: 9, scope: !18)
+!26 = !DILocation(line: 29, column: 9, scope: !18)
+!27 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 35, type: !9, isLocal: false, isDefinition: true, scopeLine: 35, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
+!33 = !DILocation(line: 36, column: 1, scope: !27)
+!35 = !DILocation(line: 38, column: 1, scope: !27)
diff --git a/test/CodeGen/AArch64/machine-outliner.ll b/test/CodeGen/AArch64/machine-outliner.ll
index b5094fe47508..9b6254fb3cc1 100644
--- a/test/CodeGen/AArch64/machine-outliner.ll
+++ b/test/CodeGen/AArch64/machine-outliner.ll
@@ -1,9 +1,31 @@
-; RUN: llc -enable-machine-outliner -mtriple=aarch64-apple-darwin < %s | FileCheck %s
+; RUN: llc -enable-machine-outliner -mtriple=aarch64-apple-darwin < %s | FileCheck %s -check-prefix=NoODR
+; RUN: llc -enable-machine-outliner -enable-linkonceodr-outlining -mtriple=aarch64-apple-darwin < %s | FileCheck %s -check-prefix=ODR
+
+define linkonce_odr void @fish() #0 {
+  ; CHECK-LABEL: _fish:
+  ; NoODR:      orr w8, wzr, #0x1
+  ; NoODR-NEXT: stp w8, wzr, [sp, #8]
+  ; NoODR-NEXT: orr w8, wzr, #0x2
+  ; NoODR-NEXT: str w8, [sp, #4]
+  ; NoODR-NEXT: orr w8, wzr, #0x3
+  ; NoODR-NEXT: str w8, [sp], #16
+  ; NoODR-NEXT: ret
+  ; ODR: b l_OUTLINED_FUNCTION_0
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  ret void
+}
 
 define void @cat() #0 {
-; CHECK-LABEL: _cat:
-; CHECK: b l_OUTLINED_FUNCTION_0
-; CHECK-NOT: ret
+  ; CHECK-LABEL: _cat:
+  ; CHECK: b l_OUTLINED_FUNCTION_0
+  ; CHECK-NOT: ret
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
@@ -16,9 +38,9 @@ define void @cat() #0 {
 }
 
 define void @dog() #0 {
-; CHECK-LABEL: _dog:
-; CHECK: b l_OUTLINED_FUNCTION_0
-; CHECK-NOT: ret
+  ; CHECK-LABEL: _dog:
+  ; CHECK: b l_OUTLINED_FUNCTION_0
+  ; CHECK-NOT: ret
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
@@ -39,5 +61,4 @@ define void @dog() #0 {
 ; CHECK-NEXT: str w8, [sp], #16
 ; CHECK-NEXT: ret
 
-
 attributes #0 = { noredzone nounwind ssp uwtable "no-frame-pointer-elim"="false" "target-cpu"="cyclone" }
diff --git a/test/CodeGen/AArch64/machine-outliner.mir b/test/CodeGen/AArch64/machine-outliner.mir
new file mode 100644
index 000000000000..708e2e428802
--- /dev/null
+++ b/test/CodeGen/AArch64/machine-outliner.mir
@@ -0,0 +1,131 @@
+# RUN: llc -mtriple=aarch64--- -run-pass=machine-outliner %s -o - | FileCheck %s
+--- |
+
+  define void @baz() #0 {
+    ret void
+  }
+
+  define i32 @main() #0 {
+    ret i32 0
+  }
+  
+  define void @bar(i32 %a) #0 {
+    ret void
+  }
+  
+  attributes #0 = { noinline noredzone "no-frame-pointer-elim"="true" }
+...
+---
+# This test ensures that we
+# - Create outlined functions
+# - Don't outline anything to do with LR or W30
+# - Save LR when it's not available
+#
+# CHECK-LABEL: name: main
+# CHECK: BL @OUTLINED_FUNCTION_[[F0:[0-9]+]]
+# CHECK-NEXT: early-clobber %sp, %lr = LDRXpost %sp, 16
+# CHECK-NEXT: STRHHroW %w16, %x9, %w30, 1, 1
+# CHECK-NEXT: %lr = ORRXri %xzr, 1
+# CHECK: BL @OUTLINED_FUNCTION_[[F0]]
+# CHECK-NEXT: early-clobber %sp, %lr = LDRXpost %sp, 16
+# CHECK-NEXT: STRHHroW %w16, %x9, %w30, 1, 1
+# CHECK-NEXT: %lr = ORRXri %xzr, 1
+# CHECK: BL @OUTLINED_FUNCTION_[[F0]]
+# CHECK-NEXT: early-clobber %sp, %lr = LDRXpost %sp, 16
+# CHECK-NEXT: STRHHroW %w16, %x9, %w30, 1, 1
+# CHECK-NEXT: %lr = ORRXri %xzr, 1
+name:            main
+body:             |
+  bb.0:
+    %sp = frame-setup SUBXri %sp, 16, 0
+    %x9 = ORRXri %xzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w30 = ORRWri %wzr, 1
+    %lr = ORRXri %xzr, 1
+
+    %x20, %x19 = LDPXi %sp, 10
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    STRHHroW %w16, %x9, %w30, 1, 1
+    %lr = ORRXri %xzr, 1
+
+    %w3 = ORRWri %wzr, 1993
+
+    %x20, %x19 = LDPXi %sp, 10
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    STRHHroW %w16, %x9, %w30, 1, 1
+    %lr = ORRXri %xzr, 1
+
+    %w4 = ORRWri %wzr, 1994
+
+    %x20, %x19 = LDPXi %sp, 10
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    %w16 = ORRWri %wzr, 1
+    STRHHroW %w16, %x9, %w30, 1, 1
+    %lr = ORRXri %xzr, 1
+
+    %sp = ADDXri %sp, 16, 0
+    RET undef %lr
+
+...
+---
+# This test ensures that we can avoid saving LR when it's available.
+# CHECK-LABEL: bb.1:
+# CHECK-NOT: BL @baz, implicit-def dead %lr, implicit %sp
+# CHECK: BL @OUTLINED_FUNCTION_[[F1:[0-9]+]], implicit-def %lr, implicit %sp
+# CHECK-NEXT: %w17 = ORRWri %wzr, 2
+# CHECK-NEXT: BL @OUTLINED_FUNCTION_[[F1]], implicit-def %lr, implicit %sp
+# CHECK-NEXT: %w8 = ORRWri %wzr, 0
+name:            bar
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: %w0, %lr, %w8
+    %sp = frame-setup SUBXri %sp, 32, 0
+    %fp = frame-setup ADDXri %sp, 16, 0
+
+  bb.1:
+    BL @baz, implicit-def dead %lr, implicit %sp
+    %w17 = ORRWri %wzr, 1
+    %w17 = ORRWri %wzr, 1
+    %w17 = ORRWri %wzr, 1
+    %w17 = ORRWri %wzr, 1
+    BL @baz, implicit-def dead %lr, implicit %sp
+    %w17 = ORRWri %wzr, 2
+    BL @baz, implicit-def dead %lr, implicit %sp
+    %w17 = ORRWri %wzr, 1
+    %w17 = ORRWri %wzr, 1
+    %w17 = ORRWri %wzr, 1
+    %w17 = ORRWri %wzr, 1
+    BL @baz, implicit-def dead %lr, implicit %sp
+    %w8 = ORRWri %wzr, 0
+  
+  bb.2:
+    %fp, %lr = LDPXi %sp, 2
+    %sp = ADDXri %sp, 32, 0
+    RET undef %lr
+
+...
+---
+name:            baz
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: %w0, %lr, %w8
+    RET undef %lr
+
+# CHECK-LABEL: name:            OUTLINED_FUNCTION_{{[0-9]}}
+# CHECK=LABEL: name:            OUTLINED_FUNCTION_{{[1-9]}}
diff --git a/test/CodeGen/AArch64/machine-zero-copy-remove.mir b/test/CodeGen/AArch64/machine-zero-copy-remove.mir
new file mode 100644
index 000000000000..3f25c0715574
--- /dev/null
+++ b/test/CodeGen/AArch64/machine-zero-copy-remove.mir
@@ -0,0 +1,565 @@
+# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-copyelim %s -verify-machineinstrs -o - | FileCheck %s
+---
+# CHECK-LABEL: name: test1
+# CHECK: ANDSWri %w0, 1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test1
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %x1, %x2
+
+    %w0 = ANDSWri %w0, 1, implicit-def %nzcv
+    STRWui killed %w0, killed %x1, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test2
+# CHECK: ANDSXri %x0, 1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test2
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2
+
+    %x0 = ANDSXri %x0, 1, implicit-def %nzcv
+    STRXui killed %x0, killed %x1, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test3
+# CHECK: ADDSWri %w0, 1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test3
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %x1, %x2
+
+    %w0 = ADDSWri %w0, 1, 0, implicit-def %nzcv
+    STRWui killed %w0, killed %x1, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test4
+# CHECK: ADDSXri %x0, 1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test4
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2
+
+    %x0 = ADDSXri %x0, 1, 0, implicit-def %nzcv
+    STRXui killed %x0, killed %x1, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test5
+# CHECK: SUBSWri %w0, 1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test5
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %x1, %x2
+
+    %w0 = SUBSWri %w0, 1, 0, implicit-def %nzcv
+    STRWui killed %w0, killed %x1, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test6
+# CHECK: SUBSXri %x0, 1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test6
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2
+
+    %x0 = SUBSXri %x0, 1, 0, implicit-def %nzcv
+    STRXui killed %x0, killed %x1, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test7
+# CHECK: ADDSWrr %w0, %w1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test7
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %w1, %x2, %x3
+
+    %w0 = ADDSWrr %w0, %w1, implicit-def %nzcv
+    STRWui killed %w0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test8
+# CHECK: ADDSXrr %x0, %x1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test8
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+
+    %x0 = ADDSXrr %x0, %x1, implicit-def %nzcv
+    STRXui killed %x0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test9
+# CHECK: ANDSWrr %w0, %w1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test9
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %w1, %x2, %x3
+
+    %w0 = ANDSWrr %w0, %w1, implicit-def %nzcv
+    STRWui killed %w0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test10
+# CHECK: ANDSXrr %x0, %x1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test10
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+
+    %x0 = ANDSXrr %x0, %x1, implicit-def %nzcv
+    STRXui killed %x0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test11
+# CHECK: BICSWrr %w0, %w1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test11
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %w1, %x2, %x3
+
+    %w0 = BICSWrr %w0, %w1, implicit-def %nzcv
+    STRWui killed %w0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test12
+# CHECK: BICSXrr %x0, %x1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test12
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+
+    %x0 = BICSXrr %x0, %x1, implicit-def %nzcv
+    STRXui killed %x0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test13
+# CHECK: SUBSWrr %w0, %w1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test13
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %w1, %x2, %x3
+
+    %w0 = SUBSWrr %w0, %w1, implicit-def %nzcv
+    STRWui killed %w0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test14
+# CHECK: SUBSXrr %x0, %x1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test14
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+
+    %x0 = SUBSXrr %x0, %x1, implicit-def %nzcv
+    STRXui killed %x0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test15
+# CHECK: ADDSWrs %w0, %w1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test15
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %w1, %x2, %x3
+
+    %w0 = ADDSWrs %w0, %w1, 0, implicit-def %nzcv
+    STRWui killed %w0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test16
+# CHECK: ADDSXrs %x0, %x1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test16
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+
+    %x0 = ADDSXrs %x0, %x1, 0, implicit-def %nzcv
+    STRXui killed %x0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test17
+# CHECK: ANDSWrs %w0, %w1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test17
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %w1, %x2, %x3
+
+    %w0 = ANDSWrs %w0, %w1, 0, implicit-def %nzcv
+    STRWui killed %w0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test18
+# CHECK: ANDSXrs %x0, %x1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %xzr
+name:            test18
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2, %x3
+
+    %x0 = ANDSXrs %x0, %x1, 0, implicit-def %nzcv
+    STRXui killed %x0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %x0 = COPY %xzr
+    STRXui killed %x0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# CHECK-LABEL: name: test19
+# CHECK: BICSWrs %w0, %w1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: COPY %wzr
+name:            test19
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %w1, %x2, %x3
+
+    %w0 = BICSWrs %w0, %w1, 0, implicit-def %nzcv
+    STRWui killed %w0, killed %x2, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x3
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x3, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# Unicorn test - we can remove a redundant copy and a redundant mov
+# CHECK-LABEL: name: test20
+# CHECK: SUBSWri %w1, 1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK-NOT: %w0 = COPY %wzr
+# CHECK-NOT: %w1 = MOVi32imm 1
+name:            test20
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w1, %x2
+
+    %w0 = SUBSWri %w1, 1, 0, implicit-def %nzcv
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %w0 = COPY %wzr
+    %w1 = MOVi32imm 1
+    STRWui killed %w0, %x2, 0
+    STRWui killed %w1, killed %x2, 1
+
+  bb.2:
+    RET_ReallyLR
+
+...
+# Negative test - MOVi32imm clobbers %w0
+# CHECK-LABEL: name: test21
+# CHECK: ANDSWri %w0, 1, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK: %w0 = COPY %wzr
+name:            test21
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %x1, %x2
+
+    %w0 = ANDSWri %w0, 1, implicit-def %nzcv
+    STRWui killed %w0, %x1, 0
+    %w0 = MOVi32imm -1
+    STRWui killed %w0, killed %x1, 1
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# Negative test - SUBSXri self-clobbers x0, so MOVi64imm can't be removed
+# CHECK-LABEL: name: test22
+# CHECK: SUBSXri %x0, 1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK: %x0 = MOVi64imm 1
+name:            test22
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %x0, %x1, %x2
+
+    %x0 = SUBSXri %x0, 1, 0, implicit-def %nzcv
+    STRXui killed %x0, killed %x1, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %x0 = MOVi64imm 1
+    STRXui killed %x0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
+...
+# Negative test - bb.1 has multiple preds
+# CHECK-LABEL: name: test23
+# CHECK: ADDSWri %w0, 1, 0, implicit-def %nzcv
+# CHECK: bb.1:
+# CHECK: COPY %wzr
+name:            test23
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: %w0, %x1, %x2
+
+    %w0 = ADDSWri %w0, 1, 0, implicit-def %nzcv
+    STRWui killed %w0, killed %x1, 0
+    Bcc 1, %bb.2, implicit killed %nzcv
+    B %bb.1
+
+  bb.3:
+    B %bb.1
+
+  bb.1:
+    liveins: %x2
+
+    %w0 = COPY %wzr
+    STRWui killed %w0, killed %x2, 0
+
+  bb.2:
+    RET_ReallyLR
diff --git a/test/CodeGen/AArch64/max-jump-table.ll b/test/CodeGen/AArch64/max-jump-table.ll
index 070502052fff..9a0179ecc1b8 100644
--- a/test/CodeGen/AArch64/max-jump-table.ll
+++ b/test/CodeGen/AArch64/max-jump-table.ll
@@ -28,19 +28,19 @@ entry:
   ]
 ; CHECK-LABEL: function jt1:
 ; CHECK-NEXT: Jump Tables:
-; CHECK0-NEXT: jt#0:
-; CHECK0-NOT: jt#1:
-; CHECK4-NEXT: jt#0:
-; CHECK4-SAME: jt#1:
-; CHECK4-SAME: jt#2:
-; CHECK4-SAME: jt#3:
-; CHECK4-NOT: jt#4:
-; CHECK8-NEXT: jt#0:
-; CHECK8-SAME: jt#1:
-; CHECK8-NOT: jt#2:
-; CHECKM1-NEXT: jt#0:
-; CHECKM1-SAME: jt#1
-; CHECKM1-NOT: jt#2:
+; CHECK0-NEXT: %jump-table.0:
+; CHECK0-NOT: %jump-table.1:
+; CHECK4-NEXT: %jump-table.0:
+; CHECK4-SAME: %jump-table.1:
+; CHECK4-SAME: %jump-table.2:
+; CHECK4-SAME: %jump-table.3:
+; CHECK4-NOT: %jump-table.4:
+; CHECK8-NEXT: %jump-table.0:
+; CHECK8-SAME: %jump-table.1:
+; CHECK8-NOT: %jump-table.2:
+; CHECKM1-NEXT: %jump-table.0:
+; CHECKM1-SAME: %jump-table.1
+; CHECKM1-NOT: %jump-table.2:
 ; CHEC-NEXT: Function Live Ins:
 
 bb1: tail call void @ext(i32 0) br label %return
@@ -77,10 +77,10 @@ entry:
   ]
 ; CHECK-LABEL: function jt2:
 ; CHECK-NEXT: Jump Tables:
-; CHECK0-NEXT: jt#0:  BB#1 BB#2 BB#3 BB#4 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#5 BB#6{{$}}
-; CHECK4-NEXT: jt#0:  BB#1 BB#2 BB#3 BB#4{{$}}
-; CHECK8-NEXT: jt#0:  BB#1 BB#2 BB#3 BB#4{{$}}
-; CHECKM1-NEXT: jt#0:  BB#1 BB#2 BB#3 BB#4{{$}}
+; CHECK0-NEXT: %jump-table.0:  %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}}
+; CHECK4-NEXT: %jump-table.0:  %bb.1 %bb.2 %bb.3 %bb.4{{$}}
+; CHECK8-NEXT: %jump-table.0:  %bb.1 %bb.2 %bb.3 %bb.4{{$}}
+; CHECKM1-NEXT: %jump-table.0:  %bb.1 %bb.2 %bb.3 %bb.4{{$}}
 ; CHEC-NEXT: Function Live Ins:
 
 bb1: tail call void @ext(i32 1) br label %return
diff --git a/test/CodeGen/AArch64/min-jump-table.ll b/test/CodeGen/AArch64/min-jump-table.ll
index 80974debc48a..b22e683ebfed 100644
--- a/test/CodeGen/AArch64/min-jump-table.ll
+++ b/test/CodeGen/AArch64/min-jump-table.ll
@@ -12,8 +12,8 @@ entry:
   ]
 ; CHECK-LABEL: function jt2:
 ; CHECK0-NEXT: Jump Tables:
-; CHECK0-NEXT: jt#0:
-; CHECK0-NOT: jt#1:
+; CHECK0-NEXT: %jump-table.0:
+; CHECK0-NOT: %jump-table.1:
 ; CHECK4-NOT: Jump Tables:
 ; CHECK8-NOT: Jump Tables:
 
@@ -33,11 +33,11 @@ entry:
   ]
 ; CHECK-LABEL: function jt4:
 ; CHECK0-NEXT: Jump Tables:
-; CHECK0-NEXT: jt#0:
-; CHECK0-NOT: jt#1:
+; CHECK0-NEXT: %jump-table.0:
+; CHECK0-NOT: %jump-table.1:
 ; CHECK4-NEXT: Jump Tables:
-; CHECK4-NEXT: jt#0:
-; CHECK4-NOT: jt#1:
+; CHECK4-NEXT: %jump-table.0:
+; CHECK4-NOT: %jump-table.1:
 ; CHECK8-NOT: Jump Tables:
 
 bb1: tail call void @ext(i32 0) br label %return
@@ -62,8 +62,8 @@ entry:
   ]
 ; CHECK-LABEL: function jt8:
 ; CHECK-NEXT: Jump Tables:
-; CHECK-NEXT: jt#0:
-; CHECK-NOT: jt#1:
+; CHECK-NEXT: %jump-table.0:
+; CHECK-NOT: %jump-table.1:
 
 bb1: tail call void @ext(i32 0) br label %return
 bb2: tail call void @ext(i32 2) br label %return
diff --git a/test/CodeGen/AArch64/misched-fusion-aes.ll b/test/CodeGen/AArch64/misched-fusion-aes.ll
index 9c3af6dae300..7901a20ca65f 100644
--- a/test/CodeGen/AArch64/misched-fusion-aes.ll
+++ b/test/CodeGen/AArch64/misched-fusion-aes.ll
@@ -5,6 +5,7 @@
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s
 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1  | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m2  | FileCheck %s
 
 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k)
 declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %d)
diff --git a/test/CodeGen/AArch64/misched-fusion.ll b/test/CodeGen/AArch64/misched-fusion.ll
index ee6007e393c9..19dfd8515c4e 100644
--- a/test/CodeGen/AArch64/misched-fusion.ll
+++ b/test/CodeGen/AArch64/misched-fusion.ll
@@ -1,14 +1,34 @@
-; RUN: llc -o - %s -mattr=+arith-cbz-fusion | FileCheck %s
-; RUN: llc -o - %s -mcpu=cyclone | FileCheck %s
+; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mattr=+arith-bcc-fusion | FileCheck %s --check-prefix=FUSEBCC
+; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mattr=+arith-cbz-fusion | FileCheck %s --check-prefix=FUSECBZ
+; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=cyclone            | FileCheck %s --check-prefix=FUSEBCC --check-prefix=FUSECBZ
 
 target triple = "aarch64-unknown"
 
 declare void @foobar(i32 %v0, i32 %v1)
 
+; Make sure cmp is scheduled in front of bcc
+; FUSEBCC-LABEL: test_cmp_bcc:
+; FUSEBCC: cmp {{w[0-9]+}}, #13
+; FUSEBCC-NEXT: b.ne {{.?LBB[0-9_]+}}
+define void @test_cmp_bcc(i32 %a0, i32 %a1) {
+entry:
+  %cond = icmp eq i32 %a0, 13
+  %v1 = add i32 %a1, 7
+  br i1 %cond, label %if, label %exit
+
+if:
+  call void @foobar(i32 %v1, i32 %a0)
+  br label %exit
+
+exit:
+  call void @foobar(i32 %a0, i32 %v1)
+  ret void
+}
+
 ; Make sure sub is scheduled in front of cbnz
-; CHECK-LABEL: test_sub_cbz:
-; CHECK: subs w[[SUBRES:[0-9]+]], w0, #13
-; CHECK: b.ne {{.?LBB[0-9_]+}}
+; FUSECBZ-LABEL: test_sub_cbz:
+; FUSECBZ: sub [[R:w[0-9]+]], {{w[0-9]+}}, #13
+; FUSECBZ-NEXT: cbnz [[R]], {{.?LBB[0-9_]+}}
 define void @test_sub_cbz(i32 %a0, i32 %a1) {
 entry:
   ; except for the fusion opportunity the sub/add should be equal so the
diff --git a/test/CodeGen/AArch64/neon-bitcast.ll b/test/CodeGen/AArch64/neon-bitcast.ll
index 61099d48fdd2..8f67ff83ae12 100644
--- a/test/CodeGen/AArch64/neon-bitcast.ll
+++ b/test/CodeGen/AArch64/neon-bitcast.ll
@@ -4,7 +4,7 @@
 
 define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind {
 ; CHECK: test_v8i8_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i8> %in to <1 x i64>
@@ -13,7 +13,7 @@ define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind {
 
 define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind {
 ; CHECK: test_v8i8_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i8> %in to <2 x i32>
@@ -22,7 +22,7 @@ define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind {
 
 define <2 x float> @test_v8i8_to_v2f32(<8 x i8> %in) nounwind{
 ; CHECK: test_v8i8_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i8> %in to <2 x float>
@@ -31,7 +31,7 @@ define <2 x float> @test_v8i8_to_v2f32(<8 x i8> %in) nounwind{
 
 define <4 x i16> @test_v8i8_to_v4i16(<8 x i8> %in) nounwind{
 ; CHECK: test_v8i8_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i8> %in to <4 x i16>
@@ -40,7 +40,7 @@ define <4 x i16> @test_v8i8_to_v4i16(<8 x i8> %in) nounwind{
 
 define <8 x i8> @test_v8i8_to_v8i8(<8 x i8> %in) nounwind{
 ; CHECK: test_v8i8_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i8> %in to <8 x i8>
@@ -51,7 +51,7 @@ define <8 x i8> @test_v8i8_to_v8i8(<8 x i8> %in) nounwind{
 
 define <1 x i64> @test_v4i16_to_v1i64(<4 x i16> %in) nounwind {
 ; CHECK: test_v4i16_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i16> %in to <1 x i64>
@@ -60,7 +60,7 @@ define <1 x i64> @test_v4i16_to_v1i64(<4 x i16> %in) nounwind {
 
 define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind {
 ; CHECK: test_v4i16_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i16> %in to <2 x i32>
@@ -69,7 +69,7 @@ define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind {
 
 define <2 x float> @test_v4i16_to_v2f32(<4 x i16> %in) nounwind{
 ; CHECK: test_v4i16_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i16> %in to <2 x float>
@@ -78,7 +78,7 @@ define <2 x float> @test_v4i16_to_v2f32(<4 x i16> %in) nounwind{
 
 define <4 x i16> @test_v4i16_to_v4i16(<4 x i16> %in) nounwind{
 ; CHECK: test_v4i16_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i16> %in to <4 x i16>
@@ -87,7 +87,7 @@ define <4 x i16> @test_v4i16_to_v4i16(<4 x i16> %in) nounwind{
 
 define <8 x i8> @test_v4i16_to_v8i8(<4 x i16> %in) nounwind{
 ; CHECK: test_v4i16_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i16> %in to <8 x i8>
@@ -98,7 +98,7 @@ define <8 x i8> @test_v4i16_to_v8i8(<4 x i16> %in) nounwind{
 
 define <1 x i64> @test_v2i32_to_v1i64(<2 x i32> %in) nounwind {
 ; CHECK: test_v2i32_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i32> %in to <1 x i64>
@@ -107,7 +107,7 @@ define <1 x i64> @test_v2i32_to_v1i64(<2 x i32> %in) nounwind {
 
 define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind {
 ; CHECK: test_v2i32_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i32> %in to <2 x i32>
@@ -116,7 +116,7 @@ define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind {
 
 define <2 x float> @test_v2i32_to_v2f32(<2 x i32> %in) nounwind{
 ; CHECK: test_v2i32_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i32> %in to <2 x float>
@@ -125,7 +125,7 @@ define <2 x float> @test_v2i32_to_v2f32(<2 x i32> %in) nounwind{
 
 define <4 x i16> @test_v2i32_to_v4i16(<2 x i32> %in) nounwind{
 ; CHECK: test_v2i32_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i32> %in to <4 x i16>
@@ -134,7 +134,7 @@ define <4 x i16> @test_v2i32_to_v4i16(<2 x i32> %in) nounwind{
 
 define <8 x i8> @test_v2i32_to_v8i8(<2 x i32> %in) nounwind{
 ; CHECK: test_v2i32_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i32> %in to <8 x i8>
@@ -145,7 +145,7 @@ define <8 x i8> @test_v2i32_to_v8i8(<2 x i32> %in) nounwind{
 
 define <1 x i64> @test_v2f32_to_v1i64(<2 x float> %in) nounwind {
 ; CHECK: test_v2f32_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x float> %in to <1 x i64>
@@ -154,7 +154,7 @@ define <1 x i64> @test_v2f32_to_v1i64(<2 x float> %in) nounwind {
 
 define <2 x i32> @test_v2f32_to_v2i32(<2 x float> %in) nounwind {
 ; CHECK: test_v2f32_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x float> %in to <2 x i32>
@@ -163,7 +163,7 @@ define <2 x i32> @test_v2f32_to_v2i32(<2 x float> %in) nounwind {
 
 define <2 x float> @test_v2f32_to_v2f32(<2 x float> %in) nounwind{
 ; CHECK: test_v2f32_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x float> %in to <2 x float>
@@ -172,7 +172,7 @@ define <2 x float> @test_v2f32_to_v2f32(<2 x float> %in) nounwind{
 
 define <4 x i16> @test_v2f32_to_v4i16(<2 x float> %in) nounwind{
 ; CHECK: test_v2f32_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x float> %in to <4 x i16>
@@ -181,7 +181,7 @@ define <4 x i16> @test_v2f32_to_v4i16(<2 x float> %in) nounwind{
 
 define <8 x i8> @test_v2f32_to_v8i8(<2 x float> %in) nounwind{
 ; CHECK: test_v2f32_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x float> %in to <8 x i8>
@@ -192,7 +192,7 @@ define <8 x i8> @test_v2f32_to_v8i8(<2 x float> %in) nounwind{
 
 define <1 x i64> @test_v1i64_to_v1i64(<1 x i64> %in) nounwind {
 ; CHECK: test_v1i64_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <1 x i64> %in to <1 x i64>
@@ -201,7 +201,7 @@ define <1 x i64> @test_v1i64_to_v1i64(<1 x i64> %in) nounwind {
 
 define <2 x i32> @test_v1i64_to_v2i32(<1 x i64> %in) nounwind {
 ; CHECK: test_v1i64_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <1 x i64> %in to <2 x i32>
@@ -210,7 +210,7 @@ define <2 x i32> @test_v1i64_to_v2i32(<1 x i64> %in) nounwind {
 
 define <2 x float> @test_v1i64_to_v2f32(<1 x i64> %in) nounwind{
 ; CHECK: test_v1i64_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <1 x i64> %in to <2 x float>
@@ -219,7 +219,7 @@ define <2 x float> @test_v1i64_to_v2f32(<1 x i64> %in) nounwind{
 
 define <4 x i16> @test_v1i64_to_v4i16(<1 x i64> %in) nounwind{
 ; CHECK: test_v1i64_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <1 x i64> %in to <4 x i16>
@@ -228,7 +228,7 @@ define <4 x i16> @test_v1i64_to_v4i16(<1 x i64> %in) nounwind{
 
 define <8 x i8> @test_v1i64_to_v8i8(<1 x i64> %in) nounwind{
 ; CHECK: test_v1i64_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <1 x i64> %in to <8 x i8>
@@ -240,7 +240,7 @@ define <8 x i8> @test_v1i64_to_v8i8(<1 x i64> %in) nounwind{
 
 define <2 x double> @test_v16i8_to_v2f64(<16 x i8> %in) nounwind {
 ; CHECK: test_v16i8_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <16 x i8> %in to <2 x double>
@@ -249,7 +249,7 @@ define <2 x double> @test_v16i8_to_v2f64(<16 x i8> %in) nounwind {
 
 define <2 x i64> @test_v16i8_to_v2i64(<16 x i8> %in) nounwind {
 ; CHECK: test_v16i8_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <16 x i8> %in to <2 x i64>
@@ -258,7 +258,7 @@ define <2 x i64> @test_v16i8_to_v2i64(<16 x i8> %in) nounwind {
 
 define <4 x i32> @test_v16i8_to_v4i32(<16 x i8> %in) nounwind {
 ; CHECK: test_v16i8_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <16 x i8> %in to <4 x i32>
@@ -267,7 +267,7 @@ define <4 x i32> @test_v16i8_to_v4i32(<16 x i8> %in) nounwind {
 
 define <4 x float> @test_v16i8_to_v2f32(<16 x i8> %in) nounwind{
 ; CHECK: test_v16i8_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <16 x i8> %in to <4 x float>
@@ -276,7 +276,7 @@ define <4 x float> @test_v16i8_to_v2f32(<16 x i8> %in) nounwind{
 
 define <8 x i16> @test_v16i8_to_v8i16(<16 x i8> %in) nounwind{
 ; CHECK: test_v16i8_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <16 x i8> %in to <8 x i16>
@@ -285,7 +285,7 @@ define <8 x i16> @test_v16i8_to_v8i16(<16 x i8> %in) nounwind{
 
 define <16 x i8> @test_v16i8_to_v16i8(<16 x i8> %in) nounwind{
 ; CHECK: test_v16i8_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <16 x i8> %in to <16 x i8>
@@ -296,7 +296,7 @@ define <16 x i8> @test_v16i8_to_v16i8(<16 x i8> %in) nounwind{
 
 define <2 x double> @test_v8i16_to_v2f64(<8 x i16> %in) nounwind {
 ; CHECK: test_v8i16_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i16> %in to <2 x double>
@@ -305,7 +305,7 @@ define <2 x double> @test_v8i16_to_v2f64(<8 x i16> %in) nounwind {
 
 define <2 x i64> @test_v8i16_to_v2i64(<8 x i16> %in) nounwind {
 ; CHECK: test_v8i16_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i16> %in to <2 x i64>
@@ -314,7 +314,7 @@ define <2 x i64> @test_v8i16_to_v2i64(<8 x i16> %in) nounwind {
 
 define <4 x i32> @test_v8i16_to_v4i32(<8 x i16> %in) nounwind {
 ; CHECK: test_v8i16_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i16> %in to <4 x i32>
@@ -323,7 +323,7 @@ define <4 x i32> @test_v8i16_to_v4i32(<8 x i16> %in) nounwind {
 
 define <4 x float> @test_v8i16_to_v2f32(<8 x i16> %in) nounwind{
 ; CHECK: test_v8i16_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i16> %in to <4 x float>
@@ -332,7 +332,7 @@ define <4 x float> @test_v8i16_to_v2f32(<8 x i16> %in) nounwind{
 
 define <8 x i16> @test_v8i16_to_v8i16(<8 x i16> %in) nounwind{
 ; CHECK: test_v8i16_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i16> %in to <8 x i16>
@@ -341,7 +341,7 @@ define <8 x i16> @test_v8i16_to_v8i16(<8 x i16> %in) nounwind{
 
 define <16 x i8> @test_v8i16_to_v16i8(<8 x i16> %in) nounwind{
 ; CHECK: test_v8i16_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <8 x i16> %in to <16 x i8>
@@ -352,7 +352,7 @@ define <16 x i8> @test_v8i16_to_v16i8(<8 x i16> %in) nounwind{
 
 define <2 x double> @test_v4i32_to_v2f64(<4 x i32> %in) nounwind {
 ; CHECK: test_v4i32_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i32> %in to <2 x double>
@@ -361,7 +361,7 @@ define <2 x double> @test_v4i32_to_v2f64(<4 x i32> %in) nounwind {
 
 define <2 x i64> @test_v4i32_to_v2i64(<4 x i32> %in) nounwind {
 ; CHECK: test_v4i32_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i32> %in to <2 x i64>
@@ -370,7 +370,7 @@ define <2 x i64> @test_v4i32_to_v2i64(<4 x i32> %in) nounwind {
 
 define <4 x i32> @test_v4i32_to_v4i32(<4 x i32> %in) nounwind {
 ; CHECK: test_v4i32_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i32> %in to <4 x i32>
@@ -379,7 +379,7 @@ define <4 x i32> @test_v4i32_to_v4i32(<4 x i32> %in) nounwind {
 
 define <4 x float> @test_v4i32_to_v2f32(<4 x i32> %in) nounwind{
 ; CHECK: test_v4i32_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i32> %in to <4 x float>
@@ -388,7 +388,7 @@ define <4 x float> @test_v4i32_to_v2f32(<4 x i32> %in) nounwind{
 
 define <8 x i16> @test_v4i32_to_v8i16(<4 x i32> %in) nounwind{
 ; CHECK: test_v4i32_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i32> %in to <8 x i16>
@@ -397,7 +397,7 @@ define <8 x i16> @test_v4i32_to_v8i16(<4 x i32> %in) nounwind{
 
 define <16 x i8> @test_v4i32_to_v16i8(<4 x i32> %in) nounwind{
 ; CHECK: test_v4i32_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x i32> %in to <16 x i8>
@@ -408,7 +408,7 @@ define <16 x i8> @test_v4i32_to_v16i8(<4 x i32> %in) nounwind{
 
 define <2 x double> @test_v4f32_to_v2f64(<4 x float> %in) nounwind {
 ; CHECK: test_v4f32_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x float> %in to <2 x double>
@@ -417,7 +417,7 @@ define <2 x double> @test_v4f32_to_v2f64(<4 x float> %in) nounwind {
 
 define <2 x i64> @test_v4f32_to_v2i64(<4 x float> %in) nounwind {
 ; CHECK: test_v4f32_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x float> %in to <2 x i64>
@@ -426,7 +426,7 @@ define <2 x i64> @test_v4f32_to_v2i64(<4 x float> %in) nounwind {
 
 define <4 x i32> @test_v4f32_to_v4i32(<4 x float> %in) nounwind {
 ; CHECK: test_v4f32_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x float> %in to <4 x i32>
@@ -435,7 +435,7 @@ define <4 x i32> @test_v4f32_to_v4i32(<4 x float> %in) nounwind {
 
 define <4 x float> @test_v4f32_to_v4f32(<4 x float> %in) nounwind{
 ; CHECK: test_v4f32_to_v4f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x float> %in to <4 x float>
@@ -444,7 +444,7 @@ define <4 x float> @test_v4f32_to_v4f32(<4 x float> %in) nounwind{
 
 define <8 x i16> @test_v4f32_to_v8i16(<4 x float> %in) nounwind{
 ; CHECK: test_v4f32_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x float> %in to <8 x i16>
@@ -453,7 +453,7 @@ define <8 x i16> @test_v4f32_to_v8i16(<4 x float> %in) nounwind{
 
 define <16 x i8> @test_v4f32_to_v16i8(<4 x float> %in) nounwind{
 ; CHECK: test_v4f32_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <4 x float> %in to <16 x i8>
@@ -464,7 +464,7 @@ define <16 x i8> @test_v4f32_to_v16i8(<4 x float> %in) nounwind{
 
 define <2 x double> @test_v2i64_to_v2f64(<2 x i64> %in) nounwind {
 ; CHECK: test_v2i64_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i64> %in to <2 x double>
@@ -473,7 +473,7 @@ define <2 x double> @test_v2i64_to_v2f64(<2 x i64> %in) nounwind {
 
 define <2 x i64> @test_v2i64_to_v2i64(<2 x i64> %in) nounwind {
 ; CHECK: test_v2i64_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i64> %in to <2 x i64>
@@ -482,7 +482,7 @@ define <2 x i64> @test_v2i64_to_v2i64(<2 x i64> %in) nounwind {
 
 define <4 x i32> @test_v2i64_to_v4i32(<2 x i64> %in) nounwind {
 ; CHECK: test_v2i64_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i64> %in to <4 x i32>
@@ -491,7 +491,7 @@ define <4 x i32> @test_v2i64_to_v4i32(<2 x i64> %in) nounwind {
 
 define <4 x float> @test_v2i64_to_v4f32(<2 x i64> %in) nounwind{
 ; CHECK: test_v2i64_to_v4f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i64> %in to <4 x float>
@@ -500,7 +500,7 @@ define <4 x float> @test_v2i64_to_v4f32(<2 x i64> %in) nounwind{
 
 define <8 x i16> @test_v2i64_to_v8i16(<2 x i64> %in) nounwind{
 ; CHECK: test_v2i64_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i64> %in to <8 x i16>
@@ -509,7 +509,7 @@ define <8 x i16> @test_v2i64_to_v8i16(<2 x i64> %in) nounwind{
 
 define <16 x i8> @test_v2i64_to_v16i8(<2 x i64> %in) nounwind{
 ; CHECK: test_v2i64_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x i64> %in to <16 x i8>
@@ -520,7 +520,7 @@ define <16 x i8> @test_v2i64_to_v16i8(<2 x i64> %in) nounwind{
 
 define <2 x double> @test_v2f64_to_v2f64(<2 x double> %in) nounwind {
 ; CHECK: test_v2f64_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x double> %in to <2 x double>
@@ -529,7 +529,7 @@ define <2 x double> @test_v2f64_to_v2f64(<2 x double> %in) nounwind {
 
 define <2 x i64> @test_v2f64_to_v2i64(<2 x double> %in) nounwind {
 ; CHECK: test_v2f64_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x double> %in to <2 x i64>
@@ -538,7 +538,7 @@ define <2 x i64> @test_v2f64_to_v2i64(<2 x double> %in) nounwind {
 
 define <4 x i32> @test_v2f64_to_v4i32(<2 x double> %in) nounwind {
 ; CHECK: test_v2f64_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x double> %in to <4 x i32>
@@ -547,7 +547,7 @@ define <4 x i32> @test_v2f64_to_v4i32(<2 x double> %in) nounwind {
 
 define <4 x float> @test_v2f64_to_v4f32(<2 x double> %in) nounwind{
 ; CHECK: test_v2f64_to_v4f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x double> %in to <4 x float>
@@ -556,7 +556,7 @@ define <4 x float> @test_v2f64_to_v4f32(<2 x double> %in) nounwind{
 
 define <8 x i16> @test_v2f64_to_v8i16(<2 x double> %in) nounwind{
 ; CHECK: test_v2f64_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x double> %in to <8 x i16>
@@ -565,7 +565,7 @@ define <8 x i16> @test_v2f64_to_v8i16(<2 x double> %in) nounwind{
 
 define <16 x i8> @test_v2f64_to_v16i8(<2 x double> %in) nounwind{
 ; CHECK: test_v2f64_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: ret
 
   %val = bitcast <2 x double> %in to <16 x i8>
diff --git a/test/CodeGen/AArch64/neon-scalar-copy.ll b/test/CodeGen/AArch64/neon-scalar-copy.ll
index 3f770600ac59..2384e485fd73 100644
--- a/test/CodeGen/AArch64/neon-scalar-copy.ll
+++ b/test/CodeGen/AArch64/neon-scalar-copy.ll
@@ -79,8 +79,7 @@ define half @test_dup_hv8H_0(<8 x half> %v) #0 {
 
 define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 {
  ; CHECK-LABEL: test_vector_dup_bv16B:
- ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.b[14]
- ; CHECK-NEXT: fmov s0, [[W]]
+ ; CHECK-NEXT: dup v0.16b, v0.b[14]
  ; CHECK-NEXT: ret
  %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14> 
  ret <1 x i8> %shuffle.i
@@ -96,8 +95,7 @@ define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 {
 
 define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 {
  ; CHECK-LABEL: test_vector_dup_hv8H:
- ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.h[7]
- ; CHECK-NEXT: fmov s0, [[W]]
+ ; CHECK-NEXT:	dup v0.8h, v0.h[7]
  ; CHECK-NEXT: ret
  %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7> 
  ret <1 x i16> %shuffle.i
@@ -113,8 +111,7 @@ define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 {
 
 define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
  ; CHECK-LABEL: test_vector_dup_sv4S:
- ; CHECK-NEXT: mov  [[W:w[0-9]+]], v0.s[3]
- ; CHECK-NEXT: fmov s0, [[W]]
+ ; CHECK-NEXT: dup v0.4s, v0.s[3]
  ; CHECK-NEXT: ret
  %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3> 
  ret <1 x i32> %shuffle
@@ -138,7 +135,7 @@ define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 {
 
 define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
   ; CHECK-LABEL: test_vector_copy_dup_dv2D:
-  ; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+  ; CHECK-NEXT: dup v0.2d, v1.d[1]
   ; CHECK-NEXT: ret
   %vget_lane = extractelement <2 x i64> %c, i32 1
   %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
diff --git a/test/CodeGen/AArch64/nest-register.ll b/test/CodeGen/AArch64/nest-register.ll
index cc42913e10a6..b8651714be34 100644
--- a/test/CodeGen/AArch64/nest-register.ll
+++ b/test/CodeGen/AArch64/nest-register.ll
@@ -5,7 +5,7 @@
 
 define i8* @nest_receiver(i8* nest %arg) nounwind {
 ; CHECK-LABEL: nest_receiver:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
 ; CHECK-NEXT: mov x0, x18
 ; CHECK-NEXT: ret
 
diff --git a/test/CodeGen/AArch64/no-fp-asm-clobbers-crash.ll b/test/CodeGen/AArch64/no-fp-asm-clobbers-crash.ll
new file mode 100644
index 000000000000..5cd8dc57f9ad
--- /dev/null
+++ b/test/CodeGen/AArch64/no-fp-asm-clobbers-crash.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s | FileCheck %s
+;
+; Be sure that we ignore clobbers of unallocatable registers, rather than
+; crashing.
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64"
+
+; CHECK-LABEL: foo:
+; CHECK: ret
+define void @foo() #0 {
+entry:
+  call void asm sideeffect "", "~{v0}"()
+  call void asm sideeffect "", "~{s0}"()
+  ret void
+}
+
+attributes #0 = { nounwind "target-features"="-crypto,-fp-armv8,-neon" }
diff --git a/test/CodeGen/AArch64/phi-dbg.ll b/test/CodeGen/AArch64/phi-dbg.ll
index a1adf0f50d9b..80bc885afa5c 100644
--- a/test/CodeGen/AArch64/phi-dbg.ll
+++ b/test/CodeGen/AArch64/phi-dbg.ll
@@ -30,7 +30,7 @@ define i32 @func(i32) #0 !dbg !8 {
 ; CHECK: ldr     w[[REG:[0-9]+]], [sp, #8]
 ; CHECK-NEXT: .Ltmp
   call void @llvm.dbg.value(metadata i32 %.0, i64 0, metadata !15, metadata !13), !dbg !16
-; CHECK-NEXT:  //DEBUG_VALUE: func:c <- %W[[REG]]
+; CHECK-NEXT:  //DEBUG_VALUE: func:c <- %w[[REG]]
   %5 = add nsw i32 %.0, %0, !dbg !22
   call void @llvm.dbg.value(metadata i32 %5, i64 0, metadata !15, metadata !13), !dbg !16
   ret i32 %5, !dbg !23
diff --git a/test/CodeGen/AArch64/preferred-function-alignment.ll b/test/CodeGen/AArch64/preferred-function-alignment.ll
index 386a6ecccf54..4a0a5821edf7 100644
--- a/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ b/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -1,20 +1,20 @@
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=generic < %s | FileCheck --check-prefix=ALIGN2 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a35 < %s | FileCheck --check-prefix=ALIGN2 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a53 < %s | FileCheck --check-prefix=ALIGN2 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cyclone < %s | FileCheck --check-prefix=ALIGN2 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=falkor < %s | FileCheck --check-prefix=ALIGN2 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=kryo < %s | FileCheck --check-prefix=ALIGN2 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx < %s | FileCheck --check-prefix=ALIGN3 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt81 < %s | FileCheck --check-prefix=ALIGN3 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefix=ALIGN3 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefix=ALIGN3 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefix=ALIGN3 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 < %s | FileCheck --check-prefix=ALIGN4 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a72 < %s | FileCheck --check-prefix=ALIGN4 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a73 < %s | FileCheck --check-prefix=ALIGN4 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m1 < %s | FileCheck --check-prefix=ALIGN4 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m2 < %s | FileCheck --check-prefix=ALIGN4 %s
-; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefix=ALIGN4 %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=generic < %s | FileCheck --check-prefixes=ALIGN2,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a35 < %s | FileCheck --check-prefixes=ALIGN2,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cyclone < %s | FileCheck --check-prefixes=ALIGN2,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=falkor < %s | FileCheck --check-prefixes=ALIGN2,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=kryo < %s | FileCheck --check-prefixes=ALIGN2,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a53 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt81 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a72 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a73 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m1 < %s | FileCheck ---check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m2 < %s | FileCheck ---check-prefixes=ALIGN4,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck ---check-prefixes=ALIGN4,CHECK %s
 
 define void @test() {
   ret void
@@ -24,3 +24,10 @@ define void @test() {
 ; ALIGN2: .p2align 2
 ; ALIGN3: .p2align 3
 ; ALIGN4: .p2align 4
+
+define void @test_optsize() optsize {
+  ret void
+}
+
+; CHECK-LABEL: test_optsize
+; CHECK-NEXT: .p2align 2
diff --git a/test/CodeGen/AArch64/prologue-epilogue-remarks.mir b/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
new file mode 100644
index 000000000000..ed139875d26a
--- /dev/null
+++ b/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
@@ -0,0 +1,57 @@
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=prologepilog -pass-remarks-output=%t -pass-remarks-analysis=prologepilog -o /dev/null %s 2>&1
+# RUN: cat %t | FileCheck %s
+...
+---
+name:            fun0
+stack:
+  - { id: 0, type: default, offset: 0, size: 8, alignment: 4 }
+# CHECK: --- !Analysis
+# CHECK-NEXT: Pass:            prologepilog
+# CHECK-NEXT: Name:            StackSize
+# CHECK-NEXT: Function:        fun0
+# CHECK-NEXT: Args:
+# CHECK-NEXT:   - NumStackBytes:   '16'
+# CHECK-NEXT:   - String:          ' stack bytes in function'
+# CHECK-NEXT: ...
+constants:
+body:             |
+  bb.0:
+    RET_ReallyLR
+
+...
+---
+name:            fun1
+stack:
+  - { id: 0, type: default, offset: 0, size: 19, alignment: 4 }
+# CHECK: --- !Analysis
+# CHECK-NEXT: Pass:            prologepilog
+# CHECK-NEXT: Name:            StackSize
+# CHECK-NEXT: Function:        fun1
+# CHECK-NEXT: Args:
+# CHECK-NEXT:   - NumStackBytes:   '32'
+# CHECK-NEXT:   - String:          ' stack bytes in function'
+# CHECK-NEXT: ...
+constants:
+body:             |
+  bb.0:
+    RET_ReallyLR
+
+...
+---
+name:            fun2
+stack:
+  - { id: 0, type: default, offset: 0, size: 1024, alignment: 4 }
+# --- !Analysis
+# CHECK: Pass:            prologepilog
+# CHECK-NEXT: Name:            StackSize
+# CHECK-NEXT: Function:        fun2
+# CHECK-NEXT: Args:
+# CHECK-NEXT:   - NumStackBytes:   '1040'
+# CHECK-NEXT:   - String:          ' stack bytes in function'
+# CHECK-NEXT: ...
+constants:
+body:             |
+  bb.0:
+    RET_ReallyLR
+
+...
diff --git a/test/CodeGen/AArch64/recp-fastmath.ll b/test/CodeGen/AArch64/recp-fastmath.ll
index 38e0fb360e49..9f00621eff6b 100644
--- a/test/CodeGen/AArch64/recp-fastmath.ll
+++ b/test/CodeGen/AArch64/recp-fastmath.ll
@@ -5,7 +5,7 @@ define float @frecp0(float %x) #0 {
   ret float %div
 
 ; CHECK-LABEL: frecp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: fmov
 ; CHECK-NEXT: fdiv
 }
@@ -15,9 +15,11 @@ define float @frecp1(float %x) #1 {
   ret float %div
 
 ; CHECK-LABEL: frecp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frecpe [[R:s[0-7]]]
 ; CHECK-NEXT: frecps {{s[0-7](, s[0-7])?}}, [[R]]
+; CHECK: frecps {{s[0-7]}}, {{s[0-7]}}, {{s[0-7]}}
+; CHECK-NOT: frecps {{s[0-7]}}, {{s[0-7]}}, {{s[0-7]}}
 }
 
 define <2 x float> @f2recp0(<2 x float> %x) #0 {
@@ -25,7 +27,7 @@ define <2 x float> @f2recp0(<2 x float> %x) #0 {
   ret <2 x float> %div
 
 ; CHECK-LABEL: f2recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: fmov
 ; CHECK-NEXT: fdiv
 }
@@ -35,9 +37,11 @@ define <2 x float> @f2recp1(<2 x float> %x) #1 {
   ret <2 x float> %div
 
 ; CHECK-LABEL: f2recp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frecpe [[R:v[0-7]\.2s]]
 ; CHECK-NEXT: frecps {{v[0-7]\.2s(, v[0-7].2s)?}}, [[R]]
+; CHECK: frecps {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, {{v[0-7]\.2s}}
+; CHECK-NOT: frecps {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, {{v[0-7]\.2s}}
 }
 
 define <4 x float> @f4recp0(<4 x float> %x) #0 {
@@ -45,7 +49,7 @@ define <4 x float> @f4recp0(<4 x float> %x) #0 {
   ret <4 x float> %div
 
 ; CHECK-LABEL: f4recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: fmov
 ; CHECK-NEXT: fdiv
 }
@@ -55,9 +59,11 @@ define <4 x float> @f4recp1(<4 x float> %x) #1 {
   ret <4 x float> %div
 
 ; CHECK-LABEL: f4recp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frecpe [[R:v[0-7]\.4s]]
 ; CHECK-NEXT: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, [[R]]
+; CHECK: frecps {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK-NOT: frecps {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
 }
 
 define <8 x float> @f8recp0(<8 x float> %x) #0 {
@@ -65,7 +71,7 @@ define <8 x float> @f8recp0(<8 x float> %x) #0 {
   ret <8 x float> %div
 
 ; CHECK-LABEL: f8recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: fmov
 ; CHECK-NEXT: fdiv
 ; CHECK-NEXT: fdiv
@@ -76,11 +82,13 @@ define <8 x float> @f8recp1(<8 x float> %x) #1 {
   ret <8 x float> %div
 
 ; CHECK-LABEL: f8recp1:
-; CHECK-NEXT: BB#0
-; CHECK-NEXT: frecpe [[RA:v[0-7]\.4s]]
-; CHECK-NEXT: frecpe [[RB:v[0-7]\.4s]]
-; CHECK-NEXT: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, [[RA]]
-; CHECK: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, [[RB]]
+; CHECK-NEXT: %bb.0
+; CHECK-NEXT: frecpe [[R:v[0-7]\.4s]]
+; CHECK: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, [[R]]
+; CHECK: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, {{v[0-7]\.4s}}
+; CHECK: frecps {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK: frecps {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK-NOT: frecps {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
 }
 
 define double @drecp0(double %x) #0 {
@@ -88,7 +96,7 @@ define double @drecp0(double %x) #0 {
   ret double %div
 
 ; CHECK-LABEL: drecp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: fmov
 ; CHECK-NEXT: fdiv
 }
@@ -98,9 +106,12 @@ define double @drecp1(double %x) #1 {
   ret double %div
 
 ; CHECK-LABEL: drecp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frecpe [[R:d[0-7]]]
 ; CHECK-NEXT: frecps {{d[0-7](, d[0-7])?}}, [[R]]
+; CHECK: frecps {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
+; CHECK: frecps {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
+; CHECK-NOT: frecps {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
 }
 
 define <2 x double> @d2recp0(<2 x double> %x) #0 {
@@ -108,7 +119,7 @@ define <2 x double> @d2recp0(<2 x double> %x) #0 {
   ret <2 x double> %div
 
 ; CHECK-LABEL: d2recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: fmov
 ; CHECK-NEXT: fdiv
 }
@@ -118,9 +129,12 @@ define <2 x double> @d2recp1(<2 x double> %x) #1 {
   ret <2 x double> %div
 
 ; CHECK-LABEL: d2recp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frecpe [[R:v[0-7]\.2d]]
 ; CHECK-NEXT: frecps {{v[0-7]\.2d(, v[0-7].2d)?}}, [[R]]
+; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
 }
 
 define <4 x double> @d4recp0(<4 x double> %x) #0 {
@@ -128,7 +142,7 @@ define <4 x double> @d4recp0(<4 x double> %x) #0 {
   ret <4 x double> %div
 
 ; CHECK-LABEL: d4recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: fmov
 ; CHECK-NEXT: fdiv
 ; CHECK-NEXT: fdiv
@@ -139,11 +153,15 @@ define <4 x double> @d4recp1(<4 x double> %x) #1 {
   ret <4 x double> %div
 
 ; CHECK-LABEL: d4recp1:
-; CHECK-NEXT: BB#0
-; CHECK-NEXT: frecpe [[RA:v[0-7]\.2d]]
-; CHECK-NEXT: frecpe [[RB:v[0-7]\.2d]]
-; CHECK-NEXT: frecps {{v[0-7]\.2d(, v[0-7].2d)?}}, [[RA]]
-; CHECK: frecps {{v[0-7]\.2d(, v[0-7].2d)?}}, [[RB]]
+; CHECK-NEXT: %bb.0
+; CHECK-NEXT: frecpe [[R:v[0-7]\.2d]]
+; CHECK: frecps {{v[0-7]\.2d(, v[0-7].2d)?}}, [[R]]
+; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
 }
 
 attributes #0 = { nounwind "unsafe-fp-math"="true" }
diff --git a/test/CodeGen/AArch64/regcoal-physreg.mir b/test/CodeGen/AArch64/regcoal-physreg.mir
index f88b7482acac..095e8a4973ce 100644
--- a/test/CodeGen/AArch64/regcoal-physreg.mir
+++ b/test/CodeGen/AArch64/regcoal-physreg.mir
@@ -13,7 +13,7 @@ name: func0
 body: |
   bb.0:
     ; We usually should not coalesce copies from allocatable physregs.
-    ; CHECK: %0 = COPY %w7
+    ; CHECK: %0:gpr32 = COPY %w7
     ; CHECK: STRWui %0, %x1, 0
     %0 : gpr32 = COPY %w7
     STRWui %0, %x1, 0
@@ -26,7 +26,7 @@ body: |
 
     ; It is not fine to coalesce copies from reserved physregs when they are
     ; clobbered.
-    ; CHECK: %2 = COPY %fp
+    ; CHECK: %2:gpr64 = COPY %fp
     ; CHECK: STRXui %2, %x1, 0
     %2 : gpr64 = COPY %fp
     %fp = SUBXri %fp, 4, 0
@@ -56,14 +56,14 @@ body: |
     ; Only coalesce when the source register is reserved as a whole (this is
     ; a limitation of the current code which cannot update liveness information
     ; of the non-reserved part).
-    ; CHECK: %6 = COPY %x28_fp
+    ; CHECK: %6:xseqpairsclass = COPY %x28_fp
     ; CHECK: HINT 0, implicit %6
     %6 : xseqpairsclass = COPY %x28_fp
     HINT 0, implicit %6
 
     ; It is not fine to coalesce copies from reserved physregs when they are
     ; clobbered by the regmask on a call.
-    ; CHECK: %7 = COPY %x18
+    ; CHECK: %7:gpr64 = COPY %x18
     ; CHECK: BL @f2, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
     ; CHECK: STRXui %7, %x1, 0
 
@@ -80,7 +80,7 @@ body: |
 
     ; Cannot coalesce when there are reads of the physreg.
     ; CHECK-NOT: %fp = SUBXri %fp, 8, 0
-    ; CHECK: %9 = SUBXri %fp, 8, 0
+    ; CHECK: %9:gpr64sp = SUBXri %fp, 8, 0
     ; CHECK: STRXui %fp, %fp, 0
     ; CHECK: %fp = COPY %9
     %9 : gpr64sp = SUBXri %fp, 8, 0
@@ -96,7 +96,7 @@ body: |
     ; Cannot coalesce physreg because we have reads on other CFG paths (we
     ; currently abort for any control flow)
     ; CHECK-NOT: %fp = SUBXri
-    ; CHECK: %0 = SUBXri %fp, 12, 0
+    ; CHECK: %0:gpr64sp = SUBXri %fp, 12, 0
     ; CHECK: CBZX undef %x0, %bb.1
     ; CHECK: B %bb.2
     %0 : gpr64sp = SUBXri %fp, 12, 0
diff --git a/test/CodeGen/AArch64/remat.ll b/test/CodeGen/AArch64/remat.ll
index 80a054beb2a5..9524154c3e0d 100644
--- a/test/CodeGen/AArch64/remat.ll
+++ b/test/CodeGen/AArch64/remat.ll
@@ -1,12 +1,15 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a75 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m2 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=falkor -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=saphira -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
diff --git a/test/CodeGen/AArch64/scheduledag-constreg.mir b/test/CodeGen/AArch64/scheduledag-constreg.mir
index 6b83dc715e0a..013f59f52a9c 100644
--- a/test/CodeGen/AArch64/scheduledag-constreg.mir
+++ b/test/CodeGen/AArch64/scheduledag-constreg.mir
@@ -7,16 +7,16 @@
 # Check that the instructions are not dependent on each other, even though
 # they all read/write to the zero register.
 # CHECK-LABEL: MI Scheduling
-# CHECK: SU(0): %WZR<def,dead> = SUBSWri %W1, 0, 0, %NZCV<imp-def,dead>
+# CHECK: SU(0): dead %wzr = SUBSWri %w1, 0, 0, implicit-def dead %nzcv
 # CHECK: # succs left : 0
 # CHECK-NOT: Successors:
-# CHECK: SU(1): %W2<def> = COPY %WZR
+# CHECK: SU(1): %w2 = COPY %wzr
 # CHECK: # succs left : 0
 # CHECK-NOT: Successors:
-# CHECK: SU(2): %WZR<def,dead> = SUBSWri %W3, 0, 0, %NZCV<imp-def,dead>
+# CHECK: SU(2): dead %wzr = SUBSWri %w3, 0, 0, implicit-def dead %nzcv
 # CHECK: # succs left : 0
 # CHECK-NOT: Successors:
-# CHECK: SU(3): %W4<def> = COPY %WZR
+# CHECK: SU(3): %w4 = COPY %wzr
 # CHECK: # succs left : 0
 # CHECK-NOT: Successors:
 name: func
diff --git a/test/CodeGen/AArch64/selectcc-to-shiftand.ll b/test/CodeGen/AArch64/selectcc-to-shiftand.ll
index 0d89cdedfa8a..99190633547c 100644
--- a/test/CodeGen/AArch64/selectcc-to-shiftand.ll
+++ b/test/CodeGen/AArch64/selectcc-to-shiftand.ll
@@ -4,7 +4,7 @@
 
 define i32 @neg_sel_constants(i32 %a) {
 ; CHECK-LABEL: neg_sel_constants:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #5
 ; CHECK-NEXT:    and w0, w8, w0, asr #31
 ; CHECK-NEXT:    ret
@@ -18,7 +18,7 @@ define i32 @neg_sel_constants(i32 %a) {
 
 define i32 @neg_sel_special_constant(i32 %a) {
 ; CHECK-LABEL: neg_sel_special_constant:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    lsr w8, w0, #22
 ; CHECK-NEXT:    and w0, w8, #0x200
 ; CHECK-NEXT:    ret
@@ -32,7 +32,7 @@ define i32 @neg_sel_special_constant(i32 %a) {
 
 define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) {
 ; CHECK-LABEL: neg_sel_variable_and_zero:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w0, w1, w0, asr #31
 ; CHECK-NEXT:    ret
 ;
@@ -45,7 +45,7 @@ define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) {
 
 define i32 @not_pos_sel_same_variable(i32 %a) {
 ; CHECK-LABEL: not_pos_sel_same_variable:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w0, w0, w0, asr #31
 ; CHECK-NEXT:    ret
 ;
@@ -60,7 +60,7 @@ define i32 @not_pos_sel_same_variable(i32 %a) {
 
 define i32 @pos_sel_constants(i32 %a) {
 ; CHECK-LABEL: pos_sel_constants:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #5
 ; CHECK-NEXT:    bic w0, w8, w0, asr #31
 ; CHECK-NEXT:    ret
@@ -74,7 +74,7 @@ define i32 @pos_sel_constants(i32 %a) {
 
 define i32 @pos_sel_special_constant(i32 %a) {
 ; CHECK-LABEL: pos_sel_special_constant:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    orr w8, wzr, #0x200
 ; CHECK-NEXT:    bic w0, w8, w0, lsr #22
 ; CHECK-NEXT:    ret
@@ -88,7 +88,7 @@ define i32 @pos_sel_special_constant(i32 %a) {
 
 define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) {
 ; CHECK-LABEL: pos_sel_variable_and_zero:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    bic w0, w1, w0, asr #31
 ; CHECK-NEXT:    ret
 ;
@@ -101,7 +101,7 @@ define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) {
 
 define i32 @not_neg_sel_same_variable(i32 %a) {
 ; CHECK-LABEL: not_neg_sel_same_variable:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    bic w0, w0, w0, asr #31
 ; CHECK-NEXT:    ret
 ;
@@ -115,7 +115,7 @@ define i32 @not_neg_sel_same_variable(i32 %a) {
 ; ret = (x-y) > 0 ? x-y : 0
 define i32 @PR31175(i32 %x, i32 %y) {
 ; CHECK-LABEL: PR31175:
-; CHECK:       // BB#0:
+; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub w8, w0, w1
 ; CHECK-NEXT:    bic w0, w8, w8, asr #31
 ; CHECK-NEXT:    ret
diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll
index 9a44b43d14e6..be59f27fa858 100644
--- a/test/CodeGen/AArch64/sibling-call.ll
+++ b/test/CodeGen/AArch64/sibling-call.ll
@@ -6,7 +6,7 @@ declare void @callee_stack16([8 x i32], i64, i64)
 
 define void @caller_to0_from0() nounwind {
 ; CHECK-LABEL: caller_to0_from0:
-; CHECK-NEXT: // BB
+; CHECK-NEXT: // %bb.
   tail call void @callee_stack0()
   ret void
 ; CHECK-NEXT: b callee_stack0
@@ -14,7 +14,7 @@ define void @caller_to0_from0() nounwind {
 
 define void @caller_to0_from8([8 x i32], i64) nounwind{
 ; CHECK-LABEL: caller_to0_from8:
-; CHECK-NEXT: // BB
+; CHECK-NEXT: // %bb.
 
   tail call void @callee_stack0()
   ret void
diff --git a/test/CodeGen/AArch64/spill-undef.mir b/test/CodeGen/AArch64/spill-undef.mir
index 4294df286bd3..c4f589b5cc49 100644
--- a/test/CodeGen/AArch64/spill-undef.mir
+++ b/test/CodeGen/AArch64/spill-undef.mir
@@ -5,19 +5,19 @@
 --- |
   ; ModuleID = 'stuff.ll'
   target triple = "aarch64--"
-  
+
   @g = external global i32
-  
+
   define void @foobar() {
     ret void
   }
-  
+
 ...
 ---
 name:            foobar
 alignment:       2
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr32 }
   - { id: 1, class: gpr32 }
   - { id: 2, class: gpr32all }
@@ -37,25 +37,25 @@ body:             |
     ; But on that path, we don't care about its value.
     ; Emit a simple KILL instruction instead of an
     ; actual spill.
-    ; CHECK: [[UNDEF:%[0-9]+]] = IMPLICIT_DEF
+    ; CHECK: [[UNDEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
     ; CHECK-NEXT: KILL [[UNDEF]]
     %8 = IMPLICIT_DEF
     ; %9 us going to be spilled.
     ; But it is only partially undef.
     ; Make sure we spill it properly
-    ; CHECK: [[NINE:%[0-9]+]] = COPY %x0
-    ; CHECK: [[NINE]].sub_32 = IMPLICIT_DEF
+    ; CHECK: [[NINE:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[NINE]].sub_32:gpr64 = IMPLICIT_DEF
     ; CHECK-NEXT: STRXui [[NINE]]
     %9 = COPY %x0
     %9.sub_32 = IMPLICIT_DEF
     CBNZW %wzr, %bb.2
     B %bb.1
-  
+
   bb.1:
     %4 = ADRP target-flags(aarch64-page) @g
     %8 = LDRWui %4, target-flags(aarch64-pageoff, aarch64-nc) @g :: (volatile dereferenceable load 4 from @g)
     INLINEASM $nop, 1, 12, implicit-def dead early-clobber %x0, 12, implicit-def dead early-clobber %x1, 12, implicit-def dead early-clobber %x2, 12, implicit-def dead early-clobber %x3, 12, implicit-def dead early-clobber %x4, 12, implicit-def dead early-clobber %x5, 12, implicit-def dead early-clobber %x6, 12, implicit-def dead early-clobber %x7, 12, implicit-def dead early-clobber %x8, 12, implicit-def dead early-clobber %x9, 12, implicit-def dead early-clobber %x10, 12, implicit-def dead early-clobber %x11, 12, implicit-def dead early-clobber %x12, 12, implicit-def dead early-clobber %x13, 12, implicit-def dead early-clobber %x14, 12, implicit-def dead early-clobber %x15, 12, implicit-def dead early-clobber %x16, 12, implicit-def dead early-clobber %x17, 12, implicit-def dead early-clobber %x18, 12, implicit-def dead early-clobber %x19, 12, implicit-def dead early-clobber %x20, 12, implicit-def dead early-clobber %x21, 12, implicit-def dead early-clobber %x22, 12, implicit-def dead early-clobber %x23, 12, implicit-def dead early-clobber %x24, 12, implicit-def dead early-clobber %x25, 12, implicit-def dead early-clobber %x26, 12, implicit-def dead early-clobber %x27, 12, implicit-def dead early-clobber %x28, 12, implicit-def dead early-clobber %fp, 12, implicit-def dead early-clobber %lr
-  
+
   bb.2:
     INLINEASM $nop, 1, 12, implicit-def dead early-clobber %x0, 12, implicit-def dead early-clobber %x1, 12, implicit-def dead early-clobber %x2, 12, implicit-def dead early-clobber %x3, 12, implicit-def dead early-clobber %x4, 12, implicit-def dead early-clobber %x5, 12, implicit-def dead early-clobber %x6, 12, implicit-def dead early-clobber %x7, 12, implicit-def dead early-clobber %x8, 12, implicit-def dead early-clobber %x9, 12, implicit-def dead early-clobber %x10, 12, implicit-def dead early-clobber %x11, 12, implicit-def dead early-clobber %x12, 12, implicit-def dead early-clobber %x13, 12, implicit-def dead early-clobber %x14, 12, implicit-def dead early-clobber %x15, 12, implicit-def dead early-clobber %x16, 12, implicit-def dead early-clobber %x17, 12, implicit-def dead early-clobber %x18, 12, implicit-def dead early-clobber %x19, 12, implicit-def dead early-clobber %x20, 12, implicit-def dead early-clobber %x21, 12, implicit-def dead early-clobber %x22, 12, implicit-def dead early-clobber %x23, 12, implicit-def dead early-clobber %x24, 12, implicit-def dead early-clobber %x25, 12, implicit-def dead early-clobber %x26, 12, implicit-def dead early-clobber %x27, 12, implicit-def dead early-clobber %x28, 12, implicit-def dead early-clobber %fp, 12, implicit-def dead early-clobber %lr
     %6 = ADRP target-flags(aarch64-page) @g
diff --git a/test/CodeGen/AArch64/sqrt-fastmath.ll b/test/CodeGen/AArch64/sqrt-fastmath.ll
index 079562c05819..ade9e3d8df32 100644
--- a/test/CodeGen/AArch64/sqrt-fastmath.ll
+++ b/test/CodeGen/AArch64/sqrt-fastmath.ll
@@ -14,15 +14,17 @@ define float @fsqrt(float %a) #0 {
   ret float %1
 
 ; FAULT-LABEL: fsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: fsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:s[0-7]]]
 ; CHECK-NEXT: fmul [[RB:s[0-7]]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{s[0-7](, s[0-7])?}}, [[RB]]
-; CHECK: fcmp s0, #0
+; CHECK: frsqrts {{s[0-7]}}, {{s[0-7]}}, {{s[0-7]}}
+; CHECK-NOT: frsqrts {{s[0-7]}}, {{s[0-7]}}, {{s[0-7]}}
+; CHECK: fcmp {{s[0-7]}}, #0
 }
 
 define <2 x float> @f2sqrt(<2 x float> %a) #0 {
@@ -30,15 +32,17 @@ define <2 x float> @f2sqrt(<2 x float> %a) #0 {
   ret <2 x float> %1
 
 ; FAULT-LABEL: f2sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: f2sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2s]]
 ; CHECK-NEXT: fmul [[RB:v[0-7]\.2s]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{v[0-7]\.2s(, v[0-7]\.2s)?}}, [[RB]]
-; CHECK: fcmeq {{v[0-7]\.2s, v0\.2s}}, #0
+; CHECK: frsqrts {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, {{v[0-7]\.2s}}
+; CHECK-NOT: frsqrts {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, {{v[0-7]\.2s}}
+; CHECK: fcmeq {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, #0
 }
 
 define <4 x float> @f4sqrt(<4 x float> %a) #0 {
@@ -46,15 +50,17 @@ define <4 x float> @f4sqrt(<4 x float> %a) #0 {
   ret <4 x float> %1
 
 ; FAULT-LABEL: f4sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: f4sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]]
 ; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
-; CHECK: fcmeq {{v[0-7]\.4s, v0\.4s}}, #0
+; CHECK: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK-NOT: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK: fcmeq {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, #0
 }
 
 define <8 x float> @f8sqrt(<8 x float> %a) #0 {
@@ -62,16 +68,23 @@ define <8 x float> @f8sqrt(<8 x float> %a) #0 {
   ret <8 x float> %1
 
 ; FAULT-LABEL: f8sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: f8sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]]
-; CHECK: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
-; CHECK: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
-; CHECK: fcmeq {{v[0-7]\.4s, v[0-1]\.4s}}, #0
+; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
+; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
+; CHECK: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK: fcmeq {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, #0
+; CHECK: frsqrte [[RC:v[0-7]\.4s]]
+; CHECK-NEXT: fmul [[RD:v[0-7]\.4s]], [[RC]], [[RC]]
+; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RD]]
+; CHECK: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK-NOT: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK: fcmeq {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, #0
 }
 
 define double @dsqrt(double %a) #0 {
@@ -79,15 +92,18 @@ define double @dsqrt(double %a) #0 {
   ret double %1
 
 ; FAULT-LABEL: dsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: dsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:d[0-7]]]
 ; CHECK-NEXT: fmul [[RB:d[0-7]]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{d[0-7](, d[0-7])?}}, [[RB]]
-; CHECK: fcmp d0, #0
+; CHECK: frsqrts {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
+; CHECK: frsqrts {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
+; CHECK-NOT: frsqrts {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
+; CHECK: fcmp {{d[0-7]}}, #0
 }
 
 define <2 x double> @d2sqrt(<2 x double> %a) #0 {
@@ -95,15 +111,18 @@ define <2 x double> @d2sqrt(<2 x double> %a) #0 {
   ret <2 x double> %1
 
 ; FAULT-LABEL: d2sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: d2sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]]
 ; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
-; CHECK: fcmeq {{v[0-7]\.2d, v0\.2d}}, #0
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: fcmeq {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, #0
 }
 
 define <4 x double> @d4sqrt(<4 x double> %a) #0 {
@@ -111,16 +130,26 @@ define <4 x double> @d4sqrt(<4 x double> %a) #0 {
   ret <4 x double> %1
 
 ; FAULT-LABEL: d4sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: d4sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]]
-; CHECK: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
-; CHECK: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
-; CHECK: fcmeq {{v[0-7]\.2d, v[0-1]\.2d}}, #0
+; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
+; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: fcmeq {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, #0
+; CHECK: frsqrte [[RC:v[0-7]\.2d]]
+; CHECK-NEXT: fmul [[RD:v[0-7]\.2d]], [[RC]], [[RC]]
+; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RD]]
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: fcmeq {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, #0
 }
 
 define float @frsqrt(float %a) #0 {
@@ -129,14 +158,16 @@ define float @frsqrt(float %a) #0 {
   ret float %2
 
 ; FAULT-LABEL: frsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: frsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:s[0-7]]]
 ; CHECK-NEXT: fmul [[RB:s[0-7]]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{s[0-7](, s[0-7])?}}, [[RB]]
+; CHECK: frsqrts {{s[0-7]}}, {{s[0-7]}}, {{s[0-7]}}
+; CHECK-NOT: frsqrts {{s[0-7]}}, {{s[0-7]}}, {{s[0-7]}}
 ; CHECK-NOT: fcmp {{s[0-7]}}, #0
 }
 
@@ -146,15 +177,17 @@ define <2 x float> @f2rsqrt(<2 x float> %a) #0 {
   ret <2 x float> %2
 
 ; FAULT-LABEL: f2rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: f2rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2s]]
 ; CHECK-NEXT: fmul [[RB:v[0-7]\.2s]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{v[0-7]\.2s(, v[0-7]\.2s)?}}, [[RB]]
-; CHECK-NOT: fcmeq {{v[0-7]\.2s, v0\.2s}}, #0
+; CHECK: frsqrts {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, {{v[0-7]\.2s}}
+; CHECK-NOT: frsqrts {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, {{v[0-7]\.2s}}
+; CHECK-NOT: fcmeq {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, #0
 }
 
 define <4 x float> @f4rsqrt(<4 x float> %a) #0 {
@@ -163,15 +196,17 @@ define <4 x float> @f4rsqrt(<4 x float> %a) #0 {
   ret <4 x float> %2
 
 ; FAULT-LABEL: f4rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: f4rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]]
 ; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
-; CHECK-NOT: fcmeq {{v[0-7]\.4s, v0\.4s}}, #0
+; CHECK: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK-NOT: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK-NOT: fcmeq {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, #0
 }
 
 define <8 x float> @f8rsqrt(<8 x float> %a) #0 {
@@ -180,16 +215,20 @@ define <8 x float> @f8rsqrt(<8 x float> %a) #0 {
   ret <8 x float> %2
 
 ; FAULT-LABEL: f8rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: f8rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]]
 ; CHECK: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
 ; CHECK: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
-; CHECK-NOT: fcmeq {{v[0-7]\.4s, v0\.4s}}, #0
+; CHECK: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK-NOT: frsqrts {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
+; CHECK-NOT: fcmeq {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, #0
 }
 
 define double @drsqrt(double %a) #0 {
@@ -198,14 +237,17 @@ define double @drsqrt(double %a) #0 {
   ret double %2
 
 ; FAULT-LABEL: drsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: drsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:d[0-7]]]
 ; CHECK-NEXT: fmul [[RB:d[0-7]]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{d[0-7](, d[0-7])?}}, [[RB]]
+; CHECK: frsqrts {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
+; CHECK: frsqrts {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
+; CHECK-NOT: frsqrts {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
 ; CHECK-NOT: fcmp d0, #0
 }
 
@@ -215,15 +257,18 @@ define <2 x double> @d2rsqrt(<2 x double> %a) #0 {
   ret <2 x double> %2
 
 ; FAULT-LABEL: d2rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: d2rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]]
 ; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
 ; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
-; CHECK-NOT: fcmeq {{v[0-7]\.2d, v0\.2d}}, #0
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: fcmeq {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, #0
 }
 
 define <4 x double> @d4rsqrt(<4 x double> %a) #0 {
@@ -232,16 +277,22 @@ define <4 x double> @d4rsqrt(<4 x double> %a) #0 {
   ret <4 x double> %2
 
 ; FAULT-LABEL: d4rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
 ; FAULT-NEXT: fsqrt
 ; FAULT-NEXT: fsqrt
 
 ; CHECK-LABEL: d4rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]]
 ; CHECK: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
 ; CHECK: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
-; CHECK-NOT: fcmeq {{v[0-7]\.2d, v0\.2d}}, #0
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: frsqrts {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
+; CHECK-NOT: fcmeq {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, #0
 }
 
 attributes #0 = { nounwind "unsafe-fp-math"="true" }
diff --git a/test/CodeGen/AArch64/strqro.ll b/test/CodeGen/AArch64/strqro.ll
new file mode 100644
index 000000000000..218248d54f85
--- /dev/null
+++ b/test/CodeGen/AArch64/strqro.ll
@@ -0,0 +1,47 @@
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-STRQRO %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mcpu=falkor | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NOSTRQRO %s
+
+; CHECK-LABEL: strqrox:
+; CHECK-STRQRO: str q{{[0-9]+}}, [x{{[0-9]+}}, x
+; CHECK-NOSTRQRO-NOT: str q{{[0-9]+}}, [x{{[0-9]+}}, x
+define void @strqrox(fp128 %val64, i64 %base, i64 %offset) {
+  %addrint = add i64 %base, %offset
+  %addr = inttoptr i64 %addrint to fp128*
+  store volatile fp128 %val64, fp128* %addr
+  ret void
+}
+
+; Check that STRQro is generated for both cases if we're optimizing for code size.
+; CHECK-LABEL: strqrox_optsize:
+; CHECK-STRQRO: str q{{[0-9]+}}, [x{{[0-9]+}}, x
+; CHECK-NOSTRQRO: str q{{[0-9]+}}, [x{{[0-9]+}}, x
+define void @strqrox_optsize(fp128 %val64, i64 %base, i64 %offset) minsize {
+  %addrint = add i64 %base, %offset
+  %addr = inttoptr i64 %addrint to fp128*
+  store volatile fp128 %val64, fp128* %addr
+  ret void
+}
+
+; CHECK-LABEL: strqrow:
+; CHECK-STRQRO: str q{{[0-9]+}}, [x{{[0-9]+}}, w
+; CHECK-NOSTRQRO-NOT: str q{{[0-9]+}}, [x{{[0-9]+}}, w
+define void @strqrow(fp128 %val64, i64 %base, i32 %offset) {
+  %offset64 = zext i32 %offset to i64
+  %addrint = add i64 %base, %offset64
+  %addr = inttoptr i64 %addrint to fp128*
+  store volatile fp128 %val64, fp128* %addr
+  ret void
+}
+
+; Check that STRQro is generated for both cases if we're optimizing for code size.
+; CHECK-LABEL: strqrow_optsize:
+; CHECK-STRQRO: str q{{[0-9]+}}, [x{{[0-9]+}}, w
+; CHECK-NOSTRQRO: str q{{[0-9]+}}, [x{{[0-9]+}}, w
+define void @strqrow_optsize(fp128 %val64, i64 %base, i32 %offset) minsize {
+  %offset64 = zext i32 %offset to i64
+  %addrint = add i64 %base, %offset64
+  %addr = inttoptr i64 %addrint to fp128*
+  store volatile fp128 %val64, fp128* %addr
+  ret void
+}
+
diff --git a/test/CodeGen/AArch64/swift-error.ll b/test/CodeGen/AArch64/swift-error.ll
new file mode 100644
index 000000000000..79a31c19be1c
--- /dev/null
+++ b/test/CodeGen/AArch64/swift-error.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple aarch64-unknown-linux-gnu -filetype asm -o - %s | FileCheck %s
+
+%swift.error = type opaque
+
+declare swiftcc void @f(%swift.error** swifterror)
+
+define swiftcc void @g(i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %swift.error** swifterror %error) {
+entry:
+  call swiftcc void @f(%swift.error** nonnull nocapture swifterror %error)
+  ret void
+}
+
+; CHEECK-LABEL: g
+; CHECK: str x30, [sp, #-16]!
+; CHECK: bl f
+; CHECK: ldr x30, [sp], #16
+; CHECK: ret
+
diff --git a/test/CodeGen/AArch64/tail-call.ll b/test/CodeGen/AArch64/tail-call.ll
index fa5d8b943b6b..ab63413bd3f1 100644
--- a/test/CodeGen/AArch64/tail-call.ll
+++ b/test/CodeGen/AArch64/tail-call.ll
@@ -7,7 +7,7 @@ declare extern_weak fastcc void @callee_weak()
 
 define fastcc void @caller_to0_from0() nounwind {
 ; CHECK-LABEL: caller_to0_from0:
-; CHECK-NEXT: // BB
+; CHECK-NEXT: // %bb.
 
   tail call fastcc void @callee_stack0()
   ret void
diff --git a/test/CodeGen/AArch64/tailcall-explicit-sret.ll b/test/CodeGen/AArch64/tailcall-explicit-sret.ll
index c15793361896..b60958b5a25d 100644
--- a/test/CodeGen/AArch64/tailcall-explicit-sret.ll
+++ b/test/CodeGen/AArch64/tailcall-explicit-sret.ll
@@ -35,7 +35,7 @@ define void @test_tailcall_explicit_sret_alloca_unused() #0 {
 }
 
 ; CHECK-LABEL: _test_tailcall_explicit_sret_alloca_dummyusers:
-; CHECK: ldr [[PTRLOAD1:x[0-9]+]], [x0]
+; CHECK: ldr [[PTRLOAD1:q[0-9]+]], [x0]
 ; CHECK: str [[PTRLOAD1]], [sp]
 ; CHECK: mov  x8, sp
 ; CHECK-NEXT: bl _test_explicit_sret
@@ -64,8 +64,8 @@ define void @test_tailcall_explicit_sret_gep(i1024* %ptr) #0 {
 ; CHECK: mov  x[[CALLERX8NUM:[0-9]+]], x8
 ; CHECK: mov  x8, sp
 ; CHECK-NEXT: bl _test_explicit_sret
-; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp]
-; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]]
+; CHECK-NEXT: ldr [[CALLERSRET1:q[0-9]+]], [sp]
+; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
 ; CHECK: ret
 define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 {
   %l = alloca i1024, align 8
@@ -79,8 +79,8 @@ define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 {
 ; CHECK-DAG: mov  [[FPTR:x[0-9]+]], x0
 ; CHECK: mov  x0, sp
 ; CHECK-NEXT: blr [[FPTR]]
-; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp]
-; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]]
+; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp]
+; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
 ; CHECK: ret
 define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, void (i1024*)* %f) #0 {
   %l = alloca i1024, align 8
@@ -94,8 +94,8 @@ define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, v
 ; CHECK: mov  x[[CALLERX8NUM:[0-9]+]], x8
 ; CHECK: mov  x8, sp
 ; CHECK-NEXT: blr x0
-; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp]
-; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]]
+; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp]
+; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
 ; CHECK: ret
 define void @test_indirect_tailcall_explicit_sret_(i1024* sret %arg, i1024 ()* %f) #0 {
   %ret = tail call i1024 %f()
diff --git a/test/CodeGen/AArch64/tailcall-implicit-sret.ll b/test/CodeGen/AArch64/tailcall-implicit-sret.ll
index 10c4ba4c31d6..f449a7e06588 100644
--- a/test/CodeGen/AArch64/tailcall-implicit-sret.ll
+++ b/test/CodeGen/AArch64/tailcall-implicit-sret.ll
@@ -11,8 +11,8 @@ declare i1024 @test_sret() #0
 ; CHECK: mov  x[[CALLERX8NUM:[0-9]+]], x8
 ; CHECK: mov  x8, sp
 ; CHECK-NEXT: bl _test_sret
-; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp]
-; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]]
+; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp]
+; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
 ; CHECK: ret
 define i1024 @test_call_sret() #0 {
   %a = call i1024 @test_sret()
@@ -23,8 +23,8 @@ define i1024 @test_call_sret() #0 {
 ; CHECK: mov  x[[CALLERX8NUM:[0-9]+]], x8
 ; CHECK: mov  x8, sp
 ; CHECK-NEXT: bl _test_sret
-; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp]
-; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]]
+; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp]
+; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
 ; CHECK: ret
 define i1024 @test_tailcall_sret() #0 {
   %a = tail call i1024 @test_sret()
@@ -35,8 +35,8 @@ define i1024 @test_tailcall_sret() #0 {
 ; CHECK: mov  x[[CALLERX8NUM:[0-9]+]], x8
 ; CHECK: mov  x8, sp
 ; CHECK-NEXT: blr x0
-; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp]
-; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]]
+; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp]
+; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
 ; CHECK: ret
 define i1024 @test_indirect_tailcall_sret(i1024 ()* %f) #0 {
   %a = tail call i1024 %f()
diff --git a/test/CodeGen/AArch64/tailcall_misched_graph.ll b/test/CodeGen/AArch64/tailcall_misched_graph.ll
index 7e76dac214a1..b926594e4504 100644
--- a/test/CodeGen/AArch64/tailcall_misched_graph.ll
+++ b/test/CodeGen/AArch64/tailcall_misched_graph.ll
@@ -26,19 +26,19 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*,
 ; CHECK:  fi#-2: {{.*}} fixed, at location [SP+8]
 ; CHECK:  fi#-1: {{.*}} fixed, at location [SP]
 
-; CHECK:  [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
-; CHECK:  [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
-; CHECK:  STRXui %vreg{{.*}}, <fi#-4>
-; CHECK:  STRXui [[VRB]], <fi#-3>
+; CHECK:  [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
+; CHECK:  [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
+; CHECK:  STRXui %{{.*}}, %fixed-stack.0
+; CHECK:  STRXui [[VRB]], %fixed-stack.1
 
 ; Make sure that there is an dependence edge between fi#-2 and fi#-4.
 ; Without this edge the scheduler would be free to move the store accross the load.
 
-; CHECK: SU({{.*}}):   [[VRB]]<def> = LDRXui <fi#-2>
+; CHECK: SU({{.*}}):   [[VRB]]:gpr64 = LDRXui %fixed-stack.2
 ; CHECK-NOT: SU
 ; CHECK:  Successors:
 ; CHECK:   SU([[DEPSTOREB:.*]]): Ord  Latency=0
 ; CHECK:   SU([[DEPSTOREA:.*]]): Ord  Latency=0
 
-; CHECK: SU([[DEPSTOREA]]):   STRXui %vreg{{.*}}, <fi#-4>
-; CHECK: SU([[DEPSTOREB]]):   STRXui %vreg{{.*}}, <fi#-3>
+; CHECK: SU([[DEPSTOREA]]):   STRXui %{{.*}}, %fixed-stack.0
+; CHECK: SU([[DEPSTOREB]]):   STRXui %{{.*}}, %fixed-stack.1
diff --git a/test/CodeGen/AArch64/vector-fcopysign.ll b/test/CodeGen/AArch64/vector-fcopysign.ll
index 47d75d5ecc61..9e9037c0d09f 100644
--- a/test/CodeGen/AArch64/vector-fcopysign.ll
+++ b/test/CodeGen/AArch64/vector-fcopysign.ll
@@ -106,10 +106,10 @@ define <4 x float> @test_copysign_v4f32_v4f64(<4 x float> %a, <4 x double> %b) #
 ; CHECK-NEXT:    bit.16b v3, v1, v4
 ; CHECK-NEXT:    mov d1, v2[1]
 ; CHECK-NEXT:    fcvt s1, d1
-; CHECK-NEXT:    ins.s v0[1], v3[0]
-; CHECK-NEXT:    ins.s v0[2], v6[0]
+; CHECK-NEXT:    mov.s v0[1], v3[0]
+; CHECK-NEXT:    mov.s v0[2], v6[0]
 ; CHECK-NEXT:    bit.16b v7, v1, v4
-; CHECK-NEXT:    ins.s v0[3], v7[0]
+; CHECK-NEXT:    mov.s v0[3], v7[0]
 ; CHECK-NEXT:    ret
   %tmp0 = fptrunc <4 x double> %b to <4 x float>
   %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0)
diff --git a/test/CodeGen/AArch64/win64_vararg.ll b/test/CodeGen/AArch64/win64_vararg.ll
index 7e28c9f79ec8..6fcbfcb62dcf 100644
--- a/test/CodeGen/AArch64/win64_vararg.ll
+++ b/test/CodeGen/AArch64/win64_vararg.ll
@@ -252,3 +252,29 @@ define i32 @snprintf(i8*, i64, i8*, ...) local_unnamed_addr #5 {
   call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %5) #2
   ret i32 %12
 }
+
+; CHECK-LABEL: fixed_params
+; CHECK: sub     sp,  sp, #32
+; CHECK: mov     w8,  w3
+; CHECK: mov     w9,  w2
+; CHECK: mov     w10, w1
+; CHECK: str     w4,  [sp]
+; CHECK: fmov    x1,  d0
+; CHECK: fmov    x3,  d1
+; CHECK: fmov    x5,  d2
+; CHECK: fmov    x7,  d3
+; CHECK: mov     w2,  w10
+; CHECK: mov     w4,  w9
+; CHECK: mov     w6,  w8
+; CHECK: str     x30, [sp, #16]
+; CHECK: str     d4,  [sp, #8]
+; CHECK: bl      varargs
+; CHECK: ldr     x30, [sp, #16]
+; CHECK: add     sp,  sp, #32
+; CHECK: ret
+define void @fixed_params(i32, double, i32, double, i32, double, i32, double, i32, double) nounwind {
+  tail call void (i32, ...) @varargs(i32 %0, double %1, i32 %2, double %3, i32 %4, double %5, i32 %6, double %7, i32 %8, double %9)
+  ret void
+}
+
+declare void @varargs(i32, ...) local_unnamed_addr
diff --git a/test/CodeGen/AArch64/xray-attribute-instrumentation.ll b/test/CodeGen/AArch64/xray-attribute-instrumentation.ll
index 5f01c7c8be84..651130414bef 100644
--- a/test/CodeGen/AArch64/xray-attribute-instrumentation.ll
+++ b/test/CodeGen/AArch64/xray-attribute-instrumentation.ll
@@ -24,9 +24,7 @@ define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always"
 ; CHECK-LABEL: Ltmp1:
 ; CHECK-NEXT:  ret
 }
-; CHECK:       .p2align 4
-; CHECK-NEXT:  .xword .Lxray_fn_idx_synth_0
-; CHECK-NEXT:  .section xray_instr_map,{{.*}}
+; CHECK-LABEL: xray_instr_map
 ; CHECK-LABEL: Lxray_sleds_start0
 ; CHECK:       .xword .Lxray_sled_0
 ; CHECK:       .xword .Lxray_sled_1
diff --git a/test/CodeGen/AArch64/xray-tail-call-sled.ll b/test/CodeGen/AArch64/xray-tail-call-sled.ll
index a7e993b3dbac..f966362b805e 100644
--- a/test/CodeGen/AArch64/xray-tail-call-sled.ll
+++ b/test/CodeGen/AArch64/xray-tail-call-sled.ll
@@ -27,15 +27,12 @@ define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-alway
 ; CHECK-LABEL: .Ltmp1:
 ; CHECK-NEXT:  ret
 }
-; CHECK:       .p2align 4
-; CHECK-NEXT:  .xword .Lxray_fn_idx_synth_0
-; CHECK-NEXT:  .section xray_instr_map,{{.*}}
+; CHECK-LABEL: xray_instr_map
 ; CHECK-LABEL: Lxray_sleds_start0:
 ; CHECK:       .xword .Lxray_sled_0
 ; CHECK:       .xword .Lxray_sled_1
 ; CHECK-LABEL: Lxray_sleds_end0:
-; CHECK:       .section xray_fn_idx,{{.*}}
-; CHECK-LABEL: Lxray_fn_idx_synth_0:
+; CHECK-LABEL: xray_fn_idx
 ; CHECK:       .xword .Lxray_sleds_start0
 ; CHECK-NEXT:  .xword .Lxray_sleds_end0
 
@@ -66,14 +63,11 @@ define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-alway
 ; CHECK:       b	callee
   ret i32 %retval
 }
-; CHECK:       .p2align 4
-; CHECK-NEXT:  .xword .Lxray_fn_idx_synth_1
-; CHECK-NEXT:  .section xray_instr_map,{{.*}}
+; CHECK-LABEL: xray_instr_map
 ; CHECK-LABEL: Lxray_sleds_start1:
 ; CHECK:       .xword .Lxray_sled_2
 ; CHECK:       .xword .Lxray_sled_3
 ; CHECK-LABEL: Lxray_sleds_end1:
 ; CHECK:       .section xray_fn_idx,{{.*}}
-; CHECK-LABEL: Lxray_fn_idx_synth_1:
 ; CHECK:       .xword .Lxray_sleds_start1
 ; CHECK-NEXT:  .xword .Lxray_sleds_end1
author	Dimitry Andric <dim@FreeBSD.org>	2017-12-18 20:10:56 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2017-12-18 20:10:56 +0000
commit	044eb2f6afba375a914ac9d8024f8f5142bb912e (patch)
tree	1475247dc9f9fe5be155ebd4c9069c75aadf8c20 /test/CodeGen/AArch64
parent	eb70dddbd77e120e5d490bd8fbe7ff3f8fa81c6b (diff)