vendor/llvm/llvm-trunk-r290819

79 files changed, 1044 insertions, 1362 deletions

diff --git a/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir b/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir
index 9a6f8dbafa00..a946b9f9f4a8 100644
--- a/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir
+++ b/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir
@@ -1,5 +1,5 @@
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the .cfi_def_cfa operands
+# This test ensures that the MIR parser parses the def_cfa operands
 # correctly.
 
 --- |
@@ -21,10 +21,10 @@ body: |
 
     %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
     %fp = frame-setup ADDXri %sp, 0, 0
-    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16
-    frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8
-    frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16
+    ; CHECK: CFI_INSTRUCTION def_cfa %w29, 16
+    frame-setup CFI_INSTRUCTION def_cfa %w29, 16
+    frame-setup CFI_INSTRUCTION offset %w30, -8
+    frame-setup CFI_INSTRUCTION offset %w29, -16
     BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
     %sp, %fp, %lr = LDPXpost %sp, 2
     RET_ReallyLR
diff --git a/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir b/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
index b3d8c5c3d361..d63c2ef6e871 100644
--- a/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
+++ b/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
@@ -1,43 +1,22 @@
-# RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2> %t.log \
-# RUN:        | FileCheck %s --check-prefix=CHECK
-# RUN: FileCheck %s -input-file=%t.log --check-prefix=ERR
-# RUN: rm -f %t.log
+# RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=ERR
 # REQUIRES: global-isel
 # This test ensures that the MIR parser errors out when
 # generic virtual register definitions are not correct.
 
 --- |
-  define void @bar() { ret void }
-
   define void @baz() { ret void }
 ...
 
 ---
-name:            bar
-isSSA:           true
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr }
-registers:
-  - { id: 0, class: gpr }
-body: |
-  bb.0:
-    liveins: %w0
-    ; ERR: generic virtual registers must have a size
-    ; ERR-NEXT: %0
-    %0 = G_ADD i32 %w0, %w0
-...
-
----
 name:            baz
-isSSA:           true
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _ }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
     liveins: %w0
-    ; ERR: generic virtual registers must have a size
+    ; ERR: generic virtual registers must have a type
     ; ERR-NEXT: %0
+    ; ERR: Unable to initialize machine function
     %0 = G_ADD i32 %w0, %w0
 ...
diff --git a/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir b/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
new file mode 100644
index 000000000000..e331179773d6
--- /dev/null
+++ b/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
@@ -0,0 +1,23 @@
+# RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=ERR
+# REQUIRES: global-isel
+# This test ensures that the MIR parser errors out when
+# generic virtual register definitions are not correct.
+# In that case, it is defined by a register bank.
+
+--- |
+  define void @bar() { ret void }
+...
+
+---
+name:            bar
+registers:
+  - { id: 0, class: gpr }
+body: |
+  bb.0:
+    liveins: %w0
+    ; ERR: generic virtual registers must have a type
+    ; ERR-NEXT: %0
+    ; ERR: Unable to initialize machine function
+    %0 = G_ADD i32 %w0, %w0
+...
diff --git a/test/CodeGen/MIR/AArch64/intrinsics.mir b/test/CodeGen/MIR/AArch64/intrinsics.mir
new file mode 100644
index 000000000000..b158c21b00ea
--- /dev/null
+++ b/test/CodeGen/MIR/AArch64/intrinsics.mir
@@ -0,0 +1,18 @@
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
+
+--- |
+
+  define void @use_intrin() {
+    ret void
+  }
+
+...
+---
+# Completely invalid code, but it checks that intrinsics round-trip properly.
+# CHECK: %x0 = COPY intrinsic(@llvm.returnaddress)
+name:            use_intrin
+body: |
+  bb.0:
+    %x0 = COPY intrinsic(@llvm.returnaddress)
+    RET_ReallyLR
+...
diff --git a/test/CodeGen/MIR/AArch64/machine-dead-copy.mir b/test/CodeGen/MIR/AArch64/machine-dead-copy.mir
deleted file mode 100644
index 90f2f3c09993..000000000000
--- a/test/CodeGen/MIR/AArch64/machine-dead-copy.mir
+++ /dev/null
@@ -1,71 +0,0 @@
-
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp  -verify-machineinstrs  -o - %s | FileCheck %s
-
---- |
-  define i32 @copyprop1(i32 %a, i32 %b) { ret i32 %a }
-  define i32 @copyprop2(i32 %a, i32 %b) { ret i32 %a }
-  define i32 @copyprop3(i32 %a, i32 %b) { ret i32 %a }
-  define i32 @copyprop4(i32 %a, i32 %b) { ret i32 %a }
-  declare i32 @foo(i32)
-...
----
-# The first copy is dead copy which is not used.
-# CHECK-LABEL: name: copyprop1
-# CHECK: bb.0:
-# CHECK-NOT: %w20 = COPY
-name:            copyprop1
-allVRegsAllocated: true
-body:             |
-  bb.0:
-    liveins: %w0,  %w1
-    %w20 = COPY %w1
-    BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
-    RET_ReallyLR implicit %w0
-...
----
-# The first copy is not a dead copy which is used in the second copy after the
-# call.
-# CHECK-LABEL: name: copyprop2
-# CHECK: bb.0:
-# CHECK: %w20 = COPY
-name:            copyprop2
-allVRegsAllocated: true
-body:             |
-  bb.0:
-    liveins: %w0,  %w1
-    %w20 = COPY %w1
-    BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
-    %w0 = COPY %w20
-    RET_ReallyLR implicit %w0
-...
----
-# Both the first and second copy are dead copies which are not used.
-# CHECK-LABEL: name: copyprop3
-# CHECK: bb.0:
-# CHECK-NOT: COPY
-name:            copyprop3
-allVRegsAllocated: true
-body:             |
-  bb.0:
-    liveins: %w0,  %w1
-    %w20 = COPY %w1
-    BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
-    %w20 = COPY %w0
-    RET_ReallyLR implicit %w0
-...
-# The second copy is removed as a NOP copy, after then the first copy become
-# dead which should be removed as well.
-# CHECK-LABEL: name: copyprop4
-# CHECK: bb.0:
-# CHECK-NOT: COPY
-name:            copyprop4
-allVRegsAllocated: true
-body:             |
-  bb.0:
-    liveins: %w0,  %w1
-    %w20 = COPY %w0
-    %w0 = COPY %w20
-    BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
-    RET_ReallyLR implicit %w0
-...
-
diff --git a/test/CodeGen/MIR/AArch64/machine-scheduler.mir b/test/CodeGen/MIR/AArch64/machine-scheduler.mir
deleted file mode 100644
index 9ea5c6811b65..000000000000
--- a/test/CodeGen/MIR/AArch64/machine-scheduler.mir
+++ /dev/null
@@ -1,35 +0,0 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler  -verify-machineinstrs  -o - %s | FileCheck %s
-
---- |
-  define i64 @load_imp-def(i64* nocapture %P, i32 %v) {
-  entry:
-    %0 = bitcast i64* %P to i32*
-    %1 = load i32, i32* %0
-    %conv = zext i32 %1 to i64
-    %arrayidx19 = getelementptr inbounds i64, i64* %P, i64 1
-    %arrayidx1 = bitcast i64* %arrayidx19 to i32*
-    store i32 %v, i32* %arrayidx1
-    %2 = load i64, i64* %arrayidx19
-    %and = and i64 %2, 4294967295
-    %add = add nuw nsw i64 %and, %conv
-    ret i64 %add
-  }
-...
----
-# CHECK-LABEL: name: load_imp-def
-# CHECK: bb.0.entry:
-# CHECK: LDRWui %x0, 0
-# CHECK: LDRWui %x0, 1
-# CHECK: STRWui %w1, %x0, 2
-name:            load_imp-def
-isSSA:           true
-body:             |
-  bb.0.entry:
-    liveins: %w1, %x0
-    %w8 = LDRWui %x0, 1, implicit-def %x8  :: (load 4 from %ir.0)
-    STRWui killed %w1, %x0, 2 :: (store 4 into %ir.arrayidx1)
-    %w9 = LDRWui killed %x0, 0, implicit-def %x9  :: (load 4 from %ir.arrayidx19, align 8)
-    %x0 = ADDXrr killed %x9, killed %x8
-    RET_ReallyLR implicit %x0
-...
-
diff --git a/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir b/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
index a2ad2092cb0e..fc0c4ce8c07f 100644
--- a/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
+++ b/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
@@ -15,7 +15,6 @@
 ...
 ---
 name:            stack_local
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gpr64common }
diff --git a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
index d4d2ae15af96..47f0e168a722 100644
--- a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
+++ b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
@@ -32,8 +32,7 @@
 
 ...
 ---
-name:            float
-tracksSubRegLiveness: true
+name: float
 liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
diff --git a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
new file mode 100644
index 000000000000..3277d37d7e4d
--- /dev/null
+++ b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
@@ -0,0 +1,709 @@
+# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s
+--- |
+  define void @add_f32_1.0_one_f16_use() #0 {
+    %f16.val0 = load volatile half, half addrspace(1)* undef
+    %f16.val1 = load volatile half, half addrspace(1)* undef
+    %f32.val = load volatile float, float addrspace(1)* undef
+    %f16.add0 = fadd half %f16.val0, 0xH3C00
+    %f32.add = fadd float %f32.val, 1.000000e+00
+    store volatile half %f16.add0, half addrspace(1)* undef
+    store volatile float %f32.add, float addrspace(1)* undef
+    ret void
+  }
+
+  define void @add_f32_1.0_multi_f16_use() #0 {
+    %f16.val0 = load volatile half, half addrspace(1)* undef
+    %f16.val1 = load volatile half, half addrspace(1)* undef
+    %f32.val = load volatile float, float addrspace(1)* undef
+    %f16.add0 = fadd half %f16.val0, 0xH3C00
+    %f32.add = fadd float %f32.val, 1.000000e+00
+    store volatile half %f16.add0, half addrspace(1)* undef
+    store volatile float %f32.add, float addrspace(1)* undef
+    ret void
+  }
+
+  define void @add_f32_1.0_one_f32_use_one_f16_use () #0 {
+    %f16.val0 = load volatile half, half addrspace(1)* undef
+    %f16.val1 = load volatile half, half addrspace(1)* undef
+    %f32.val = load volatile float, float addrspace(1)* undef
+    %f16.add0 = fadd half %f16.val0, 0xH3C00
+    %f32.add = fadd float %f32.val, 1.000000e+00
+    store volatile half %f16.add0, half addrspace(1)* undef
+    store volatile float %f32.add, float addrspace(1)* undef
+    ret void
+  }
+
+  define void @add_f32_1.0_one_f32_use_multi_f16_use () #0 {
+    %f16.val0 = load volatile half, half addrspace(1)* undef
+    %f16.val1 = load volatile half, half addrspace(1)* undef
+    %f32.val = load volatile float, float addrspace(1)* undef
+    %f16.add0 = fadd half %f16.val0, 0xH3C00
+    %f16.add1 = fadd half %f16.val1, 0xH3C00
+    %f32.add = fadd float %f32.val, 1.000000e+00
+    store volatile half %f16.add0, half addrspace(1)* undef
+    store volatile half %f16.add1, half addrspace(1)* undef
+    store volatile float %f32.add, float addrspace(1)* undef
+    ret void
+  }
+
+  define void @add_i32_1_multi_f16_use() #0 {
+    %f16.val0 = load volatile half, half addrspace(1)* undef
+    %f16.val1 = load volatile half, half addrspace(1)* undef
+    %f16.add0 = fadd half %f16.val0, 0xH0001
+    %f16.add1 = fadd half %f16.val1, 0xH0001
+    store volatile half %f16.add0, half addrspace(1)* undef
+    store volatile half %f16.add1,half addrspace(1)* undef
+    ret void
+  }
+
+  define void @add_i32_m2_one_f32_use_multi_f16_use () #0 {
+    %f16.val0 = load volatile half, half addrspace(1)* undef
+    %f16.val1 = load volatile half, half addrspace(1)* undef
+    %f32.val = load volatile float, float addrspace(1)* undef
+    %f16.add0 = fadd half %f16.val0, 0xHFFFE
+    %f16.add1 = fadd half %f16.val1, 0xHFFFE
+    %f32.add = fadd float %f32.val, 0xffffffffc0000000
+    store volatile half %f16.add0, half addrspace(1)* undef
+    store volatile half %f16.add1, half addrspace(1)* undef
+    store volatile float %f32.add, float addrspace(1)* undef
+    ret void
+  }
+
+  define void @add_f16_1.0_multi_f32_use() #0 {
+    %f32.val0 = load volatile float, float addrspace(1)* undef
+    %f32.val1 = load volatile float, float addrspace(1)* undef
+    %f32.val = load volatile float, float addrspace(1)* undef
+    %f32.add0 = fadd float %f32.val0, 1.0
+    %f32.add1 = fadd float %f32.val1, 1.0
+    store volatile float %f32.add0, float addrspace(1)* undef
+    store volatile float %f32.add1, float addrspace(1)* undef
+    ret void
+  }
+
+  define void @add_f16_1.0_other_high_bits_multi_f16_use() #0 {
+    %f16.val0 = load volatile half, half addrspace(1)* undef
+    %f16.val1 = load volatile half, half addrspace(1)* undef
+    %f32.val = load volatile half, half addrspace(1)* undef
+    %f16.add0 = fadd half %f16.val0, 0xH3C00
+    %f32.add = fadd half %f32.val, 1.000000e+00
+    store volatile half %f16.add0, half addrspace(1)* undef
+    store volatile half %f32.add, half addrspace(1)* undef
+    ret void
+  }
+
+  define void @add_f16_1.0_other_high_bits_use_f16_f32() #0 {
+    %f16.val0 = load volatile half, half addrspace(1)* undef
+    %f16.val1 = load volatile half, half addrspace(1)* undef
+    %f32.val = load volatile half, half addrspace(1)* undef
+    %f16.add0 = fadd half %f16.val0, 0xH3C00
+    %f32.add = fadd half %f32.val, 1.000000e+00
+    store volatile half %f16.add0, half addrspace(1)* undef
+    store volatile half %f32.add, half addrspace(1)* undef
+    ret void
+  }
+
+  attributes #0 = { nounwind }
+
+...
+---
+
+# f32 1.0 with a single use should be folded as the low 32-bits of a
+#  literal constant.
+
+# CHECK-LABEL: name: add_f32_1.0_one_f16_use
+# CHECK: %13 = V_ADD_F16_e32  1065353216, killed %11, implicit %exec
+
+name:            add_f32_1.0_one_f16_use
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %12 = V_MOV_B32_e32 1065353216, implicit %exec
+    %13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit %exec
+    BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    S_ENDPGM
+
+...
+---
+# Materialized f32 inline immediate should not be folded into the f16
+# operands
+
+# CHECK-LABEL: name: add_f32_1.0_multi_f16_use
+# CHECK: %13 = V_MOV_B32_e32 1065353216, implicit %exec
+# CHECK: %14 = V_ADD_F16_e32 %13, killed %11, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 killed %13, killed %12, implicit %exec
+
+
+name:            add_f32_1.0_multi_f16_use
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+  - { id: 14, class: vgpr_32 }
+  - { id: 15, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
+    %13 = V_MOV_B32_e32 1065353216, implicit %exec
+    %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit %exec
+    %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit %exec
+    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    S_ENDPGM
+
+...
+---
+
+# f32 1.0 should be folded into the single f32 use as an inline
+#  immediate, and folded into the single f16 use as a literal constant
+
+# CHECK-LABEL: name: add_f32_1.0_one_f32_use_one_f16_use
+# CHECK: %15 = V_ADD_F16_e32 1065353216, %11, implicit %exec
+# CHECK: %16 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
+
+name:            add_f32_1.0_one_f32_use_one_f16_use
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+  - { id: 14, class: vgpr_32 }
+  - { id: 15, class: vgpr_32 }
+  - { id: 16, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
+    %14 = V_MOV_B32_e32 1065353216, implicit %exec
+    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec
+    %16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec
+    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
+    S_ENDPGM
+
+...
+---
+
+# f32 1.0 should be folded for the single f32 use as an inline
+#  constant, and not folded as a multi-use literal for the f16 cases
+
+# CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use
+# CHECK: %14 = V_MOV_B32_e32 1065353216, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32  %14, %11, implicit %exec
+# CHECK: %16 = V_ADD_F16_e32 %14,  %12, implicit %exec
+# CHECK: %17 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
+
+name:            add_f32_1.0_one_f32_use_multi_f16_use
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+  - { id: 14, class: vgpr_32 }
+  - { id: 15, class: vgpr_32 }
+  - { id: 16, class: vgpr_32 }
+  - { id: 17, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
+    %14 = V_MOV_B32_e32 1065353216, implicit %exec
+    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec
+    %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit %exec
+    %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec
+    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
+    S_ENDPGM
+
+...
+---
+# CHECK-LABEL: name: add_i32_1_multi_f16_use
+# CHECK: %13 = V_MOV_B32_e32 1, implicit %exec
+# CHECK: %14 = V_ADD_F16_e32 1, killed %11, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 1, killed %12, implicit %exec
+
+
+name:            add_i32_1_multi_f16_use
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+  - { id: 14, class: vgpr_32 }
+  - { id: 15, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
+    %13 = V_MOV_B32_e32 1, implicit %exec
+    %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit %exec
+    %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit %exec
+    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    S_ENDPGM
+
+...
+---
+
+# CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use
+# CHECK: %14 = V_MOV_B32_e32 -2, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 -2, %11, implicit %exec
+# CHECK: %16 = V_ADD_F16_e32 -2, %12, implicit %exec
+# CHECK: %17 = V_ADD_F32_e32 -2, killed %13, implicit %exec
+
+name:            add_i32_m2_one_f32_use_multi_f16_use
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+  - { id: 14, class: vgpr_32 }
+  - { id: 15, class: vgpr_32 }
+  - { id: 16, class: vgpr_32 }
+  - { id: 17, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
+    %14 = V_MOV_B32_e32 -2, implicit %exec
+    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec
+    %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit %exec
+    %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec
+    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
+    S_ENDPGM
+
+...
+---
+
+# f32 1.0 should be folded for the single f32 use as an inline
+#  constant, and not folded as a multi-use literal for the f16 cases
+
+# CHECK-LABEL: name: add_f16_1.0_multi_f32_use
+# CHECK: %13 = V_MOV_B32_e32 15360, implicit %exec
+# CHECK: %14 = V_ADD_F32_e32 %13, %11, implicit %exec
+# CHECK: %15 = V_ADD_F32_e32 %13, %12, implicit %exec
+
+name:            add_f16_1.0_multi_f32_use
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+  - { id: 14, class: vgpr_32 }
+  - { id: 15, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
+    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
+    %13 = V_MOV_B32_e32 15360, implicit %exec
+    %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit %exec
+    %15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
+    BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
+    S_ENDPGM
+
+...
+---
+
+# The low 16-bits are an inline immediate, but the high bits are junk
+# FIXME: Should be able to fold this
+
+# CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use
+# CHECK: %13 = V_MOV_B32_e32 80886784, implicit %exec
+# CHECK: %14 = V_ADD_F16_e32 %13, %11, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 %13, %12, implicit %exec
+
+name:            add_f16_1.0_other_high_bits_multi_f16_use
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+  - { id: 14, class: vgpr_32 }
+  - { id: 15, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %13 = V_MOV_B32_e32 80886784, implicit %exec
+    %14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit %exec
+    %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit %exec
+    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    S_ENDPGM
+
+...
+---
+
+# FIXME: Should fold inline immediate into f16 and literal use into
+# f32 instruction.
+
+# CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32
+# CHECK: %13 = V_MOV_B32_e32 305413120, implicit %exec
+# CHECK: %14 = V_ADD_F32_e32 %13, %11, implicit %exec
+# CHECK: %15 = V_ADD_F16_e32 %13, %12, implicit %exec
+name:            add_f16_1.0_other_high_bits_use_f16_f32
+alignment:       0
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64 }
+  - { id: 1, class: sreg_32 }
+  - { id: 2, class: sgpr_32 }
+  - { id: 3, class: vgpr_32 }
+  - { id: 4, class: sreg_64 }
+  - { id: 5, class: sreg_32 }
+  - { id: 6, class: sreg_64 }
+  - { id: 7, class: sreg_32 }
+  - { id: 8, class: sreg_32 }
+  - { id: 9, class: sreg_32 }
+  - { id: 10, class: sreg_128 }
+  - { id: 11, class: vgpr_32 }
+  - { id: 12, class: vgpr_32 }
+  - { id: 13, class: vgpr_32 }
+  - { id: 14, class: vgpr_32 }
+  - { id: 15, class: vgpr_32 }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0 (%ir-block.0):
+    %4 = IMPLICIT_DEF
+    %5 = COPY %4.sub1
+    %6 = IMPLICIT_DEF
+    %7 = COPY %6.sub0
+    %8 = S_MOV_B32 61440
+    %9 = S_MOV_B32 -1
+    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
+    %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`)
+    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`)
+    %13 = V_MOV_B32_e32 305413120, implicit %exec
+    %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit %exec
+    %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`)
+    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`)
+    S_ENDPGM
+
+...
diff --git a/test/CodeGen/MIR/AMDGPU/intrinsics.mir b/test/CodeGen/MIR/AMDGPU/intrinsics.mir
new file mode 100644
index 000000000000..f43266eacbf0
--- /dev/null
+++ b/test/CodeGen/MIR/AMDGPU/intrinsics.mir
@@ -0,0 +1,19 @@
+# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
+
+--- |
+
+  define void @use_intrin() {
+    ret void
+  }
+
+...
+---
+# Completely invalid code, but it checks that intrinsics round-trip properly.
+# CHECK: %0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32)
+name:            use_intrin
+registers:
+  - { id: 0, class: _ }
+body: |
+  bb.0:
+    %0(s64) = COPY intrinsic(@llvm.AMDGPU.bfe.i32)
+...
diff --git a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
index 1b67edc6bb43..d73503223aa8 100644
--- a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
+++ b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
@@ -32,8 +32,7 @@
 
 ...
 ---
-name:            float
-tracksSubRegLiveness: true
+name: float
 liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
diff --git a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
index b0b7ea4eabd0..a4e77f281ea6 100644
--- a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
+++ b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -mcpu=SI -run-pass none -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s
 # This test verifies that the MIR parser can parse target index operands.
 
 --- |
@@ -41,8 +41,7 @@
 
 ...
 ---
-name:            float
-tracksSubRegLiveness: true
+name: float
 liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
@@ -56,15 +55,15 @@ body: |
     %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
     %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
     %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
-    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0
     %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
     %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
     %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
     %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
     %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
     %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
-    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
-    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
@@ -72,8 +71,7 @@ body: |
     S_ENDPGM
 ...
 ---
-name:            float2
-tracksSubRegLiveness: true
+name: float2
 liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
@@ -87,15 +85,15 @@ body: |
     %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
     %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
     %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
-    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0
     %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
     %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
     %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
     %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
     %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
     %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
-    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
-    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0
     %sgpr7 = S_MOV_B32 61440
     %sgpr6 = S_MOV_B32 -1
     %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
diff --git a/test/CodeGen/MIR/ARM/cfi-same-value.mir b/test/CodeGen/MIR/ARM/cfi-same-value.mir
index 32d0a85b5484..1a840883641d 100644
--- a/test/CodeGen/MIR/ARM/cfi-same-value.mir
+++ b/test/CodeGen/MIR/ARM/cfi-same-value.mir
@@ -32,9 +32,9 @@ body: |
     liveins: %r11, %lr
 
     %sp = STMDB_UPD %sp, 14, _, %r4, %r5
-    CFI_INSTRUCTION .cfi_def_cfa_offset 8
-    CFI_INSTRUCTION .cfi_offset %r5, -4
-    CFI_INSTRUCTION .cfi_offset %r4, -8
+    CFI_INSTRUCTION def_cfa_offset 8
+    CFI_INSTRUCTION offset %r5, -4
+    CFI_INSTRUCTION offset %r4, -8
     %r5 = MOVr %sp, 14, _, _
     %r4 = MRC 15, 0, 13, 0, 3, 14, _
     %r4 = LDRi12 %r4, 4, 14, _
@@ -48,29 +48,29 @@ body: |
     %r4 = MOVi 48, 14, _, _
     %r5 = MOVi 0, 14, _, _
     %sp = STMDB_UPD %sp, 14, _, %lr
-    CFI_INSTRUCTION .cfi_def_cfa_offset 12
-    CFI_INSTRUCTION .cfi_offset %lr, -12
+    CFI_INSTRUCTION def_cfa_offset 12
+    CFI_INSTRUCTION offset %lr, -12
     BL $__morestack, implicit-def %lr, implicit %sp
     %sp = LDMIA_UPD %sp, 14, _, %lr
     %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
-    CFI_INSTRUCTION .cfi_def_cfa_offset 0
+    CFI_INSTRUCTION def_cfa_offset 0
     BX_RET 14, _
 
   bb.2:
     liveins: %r11, %lr
 
     %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
-    CFI_INSTRUCTION .cfi_def_cfa_offset 0
-  ; CHECK:      CFI_INSTRUCTION .cfi_same_value %r4
-  ; CHECK-NEXT: CFI_INSTRUCTION .cfi_same_value %r5
-    CFI_INSTRUCTION .cfi_same_value %r4
-    CFI_INSTRUCTION .cfi_same_value %r5
+    CFI_INSTRUCTION def_cfa_offset 0
+  ; CHECK:      CFI_INSTRUCTION same_value %r4
+  ; CHECK-NEXT: CFI_INSTRUCTION same_value %r5
+    CFI_INSTRUCTION same_value %r4
+    CFI_INSTRUCTION same_value %r5
     %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r11, killed %lr
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8
-    frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4
-    frame-setup CFI_INSTRUCTION .cfi_offset %r11, -8
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset %lr, -4
+    frame-setup CFI_INSTRUCTION offset %r11, -8
     %sp = frame-setup SUBri killed %sp, 40, 14, _, _
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 48
+    frame-setup CFI_INSTRUCTION def_cfa_offset 48
     %r0 = MOVr %sp, 14, _, _
     %r1 = MOVi 10, 14, _, _
     BL @dummy_use, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit killed %r1, implicit-def %sp
diff --git a/test/CodeGen/MIR/ARM/imm-peephole-arm.mir b/test/CodeGen/MIR/ARM/imm-peephole-arm.mir
deleted file mode 100644
index cd30bdb74d57..000000000000
--- a/test/CodeGen/MIR/ARM/imm-peephole-arm.mir
+++ /dev/null
@@ -1,60 +0,0 @@
-# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
-
-# CHECK: [[IN:%.*]] = COPY %r0
-# CHECK: [[SUM1TMP:%.*]] = ADDri [[IN]], 133
-# CHECK: [[SUM1:%.*]] = ADDri killed [[SUM1TMP]], 25600
-
-# CHECK: [[SUM2TMP:%.*]] = SUBri [[IN]], 133
-# CHECK: [[SUM2:%.*]] = SUBri killed [[SUM2TMP]], 25600
-
-# CHECK: [[SUM3TMP:%.*]] = SUBri [[IN]], 133
-# CHECK: [[SUM3:%.*]] = SUBri killed [[SUM3TMP]], 25600
-
-# CHECK: [[SUM4TMP:%.*]] = ADDri killed [[IN]], 133
-# CHECK: [[SUM4:%.*]] = ADDri killed [[SUM4TMP]], 25600
-
-
---- |
-  target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
-  target triple = "armv7-apple-ios"
-
-  define i32 @foo(i32 %in) {
-    ret i32 undef
-  }
-...
----
-name:            foo
-registers:
-  - { id: 0, class: gprnopc }
-  - { id: 1, class: rgpr }
-  - { id: 2, class: rgpr }
-  - { id: 3, class: rgpr }
-  - { id: 4, class: rgpr }
-  - { id: 5, class: rgpr }
-  - { id: 6, class: rgpr }
-  - { id: 7, class: rgpr }
-  - { id: 8, class: rgpr }
-liveins:
-  - { reg: '%r0', virtual-reg: '%0' }
-body:             |
-  bb.0 (%ir-block.0):
-    liveins: %r0
-
-    %0 = COPY %r0
-    %1 = MOVi32imm -25733
-    %2 = SUBrr %0, killed %1, 14, _, _
-
-    %3 = MOVi32imm 25733
-    %4 = SUBrr %0, killed %3, 14, _, _
-
-    %5 = MOVi32imm -25733
-    %6 = ADDrr %0, killed %5, 14, _, _
-
-    %7 = MOVi32imm 25733
-    %8 = ADDrr killed %0, killed %7, 14, _, _
-
-    %r0 = COPY killed %8
-    BX_RET 14, _, implicit %r0
-
-...
-
diff --git a/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir b/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir
deleted file mode 100644
index 3d342902d80d..000000000000
--- a/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir
+++ /dev/null
@@ -1,59 +0,0 @@
-# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
-
-# CHECK: [[IN:%.*]] = COPY %r0
-# CHECK: [[SUM1TMP:%.*]] = t2ADDri [[IN]], 25600
-# CHECK: [[SUM1:%.*]] = t2ADDri killed [[SUM1TMP]], 133
-
-# CHECK: [[SUM2TMP:%.*]] = t2SUBri [[IN]], 25600
-# CHECK: [[SUM2:%.*]] = t2SUBri killed [[SUM2TMP]], 133
-
-# CHECK: [[SUM3TMP:%.*]] = t2SUBri [[IN]], 25600
-# CHECK: [[SUM3:%.*]] = t2SUBri killed [[SUM3TMP]], 133
-
-# CHECK: [[SUM4TMP:%.*]] = t2ADDri killed [[IN]], 25600
-# CHECK: [[SUM4:%.*]] = t2ADDri killed [[SUM4TMP]], 133
-
-
---- |
-  target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
-  target triple = "thumbv7-apple-ios"
-
-  define i32 @foo(i32 %in) {
-    ret i32 undef
-  }
-...
----
-name:            foo
-registers:
-  - { id: 0, class: gprnopc }
-  - { id: 1, class: rgpr }
-  - { id: 2, class: rgpr }
-  - { id: 3, class: rgpr }
-  - { id: 4, class: rgpr }
-  - { id: 5, class: rgpr }
-  - { id: 6, class: rgpr }
-  - { id: 7, class: rgpr }
-  - { id: 8, class: rgpr }
-liveins:
-  - { reg: '%r0', virtual-reg: '%0' }
-body:             |
-  bb.0 (%ir-block.0):
-    liveins: %r0
-    %0 = COPY %r0
-    %1 = t2MOVi32imm -25733
-    %2 = t2SUBrr %0, killed %1, 14, _, _
-
-    %3 = t2MOVi32imm 25733
-    %4 = t2SUBrr %0, killed %3, 14, _, _
-
-    %5 = t2MOVi32imm -25733
-    %6= t2ADDrr %0, killed %5, 14, _, _
-
-    %7 = t2MOVi32imm 25733
-    %8 = t2ADDrr killed %0, killed %7, 14, _, _
-
-    %r0 = COPY killed %8
-    tBX_RET 14, _, implicit %r0
-
-...
-
diff --git a/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
deleted file mode 100644
index eb4a44b7e175..000000000000
--- a/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
+++ /dev/null
@@ -1,161 +0,0 @@
-# RUN: llc -mtriple thumbv7 -verify-machineinstrs -start-after if-converter -print-before post-RA-sched -print-after post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s
---- |
-  ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll'
-  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
-  target triple = "thumbv7"
-
-  %struct.s = type opaque
-
-  ; Function Attrs: nounwind
-  define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 {
-  entry:
-    tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !18, metadata !27), !dbg !28
-    tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !19, metadata !27), !dbg !28
-    tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !20, metadata !27), !dbg !28
-    tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28
-    %cmp = icmp ult i32 %n, 4, !dbg !29
-    br i1 %cmp, label %return, label %if.end, !dbg !31
-
-  if.end:                                           ; preds = %entry
-    tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32
-    br label %return, !dbg !33
-
-  return:                                           ; preds = %if.end, %entry
-    %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ]
-    ret i32 %retval.0, !dbg !34
-  }
-
-  ; NOTE: This is checking that the register in the DEBUG_VALUE node is not
-  ; accidentally being marked as KILL.  The DBG_VALUE node gets introduced in
-  ; If-Conversion, and gets bundled into the IT block.  The Post RA Scheduler
-  ; attempts to schedule the Machine Instr, and tries to tag the register in the
-  ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen!  (or
-  ; hopefully, triggering an assert).
-
-  ; CHECK: BUNDLE %ITSTATE<imp-def,dead>
-  ; CHECK:  * DBG_VALUE %R1, %noreg, !"u"
-  ; CHECK-NOT:  * DBG_VALUE %R1<kill>, %noreg, !"u"
-
-  declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1
-
-  ; Function Attrs: nounwind readnone
-  declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
-
-  attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-  attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-  attributes #2 = { nounwind readnone }
-  attributes #3 = { nounwind }
-
-  !llvm.dbg.cu = !{!0}
-  !llvm.module.flags = !{!22, !23, !24, !25}
-  !llvm.ident = !{!26}
-
-  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0  (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2)
-  !1 = !DIFile(filename: "<stdin>", directory: "/Users/compnerd/Source/llvm")
-  !2 = !{}
-  !4 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !17)
-  !5 = !DISubroutineType(types: !6)
-  !6 = !{!7, !8, !11, !12, !16}
-  !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
-  !8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 32, align: 32)
-  !9 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !1, line: 5, baseType: !10)
-  !10 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !1, line: 5, flags: DIFlagFwdDecl)
-  !11 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
-  !12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 32, align: 32)
-  !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14)
-  !14 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !1, line: 2, baseType: !15)
-  !15 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char)
-  !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !1, line: 3, baseType: !11)
-  !17 = !{!18, !19, !20, !21}
-  !18 = !DILocalVariable(name: "s", arg: 1, scope: !4, file: !1, line: 9, type: !8)
-  !19 = !DILocalVariable(name: "u", arg: 2, scope: !4, file: !1, line: 9, type: !11)
-  !20 = !DILocalVariable(name: "b", arg: 3, scope: !4, file: !1, line: 9, type: !12)
-  !21 = !DILocalVariable(name: "n", arg: 4, scope: !4, file: !1, line: 9, type: !16)
-  !22 = !{i32 2, !"Dwarf Version", i32 4}
-  !23 = !{i32 2, !"Debug Info Version", i32 3}
-  !24 = !{i32 1, !"wchar_size", i32 4}
-  !25 = !{i32 1, !"min_enum_size", i32 4}
-  !26 = !{!"clang version 3.7.0  (llvm/trunk 237059)"}
-  !27 = !DIExpression()
-  !28 = !DILocation(line: 9, scope: !4)
-  !29 = !DILocation(line: 10, scope: !30)
-  !30 = distinct !DILexicalBlock(scope: !4, file: !1, line: 10)
-  !31 = !DILocation(line: 10, scope: !4)
-  !32 = !DILocation(line: 13, scope: !4)
-  !33 = !DILocation(line: 14, scope: !4)
-  !34 = !DILocation(line: 15, scope: !4)
-
-...
----
-name:            f
-alignment:       1
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: true
-isSSA:           false
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-liveins:
-  - { reg: '%r0' }
-  - { reg: '%r1' }
-  - { reg: '%r2' }
-  - { reg: '%r3' }
-calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
-                        '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
-                        '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11',
-                        '%s16', '%s17', '%s18', '%s19', '%s20', '%s21',
-                        '%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
-                        '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
-                        '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15',
-                        '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5',
-                        '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11',
-                        '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14',
-                        '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14',
-                        '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15',
-                        '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12',
-                        '%d11_d12_d13_d14' ]
-frameInfo:
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       8
-  offsetAdjustment: 0
-  maxAlignment:    4
-  adjustsStack:    true
-  hasCalls:        true
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-stack:
-  - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
-  - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
-body:             |
-  bb.0.entry:
-    liveins: %r0, %r1, %r2, %r3, %lr, %r7
-
-    DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
-    DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
-    t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    %r0 = t2MOVi -1, 3, %cpsr, _, implicit undef %r0
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    tBX_RET 3, %cpsr, implicit %r0, debug-location !34
-    %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr
-    frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8
-    frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4
-    frame-setup CFI_INSTRUCTION .cfi_offset %r7, -8
-    DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28
-    DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28
-    DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28
-    DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28
-    %r1 = tMOVr killed %r2, 14, _, debug-location !32
-    %r2 = tMOVr killed %r3, 14, _, debug-location !32
-    tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
-    %r0 = t2MOVi 0, 14, _, _
-    %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0
-
-...
diff --git a/test/CodeGen/MIR/Generic/branch-probabilities.ll b/test/CodeGen/MIR/Generic/branch-probabilities.ll
new file mode 100644
index 000000000000..8d119316b134
--- /dev/null
+++ b/test/CodeGen/MIR/Generic/branch-probabilities.ll
@@ -0,0 +1,28 @@
+; RUN: llc -stop-after machine-sink %s -o %t.mir
+; RUN: FileCheck %s < %t.mir
+; RUN: llc %t.mir -run-pass machine-sink
+; Check that branch probabilities are printed in a format that can then be parsed.
+; This test fails on powerpc because of an undefined physical register use in the MIR.  See PR31062.
+; XFAIL: powerpc
+
+declare void @foo()
+declare void @bar()
+
+define void @test(i1 %c) {
+; CHECK-LABEL: name: test
+entry:
+        br i1 %c, label %then, label %else
+
+then:
+        call void @foo()
+        br label %end
+; CHECK: successors: %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}}), %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}})
+
+else:
+        call void @bar()
+        br label %end
+; CHECK: successors: %{{[a-z0-9\-\.]+}}({{0x[0-9a-f]+}})
+
+end:
+        ret void
+}
diff --git a/test/CodeGen/MIR/Generic/frame-info.mir b/test/CodeGen/MIR/Generic/frame-info.mir
index 71448c8a71ba..7c6e6ebbfeee 100644
--- a/test/CodeGen/MIR/Generic/frame-info.mir
+++ b/test/CodeGen/MIR/Generic/frame-info.mir
@@ -23,7 +23,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 
 # CHECK: frameInfo:
@@ -49,7 +48,6 @@ body: |
 ...
 ---
 name:            test2
-isSSA:           true
 tracksRegLiveness: true
 
 # CHECK: test2
diff --git a/test/CodeGen/MIR/Generic/global-isel-properties.mir b/test/CodeGen/MIR/Generic/global-isel-properties.mir
new file mode 100644
index 000000000000..1384632afd0a
--- /dev/null
+++ b/test/CodeGen/MIR/Generic/global-isel-properties.mir
@@ -0,0 +1,40 @@
+# RUN: llc -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses GlobalISel MachineFunction
+# properties correctly.
+# This doesn't require GlobalISel to be built, as the properties are always
+# available in CodeGen.
+
+--- |
+
+  define i32 @test_defaults() {
+  entry:
+    ret i32 0
+  }
+
+  define i32 @test() {
+  start:
+    ret i32 0
+  }
+
+...
+---
+# CHECK-LABEL: name: test_defaults
+# CHECK:      legalized: false
+# CHECK-NEXT: regBankSelected: false
+# CHECK-NEXT: selected: false
+name:            test_defaults
+body: |
+  bb.0:
+...
+---
+# CHECK-LABEL: name: test
+# CHECK:      legalized: true
+# CHECK-NEXT: regBankSelected: true
+# CHECK-NEXT: selected: true
+name: test
+legalized: true
+regBankSelected: true
+selected: true
+body: |
+  bb.0:
+...
diff --git a/test/CodeGen/MIR/Generic/machine-function.mir b/test/CodeGen/MIR/Generic/machine-function.mir
index 64802a13060e..f9001cca4c26 100644
--- a/test/CodeGen/MIR/Generic/machine-function.mir
+++ b/test/CodeGen/MIR/Generic/machine-function.mir
@@ -24,7 +24,6 @@
 # CHECK: name: foo
 # CHECK-NEXT: alignment:
 # CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            foo
 body: |
@@ -34,7 +33,6 @@ body: |
 # CHECK: name: bar
 # CHECK-NEXT: alignment:
 # CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            bar
 body: |
@@ -44,7 +42,6 @@ body: |
 # CHECK: name: func
 # CHECK-NEXT: alignment: 8
 # CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            func
 alignment:       8
@@ -55,12 +52,10 @@ body: |
 # CHECK: name: func2
 # CHECK-NEXT: alignment: 16
 # CHECK-NEXT: exposesReturnsTwice: true
-# CHECK-NEXT: hasInlineAsm: true
 # CHECK: ...
 name:            func2
 alignment:       16
 exposesReturnsTwice: true
-hasInlineAsm:    true
 body: |
   bb.0:
 ...
diff --git a/test/CodeGen/MIR/Generic/register-info.mir b/test/CodeGen/MIR/Generic/register-info.mir
index bf90196b3e6e..af3f44f9abcc 100644
--- a/test/CodeGen/MIR/Generic/register-info.mir
+++ b/test/CodeGen/MIR/Generic/register-info.mir
@@ -17,9 +17,7 @@
 ...
 ---
 # CHECK: name: foo
-# CHECK:      isSSA: false
-# CHECK-NEXT: tracksRegLiveness: false
-# CHECK-NEXT: tracksSubRegLiveness: false
+# CHECK: tracksRegLiveness: false
 # CHECK: ...
 name:            foo
 body: |
@@ -27,14 +25,10 @@ body: |
 ...
 ---
 # CHECK: name: bar
-# CHECK:      isSSA: false
-# CHECK-NEXT: tracksRegLiveness: true
-# CHECK-NEXT: tracksSubRegLiveness: true
+# CHECK: tracksRegLiveness: true
 # CHECK: ...
 name: bar
-isSSA: false
 tracksRegLiveness: true
-tracksSubRegLiveness: true
 body: |
   bb.0:
 ...
diff --git a/test/CodeGen/MIR/Generic/runPass.mir b/test/CodeGen/MIR/Generic/runPass.mir
new file mode 100644
index 000000000000..bf37bdd1836b
--- /dev/null
+++ b/test/CodeGen/MIR/Generic/runPass.mir
@@ -0,0 +1,11 @@
+# RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s
+
+# Check that passes are initialized correctly, so that it's possible to
+# use -run-pass.
+
+---
+# CHECK: name: foo
+name: foo
+body: |
+  bb.0:
+...
diff --git a/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir b/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir
deleted file mode 100644
index a83c53e57cd3..000000000000
--- a/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir
+++ /dev/null
@@ -1,35 +0,0 @@
-# RUN: llc -march=hexagon -post-RA-scheduler -run-pass post-RA-sched %s -o - | FileCheck %s
-
---- |
-  declare void @check(i64, i32, i32, i64)
-  define void @foo() {
-    ret void
-  }
-...
-
----
-name: foo
-tracksRegLiveness: true
-allVRegsAllocated: true
-body: |
-  bb.0:
-    successors:
-    liveins: %r0, %r1, %d1, %d2, %r16, %r17, %r19, %r22, %r23
-        %r2 = A2_add %r23, killed %r17
-        %r6 = M2_mpyi %r16, %r16
-        %r22 = M2_accii %r22, killed %r2, 2
-        %r7 = A2_tfrsi 12345678
-        %r3 = A2_tfr killed %r16
-        %d2 = A2_tfrp killed %d0
-        %r2 = L2_loadri_io %r29, 28
-        %r2 = M2_mpyi killed %r6, killed %r2
-        %r23 = S2_asr_i_r %r22, 31
-        S2_storeri_io killed %r29, 0, killed %r7
-        ; The anti-dependency on r23 between the first A2_add and the
-        ; S2_asr_i_r was causing d11 to be renamed, while r22 remained
-        ; unchanged. Check that the renaming of d11 does not happen.
-        ; CHECK: d11
-        %d0 = A2_tfrp killed %d11
-        J2_call @check, implicit-def %d0, implicit-def %d1, implicit-def %d2, implicit %d0, implicit %d1, implicit %d2
-...
-
diff --git a/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir b/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir
new file mode 100644
index 000000000000..7f6f3469478b
--- /dev/null
+++ b/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir
@@ -0,0 +1,23 @@
+# RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s
+# Check that the MIR parser can parse lane masks in block liveins.
+
+# CHECK-LABEL: name: foo
+# CHECK: bb.0:
+# CHECK: liveins: %d0:0x00000002, %d1, %d2:0x00000010
+
+--- |
+  define void @foo() {
+    ret void
+  }
+...
+
+---
+name: foo
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: %d0:0x00002, %d1, %d2:16
+    A2_nop
+...
+
diff --git a/test/CodeGen/MIR/Lanai/lit.local.cfg b/test/CodeGen/MIR/Lanai/lit.local.cfg
deleted file mode 100644
index f1b8b4f4e21f..000000000000
--- a/test/CodeGen/MIR/Lanai/lit.local.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-if not 'Lanai' in config.root.targets:
-    config.unsupported = True
diff --git a/test/CodeGen/MIR/Lanai/peephole-compare.mir b/test/CodeGen/MIR/Lanai/peephole-compare.mir
deleted file mode 100644
index 763fe2b9b961..000000000000
--- a/test/CodeGen/MIR/Lanai/peephole-compare.mir
+++ /dev/null
@@ -1,714 +0,0 @@
-# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
-
-# Test the compare fold peephole.
-
-# CHECK-LABEL: name: test0a
-# TODO: Enhance combiner to handle this case. This expands into:
-#   sub     %r7, %r6, %r3
-#   sub.f   %r7, %r6, %r0
-#   sel.eq %r18, %r3, %rv
-# This is different from the pattern currently matched. If the lowered form had
-# been sub.f %r3, 0, %r0 then it would have matched.
-
-# CHECK-LABEL: name: test1a
-# CHECK: [[IN1:%.*]] = COPY %r7
-# CHECK: [[IN2:%.*]] = COPY %r6
-# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
-
-# CHECK-LABEL: name: test1b
-# CHECK: [[IN1:%.*]] = COPY %r7
-# CHECK: [[IN2:%.*]] = COPY %r6
-# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
-
-# CHECK-LABEL: name: test2a
-# CHECK: [[IN1:%.*]] = COPY %r7
-# CHECK: [[IN2:%.*]] = COPY %r6
-# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
-
-# CHECK-LABEL: name: test2b
-# CHECK: [[IN1:%.*]] = COPY %r7
-# CHECK: [[IN2:%.*]] = COPY %r6
-# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
-
-# CHECK-LABEL: name: test3
-# CHECK: AND_F_R
-# CHECK: AND_F_R
-# CHECK: AND_F_R
-
---- |
-  target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
-  target triple = "lanai-unknown-unknown"
-  
-  @a = global i32 -1, align 4
-  @b = global i32 0, align 4
-  
-  define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
-  entry:
-    %sub = sub i32 %b, %a
-    %cmp = icmp eq i32 %sub, 0
-    %cond = select i1 %cmp, i32 %c, i32 %sub
-    ret i32 %cond
-  }
-  
-  define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
-  entry:
-    %cmp = icmp eq i32 %b, %a
-    %cond = select i1 %cmp, i32 %c, i32 %b
-    ret i32 %cond
-  }
-  
-  define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
-  entry:
-    %sub = sub i32 %b, %a
-    %cmp = icmp slt i32 %sub, 0
-    %cond = select i1 %cmp, i32 %c, i32 %d
-    ret i32 %cond
-  }
-  
-  define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
-  entry:
-    %sub = sub i32 %b, %a
-    %cmp = icmp slt i32 %sub, 0
-    %cond = select i1 %cmp, i32 %c, i32 %d
-    ret i32 %cond
-  }
-  
-  define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
-  entry:
-    %sub = sub i32 %b, %a
-    %cmp = icmp sgt i32 %sub, -1
-    %cond = select i1 %cmp, i32 %c, i32 %d
-    ret i32 %cond
-  }
-  
-  define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
-  entry:
-    %sub = sub i32 %b, %a
-    %cmp = icmp sgt i32 %sub, -1
-    %cond = select i1 %cmp, i32 %c, i32 %d
-    ret i32 %cond
-  }
-  
-  define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
-  entry:
-    %sub = sub i32 %b, %a
-    %cmp = icmp slt i32 %sub, 1
-    %cond = select i1 %cmp, i32 %c, i32 %d
-    ret i32 %cond
-  }
-  
-  define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
-  entry:
-    %cmp = icmp ne i32 %a, 0
-    %cmp1 = icmp ult i32 %a, %b
-    %or.cond = and i1 %cmp, %cmp1
-    br i1 %or.cond, label %return, label %if.end
-  
-  if.end:                                           ; preds = %entry
-    %cmp2 = icmp ne i32 %b, 0
-    %cmp4 = icmp ult i32 %b, %c
-    %or.cond29 = and i1 %cmp2, %cmp4
-    br i1 %or.cond29, label %return, label %if.end6
-  
-  if.end6:                                          ; preds = %if.end
-    %cmp7 = icmp ne i32 %c, 0
-    %cmp9 = icmp ult i32 %c, %d
-    %or.cond30 = and i1 %cmp7, %cmp9
-    br i1 %or.cond30, label %return, label %if.end11
-  
-  if.end11:                                         ; preds = %if.end6
-    %cmp12 = icmp ne i32 %d, 0
-    %cmp14 = icmp ult i32 %d, %a
-    %or.cond31 = and i1 %cmp12, %cmp14
-    %b. = select i1 %or.cond31, i32 %b, i32 21
-    ret i32 %b.
-  
-  return:                                           ; preds = %if.end6, %if.end, %entry
-    %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ]
-    ret i32 %retval.0
-  }
-  
-  define void @testBB() {
-  entry:
-    %0 = load i32, i32* @a, align 4, !tbaa !0
-    %1 = load i32, i32* @b, align 4, !tbaa !0
-    %sub.i = sub i32 %1, %0
-    %tobool = icmp sgt i32 %sub.i, -1
-    br i1 %tobool, label %if.end, label %if.then
-  
-  if.then:                                          ; preds = %entry
-    %call1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
-    br label %while.body
-  
-  while.body:                                       ; preds = %while.body, %if.then
-    br label %while.body
-  
-  if.end:                                           ; preds = %entry
-    %cmp.i = icmp slt i32 %sub.i, 1
-    br i1 %cmp.i, label %if.then4, label %if.end7
-  
-  if.then4:                                         ; preds = %if.end
-    %call5 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
-    br label %while.body6
-  
-  while.body6:                                      ; preds = %while.body6, %if.then4
-    br label %while.body6
-  
-  if.end7:                                          ; preds = %if.end
-    ret void
-  }
-  
-  declare i32 @g(...)
-  
-  ; Function Attrs: nounwind
-  declare void @llvm.stackprotector(i8*, i8**) #0
-  
-  attributes #0 = { nounwind }
-  
-  !0 = !{!1, !1, i64 0}
-  !1 = !{!"int", !2, i64 0}
-  !2 = !{!"omnipotent char", !3, i64 0}
-  !3 = !{!"Simple C/C++ TBAA"}
-
-...
----
-name:            test0a
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-liveins:         
-  - { reg: '%r6', virtual-reg: '%0' }
-  - { reg: '%r7', virtual-reg: '%1' }
-  - { reg: '%r18', virtual-reg: '%2' }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    liveins: %r6, %r7, %r18
-  
-    %2 = COPY %r18
-    %1 = COPY %r7
-    %0 = COPY %r6
-    %4 = SUB_R %1, %0, 0
-    SFSUB_F_RI_LO %4, 0, implicit-def %sr
-    %5 = SELECT %2, %4, 7, implicit %sr
-    %rv = COPY %5
-    RET implicit %rca, implicit %rv
-
-...
----
-name:            test0b
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-liveins:         
-  - { reg: '%r6', virtual-reg: '%0' }
-  - { reg: '%r7', virtual-reg: '%1' }
-  - { reg: '%r18', virtual-reg: '%2' }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    liveins: %r6, %r7, %r18
-  
-    %2 = COPY %r18
-    %1 = COPY %r7
-    %0 = COPY %r6
-    SFSUB_F_RR %1, %0, implicit-def %sr
-    %4 = SELECT %2, %1, 7, implicit %sr
-    %rv = COPY %4
-    RET implicit %rca, implicit %rv
-
-...
----
-name:            test1a
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-liveins:         
-  - { reg: '%r6', virtual-reg: '%0' }
-  - { reg: '%r7', virtual-reg: '%1' }
-  - { reg: '%r18', virtual-reg: '%2' }
-  - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    liveins: %r6, %r7, %r18, %r19
-  
-    %3 = COPY %r19
-    %2 = COPY %r18
-    %1 = COPY %r7
-    %0 = COPY %r6
-    %4 = SUB_R %1, %0, 0
-    SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
-    %5 = SELECT %2, %3, 11, implicit %sr
-    %rv = COPY %5
-    RET implicit %rca, implicit %rv
-
-...
----
-name:            test1b
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-liveins:         
-  - { reg: '%r6', virtual-reg: '%0' }
-  - { reg: '%r7', virtual-reg: '%1' }
-  - { reg: '%r18', virtual-reg: '%2' }
-  - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    liveins: %r6, %r7, %r18, %r19
-  
-    %3 = COPY %r19
-    %2 = COPY %r18
-    %1 = COPY %r7
-    %0 = COPY %r6
-    %4 = SUB_R %1, %0, 0
-    SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
-    %5 = SELECT %2, %3, 11, implicit %sr
-    %rv = COPY %5
-    RET implicit %rca, implicit %rv
-
-...
----
-name:            test2a
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-liveins:         
-  - { reg: '%r6', virtual-reg: '%0' }
-  - { reg: '%r7', virtual-reg: '%1' }
-  - { reg: '%r18', virtual-reg: '%2' }
-  - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    liveins: %r6, %r7, %r18, %r19
-  
-    %3 = COPY %r19
-    %2 = COPY %r18
-    %1 = COPY %r7
-    %0 = COPY %r6
-    %4 = SUB_R %1, %0, 0
-    SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
-    %5 = SELECT %2, %3, 10, implicit %sr
-    %rv = COPY %5
-    RET implicit %rca, implicit %rv
-
-...
----
-name:            test2b
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-liveins:         
-  - { reg: '%r6', virtual-reg: '%0' }
-  - { reg: '%r7', virtual-reg: '%1' }
-  - { reg: '%r18', virtual-reg: '%2' }
-  - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    liveins: %r6, %r7, %r18, %r19
-  
-    %3 = COPY %r19
-    %2 = COPY %r18
-    %1 = COPY %r7
-    %0 = COPY %r6
-    %4 = SUB_R %1, %0, 0
-    SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
-    %5 = SELECT %2, %3, 10, implicit %sr
-    %rv = COPY %5
-    RET implicit %rca, implicit %rv
-
-...
----
-name:            test3
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-liveins:         
-  - { reg: '%r6', virtual-reg: '%0' }
-  - { reg: '%r7', virtual-reg: '%1' }
-  - { reg: '%r18', virtual-reg: '%2' }
-  - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    liveins: %r6, %r7, %r18, %r19
-  
-    %3 = COPY %r19
-    %2 = COPY %r18
-    %1 = COPY %r7
-    %0 = COPY %r6
-    %4 = SUB_R %1, %0, 0
-    SFSUB_F_RI_LO killed %4, 1, implicit-def %sr
-    %5 = SELECT %2, %3, 13, implicit %sr
-    %rv = COPY %5
-    RET implicit %rca, implicit %rv
-
-...
----
-name:            test4
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-  - { id: 6, class: gpr }
-  - { id: 7, class: gpr }
-  - { id: 8, class: gpr }
-  - { id: 9, class: gpr }
-  - { id: 10, class: gpr }
-  - { id: 11, class: gpr }
-  - { id: 12, class: gpr }
-  - { id: 13, class: gpr }
-  - { id: 14, class: gpr }
-  - { id: 15, class: gpr }
-  - { id: 16, class: gpr }
-  - { id: 17, class: gpr }
-  - { id: 18, class: gpr }
-  - { id: 19, class: gpr }
-  - { id: 20, class: gpr }
-  - { id: 21, class: gpr }
-  - { id: 22, class: gpr }
-liveins:         
-  - { reg: '%r6', virtual-reg: '%1' }
-  - { reg: '%r7', virtual-reg: '%2' }
-  - { reg: '%r18', virtual-reg: '%3' }
-  - { reg: '%r19', virtual-reg: '%4' }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        false
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    successors: %bb.4.return, %bb.1.if.end
-    liveins: %r6, %r7, %r18, %r19
-  
-    %4 = COPY %r19
-    %3 = COPY %r18
-    %2 = COPY %r7
-    %1 = COPY %r6
-    SFSUB_F_RI_LO %1, 0, implicit-def %sr
-    %5 = SCC 6, implicit %sr
-    SFSUB_F_RR %1, %2, implicit-def %sr
-    %6 = SCC 4, implicit %sr
-    %7 = AND_R killed %5, killed %6, 0
-    %8 = SLI 1
-    %9 = AND_R killed %7, %8, 0
-    SFSUB_F_RI_LO killed %9, 0, implicit-def %sr
-    BRCC %bb.4.return, 6, implicit %sr
-    BT %bb.1.if.end
-  
-  bb.1.if.end:
-    successors: %bb.4.return, %bb.2.if.end6
-  
-    SFSUB_F_RI_LO %2, 0, implicit-def %sr
-    %10 = SCC 6, implicit %sr
-    SFSUB_F_RR %2, %3, implicit-def %sr
-    %11 = SCC 4, implicit %sr
-    %12 = AND_R killed %10, killed %11, 0
-    %14 = AND_R killed %12, %8, 0
-    SFSUB_F_RI_LO killed %14, 0, implicit-def %sr
-    BRCC %bb.4.return, 6, implicit %sr
-    BT %bb.2.if.end6
-  
-  bb.2.if.end6:
-    successors: %bb.4.return, %bb.3.if.end11
-  
-    SFSUB_F_RI_LO %3, 0, implicit-def %sr
-    %15 = SCC 6, implicit %sr
-    SFSUB_F_RR %3, %4, implicit-def %sr
-    %16 = SCC 4, implicit %sr
-    %17 = AND_R killed %15, killed %16, 0
-    %18 = SLI 1
-    %19 = AND_R killed %17, killed %18, 0
-    SFSUB_F_RI_LO killed %19, 0, implicit-def %sr
-    BRCC %bb.4.return, 6, implicit %sr
-    BT %bb.3.if.end11
-  
-  bb.3.if.end11:
-    %20 = SLI 21
-    SFSUB_F_RR %4, %1, implicit-def %sr
-    %21 = SELECT %2, %20, 4, implicit %sr
-    SFSUB_F_RI_LO %4, 0, implicit-def %sr
-    %22 = SELECT killed %21, %20, 6, implicit %sr
-    %rv = COPY %22
-    RET implicit %rca, implicit %rv
-  
-  bb.4.return:
-    %0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6
-    %rv = COPY %0
-    RET implicit %rca, implicit %rv
-
-...
----
-name:            testBB
-alignment:       2
-exposesReturnsTwice: false
-hasInlineAsm:    false
-allVRegsAllocated: false
-isSSA:           true
-tracksRegLiveness: true
-tracksSubRegLiveness: false
-registers:       
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-  - { id: 6, class: gpr }
-  - { id: 7, class: gpr }
-  - { id: 8, class: gpr }
-frameInfo:       
-  isFrameAddressTaken: false
-  isReturnAddressTaken: false
-  hasStackMap:     false
-  hasPatchPoint:   false
-  stackSize:       0
-  offsetAdjustment: 0
-  maxAlignment:    0
-  adjustsStack:    false
-  hasCalls:        true
-  maxCallFrameSize: 0
-  hasOpaqueSPAdjustment: false
-  hasVAStart:      false
-  hasMustTailInVarArgFunc: false
-body:             |
-  bb.0.entry:
-    successors: %bb.3.if.end, %bb.1.if.then
-  
-    %1 = MOVHI target-flags(lanai-hi) @a
-    %2 = OR_I_LO killed %1, target-flags(lanai-lo) @a
-    %3 = LDW_RI killed %2, 0, 0 :: (load 4 from @a, !tbaa !0)
-    %4 = MOVHI target-flags(lanai-hi) @b
-    %5 = OR_I_LO killed %4, target-flags(lanai-lo) @b
-    %6 = LDW_RI killed %5, 0, 0 :: (load 4 from @b, !tbaa !0)
-    %0 = SUB_R killed %6, killed %3, 0
-    SFSUB_F_RI_LO %0, 0, implicit-def %sr
-    BRCC %bb.3.if.end, 10, implicit %sr
-    BT %bb.1.if.then
-  
-  bb.1.if.then:
-    successors: %bb.2.while.body
-  
-    ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp
-    CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
-    ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
-  
-  bb.2.while.body:
-    successors: %bb.2.while.body
-  
-    BT %bb.2.while.body
-  
-  bb.3.if.end:
-    successors: %bb.4.if.then4, %bb.6.if.end7
-    liveins: %sr
-  
-    BRCC %bb.6.if.end7, 14, implicit %sr
-    BT %bb.4.if.then4
-  
-  bb.4.if.then4:
-    successors: %bb.5.while.body6
-  
-    ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp
-    CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
-    ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
-  
-  bb.5.while.body6:
-    successors: %bb.5.while.body6
-  
-    BT %bb.5.while.body6
-  
-  bb.6.if.end7:
-    RET implicit %rca
-
-...
diff --git a/test/CodeGen/MIR/Mips/memory-operands.mir b/test/CodeGen/MIR/Mips/memory-operands.mir
index 69ecf985fcc0..0e465e82b333 100644
--- a/test/CodeGen/MIR/Mips/memory-operands.mir
+++ b/test/CodeGen/MIR/Mips/memory-operands.mir
@@ -44,8 +44,8 @@ body:             |
     liveins: %a0, %ra
 
     Save16 %ra, 24, implicit-def %sp, implicit %sp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 24
-    CFI_INSTRUCTION .cfi_offset %ra_64, -4
+    CFI_INSTRUCTION def_cfa_offset 24
+    CFI_INSTRUCTION offset %ra_64, -4
     %v0, %v1 = GotPrologue16 $_gp_disp, $_gp_disp
     %v0 = SllX16 killed %v0, 16
     %v0 = AdduRxRyRz16 killed %v1, killed %v0
@@ -80,10 +80,10 @@ body:             |
     liveins: %ra, %s2, %s0, %ra, %s2, %s0
 
     SaveX16 %s0, %ra, %s2, 32, implicit-def %sp, implicit %sp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 32
-    CFI_INSTRUCTION .cfi_offset %ra_64, -4
-    CFI_INSTRUCTION .cfi_offset %s2_64, -8
-    CFI_INSTRUCTION .cfi_offset %s0_64, -12
+    CFI_INSTRUCTION def_cfa_offset 32
+    CFI_INSTRUCTION offset %ra_64, -4
+    CFI_INSTRUCTION offset %s2_64, -8
+    CFI_INSTRUCTION offset %s0_64, -12
     %v0, %v1 = GotPrologue16 $_gp_disp, $_gp_disp
     %v0 = SllX16 killed %v0, 16
     %s0 = AdduRxRyRz16 killed %v1, killed %v0
diff --git a/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir b/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
index 3caab2c7a578..d1c38acd5d33 100644
--- a/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
+++ b/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
@@ -20,7 +20,6 @@
 ...
 ---
 name:            main
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: g8rc_and_g8rc_nox0 }
diff --git a/test/CodeGen/MIR/README b/test/CodeGen/MIR/README
new file mode 100644
index 000000000000..72e55403165c
--- /dev/null
+++ b/test/CodeGen/MIR/README
@@ -0,0 +1,7 @@
+This directory contains tests for the MIR file format parser and printer. It
+was necessary to split the tests across different targets as no single target
+covers all features available in machine IR.
+
+Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
+a rule of thumb this directory should only contain tests using
+'llc -run-pass none'.
diff --git a/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir b/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
index ed26df684b00..2bdec446af07 100644
--- a/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
+++ b/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
@@ -1,5 +1,5 @@
 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the .cfi_def_cfa_offset operands
+# This test ensures that the MIR parser parses the cfi offset operands
 # correctly.
 
 --- |
@@ -21,8 +21,8 @@ stack:
 body: |
   bb.0.entry:
     %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
-    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048
-    CFI_INSTRUCTION .cfi_def_cfa_offset 4048
+    ; CHECK: CFI_INSTRUCTION def_cfa_offset 4048
+    CFI_INSTRUCTION def_cfa_offset 4048
     %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
     RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir b/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
index 9a57eb047b87..2afa8e3bf920 100644
--- a/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
+++ b/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
@@ -1,5 +1,5 @@
 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the .cfi_def_cfa_register
+# This test ensures that the MIR parser parses the cfi def_cfa_register
 # operands correctly.
 
 --- |
@@ -24,9 +24,9 @@ body: |
     liveins: %rbp
 
     PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    CFI_INSTRUCTION .cfi_offset %rbp, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbp, -16
     %rbp = MOV64rr %rsp
-    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp
-    CFI_INSTRUCTION .cfi_def_cfa_register %rbp
+    ; CHECK: CFI_INSTRUCTION def_cfa_register %rbp
+    CFI_INSTRUCTION def_cfa_register %rbp
 ...
diff --git a/test/CodeGen/MIR/X86/cfi-offset.mir b/test/CodeGen/MIR/X86/cfi-offset.mir
index 0a50fe1866f4..4cb33073f805 100644
--- a/test/CodeGen/MIR/X86/cfi-offset.mir
+++ b/test/CodeGen/MIR/X86/cfi-offset.mir
@@ -1,5 +1,5 @@
 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the .cfi_offset operands
+# This test ensures that the MIR parser parses the cfi offset operands
 # correctly.
 
 --- |
@@ -31,9 +31,9 @@ body: |
     liveins: %ecx, %edi, %edx, %esi, %rbx
 
     PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    ; CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16
-    CFI_INSTRUCTION .cfi_offset %rbx, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK: CFI_INSTRUCTION offset %rbx, -16
+    CFI_INSTRUCTION offset %rbx, -16
     %ebx = COPY %edi, implicit-def %rbx
     %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
diff --git a/test/CodeGen/MIR/X86/def-register-already-tied-error.mir b/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
index bd9365b5f416..fe0740e9c622 100644
--- a/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
+++ b/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
diff --git a/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
index 0870fa062be6..2bc825016bc2 100644
--- a/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
+++ b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
@@ -19,7 +19,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '%edi' }
@@ -33,7 +32,7 @@ body: |
     liveins: %edi, %esi
 
     frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    CFI_INSTRUCTION def_cfa_offset 16
     %ecx = COPY %edi
     %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags
   ; CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
diff --git a/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir b/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
index 52ba166094f3..eb0d16755c47 100644
--- a/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
+++ b/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
@@ -27,9 +27,9 @@ fixedStack:
 body: |
   bb.0.entry:
     PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    ; CHECK: [[@LINE+1]]:38: expected ','
-    CFI_INSTRUCTION .cfi_offset %rbx -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK: [[@LINE+1]]:33: expected ','
+    CFI_INSTRUCTION offset %rbx -16
     %ebx = COPY %edi, implicit-def %rbx
     %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
diff --git a/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir b/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
index c3f4fca11eaa..edbe7d4c34e4 100644
--- a/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
+++ b/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
@@ -18,7 +17,7 @@ body: |
   bb.0.entry:
     liveins: %rdi
 
-  ; CHECK: [[@LINE+1]]:78: expected an integer literal after 'tied-def'
+  ; CHECK: [[@LINE+1]]:78: expected tied-def or low-level type after '('
     INLINEASM $"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def)
     %rax = COPY killed %rdi
     RETQ killed %rax
diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir b/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
index c5d7d5eb2893..d2729978669c 100644
--- a/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
+++ b/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
@@ -39,7 +39,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir b/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
index c94fd9f5028e..3f668cd815fd 100644
--- a/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
+++ b/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
@@ -39,7 +39,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
index bba7b1a6e4a0..5e7dde26769b 100644
--- a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
+++ b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: llc -march=x86-64 -run-pass none -o - %s 2>&1 | FileCheck %s
 
 --- |
 
@@ -14,7 +14,8 @@ name:            test
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
-  # CHECK: [[@LINE+1]]:48: expected a named register
+  # CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
+  # CHECK: - { id: 2, class: gr32, preferred-register: '%edi' }
   - { id: 1, class: gr32, preferred-register: '%0' }
   - { id: 2, class: gr32, preferred-register: '%edi' }
 body: |
diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir b/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
index a6384bb07197..af563bd672ad 100644
--- a/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
+++ b/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir b/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
index e3c5ee9b9c88..fd7ad1bb9a45 100644
--- a/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
@@ -19,8 +19,8 @@ stack:
 body: |
   bb.0.entry:
     %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
-    ; CHECK: [[@LINE+1]]:41: expected a cfi offset
-    CFI_INSTRUCTION .cfi_def_cfa_offset _
+    ; CHECK: [[@LINE+1]]:36: expected a cfi offset
+    CFI_INSTRUCTION def_cfa_offset _
     %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
     RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir b/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
index eea795821465..eb53d629a85e 100644
--- a/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
+++ b/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
@@ -27,9 +27,9 @@ fixedStack:
 body: |
   bb.0.entry:
     PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    ; CHECK: [[@LINE+1]]:33: expected a cfi register
-    CFI_INSTRUCTION .cfi_offset %0, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK: [[@LINE+1]]:28: expected a cfi register
+    CFI_INSTRUCTION offset %0, -16
     %ebx = COPY %edi, implicit-def %rbx
     %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
     %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
diff --git a/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
index d1d62461d371..e9c49c023482 100644
--- a/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
+++ b/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
@@ -19,8 +18,8 @@ registers:
 body: |
   bb.0.entry:
     %0 = COPY %edi
-    ; CHECK: [[@LINE+1]]:20: expected a subregister index after ':'
-    %1 = COPY %0 : 42
+    ; CHECK: [[@LINE+1]]:20: expected a subregister index after '.'
+    %1 = COPY %0 . 42
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
diff --git a/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir b/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
index 9e307f8833d9..f80dd8d7e627 100644
--- a/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
+++ b/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
@@ -18,7 +17,7 @@ body: |
   bb.0.entry:
     liveins: %rdi
 
-  ; CHECK: [[@LINE+1]]:70: expected 'tied-def' after '('
+  ; CHECK: [[@LINE+1]]:70: expected tied-def or low-level type after '('
     INLINEASM $"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(3)
     %rax = COPY killed %rdi
     RETQ killed %rax
diff --git a/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir b/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
index cdfcabbbf827..e5b0183c44df 100644
--- a/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
+++ b/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
index f7a48d2eec06..8ae76753984d 100644
--- a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
+++ b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
@@ -29,7 +29,7 @@ stack:
 body: |
   bb.0.entry:
     frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 8
+    CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK: name: test
   ; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
     %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
diff --git a/test/CodeGen/MIR/X86/function-liveins.mir b/test/CodeGen/MIR/X86/function-liveins.mir
index cbdc36281b71..a388bfac3b01 100644
--- a/test/CodeGen/MIR/X86/function-liveins.mir
+++ b/test/CodeGen/MIR/X86/function-liveins.mir
@@ -13,7 +13,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/generic-instr-type-error.mir b/test/CodeGen/MIR/X86/generic-instr-type-error.mir
deleted file mode 100644
index 1f196919afa0..000000000000
--- a/test/CodeGen/MIR/X86/generic-instr-type-error.mir
+++ /dev/null
@@ -1,15 +0,0 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# This test ensures that the MIR parser report an error for
-# opaque types used on generic instruction.
-
----
-name:            bar
-isSSA:           true
-registers:
-  - { id: 0, class: gr32 }
-body: |
-  bb.0.entry:
-    liveins: %edi
-    ; CHECK: [[@LINE+1]]:20: expected a sized type
-    %0(32) = G_ADD %opaque %edi, %edi
-...
diff --git a/test/CodeGen/MIR/X86/generic-instr-type.mir b/test/CodeGen/MIR/X86/generic-instr-type.mir
new file mode 100644
index 000000000000..b9e47cdf6192
--- /dev/null
+++ b/test/CodeGen/MIR/X86/generic-instr-type.mir
@@ -0,0 +1,64 @@
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# REQUIRES: global-isel
+# Test that the MIR parser parses types on generic instructions correctly.
+
+--- |
+  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+  %type_alias = type <2 x i32>
+  %structure_alias = type { i32, i16 }
+  define void @test_vregs() {
+    ret void
+  }
+
+  define void @test_unsized() {
+    ret void
+  }
+
+...
+
+---
+name:            test_vregs
+# CHECK:      registers:
+# CHECK-NEXT:   - { id: 0, class: _ }
+# CHECK-NEXT:   - { id: 1, class: _ }
+# CHECK-NEXT:   - { id: 2, class: _ }
+# CHECK-NEXT:   - { id: 3, class: _ }
+# CHECK-NEXT:   - { id: 4, class: _ }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+  - { id: 6, class: _ }
+  - { id: 7, class: _ }
+  - { id: 8, class: _ }
+body: |
+  bb.0:
+    liveins: %edi, %xmm0
+    ; CHECK:      %1(s32) = G_ADD %0
+    %0(s32) = COPY %edi
+    %6(<2 x s32>) = COPY %xmm0
+    %7(s64) = COPY %rdi
+
+    %1(s32) = G_ADD %0, %0
+    ; CHECK:      %2(<2 x s32>) = G_ADD %6, %6
+    %2(<2 x s32>) = G_ADD %6, %6
+    ; CHECK:      %3(s64) = G_ADD %7, %7
+    %3(s64) = G_ADD %7, %7
+
+    ; CHECK:      %5(s48) = G_ADD %8, %8
+    %8(s48) = G_TRUNC %7
+    %5(s48) = G_ADD %8, %8
+...
+
+---
+name:            test_unsized
+body: |
+  bb.0:
+    successors: %bb.0
+
+    ; CHECK:      G_BR %bb.0
+    G_BR  %bb.0
+...
diff --git a/test/CodeGen/MIR/X86/generic-virtual-registers.mir b/test/CodeGen/MIR/X86/generic-virtual-registers.mir
deleted file mode 100644
index 225ddfbc452a..000000000000
--- a/test/CodeGen/MIR/X86/generic-virtual-registers.mir
+++ /dev/null
@@ -1,48 +0,0 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# REQUIRES: global-isel
-# This test ensures that the MIR parser parses generic virtual
-# register definitions correctly.
-
---- |
-  ; ModuleID = 'generic-virtual-registers-type-error.mir'
-  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
-  %type_alias = type <2 x i32>
-  %structure_alias = type { i32, i16 }
-  define void @bar() {
-  entry:
-    ret void
-  }
-
-...
-
----
-name:            bar
-isSSA:           true
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _ }
-# CHECK-NEXT:   - { id: 1, class: _ }
-# CHECK-NEXT:   - { id: 2, class: _ }
-# CHECK-NEXT:   - { id: 3, class: _ }
-# CHECK-NEXT:   - { id: 4, class: _ }
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
-body: |
-  bb.0.entry:
-    liveins: %edi
-    ; CHECK:      %0(32) = G_ADD i32 %edi
-    %0(32) = G_ADD i32 %edi, %edi
-    ; CHECK:      %1(64) = G_ADD <2 x i32> %edi
-    %1(64) = G_ADD <2 x i32> %edi, %edi
-    ; CHECK:      %2(64) = G_ADD <2 x i32> %edi
-    %2(64) = G_ADD %type_alias %edi, %edi
-    ; G_ADD is actually not a valid operand for structure type,
-    ; but that is the only one we have for now for testing.
-    ; CHECK:      %3(64) = G_ADD { i32, i32 } %edi
-    %3(64) = G_ADD {i32, i32} %edi, %edi
-    ; CHECK:      %4(48) = G_ADD %structure_alias %edi
-    %4(48) = G_ADD %structure_alias %edi, %edi
-...
diff --git a/test/CodeGen/MIR/X86/inline-asm-registers.mir b/test/CodeGen/MIR/X86/inline-asm-registers.mir
index f0e8d1fcd8ff..d84cebfc6df1 100644
--- a/test/CodeGen/MIR/X86/inline-asm-registers.mir
+++ b/test/CodeGen/MIR/X86/inline-asm-registers.mir
@@ -19,7 +19,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
@@ -36,7 +35,6 @@ body: |
 ...
 ---
 name:            test2
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
diff --git a/test/CodeGen/MIR/X86/instructions-debug-location.mir b/test/CodeGen/MIR/X86/instructions-debug-location.mir
index 12ee5d873d94..aa6cd5a0a45f 100644
--- a/test/CodeGen/MIR/X86/instructions-debug-location.mir
+++ b/test/CodeGen/MIR/X86/instructions-debug-location.mir
@@ -50,7 +50,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
@@ -72,7 +71,6 @@ body: |
 ...
 ---
 name:            test_typed_immediates
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir b/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
index 42d05274e7cd..c921e497d463 100644
--- a/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
+++ b/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
@@ -34,7 +34,6 @@
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
diff --git a/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir b/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
index 2ba3288335fb..7a0994def210 100644
--- a/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
+++ b/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
diff --git a/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir b/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
index 3339115c8bdf..988a3432e793 100644
--- a/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
+++ b/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
@@ -19,8 +19,8 @@ stack:
 body: |
   bb.0.entry:
     %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
-    ; CHECK: [[@LINE+1]]:41: expected a 32 bit integer (the cfi offset is too large)
-    CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456
+    ; CHECK: [[@LINE+1]]:36: expected a 32 bit integer (the cfi offset is too large)
+    CFI_INSTRUCTION def_cfa_offset 123456789123456
     %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
     RETQ
 ...
diff --git a/test/CodeGen/MIR/X86/liveout-register-mask.mir b/test/CodeGen/MIR/X86/liveout-register-mask.mir
index c2a5a34a85ca..3e38348961fe 100644
--- a/test/CodeGen/MIR/X86/liveout-register-mask.mir
+++ b/test/CodeGen/MIR/X86/liveout-register-mask.mir
@@ -31,10 +31,10 @@ body: |
     liveins: %rdi, %rsi, %rbp
 
     frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_offset 16
-    CFI_INSTRUCTION .cfi_offset %rbp, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    CFI_INSTRUCTION offset %rbp, -16
     %rbp = frame-setup MOV64rr %rsp
-    CFI_INSTRUCTION .cfi_def_cfa_register %rbp
+    CFI_INSTRUCTION def_cfa_register %rbp
   ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),
     PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax
     %rbp = POP64r implicit-def %rsp, implicit %rsp
diff --git a/test/CodeGen/MIR/X86/memory-operands.mir b/test/CodeGen/MIR/X86/memory-operands.mir
index a25538d9b1fc..5ac932e90348 100644
--- a/test/CodeGen/MIR/X86/memory-operands.mir
+++ b/test/CodeGen/MIR/X86/memory-operands.mir
@@ -354,7 +354,7 @@ fixedStack:
 body: |
   bb.0.entry:
     %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags
-    CFI_INSTRUCTION .cfi_def_cfa_offset 32
+    CFI_INSTRUCTION def_cfa_offset 32
     LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw
   ; CHECK: name: stack_psv
   ; CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
diff --git a/test/CodeGen/MIR/X86/metadata-operands.mir b/test/CodeGen/MIR/X86/metadata-operands.mir
index 42f3fe1c86c7..9d92fe5c2c6d 100644
--- a/test/CodeGen/MIR/X86/metadata-operands.mir
+++ b/test/CodeGen/MIR/X86/metadata-operands.mir
@@ -41,7 +41,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/newline-handling.mir b/test/CodeGen/MIR/X86/newline-handling.mir
index ce43a83ecae5..ce53e49eddbb 100644
--- a/test/CodeGen/MIR/X86/newline-handling.mir
+++ b/test/CodeGen/MIR/X86/newline-handling.mir
@@ -35,7 +35,7 @@ liveins:
 # CHECK-LABEL: name: foo
 # CHECK: body: |
 # CHECK-NEXT: bb.0.entry:
-# CHECK-NEXT: successors: %bb.1.less(0x40000000 / 0x80000000 = 50.00%), %bb.2.exit(0x40000000 / 0x80000000 = 50.00%)
+# CHECK-NEXT: successors: %bb.1.less(0x40000000), %bb.2.exit(0x40000000)
 # CHECK-NEXT: liveins: %edi
 # CHECK:      CMP32ri8 %edi, 10, implicit-def %eflags
 # CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags
@@ -79,7 +79,7 @@ liveins:
 # CHECK-LABEL: name: bar
 # CHECK: body: |
 # CHECK-NEXT: bb.0.entry:
-# CHECK-NEXT: successors: %bb.1.less(0x40000000 / 0x80000000 = 50.00%), %bb.2.exit(0x40000000 / 0x80000000 = 50.00%)
+# CHECK-NEXT: successors: %bb.1.less(0x40000000), %bb.2.exit(0x40000000)
 # CHECK-NEXT: liveins: %edi
 # CHECK:      CMP32ri8 %edi, 10, implicit-def %eflags
 # CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags
diff --git a/test/CodeGen/MIR/X86/stack-object-debug-info.mir b/test/CodeGen/MIR/X86/stack-object-debug-info.mir
index d80b7d0bfcb1..a893b0836a62 100644
--- a/test/CodeGen/MIR/X86/stack-object-debug-info.mir
+++ b/test/CodeGen/MIR/X86/stack-object-debug-info.mir
@@ -46,7 +46,6 @@
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
diff --git a/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir b/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
index 2115a11ae693..12f731e2f551 100644
--- a/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
+++ b/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
@@ -15,7 +15,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/stack-object-operands.mir b/test/CodeGen/MIR/X86/stack-object-operands.mir
index 6ff15aef4d7f..1c5208ee30ea 100644
--- a/test/CodeGen/MIR/X86/stack-object-operands.mir
+++ b/test/CodeGen/MIR/X86/stack-object-operands.mir
@@ -17,7 +17,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/standalone-register-error.mir b/test/CodeGen/MIR/X86/standalone-register-error.mir
index b50393390289..c840dd52de11 100644
--- a/test/CodeGen/MIR/X86/standalone-register-error.mir
+++ b/test/CodeGen/MIR/X86/standalone-register-error.mir
@@ -7,7 +7,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/subreg-on-physreg.mir b/test/CodeGen/MIR/X86/subreg-on-physreg.mir
index f20195e7ddf5..740d706433ff 100644
--- a/test/CodeGen/MIR/X86/subreg-on-physreg.mir
+++ b/test/CodeGen/MIR/X86/subreg-on-physreg.mir
@@ -8,5 +8,5 @@ name: t
 body: |
   bb.0:
     ; CHECK: [[@LINE+1]]:19: subregister index expects a virtual register
-    %eax:sub_8bit = COPY %bl
+    %eax.sub_8bit = COPY %bl
 ...
diff --git a/test/CodeGen/MIR/X86/subregister-index-operands.mir b/test/CodeGen/MIR/X86/subregister-index-operands.mir
index a9a45adadf6e..e6c7c6e2e4ce 100644
--- a/test/CodeGen/MIR/X86/subregister-index-operands.mir
+++ b/test/CodeGen/MIR/X86/subregister-index-operands.mir
@@ -16,7 +16,6 @@
 # CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
 # CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/subregister-operands.mir b/test/CodeGen/MIR/X86/subregister-operands.mir
index a02bfe8359dc..6dd44aec07a9 100644
--- a/test/CodeGen/MIR/X86/subregister-operands.mir
+++ b/test/CodeGen/MIR/X86/subregister-operands.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
@@ -22,9 +21,9 @@ body: |
   bb.0.entry:
     liveins: %edi
     ; CHECK:      %0 = COPY %edi
-    ; CHECK-NEXT: %1 = COPY %0:sub_8bit
+    ; CHECK-NEXT: %1 = COPY %0.sub_8bit
     %0 = COPY %edi
-    %1 = COPY %0:sub_8bit
+    %1 = COPY %0.sub_8bit
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
index 8de31f3274df..512ba4e41aac 100644
--- a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
+++ b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
@@ -21,7 +21,7 @@
 name:            foo
 body: |
   ; CHECK-LABEL: bb.0.entry:
-  ; CHECK:         successors: %bb.1.less({{[0-9a-fx/= ]+}}33.00%), %bb.2.exit({{[0-9a-fx/= ]+}}67.00%)
+  ; CHECK:         successors: %bb.1.less(0x2a3d70a4), %bb.2.exit(0x55c28f5c)
   ; CHECK-LABEL: bb.1.less:
   bb.0.entry:
     successors: %bb.1.less (33), %bb.2.exit(67)
diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks.mir b/test/CodeGen/MIR/X86/successor-basic-blocks.mir
index 6f15f522bd5f..395272bb23c0 100644
--- a/test/CodeGen/MIR/X86/successor-basic-blocks.mir
+++ b/test/CodeGen/MIR/X86/successor-basic-blocks.mir
@@ -32,7 +32,7 @@
 name:            foo
 body: |
   ; CHECK-LABEL: bb.0.entry:
-  ; CHECK:         successors: %bb.1.less(0x40000000 / 0x80000000 = 50.00%), %bb.2.exit(0x40000000 / 0x80000000 = 50.00%)
+  ; CHECK:         successors: %bb.1.less(0x40000000), %bb.2.exit(0x40000000)
   ; CHECK-LABEL: bb.1.less:
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
@@ -58,7 +58,7 @@ body: |
   ; Verify that we can have multiple lists of successors that will be merged
   ; into one.
   ; CHECK-LABEL: bb.0.entry:
-  ; CHECK:         successors: %bb.1(0x80000000 / 0x80000000 = 100.00%), %bb.2(0x00000000 / 0x80000000 = 0.00%)
+  ; CHECK:         successors: %bb.1(0x80000000), %bb.2(0x00000000)
   bb.0.entry:
     liveins: %edi
     successors: %bb.1
diff --git a/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir b/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
index 05502fff4062..84a38bf8380c 100644
--- a/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
+++ b/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
diff --git a/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir b/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
index 18cb758408ff..35879b7036d3 100644
--- a/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
+++ b/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
@@ -14,7 +14,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/undefined-register-class.mir b/test/CodeGen/MIR/X86/undefined-register-class.mir
index 70b413b5ad37..f17fc7e8ef9c 100644
--- a/test/CodeGen/MIR/X86/undefined-register-class.mir
+++ b/test/CodeGen/MIR/X86/undefined-register-class.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   # CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200'
diff --git a/test/CodeGen/MIR/X86/undefined-stack-object.mir b/test/CodeGen/MIR/X86/undefined-stack-object.mir
index 5d40791b4c31..cbf0322860e5 100644
--- a/test/CodeGen/MIR/X86/undefined-stack-object.mir
+++ b/test/CodeGen/MIR/X86/undefined-stack-object.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/undefined-virtual-register.mir b/test/CodeGen/MIR/X86/undefined-virtual-register.mir
index fe41e0a4d2fc..8a6222481d68 100644
--- a/test/CodeGen/MIR/X86/undefined-virtual-register.mir
+++ b/test/CodeGen/MIR/X86/undefined-virtual-register.mir
@@ -12,15 +12,14 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
-    ; CHECK: [[@LINE+1]]:17: use of undefined virtual register '%10'
-    %eax = COPY %10
+    ; CHECK: Cannot determine class/bank of virtual register 1 in function 'test'
+    %eax = COPY %1
     RETQ %eax
 ...
 
diff --git a/test/CodeGen/MIR/X86/unexpected-type-phys.mir b/test/CodeGen/MIR/X86/unexpected-type-phys.mir
new file mode 100644
index 000000000000..df0f849bc182
--- /dev/null
+++ b/test/CodeGen/MIR/X86/unexpected-type-phys.mir
@@ -0,0 +1,13 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when a register operand is sized
+# but isn't generic, like a physical register.
+
+---
+name:            test_size_physreg
+registers:
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK: [[@LINE+1]]:10: unexpected type on physical register
+    %edi(s32) = G_ADD i32 %edi, %edi
+...
diff --git a/test/CodeGen/MIR/X86/unknown-metadata-node.mir b/test/CodeGen/MIR/X86/unknown-metadata-node.mir
index 793f9123776a..3c709eb9423e 100644
--- a/test/CodeGen/MIR/X86/unknown-metadata-node.mir
+++ b/test/CodeGen/MIR/X86/unknown-metadata-node.mir
@@ -39,7 +39,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir b/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
index 2d997b07dbd5..1f4f9c63157a 100644
--- a/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
+++ b/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/test/CodeGen/MIR/X86/unknown-subregister-index.mir
index 6ad6242f79a3..090ca52930a3 100644
--- a/test/CodeGen/MIR/X86/unknown-subregister-index.mir
+++ b/test/CodeGen/MIR/X86/unknown-subregister-index.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
@@ -22,7 +21,7 @@ body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
-    %1 = COPY %0:bit8
+    %1 = COPY %0.bit8
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
diff --git a/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
index 4d2350a01b8d..6ecfabc1b30f 100644
--- a/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
+++ b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/test/CodeGen/MIR/X86/virtual-registers.mir b/test/CodeGen/MIR/X86/virtual-registers.mir
index 3f7b0fdcc0e3..e63bcf4acdd1 100644
--- a/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -31,7 +31,6 @@
 ...
 ---
 name:            bar
-isSSA:           true
 tracksRegLiveness: true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gr32 }
@@ -65,7 +64,6 @@ body: |
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 # CHECK: name: foo
 # CHECK:      registers: