vendor/llvm/llvm-r130700

18 files changed, 888 insertions, 32 deletions

diff --git a/test/CodeGen/Mips/2008-07-22-Cstpool.ll b/test/CodeGen/Mips/2008-07-22-Cstpool.ll
index 20bd88889061..94dfe35faba1 100644
--- a/test/CodeGen/Mips/2008-07-22-Cstpool.ll
+++ b/test/CodeGen/Mips/2008-07-22-Cstpool.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=mips -o %t
 ; RUN: grep {CPI\[01\]_\[01\]:} %t | count 2
-; RUN: grep {rodata.cst4,"aM",@progbits} %t | count 1
+; RUN: grep {.rodata.cst4,"aM",@progbits} %t | count 1
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"
 
diff --git a/test/CodeGen/Mips/2008-07-23-fpcmp.ll b/test/CodeGen/Mips/2008-07-23-fpcmp.ll
index ca837ffd2a50..519e4b93a72b 100644
--- a/test/CodeGen/Mips/2008-07-23-fpcmp.ll
+++ b/test/CodeGen/Mips/2008-07-23-fpcmp.ll
@@ -2,6 +2,10 @@
 ; RUN: grep {c\\..*\\.s} %t | count 3
 ; RUN: grep {bc1\[tf\]} %t | count 3
 
+; FIXME: Disabled because branch instructions are generated where
+; conditional move instructions are expected.
+; REQUIRES: disabled
+
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"
 
diff --git a/test/CodeGen/Mips/2008-07-29-icmp.ll b/test/CodeGen/Mips/2008-07-29-icmp.ll
index 52a4b081ddb3..e85a749f7dcd 100644
--- a/test/CodeGen/Mips/2008-07-29-icmp.ll
+++ b/test/CodeGen/Mips/2008-07-29-icmp.ll
@@ -1,5 +1,9 @@
 ; RUN: llc < %s -march=mips | grep {b\[ne\]\[eq\]} | count 1
 
+; FIXME: Disabled because branch instructions are generated where
+; conditional move instructions are expected.
+; REQUIRES: disabled
+
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"
 
diff --git a/test/CodeGen/Mips/2008-08-06-Alloca.ll b/test/CodeGen/Mips/2008-08-06-Alloca.ll
index 7be7974e0ffe..6dd4af111cd9 100644
--- a/test/CodeGen/Mips/2008-08-06-Alloca.ll
+++ b/test/CodeGen/Mips/2008-08-06-Alloca.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2
+; RUN: llc < %s -march=mips -regalloc=basic | grep {subu.*sp} | count 2
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"
diff --git a/test/CodeGen/Mips/2010-07-20-Select.ll b/test/CodeGen/Mips/2010-07-20-Select.ll
index 891b5d9e1884..e5e2c5473770 100644
--- a/test/CodeGen/Mips/2010-07-20-Select.ll
+++ b/test/CodeGen/Mips/2010-07-20-Select.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s
+; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
 ; Fix PR7473
 
 define i32 @main() nounwind readnone {
@@ -9,12 +10,12 @@ entry:
   volatile store i32 0, i32* %c, align 4
   %0 = volatile load i32* %a, align 4             ; <i32> [#uses=1]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
-; CHECK: addiu $3, $zero, 0
+; CHECK: addiu $[[R1:[0-9]+]], $zero, 0
   %iftmp.0.0 = select i1 %1, i32 3, i32 0         ; <i32> [#uses=1]
   %2 = volatile load i32* %c, align 4             ; <i32> [#uses=1]
   %3 = icmp eq i32 %2, 0                          ; <i1> [#uses=1]
-; CHECK: addiu $3, $zero, 3
-; CHECK: addu $2, $5, $3
+; CHECK: addiu $[[R1]], $zero, 3
+; CHECK: addu $2, ${{.}}, $[[R1]]
   %iftmp.2.0 = select i1 %3, i32 0, i32 5         ; <i32> [#uses=1]
   %4 = add nsw i32 %iftmp.2.0, %iftmp.0.0         ; <i32> [#uses=1]
   ret i32 %4
diff --git a/test/CodeGen/Mips/addc.ll b/test/CodeGen/Mips/addc.ll
new file mode 100644
index 000000000000..e5d05b1d6dbb
--- /dev/null
+++ b/test/CodeGen/Mips/addc.ll
@@ -0,0 +1,13 @@
+; RUN: llc  < %s -march=mipsel | FileCheck %s 
+; RUN: llc  < %s -march=mips   | FileCheck %s
+
+define void @f(i64 %l, i64* nocapture %p) nounwind {
+entry:
+; CHECK: lui  
+; CHECK: ori
+; CHECK: addu  
+  %add = add i64 %l, 1311768467294899695
+  store i64 %add, i64* %p, align 4 
+  ret void
+}
+
diff --git a/test/CodeGen/Mips/analyzebranch.ll b/test/CodeGen/Mips/analyzebranch.ll
new file mode 100644
index 000000000000..8f0bdf286c52
--- /dev/null
+++ b/test/CodeGen/Mips/analyzebranch.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=mips < %s | FileCheck %s
+
+define double @foo(double %a, double %b) nounwind readnone {
+entry:
+; CHECK: bc1f $BB0_2
+; CHECK: nop
+; CHECK: # BB#1:    
+
+  %cmp = fcmp ogt double %a, 0.000000e+00
+  br i1 %cmp, label %if.end6, label %if.else
+
+if.else:                                          ; preds = %entry
+  %cmp3 = fcmp ogt double %b, 0.000000e+00
+  br i1 %cmp3, label %if.end6, label %return
+
+if.end6:                                          ; preds = %if.else, %entry
+  %c.0 = phi double [ %a, %entry ], [ 0.000000e+00, %if.else ]
+  %sub = fsub double %b, %c.0
+  %mul = fmul double %sub, 2.000000e+00
+  br label %return
+
+return:                                           ; preds = %if.else, %if.end6
+  %retval.0 = phi double [ %mul, %if.end6 ], [ 0.000000e+00, %if.else ]
+  ret double %retval.0
+}
+
+define void @f1(float %f) nounwind {
+entry:
+; CHECK: bc1t $BB1_2
+; CHECK: nop
+; CHECK: # BB#1:      
+  %cmp = fcmp une float %f, 0.000000e+00
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  tail call void @abort() noreturn
+  unreachable
+
+if.end:                                           ; preds = %entry
+  tail call void (...)* @f2() nounwind
+  ret void
+}
+
+declare void @abort() noreturn nounwind
+
+declare void @f2(...)
diff --git a/test/CodeGen/Mips/blockaddr.ll b/test/CodeGen/Mips/blockaddr.ll
new file mode 100644
index 000000000000..e9af3045e15f
--- /dev/null
+++ b/test/CodeGen/Mips/blockaddr.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC
+; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC
+
+@reg = common global i8* null, align 4
+
+define i8* @dummy(i8* %x) nounwind readnone noinline {
+entry:
+  ret i8* %x
+}
+
+; CHECK-PIC: lw  $[[R0:[0-9]+]], %got($tmp1)($gp)
+; CHECK-PIC: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp1)
+; CHECK-PIC: lw  $[[R1:[0-9]+]], %got($tmp2)($gp)
+; CHECK-PIC: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp2)
+; CHECK-STATIC: lui  $[[R2:[0-9]+]], %hi($tmp1)
+; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp1)
+; CHECK-STATIC: lui   $[[R3:[0-9]+]], %hi($tmp2)
+; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp2)
+define void @f() nounwind {
+entry:
+  %call = tail call i8* @dummy(i8* blockaddress(@f, %baz))
+  indirectbr i8* %call, [label %baz, label %foo]
+
+foo:                                              ; preds = %foo, %entry
+  store i8* blockaddress(@f, %foo), i8** @reg, align 4
+  br label %foo
+
+baz:                                              ; preds = %entry
+  store i8* null, i8** @reg, align 4
+  ret void
+}
diff --git a/test/CodeGen/Mips/buildpairextractelementf64.ll b/test/CodeGen/Mips/buildpairextractelementf64.ll
new file mode 100644
index 000000000000..585bc250fb8c
--- /dev/null
+++ b/test/CodeGen/Mips/buildpairextractelementf64.ll
@@ -0,0 +1,23 @@
+; RUN: llc  < %s -march=mipsel | FileCheck %s
+; RUN: llc  < %s -march=mips   | FileCheck %s
+@a = external global i32
+
+define double @f(i32 %a1, double %d) nounwind {
+entry:
+; CHECK: mtc1
+; CHECK: mtc1
+  store i32 %a1, i32* @a, align 4
+  %add = fadd double %d, 2.000000e+00
+  ret double %add
+}
+
+define void @f3(double %d, i32 %a1) nounwind {
+entry:
+; CHECK: mfc1
+; CHECK: mfc1
+  tail call void @f2(i32 %a1, double %d) nounwind
+  ret void
+}
+
+declare void @f2(i32, double)
+
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index 7d3e0252e3c9..8329c891f0c2 100755
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -1,10 +1,11 @@
 ; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=4ke -regalloc=basic < %s | FileCheck %s
 
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
-; CHECK:  lw  $3, %got(i3)($gp)
-; CHECK:  addiu $5, $gp, %got(i1)
+; CHECK:  lw  ${{[0-9]+}}, %got(i3)($gp)
+; CHECK:  addiu ${{[0-9]+}}, $gp, %got(i1)
 define i32* @cmov1(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
diff --git a/test/CodeGen/Mips/divrem.ll b/test/CodeGen/Mips/divrem.ll
new file mode 100644
index 000000000000..398d1b78bd43
--- /dev/null
+++ b/test/CodeGen/Mips/divrem.ll
@@ -0,0 +1,51 @@
+; RUN: llc -march=mips < %s | FileCheck %s
+
+; CHECK: div $zero,
+define i32 @sdiv1(i32 %a0, i32 %a1) nounwind readnone {
+entry:
+  %div = sdiv i32 %a0, %a1
+  ret i32 %div
+}
+
+; CHECK: div $zero,
+define i32 @srem1(i32 %a0, i32 %a1) nounwind readnone {
+entry:
+  %rem = srem i32 %a0, %a1
+  ret i32 %rem
+}
+
+; CHECK: divu $zero,
+define i32 @udiv1(i32 %a0, i32 %a1) nounwind readnone {
+entry:
+  %div = udiv i32 %a0, %a1
+  ret i32 %div
+}
+
+; CHECK: divu $zero,
+define i32 @urem1(i32 %a0, i32 %a1) nounwind readnone {
+entry:
+  %rem = urem i32 %a0, %a1
+  ret i32 %rem
+}
+
+; CHECK: div $zero,
+define i32 @sdivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind {
+entry:
+  %rem = srem i32 %a0, %a1
+  store i32 %rem, i32* %r, align 4, !tbaa !0
+  %div = sdiv i32 %a0, %a1
+  ret i32 %div
+}
+
+; CHECK: divu $zero,
+define i32 @udivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind {
+entry:
+  %rem = urem i32 %a0, %a1
+  store i32 %rem, i32* %r, align 4, !tbaa !0
+  %div = udiv i32 %a0, %a1
+  ret i32 %div
+}
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
diff --git a/test/CodeGen/Mips/fpbr.ll b/test/CodeGen/Mips/fpbr.ll
new file mode 100644
index 000000000000..0a6478b0f8f0
--- /dev/null
+++ b/test/CodeGen/Mips/fpbr.ll
@@ -0,0 +1,119 @@
+; RUN: llc  < %s -march=mipsel | FileCheck %s
+
+define void @func0(float %f2, float %f3) nounwind {
+entry:
+; CHECK: c.eq.s
+; CHECK: bc1f
+  %cmp = fcmp oeq float %f2, %f3
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  tail call void (...)* @g0() nounwind
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void (...)* @g1() nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+declare void @g0(...)
+
+declare void @g1(...)
+
+define void @func1(float %f2, float %f3) nounwind {
+entry:
+; CHECK: c.olt.s
+; CHECK: bc1f
+  %cmp = fcmp olt float %f2, %f3
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  tail call void (...)* @g0() nounwind
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void (...)* @g1() nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+define void @func2(float %f2, float %f3) nounwind {
+entry:
+; CHECK: c.ole.s
+; CHECK: bc1f
+  %cmp = fcmp ugt float %f2, %f3
+  br i1 %cmp, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  tail call void (...)* @g0() nounwind
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void (...)* @g1() nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+define void @func3(double %f2, double %f3) nounwind {
+entry:
+; CHECK: c.eq.d
+; CHECK: bc1f
+  %cmp = fcmp oeq double %f2, %f3
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  tail call void (...)* @g0() nounwind
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void (...)* @g1() nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+define void @func4(double %f2, double %f3) nounwind {
+entry:
+; CHECK: c.olt.d
+; CHECK: bc1f
+  %cmp = fcmp olt double %f2, %f3
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  tail call void (...)* @g0() nounwind
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void (...)* @g1() nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+define void @func5(double %f2, double %f3) nounwind {
+entry:
+; CHECK: c.ole.d
+; CHECK: bc1f
+  %cmp = fcmp ugt double %f2, %f3
+  br i1 %cmp, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  tail call void (...)* @g0() nounwind
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void (...)* @g1() nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
diff --git a/test/CodeGen/Mips/fpcmp.ll b/test/CodeGen/Mips/fpcmp.ll
new file mode 100644
index 000000000000..c89ffe67f1b9
--- /dev/null
+++ b/test/CodeGen/Mips/fpcmp.ll
@@ -0,0 +1,23 @@
+; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
+; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1
+
+@g1 = external global i32
+
+define i32 @f(float %f0, float %f1) nounwind {
+entry:
+; CHECK-MIPS32R2: c.olt.s
+; CHECK-MIPS32R2: movt
+; CHECK-MIPS32R2: c.olt.s
+; CHECK-MIPS32R2: movt
+; CHECK-MIPS1: c.olt.s
+; CHECK-MIPS1: bc1t
+; CHECK-MIPS1: c.olt.s
+; CHECK-MIPS1: bc1t
+  %cmp = fcmp olt float %f0, %f1
+  %conv = zext i1 %cmp to i32
+  %tmp2 = load i32* @g1, align 4
+  %add = add nsw i32 %tmp2, %conv
+  store i32 %add, i32* @g1, align 4
+  %cond = select i1 %cmp, i32 10, i32 20
+  ret i32 %cond
+}
diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll
new file mode 100644
index 000000000000..fdfa01a9e0f7
--- /dev/null
+++ b/test/CodeGen/Mips/internalfunc.ll
@@ -0,0 +1,52 @@
+; RUN: llc  < %s -march=mips | FileCheck %s
+
+@caller.sf1 = internal unnamed_addr global void (...)* null, align 4
+@gf1 = external global void (...)*
+@.str = private unnamed_addr constant [3 x i8] c"f2\00"
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+; CHECK: lw $[[R0:[0-9]+]], %got(f2)($gp)
+; CHECK: addiu $25, $[[R0]], %lo(f2)
+  tail call fastcc void @f2()
+  ret i32 0
+}
+
+define void @caller(i32 %a0, i32 %a1) nounwind {
+entry:
+; CHECK: lw  $[[R1:[0-9]+]], %got(caller.sf1)($gp)
+; CHECK: addiu ${{[0-9]+}}, $[[R1]], %lo(caller.sf1)
+  %tobool = icmp eq i32 %a1, 0
+  br i1 %tobool, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %tmp1 = load void (...)** @caller.sf1, align 4
+  tail call void (...)* %tmp1() nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+; CHECK: lw  $[[R2:[0-9]+]], %got(sf2)($gp)
+; CHECK: lw  $[[R3:[0-9]+]], %got(caller.sf1)($gp)
+; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2)
+; CHECK: addiu ${{[0-9]+}}, $[[R3]], %lo(caller.sf1)
+  %tobool3 = icmp ne i32 %a0, 0
+  %tmp4 = load void (...)** @gf1, align 4
+  %cond = select i1 %tobool3, void (...)* %tmp4, void (...)* bitcast (void ()* @sf2 to void (...)*)
+  store void (...)* %cond, void (...)** @caller.sf1, align 4
+  ret void
+}
+
+define internal void @sf2() nounwind {
+entry:
+  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0)) nounwind
+  ret void
+}
+
+declare i32 @printf(i8* nocapture, ...) nounwind
+
+define internal fastcc void @f2() nounwind noinline {
+entry:
+  %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0)) nounwind
+  ret void
+}
+
diff --git a/test/CodeGen/Mips/largeimm1.ll b/test/CodeGen/Mips/largeimm1.ll
new file mode 100644
index 000000000000..d65cc025d085
--- /dev/null
+++ b/test/CodeGen/Mips/largeimm1.ll
@@ -0,0 +1,13 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+; CHECK: lui $at, 49152
+; CHECK: lui $at, 16384
+define void @f() nounwind {
+entry:
+  %a1 = alloca [1073741824 x i8], align 1
+  %arrayidx = getelementptr inbounds [1073741824 x i8]* %a1, i32 0, i32 1048676
+  call void @f2(i8* %arrayidx) nounwind
+  ret void
+}
+
+declare void @f2(i8*)
diff --git a/test/CodeGen/Mips/o32_cc.ll b/test/CodeGen/Mips/o32_cc.ll
index b6df62be6603..3974cd4a6a76 100644
--- a/test/CodeGen/Mips/o32_cc.ll
+++ b/test/CodeGen/Mips/o32_cc.ll
@@ -61,8 +61,8 @@ entry:
 declare void @f4(i32, i32, i32, i32)
 
 ; $f12, $6, stack
-; CHECK: sw  $2, 16($sp)
-; CHECK: sw  $zero, 20($sp)
+; CHECK: sw
+; CHECK: sw
 ; CHECK: ldc1 $f12, %lo
 ; CHECK: addiu $6, $zero, 23
 define void @testlowercall5() nounwind {
@@ -98,8 +98,8 @@ entry:
 declare void @f7(float, i32, i32)
 
 ; $4, $5, $6, stack
-; CHECK: sw  $2, 16($sp)
-; CHECK: sw  $zero, 20($sp)
+; CHECK: sw
+; CHECK: sw
 ; CHECK: addiu $4, $zero, 22
 ; CHECK: addiu $5, $zero, 53
 ; CHECK: addiu $6, $zero, 44
@@ -115,7 +115,7 @@ declare void @f8(i32, i32, i32, double)
 ; CHECK: addiu $4, $zero, 32
 ; CHECK: addiu $5, $zero, 63
 ; CHECK: addiu $6, $zero, 54
-; CHECK: ori $7, $2, 0
+; CHECK: ori $7
 define void @testlowercall9() nounwind {
 entry:
   tail call void @f9(i32 32, i32 63, i32 54, float 1.100000e+01) nounwind
@@ -128,7 +128,7 @@ declare void @f9(i32, i32, i32, float)
 ; CHECK: addiu $4, $zero, 42
 ; CHECK: addiu $5, $zero, 73
 ; CHECK: addiu $6, $zero, 0
-; CHECK: ori $7, $2, 0
+; CHECK: ori $7
 define void @testlowercall10() nounwind {
 entry:
   tail call void @f10(i32 42, i32 73, double 2.700000e+01) nounwind
@@ -140,7 +140,7 @@ declare void @f10(i32, i32, double)
 ; $4, ($6, $7)
 ; CHECK: addiu $4, $zero, 52
 ; CHECK: addiu $6, $zero, 0
-; CHECK: ori $7, $2, 0
+; CHECK: ori $7
 define void @testlowercall11() nounwind {
 entry:
   tail call void @f11(i32 52, double 1.600000e+01) nounwind
@@ -152,8 +152,8 @@ declare void @f11(i32, double)
 ; $f12, $f14, $6, $7
 ; CHECK: lwc1 $f12, %lo
 ; CHECK: lwc1 $f14, %lo
-; CHECK: ori $6, $4, 0
-; CHECK: ori $7, $5, 0
+; CHECK: ori $6
+; CHECK: ori $7
 define void @testlowercall12() nounwind {
 entry:
   tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind
@@ -165,7 +165,7 @@ declare void @f12(float, float, float, float)
 ; $f12, $5, $6, $7
 ; CHECK: lwc1 $f12, %lo
 ; CHECK: addiu $5, $zero, 83
-; CHECK: ori $6, $3, 0
+; CHECK: ori $6
 ; CHECK: addiu $7, $zero, 25
 define void @testlowercall13() nounwind {
 entry:
@@ -179,7 +179,7 @@ declare void @f13(float, i32, float, i32)
 ; $f12, $f14, $7
 ; CHECK: ldc1 $f12, %lo
 ; CHECK: lwc1 $f14, %lo
-; CHECK: ori $7, $4, 0
+; CHECK: ori $7
 define void @testlowercall14() nounwind {
 entry:
   tail call void @f14(double 3.500000e+01, float 2.900000e+01, float 3.000000e+01) nounwind
@@ -192,7 +192,7 @@ declare void @f14(double, float, float)
 ; CHECK: lwc1 $f12, %lo
 ; CHECK: lwc1 $f14, %lo
 ; CHECK: addiu $6, $zero, 0
-; CHECK: ori $7, $4, 32768
+; CHECK: ori $7
 define void @testlowercall15() nounwind {
 entry:
   tail call void @f15(float 4.800000e+01, float 3.900000e+01, double 3.700000e+01) nounwind
@@ -203,9 +203,9 @@ declare void @f15(float, float, double)
 
 ; $4, $5, $6, $7
 ; CHECK: addiu $4, $zero, 62
-; CHECK: ori $5, $2, 0
+; CHECK: ori $5
 ; CHECK: addiu $6, $zero, 64
-; CHECK: ori $7, $3, 0
+; CHECK: ori $7
 define void @testlowercall16() nounwind {
 entry:
   tail call void @f16(i32 62, float 4.900000e+01, i32 64, float 3.100000e+01) nounwind
@@ -216,7 +216,7 @@ declare void @f16(i32, float, i32, float)
 
 ; $4, $5, $6, $7
 ; CHECK: addiu $4, $zero, 72
-; CHECK: ori $5, $2, 0
+; CHECK: ori $5
 ; CHECK: addiu $6, $zero, 74
 ; CHECK: addiu $7, $zero, 35
 define void @testlowercall17() nounwind {
@@ -230,7 +230,7 @@ declare void @f17(i32, float, i32, i32)
 ; $4, $5, $6, $7
 ; CHECK: addiu $4, $zero, 82
 ; CHECK: addiu $5, $zero, 93
-; CHECK: ori $6, $2, 0
+; CHECK: ori $6
 ; CHECK: addiu $7, $zero, 45
 define void @testlowercall18() nounwind {
 entry:
@@ -242,11 +242,11 @@ declare void @f18(i32, i32, float, i32)
 
 
 ; $4, ($6, $7), stack
-; CHECK: sw  $2, 16($sp)
-; CHECK: sw  $zero, 20($sp)
+; CHECK: sw
+; CHECK: sw
 ; CHECK: addiu $4, $zero, 92
 ; CHECK: addiu $6, $zero, 0
-; CHECK: ori $7, $3, 0
+; CHECK: ori $7
 define void @testlowercall20() nounwind {
 entry:
   tail call void @f20(i32 92, double 2.600000e+01, double 4.700000e+01) nounwind
@@ -270,7 +270,7 @@ declare void @f21(float, i32)
 ; CHECK: lwc1 $f12, %lo
 ; CHECK: addiu $5, $zero, 113
 ; CHECK: addiu $6, $zero, 0
-; CHECK: ori $7, $3, 32768
+; CHECK: ori $7
 define void @testlowercall22() nounwind {
 entry:
   tail call void @f22(float 6.800000e+01, i32 113, double 5.700000e+01) nounwind
@@ -291,8 +291,8 @@ entry:
 declare void @f23(double, i32)
 
 ; $f12,$6, stack
-; CHECK: sw  $2, 16($sp)
-; CHECK: sw  $zero, 20($sp)
+; CHECK: sw
+; CHECK: sw
 ; CHECK: ldc1 $f12, %lo
 ; CHECK: addiu $6, $zero, 133
 define void @testlowercall24() nounwind {
@@ -306,15 +306,15 @@ declare void @f24(double, i32, double)
 ; CHECK: lwc1 $f12, %lo
 ; lwc1 $f12, %lo
 ; CHECK: lwc1 $f14, %lo
-; CHECK: ori $6, $4, 0
-; CHECK: ori $7, $5, 0
+; CHECK: ori $6
+; CHECK: ori $7
 ; CHECK: lwc1 $f12, %lo
 ; CHECK: addiu $5, $zero, 83
-; CHECK: ori $6, $3, 0
+; CHECK: ori $6
 ; CHECK: addiu $7, $zero, 25
 ; CHECK: addiu $4, $zero, 82
 ; CHECK: addiu $5, $zero, 93
-; CHECK: ori $6, $2, 0
+; CHECK: ori $6
 ; CHECK: addiu $7, $zero, 45
 define void @testlowercall25() nounwind {
 entry:
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll
new file mode 100644
index 000000000000..1f71ed2640eb
--- /dev/null
+++ b/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -0,0 +1,278 @@
+; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s -regalloc=basic | FileCheck %s
+
+
+; All test functions do the same thing - they return the first variable
+; argument.
+
+; All CHECK's do the same thing - they check whether variable arguments from
+; registers are placed on correct stack locations, and whether the first
+; variable argument is returned from the correct stack location.
+
+
+declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_end(i8*) nounwind
+
+; return int
+define i32 @va1(i32 %a, ...) nounwind {
+entry:
+  %a.addr = alloca i32, align 4
+  %ap = alloca i8*, align 4
+  %b = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, i32
+  store i32 %0, i32* %b, align 4
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load i32* %b, align 4
+  ret i32 %tmp
+
+; CHECK: va1:
+; CHECK: addiu   $sp, $sp, -32
+; CHECK: sw      $7, 44($sp)
+; CHECK: sw      $6, 40($sp)
+; CHECK: sw      $5, 36($sp)
+; CHECK: lw      $2, 36($sp)
+}
+
+; check whether the variable double argument will be accessed from the 8-byte
+; aligned location (i.e. whether the address is computed by adding 7 and
+; clearing lower 3 bits)
+define double @va2(i32 %a, ...) nounwind {
+entry:
+  %a.addr = alloca i32, align 4
+  %ap = alloca i8*, align 4
+  %b = alloca double, align 8
+  store i32 %a, i32* %a.addr, align 4
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, double
+  store double %0, double* %b, align 8
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load double* %b, align 8
+  ret double %tmp
+
+; CHECK: va2:
+; CHECK: addiu   $sp, $sp, -40
+; CHECK: sw      $7, 52($sp)
+; CHECK: sw      $6, 48($sp)
+; CHECK: sw      $5, 44($sp)
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 44
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
+}
+
+; int
+define i32 @va3(double %a, ...) nounwind {
+entry:
+  %a.addr = alloca double, align 8
+  %ap = alloca i8*, align 4
+  %b = alloca i32, align 4
+  store double %a, double* %a.addr, align 8
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, i32
+  store i32 %0, i32* %b, align 4
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load i32* %b, align 4
+  ret i32 %tmp
+
+; CHECK: va3:
+; CHECK: addiu   $sp, $sp, -40
+; CHECK: sw      $7, 52($sp)
+; CHECK: sw      $6, 48($sp)
+; CHECK: lw      $2, 48($sp)
+}
+
+; double
+define double @va4(double %a, ...) nounwind {
+entry:
+  %a.addr = alloca double, align 8
+  %ap = alloca i8*, align 4
+  %b = alloca double, align 8
+  store double %a, double* %a.addr, align 8
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, double
+  store double %0, double* %b, align 8
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load double* %b, align 8
+  ret double %tmp
+
+; CHECK: va4:
+; CHECK: addiu   $sp, $sp, -48
+; CHECK: sw      $7, 60($sp)
+; CHECK: sw      $6, 56($sp)
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 56
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
+}
+
+; int
+define i32 @va5(i32 %a, i32 %b, i32 %c, ...) nounwind {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  %ap = alloca i8*, align 4
+  %d = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  store i32 %c, i32* %c.addr, align 4
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, i32
+  store i32 %0, i32* %d, align 4
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load i32* %d, align 4
+  ret i32 %tmp
+
+; CHECK: va5:
+; CHECK: addiu   $sp, $sp, -40
+; CHECK: sw      $7, 52($sp)
+; CHECK: lw      $2, 52($sp)
+}
+
+; double
+define double @va6(i32 %a, i32 %b, i32 %c, ...) nounwind {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  %ap = alloca i8*, align 4
+  %d = alloca double, align 8
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  store i32 %c, i32* %c.addr, align 4
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, double
+  store double %0, double* %d, align 8
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load double* %d, align 8
+  ret double %tmp
+
+; CHECK: va6:
+; CHECK: addiu   $sp, $sp, -48
+; CHECK: sw      $7, 60($sp)
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 60
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
+}
+
+; int
+define i32 @va7(i32 %a, double %b, ...) nounwind {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca double, align 8
+  %ap = alloca i8*, align 4
+  %c = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store double %b, double* %b.addr, align 8
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, i32
+  store i32 %0, i32* %c, align 4
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load i32* %c, align 4
+  ret i32 %tmp
+
+; CHECK: va7:
+; CHECK: addiu   $sp, $sp, -40
+; CHECK: lw      $2, 56($sp)
+}
+
+; double
+define double @va8(i32 %a, double %b, ...) nounwind {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca double, align 8
+  %ap = alloca i8*, align 4
+  %c = alloca double, align 8
+  store i32 %a, i32* %a.addr, align 4
+  store double %b, double* %b.addr, align 8
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, double
+  store double %0, double* %c, align 8
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load double* %c, align 8
+  ret double %tmp
+
+; CHECK: va8:
+; CHECK: addiu   $sp, $sp, -48
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 64
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
+}
+
+; int
+define i32 @va9(double %a, double %b, i32 %c, ...) nounwind {
+entry:
+  %a.addr = alloca double, align 8
+  %b.addr = alloca double, align 8
+  %c.addr = alloca i32, align 4
+  %ap = alloca i8*, align 4
+  %d = alloca i32, align 4
+  store double %a, double* %a.addr, align 8
+  store double %b, double* %b.addr, align 8
+  store i32 %c, i32* %c.addr, align 4
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, i32
+  store i32 %0, i32* %d, align 4
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load i32* %d, align 4
+  ret i32 %tmp
+
+; CHECK: va9:
+; CHECK: addiu   $sp, $sp, -56
+; CHECK: lw      $2, 76($sp)
+}
+
+; double
+define double @va10(double %a, double %b, i32 %c, ...) nounwind {
+entry:
+  %a.addr = alloca double, align 8
+  %b.addr = alloca double, align 8
+  %c.addr = alloca i32, align 4
+  %ap = alloca i8*, align 4
+  %d = alloca double, align 8
+  store double %a, double* %a.addr, align 8
+  store double %b, double* %b.addr, align 8
+  store i32 %c, i32* %c.addr, align 4
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %0 = va_arg i8** %ap, double
+  store double %0, double* %d, align 8
+  %ap2 = bitcast i8** %ap to i8*
+  call void @llvm.va_end(i8* %ap2)
+  %tmp = load double* %d, align 8
+  ret double %tmp
+
+; CHECK: va10:
+; CHECK: addiu   $sp, $sp, -56
+; CHECK: addiu   $[[R0:[0-9]+]], $sp, 76
+; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu   $[[R2:[0-9]+]], $zero, -8
+; CHECK: and     $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1    $f0, 0($[[R3]])
+}
diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll
new file mode 100644
index 000000000000..c83fa3ece026
--- /dev/null
+++ b/test/CodeGen/Mips/select.ll
@@ -0,0 +1,196 @@
+; RUN: llc  < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
+; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1
+
+@d2 = external global double
+@d3 = external global double
+
+define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: movn
+; CHECK-MIPS1: beq
+  %tobool = icmp ne i32 %s, 0
+  %cond = select i1 %tobool, i32 %f1, i32 %f0
+  ret i32 %cond
+}
+
+define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: movn.s
+; CHECK-MIPS1: beq
+  %tobool = icmp ne i32 %s, 0
+  %cond = select i1 %tobool, float %f0, float %f1
+  ret float %cond
+}
+
+define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: movn.d
+; CHECK-MIPS1: beq
+  %tobool = icmp ne i32 %s, 0
+  %cond = select i1 %tobool, double %f0, double %f1
+  ret double %cond
+}
+
+define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.eq.s
+; CHECK-MIPS32R2: movt.s
+; CHECK-MIPS1: c.eq.s
+; CHECK-MIPS1: bc1f
+  %cmp = fcmp oeq float %f2, %f3
+  %cond = select i1 %cmp, float %f0, float %f1
+  ret float %cond
+}
+
+define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.olt.s
+; CHECK-MIPS32R2: movt.s
+; CHECK-MIPS1: c.olt.s
+; CHECK-MIPS1: bc1f
+  %cmp = fcmp olt float %f2, %f3
+  %cond = select i1 %cmp, float %f0, float %f1
+  ret float %cond
+}
+
+define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.ule.s
+; CHECK-MIPS32R2: movf.s
+; CHECK-MIPS1: c.ule.s
+; CHECK-MIPS1: bc1t
+  %cmp = fcmp ogt float %f2, %f3
+  %cond = select i1 %cmp, float %f0, float %f1
+  ret float %cond
+}
+
+define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.ule.s
+; CHECK-MIPS32R2: movf.d
+; CHECK-MIPS1: c.ule.s
+; CHECK-MIPS1: bc1t
+  %cmp = fcmp ogt float %f2, %f3
+  %cond = select i1 %cmp, double %f0, double %f1
+  ret double %cond
+}
+
+define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.eq.d
+; CHECK-MIPS32R2: movt.d
+; CHECK-MIPS1: c.eq.d
+; CHECK-MIPS1: bc1f
+  %cmp = fcmp oeq double %f2, %f3
+  %cond = select i1 %cmp, double %f0, double %f1
+  ret double %cond
+}
+
+define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.olt.d
+; CHECK-MIPS32R2: movt.d
+; CHECK-MIPS1: c.olt.d
+; CHECK-MIPS1: bc1f
+  %cmp = fcmp olt double %f2, %f3
+  %cond = select i1 %cmp, double %f0, double %f1
+  ret double %cond
+}
+
+define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.ule.d
+; CHECK-MIPS32R2: movf.d
+; CHECK-MIPS1: c.ule.d
+; CHECK-MIPS1: bc1t
+  %cmp = fcmp ogt double %f2, %f3
+  %cond = select i1 %cmp, double %f0, double %f1
+  ret double %cond
+}
+
+define float @sel8_1(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.ule.d
+; CHECK-MIPS32R2: movf.s
+; CHECK-MIPS1: c.ule.d
+; CHECK-MIPS1: bc1t
+  %cmp = fcmp ogt double %f2, %f3
+  %cond = select i1 %cmp, float %f0, float %f1
+  ret float %cond
+}
+
+define i32 @sel9(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.eq.s
+; CHECK-MIPS32R2: movt
+; CHECK-MIPS1: c.eq.s
+; CHECK-MIPS1: bc1f
+  %cmp = fcmp oeq float %f2, %f3
+  %cond = select i1 %cmp, i32 %f0, i32 %f1
+  ret i32 %cond
+}
+
+define i32 @sel10(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.olt.s
+; CHECK-MIPS32R2: movt
+; CHECK-MIPS1: c.olt.s
+; CHECK-MIPS1: bc1f
+  %cmp = fcmp olt float %f2, %f3
+  %cond = select i1 %cmp, i32 %f0, i32 %f1
+  ret i32 %cond
+}
+
+define i32 @sel11(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
+entry:
+; CHECK-MIPS32R2: c.ule.s
+; CHECK-MIPS32R2: movf
+; CHECK-MIPS1: c.ule.s
+; CHECK-MIPS1: bc1t
+  %cmp = fcmp ogt float %f2, %f3
+  %cond = select i1 %cmp, i32 %f0, i32 %f1
+  ret i32 %cond
+}
+
+define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly {
+entry:
+; CHECK-MIPS32R2: c.eq.d
+; CHECK-MIPS32R2: movt
+; CHECK-MIPS1: c.eq.d
+; CHECK-MIPS1: bc1f
+  %tmp = load double* @d2, align 8, !tbaa !0
+  %tmp1 = load double* @d3, align 8, !tbaa !0
+  %cmp = fcmp oeq double %tmp, %tmp1
+  %cond = select i1 %cmp, i32 %f0, i32 %f1
+  ret i32 %cond
+}
+
+define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly {
+entry:
+; CHECK-MIPS32R2: c.olt.d
+; CHECK-MIPS32R2: movt
+; CHECK-MIPS1: c.olt.d
+; CHECK-MIPS1: bc1f
+  %tmp = load double* @d2, align 8, !tbaa !0
+  %tmp1 = load double* @d3, align 8, !tbaa !0
+  %cmp = fcmp olt double %tmp, %tmp1
+  %cond = select i1 %cmp, i32 %f0, i32 %f1
+  ret i32 %cond
+}
+
+define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly {
+entry:
+; CHECK-MIPS32R2: c.ule.d
+; CHECK-MIPS32R2: movf
+; CHECK-MIPS1: c.ule.d
+; CHECK-MIPS1: bc1t
+  %tmp = load double* @d2, align 8, !tbaa !0
+  %tmp1 = load double* @d3, align 8, !tbaa !0
+  %cmp = fcmp ogt double %tmp, %tmp1
+  %cond = select i1 %cmp, i32 %f0, i32 %f1
+  ret i32 %cond
+}
+
+!0 = metadata !{metadata !"double", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}