vendor/llvm/llvm-trunk-r306325

9 files changed, 349 insertions, 56 deletions

diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index 5f1555e77af4..9540249eaedc 100644
--- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -8,15 +8,15 @@ entry:
 ; Note that part of what is being checked here is proper register reuse.
 ; CHECK: mfcr [[T1:r[0-9]+]]                         ; cr2
 ; CHECK: lis [[T2:r[0-9]+]], 1
-; CHECK: addi r3, r1, 72
 ; CHECK: rotlwi [[T1]], [[T1]], 8
 ; CHECK: ori [[T2]], [[T2]], 34540
 ; CHECK: stwx [[T1]], r1, [[T2]]
-; CHECK: lis [[T3:r[0-9]+]], 1
 ; CHECK: mfcr [[T4:r[0-9]+]]                         ; cr3
-; CHECK: ori [[T3]], [[T3]], 34536
+; CHECK: lis [[T3:r[0-9]+]], 1
 ; CHECK: rotlwi [[T4]], [[T4]], 12
+; CHECK: ori [[T3]], [[T3]], 34536
 ; CHECK: stwx [[T4]], r1, [[T3]]
+; CHECK: addi r3, r1, 72
   %x = alloca [100000 x i8]                       ; <[100000 x i8]*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   %x1 = bitcast [100000 x i8]* %x to i8*          ; <i8*> [#uses=1]
diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll
index ec87a89b1108..b25420a48e69 100644
--- a/test/CodeGen/PowerPC/complex-return.ll
+++ b/test/CodeGen/PowerPC/complex-return.ll
@@ -9,7 +9,7 @@ entry:
   %x = alloca { ppc_fp128, ppc_fp128 }, align 16
   %real = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 0
   %imag = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 1
-  store ppc_fp128 0xM400C0000000000000000000000000000, ppc_fp128* %real
+  store ppc_fp128 0xM400C0000000000300000000010000000, ppc_fp128* %real
   store ppc_fp128 0xMC00547AE147AE1483CA47AE147AE147A, ppc_fp128* %imag
   %x.realp = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* %x, i32 0, i32 0
   %x.real = load ppc_fp128, ppc_fp128* %x.realp
diff --git a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll
index 0de2e220c2cc..e0f28475d8fd 100644
--- a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll
+++ b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll
@@ -25,8 +25,8 @@ entry:
 
 ; CHECK-DAG: li [[REG1:[0-9]+]], -128
 ; CHECK-DAG: neg [[REG2:[0-9]+]],
-; CHECK: and [[REG1]], [[REG2]], [[REG1]]
-; CHECK: stdux {{[0-9]+}}, 1, [[REG1]]
+; CHECK: and [[REG3:[0-9]+]], [[REG2]], [[REG1]]
+; CHECK: stdux {{[0-9]+}}, 1, [[REG3]]
 
 ; CHECK: blr
 
diff --git a/test/CodeGen/PowerPC/licm-remat.ll b/test/CodeGen/PowerPC/licm-remat.ll
new file mode 100644
index 000000000000..cbd1af62b842
--- /dev/null
+++ b/test/CodeGen/PowerPC/licm-remat.ll
@@ -0,0 +1,179 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Test case is reduced from the snappy benchmark.
+; Verify MachineLICM will always hoist trivially rematerializable instructions even when register pressure is high.
+
+%"class.snappy::SnappyDecompressor" = type <{ %"class.snappy::Source"*, i8*, i8*, i32, i8, [5 x i8], [6 x i8] }>
+%"class.snappy::Source" = type { i32 (...)** }
+%"struct.snappy::iovec" = type { i8*, i64 }
+%"class.snappy::SnappyIOVecWriter" = type { %"struct.snappy::iovec"*, i64, i64, i64, i64, i64 }
+
+@_ZN6snappy8internalL10char_tableE = internal unnamed_addr constant [5 x i16] [i16 1, i16 2052, i16 4097, i16 8193, i16 2], align 2
+@_ZN6snappy8internalL8wordmaskE = internal unnamed_addr constant [5 x i32] [i32 0, i32 255, i32 65535, i32 16777215, i32 -1], align 4
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2
+; Function Attrs: argmemonly nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #2
+
+define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) {
+; CHECK-LABEL: ZN6snappyDecompressor_:
+; CHECK:       # BB#0: # %entry
+; CHECK:       addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
+; CHECK-DAG:   addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l
+; CHECK-DAG:   addis 4, 2, _ZN6snappy8internalL10char_tableE@toc@ha
+; CHECK-DAG:   addi 24, 4, _ZN6snappy8internalL10char_tableE@toc@l
+; CHECK:       b .LBB0_2
+; CHECK:       .LBB0_2: # %for.cond
+; CHECK-NOT:   addis {{[0-9]+}}, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
+; CHECK-NOT:   addis {{[0-9]+}}, 2, _ZN6snappy8internalL10char_tableE@toc@ha
+; CHECK:       bctrl
+entry:
+  %ip_limit_ = getelementptr inbounds %"class.snappy::SnappyDecompressor", %"class.snappy::SnappyDecompressor"* %this, i64 0, i32 2
+  %0 = bitcast i8** %ip_limit_ to i64*
+  %curr_iov_index_.i = getelementptr inbounds %"class.snappy::SnappyIOVecWriter", %"class.snappy::SnappyIOVecWriter"* %writer, i64 0, i32 2
+  %curr_iov_written_.i = getelementptr inbounds %"class.snappy::SnappyIOVecWriter", %"class.snappy::SnappyIOVecWriter"* %writer, i64 0, i32 3
+  %1 = bitcast i64* %curr_iov_written_.i to <2 x i64>*
+  br label %for.cond
+
+for.cond:                                         ; preds = %if.end82, %if.then56, %if.end49, %entry
+  %ip.0 = phi i8* [ null, %entry ], [ %add.ptr50, %if.end49 ], [ null, %if.then56 ], [ undef, %if.end82 ]
+  %incdec.ptr = getelementptr inbounds i8, i8* %ip.0, i64 1
+  %2 = load i8, i8* %ip.0, align 1
+  %conv = zext i8 %2 to i32
+  br i1 undef, label %if.then7, label %if.else
+
+if.then7:                                         ; preds = %for.cond
+  %3 = lshr i32 %conv, 2
+  %add = add nuw nsw i32 %3, 1
+  %conv9 = zext i32 %add to i64
+  %4 = load i64, i64* %0, align 8
+  %sub.ptr.sub13 = sub i64 %4, 0
+  %5 = load i64, i64* undef, align 8
+  %6 = load i64, i64* null, align 8
+  %sub.i = sub i64 %5, %6
+  %cmp.i = icmp ult i32 %add, 17
+  %cmp2.i = icmp ugt i64 %sub.ptr.sub13, 20
+  %or.cond.i = and i1 %cmp.i, %cmp2.i
+  %cmp4.i = icmp ugt i64 %sub.i, 15
+  %or.cond13.i = and i1 %or.cond.i, %cmp4.i
+  br i1 %or.cond13.i, label %land.lhs.true5.i, label %if.end17
+
+land.lhs.true5.i:                                 ; preds = %if.then7
+  %7 = load %"struct.snappy::iovec"*, %"struct.snappy::iovec"** undef, align 8
+  %8 = load i64, i64* %curr_iov_index_.i, align 8
+  %9 = load i64, i64* %curr_iov_written_.i, align 8
+  %sub6.i = sub i64 0, %9
+  %cmp7.i = icmp ugt i64 %sub6.i, 15
+  br i1 %cmp7.i, label %cleanup102, label %if.end17
+
+if.end17:                                         ; preds = %land.lhs.true5.i, %if.then7
+  %sub = add nsw i64 %conv9, -60
+  %10 = load i32, i32* undef, align 4
+  %arrayidx = getelementptr inbounds [5 x i32], [5 x i32]* @_ZN6snappy8internalL8wordmaskE, i64 0, i64 %sub
+  %11 = load i32, i32* %arrayidx, align 4
+  %and21 = and i32 %11, %10
+  %add22 = add i32 %and21, 1
+  %conv23 = zext i32 %add22 to i64
+  %add.ptr24 = getelementptr inbounds i8, i8* %incdec.ptr, i64 %sub
+  br label %if.end25
+
+if.end25:                                         ; preds = %if.end17
+  %sub.ptr.rhs.cast28 = ptrtoint i8* %add.ptr24 to i64
+  %cmp30233 = icmp ugt i64 %conv23, 0
+  br i1 %cmp30233, label %while.body.preheader, label %while.end
+
+while.body.preheader:                             ; preds = %if.end25
+  %add.i158256 = add i64 %6, 0
+  %cmp.i160257 = icmp ugt i64 %add.i158256, %5
+  br i1 %cmp.i160257, label %cleanup105, label %while.cond.preheader.i
+
+while.cond.preheader.i:                           ; preds = %while.body.preheader
+  %call39 = call i8* undef(%"class.snappy::Source"* undef, i64* nonnull undef)
+  unreachable
+
+while.end:                                        ; preds = %if.end25
+  br label %while.cond.preheader.i176
+
+while.cond.preheader.i176:                        ; preds = %while.end
+  br i1 undef, label %if.end49, label %while.body.lr.ph.i182
+
+while.body.lr.ph.i182:                            ; preds = %while.cond.preheader.i176
+  %.pre.i181 = load i64, i64* %curr_iov_written_.i, align 8
+  %12 = load %"struct.snappy::iovec"*, %"struct.snappy::iovec"** undef, align 8
+  %13 = load i64, i64* %curr_iov_index_.i, align 8
+  %iov_len.i185 = getelementptr inbounds %"struct.snappy::iovec", %"struct.snappy::iovec"* %12, i64 %13, i32 1
+  %14 = load i64, i64* %iov_len.i185, align 8
+  br label %cond.end.i190
+
+cond.end.i190:                                    ; preds = %while.body.lr.ph.i182
+  br i1 undef, label %if.end18.i207, label %if.then10.i193
+
+if.then10.i193:                                   ; preds = %cond.end.i190
+  %add12.i191 = add i64 %13, 1
+  %iov_len22.phi.trans.insert.i194 = getelementptr inbounds %"struct.snappy::iovec", %"struct.snappy::iovec"* %12, i64 %add12.i191, i32 1
+  %.pre48.i195 = load i64, i64* %iov_len22.phi.trans.insert.i194, align 8
+  br label %if.end18.i207
+
+if.end18.i207:                                    ; preds = %if.then10.i193, %cond.end.i190
+  %15 = phi i64 [ %.pre.i181, %cond.end.i190 ], [ 0, %if.then10.i193 ]
+  %16 = phi i64 [ %14, %cond.end.i190 ], [ %.pre48.i195, %if.then10.i193 ]
+  %17 = phi i64 [ %13, %cond.end.i190 ], [ %add12.i191, %if.then10.i193 ]
+  %sub.i197 = sub i64 %16, %15
+  %cmp.i.i198 = icmp ult i64 %sub.i197, %conv23
+  %.sroa.speculated.i199 = select i1 %cmp.i.i198, i64 %sub.i197, i64 %conv23
+  %iov_base.i.i200 = getelementptr inbounds %"struct.snappy::iovec", %"struct.snappy::iovec"* %12, i64 %17, i32 0
+  %18 = load i8*, i8** %iov_base.i.i200, align 8
+  %add.ptr.i.i201 = getelementptr inbounds i8, i8* %18, i64 %15
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %add.ptr.i.i201, i8* %add.ptr24, i64 %.sroa.speculated.i199, i32 1, i1 false) #12
+  %add30.i203 = add i64 0, %.sroa.speculated.i199
+  store i64 %add30.i203, i64* null, align 8
+  %.pre245 = load i64, i64* %0, align 8
+  br label %if.end49
+
+if.end49:                                         ; preds = %if.end18.i207, %while.cond.preheader.i176
+  %19 = phi i64 [ %.pre245, %if.end18.i207 ], [ %4, %while.cond.preheader.i176 ]
+  %add.ptr50 = getelementptr inbounds i8, i8* %add.ptr24, i64 %conv23
+  %sub.ptr.sub54 = sub i64 %19, 0
+  %cmp55 = icmp slt i64 %sub.ptr.sub54, 5
+  br i1 %cmp55, label %if.then56, label %for.cond
+
+if.then56:                                        ; preds = %if.end49
+  br label %for.cond
+
+if.else:                                          ; preds = %for.cond
+  %idxprom = zext i8 %2 to i64
+  %arrayidx68 = getelementptr inbounds [5 x i16], [5 x i16]* @_ZN6snappy8internalL10char_tableE, i64 0, i64 %idxprom
+  %20 = load i16, i16* %arrayidx68, align 2
+  %conv69 = zext i16 %20 to i64
+  %21 = load i32, i32* undef, align 4
+  %shr71 = lshr i64 %conv69, 11
+  %arrayidx72 = getelementptr inbounds [5 x i32], [5 x i32]* @_ZN6snappy8internalL8wordmaskE, i64 0, i64 %shr71
+  %22 = load i32, i32* %arrayidx72, align 4
+  %and73 = and i32 %22, %21
+  %conv74 = zext i32 %and73 to i64
+  %add79 = add nuw nsw i64 0, %conv74
+  %call80 = call zeroext i1 @_ZN6snappy17SnappyIOVecWriterAppendFromSelfEmm(%"class.snappy::SnappyIOVecWriter"* %writer, i64 %add79, i64 undef)
+  br i1 %call80, label %if.end82, label %cleanup105
+
+if.end82:                                         ; preds = %if.else
+  br label %for.cond
+
+cleanup102:                                       ; preds = %land.lhs.true5.i
+  %iov_base.i.i = getelementptr inbounds %"struct.snappy::iovec", %"struct.snappy::iovec"* %7, i64 %8, i32 0
+  %23 = load i8*, i8** %iov_base.i.i, align 8
+  %add.ptr.i.i = getelementptr inbounds i8, i8* %23, i64 %9
+  call void @llvm.memmove.p0i8.p0i8.i64(i8* %add.ptr.i.i, i8* %incdec.ptr, i64 16, i32 1, i1 false) #12
+  %24 = load <2 x i64>, <2 x i64>* %1, align 8
+  %25 = insertelement <2 x i64> undef, i64 %conv9, i32 0
+  %26 = shufflevector <2 x i64> %25, <2 x i64> undef, <2 x i32> zeroinitializer
+  %27 = add <2 x i64> %24, %26
+  store <2 x i64> %27, <2 x i64>* undef, align 8
+  unreachable
+
+cleanup105:                                       ; preds = %if.else, %while.body.preheader
+  ret void
+}
+
+; Function Attrs: inlinehint
+declare zeroext i1 @_ZN6snappy17SnappyIOVecWriterAppendFromSelfEmm(%"class.snappy::SnappyIOVecWriter"*, i64, i64) local_unnamed_addr #10 align 2
diff --git a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
index ad9078c82066..d398dfe7fc92 100644
--- a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+++ b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -168,26 +168,8 @@ define signext i32 @zeroEqualityTest05() {
 ; Validate with memcmp()?:
 define signext i32 @equalityFoldTwoConstants() {
 ; CHECK-LABEL: equalityFoldTwoConstants:
-; CHECK:       # BB#0: # %loadbb
-; CHECK-NEXT:    addis 3, 2, .LzeroEqualityTest04.buffer1@toc@ha
-; CHECK-NEXT:    addis 4, 2, .LzeroEqualityTest04.buffer2@toc@ha
-; CHECK-NEXT:    ld 3, .LzeroEqualityTest04.buffer1@toc@l(3)
-; CHECK-NEXT:    ld 4, .LzeroEqualityTest04.buffer2@toc@l(4)
-; CHECK-NEXT:    cmpld 3, 4
-; CHECK-NEXT:    bne 0, .LBB5_2
-; CHECK-NEXT:  # BB#1: # %loadbb1
-; CHECK-NEXT:    addis 3, 2, .LzeroEqualityTest04.buffer1@toc@ha+8
-; CHECK-NEXT:    addis 4, 2, .LzeroEqualityTest04.buffer2@toc@ha+8
-; CHECK-NEXT:    ld 3, .LzeroEqualityTest04.buffer1@toc@l+8(3)
-; CHECK-NEXT:    ld 4, .LzeroEqualityTest04.buffer2@toc@l+8(4)
-; CHECK-NEXT:    cmpld 3, 4
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    beq 0, .LBB5_3
-; CHECK-NEXT:  .LBB5_2: # %res_block
+; CHECK:       # BB#0: # %endblock
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:  .LBB5_3: # %endblock
-; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    srwi 3, 3, 5
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16)
   %not.tobool = icmp eq i32 %call, 0
@@ -198,16 +180,17 @@ define signext i32 @equalityFoldTwoConstants() {
 define signext i32 @equalityFoldOneConstant(i8* %X) {
 ; CHECK-LABEL: equalityFoldOneConstant:
 ; CHECK:       # BB#0: # %loadbb
-; CHECK-NEXT:    addis 4, 2, .LzeroEqualityTest04.buffer1@toc@ha
+; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    ld 5, 0(3)
-; CHECK-NEXT:    ld 4, .LzeroEqualityTest04.buffer1@toc@l(4)
-; CHECK-NEXT:    cmpld 4, 5
+; CHECK-NEXT:    sldi 4, 4, 32
+; CHECK-NEXT:    cmpld 5, 4
 ; CHECK-NEXT:    bne 0, .LBB6_2
 ; CHECK-NEXT:  # BB#1: # %loadbb1
-; CHECK-NEXT:    addis 4, 2, .LzeroEqualityTest04.buffer1@toc@ha+8
+; CHECK-NEXT:    li 4, 3
 ; CHECK-NEXT:    ld 3, 8(3)
-; CHECK-NEXT:    ld 4, .LzeroEqualityTest04.buffer1@toc@l+8(4)
-; CHECK-NEXT:    cmpld 4, 3
+; CHECK-NEXT:    sldi 4, 4, 32
+; CHECK-NEXT:    ori 4, 4, 2
+; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    beq 0, .LBB6_3
 ; CHECK-NEXT:  .LBB6_2: # %res_block
diff --git a/test/CodeGen/PowerPC/memcpy_dereferenceable.ll b/test/CodeGen/PowerPC/memcpy_dereferenceable.ll
new file mode 100644
index 000000000000..ed821849f09c
--- /dev/null
+++ b/test/CodeGen/PowerPC/memcpy_dereferenceable.ll
@@ -0,0 +1,74 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; This code causes an assertion failure if dereferenceable flag is not properly set in the load generated for memcpy
+
+; CHECK-LABEL: @func
+; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOT: lxvd2x
+; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+
+define void @func(i1 %flag) {
+entry:
+  %pairs = alloca [4 x <2 x i64>], align 8
+  %pair1 = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %pairs, i64 0, i64 1
+  %pair2 = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %pairs, i64 0, i64 2
+  %pvec1 = bitcast <2 x i64>* %pair1 to <2 x i64>*
+  %pvec2 = bitcast <2 x i64>* %pair2 to <2 x i64>*
+  %dst = bitcast [4 x <2 x i64>]* %pairs to i8*
+  %src = bitcast <2 x i64>* %pair2 to i8*
+  br i1 %flag, label %end, label %dummy
+
+end:
+  ; copy third element into first element by memcpy
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %dst, i8* %src, i64 16, i32 8, i1 false)
+  ; copy third element into second element by LD/ST
+  %vec2 = load <2 x i64>, <2 x i64>* %pvec2, align 8
+  store <2 x i64> %vec2, <2 x i64>* %pvec1, align 8
+  ret void
+
+dummy:
+  ; to make use of %src in another BB
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %src, i8* %src, i64 0, i32 0, i1 false)
+  br label %end
+}
+
+
+; CHECK-LABEL: @func2
+; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-NOT: lxvd2x
+; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: blr
+
+define void @func2(i1 %flag) {
+entry:
+  %pairs = alloca [4 x <2 x i64>], align 8
+  %pair1 = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %pairs, i64 0, i64 1
+  %pair2 = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %pairs, i64 0, i64 2
+  %pvec1 = bitcast <2 x i64>* %pair1 to <2 x i64>*
+  %pvec2 = bitcast <2 x i64>* %pair2 to <2 x i64>*
+  %dst = bitcast [4 x <2 x i64>]* %pairs to i8*
+  %src = bitcast <2 x i64>* %pair2 to i8*
+  br i1 %flag, label %end, label %dummy
+
+end:
+  ; copy third element into first element by memcpy
+  call void @llvm.memmove.p0i8.p0i8.i64(i8* nonnull %dst, i8* %src, i64 16, i32 8, i1 false)
+  ; copy third element into second element by LD/ST
+  %vec2 = load <2 x i64>, <2 x i64>* %pvec2, align 8
+  store <2 x i64> %vec2, <2 x i64>* %pvec1, align 8
+  ret void
+
+dummy:
+  ; to make use of %src in another BB
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %src, i8* %src, i64 0, i32 0, i1 false)
+  br label %end
+}
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1
+declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1
+
+attributes #1 = { argmemonly nounwind }
diff --git a/test/CodeGen/PowerPC/scavenging.mir b/test/CodeGen/PowerPC/scavenging.mir
index 8b5c26230bc6..a72aaa443a0b 100644
--- a/test/CodeGen/PowerPC/scavenging.mir
+++ b/test/CodeGen/PowerPC/scavenging.mir
@@ -6,7 +6,7 @@ tracksRegLiveness: true
 body: |
   bb.0:
     ; CHECK: [[REG0:%r[0-9]+]] = LI 42
-    ; CHECK-NEXT: NOP implicit [[REG0]]
+    ; CHECK-NEXT: NOP implicit killed [[REG0]]
     %0 : gprc = LI 42
     NOP implicit %0
 
@@ -14,7 +14,7 @@ body: |
     ; CHECK-NEXT: NOP
     ; CHECK-NEXT: NOP implicit [[REG1]]
     ; CHECK-NEXT: NOP
-    ; CHECK-NEXT: NOP implicit [[REG1]]
+    ; CHECK-NEXT: NOP implicit killed [[REG1]]
     %1 : gprc = LI 42
     NOP
     NOP implicit %1
@@ -48,8 +48,8 @@ body: |
     ; CHECK-NOT: %x30 = LI 42
     ; CHECK: [[REG3:%r[0-9]+]] = LI 42
     ; CHECK-NEXT: %x5 = IMPLICIT_DEF
-    ; CHECK-NEXT: NOP implicit [[REG2]]
-    ; CHECK-NEXT: NOP implicit [[REG3]]
+    ; CHECK-NEXT: NOP implicit killed [[REG2]]
+    ; CHECK-NEXT: NOP implicit killed [[REG3]]
     %3 : gprc = LI 42
     %x5 = IMPLICIT_DEF
     NOP implicit %2
@@ -110,7 +110,7 @@ body: |
 
     ; CHECK: STD killed [[SPILLEDREG:%x[0-9]+]]
     ; CHECK: [[SPILLEDREG]] = LI8 42
-    ; CHECK: NOP implicit [[SPILLEDREG]]
+    ; CHECK: NOP implicit killed [[SPILLEDREG]]
     ; CHECK: [[SPILLEDREG]] = LD
     %0 : g8rc = LI8 42
     NOP implicit %0
@@ -147,3 +147,60 @@ body: |
     NOP implicit %x29
     NOP implicit %x30
 ...
+---
+# Check for bug where we would refuse to spill before the first instruction in a
+# block.
+# CHECK-LABEL: name: spill_at_begin
+# CHECK: bb.0:
+# CHECK: liveins:
+# CHECK: STD killed [[REG:%x[0-9]+]]{{.*}}(store 8 into %stack.{{[0-9]+}})
+# CHECK: [[REG]] = LIS8 0
+# CHECK: [[REG]] = ORI8 killed [[REG]], 48
+# CHECK: NOP implicit killed [[REG]]
+# CHEKC: [[REG]] = LD{{.*}}(load 8 from %stack.{{[0-9]+}})
+name: spill_at_begin
+tracksRegLiveness: true
+stack:
+  # variable-sized object should be a reason to reserve an emergency spillslot
+  # in the RegScavenger
+  - { id: 0, type: variable-sized, offset: -32, alignment: 1 }
+body: |
+  bb.0:
+    liveins: %x0, %x1, %x2, %x3, %x4, %x5, %x6, %x7, %x8, %x9, %x10, %x11, %x12, %x13, %x14, %x15, %x16, %x17, %x18, %x19, %x20, %x21, %x22, %x23, %x24, %x25, %x26, %x27, %x28, %x29, %x30, %x31
+    %0 : g8rc = LIS8 0
+    %1 : g8rc = ORI8 %0, 48
+    NOP implicit %1
+
+    NOP implicit %x0
+    NOP implicit %x1
+    NOP implicit %x2
+    NOP implicit %x3
+    NOP implicit %x4
+    NOP implicit %x5
+    NOP implicit %x6
+    NOP implicit %x7
+    NOP implicit %x8
+    NOP implicit %x9
+    NOP implicit %x10
+    NOP implicit %x11
+    NOP implicit %x12
+    NOP implicit %x13
+    NOP implicit %x14
+    NOP implicit %x15
+    NOP implicit %x16
+    NOP implicit %x17
+    NOP implicit %x18
+    NOP implicit %x19
+    NOP implicit %x20
+    NOP implicit %x21
+    NOP implicit %x22
+    NOP implicit %x23
+    NOP implicit %x24
+    NOP implicit %x25
+    NOP implicit %x26
+    NOP implicit %x27
+    NOP implicit %x28
+    NOP implicit %x29
+    NOP implicit %x30
+    NOP implicit %x31
+...
diff --git a/test/CodeGen/PowerPC/vsx-spill.ll b/test/CodeGen/PowerPC/vsx-spill.ll
index 4dec0daecd9b..93ad98556267 100644
--- a/test/CodeGen/PowerPC/vsx-spill.ll
+++ b/test/CodeGen/PowerPC/vsx-spill.ll
@@ -23,9 +23,9 @@ entry:
 ; CHECK-REG: blr
 
 ; CHECK-FISL: @foo1
-; CHECK-FISL: lis 0, -1
-; CHECK-FISL: ori 0, 0, 65384
-; CHECK-FISL: stxsdx 1, 1, 0
+; CHECK-FISL: lis 3, -1
+; CHECK-FISL: ori 3, 3, 65384
+; CHECK-FISL: stxsdx 1, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-P9-REG: @foo1
@@ -54,8 +54,8 @@ entry:
 
 ; CHECK-FISL: @foo2
 ; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1
-; CHECK-FISL: stxsdx [[R1]], [[R1]], 0
-; CHECK-FISL: lxsdx [[R1]], [[R1]], 0
+; CHECK-FISL: stxsdx [[R1]], [[R1]], 3
+; CHECK-FISL: lxsdx [[R1]], [[R1]], 3
 ; CHECK-FISL: blr
 
 ; CHECK-P9-REG: @foo2
diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll
index cfea3e5696de..26b59926c7f1 100644
--- a/test/CodeGen/PowerPC/vsx.ll
+++ b/test/CodeGen/PowerPC/vsx.ll
@@ -235,9 +235,9 @@ entry:
 ; CHECK-FISL-LABEL: @test14
 ; CHECK-FISL: xxlor 0, 34, 35
 ; CHECK-FISL: xxlnor 34, 34, 35
-; CHECK-FISL: lis 0, -1
-; CHECK-FISL: ori 0, 0, 65520
-; CHECK-FISL: stxvd2x 0, 1, 0
+; CHECK-FISL: lis 3, -1
+; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL: stxvd2x 0, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test14
@@ -260,9 +260,9 @@ entry:
 ; CHECK-FISL: xxlor 36, 0, 0
 ; CHECK-FISL: xxlnor 0, 34, 35
 ; CHECK-FISL: xxlor 34, 0, 0
-; CHECK-FISL: lis 0, -1
-; CHECK-FISL: ori 0, 0, 65520
-; CHECK-FISL: stxvd2x 36, 1, 0
+; CHECK-FISL: lis 3, -1
+; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL: stxvd2x 36, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test15
@@ -285,9 +285,9 @@ entry:
 ; CHECK-FISL: xxlor 36, 0, 0
 ; CHECK-FISL: xxlnor 0, 34, 35
 ; CHECK-FISL: xxlor 34, 0, 0
-; CHECK-FISL: lis 0, -1
-; CHECK-FISL: ori 0, 0, 65520
-; CHECK-FISL: stxvd2x 36, 1, 0
+; CHECK-FISL: lis 3, -1
+; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL: stxvd2x 36, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test16
@@ -330,9 +330,9 @@ entry:
 ; CHECK-FISL: xxlor 36, 0, 0
 ; CHECK-FISL: xxlandc 0, 34, 35
 ; CHECK-FISL: xxlor 34, 0, 0
-; CHECK-FISL: lis 0, -1
-; CHECK-FISL: ori 0, 0, 65520
-; CHECK-FISL: stxvd2x 36, 1, 0
+; CHECK-FISL: lis 3, -1
+; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL: stxvd2x 36, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test18
@@ -355,9 +355,9 @@ entry:
 ; CHECK-FISL: xxlor 36, 0, 0
 ; CHECK-FISL: xxlandc 0, 34, 35
 ; CHECK-FISL: xxlor 34, 0, 0
-; CHECK-FISL: lis 0, -1
-; CHECK-FISL: ori 0, 0, 65520
-; CHECK-FISL: stxvd2x 36, 1, 0
+; CHECK-FISL: lis 3, -1
+; CHECK-FISL: ori 3, 3, 65520
+; CHECK-FISL: stxvd2x 36, 1, 3
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test19