vendor/llvm/llvm-trunk-r241361

6 files changed, 630 insertions, 6 deletions

diff --git a/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll b/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll
new file mode 100644
index 000000000000..16dc2ccb111d
--- /dev/null
+++ b/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll
@@ -0,0 +1,165 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+@vda = common global <2 x double> zeroinitializer, align 16
+@vdb = common global <2 x double> zeroinitializer, align 16
+@vdr = common global <2 x double> zeroinitializer, align 16
+@vfa = common global <4 x float> zeroinitializer, align 16
+@vfb = common global <4 x float> zeroinitializer, align 16
+@vfr = common global <4 x float> zeroinitializer, align 16
+@vbllr = common global <2 x i64> zeroinitializer, align 16
+@vbir = common global <4 x i32> zeroinitializer, align 16
+@vblla = common global <2 x i64> zeroinitializer, align 16
+@vbllb = common global <2 x i64> zeroinitializer, align 16
+@vbia = common global <4 x i32> zeroinitializer, align 16
+@vbib = common global <4 x i32> zeroinitializer, align 16
+
+; Function Attrs: nounwind
+define void @test1() {
+entry:
+  %0 = load <2 x double>, <2 x double>* @vda, align 16
+  %1 = load <2 x double>, <2 x double>* @vdb, align 16
+  %2 = call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %1)
+  store <2 x double> %2, <2 x double>* @vdr, align 16
+  ret void
+; CHECK-LABEL: @test1
+; CHECK: xvdivdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test2() {
+entry:
+  %0 = load <4 x float>, <4 x float>* @vfa, align 16
+  %1 = load <4 x float>, <4 x float>* @vfb, align 16
+  %2 = call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %1)
+  store <4 x float> %2, <4 x float>* @vfr, align 16
+  ret void
+; CHECK-LABEL: @test2
+; CHECK: xvdivsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test3() {
+entry:
+  %0 = load <2 x double>, <2 x double>* @vda, align 16
+  %1 = load <2 x double>, <2 x double>* @vda, align 16
+  %2 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %1)
+  store <2 x double> %2, <2 x double>* @vdr, align 16
+  ret void
+; CHECK-LABEL: @test3
+; CHECK: xvrdpip {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test4() {
+entry:
+  %0 = load <4 x float>, <4 x float>* @vfa, align 16
+  %1 = load <4 x float>, <4 x float>* @vfa, align 16
+  %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %1)
+  store <4 x float> %2, <4 x float>* @vfr, align 16
+  ret void
+; CHECK-LABEL: @test4
+; CHECK: xvrspip {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test5() {
+entry:
+  %0 = load <2 x double>, <2 x double>* @vda, align 16
+  %1 = load <2 x double>, <2 x double>* @vdb, align 16
+  %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %0, <2 x double> %1)
+  store <2 x i64> %2, <2 x i64>* @vbllr, align 16
+  ret void
+; CHECK-LABEL: @test5
+; CHECK: xvcmpeqdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test6() {
+entry:
+  %0 = load <4 x float>, <4 x float>* @vfa, align 16
+  %1 = load <4 x float>, <4 x float>* @vfb, align 16
+  %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %0, <4 x float> %1)
+  store <4 x i32> %2, <4 x i32>* @vbir, align 16
+  ret void
+; CHECK-LABEL: @test6
+; CHECK: xvcmpeqsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test7() {
+entry:
+  %0 = load <2 x double>, <2 x double>* @vda, align 16
+  %1 = load <2 x double>, <2 x double>* @vdb, align 16
+  %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %0, <2 x double> %1)
+  store <2 x i64> %2, <2 x i64>* @vbllr, align 16
+  ret void
+; CHECK-LABEL: @test7
+; CHECK: xvcmpgedp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test8() {
+entry:
+  %0 = load <4 x float>, <4 x float>* @vfa, align 16
+  %1 = load <4 x float>, <4 x float>* @vfb, align 16
+  %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %0, <4 x float> %1)
+  store <4 x i32> %2, <4 x i32>* @vbir, align 16
+  ret void
+; CHECK-LABEL: @test8
+; CHECK: xvcmpgesp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test9() {
+entry:
+  %0 = load <2 x double>, <2 x double>* @vda, align 16
+  %1 = load <2 x double>, <2 x double>* @vdb, align 16
+  %2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %0, <2 x double> %1)
+  store <2 x i64> %2, <2 x i64>* @vbllr, align 16
+  ret void
+; CHECK-LABEL: @test9
+; CHECK: xvcmpgtdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind
+define void @test10() {
+entry:
+  %0 = load <4 x float>, <4 x float>* @vfa, align 16
+  %1 = load <4 x float>, <4 x float>* @vfb, align 16
+  %2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %0, <4 x float> %1)
+  store <4 x i32> %2, <4 x i32>* @vbir, align 16
+  ret void
+; CHECK-LABEL: @test10
+; CHECK: xvcmpgtsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
+
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
+
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
+
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double>, <2 x double>)
+
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float>, <4 x float>)
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double>, <2 x double>)
+
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float>, <4 x float>)
+
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>)
+
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
diff --git a/test/CodeGen/PowerPC/lxvw4x-bug.ll b/test/CodeGen/PowerPC/lxvw4x-bug.ll
new file mode 100644
index 000000000000..1f521a5d533c
--- /dev/null
+++ b/test/CodeGen/PowerPC/lxvw4x-bug.ll
@@ -0,0 +1,25 @@
+; RUN: llc -O0 -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+; Function Attrs: nounwind
+define void @test() {
+entry:
+  %__a.addr.i = alloca i32, align 4
+  %__b.addr.i = alloca <4 x i32>*, align 8
+  %i = alloca <4 x i32>, align 16
+  %j = alloca <4 x i32>, align 16
+  store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %i, align 16
+  store i32 0, i32* %__a.addr.i, align 4
+  store <4 x i32>* %i, <4 x i32>** %__b.addr.i, align 8
+  %0 = load i32, i32* %__a.addr.i, align 4
+  %1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8
+  %2 = bitcast <4 x i32>* %1 to i8*
+  %3 = getelementptr i8, i8* %2, i32 %0
+  %4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3)
+; CHECK: lwa [[REG0:[0-9]+]],
+; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
+; CHECK: xxswapd [[REG1]], [[REG1]]
+  store <4 x i32> %4, <4 x i32>* %j, align 16
+  ret void
+}
+
+; Function Attrs: nounwind readonly
+declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)
diff --git a/test/CodeGen/PowerPC/swaps-le-3.ll b/test/CodeGen/PowerPC/swaps-le-3.ll
new file mode 100644
index 000000000000..0c1748df9fcd
--- /dev/null
+++ b/test/CodeGen/PowerPC/swaps-le-3.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
+
+; This test verifies that VSX swap optimization works for the
+; doubleword splat idiom.
+
+@a = external global <2 x double>, align 16
+@b = external global <2 x double>, align 16
+
+define void @test(double %s) {
+entry:
+  %0 = insertelement <2 x double> undef, double %s, i32 0
+  %1 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
+  %2 = load <2 x double>, <2 x double>* @a, align 16
+  %3 = fadd <2 x double> %0, %2
+  store <2 x double> %3, <2 x double>* @b, align 16
+  ret void
+}
+
+; CHECK-LABEL: @test
+; CHECK: xxspltd
+; CHECK: lxvd2x
+; CHECK: xvadddp
+; CHECK: stxvd2x
+; CHECK-NOT: xxswapd
diff --git a/test/CodeGen/PowerPC/swaps-le-4.ll b/test/CodeGen/PowerPC/swaps-le-4.ll
new file mode 100644
index 000000000000..7d8239bd2557
--- /dev/null
+++ b/test/CodeGen/PowerPC/swaps-le-4.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
+
+; This test verifies that VSX swap optimization works when an implicit
+; subregister is present (in this case, in the XXPERMDI associated with
+; the store).
+
+define void @bar() {
+entry:
+  %x = alloca <2 x i64>, align 16
+  %0 = bitcast <2 x i64>* %x to i8*
+  call void @llvm.lifetime.start(i64 16, i8* %0)
+  %arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %x, i64 0, i64 0
+  store <2 x i64> <i64 0, i64 1>, <2 x i64>* %x, align 16
+  call void @foo(i64* %arrayidx)
+  call void @llvm.lifetime.end(i64 16, i8* %0)
+  ret void
+}
+
+; CHECK-LABEL: @bar
+; CHECK: lxvd2x
+; CHECK: stxvd2x
+; CHECK-NOT: xxswapd
+
+declare void @llvm.lifetime.start(i64, i8* nocapture)
+declare void @foo(i64*)
+declare void @llvm.lifetime.end(i64, i8* nocapture)
+
diff --git a/test/CodeGen/PowerPC/vec_mergeow.ll b/test/CodeGen/PowerPC/vec_mergeow.ll
new file mode 100644
index 000000000000..c7c7448e3ae8
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_mergeow.ll
@@ -0,0 +1,101 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \
+; RUN:   FileCheck %s  -check-prefix=CHECK-LE
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \
+; RUN:   FileCheck %s -check-prefix=CHECK-BE
+
+; Check for a vector merge instruction using two inputs
+; The shufflevector specifies the even elements, using big endian element 
+; ordering. If run on a big endian machine, this should produce the vmrgew 
+; instruction. If run on a little endian machine, this should produce the
+; vmrgow instruction. Note also that on little endian the input registers 
+; are swapped also.
+define void @check_merge_even_xy(<16 x i8>* %A, <16 x i8>* %B) {
+entry:
+; CHECK-LE-LABEL: @check_merge_even_xy
+; CHECK-BE-LABEL: @check_merge_even_xy
+        %tmp = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
+	%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, 
+	      		      <16 x i32> <i32 0, i32 1, i32 2, i32 3, 
+			      	    	  i32 16, i32 17, i32 18, i32 19, 
+					  i32 8, i32 9, i32 10, i32 11, 
+					  i32 24, i32 25, i32 26, i32 27>
+; CHECK-LE: vmrgow 2, 3, 2
+; CHECK-BE: vmrgew 2, 2, 3
+      	store <16 x i8> %tmp3, <16 x i8>* %A
+	ret void
+; CHECK-LE: blr
+; CHECK-BE: blr
+}
+
+; Check for a vector merge instruction using a single input. 
+; The shufflevector specifies the even elements, using big endian element 
+; ordering. If run on a big endian machine, this should produce the vmrgew 
+; instruction. If run on a little endian machine, this should produce the
+; vmrgow instruction. 
+define void @check_merge_even_xx(<16 x i8>* %A) {
+entry:
+; CHECK-LE-LABEL: @check_merge_even_xx
+; CHECK-BE-LABEL: @check_merge_even_xx
+        %tmp = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, 
+	      		      <16 x i32> <i32 0, i32 1, i32 2, i32 3, 
+			      	          i32 0, i32 1, i32 2, i32 3, 
+					  i32 8, i32 9, i32 10, i32 11, 
+					  i32 8, i32 9, i32 10, i32 11>
+; CHECK-LE: vmrgow 2, 2, 2
+; CHECK-BE: vmrgew 2, 2, 2
+  	store <16 x i8> %tmp2, <16 x i8>* %A
+	ret void
+; CHECK-LE: blr
+; CHECK-BE: blr       
+}
+
+; Check for a vector merge instruction using two inputs.
+; The shufflevector specifies the odd elements, using big endian element 
+; ordering. If run on a big endian machine, this should produce the vmrgow 
+; instruction. If run on a little endian machine, this should produce the
+; vmrgew instruction. Note also that on little endian the input registers 
+; are swapped also.
+define void @check_merge_odd_xy(<16 x i8>* %A, <16 x i8>* %B) {
+entry:
+; CHECK-LE-LABEL: @check_merge_odd_xy
+; CHECK-BE-LABEL: @check_merge_odd_xy
+        %tmp = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = load <16 x i8>, <16 x i8>* %B
+	%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, 
+	      		      <16 x i32> <i32 4, i32 5, i32 6, i32 7, 
+			      	    	  i32 20, i32 21, i32 22, i32 23, 
+					  i32 12, i32 13, i32 14, i32 15, 
+					  i32 28, i32 29, i32 30, i32 31>
+; CHECK-LE: vmrgew 2, 3, 2
+; CHECK-BE: vmrgow 2, 2, 3
+        store <16 x i8> %tmp3, <16 x i8>* %A
+	ret void
+; CHECK-LE: blr
+; CHECK-BE: blr
+}
+
+; Check for a vector merge instruction using a single input.
+; The shufflevector specifies the odd elements, using big endian element 
+; ordering. If run on a big endian machine, this should produce the vmrgow 
+; instruction. If run on a little endian machine, this should produce the
+; vmrgew instruction. 
+define void @check_merge_odd_xx(<16 x i8>* %A) {
+entry:
+; CHECK-LE-LABEL: @check_merge_odd_xx
+; CHECK-BE-LABEL: @check_merge_odd_xx
+        %tmp = load <16 x i8>, <16 x i8>* %A
+	%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, 
+	      		      <16 x i32> <i32 4, i32 5, i32 6, i32 7, 
+			      	    	  i32 4, i32 5, i32 6, i32 7, 
+					  i32 12, i32 13, i32 14, i32 15, 
+					  i32 12, i32 13, i32 14, i32 15>
+; CHECK-LE: vmrgew 2, 2, 2
+; CHECK-BE: vmrgow 2, 2, 2
+        store <16 x i8> %tmp2, <16 x i8>* %A
+	ret void
+; CHECK-LE: blr
+; CHECK-BE: blr
+}
+
diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll
index b185fed4cd5b..f85acebeea67 100644
--- a/test/CodeGen/PowerPC/vsx.ll
+++ b/test/CodeGen/PowerPC/vsx.ll
@@ -1,9 +1,8 @@
-; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
-; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
-; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
-; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s
 
 define double @test1(double %a, double %b) {
 entry:
@@ -13,6 +12,10 @@ entry:
 ; CHECK-LABEL: @test1
 ; CHECK: xsmuldp 1, 1, 2
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test1
+; CHECK-LE: xsmuldp 1, 1, 2
+; CHECK-LE: blr
 }
 
 define double @test2(double %a, double %b) {
@@ -23,6 +26,10 @@ entry:
 ; CHECK-LABEL: @test2
 ; CHECK: xsdivdp 1, 1, 2
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test2
+; CHECK-LE: xsdivdp 1, 1, 2
+; CHECK-LE: blr
 }
 
 define double @test3(double %a, double %b) {
@@ -33,6 +40,10 @@ entry:
 ; CHECK-LABEL: @test3
 ; CHECK: xsadddp 1, 1, 2
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test3
+; CHECK-LE: xsadddp 1, 1, 2
+; CHECK-LE: blr
 }
 
 define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
@@ -43,6 +54,10 @@ entry:
 ; CHECK-LABEL: @test4
 ; CHECK: xvadddp 34, 34, 35
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test4
+; CHECK-LE: xvadddp 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
@@ -60,6 +75,10 @@ entry:
 ; CHECK-FISL: xxlxor 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test5
+; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
@@ -77,6 +96,10 @@ entry:
 ; CHECK-FISL: xxlxor 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test6
+; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
@@ -94,6 +117,10 @@ entry:
 ; CHECK-FISL: xxlxor 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test7
+; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
@@ -111,6 +138,10 @@ entry:
 ; CHECK-FISL: xxlor 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test8
+; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
@@ -128,6 +159,10 @@ entry:
 ; CHECK-FISL: xxlor 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test9
+; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
@@ -145,6 +180,10 @@ entry:
 ; CHECK-FISL: xxlor 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test10
+; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
@@ -162,6 +201,10 @@ entry:
 ; CHECK-FISL: xxland 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test11
+; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
@@ -179,6 +222,10 @@ entry:
 ; CHECK-FISL: xxland 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test12
+; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
@@ -196,6 +243,10 @@ entry:
 ; CHECK-FISL: xxland 36, 36, 37
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test13
+; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
@@ -221,6 +272,10 @@ entry:
 ; CHECK-FISL: ori 0, 0, 65520
 ; CHECK-FISL: stvx 0, 1, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test14
+; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
@@ -246,6 +301,10 @@ entry:
 ; CHECK-FISL: ori 0, 0, 65520
 ; CHECK-FISL: stvx 0, 1, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test15
+; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
@@ -271,6 +330,10 @@ entry:
 ; CHECK-FISL: ori 0, 0, 65520
 ; CHECK-FISL: stvx 0, 1, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test16
+; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
@@ -294,6 +357,10 @@ entry:
 ; CHECK-FISL: xxland 37, 37, 32
 ; CHECK-FISL: vor 2, 5, 5
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test17
+; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
@@ -320,6 +387,10 @@ entry:
 ; CHECK-FISL: ori 0, 0, 65520
 ; CHECK-FISL: stvx 4, 1, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test18
+; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
@@ -346,6 +417,10 @@ entry:
 ; CHECK-FISL: ori 0, 0, 65520
 ; CHECK-FISL: stvx 4, 1, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test19
+; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
@@ -367,6 +442,11 @@ entry:
 ; CHECK-FISL: xxsel 32, 32, 33, 38
 ; CHECK-FISL: vor 2, 0, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test20
+; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5
+; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: blr
 }
 
 define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
@@ -389,6 +469,11 @@ entry:
 ; CHECK-FISL: xxsel 32, 38, 39, 32
 ; CHECK-FISL: vor 2, 0, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test21
+; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37
+; CHECK-LE: xxsel 34, 35, 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
@@ -418,6 +503,17 @@ entry:
 ; CHECK-FISL-DAG: xxlor
 ; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}}
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test22
+; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
+; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
+; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
+; CHECK-LE-DAG: xxlnor
+; CHECK-LE-DAG: xxlnor
+; CHECK-LE-DAG: xxlor
+; CHECK-LE-DAG: xxlor
+; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: blr
 }
 
 define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
@@ -439,6 +535,11 @@ entry:
 ; CHECK-FISL: xxsel 32, 32, 33, 38
 ; CHECK-FISL: vor 2, 0, 
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test23
+; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5
+; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: blr
 }
 
 define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
@@ -460,6 +561,11 @@ entry:
 ; CHECK-FISL: xxsel 32, 32, 33, 38
 ; CHECK-FISL: vor 2, 0, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test24
+; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5
+; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: blr
 }
 
 define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
@@ -472,6 +578,11 @@ entry:
 ; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37
 ; CHECK: xxsel 34, 35, 34, [[V1]]
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test25
+; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37
+; CHECK-LE: xxsel 34, 35, 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
@@ -489,6 +600,9 @@ define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK: add
 ; CHECK: add
 ; CHECK: blr
+
+; CHECK-LE: vaddudm 2, 2, 3
+; CHECK-LE: blr
 }
 
 define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
@@ -498,6 +612,10 @@ define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: @test27
 ; CHECK: xxland 34, 34, 35
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test27
+; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <2 x double> @test28(<2 x double>* %a) {
@@ -507,6 +625,11 @@ define <2 x double> @test28(<2 x double>* %a) {
 ; CHECK-LABEL: @test28
 ; CHECK: lxvd2x 34, 0, 3
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test28
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define void @test29(<2 x double>* %a, <2 x double> %b) {
@@ -516,6 +639,11 @@ define void @test29(<2 x double>* %a, <2 x double> %b) {
 ; CHECK-LABEL: @test29
 ; CHECK: stxvd2x 34, 0, 3
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test29
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
 }
 
 define <2 x double> @test28u(<2 x double>* %a) {
@@ -525,6 +653,11 @@ define <2 x double> @test28u(<2 x double>* %a) {
 ; CHECK-LABEL: @test28u
 ; CHECK: lxvd2x 34, 0, 3
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test28u
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define void @test29u(<2 x double>* %a, <2 x double> %b) {
@@ -534,6 +667,11 @@ define void @test29u(<2 x double>* %a, <2 x double> %b) {
 ; CHECK-LABEL: @test29u
 ; CHECK: stxvd2x 34, 0, 3
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test29u
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
 }
 
 define <2 x i64> @test30(<2 x i64>* %a) {
@@ -550,6 +688,11 @@ define <2 x i64> @test30(<2 x i64>* %a) {
 ; CHECK-FISL: vor 3, 2, 2
 ; CHECK-FISL: vor 2, 3, 3
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test30
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define void @test31(<2 x i64>* %a, <2 x i64> %b) {
@@ -559,6 +702,11 @@ define void @test31(<2 x i64>* %a, <2 x i64> %b) {
 ; CHECK-LABEL: @test31
 ; CHECK: stxvd2x 34, 0, 3
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test31
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
 }
 
 define <4 x float> @test32(<4 x float>* %a) {
@@ -573,6 +721,11 @@ define <4 x float> @test32(<4 x float>* %a) {
 ; CHECK-FISL: lxvw4x 0, 0, 3
 ; CHECK-FISL: xxlor 34, 0, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test32
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define void @test33(<4 x float>* %a, <4 x float> %b) {
@@ -587,6 +740,11 @@ define void @test33(<4 x float>* %a, <4 x float> %b) {
 ; CHECK-FISL: vor 3, 2, 2
 ; CHECK-FISL: stxvw4x 35, 0, 3
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test33
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
 }
 
 define <4 x float> @test32u(<4 x float>* %a) {
@@ -599,6 +757,11 @@ define <4 x float> @test32u(<4 x float>* %a) {
 ; CHECK-DAG: lvx
 ; CHECK: vperm 2,
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test32u
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define void @test33u(<4 x float>* %a, <4 x float> %b) {
@@ -613,6 +776,11 @@ define void @test33u(<4 x float>* %a, <4 x float> %b) {
 ; CHECK-FISL: vor 3, 2, 2
 ; CHECK-FISL: stxvw4x 35, 0, 3
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test33u
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
 }
 
 define <4 x i32> @test34(<4 x i32>* %a) {
@@ -629,6 +797,11 @@ define <4 x i32> @test34(<4 x i32>* %a) {
 ; CHECK-FISL: vor 3, 2, 2
 ; CHECK-FISL: vor 2, 3, 3
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test34
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define void @test35(<4 x i32>* %a, <4 x i32> %b) {
@@ -643,6 +816,11 @@ define void @test35(<4 x i32>* %a, <4 x i32> %b) {
 ; CHECK-FISL: vor 3, 2, 2
 ; CHECK-FISL: stxvw4x 35, 0, 3
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test35
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
 }
 
 define <2 x double> @test40(<2 x i64> %a) {
@@ -652,6 +830,10 @@ define <2 x double> @test40(<2 x i64> %a) {
 ; CHECK-LABEL: @test40
 ; CHECK: xvcvuxddp 34, 34
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test40
+; CHECK-LE: xvcvuxddp 34, 34
+; CHECK-LE: blr
 }
 
 define <2 x double> @test41(<2 x i64> %a) {
@@ -661,6 +843,10 @@ define <2 x double> @test41(<2 x i64> %a) {
 ; CHECK-LABEL: @test41
 ; CHECK: xvcvsxddp 34, 34
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test41
+; CHECK-LE: xvcvsxddp 34, 34
+; CHECK-LE: blr
 }
 
 define <2 x i64> @test42(<2 x double> %a) {
@@ -670,6 +856,10 @@ define <2 x i64> @test42(<2 x double> %a) {
 ; CHECK-LABEL: @test42
 ; CHECK: xvcvdpuxds 34, 34
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test42
+; CHECK-LE: xvcvdpuxds 34, 34
+; CHECK-LE: blr
 }
 
 define <2 x i64> @test43(<2 x double> %a) {
@@ -679,6 +869,10 @@ define <2 x i64> @test43(<2 x double> %a) {
 ; CHECK-LABEL: @test43
 ; CHECK: xvcvdpsxds 34, 34
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test43
+; CHECK-LE: xvcvdpsxds 34, 34
+; CHECK-LE: blr
 }
 
 define <2 x float> @test44(<2 x i64> %a) {
@@ -726,6 +920,10 @@ define <2 x double> @test50(double* %a) {
 ; CHECK-LABEL: @test50
 ; CHECK: lxvdsx 34, 0, 3
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test50
+; CHECK-LE: lxvdsx 34, 0, 3
+; CHECK-LE: blr
 }
 
 define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
@@ -735,6 +933,10 @@ define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: @test51
 ; CHECK: xxspltd 34, 34, 0
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test51
+; CHECK-LE: xxspltd 34, 34, 1
+; CHECK-LE: blr
 }
 
 define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
@@ -744,6 +946,10 @@ define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: @test52
 ; CHECK: xxmrghd 34, 34, 35
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test52
+; CHECK-LE: xxmrgld 34, 35, 34
+; CHECK-LE: blr
 }
 
 define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
@@ -753,6 +959,10 @@ define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: @test53
 ; CHECK: xxmrghd 34, 35, 34
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test53
+; CHECK-LE: xxmrgld 34, 34, 35
+; CHECK-LE: blr
 }
 
 define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
@@ -762,6 +972,10 @@ define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: @test54
 ; CHECK: xxpermdi 34, 34, 35, 2
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test54
+; CHECK-LE: xxpermdi 34, 35, 34, 2
+; CHECK-LE: blr
 }
 
 define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
@@ -771,6 +985,10 @@ define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: @test55
 ; CHECK: xxmrgld 34, 34, 35
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test55
+; CHECK-LE: xxmrghd 34, 35, 34
+; CHECK-LE: blr
 }
 
 define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
@@ -780,6 +998,10 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: @test56
 ; CHECK: xxmrgld 34, 34, 35
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test56
+; CHECK-LE: xxmrghd 34, 35, 34
+; CHECK-LE: blr
 }
 
 define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
@@ -836,6 +1058,10 @@ define double @test63(<2 x double> %a) {
 ; CHECK-FISL: xxlor 0, 34, 34
 ; CHECK-FISL: fmr 1, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test63
+; CHECK-LE: xxswapd 1, 34
+; CHECK-LE: blr
 }
 
 define double @test64(<2 x double> %a) {
@@ -851,6 +1077,9 @@ define double @test64(<2 x double> %a) {
 ; CHECK-FISL: xxlor 0, 34, 34
 ; CHECK-FISL: fmr 1, 0
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test64
+; CHECK-LE: xxlor 1, 34, 34
 }
 
 define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
@@ -867,6 +1096,10 @@ define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-FISL: vcmpequw 4, 5, 4
 ; CHECK-FISL: vor 2, 4, 4
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test65
+; CHECK-LE: vcmpequd 2, 2, 3
+; CHECK-LE: blr
 }
 
 define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
@@ -882,6 +1115,11 @@ define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4
 ; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test66
+; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3
+; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-LE: blr
 }
 
 define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
@@ -896,6 +1134,10 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK: cmpld
 ; CHECK: lxvd2x
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test67
+; CHECK-LE: vcmpgtud 2, 3, 2
+; CHECK-LE: blr
 }
 
 define <2 x double> @test68(<2 x i32> %a) {
@@ -906,6 +1148,11 @@ define <2 x double> @test68(<2 x i32> %a) {
 ; CHECK: xxsldwi [[V1:[0-9]+]], 34, 34, 1
 ; CHECK: xvcvsxwdp 34, [[V1]]
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test68
+; CHECK-LE: xxsldwi [[V1:[0-9]+]], 34, 34, 1
+; CHECK-LE: xvcvsxwdp 34, [[V1]]
+; CHECK-LE: blr
 }
 
 define <2 x double> @test69(<2 x i16> %a) {
@@ -920,6 +1167,15 @@ define <2 x double> @test69(<2 x i16> %a) {
 ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
 ; CHECK: xvcvsxwdp 34, [[V4]]
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test69
+; CHECK-LE: vspltisw [[V1:[0-9]+]], 8
+; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
+; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
+; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]]
+; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
+; CHECK-LE: xvcvsxwdp 34, [[V4]]
+; CHECK-LE: blr
 }
 
 define <2 x double> @test70(<2 x i8> %a) {
@@ -934,6 +1190,15 @@ define <2 x double> @test70(<2 x i8> %a) {
 ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
 ; CHECK: xvcvsxwdp 34, [[V4]]
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test70
+; CHECK-LE: vspltisw [[V1:[0-9]+]], 12
+; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
+; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
+; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]]
+; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
+; CHECK-LE: xvcvsxwdp 34, [[V4]]
+; CHECK-LE: blr
 }
 
 define <2 x i32> @test80(i32 %v) {
@@ -960,6 +1225,16 @@ define <2 x i32> @test80(i32 %v) {
 ; CHECK-FISL-DAG: std [[R3]], -16(1)
 ; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]]
 ; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test80
+; CHECK-LE-DAG: addi [[R1:[0-9]+]], 1, -16
+; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
+; CHECK-LE-DAG: lxvd2x [[V1:[0-9]+]], 0, [[R1]]
+; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]]
+; CHECK-LE-DAG: xxswapd 34, [[V1]]
+; CHECK-LE-DAG: xxswapd 35, [[V2]]
+; CHECK-LE: vaddudm 2, 2, 3
+; CHECK-LE: blr
 }
 
 define <2 x double> @test81(<4 x float> %b) {
@@ -968,6 +1243,9 @@ define <2 x double> @test81(<4 x float> %b) {
 
 ; CHECK-LABEL: @test81
 ; CHECK: blr
+
+; CHECK-LE-LABEL: @test81
+; CHECK-LE: blr
 }
 
 define double @test82(double %a, double %b, double %c, double %d) {
@@ -983,4 +1261,8 @@ entry:
 ; CHECK-FISL-LABEL: @test82
 ; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
 ; CHECK-FISL: beq [[REG]], {{.*}}
+
+; CHECK-LE-LABEL: @test82
+; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4
+; CHECK-LE: beqlr [[REG]]
 }