vendor/llvm/llvm-release_601-r335540vendor/llvm-60

3 files changed, 291 insertions, 0 deletions

diff --git a/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
index 67733795ed5d..f2ca07367b99 100644
--- a/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -561,6 +561,25 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
+  define i64 @testRLDICLo2(i64 %a, i64 %b) local_unnamed_addr #0 {
+  entry:
+    %shr = lshr i64 %a, 11
+    %and = and i64 %shr, 16777215
+    %tobool = icmp eq i64 %and, 0
+    %cond = select i1 %tobool, i64 %b, i64 %and
+    ret i64 %cond
+  }
+
+  define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {
+  entry:
+    %shr = lshr i64 %a, 11
+    %and = and i64 %shr, 16777215
+    %tobool = icmp eq i64 %and, 0
+    %cond = select i1 %tobool, i64 %b, i64 %and
+    ret i64 %cond
+  }
+  
+  ; Function Attrs: norecurse nounwind readnone
   define zeroext i32 @testRLWINM(i32 zeroext %a) local_unnamed_addr #0 {
   entry:
     %shl = shl i32 %a, 4
@@ -602,6 +621,15 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
+  define zeroext i32 @testRLWINMo2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  entry:
+    %and = and i32 %a, 255
+    %tobool = icmp eq i32 %and, 0
+    %cond = select i1 %tobool, i32 %b, i32 %a
+    ret i32 %cond
+  }
+
+  ; Function Attrs: norecurse nounwind readnone
   define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %a.tr = trunc i64 %a to i32
@@ -3904,6 +3932,113 @@ body:             |
 
 ...
 ---
+name:            testRLDICLo2
+# CHECK-ALL: name: testRLDICLo2
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: g8rc, preferred-register: '' }
+  - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
+  - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
+  - { id: 3, class: crrc, preferred-register: '' }
+  - { id: 4, class: g8rc, preferred-register: '' }
+liveins:         
+  - { reg: '%x3', virtual-reg: '%0' }
+  - { reg: '%x4', virtual-reg: '%1' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.0.entry:
+    liveins: %x3, %x4
+  
+    %1 = COPY %x4
+    %0 = LI8 200
+    %2 = RLDICLo %0, 61, 3, implicit-def %cr0
+    ; CHECK-NOT: ANDI
+    ; CHECK-LATE-NOT: andi.
+    %3 = COPY killed %cr0
+    %4 = ISEL8 %1, %2, %3.sub_eq
+    %x3 = COPY %4
+    BLR8 implicit %lr8, implicit %rm, implicit %x3
+
+...
+---
+name:            testRLDICLo3
+# CHECK-ALL: name: testRLDICLo3
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: g8rc, preferred-register: '' }
+  - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
+  - { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
+  - { id: 3, class: crrc, preferred-register: '' }
+  - { id: 4, class: g8rc, preferred-register: '' }
+liveins:         
+  - { reg: '%x3', virtual-reg: '%0' }
+  - { reg: '%x4', virtual-reg: '%1' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.0.entry:
+    liveins: %x3, %x4
+  
+    %1 = COPY %x4
+    %0 = LI8 2
+    %2 = RLDICLo %0, 32, 32, implicit-def %cr0
+    ; CHECK: ANDIo8 %0, 0
+    ; CHECK-LATE: li 3, 2
+    ; CHECK-LATE: andi. 3, 3, 0
+    %3 = COPY killed %cr0
+    %4 = ISEL8 %1, %2, %3.sub_eq
+    %x3 = COPY %4
+    BLR8 implicit %lr8, implicit %rm, implicit %x3
+
+...
+---
 name:            testRLWINM
 # CHECK-ALL: name: testRLWINM
 alignment:       4
@@ -4170,6 +4305,69 @@ body:             |
 
 ...
 ---
+name:            testRLWINMo2
+# CHECK-ALL: name: testRLWINMo2
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: g8rc, preferred-register: '' }
+  - { id: 1, class: g8rc, preferred-register: '' }
+  - { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
+  - { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
+  - { id: 4, class: gprc, preferred-register: '' }
+  - { id: 5, class: crrc, preferred-register: '' }
+  - { id: 6, class: gprc, preferred-register: '' }
+  - { id: 7, class: g8rc, preferred-register: '' }
+  - { id: 8, class: g8rc, preferred-register: '' }
+  - { id: 9, class: g8rc, preferred-register: '' }
+liveins:         
+  - { reg: '%x3', virtual-reg: '%0' }
+  - { reg: '%x4', virtual-reg: '%1' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+constants:       
+body:             |
+  bb.0.entry:
+    liveins: %x3, %x4
+  
+    %1 = COPY %x4
+    %0 = COPY %x3
+    %2 = COPY %1.sub_32
+    %3 = LI -22
+    %4 = RLWINMo %3, 5, 24, 31, implicit-def %cr0
+    ; CHECK-NOT: ANDI
+    ; CHECK-LATE-NOT: andi.
+    %5 = COPY killed %cr0
+    %6 = ISEL %2, %3, %5.sub_eq
+    %8 = IMPLICIT_DEF
+    %7 = INSERT_SUBREG %8, killed %6, 1
+    %9 = RLDICL killed %7, 0, 32
+    %x3 = COPY %9
+    BLR8 implicit %lr8, implicit %rm, implicit %x3
+
+...
+---
 name:            testRLWINM8o
 # CHECK-ALL: name: testRLWINM8o
 alignment:       4
diff --git a/test/CodeGen/PowerPC/no-dup-of-bdnz.ll b/test/CodeGen/PowerPC/no-dup-of-bdnz.ll
new file mode 100644
index 000000000000..7d72242aa457
--- /dev/null
+++ b/test/CodeGen/PowerPC/no-dup-of-bdnz.ll
@@ -0,0 +1,75 @@
+; RUN: opt -early-cse-memssa -loop-rotate -licm -loop-rotate -S %s -o - | FileCheck %s
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+source_filename = "bugpoint-output-8903f29.bc"
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+define void @test(i64 %arg.ssa, i64 %arg.nb) local_unnamed_addr {
+; Ensure that loop rotation doesn't duplicate the call to
+; llvm.ppc.is.decremented.ctr.nonzero
+; CHECK-LABEL: test
+; CHECK: call i1 @llvm.ppc.is.decremented.ctr.nonzero
+; CHECK-NOT: call i1 @llvm.ppc.is.decremented.ctr.nonzero
+; CHECK: declare i1 @llvm.ppc.is.decremented.ctr.nonzero
+entry:
+  switch i32 undef, label %BB_8 [
+    i32 -2, label %BB_9
+    i32 0, label %BB_9
+  ]
+
+BB_1:                                    ; preds = %BB_12, %BB_4
+  %bcount.1.us = phi i64 [ %.810.us, %BB_4 ], [ 0, %BB_12 ]
+  %0 = add i64 %arg.ssa, %bcount.1.us
+  %.568.us = load i32, i32* undef, align 4
+  %.15.i.us = icmp slt i32 0, %.568.us
+  br i1 %.15.i.us, label %BB_3, label %BB_2
+
+BB_2:                                          ; preds = %BB_1
+  %.982.us = add nsw i64 %0, 1
+  unreachable
+
+BB_3:                                          ; preds = %BB_1
+  %1 = add i64 %arg.ssa, %bcount.1.us
+  %2 = add i64 %1, 1
+  %3 = call i1 @llvm.ppc.is.decremented.ctr.nonzero()
+  br i1 %3, label %BB_4, label %BB_7
+
+BB_4:                                          ; preds = %BB_3
+  %.810.us = add nuw nsw i64 %bcount.1.us, 1
+  br label %BB_1
+
+BB_5:                                         ; preds = %BB_7, %BB_5
+  %lsr.iv20.i116 = phi i64 [ %2, %BB_7 ], [ %lsr.iv.next21.i126, %BB_5 ]
+  %lsr.iv.next21.i126 = add i64 %lsr.iv20.i116, 1
+  br i1 undef, label %BB_5, label %BB_6
+
+BB_6:                                         ; preds = %BB_5
+  ret void
+
+BB_7:                                     ; preds = %BB_3
+  br label %BB_5
+
+BB_8:                                           ; preds = %entry
+  ret void
+
+BB_9:                                        ; preds = %entry, %entry
+  br label %BB_10
+
+BB_10:                               ; preds = %BB_9
+  br label %BB_11
+
+BB_11:                                         ; preds = %BB_11, %BB_10
+  br i1 undef, label %BB_11, label %BB_12
+
+BB_12:                                         ; preds = %BB_11
+  call void @llvm.ppc.mtctr.i64(i64 %arg.nb)
+  br label %BB_1
+}
+
+; Function Attrs: nounwind
+declare void @llvm.ppc.mtctr.i64(i64) #0
+
+; Function Attrs: nounwind
+declare i1 @llvm.ppc.is.decremented.ctr.nonzero() #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/PowerPC/pr35402.ll b/test/CodeGen/PowerPC/pr35402.ll
new file mode 100644
index 000000000000..06e6d963b13f
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr35402.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O2 < %s | FileCheck %s
+target triple = "powerpc64le-linux-gnu"
+
+define void @test(i8* %p, i64 %data) {
+entry:
+  %0 = tail call i64 @llvm.bswap.i64(i64 %data)
+  %ptr = bitcast i8* %p to i48*
+  %val = trunc i64 %0 to i48
+  store i48 %val, i48* %ptr, align 1
+  ret void
+
+; CHECK:     sth
+; CHECK:     stw
+; CHECK-NOT: stdbrx
+
+}
+
+declare i64 @llvm.bswap.i64(i64)