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| author | Dimitry Andric <dim@FreeBSD.org> | 2015-01-18 16:17:27 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-01-18 16:17:27 +0000 |
| commit | 67c32a98315f785a9ec9d531c1f571a0196c7463 (patch) | |
| tree | 4abb9cbeecc7901726dd0b4a37369596c852e9ef /test/CodeGen/R600/llvm.SI.sample-masked.ll | |
| parent | 9f61947910e6ab40de38e6b4034751ef1513200f (diff) | |
| download | src-test2-67c32a98315f785a9ec9d531c1f571a0196c7463.tar.gz src-test2-67c32a98315f785a9ec9d531c1f571a0196c7463.zip | |
Notes
Diffstat (limited to 'test/CodeGen/R600/llvm.SI.sample-masked.ll')
| -rw-r--r-- | test/CodeGen/R600/llvm.SI.sample-masked.ll | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/test/CodeGen/R600/llvm.SI.sample-masked.ll b/test/CodeGen/R600/llvm.SI.sample-masked.ll index 445359a4ced7..071938f2c249 100644 --- a/test/CodeGen/R600/llvm.SI.sample-masked.ll +++ b/test/CodeGen/R600/llvm.SI.sample-masked.ll @@ -1,7 +1,7 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s -; CHECK-LABEL: @v1 -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 13 +; CHECK-LABEL: {{^}}v1: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 13 define void @v1(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -13,8 +13,8 @@ entry: ret void } -; CHECK-LABEL: @v2 -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 11 +; CHECK-LABEL: {{^}}v2: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 11 define void @v2(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -26,8 +26,8 @@ entry: ret void } -; CHECK-LABEL: @v3 -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 14 +; CHECK-LABEL: {{^}}v3: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14 define void @v3(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -39,8 +39,8 @@ entry: ret void } -; CHECK-LABEL: @v4 -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 7 +; CHECK-LABEL: {{^}}v4: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 7 define void @v4(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -52,8 +52,8 @@ entry: ret void } -; CHECK-LABEL: @v5 -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 10 +; CHECK-LABEL: {{^}}v5: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10 define void @v5(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -64,8 +64,8 @@ entry: ret void } -; CHECK-LABEL: @v6 -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 6 +; CHECK-LABEL: {{^}}v6: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 6 define void @v6(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 @@ -76,8 +76,8 @@ entry: ret void } -; CHECK-LABEL: @v7 -; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 9 +; CHECK-LABEL: {{^}}v7: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 9 define void @v7(i32 %a1) #0 { entry: %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 |