diff options
| author | Roman Divacky <rdivacky@FreeBSD.org> | 2010-05-04 16:11:02 +0000 |
|---|---|---|
| committer | Roman Divacky <rdivacky@FreeBSD.org> | 2010-05-04 16:11:02 +0000 |
| commit | d7f7719e5e082c0b8ea2182dcbd2242b7834aa26 (patch) | |
| tree | 70fbd90da02177c8e6ef82adba9fa8ace285a5e3 /test/CodeGen/X86 | |
| parent | 9f4a1da9a0a56a0b0a7f8249f34b3cdea6179c41 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/X86')
76 files changed, 2544 insertions, 722 deletions
diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll index 58e186b4c4f8..ef19d72150a0 100644 --- a/test/CodeGen/X86/2007-01-08-InstrSched.ll +++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll @@ -11,12 +11,12 @@ define float @foo(float %x) nounwind { %tmp14 = fadd float %tmp12, %tmp7 ret float %tmp14 -; CHECK: mulss LCPI1_0(%rip) -; CHECK: mulss LCPI1_1(%rip) +; CHECK: mulss LCPI0_0(%rip) +; CHECK: mulss LCPI0_1(%rip) ; CHECK: addss -; CHECK: mulss LCPI1_2(%rip) +; CHECK: mulss LCPI0_2(%rip) ; CHECK: addss -; CHECK: mulss LCPI1_3(%rip) +; CHECK: mulss LCPI0_3(%rip) ; CHECK: addss ; CHECK: ret } diff --git a/test/CodeGen/X86/2007-05-05-Personality.ll b/test/CodeGen/X86/2007-05-05-Personality.ll index c92783e5e4eb..a9b17d3b8f36 100644 --- a/test/CodeGen/X86/2007-05-05-Personality.ll +++ b/test/CodeGen/X86/2007-05-05-Personality.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-pc-linux-gnu -enable-eh -o - | grep zPL +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -o - | grep zPL @error = external global i8 ; <i8*> [#uses=2] diff --git a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll index a3ff2f60c8d7..ae49bd002208 100644 --- a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll +++ b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-pc-linux-gnu -enable-eh -disable-fp-elim | not grep {addl .12, %esp} +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -disable-fp-elim | not grep {addl .12, %esp} ; PR1398 %struct.S = type { i32, i32 } diff --git a/test/CodeGen/X86/2007-06-04-tailmerge4.ll b/test/CodeGen/X86/2007-06-04-tailmerge4.ll index baf2377c5a02..d5ec0898b9a9 100644 --- a/test/CodeGen/X86/2007-06-04-tailmerge4.ll +++ b/test/CodeGen/X86/2007-06-04-tailmerge4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -enable-eh -asm-verbose | grep invcont131 +; RUN: llc < %s -asm-verbose | grep invcont131 ; PR 1496: tail merge was incorrectly removing this block ; ModuleID = 'report.1.bc' diff --git a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll index 56ee2a314990..c3403a0b4eeb 100644 --- a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll +++ b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin -enable-eh | grep {isNullOrNil].eh"} | count 2 +; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | grep {isNullOrNil].eh"} | count 2 %struct.NSString = type { } %struct._objc__method_prototype_list = type opaque diff --git a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll index 387645f74366..b936686798f0 100644 --- a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll +++ b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep {.byte 0} +; RUN: llc < %s -march=x86 | grep nop target triple = "i686-apple-darwin8" diff --git a/test/CodeGen/X86/2008-07-11-SpillerBug.ll b/test/CodeGen/X86/2008-07-11-SpillerBug.ll index 548b44db6d27..d0023b28c6dd 100644 --- a/test/CodeGen/X86/2008-07-11-SpillerBug.ll +++ b/test/CodeGen/X86/2008-07-11-SpillerBug.ll @@ -3,6 +3,7 @@ ; CHECK: andl $65534, % ; CHECK-NEXT: movl % +; CHECK-NEXT: movzwl ; CHECK-NEXT: movl $17 @g_5 = external global i16 ; <i16*> [#uses=2] diff --git a/test/CodeGen/X86/2008-10-16-SpillerBug.ll b/test/CodeGen/X86/2008-10-16-SpillerBug.ll index b8ca364d1798..87305a0b3116 100644 --- a/test/CodeGen/X86/2008-10-16-SpillerBug.ll +++ b/test/CodeGen/X86/2008-10-16-SpillerBug.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edi} +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 41 +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | FileCheck %s %struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 } %struct.XXDAlphaTest = type { float, i16, i8, i8 } @@ -61,11 +62,15 @@ define void @t(%struct.XXDState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._XXVMConstants* %cnstn, %struct.YYToken* %pstrm, %struct.XXVMVPContext* %vmctx, %struct.XXVMTextures* %txtrs, %struct.XXVMVPStack* %vpstk, <4 x float>* %atr0, <4 x float>* %atr1, <4 x float>* %atr2, <4 x float>* %atr3, <4 x float>* %vtx0, <4 x float>* %vtx1, <4 x float>* %vtx2, <4 x float>* %vtx3, [4 x <4 x float>]* %tmpGbl, i32* %oldMsk, <4 x i32>* %adrGbl, i64 %key_token) nounwind { entry: +; CHECK: t: %0 = trunc i64 %key_token to i32 ; <i32> [#uses=1] %1 = getelementptr %struct.YYToken* %pstrm, i32 %0 ; <%struct.YYToken*> [#uses=5] br label %bb1132 bb51: ; preds = %bb1132 +; CHECK: .align 4 +; CHECK: xorl %ecx, %ecx +; CHECK: andl $7 %2 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec, i32 0, i32 0 ; <i16*> [#uses=1] %3 = load i16* %2, align 1 ; <i16> [#uses=3] %4 = lshr i16 %3, 6 ; <i16> [#uses=1] diff --git a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll index a6cabc4fd331..5eba9b9c3022 100644 --- a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll +++ b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll @@ -3,7 +3,7 @@ ; Make sure the copy after inline asm is not coalesced away. ; CHECK: ## InlineAsm End -; CHECK-NEXT: BB1_2: +; CHECK-NEXT: BB0_2: ; CHECK-NEXT: movl %esi, %eax diff --git a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll index abbe97ac193e..69f644f5834b 100644 --- a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll +++ b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll @@ -4,7 +4,7 @@ ; rdar://6808032 ; CHECK: pextrw $14 -; CHECK-NEXT: movzbl +; CHECK-NEXT: shrl $8 ; CHECK-NEXT: (%ebp) ; CHECK-NEXT: pinsrw diff --git a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll index 2fd42f40d891..1d1462075492 100644 --- a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll +++ b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll @@ -1,38 +1,15 @@ ; RUN: llc < %s -march=x86-64 - %struct.tempsym_t = type { i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32 } - -define fastcc signext i8 @S_next_symbol(%struct.tempsym_t* %symptr) nounwind ssp { +define fastcc void @S_next_symbol(i448* %P) nounwind ssp { entry: - br label %bb116 - -bb: ; preds = %bb116 - switch i8 undef, label %bb14 [ - i8 9, label %bb116 - i8 32, label %bb116 - i8 10, label %bb116 - i8 13, label %bb116 - i8 12, label %bb116 - ] + br label %bb14 bb14: ; preds = %bb - br i1 undef, label %bb75, label %bb115 - -bb75: ; preds = %bb14 - %srcval16 = load i448* null, align 8 ; <i448> [#uses=1] + %srcval16 = load i448* %P, align 8 ; <i448> [#uses=1] %tmp = zext i32 undef to i448 ; <i448> [#uses=1] %tmp15 = shl i448 %tmp, 288 ; <i448> [#uses=1] %mask = and i448 %srcval16, -2135987035423586845985235064014169866455883682256196619149693890381755748887481053010428711403521 ; <i448> [#uses=1] %ins = or i448 %tmp15, %mask ; <i448> [#uses=1] - store i448 %ins, i448* null, align 8 - ret i8 1 - -bb115: ; preds = %bb14 - ret i8 1 - -bb116: ; preds = %bb, %bb, %bb, %bb, %bb, %entry - br i1 undef, label %bb, label %bb117 - -bb117: ; preds = %bb116 - ret i8 0 + store i448 %ins, i448* %P, align 8 + ret void } diff --git a/test/CodeGen/X86/2009-11-16-MachineLICM.ll b/test/CodeGen/X86/2009-11-16-MachineLICM.ll index 8f274df918d1..2ac688fd80af 100644 --- a/test/CodeGen/X86/2009-11-16-MachineLICM.ll +++ b/test/CodeGen/X86/2009-11-16-MachineLICM.ll @@ -15,7 +15,7 @@ bb.nph: ; preds = %entry br label %bb bb: ; preds = %bb, %bb.nph -; CHECK: LBB1_2: +; CHECK: LBB0_2: %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=2] %tmp9 = shl i64 %indvar, 2 ; <i64> [#uses=4] %tmp1016 = or i64 %tmp9, 1 ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll index 26bf09c723a0..d33f93ea7b27 100644 --- a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll +++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll @@ -13,7 +13,7 @@ entry: br label %bb1 bb1: -; CHECK: LBB1_1: +; CHECK: LBB0_1: ; CHECK: movaps %xmm0, (%rsp) %tmp2 = phi i32 [ %tmp3, %bb1 ], [ 0, %entry ] call void @llvm.memcpy.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8]* @str, i64 0, i64 0), i64 28, i32 1) diff --git a/test/CodeGen/X86/2010-01-07-UAMemFeature.ll b/test/CodeGen/X86/2010-01-07-UAMemFeature.ll index 3728f15d969c..bb24adb41817 100644 --- a/test/CodeGen/X86/2010-01-07-UAMemFeature.ll +++ b/test/CodeGen/X86/2010-01-07-UAMemFeature.ll @@ -6,6 +6,6 @@ target triple = "x86_64-unknown-linux-gnu" define <4 x float> @foo(<4 x float>* %P, <4 x float> %In) nounwind { %A = load <4 x float>* %P, align 4 - %B = add <4 x float> %A, %In + %B = fadd <4 x float> %A, %In ret <4 x float> %B } diff --git a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll index 172e1c73d568..c6936362048b 100644 --- a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll +++ b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll @@ -10,7 +10,7 @@ entry: ; CHECK: movl $1 ; CHECK: movl (%ebp), %eax ; CHECK: movl 4(%ebp), %edx -; CHECK: LBB1_1: +; CHECK: LBB0_1: ; CHECK-NOT: movl $1 ; CHECK-NOT: movl $0 ; CHECK: addl diff --git a/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll b/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll new file mode 100644 index 000000000000..ef1798d1ae43 --- /dev/null +++ b/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll @@ -0,0 +1,64 @@ +; RUN: llc < %s -O3 -relocation-model=pic -disable-fp-elim -mcpu=nocona +; +; This test case is reduced from Bullet. It crashes SSEDomainFix. +; +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10.0" + +declare i32 @_ZN11HullLibrary16CreateConvexHullERK8HullDescR10HullResult(i8*, i8* nocapture, i8* nocapture) ssp align 2 + +define void @_ZN17btSoftBodyHelpers4DrawEP10btSoftBodyP12btIDebugDrawi(i8* %psb, i8* %idraw, i32 %drawflags) ssp align 2 { +entry: + br i1 undef, label %bb92, label %bb58 + +bb58: ; preds = %entry + %0 = invoke i32 @_ZN11HullLibrary16CreateConvexHullERK8HullDescR10HullResult(i8* undef, i8* undef, i8* undef) + to label %invcont64 unwind label %lpad159 ; <i32> [#uses=0] + +invcont64: ; preds = %bb58 + br i1 undef, label %invcont65, label %bb.i.i + +bb.i.i: ; preds = %invcont64 + %1 = load <4 x float>* undef, align 16 ; <<4 x float>> [#uses=5] + br i1 undef, label %bb.nph.i.i, label %invcont65 + +bb.nph.i.i: ; preds = %bb.i.i + %tmp22.i.i = bitcast <4 x float> %1 to i128 ; <i128> [#uses=1] + %tmp23.i.i = trunc i128 %tmp22.i.i to i32 ; <i32> [#uses=1] + %2 = bitcast i32 %tmp23.i.i to float ; <float> [#uses=1] + %tmp6.i = extractelement <4 x float> %1, i32 1 ; <float> [#uses=1] + %tmp2.i = extractelement <4 x float> %1, i32 2 ; <float> [#uses=1] + br label %bb1.i.i + +bb1.i.i: ; preds = %bb1.i.i, %bb.nph.i.i + %.tmp6.0.i.i = phi float [ %tmp2.i, %bb.nph.i.i ], [ %5, %bb1.i.i ] ; <float> [#uses=1] + %.tmp5.0.i.i = phi float [ %tmp6.i, %bb.nph.i.i ], [ %4, %bb1.i.i ] ; <float> [#uses=1] + %.tmp.0.i.i = phi float [ %2, %bb.nph.i.i ], [ %3, %bb1.i.i ] ; <float> [#uses=1] + %3 = fadd float %.tmp.0.i.i, undef ; <float> [#uses=2] + %4 = fadd float %.tmp5.0.i.i, undef ; <float> [#uses=2] + %5 = fadd float %.tmp6.0.i.i, undef ; <float> [#uses=2] + br i1 undef, label %bb2.return.loopexit_crit_edge.i.i, label %bb1.i.i + +bb2.return.loopexit_crit_edge.i.i: ; preds = %bb1.i.i + %tmp8.i = insertelement <4 x float> %1, float %3, i32 0 ; <<4 x float>> [#uses=1] + %tmp4.i = insertelement <4 x float> %tmp8.i, float %4, i32 1 ; <<4 x float>> [#uses=1] + %tmp.i = insertelement <4 x float> %tmp4.i, float %5, i32 2 ; <<4 x float>> [#uses=1] + br label %invcont65 + +invcont65: ; preds = %bb2.return.loopexit_crit_edge.i.i, %bb.i.i, %invcont64 + %.0.i = phi <4 x float> [ %tmp.i, %bb2.return.loopexit_crit_edge.i.i ], [ undef, %invcont64 ], [ %1, %bb.i.i ] ; <<4 x float>> [#uses=1] + %tmp15.i = extractelement <4 x float> %.0.i, i32 2 ; <float> [#uses=1] + %6 = fmul float %tmp15.i, undef ; <float> [#uses=1] + br label %bb.i265 + +bb.i265: ; preds = %bb.i265, %invcont65 + %7 = fsub float 0.000000e+00, %6 ; <float> [#uses=1] + store float %7, float* undef, align 4 + br label %bb.i265 + +bb92: ; preds = %entry + unreachable + +lpad159: ; preds = %bb58 + unreachable +} diff --git a/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..76cc1a497d3d --- /dev/null +++ b/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,34 @@ +; RUN: llc -O0 -march=x86 -asm-verbose < %s | FileCheck %s +; RUN: llc -O0 -march=x86-64 -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll new file mode 100644 index 000000000000..1c7c28c68e9f --- /dev/null +++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; rdar://7842028 + +; Do not delete partially dead copy instructions. +; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def> +; REP_MOVSD %ECX<imp-def,dead>, %EDI<imp-def,dead>, %ESI<imp-def,dead>, %ECX<imp-use,kill>, %EDI<imp-use,kill>, %ESI<imp-use,kill> + + +%struct.F = type { %struct.FC*, i32, i32, i8, i32, i32, i32 } +%struct.FC = type { [10 x i8], [32 x i32], %struct.FC*, i32 } + +define void @t(%struct.F* %this) nounwind { +entry: +; CHECK: t: +; CHECK: addq $12, %rsi + %BitValueArray = alloca [32 x i32], align 4 + %tmp2 = getelementptr inbounds %struct.F* %this, i64 0, i32 0 + %tmp3 = load %struct.FC** %tmp2, align 8 + %tmp4 = getelementptr inbounds %struct.FC* %tmp3, i64 0, i32 1, i64 0 + %tmp5 = bitcast [32 x i32]* %BitValueArray to i8* + %tmp6 = bitcast i32* %tmp4 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp5, i8* %tmp6, i64 128, i32 4, i1 false) + unreachable +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll b/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll new file mode 100644 index 000000000000..fadbd2191989 --- /dev/null +++ b/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll @@ -0,0 +1,42 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=core2 +; rdar://7857830 + +%0 = type opaque +%1 = type opaque + +define void @t(%0* %self, i8* nocapture %_cmd, %1* %scroller, i32 %hitPart, float %multiplier) nounwind optsize ssp { +entry: + switch i32 %hitPart, label %if.else [ + i32 7, label %if.then + i32 8, label %if.then + ] + +if.then: ; preds = %entry, %entry + %tmp69 = load float* null, align 4 ; <float> [#uses=1] + %cmp19 = icmp eq %1* null, %scroller ; <i1> [#uses=2] + %cond = select i1 %cmp19, float %tmp69, float 0.000000e+00 ; <float> [#uses=1] + %call36 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*)*)(i8* undef, i8* undef) nounwind optsize ; <i64> [#uses=2] + br i1 %cmp19, label %cond.true32, label %cond.false39 + +cond.true32: ; preds = %if.then + %sroa.store.elt68 = lshr i64 %call36, 32 ; <i64> [#uses=1] + %0 = trunc i64 %sroa.store.elt68 to i32 ; <i32> [#uses=1] + br label %cond.end47 + +cond.false39: ; preds = %if.then + %1 = trunc i64 %call36 to i32 ; <i32> [#uses=1] + br label %cond.end47 + +cond.end47: ; preds = %cond.false39, %cond.true32 + %cond48.in = phi i32 [ %0, %cond.true32 ], [ %1, %cond.false39 ] ; <i32> [#uses=1] + %cond48 = bitcast i32 %cond48.in to float ; <float> [#uses=1] + %div = fdiv float %cond, undef ; <float> [#uses=1] + %div58 = fdiv float %div, %cond48 ; <float> [#uses=1] + call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, float)*)(i8* undef, i8* undef, float %div58) nounwind optsize + ret void + +if.else: ; preds = %entry + ret void +} + +declare i8* @objc_msgSend(i8*, i8*, ...) diff --git a/test/CodeGen/X86/2010-04-21-CoalescerBug.ll b/test/CodeGen/X86/2010-04-21-CoalescerBug.ll new file mode 100644 index 000000000000..d5987645cfca --- /dev/null +++ b/test/CodeGen/X86/2010-04-21-CoalescerBug.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin +; rdar://7886733 + +%struct.CMTime = type <{ i64, i32, i32, i64 }> +%struct.CMTimeMapping = type { %struct.CMTimeRange, %struct.CMTimeRange } +%struct.CMTimeRange = type { %struct.CMTime, %struct.CMTime } + +define void @t(%struct.CMTimeMapping* noalias nocapture sret %agg.result) nounwind optsize ssp { +entry: + %agg.result1 = bitcast %struct.CMTimeMapping* %agg.result to i8* ; <i8*> [#uses=1] + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %agg.result1, i8* null, i64 96, i32 4, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll new file mode 100644 index 000000000000..4cd3be35e820 --- /dev/null +++ b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s + +define void @ti8(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <8 x i8> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <8 x i8> +; CHECK: movdq2q + %tmp3 = add <8 x i8> %tmp1, %tmp2 + store <8 x i8> %tmp3, <8 x i8>* null + ret void +} + +define void @ti16(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <4 x i16> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <4 x i16> +; CHECK: movdq2q + %tmp3 = add <4 x i16> %tmp1, %tmp2 + store <4 x i16> %tmp3, <4 x i16>* null + ret void +} + +define void @ti32(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <2 x i32> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <2 x i32> +; CHECK: movdq2q + %tmp3 = add <2 x i32> %tmp1, %tmp2 + store <2 x i32> %tmp3, <2 x i32>* null + ret void +} + +define void @ti64(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <1 x i64> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <1 x i64> +; CHECK: movdq2q + %tmp3 = add <1 x i64> %tmp1, %tmp2 + store <1 x i64> %tmp3, <1 x i64>* null + ret void +} diff --git a/test/CodeGen/X86/2010-04-29-CoalescerCrash.ll b/test/CodeGen/X86/2010-04-29-CoalescerCrash.ll new file mode 100644 index 000000000000..a22f38ae3baa --- /dev/null +++ b/test/CodeGen/X86/2010-04-29-CoalescerCrash.ll @@ -0,0 +1,142 @@ +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -verify-machineinstrs +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define void @_ZN12_GLOBAL__N_113SPUAsmPrinter15EmitInstructionEPKN4llvm12MachineInstrE(i8* %this, i8* %MI) nounwind inlinehint align 2 { +entry: + br i1 undef, label %"3.i", label %"4.i" + +"3.i": ; preds = %entry + unreachable + +"4.i": ; preds = %entry + switch i32 undef, label %_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit [ + i32 1, label %"5.i" + i32 2, label %"6.i" + i32 3, label %"7.i" + i32 4, label %"8.i" + i32 5, label %"9.i" + ] + +"5.i": ; preds = %"4.i" + unreachable + +"6.i": ; preds = %"4.i" + switch i32 undef, label %"11.i" [ + i32 1, label %"12.i" + i32 2, label %"13.i" + i32 3, label %_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit + i32 4, label %"14.i" + ] + +"7.i": ; preds = %"4.i" + unreachable + +"8.i": ; preds = %"4.i" + unreachable + +"9.i": ; preds = %"4.i" + unreachable + +"11.i": ; preds = %"6.i" + switch i32 undef, label %"15.i" [ + i32 1, label %"16.i" + i32 2, label %"17.i" + i32 3, label %"18.i" + i32 4, label %"19.i" + i32 5, label %"20.i" + i32 6, label %"21.i" + i32 7, label %"24.i" + i32 8, label %"27.i" + i32 9, label %"28.i" + i32 10, label %"29.i" + i32 11, label %"30.i" + i32 12, label %"31.i" + i32 13, label %"32.i" + i32 14, label %"39.i" + ] + +"12.i": ; preds = %"6.i" + unreachable + +"13.i": ; preds = %"6.i" + unreachable + +"14.i": ; preds = %"6.i" + unreachable + +"15.i": ; preds = %"11.i" + unreachable + +"16.i": ; preds = %"11.i" + unreachable + +"17.i": ; preds = %"11.i" + unreachable + +"18.i": ; preds = %"11.i" + unreachable + +"19.i": ; preds = %"11.i" + unreachable + +"20.i": ; preds = %"11.i" + unreachable + +"21.i": ; preds = %"11.i" + br i1 undef, label %"22.i", label %"23.i" + +"22.i": ; preds = %"21.i" + unreachable + +"23.i": ; preds = %"21.i" + unreachable + +"24.i": ; preds = %"11.i" + unreachable + +"27.i": ; preds = %"11.i" + unreachable + +"28.i": ; preds = %"11.i" + unreachable + +"29.i": ; preds = %"11.i" + unreachable + +"30.i": ; preds = %"11.i" + unreachable + +"31.i": ; preds = %"11.i" + unreachable + +"32.i": ; preds = %"11.i" + unreachable + +"39.i": ; preds = %"11.i" + br i1 undef, label %"41.i", label %"40.i" + +"40.i": ; preds = %"39.i" + unreachable + +"41.i": ; preds = %"39.i" + %0 = call i64 @_ZNK4llvm14MachineOperand6getImmEv(i8 undef) nounwind inlinehint ; <i64> [#uses=1] + %1 = trunc i64 %0 to i16 ; <i16> [#uses=1] + br i1 undef, label %"42.i", label %"43.i" + +"42.i": ; preds = %"41.i" + unreachable + +"43.i": ; preds = %"41.i" + %2 = and i16 %1, -16 ; <i16> [#uses=1] + %3 = sext i16 %2 to i64 ; <i64> [#uses=1] + %4 = call i8 @_ZN4llvm11raw_ostreamlsEl(i8 undef, i64 %3) nounwind ; <i8> [#uses=0] + unreachable + +_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit: ; preds = %"6.i", %"4.i" + ret void +} + +declare i64 @_ZNK4llvm14MachineOperand6getImmEv(i8) nounwind inlinehint align 2 + +declare i8 @_ZN4llvm11raw_ostreamlsEl(i8, i64) diff --git a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll new file mode 100644 index 000000000000..f5048afd7cc2 --- /dev/null +++ b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll @@ -0,0 +1,143 @@ +; RUN: llc < %s -O0 -regalloc=local -relocation-model=pic -disable-fp-elim | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10.0.0" + +%struct.S = type { [2 x i8*] } + +@_ZTIi = external constant i8* ; <i8**> [#uses=1] +@.str = internal constant [4 x i8] c"%p\0A\00" ; <[4 x i8]*> [#uses=1] +@llvm.used = appending global [1 x i8*] [i8* bitcast (i8* (%struct.S*, i32, %struct.S*)* @_Z4test1SiS_ to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +; Verify that %esi gets spilled before the call. +; CHECK: Z4test1SiS +; CHECK: movl %esi,{{.*}}(%ebp) +; CHECK: call __Z6throwsv + +define i8* @_Z4test1SiS_(%struct.S* byval %s1, i32 %n, %struct.S* byval %s2) ssp { +entry: + %retval = alloca i8*, align 4 ; <i8**> [#uses=2] + %n.addr = alloca i32, align 4 ; <i32*> [#uses=1] + %_rethrow = alloca i8* ; <i8**> [#uses=4] + %0 = alloca i32, align 4 ; <i32*> [#uses=1] + %cleanup.dst = alloca i32 ; <i32*> [#uses=3] + %cleanup.dst7 = alloca i32 ; <i32*> [#uses=6] + store i32 %n, i32* %n.addr + invoke void @_Z6throwsv() + to label %invoke.cont unwind label %try.handler + +invoke.cont: ; preds = %entry + store i32 1, i32* %cleanup.dst7 + br label %finally + +terminate.handler: ; preds = %match.end + %exc = call i8* @llvm.eh.exception() ; <i8*> [#uses=1] + %1 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 1) ; <i32> [#uses=0] + call void @_ZSt9terminatev() noreturn nounwind + unreachable + +try.handler: ; preds = %entry + %exc1 = call i8* @llvm.eh.exception() ; <i8*> [#uses=3] + %selector = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc1, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTIi to i8*), i8* null) ; <i32> [#uses=1] + %2 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) ; <i32> [#uses=1] + %3 = icmp eq i32 %selector, %2 ; <i1> [#uses=1] + br i1 %3, label %match, label %catch.next + +match: ; preds = %try.handler + %4 = call i8* @__cxa_begin_catch(i8* %exc1) ; <i8*> [#uses=1] + %5 = bitcast i8* %4 to i32* ; <i32*> [#uses=1] + %6 = load i32* %5 ; <i32> [#uses=1] + store i32 %6, i32* %0 + %call = invoke i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), %struct.S* %s2) + to label %invoke.cont2 unwind label %match.handler ; <i32> [#uses=0] + +invoke.cont2: ; preds = %match + store i32 1, i32* %cleanup.dst + br label %match.end + +match.handler: ; preds = %match + %exc3 = call i8* @llvm.eh.exception() ; <i8*> [#uses=2] + %7 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc3, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 0) ; <i32> [#uses=0] + store i8* %exc3, i8** %_rethrow + store i32 2, i32* %cleanup.dst + br label %match.end + +cleanup.pad: ; preds = %cleanup.switch + store i32 1, i32* %cleanup.dst7 + br label %finally + +cleanup.pad4: ; preds = %cleanup.switch + store i32 2, i32* %cleanup.dst7 + br label %finally + +match.end: ; preds = %match.handler, %invoke.cont2 + invoke void @__cxa_end_catch() + to label %invoke.cont5 unwind label %terminate.handler + +invoke.cont5: ; preds = %match.end + br label %cleanup.switch + +cleanup.switch: ; preds = %invoke.cont5 + %tmp = load i32* %cleanup.dst ; <i32> [#uses=1] + switch i32 %tmp, label %cleanup.end [ + i32 1, label %cleanup.pad + i32 2, label %cleanup.pad4 + ] + +cleanup.end: ; preds = %cleanup.switch + %exc6 = call i8* @llvm.eh.exception() ; <i8*> [#uses=1] + store i8* %exc6, i8** %_rethrow + store i32 2, i32* %cleanup.dst7 + br label %finally + +catch.next: ; preds = %try.handler + store i8* %exc1, i8** %_rethrow + store i32 2, i32* %cleanup.dst7 + br label %finally + +finally: ; preds = %catch.next, %cleanup.end, %cleanup.pad4, %cleanup.pad, %invoke.cont + br label %cleanup.switch9 + +cleanup.switch9: ; preds = %finally + %tmp8 = load i32* %cleanup.dst7 ; <i32> [#uses=1] + switch i32 %tmp8, label %cleanup.end10 [ + i32 1, label %finally.end + i32 2, label %finally.throw + ] + +cleanup.end10: ; preds = %cleanup.switch9 + br label %finally.end + +finally.throw: ; preds = %cleanup.switch9 + %8 = load i8** %_rethrow ; <i8*> [#uses=1] + call void @_Unwind_Resume_or_Rethrow(i8* %8) + unreachable + +finally.end: ; preds = %cleanup.end10, %cleanup.switch9 + %tmp11 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; <[2 x i8*]*> [#uses=1] + %arraydecay = getelementptr inbounds [2 x i8*]* %tmp11, i32 0, i32 0 ; <i8**> [#uses=1] + %arrayidx = getelementptr inbounds i8** %arraydecay, i32 1 ; <i8**> [#uses=1] + %tmp12 = load i8** %arrayidx ; <i8*> [#uses=1] + store i8* %tmp12, i8** %retval + %9 = load i8** %retval ; <i8*> [#uses=1] + ret i8* %9 +} + +declare void @_Z6throwsv() ssp + +declare i32 @__gxx_personality_v0(...) + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind + +declare void @_ZSt9terminatev() + +declare void @_Unwind_Resume_or_Rethrow(i8*) + +declare i32 @llvm.eh.typeid.for(i8*) nounwind + +declare i8* @__cxa_begin_catch(i8*) + +declare i32 @printf(i8*, ...) + +declare void @__cxa_end_catch() diff --git a/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll b/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll new file mode 100644 index 000000000000..323925c7ff68 --- /dev/null +++ b/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s | FileCheck %s +; PR6941 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @snd_xbytes(i32 %v, i32 %from, i32 %to) nounwind readnone ssp { +entry: + %cmp19 = icmp eq i32 %to, 0 ; <i1> [#uses=1] + br i1 %cmp19, label %while.end, label %while.cond + +while.cond: ; preds = %entry, %while.cond + %y.021 = phi i32 [ %rem, %while.cond ], [ %to, %entry ] ; <i32> [#uses=3] + %x.020 = phi i32 [ %y.021, %while.cond ], [ %from, %entry ] ; <i32> [#uses=1] + %rem = urem i32 %x.020, %y.021 ; <i32> [#uses=2] + %cmp = icmp eq i32 %rem, 0 ; <i1> [#uses=1] + br i1 %cmp, label %while.end, label %while.cond + +while.end: ; preds = %while.cond, %entry + %x.0.lcssa = phi i32 [ %from, %entry ], [ %y.021, %while.cond ] ; <i32> [#uses=2] + %div = udiv i32 %from, %x.0.lcssa ; <i32> [#uses=1] + %div11 = udiv i32 %to, %x.0.lcssa ; <i32> [#uses=1] + %conv = zext i32 %v to i64 ; <i64> [#uses=1] + %conv14 = zext i32 %div11 to i64 ; <i64> [#uses=1] +; Verify that we don't clobber %eax after putting the imulq result in %rax +; CHECK: imulq %r{{.}}x, %r[[RES:.]]x +; CHECK-NOT: movl {{.*}}, %e[[RES]]x +; CHECK: div + %mul = mul i64 %conv14, %conv ; <i64> [#uses=1] + %conv16 = zext i32 %div to i64 ; <i64> [#uses=1] + %div17 = udiv i64 %mul, %conv16 ; <i64> [#uses=1] + %conv18 = trunc i64 %div17 to i32 ; <i32> [#uses=1] + ret i32 %conv18 +} diff --git a/test/CodeGen/X86/MachineSink-CritEdge.ll b/test/CodeGen/X86/MachineSink-CritEdge.ll new file mode 100644 index 000000000000..74a1049772a0 --- /dev/null +++ b/test/CodeGen/X86/MachineSink-CritEdge.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @f(i32 %x) nounwind ssp { +entry: + %shl.i = shl i32 %x, 12 + %neg.i = xor i32 %shl.i, -1 + %add.i = add nsw i32 %neg.i, %x + %shr.i = ashr i32 %add.i, 22 + %xor.i = xor i32 %shr.i, %add.i + %shl5.i = shl i32 %xor.i, 13 + %neg6.i = xor i32 %shl5.i, -1 + %add8.i = add nsw i32 %xor.i, %neg6.i + %shr10.i = ashr i32 %add8.i, 8 + %xor12.i = xor i32 %shr10.i, %add8.i + %add16.i = mul i32 %xor12.i, 9 + %shr18.i = ashr i32 %add16.i, 15 + %xor20.i = xor i32 %shr18.i, %add16.i + %shl22.i = shl i32 %xor20.i, 27 + %neg23.i = xor i32 %shl22.i, -1 + %add25.i = add nsw i32 %xor20.i, %neg23.i + %shr27.i = ashr i32 %add25.i, 31 + %rem = srem i32 %x, 7 + %cmp = icmp eq i32 %rem, 3 + br i1 %cmp, label %land.lhs.true, label %do.body.preheader + +land.lhs.true: + %call3 = tail call i32 @g(i32 %x) nounwind + %cmp4 = icmp eq i32 %call3, 10 + br i1 %cmp4, label %do.body.preheader, label %if.then + +; %shl.i should be sinked all the way down to do.body.preheader, but not into the loop. +; CHECK: do.body.preheader +; CHECK-NOT: do.body +; CHECK: shll $12 + +do.body.preheader: + %xor29.i = xor i32 %shr27.i, %add25.i + br label %do.body + +if.then: + %add = add nsw i32 %x, 11 + ret i32 %add + +do.body: + %x.addr.1 = phi i32 [ %add9, %do.body ], [ %x, %do.body.preheader ] + %xor = xor i32 %xor29.i, %x.addr.1 + %add9 = add nsw i32 %xor, %x.addr.1 + %and = and i32 %add9, 13 + %tobool = icmp eq i32 %and, 0 + br i1 %tobool, label %if.end, label %do.body + +if.end: + ret i32 %add9 +} + +declare i32 @g(i32) diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll index 920873813e45..23042b6eff3e 100644 --- a/test/CodeGen/X86/abi-isel.ll +++ b/test/CodeGen/X86/abi-isel.ll @@ -72,12 +72,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo00: -; DARWIN-32-PIC: call L1$pb -; DARWIN-32-PIC-NEXT: L1$pb: +; DARWIN-32-PIC: call L0$pb +; DARWIN-32-PIC-NEXT: L0$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L1$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L0$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L1$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L0$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -144,12 +144,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo00: -; DARWIN-32-PIC: call L2$pb -; DARWIN-32-PIC-NEXT: L2$pb: +; DARWIN-32-PIC: call L1$pb +; DARWIN-32-PIC-NEXT: L1$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L2$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L1$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L2$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L1$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -208,11 +208,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo01: -; DARWIN-32-PIC: call L3$pb -; DARWIN-32-PIC-NEXT: L3$pb: +; DARWIN-32-PIC: call L2$pb +; DARWIN-32-PIC-NEXT: L2$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L3$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L2$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L2$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -268,11 +268,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo01: -; DARWIN-32-PIC: call L4$pb -; DARWIN-32-PIC-NEXT: L4$pb: +; DARWIN-32-PIC: call L3$pb +; DARWIN-32-PIC-NEXT: L3$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L4$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L3$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -342,12 +342,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo02: -; DARWIN-32-PIC: call L5$pb -; DARWIN-32-PIC-NEXT: L5$pb: +; DARWIN-32-PIC: call L4$pb +; DARWIN-32-PIC-NEXT: L4$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L5$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L4$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -424,12 +424,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo02: -; DARWIN-32-PIC: call L6$pb -; DARWIN-32-PIC-NEXT: L6$pb: +; DARWIN-32-PIC: call L5$pb +; DARWIN-32-PIC-NEXT: L5$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L6$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L5$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L6$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -497,11 +497,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo03: -; DARWIN-32-PIC: call L7$pb -; DARWIN-32-PIC-NEXT: L7$pb: +; DARWIN-32-PIC: call L6$pb +; DARWIN-32-PIC-NEXT: L6$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dsrc-L7$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L7$pb(%eax) +; DARWIN-32-PIC-NEXT: movl _dsrc-L6$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L6$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo03: @@ -551,11 +551,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo04: -; DARWIN-32-PIC: call L8$pb -; DARWIN-32-PIC-NEXT: L8$pb: +; DARWIN-32-PIC: call L7$pb +; DARWIN-32-PIC-NEXT: L7$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L8$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L8$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ddst-L7$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L7$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo04: @@ -619,11 +619,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo05: -; DARWIN-32-PIC: call L9$pb -; DARWIN-32-PIC-NEXT: L9$pb: +; DARWIN-32-PIC: call L8$pb +; DARWIN-32-PIC-NEXT: L8$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dsrc-L9$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L9$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dsrc-L8$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L8$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -682,11 +682,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo06: -; DARWIN-32-PIC: call L10$pb -; DARWIN-32-PIC-NEXT: L10$pb: +; DARWIN-32-PIC: call L9$pb +; DARWIN-32-PIC-NEXT: L9$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lsrc-L10$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L10$pb(%eax) +; DARWIN-32-PIC-NEXT: movl _lsrc-L9$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L9$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo06: @@ -735,11 +735,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo07: -; DARWIN-32-PIC: call L11$pb -; DARWIN-32-PIC-NEXT: L11$pb: +; DARWIN-32-PIC: call L10$pb +; DARWIN-32-PIC-NEXT: L10$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L11$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L11$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ldst-L10$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L10$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo07: @@ -801,11 +801,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo08: -; DARWIN-32-PIC: call L12$pb -; DARWIN-32-PIC-NEXT: L12$pb: +; DARWIN-32-PIC: call L11$pb +; DARWIN-32-PIC-NEXT: L11$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lsrc-L12$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L12$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lsrc-L11$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L11$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -868,12 +868,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux00: -; DARWIN-32-PIC: call L13$pb -; DARWIN-32-PIC-NEXT: L13$pb: +; DARWIN-32-PIC: call L12$pb +; DARWIN-32-PIC-NEXT: L12$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L13$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L12$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L13$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L12$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -939,12 +939,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx00: -; DARWIN-32-PIC: call L14$pb -; DARWIN-32-PIC-NEXT: L14$pb: +; DARWIN-32-PIC: call L13$pb +; DARWIN-32-PIC-NEXT: L13$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L14$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L13$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L14$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L13$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1005,12 +1005,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux01: -; DARWIN-32-PIC: call L15$pb -; DARWIN-32-PIC-NEXT: L15$pb: +; DARWIN-32-PIC: call L14$pb +; DARWIN-32-PIC-NEXT: L14$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L15$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L14$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: addl $64, %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L14$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1071,12 +1071,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx01: -; DARWIN-32-PIC: call L16$pb -; DARWIN-32-PIC-NEXT: L16$pb: +; DARWIN-32-PIC: call L15$pb +; DARWIN-32-PIC-NEXT: L15$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L16$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L15$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: addl $64, %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1150,12 +1150,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux02: -; DARWIN-32-PIC: call L17$pb -; DARWIN-32-PIC-NEXT: L17$pb: +; DARWIN-32-PIC: call L16$pb +; DARWIN-32-PIC-NEXT: L16$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L17$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L16$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1233,12 +1233,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx02: -; DARWIN-32-PIC: call L18$pb -; DARWIN-32-PIC-NEXT: L18$pb: +; DARWIN-32-PIC: call L17$pb +; DARWIN-32-PIC-NEXT: L17$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L18$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L17$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L18$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1306,11 +1306,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux03: -; DARWIN-32-PIC: call L19$pb -; DARWIN-32-PIC-NEXT: L19$pb: +; DARWIN-32-PIC: call L18$pb +; DARWIN-32-PIC-NEXT: L18$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L19$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L19$pb)+64(%eax) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L18$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L18$pb)+64(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux03: @@ -1361,11 +1361,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux04: -; DARWIN-32-PIC: call L20$pb -; DARWIN-32-PIC-NEXT: L20$pb: +; DARWIN-32-PIC: call L19$pb +; DARWIN-32-PIC-NEXT: L19$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L20$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L20$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L19$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L19$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux04: @@ -1430,11 +1430,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux05: -; DARWIN-32-PIC: call L21$pb -; DARWIN-32-PIC-NEXT: L21$pb: +; DARWIN-32-PIC: call L20$pb +; DARWIN-32-PIC-NEXT: L20$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L21$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L21$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L20$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L20$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1493,11 +1493,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux06: -; DARWIN-32-PIC: call L22$pb -; DARWIN-32-PIC-NEXT: L22$pb: +; DARWIN-32-PIC: call L21$pb +; DARWIN-32-PIC-NEXT: L21$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L22$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L22$pb)+64(%eax) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L21$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L21$pb)+64(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux06: @@ -1546,11 +1546,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux07: -; DARWIN-32-PIC: call L23$pb -; DARWIN-32-PIC-NEXT: L23$pb: +; DARWIN-32-PIC: call L22$pb +; DARWIN-32-PIC-NEXT: L22$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L23$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L23$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L22$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L22$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux07: @@ -1613,11 +1613,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux08: -; DARWIN-32-PIC: call L24$pb -; DARWIN-32-PIC-NEXT: L24$pb: +; DARWIN-32-PIC: call L23$pb +; DARWIN-32-PIC-NEXT: L23$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L24$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L24$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L23$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L23$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1686,13 +1686,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind00: -; DARWIN-32-PIC: call L25$pb -; DARWIN-32-PIC-NEXT: L25$pb: +; DARWIN-32-PIC: call L24$pb +; DARWIN-32-PIC-NEXT: L24$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L25$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L24$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L25$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L24$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -1764,13 +1764,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd00: -; DARWIN-32-PIC: call L26$pb -; DARWIN-32-PIC-NEXT: L26$pb: +; DARWIN-32-PIC: call L25$pb +; DARWIN-32-PIC-NEXT: L25$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L26$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L25$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L26$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L25$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -1840,13 +1840,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind01: -; DARWIN-32-PIC: call L27$pb -; DARWIN-32-PIC-NEXT: L27$pb: +; DARWIN-32-PIC: call L26$pb +; DARWIN-32-PIC-NEXT: L26$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: shll $2, %ecx -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L27$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L26$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L26$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1916,13 +1916,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd01: -; DARWIN-32-PIC: call L28$pb -; DARWIN-32-PIC-NEXT: L28$pb: +; DARWIN-32-PIC: call L27$pb +; DARWIN-32-PIC-NEXT: L27$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: shll $2, %ecx -; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L28$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L27$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2001,13 +2001,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind02: -; DARWIN-32-PIC: call L29$pb -; DARWIN-32-PIC-NEXT: L29$pb: +; DARWIN-32-PIC: call L28$pb +; DARWIN-32-PIC-NEXT: L28$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L29$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L28$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2090,13 +2090,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd02: -; DARWIN-32-PIC: call L30$pb -; DARWIN-32-PIC-NEXT: L30$pb: +; DARWIN-32-PIC: call L29$pb +; DARWIN-32-PIC-NEXT: L29$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L30$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L29$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L30$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2170,12 +2170,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind03: -; DARWIN-32-PIC: call L31$pb -; DARWIN-32-PIC-NEXT: L31$pb: +; DARWIN-32-PIC: call L30$pb +; DARWIN-32-PIC-NEXT: L30$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dsrc-L31$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L31$pb(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl _dsrc-L30$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L30$pb(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind03: @@ -2242,12 +2242,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind04: -; DARWIN-32-PIC: call L32$pb -; DARWIN-32-PIC-NEXT: L32$pb: +; DARWIN-32-PIC: call L31$pb +; DARWIN-32-PIC-NEXT: L31$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal _ddst-L32$pb(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L32$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ddst-L31$pb(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L31$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind04: @@ -2320,12 +2320,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind05: -; DARWIN-32-PIC: call L33$pb -; DARWIN-32-PIC-NEXT: L33$pb: +; DARWIN-32-PIC: call L32$pb +; DARWIN-32-PIC-NEXT: L32$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dsrc-L33$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L33$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dsrc-L32$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L32$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2395,12 +2395,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind06: -; DARWIN-32-PIC: call L34$pb -; DARWIN-32-PIC-NEXT: L34$pb: +; DARWIN-32-PIC: call L33$pb +; DARWIN-32-PIC-NEXT: L33$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lsrc-L34$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L34$pb(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl _lsrc-L33$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L33$pb(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind06: @@ -2466,12 +2466,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind07: -; DARWIN-32-PIC: call L35$pb -; DARWIN-32-PIC-NEXT: L35$pb: +; DARWIN-32-PIC: call L34$pb +; DARWIN-32-PIC-NEXT: L34$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal _ldst-L35$pb(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L35$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ldst-L34$pb(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L34$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind07: @@ -2543,12 +2543,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind08: -; DARWIN-32-PIC: call L36$pb -; DARWIN-32-PIC-NEXT: L36$pb: +; DARWIN-32-PIC: call L35$pb +; DARWIN-32-PIC-NEXT: L35$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lsrc-L36$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L36$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lsrc-L35$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L35$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2621,13 +2621,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off00: -; DARWIN-32-PIC: call L37$pb -; DARWIN-32-PIC-NEXT: L37$pb: +; DARWIN-32-PIC: call L36$pb +; DARWIN-32-PIC-NEXT: L36$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L37$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L36$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L37$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L36$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2700,13 +2700,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf00: -; DARWIN-32-PIC: call L38$pb -; DARWIN-32-PIC-NEXT: L38$pb: +; DARWIN-32-PIC: call L37$pb +; DARWIN-32-PIC-NEXT: L37$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L38$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L37$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L38$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L37$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2777,13 +2777,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off01: -; DARWIN-32-PIC: call L39$pb -; DARWIN-32-PIC-NEXT: L39$pb: +; DARWIN-32-PIC: call L38$pb +; DARWIN-32-PIC-NEXT: L38$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L39$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L38$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L38$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2854,13 +2854,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf01: -; DARWIN-32-PIC: call L40$pb -; DARWIN-32-PIC-NEXT: L40$pb: +; DARWIN-32-PIC: call L39$pb +; DARWIN-32-PIC-NEXT: L39$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L40$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L39$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2940,13 +2940,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off02: -; DARWIN-32-PIC: call L41$pb -; DARWIN-32-PIC-NEXT: L41$pb: +; DARWIN-32-PIC: call L40$pb +; DARWIN-32-PIC-NEXT: L40$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L41$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L40$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3030,13 +3030,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf02: -; DARWIN-32-PIC: call L42$pb -; DARWIN-32-PIC-NEXT: L42$pb: +; DARWIN-32-PIC: call L41$pb +; DARWIN-32-PIC-NEXT: L41$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L42$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L41$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L42$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3111,12 +3111,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off03: -; DARWIN-32-PIC: call L43$pb -; DARWIN-32-PIC-NEXT: L43$pb: +; DARWIN-32-PIC: call L42$pb +; DARWIN-32-PIC-NEXT: L42$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L43$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L43$pb)+64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L42$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L42$pb)+64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off03: @@ -3184,12 +3184,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off04: -; DARWIN-32-PIC: call L44$pb -; DARWIN-32-PIC-NEXT: L44$pb: +; DARWIN-32-PIC: call L43$pb +; DARWIN-32-PIC-NEXT: L43$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L44$pb)+64(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L44$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L43$pb)+64(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L43$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off04: @@ -3263,12 +3263,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off05: -; DARWIN-32-PIC: call L45$pb -; DARWIN-32-PIC-NEXT: L45$pb: +; DARWIN-32-PIC: call L44$pb +; DARWIN-32-PIC-NEXT: L44$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L45$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L45$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L44$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L44$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3339,12 +3339,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off06: -; DARWIN-32-PIC: call L46$pb -; DARWIN-32-PIC-NEXT: L46$pb: +; DARWIN-32-PIC: call L45$pb +; DARWIN-32-PIC-NEXT: L45$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L46$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L46$pb)+64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L45$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L45$pb)+64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off06: @@ -3411,12 +3411,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off07: -; DARWIN-32-PIC: call L47$pb -; DARWIN-32-PIC-NEXT: L47$pb: +; DARWIN-32-PIC: call L46$pb +; DARWIN-32-PIC-NEXT: L46$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L47$pb)+64(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L47$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L46$pb)+64(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L46$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off07: @@ -3489,12 +3489,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off08: -; DARWIN-32-PIC: call L48$pb -; DARWIN-32-PIC-NEXT: L48$pb: +; DARWIN-32-PIC: call L47$pb +; DARWIN-32-PIC-NEXT: L47$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L48$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L48$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L47$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L47$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3560,12 +3560,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo00: -; DARWIN-32-PIC: call L49$pb -; DARWIN-32-PIC-NEXT: L49$pb: +; DARWIN-32-PIC: call L48$pb +; DARWIN-32-PIC-NEXT: L48$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L49$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L48$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L49$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L48$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3626,12 +3626,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo01: -; DARWIN-32-PIC: call L50$pb -; DARWIN-32-PIC-NEXT: L50$pb: +; DARWIN-32-PIC: call L49$pb +; DARWIN-32-PIC-NEXT: L49$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl $262144, %ecx -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L50$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L49$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L49$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3705,12 +3705,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo02: -; DARWIN-32-PIC: call L51$pb -; DARWIN-32-PIC-NEXT: L51$pb: +; DARWIN-32-PIC: call L50$pb +; DARWIN-32-PIC-NEXT: L50$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L51$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L50$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L51$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3778,11 +3778,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo03: -; DARWIN-32-PIC: call L52$pb -; DARWIN-32-PIC-NEXT: L52$pb: +; DARWIN-32-PIC: call L51$pb +; DARWIN-32-PIC-NEXT: L51$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L52$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L52$pb)+262144(%eax) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L51$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L51$pb)+262144(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo03: @@ -3833,11 +3833,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo04: -; DARWIN-32-PIC: call L53$pb -; DARWIN-32-PIC-NEXT: L53$pb: +; DARWIN-32-PIC: call L52$pb +; DARWIN-32-PIC-NEXT: L52$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L53$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L53$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L52$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L52$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo04: @@ -3902,11 +3902,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo05: -; DARWIN-32-PIC: call L54$pb -; DARWIN-32-PIC-NEXT: L54$pb: +; DARWIN-32-PIC: call L53$pb +; DARWIN-32-PIC-NEXT: L53$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L54$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L54$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L53$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L53$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3965,11 +3965,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo06: -; DARWIN-32-PIC: call L55$pb -; DARWIN-32-PIC-NEXT: L55$pb: +; DARWIN-32-PIC: call L54$pb +; DARWIN-32-PIC-NEXT: L54$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L55$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L55$pb)+262144(%eax) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L54$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L54$pb)+262144(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo06: @@ -4018,11 +4018,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo07: -; DARWIN-32-PIC: call L56$pb -; DARWIN-32-PIC-NEXT: L56$pb: +; DARWIN-32-PIC: call L55$pb +; DARWIN-32-PIC-NEXT: L55$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L56$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L56$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L55$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L55$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo07: @@ -4085,11 +4085,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo08: -; DARWIN-32-PIC: call L57$pb -; DARWIN-32-PIC-NEXT: L57$pb: +; DARWIN-32-PIC: call L56$pb +; DARWIN-32-PIC-NEXT: L56$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L57$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L57$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L56$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L56$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -4159,13 +4159,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big00: -; DARWIN-32-PIC: call L58$pb -; DARWIN-32-PIC-NEXT: L58$pb: +; DARWIN-32-PIC: call L57$pb +; DARWIN-32-PIC-NEXT: L57$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L58$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L57$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L57$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4236,13 +4236,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big01: -; DARWIN-32-PIC: call L59$pb -; DARWIN-32-PIC-NEXT: L59$pb: +; DARWIN-32-PIC: call L58$pb +; DARWIN-32-PIC-NEXT: L58$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L59$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 262144(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L58$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -4322,13 +4322,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big02: -; DARWIN-32-PIC: call L60$pb -; DARWIN-32-PIC-NEXT: L60$pb: +; DARWIN-32-PIC: call L59$pb +; DARWIN-32-PIC-NEXT: L59$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L60$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L59$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L60$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4403,12 +4403,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big03: -; DARWIN-32-PIC: call L61$pb -; DARWIN-32-PIC-NEXT: L61$pb: +; DARWIN-32-PIC: call L60$pb +; DARWIN-32-PIC-NEXT: L60$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L61$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L61$pb)+262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L60$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L60$pb)+262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big03: @@ -4476,12 +4476,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big04: -; DARWIN-32-PIC: call L62$pb -; DARWIN-32-PIC-NEXT: L62$pb: +; DARWIN-32-PIC: call L61$pb +; DARWIN-32-PIC-NEXT: L61$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L62$pb)+262144(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L62$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L61$pb)+262144(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L61$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big04: @@ -4555,12 +4555,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big05: -; DARWIN-32-PIC: call L63$pb -; DARWIN-32-PIC-NEXT: L63$pb: +; DARWIN-32-PIC: call L62$pb +; DARWIN-32-PIC-NEXT: L62$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L63$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L63$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L62$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L62$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4631,12 +4631,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big06: -; DARWIN-32-PIC: call L64$pb -; DARWIN-32-PIC-NEXT: L64$pb: +; DARWIN-32-PIC: call L63$pb +; DARWIN-32-PIC-NEXT: L63$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L64$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L64$pb)+262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L63$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L63$pb)+262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big06: @@ -4703,12 +4703,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big07: -; DARWIN-32-PIC: call L65$pb -; DARWIN-32-PIC-NEXT: L65$pb: +; DARWIN-32-PIC: call L64$pb +; DARWIN-32-PIC-NEXT: L64$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L65$pb)+262144(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L65$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L64$pb)+262144(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L64$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big07: @@ -4781,12 +4781,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big08: -; DARWIN-32-PIC: call L66$pb -; DARWIN-32-PIC-NEXT: L66$pb: +; DARWIN-32-PIC: call L65$pb +; DARWIN-32-PIC-NEXT: L65$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L66$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L66$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L65$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L65$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4840,10 +4840,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar00: -; DARWIN-32-PIC: call L67$pb -; DARWIN-32-PIC-NEXT: L67$pb: +; DARWIN-32-PIC: call L66$pb +; DARWIN-32-PIC-NEXT: L66$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L67$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L66$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar00: @@ -4887,10 +4887,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxr00: -; DARWIN-32-PIC: call L68$pb -; DARWIN-32-PIC-NEXT: L68$pb: +; DARWIN-32-PIC: call L67$pb +; DARWIN-32-PIC-NEXT: L67$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L68$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L67$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxr00: @@ -4934,10 +4934,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar01: -; DARWIN-32-PIC: call L69$pb -; DARWIN-32-PIC-NEXT: L69$pb: +; DARWIN-32-PIC: call L68$pb +; DARWIN-32-PIC-NEXT: L68$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L69$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L68$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar01: @@ -4981,10 +4981,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxr01: -; DARWIN-32-PIC: call L70$pb -; DARWIN-32-PIC-NEXT: L70$pb: +; DARWIN-32-PIC: call L69$pb +; DARWIN-32-PIC-NEXT: L69$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L70$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L69$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxr01: @@ -5028,10 +5028,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar02: -; DARWIN-32-PIC: call L71$pb -; DARWIN-32-PIC-NEXT: L71$pb: +; DARWIN-32-PIC: call L70$pb +; DARWIN-32-PIC-NEXT: L70$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L71$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L70$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar02: @@ -5075,10 +5075,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar03: -; DARWIN-32-PIC: call L72$pb -; DARWIN-32-PIC-NEXT: L72$pb: +; DARWIN-32-PIC: call L71$pb +; DARWIN-32-PIC-NEXT: L71$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dsrc-L72$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dsrc-L71$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar03: @@ -5122,10 +5122,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar04: -; DARWIN-32-PIC: call L73$pb -; DARWIN-32-PIC-NEXT: L73$pb: +; DARWIN-32-PIC: call L72$pb +; DARWIN-32-PIC-NEXT: L72$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L73$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ddst-L72$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar04: @@ -5169,10 +5169,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar05: -; DARWIN-32-PIC: call L74$pb -; DARWIN-32-PIC-NEXT: L74$pb: +; DARWIN-32-PIC: call L73$pb +; DARWIN-32-PIC-NEXT: L73$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dptr-L74$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dptr-L73$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar05: @@ -5216,10 +5216,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar06: -; DARWIN-32-PIC: call L75$pb -; DARWIN-32-PIC-NEXT: L75$pb: +; DARWIN-32-PIC: call L74$pb +; DARWIN-32-PIC-NEXT: L74$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lsrc-L75$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lsrc-L74$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar06: @@ -5263,10 +5263,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar07: -; DARWIN-32-PIC: call L76$pb -; DARWIN-32-PIC-NEXT: L76$pb: +; DARWIN-32-PIC: call L75$pb +; DARWIN-32-PIC-NEXT: L75$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L76$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ldst-L75$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar07: @@ -5310,10 +5310,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar08: -; DARWIN-32-PIC: call L77$pb -; DARWIN-32-PIC-NEXT: L77$pb: +; DARWIN-32-PIC: call L76$pb +; DARWIN-32-PIC-NEXT: L76$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lptr-L77$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lptr-L76$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar08: @@ -5357,10 +5357,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har00: -; DARWIN-32-PIC: call L78$pb -; DARWIN-32-PIC-NEXT: L78$pb: +; DARWIN-32-PIC: call L77$pb +; DARWIN-32-PIC-NEXT: L77$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L78$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L77$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har00: @@ -5404,10 +5404,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _hxr00: -; DARWIN-32-PIC: call L79$pb -; DARWIN-32-PIC-NEXT: L79$pb: +; DARWIN-32-PIC: call L78$pb +; DARWIN-32-PIC-NEXT: L78$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L79$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L78$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _hxr00: @@ -5451,10 +5451,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har01: -; DARWIN-32-PIC: call L80$pb -; DARWIN-32-PIC-NEXT: L80$pb: +; DARWIN-32-PIC: call L79$pb +; DARWIN-32-PIC-NEXT: L79$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L80$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L79$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har01: @@ -5498,10 +5498,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _hxr01: -; DARWIN-32-PIC: call L81$pb -; DARWIN-32-PIC-NEXT: L81$pb: +; DARWIN-32-PIC: call L80$pb +; DARWIN-32-PIC-NEXT: L80$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L81$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L80$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _hxr01: @@ -5549,10 +5549,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har02: -; DARWIN-32-PIC: call L82$pb -; DARWIN-32-PIC-NEXT: L82$pb: +; DARWIN-32-PIC: call L81$pb +; DARWIN-32-PIC-NEXT: L81$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L82$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L81$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: ret @@ -5600,10 +5600,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har03: -; DARWIN-32-PIC: call L83$pb -; DARWIN-32-PIC-NEXT: L83$pb: +; DARWIN-32-PIC: call L82$pb +; DARWIN-32-PIC-NEXT: L82$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dsrc-L83$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dsrc-L82$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har03: @@ -5647,10 +5647,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har04: -; DARWIN-32-PIC: call L84$pb -; DARWIN-32-PIC-NEXT: L84$pb: +; DARWIN-32-PIC: call L83$pb +; DARWIN-32-PIC-NEXT: L83$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L84$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ddst-L83$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har04: @@ -5697,10 +5697,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har05: -; DARWIN-32-PIC: call L85$pb -; DARWIN-32-PIC-NEXT: L85$pb: +; DARWIN-32-PIC: call L84$pb +; DARWIN-32-PIC-NEXT: L84$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dptr-L85$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L84$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har05: @@ -5744,10 +5744,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har06: -; DARWIN-32-PIC: call L86$pb -; DARWIN-32-PIC-NEXT: L86$pb: +; DARWIN-32-PIC: call L85$pb +; DARWIN-32-PIC-NEXT: L85$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lsrc-L86$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lsrc-L85$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har06: @@ -5791,10 +5791,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har07: -; DARWIN-32-PIC: call L87$pb -; DARWIN-32-PIC-NEXT: L87$pb: +; DARWIN-32-PIC: call L86$pb +; DARWIN-32-PIC-NEXT: L86$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L87$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ldst-L86$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har07: @@ -5840,10 +5840,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har08: -; DARWIN-32-PIC: call L88$pb -; DARWIN-32-PIC-NEXT: L88$pb: +; DARWIN-32-PIC: call L87$pb +; DARWIN-32-PIC-NEXT: L87$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lptr-L88$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L87$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har08: @@ -5889,10 +5889,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat00: -; DARWIN-32-PIC: call L89$pb -; DARWIN-32-PIC-NEXT: L89$pb: +; DARWIN-32-PIC: call L88$pb +; DARWIN-32-PIC-NEXT: L88$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L89$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L88$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -5942,10 +5942,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxt00: -; DARWIN-32-PIC: call L90$pb -; DARWIN-32-PIC-NEXT: L90$pb: +; DARWIN-32-PIC: call L89$pb +; DARWIN-32-PIC-NEXT: L89$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L90$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L89$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -5995,10 +5995,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat01: -; DARWIN-32-PIC: call L91$pb -; DARWIN-32-PIC-NEXT: L91$pb: +; DARWIN-32-PIC: call L90$pb +; DARWIN-32-PIC-NEXT: L90$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L91$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L90$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6048,10 +6048,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxt01: -; DARWIN-32-PIC: call L92$pb -; DARWIN-32-PIC-NEXT: L92$pb: +; DARWIN-32-PIC: call L91$pb +; DARWIN-32-PIC-NEXT: L91$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L92$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L91$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6110,10 +6110,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat02: -; DARWIN-32-PIC: call L93$pb -; DARWIN-32-PIC-NEXT: L93$pb: +; DARWIN-32-PIC: call L92$pb +; DARWIN-32-PIC-NEXT: L92$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L93$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L92$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6166,10 +6166,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat03: -; DARWIN-32-PIC: call L94$pb -; DARWIN-32-PIC-NEXT: L94$pb: +; DARWIN-32-PIC: call L93$pb +; DARWIN-32-PIC-NEXT: L93$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_dsrc-L94$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L93$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat03: @@ -6214,10 +6214,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat04: -; DARWIN-32-PIC: call L95$pb -; DARWIN-32-PIC-NEXT: L95$pb: +; DARWIN-32-PIC: call L94$pb +; DARWIN-32-PIC-NEXT: L94$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L95$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L94$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat04: @@ -6271,10 +6271,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat05: -; DARWIN-32-PIC: call L96$pb -; DARWIN-32-PIC-NEXT: L96$pb: +; DARWIN-32-PIC: call L95$pb +; DARWIN-32-PIC-NEXT: L95$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dptr-L96$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L95$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6322,10 +6322,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat06: -; DARWIN-32-PIC: call L97$pb -; DARWIN-32-PIC-NEXT: L97$pb: +; DARWIN-32-PIC: call L96$pb +; DARWIN-32-PIC-NEXT: L96$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_lsrc-L97$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L96$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat06: @@ -6369,10 +6369,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat07: -; DARWIN-32-PIC: call L98$pb -; DARWIN-32-PIC-NEXT: L98$pb: +; DARWIN-32-PIC: call L97$pb +; DARWIN-32-PIC-NEXT: L97$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L98$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L97$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat07: @@ -6425,10 +6425,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat08: -; DARWIN-32-PIC: call L99$pb -; DARWIN-32-PIC-NEXT: L99$pb: +; DARWIN-32-PIC: call L98$pb +; DARWIN-32-PIC-NEXT: L98$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lptr-L99$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L98$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6478,11 +6478,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam00: -; DARWIN-32-PIC: call L100$pb -; DARWIN-32-PIC-NEXT: L100$pb: +; DARWIN-32-PIC: call L99$pb +; DARWIN-32-PIC-NEXT: L99$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L100$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L99$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam00: @@ -6531,11 +6531,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam01: -; DARWIN-32-PIC: call L101$pb -; DARWIN-32-PIC-NEXT: L101$pb: +; DARWIN-32-PIC: call L100$pb +; DARWIN-32-PIC-NEXT: L100$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L101$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L100$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam01: @@ -6584,11 +6584,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxm01: -; DARWIN-32-PIC: call L102$pb -; DARWIN-32-PIC-NEXT: L102$pb: +; DARWIN-32-PIC: call L101$pb +; DARWIN-32-PIC-NEXT: L101$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L102$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L101$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxm01: @@ -6646,10 +6646,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam02: -; DARWIN-32-PIC: call L103$pb -; DARWIN-32-PIC-NEXT: L103$pb: +; DARWIN-32-PIC: call L102$pb +; DARWIN-32-PIC-NEXT: L102$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L103$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L102$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax ; DARWIN-32-PIC-NEXT: addl (%ecx), %eax ; DARWIN-32-PIC-NEXT: ret @@ -6702,10 +6702,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam03: -; DARWIN-32-PIC: call L104$pb -; DARWIN-32-PIC-NEXT: L104$pb: +; DARWIN-32-PIC: call L103$pb +; DARWIN-32-PIC-NEXT: L103$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_dsrc-L104$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L103$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam03: @@ -6750,10 +6750,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam04: -; DARWIN-32-PIC: call L105$pb -; DARWIN-32-PIC-NEXT: L105$pb: +; DARWIN-32-PIC: call L104$pb +; DARWIN-32-PIC-NEXT: L104$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L105$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L104$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam04: @@ -6807,11 +6807,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam05: -; DARWIN-32-PIC: call L106$pb -; DARWIN-32-PIC-NEXT: L106$pb: +; DARWIN-32-PIC: call L105$pb +; DARWIN-32-PIC-NEXT: L105$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl _dptr-L106$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl _dptr-L105$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam05: @@ -6858,10 +6858,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam06: -; DARWIN-32-PIC: call L107$pb -; DARWIN-32-PIC-NEXT: L107$pb: +; DARWIN-32-PIC: call L106$pb +; DARWIN-32-PIC-NEXT: L106$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_lsrc-L107$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L106$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam06: @@ -6905,10 +6905,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam07: -; DARWIN-32-PIC: call L108$pb -; DARWIN-32-PIC-NEXT: L108$pb: +; DARWIN-32-PIC: call L107$pb +; DARWIN-32-PIC-NEXT: L107$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L108$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L107$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam07: @@ -6961,11 +6961,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam08: -; DARWIN-32-PIC: call L109$pb -; DARWIN-32-PIC-NEXT: L109$pb: +; DARWIN-32-PIC: call L108$pb +; DARWIN-32-PIC-NEXT: L108$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl _lptr-L109$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl _lptr-L108$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam08: @@ -7021,11 +7021,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat00: -; DARWIN-32-PIC: call L110$pb -; DARWIN-32-PIC-NEXT: L110$pb: +; DARWIN-32-PIC: call L109$pb +; DARWIN-32-PIC-NEXT: L109$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L110$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L109$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7082,11 +7082,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxt00: -; DARWIN-32-PIC: call L111$pb -; DARWIN-32-PIC-NEXT: L111$pb: +; DARWIN-32-PIC: call L110$pb +; DARWIN-32-PIC-NEXT: L110$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L111$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L110$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7143,11 +7143,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat01: -; DARWIN-32-PIC: call L112$pb -; DARWIN-32-PIC-NEXT: L112$pb: +; DARWIN-32-PIC: call L111$pb +; DARWIN-32-PIC-NEXT: L111$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L112$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L111$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7204,11 +7204,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxt01: -; DARWIN-32-PIC: call L113$pb -; DARWIN-32-PIC-NEXT: L113$pb: +; DARWIN-32-PIC: call L112$pb +; DARWIN-32-PIC-NEXT: L112$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L113$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L112$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7272,10 +7272,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat02: -; DARWIN-32-PIC: call L114$pb -; DARWIN-32-PIC-NEXT: L114$pb: +; DARWIN-32-PIC: call L113$pb +; DARWIN-32-PIC-NEXT: L113$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L114$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L113$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax @@ -7336,11 +7336,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat03: -; DARWIN-32-PIC: call L115$pb -; DARWIN-32-PIC-NEXT: L115$pb: +; DARWIN-32-PIC: call L114$pb +; DARWIN-32-PIC-NEXT: L114$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_dsrc-L115$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L114$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat03: @@ -7395,11 +7395,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat04: -; DARWIN-32-PIC: call L116$pb -; DARWIN-32-PIC-NEXT: L116$pb: +; DARWIN-32-PIC: call L115$pb +; DARWIN-32-PIC-NEXT: L115$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L116$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L115$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat04: @@ -7461,11 +7461,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat05: -; DARWIN-32-PIC: call L117$pb -; DARWIN-32-PIC-NEXT: L117$pb: +; DARWIN-32-PIC: call L116$pb +; DARWIN-32-PIC-NEXT: L116$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L117$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L116$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7521,11 +7521,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat06: -; DARWIN-32-PIC: call L118$pb -; DARWIN-32-PIC-NEXT: L118$pb: +; DARWIN-32-PIC: call L117$pb +; DARWIN-32-PIC-NEXT: L117$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_lsrc-L118$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L117$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat06: @@ -7580,11 +7580,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat07: -; DARWIN-32-PIC: call L119$pb -; DARWIN-32-PIC-NEXT: L119$pb: +; DARWIN-32-PIC: call L118$pb +; DARWIN-32-PIC-NEXT: L118$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L119$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L118$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat07: @@ -7645,11 +7645,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat08: -; DARWIN-32-PIC: call L120$pb -; DARWIN-32-PIC-NEXT: L120$pb: +; DARWIN-32-PIC: call L119$pb +; DARWIN-32-PIC-NEXT: L119$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L120$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L119$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7706,11 +7706,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam00: -; DARWIN-32-PIC: call L121$pb -; DARWIN-32-PIC-NEXT: L121$pb: +; DARWIN-32-PIC: call L120$pb +; DARWIN-32-PIC-NEXT: L120$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L121$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L120$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7767,11 +7767,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxm00: -; DARWIN-32-PIC: call L122$pb -; DARWIN-32-PIC-NEXT: L122$pb: +; DARWIN-32-PIC: call L121$pb +; DARWIN-32-PIC-NEXT: L121$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L122$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L121$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7828,11 +7828,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam01: -; DARWIN-32-PIC: call L123$pb -; DARWIN-32-PIC-NEXT: L123$pb: +; DARWIN-32-PIC: call L122$pb +; DARWIN-32-PIC-NEXT: L122$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L123$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L122$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7889,11 +7889,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxm01: -; DARWIN-32-PIC: call L124$pb -; DARWIN-32-PIC-NEXT: L124$pb: +; DARWIN-32-PIC: call L123$pb +; DARWIN-32-PIC-NEXT: L123$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L124$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L123$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7957,10 +7957,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam02: -; DARWIN-32-PIC: call L125$pb -; DARWIN-32-PIC-NEXT: L125$pb: +; DARWIN-32-PIC: call L124$pb +; DARWIN-32-PIC-NEXT: L124$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L125$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L124$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax @@ -8021,11 +8021,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam03: -; DARWIN-32-PIC: call L126$pb -; DARWIN-32-PIC-NEXT: L126$pb: +; DARWIN-32-PIC: call L125$pb +; DARWIN-32-PIC-NEXT: L125$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_dsrc-L126$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L125$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam03: @@ -8080,11 +8080,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam04: -; DARWIN-32-PIC: call L127$pb -; DARWIN-32-PIC-NEXT: L127$pb: +; DARWIN-32-PIC: call L126$pb +; DARWIN-32-PIC-NEXT: L126$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L127$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L126$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam04: @@ -8146,11 +8146,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam05: -; DARWIN-32-PIC: call L128$pb -; DARWIN-32-PIC-NEXT: L128$pb: +; DARWIN-32-PIC: call L127$pb +; DARWIN-32-PIC-NEXT: L127$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L128$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L127$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -8206,11 +8206,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam06: -; DARWIN-32-PIC: call L129$pb -; DARWIN-32-PIC-NEXT: L129$pb: +; DARWIN-32-PIC: call L128$pb +; DARWIN-32-PIC-NEXT: L128$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_lsrc-L129$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L128$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam06: @@ -8265,11 +8265,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam07: -; DARWIN-32-PIC: call L130$pb -; DARWIN-32-PIC-NEXT: L130$pb: +; DARWIN-32-PIC: call L129$pb +; DARWIN-32-PIC-NEXT: L129$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L130$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L129$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam07: @@ -8330,11 +8330,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam08: -; DARWIN-32-PIC: call L131$pb -; DARWIN-32-PIC-NEXT: L131$pb: +; DARWIN-32-PIC: call L130$pb +; DARWIN-32-PIC-NEXT: L130$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L131$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L130$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -8644,10 +8644,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _address: -; DARWIN-32-PIC: call L134$pb -; DARWIN-32-PIC-NEXT: L134$pb: +; DARWIN-32-PIC: call L133$pb +; DARWIN-32-PIC-NEXT: L133$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L134$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L133$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _address: @@ -8693,10 +8693,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _laddress: -; DARWIN-32-PIC: call L135$pb -; DARWIN-32-PIC-NEXT: L135$pb: +; DARWIN-32-PIC: call L134$pb +; DARWIN-32-PIC-NEXT: L134$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lcallee-L135$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lcallee-L134$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _laddress: @@ -8740,10 +8740,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _daddress: -; DARWIN-32-PIC: call L136$pb -; DARWIN-32-PIC-NEXT: L136$pb: +; DARWIN-32-PIC: call L135$pb +; DARWIN-32-PIC-NEXT: L135$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dcallee-L136$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dcallee-L135$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _daddress: @@ -9224,10 +9224,10 @@ entry: ; DARWIN-32-PIC: _icaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L143$pb -; DARWIN-32-PIC-NEXT: L143$pb: +; DARWIN-32-PIC-NEXT: call L142$pb +; DARWIN-32-PIC-NEXT: L142$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L143$pb(%eax), %esi +; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L142$pb(%eax), %esi ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp @@ -9310,11 +9310,11 @@ entry: ; DARWIN-32-PIC: _dicaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L144$pb -; DARWIN-32-PIC-NEXT: L144$pb: +; DARWIN-32-PIC-NEXT: call L143$pb +; DARWIN-32-PIC-NEXT: L143$pb: ; DARWIN-32-PIC-NEXT: popl %esi -; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi) -; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_difunc-L143$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_difunc-L143$pb(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp ; DARWIN-32-PIC-NEXT: popl %esi ; DARWIN-32-PIC-NEXT: ret @@ -9391,11 +9391,11 @@ entry: ; DARWIN-32-PIC: _licaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L145$pb -; DARWIN-32-PIC-NEXT: L145$pb: +; DARWIN-32-PIC-NEXT: call L144$pb +; DARWIN-32-PIC-NEXT: L144$pb: ; DARWIN-32-PIC-NEXT: popl %esi -; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi) -; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_lifunc-L144$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_lifunc-L144$pb(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp ; DARWIN-32-PIC-NEXT: popl %esi ; DARWIN-32-PIC-NEXT: ret @@ -9476,10 +9476,10 @@ entry: ; DARWIN-32-PIC: _itailcaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L146$pb -; DARWIN-32-PIC-NEXT: L146$pb: +; DARWIN-32-PIC-NEXT: call L145$pb +; DARWIN-32-PIC-NEXT: L145$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L146$pb(%eax), %esi +; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L145$pb(%eax), %esi ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp @@ -9553,10 +9553,10 @@ entry: ; DARWIN-32-PIC: _ditailcaller: ; DARWIN-32-PIC: subl $12, %esp -; DARWIN-32-PIC-NEXT: call L147$pb -; DARWIN-32-PIC-NEXT: L147$pb: +; DARWIN-32-PIC-NEXT: call L146$pb +; DARWIN-32-PIC-NEXT: L146$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: call *_difunc-L147$pb(%eax) +; DARWIN-32-PIC-NEXT: call *_difunc-L146$pb(%eax) ; DARWIN-32-PIC-NEXT: addl $12, %esp ; DARWIN-32-PIC-NEXT: ret @@ -9619,10 +9619,10 @@ entry: ; DARWIN-32-PIC: _litailcaller: ; DARWIN-32-PIC: subl $12, %esp -; DARWIN-32-PIC-NEXT: call L148$pb -; DARWIN-32-PIC-NEXT: L148$pb: +; DARWIN-32-PIC-NEXT: call L147$pb +; DARWIN-32-PIC-NEXT: L147$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: call *_lifunc-L148$pb(%eax) +; DARWIN-32-PIC-NEXT: call *_lifunc-L147$pb(%eax) ; DARWIN-32-PIC-NEXT: addl $12, %esp ; DARWIN-32-PIC-NEXT: ret diff --git a/test/CodeGen/X86/alignment.ll b/test/CodeGen/X86/alignment.ll new file mode 100644 index 000000000000..9678e6df740e --- /dev/null +++ b/test/CodeGen/X86/alignment.ll @@ -0,0 +1,43 @@ +; RUN: llc %s -o - -mtriple=x86_64-linux-gnu | FileCheck %s + +; This cannot get rounded up to the preferred alignment (16) if they have an +; explicit alignment specified. +@GlobalA = global { [384 x i8] } zeroinitializer, align 8 + +; CHECK: .bss +; CHECK: .globl GlobalA +; CHECK: .align 16 +; CHECK: GlobalA: +; CHECK: .zero 384 + +; Common variables should not get rounded up to the preferred alignment (16) if +; they have an explicit alignment specified. +; PR6921 +@GlobalB = common global { [384 x i8] } zeroinitializer, align 8 + +; CHECK: .comm GlobalB,384,16 + + +@GlobalC = common global { [384 x i8] } zeroinitializer, align 2 + +; CHECK: .comm GlobalC,384,16 + + + +; This cannot get rounded up to the preferred alignment (16) if they have an +; explicit alignment specified *and* a section specified. +@GlobalAS = global { [384 x i8] } zeroinitializer, align 8, section "foo" + +; CHECK: .globl GlobalAS +; CHECK: .align 8 +; CHECK: GlobalAS: +; CHECK: .zero 384 + +; Common variables should not get rounded up to the preferred alignment (16) if +; they have an explicit alignment specified and a section specified. +; PR6921 +@GlobalBS = common global { [384 x i8] } zeroinitializer, align 8, section "foo" +; CHECK: .comm GlobalBS,384,8 + +@GlobalCS = common global { [384 x i8] } zeroinitializer, align 2, section "foo" +; CHECK: .comm GlobalCS,384,2
\ No newline at end of file diff --git a/test/CodeGen/X86/atomic_add.ll b/test/CodeGen/X86/atomic_add.ll index d00f8e861c21..26d25e24dfbc 100644 --- a/test/CodeGen/X86/atomic_add.ll +++ b/test/CodeGen/X86/atomic_add.ll @@ -192,7 +192,7 @@ entry: define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp { entry: ; CHECK: sub2: -; CHECK: subw +; CHECK: negl %0 = trunc i32 %v to i16 ; <i16> [#uses=1] %1 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 %0) ; <i16> [#uses=0] ret void diff --git a/test/CodeGen/X86/avoid-loop-align.ll b/test/CodeGen/X86/avoid-loop-align.ll index d4c5c6723243..7957db72fe6d 100644 --- a/test/CodeGen/X86/avoid-loop-align.ll +++ b/test/CodeGen/X86/avoid-loop-align.ll @@ -3,9 +3,9 @@ ; CodeGen should align the top of the loop, which differs from the loop ; header in this case. -; CHECK: jmp LBB1_2 +; CHECK: jmp LBB0_2 ; CHECK: .align -; CHECK: LBB1_1: +; CHECK: LBB0_1: @A = common global [100 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=1] diff --git a/test/CodeGen/X86/brcond.ll b/test/CodeGen/X86/brcond.ll index 130483ad8410..5cdc1000f3cd 100644 --- a/test/CodeGen/X86/brcond.ll +++ b/test/CodeGen/X86/brcond.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=core2 | FileCheck %s ; rdar://7475489 define i32 @test1(i32 %a, i32 %b) nounwind ssp { @@ -46,7 +46,7 @@ return: ; preds = %entry ; CHECK: test2: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: orl 8(%esp), %eax -; CHECK-NEXT: jne LBB2_2 +; CHECK-NEXT: jne LBB1_2 } ; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0 @@ -65,5 +65,44 @@ return: ; preds = %entry ; CHECK: test3: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: orl 8(%esp), %eax -; CHECK-NEXT: je LBB3_2 +; CHECK-NEXT: je LBB2_2 +} + +; <rdar://problem/7598384>: +; +; jCC L1 +; jmp L2 +; L1: +; ... +; L2: +; ... +; +; to: +; +; jnCC L2 +; L1: +; ... +; L2: +; ... +define float @test4(float %x, float %y) nounwind readnone optsize ssp { +entry: + %0 = fpext float %x to double ; <double> [#uses=1] + %1 = fpext float %y to double ; <double> [#uses=1] + %2 = fmul double %0, %1 ; <double> [#uses=3] + %3 = fcmp oeq double %2, 0.000000e+00 ; <i1> [#uses=1] + br i1 %3, label %bb2, label %bb1 + +; CHECK: jne +; CHECK-NEXT: jnp +; CHECK-NOT: jmp +; CHECK: LBB + +bb1: ; preds = %entry + %4 = fadd double %2, -1.000000e+00 ; <double> [#uses=1] + br label %bb2 + +bb2: ; preds = %entry, %bb1 + %.0.in = phi double [ %4, %bb1 ], [ %2, %entry ] ; <double> [#uses=1] + %.0 = fptrunc double %.0.in to float ; <float> [#uses=1] + ret float %.0 } diff --git a/test/CodeGen/X86/const-select.ll b/test/CodeGen/X86/const-select.ll index ca8cc1464c77..665984ce28ed 100644 --- a/test/CodeGen/X86/const-select.ll +++ b/test/CodeGen/X86/const-select.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin7" -; RUN: llc < %s | grep {LCPI1_0(,%eax,4)} +; RUN: llc < %s | grep {LCPI0_0(,%eax,4)} define float @f(i32 %x) nounwind readnone { entry: %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/X86/constant-pool-sharing.ll b/test/CodeGen/X86/constant-pool-sharing.ll index c3e97adffb19..33de5767ad65 100644 --- a/test/CodeGen/X86/constant-pool-sharing.ll +++ b/test/CodeGen/X86/constant-pool-sharing.ll @@ -3,7 +3,7 @@ ; llc should share constant pool entries between this integer vector ; and this floating-point vector since they have the same encoding. -; CHECK: LCPI1_0(%rip), %xmm0 +; CHECK: LCPI0_0(%rip), %xmm0 ; CHECK: movaps %xmm0, (%rdi) ; CHECK: movaps %xmm0, (%rsi) diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll index 8e38fe309f7c..17cb2b305721 100644 --- a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll +++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \ -; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 10 +; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 9 ; RUN: grep {leal 1(\%rsi),} %t define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize { diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 4b7c85099389..2f27f35f0acd 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -92,3 +92,41 @@ foo: } +; Crash commoning identical asms. +; PR6803 +define void @test6(i1 %C) nounwind optsize ssp { +entry: + br i1 %C, label %do.body55, label %do.body92 + +do.body55: ; preds = %if.else36 + call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0 + ret void + +do.body92: ; preds = %if.then66 + call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !1 + ret void +} + +!0 = metadata !{i32 633550} +!1 = metadata !{i32 634261} + + +; Crash during XOR optimization. +; <rdar://problem/7869290> + +define void @test7() nounwind ssp { +entry: + br i1 undef, label %bb14, label %bb67 + +bb14: + %tmp0 = trunc i16 undef to i1 + %tmp1 = load i8* undef, align 8 + %tmp2 = shl i8 %tmp1, 4 + %tmp3 = lshr i8 %tmp2, 7 + %tmp4 = trunc i8 %tmp3 to i1 + %tmp5 = icmp ne i1 %tmp0, %tmp4 + br i1 %tmp5, label %bb14, label %bb67 + +bb67: + ret void +} diff --git a/test/CodeGen/X86/dbg-byval-parameter.ll b/test/CodeGen/X86/dbg-byval-parameter.ll new file mode 100644 index 000000000000..5e5577620d97 --- /dev/null +++ b/test/CodeGen/X86/dbg-byval-parameter.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=x86 -asm-verbose < %s | grep DW_TAG_formal_parameter + + +%struct.Pt = type { double, double } +%struct.Rect = type { %struct.Pt, %struct.Pt } + +define double @foo(%struct.Rect* byval %my_r0) nounwind ssp { +entry: + %retval = alloca double ; <double*> [#uses=2] + %0 = alloca double ; <double*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{%struct.Rect* %my_r0}, metadata !0), !dbg !15 + %1 = getelementptr inbounds %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1] + %2 = getelementptr inbounds %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; <double*> [#uses=1] + %3 = load double* %2, align 8, !dbg !16 ; <double> [#uses=1] + store double %3, double* %0, align 8, !dbg !16 + %4 = load double* %0, align 8, !dbg !16 ; <double> [#uses=1] + store double %4, double* %retval, align 8, !dbg !16 + br label %return, !dbg !16 + +return: ; preds = %entry + %retval1 = load double* %retval, !dbg !16 ; <double> [#uses=1] + ret double %retval1, !dbg !16 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!0 = metadata !{i32 524545, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"b2.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"b2.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !7} +!6 = metadata !{i32 524324, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 524307, metadata !2, metadata !"Rect", metadata !2, i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] +!8 = metadata !{metadata !9, metadata !14} +!9 = metadata !{i32 524301, metadata !7, metadata !"P1", metadata !2, i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 524307, metadata !2, metadata !"Pt", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!11 = metadata !{metadata !12, metadata !13} +!12 = metadata !{i32 524301, metadata !10, metadata !"x", metadata !2, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 524301, metadata !10, metadata !"y", metadata !2, i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!14 = metadata !{i32 524301, metadata !7, metadata !"P2", metadata !2, i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] +!15 = metadata !{i32 11, i32 0, metadata !1, null} +!16 = metadata !{i32 12, i32 0, metadata !17, null} +!17 = metadata !{i32 524299, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/CodeGen/X86/dllexport.ll b/test/CodeGen/X86/dllexport.ll index 2c699bfb0db4..bdbaac05f118 100644 --- a/test/CodeGen/X86/dllexport.ll +++ b/test/CodeGen/X86/dllexport.ll @@ -9,4 +9,4 @@ entry: } ; CHECK: .section .drectve -; CHECK: -export:@foo@0
\ No newline at end of file +; CHECK: -export:@foo@0 diff --git a/test/CodeGen/X86/fast-isel-constpool.ll b/test/CodeGen/X86/fast-isel-constpool.ll index 84d10f32c294..323c8533cec2 100644 --- a/test/CodeGen/X86/fast-isel-constpool.ll +++ b/test/CodeGen/X86/fast-isel-constpool.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -fast-isel | grep {LCPI1_0(%rip)} +; RUN: llc < %s -fast-isel | grep {LCPI0_0(%rip)} ; Make sure fast isel uses rip-relative addressing when required. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin9.0" diff --git a/test/CodeGen/X86/fast-isel-phys.ll b/test/CodeGen/X86/fast-isel-phys.ll deleted file mode 100644 index 158ef551ce42..000000000000 --- a/test/CodeGen/X86/fast-isel-phys.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 - -define i8 @t2(i8 %a, i8 %c) nounwind { - %tmp = shl i8 %a, %c - ret i8 %tmp -} - -define i8 @t1(i8 %a) nounwind { - %tmp = mul i8 %a, 17 - ret i8 %tmp -} diff --git a/test/CodeGen/X86/fast-isel-trunc.ll b/test/CodeGen/X86/fast-isel-trunc.ll deleted file mode 100644 index 69b26c5442e4..000000000000 --- a/test/CodeGen/X86/fast-isel-trunc.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort -; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort - -define i8 @t1(i32 %x) signext nounwind { - %tmp1 = trunc i32 %x to i8 - ret i8 %tmp1 -} - -define i8 @t2(i16 signext %x) signext nounwind { - %tmp1 = trunc i16 %x to i8 - ret i8 %tmp1 -} diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll index 84b3fd7caf3a..3d26ae7018b5 100644 --- a/test/CodeGen/X86/fast-isel.ll +++ b/test/CodeGen/X86/fast-isel.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 -mattr=sse2 +; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 ; This tests very minimal fast-isel functionality. @@ -65,6 +66,26 @@ define i8* @inttoptr_i32(i32 %p) nounwind { ret i8* %t } +define i8 @trunc_i32_i8(i32 %x) signext nounwind { + %tmp1 = trunc i32 %x to i8 + ret i8 %tmp1 +} + +define i8 @trunc_i16_i8(i16 signext %x) signext nounwind { + %tmp1 = trunc i16 %x to i8 + ret i8 %tmp1 +} + +define i8 @shl_i8(i8 %a, i8 %c) nounwind { + %tmp = shl i8 %a, %c + ret i8 %tmp +} + +define i8 @mul_i8(i8 %a) nounwind { + %tmp = mul i8 %a, 17 + ret i8 %tmp +} + define void @store_i1(i1* %p, i1 %t) nounwind { store i1 %t, i1* %p ret void diff --git a/test/CodeGen/X86/field-extract-use-trunc.ll b/test/CodeGen/X86/field-extract-use-trunc.ll index 60205305a977..735e1341f65b 100644 --- a/test/CodeGen/X86/field-extract-use-trunc.ll +++ b/test/CodeGen/X86/field-extract-use-trunc.ll @@ -1,38 +1,38 @@ ; RUN: llc < %s -march=x86 | grep sar | count 1 ; RUN: llc < %s -march=x86-64 | not grep sar -define i32 @test(i32 %f12) { +define i32 @test(i32 %f12) nounwind { %tmp7.25 = lshr i32 %f12, 16 %tmp7.26 = trunc i32 %tmp7.25 to i8 %tmp78.2 = sext i8 %tmp7.26 to i32 ret i32 %tmp78.2 } -define i32 @test2(i32 %f12) { +define i32 @test2(i32 %f12) nounwind { %f11 = shl i32 %f12, 8 %tmp7.25 = ashr i32 %f11, 24 ret i32 %tmp7.25 } -define i32 @test3(i32 %f12) { +define i32 @test3(i32 %f12) nounwind { %f11 = shl i32 %f12, 13 %tmp7.25 = ashr i32 %f11, 24 ret i32 %tmp7.25 } -define i64 @test4(i64 %f12) { +define i64 @test4(i64 %f12) nounwind { %f11 = shl i64 %f12, 32 %tmp7.25 = ashr i64 %f11, 32 ret i64 %tmp7.25 } -define i16 @test5(i16 %f12) { +define i16 @test5(i16 %f12) nounwind { %f11 = shl i16 %f12, 2 %tmp7.25 = ashr i16 %f11, 8 ret i16 %tmp7.25 } -define i16 @test6(i16 %f12) { +define i16 @test6(i16 %f12) nounwind { %f11 = shl i16 %f12, 8 %tmp7.25 = ashr i16 %f11, 8 ret i16 %tmp7.25 diff --git a/test/CodeGen/X86/fold-pcmpeqd-0.ll b/test/CodeGen/X86/fold-pcmpeqd-0.ll index ef5202f554c5..e5be58e1aaa3 100644 --- a/test/CodeGen/X86/fold-pcmpeqd-0.ll +++ b/test/CodeGen/X86/fold-pcmpeqd-0.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI1_2 | count 2 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI0_2 | count 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1 ; This testcase shouldn't need to spill the -1 value, diff --git a/test/CodeGen/X86/fp-elim.ll b/test/CodeGen/X86/fp-elim.ll new file mode 100644 index 000000000000..60892a2352fb --- /dev/null +++ b/test/CodeGen/X86/fp-elim.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -march=x86 -asm-verbose=false | FileCheck %s -check-prefix=FP-ELIM +; RUN: llc < %s -march=x86 -asm-verbose=false -disable-fp-elim | FileCheck %s -check-prefix=NO-ELIM +; RUN: llc < %s -march=x86 -asm-verbose=false -disable-non-leaf-fp-elim | FileCheck %s -check-prefix=NON-LEAF + +; Implement -momit-leaf-frame-pointer +; rdar://7886181 + +define i32 @t1() nounwind readnone { +entry: +; FP-ELIM: t1: +; FP-ELIM-NEXT: movl +; FP-ELIM-NEXT: ret + +; NO-ELIM: t1: +; NO-ELIM-NEXT: pushl %ebp +; NO-ELIM: popl %ebp +; NO-ELIM-NEXT: ret + +; NON-LEAF: t1: +; NON-LEAF-NEXT: movl +; NON-LEAF-NEXT: ret + ret i32 10 +} + +define void @t2() nounwind { +entry: +; FP-ELIM: t2: +; FP-ELIM-NOT: pushl %ebp +; FP-ELIM: ret + +; NO-ELIM: t2: +; NO-ELIM-NEXT: pushl %ebp +; NO-ELIM: popl %ebp +; NO-ELIM-NEXT: ret + +; NON-LEAF: t2: +; NON-LEAF-NEXT: pushl %ebp +; NON-LEAF: popl %ebp +; NON-LEAF-NEXT: ret + tail call void @foo(i32 0) nounwind + ret void +} + +declare void @foo(i32) diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll index d79c56bc4637..6d211913b015 100644 --- a/test/CodeGen/X86/global-sections.ll +++ b/test/CodeGen/X86/global-sections.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX ; RUN: llc < %s -mtriple=i386-apple-darwin9.7 | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -fdata-sections | FileCheck %s -check-prefix=LINUX-SECTIONS ; int G1; @@ -32,6 +33,12 @@ ; DARWIN: _G3: ; DARWIN: .long _G1 +; LINUX: .section .rodata,"a",@progbits +; LINUX: .globl G3 + +; LINUX-SECTIONS: .section .rodata.G3,"a",@progbits +; LINUX-SECTIONS: .globl G3 + ; _Complex long long const G4 = 34; @G4 = constant {i64,i64} { i64 34, i64 0 } @@ -97,6 +104,9 @@ ; LINUX: G7: ; LINUX: .asciz "abcdefghi" +; LINUX-SECTIONS: .section .rodata.G7,"aMS",@progbits,1 +; LINUX-SECTIONS: .globl G7 + @G8 = constant [4 x i16] [ i16 1, i16 2, i16 3, i16 0 ] @@ -134,3 +144,17 @@ ; LINUX: G10: ; LINUX: .zero 400 + + +;; Zero sized objects should round up to 1 byte in zerofill directives. +; rdar://7886017 +@G11 = global [0 x i32] zeroinitializer +@G12 = global {} zeroinitializer +@G13 = global { [0 x {}] } zeroinitializer + +; DARWIN: .globl _G11 +; DARWIN: .zerofill __DATA,__common,_G11,1,2 +; DARWIN: .globl _G12 +; DARWIN: .zerofill __DATA,__common,_G12,1,3 +; DARWIN: .globl _G13 +; DARWIN: .zerofill __DATA,__common,_G13,1,3 diff --git a/test/CodeGen/X86/h-registers-0.ll b/test/CodeGen/X86/h-registers-0.ll index 878fd93b737c..e84bb9a34a26 100644 --- a/test/CodeGen/X86/h-registers-0.ll +++ b/test/CodeGen/X86/h-registers-0.ll @@ -1,12 +1,16 @@ -; RUN: llc < %s -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 4 -; RUN: llc < %s -march=x86 > %t -; RUN: grep {incb %ah} %t | count 3 -; RUN: grep {movzbl %ah,} %t | count 3 +; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X86-64 +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32 ; Use h registers. On x86-64, codegen doesn't support general allocation ; of h registers yet, due to x86 encoding complications. define void @bar64(i64 inreg %x, i8* inreg %p) nounwind { +; X86-64: bar64: +; X86-64: shrq $8, %rdi +; X86-64: incb %dil + +; X86-32: bar64: +; X86-32: incb %ah %t0 = lshr i64 %x, 8 %t1 = trunc i64 %t0 to i8 %t2 = add i8 %t1, 1 @@ -15,6 +19,12 @@ define void @bar64(i64 inreg %x, i8* inreg %p) nounwind { } define void @bar32(i32 inreg %x, i8* inreg %p) nounwind { +; X86-64: bar32: +; X86-64: shrl $8, %edi +; X86-64: incb %dil + +; X86-32: bar32: +; X86-32: incb %ah %t0 = lshr i32 %x, 8 %t1 = trunc i32 %t0 to i8 %t2 = add i8 %t1, 1 @@ -23,6 +33,12 @@ define void @bar32(i32 inreg %x, i8* inreg %p) nounwind { } define void @bar16(i16 inreg %x, i8* inreg %p) nounwind { +; X86-64: bar16: +; X86-64: shrl $8, %edi +; X86-64: incb %dil + +; X86-32: bar16: +; X86-32: incb %ah %t0 = lshr i16 %x, 8 %t1 = trunc i16 %t0 to i8 %t2 = add i8 %t1, 1 @@ -31,18 +47,36 @@ define void @bar16(i16 inreg %x, i8* inreg %p) nounwind { } define i64 @qux64(i64 inreg %x) nounwind { +; X86-64: qux64: +; X86-64: movq %rdi, %rax +; X86-64: movzbl %ah, %eax + +; X86-32: qux64: +; X86-32: movzbl %ah, %eax %t0 = lshr i64 %x, 8 %t1 = and i64 %t0, 255 ret i64 %t1 } define i32 @qux32(i32 inreg %x) nounwind { +; X86-64: qux32: +; X86-64: movl %edi, %eax +; X86-64: movzbl %ah, %eax + +; X86-32: qux32: +; X86-32: movzbl %ah, %eax %t0 = lshr i32 %x, 8 %t1 = and i32 %t0, 255 ret i32 %t1 } define i16 @qux16(i16 inreg %x) nounwind { +; X86-64: qux16: +; X86-64: movl %edi, %eax +; X86-64: movzbl %ah, %eax + +; X86-32: qux16: +; X86-32: movzbl %ah, %eax %t0 = lshr i16 %x, 8 ret i16 %t0 } diff --git a/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/test/CodeGen/X86/ins_subreg_coalesce-1.ll index 2243f93f3ddd..83674361a773 100644 --- a/test/CodeGen/X86/ins_subreg_coalesce-1.ll +++ b/test/CodeGen/X86/ins_subreg_coalesce-1.ll @@ -1,7 +1,13 @@ -; RUN: llc < %s -march=x86 | grep mov | count 3 +; RUN: llc < %s -march=x86 | FileCheck %s -define fastcc i32 @sqlite3ExprResolveNames() nounwind { +define fastcc i32 @t() nounwind { entry: +; CHECK: t: +; CHECK: movzwl 0, %eax +; CHECK: orl $2, %eax +; CHECK: movw %ax, 0 +; CHECK: shrl $3, %eax +; CHECK: andl $1, %eax br i1 false, label %UnifiedReturnBlock, label %bb4 bb4: ; preds = %entry br i1 false, label %bb17, label %bb22 diff --git a/test/CodeGen/X86/loop-blocks.ll b/test/CodeGen/X86/loop-blocks.ll index a125e54050bb..354d08206972 100644 --- a/test/CodeGen/X86/loop-blocks.ll +++ b/test/CodeGen/X86/loop-blocks.ll @@ -7,11 +7,11 @@ ; order to avoid a branch within the loop. ; CHECK: simple: -; CHECK: jmp .LBB1_1 +; CHECK: jmp .LBB0_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: callq loop_latch -; CHECK-NEXT: .LBB1_1: +; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: callq loop_header define void @simple() nounwind { @@ -37,11 +37,11 @@ done: ; falls through into the loop, avoiding a branch within the loop. ; CHECK: slightly_more_involved: -; CHECK: jmp .LBB2_1 +; CHECK: jmp .LBB1_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: .LBB1_4: ; CHECK-NEXT: callq bar99 -; CHECK-NEXT: .LBB2_1: +; CHECK-NEXT: .LBB1_1: ; CHECK-NEXT: callq body define void @slightly_more_involved() nounwind { @@ -72,20 +72,20 @@ exit: ; fallthrough edges which should be preserved. ; CHECK: yet_more_involved: -; CHECK: jmp .LBB3_1 +; CHECK: jmp .LBB2_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: callq bar99 ; CHECK-NEXT: callq get ; CHECK-NEXT: cmpl $2999, %eax -; CHECK-NEXT: jg .LBB3_6 +; CHECK-NEXT: jg .LBB2_6 ; CHECK-NEXT: callq block_a_true_func -; CHECK-NEXT: jmp .LBB3_7 -; CHECK-NEXT: .LBB3_6: +; CHECK-NEXT: jmp .LBB2_7 +; CHECK-NEXT: .LBB2_6: ; CHECK-NEXT: callq block_a_false_func -; CHECK-NEXT: .LBB3_7: +; CHECK-NEXT: .LBB2_7: ; CHECK-NEXT: callq block_a_merge_func -; CHECK-NEXT: .LBB3_1: +; CHECK-NEXT: .LBB2_1: ; CHECK-NEXT: callq body define void @yet_more_involved() nounwind { @@ -131,20 +131,20 @@ exit: ; loop. ; CHECK: cfg_islands: -; CHECK: jmp .LBB4_1 +; CHECK: jmp .LBB3_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB4_7: +; CHECK-NEXT: .LBB3_7: ; CHECK-NEXT: callq bar100 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_8: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_8: ; CHECK-NEXT: callq bar101 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_9: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_9: ; CHECK-NEXT: callq bar102 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_5: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_5: ; CHECK-NEXT: callq loop_latch -; CHECK-NEXT: .LBB4_1: +; CHECK-NEXT: .LBB3_1: ; CHECK-NEXT: callq loop_header define void @cfg_islands() nounwind { diff --git a/test/CodeGen/X86/loop-hoist.ll b/test/CodeGen/X86/loop-hoist.ll index b9008e5e3022..c103e29f3bf3 100644 --- a/test/CodeGen/X86/loop-hoist.ll +++ b/test/CodeGen/X86/loop-hoist.ll @@ -4,7 +4,7 @@ ; CHECK: _foo: ; CHECK: L_Arr$non_lazy_ptr -; CHECK: LBB1_1: +; CHECK: LBB0_1: @Arr = external global [0 x i32] ; <[0 x i32]*> [#uses=1] diff --git a/test/CodeGen/X86/loop-strength-reduce8.ll b/test/CodeGen/X86/loop-strength-reduce8.ll index 6b2247d1d619..1d042769b0ba 100644 --- a/test/CodeGen/X86/loop-strength-reduce8.ll +++ b/test/CodeGen/X86/loop-strength-reduce8.ll @@ -4,7 +4,7 @@ ; CHECK: align ; CHECK: addl $4, %edx ; CHECK: decl %ecx -; CHECK: jne LBB1_2 +; CHECK: jne LBB0_2 %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32 } %struct.bitmap_element = type { %struct.bitmap_element*, %struct.bitmap_element*, i32, [2 x i64] } diff --git a/test/CodeGen/X86/lsr-delayed-fold.ll b/test/CodeGen/X86/lsr-delayed-fold.ll new file mode 100644 index 000000000000..17d6a4c0915f --- /dev/null +++ b/test/CodeGen/X86/lsr-delayed-fold.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=x86-64 < %s > /dev/null + +; ScalarEvolution misses an opportunity to fold ((trunc x) + (trunc -x) + y), +; but LSR should tolerate this. +; rdar://7886751 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11.0" + +define fastcc void @formatValue(i64 %arg5) nounwind { +bb12: ; preds = %bb11 + %t = trunc i64 %arg5 to i32 ; <i32> [#uses=1] + %t13 = sub i64 0, %arg5 ; <i64> [#uses=1] + %t14 = and i64 %t13, 4294967295 ; <i64> [#uses=1] + br label %bb15 + +bb15: ; preds = %bb21, %bb12 + %t16 = phi i64 [ 0, %bb12 ], [ %t23, %bb15 ] ; <i64> [#uses=2] + %t17 = mul i64 %t14, %t16 ; <i64> [#uses=1] + %t18 = add i64 undef, %t17 ; <i64> [#uses=1] + %t19 = trunc i64 %t18 to i32 ; <i32> [#uses=1] + %t22 = icmp eq i32 %t19, %t ; <i1> [#uses=1] + %t23 = add i64 %t16, 1 ; <i64> [#uses=1] + br i1 %t22, label %bb24, label %bb15 + +bb24: ; preds = %bb21, %bb11 + unreachable +} + +; ScalarEvolution should be able to correctly expand the crazy addrec here. +; PR6914 + +define void @int323() nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %lbl_264, %for.inc, %entry + %g_263.tmp.1 = phi i8 [ undef, %entry ], [ %g_263.tmp.1, %for.cond ] + %p_95.addr.0 = phi i8 [ 0, %entry ], [ %add, %for.cond ] + %add = add i8 %p_95.addr.0, 1 ; <i8> [#uses=1] + br i1 undef, label %for.cond, label %lbl_264 + +lbl_264: ; preds = %if.end, %lbl_264.preheader + %g_263.tmp.0 = phi i8 [ %g_263.tmp.1, %for.cond ] ; <i8> [#uses=1] + %tmp7 = load i16* undef ; <i16> [#uses=1] + %conv8 = trunc i16 %tmp7 to i8 ; <i8> [#uses=1] + %mul.i = mul i8 %p_95.addr.0, %p_95.addr.0 ; <i8> [#uses=1] + %mul.i18 = mul i8 %mul.i, %conv8 ; <i8> [#uses=1] + %tobool12 = icmp eq i8 %mul.i18, 0 ; <i1> [#uses=1] + unreachable +} diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll index ab71555950b2..b80ee0897d89 100644 --- a/test/CodeGen/X86/lsr-reuse.ll +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -260,7 +260,7 @@ return: ; CHECK: count_me_2: ; CHECK: movl $10, %eax ; CHECK: align -; CHECK: BB7_1: +; CHECK: BB6_1: ; CHECK: movsd -40(%rdi,%rax,8), %xmm0 ; CHECK: addsd -40(%rsi,%rax,8), %xmm0 ; CHECK: movsd %xmm0, -40(%rdx,%rax,8) @@ -305,7 +305,7 @@ return: ; CHECK: full_me_1: ; CHECK: align -; CHECK: BB8_1: +; CHECK: BB7_1: ; CHECK: movsd (%rdi), %xmm0 ; CHECK: addsd (%rsi), %xmm0 ; CHECK: movsd %xmm0, (%rdx) @@ -389,7 +389,7 @@ return: ; rdar://7657764 ; CHECK: asd: -; CHECK: BB10_5: +; CHECK: BB9_5: ; CHECK-NEXT: addl (%r{{[^,]*}},%rdi,4), %e ; CHECK-NEXT: incq %rdi ; CHECK-NEXT: cmpq %rdi, %r{{[^,]*}} diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll index 4fe32d974d05..17cd8e868a25 100644 --- a/test/CodeGen/X86/memcpy-2.ll +++ b/test/CodeGen/X86/memcpy-2.ll @@ -3,20 +3,20 @@ ; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64 - %struct.ParmT = type { [25 x i8], i8, i8* } -@.str12 = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" ; <[25 x i8]*> [#uses=1] +@.str = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" +@.str2 = internal constant [30 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 4 define void @t1(i32 %argc, i8** %argv) nounwind { entry: ; SSE2: t1: -; SSE2: movaps _.str12, %xmm0 +; SSE2: movaps _.str, %xmm0 ; SSE2: movaps %xmm0 ; SSE2: movb $0 ; SSE2: movl $0 ; SSE2: movl $0 ; SSE1: t1: -; SSE1: movaps _.str12, %xmm0 +; SSE1: movaps _.str, %xmm0 ; SSE1: movaps %xmm0 ; SSE1: movb $0 ; SSE1: movl $0 @@ -32,14 +32,14 @@ entry: ; NOSSE: movl $1734438249 ; X86-64: t1: -; X86-64: movaps _.str12(%rip), %xmm0 +; X86-64: movaps _.str(%rip), %xmm0 ; X86-64: movaps %xmm0 ; X86-64: movb $0 ; X86-64: movq $0 - %parms.i = alloca [13 x %struct.ParmT] ; <[13 x %struct.ParmT]*> [#uses=1] - %parms1.i = getelementptr [13 x %struct.ParmT]* %parms.i, i32 0, i32 0, i32 0, i32 0 ; <i8*> [#uses=1] - call void @llvm.memcpy.i32( i8* %parms1.i, i8* getelementptr ([25 x i8]* @.str12, i32 0, i32 0), i32 25, i32 1 ) nounwind - unreachable + %tmp1 = alloca [25 x i8] + %tmp2 = bitcast [25 x i8]* %tmp1 to i8* + call void @llvm.memcpy.i32( i8* %tmp2, i8* getelementptr ([25 x i8]* @.str, i32 0, i32 0), i32 25, i32 1 ) nounwind + unreachable } ;rdar://7774704 @@ -119,4 +119,49 @@ entry: ret void } +define void @t4() nounwind { +entry: +; SSE2: t4: +; SSE2: movw $120 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 + +; SSE1: t4: +; SSE1: movw $120 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 + +; NOSSE: t4: +; NOSSE: movw $120 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 + +; X86-64: t4: +; X86-64: movabsq $8680820740569200760, %rax +; X86-64: movq %rax +; X86-64: movq %rax +; X86-64: movq %rax +; X86-64: movw $120 +; X86-64: movl $2021161080 + %tmp1 = alloca [30 x i8] + %tmp2 = bitcast [30 x i8]* %tmp1 to i8* + call void @llvm.memcpy.i32(i8* %tmp2, i8* getelementptr inbounds ([30 x i8]* @.str2, i32 0, i32 0), i32 30, i32 1) + unreachable +} + declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind diff --git a/test/CodeGen/X86/multiple-loop-post-inc.ll b/test/CodeGen/X86/multiple-loop-post-inc.ll new file mode 100644 index 000000000000..51a06112aada --- /dev/null +++ b/test/CodeGen/X86/multiple-loop-post-inc.ll @@ -0,0 +1,304 @@ +; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 < %s | FileCheck %s +; rdar://7236213 + +; CodeGen shouldn't require any lea instructions inside the marked loop. +; It should properly set up post-increment uses and do coalescing for +; the induction variables. + +; CHECK: # Start +; CHECK-NOT: lea +; CHECK: # Stop + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @foo(float* %I, i64 %IS, float* nocapture %Start, float* nocapture %Step, float* %O, i64 %OS, i64 %N) nounwind { +entry: + %times4 = alloca float, align 4 ; <float*> [#uses=3] + %timesN = alloca float, align 4 ; <float*> [#uses=2] + %0 = load float* %Step, align 4 ; <float> [#uses=8] + %1 = ptrtoint float* %I to i64 ; <i64> [#uses=1] + %2 = ptrtoint float* %O to i64 ; <i64> [#uses=1] + %tmp = xor i64 %2, %1 ; <i64> [#uses=1] + %tmp16 = and i64 %tmp, 15 ; <i64> [#uses=1] + %3 = icmp eq i64 %tmp16, 0 ; <i1> [#uses=1] + %4 = trunc i64 %IS to i32 ; <i32> [#uses=1] + %5 = xor i32 %4, 1 ; <i32> [#uses=1] + %6 = trunc i64 %OS to i32 ; <i32> [#uses=1] + %7 = xor i32 %6, 1 ; <i32> [#uses=1] + %8 = or i32 %7, %5 ; <i32> [#uses=1] + %9 = icmp eq i32 %8, 0 ; <i1> [#uses=1] + br i1 %9, label %bb, label %return + +bb: ; preds = %entry + %10 = load float* %Start, align 4 ; <float> [#uses=1] + br label %bb2 + +bb1: ; preds = %bb3 + %11 = load float* %I_addr.0, align 4 ; <float> [#uses=1] + %12 = fmul float %11, %x.0 ; <float> [#uses=1] + store float %12, float* %O_addr.0, align 4 + %13 = fadd float %x.0, %0 ; <float> [#uses=1] + %indvar.next53 = add i64 %14, 1 ; <i64> [#uses=1] + br label %bb2 + +bb2: ; preds = %bb1, %bb + %14 = phi i64 [ %indvar.next53, %bb1 ], [ 0, %bb ] ; <i64> [#uses=21] + %x.0 = phi float [ %13, %bb1 ], [ %10, %bb ] ; <float> [#uses=6] + %N_addr.0 = sub i64 %N, %14 ; <i64> [#uses=4] + %O_addr.0 = getelementptr float* %O, i64 %14 ; <float*> [#uses=4] + %I_addr.0 = getelementptr float* %I, i64 %14 ; <float*> [#uses=3] + %15 = icmp slt i64 %N_addr.0, 1 ; <i1> [#uses=1] + br i1 %15, label %bb4, label %bb3 + +bb3: ; preds = %bb2 + %16 = ptrtoint float* %O_addr.0 to i64 ; <i64> [#uses=1] + %17 = and i64 %16, 15 ; <i64> [#uses=1] + %18 = icmp eq i64 %17, 0 ; <i1> [#uses=1] + br i1 %18, label %bb4, label %bb1 + +bb4: ; preds = %bb3, %bb2 + %19 = fmul float %0, 4.000000e+00 ; <float> [#uses=1] + store float %19, float* %times4, align 4 + %20 = fmul float %0, 1.600000e+01 ; <float> [#uses=1] + store float %20, float* %timesN, align 4 + %21 = fmul float %0, 0.000000e+00 ; <float> [#uses=1] + %22 = fadd float %21, %x.0 ; <float> [#uses=1] + %23 = fadd float %x.0, %0 ; <float> [#uses=1] + %24 = fmul float %0, 2.000000e+00 ; <float> [#uses=1] + %25 = fadd float %24, %x.0 ; <float> [#uses=1] + %26 = fmul float %0, 3.000000e+00 ; <float> [#uses=1] + %27 = fadd float %26, %x.0 ; <float> [#uses=1] + %28 = insertelement <4 x float> undef, float %22, i32 0 ; <<4 x float>> [#uses=1] + %29 = insertelement <4 x float> %28, float %23, i32 1 ; <<4 x float>> [#uses=1] + %30 = insertelement <4 x float> %29, float %25, i32 2 ; <<4 x float>> [#uses=1] + %31 = insertelement <4 x float> %30, float %27, i32 3 ; <<4 x float>> [#uses=5] + %asmtmp.i = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %times4) nounwind ; <<4 x float>> [#uses=3] + %32 = fadd <4 x float> %31, %asmtmp.i ; <<4 x float>> [#uses=3] + %33 = fadd <4 x float> %32, %asmtmp.i ; <<4 x float>> [#uses=3] + %34 = fadd <4 x float> %33, %asmtmp.i ; <<4 x float>> [#uses=2] + %asmtmp.i18 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %timesN) nounwind ; <<4 x float>> [#uses=8] + %35 = icmp sgt i64 %N_addr.0, 15 ; <i1> [#uses=2] + br i1 %3, label %bb6.preheader, label %bb8 + +bb6.preheader: ; preds = %bb4 + br i1 %35, label %bb.nph43, label %bb7 + +bb.nph43: ; preds = %bb6.preheader + %tmp108 = add i64 %14, 16 ; <i64> [#uses=1] + %tmp111 = add i64 %14, 4 ; <i64> [#uses=1] + %tmp115 = add i64 %14, 8 ; <i64> [#uses=1] + %tmp119 = add i64 %14, 12 ; <i64> [#uses=1] + %tmp134 = add i64 %N, -16 ; <i64> [#uses=1] + %tmp135 = sub i64 %tmp134, %14 ; <i64> [#uses=1] + call void asm sideeffect "# Start.", "~{dirflag},~{fpsr},~{flags}"() nounwind + br label %bb5 + +bb5: ; preds = %bb.nph43, %bb5 + %indvar102 = phi i64 [ 0, %bb.nph43 ], [ %indvar.next103, %bb5 ] ; <i64> [#uses=3] + %vX3.041 = phi <4 x float> [ %34, %bb.nph43 ], [ %45, %bb5 ] ; <<4 x float>> [#uses=2] + %vX0.039 = phi <4 x float> [ %31, %bb.nph43 ], [ %41, %bb5 ] ; <<4 x float>> [#uses=2] + %vX2.037 = phi <4 x float> [ %33, %bb.nph43 ], [ %46, %bb5 ] ; <<4 x float>> [#uses=2] + %vX1.036 = phi <4 x float> [ %32, %bb.nph43 ], [ %47, %bb5 ] ; <<4 x float>> [#uses=2] + %tmp104 = shl i64 %indvar102, 4 ; <i64> [#uses=5] + %tmp105 = add i64 %14, %tmp104 ; <i64> [#uses=2] + %scevgep106 = getelementptr float* %I, i64 %tmp105 ; <float*> [#uses=1] + %scevgep106107 = bitcast float* %scevgep106 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp109 = add i64 %tmp108, %tmp104 ; <i64> [#uses=2] + %tmp112 = add i64 %tmp111, %tmp104 ; <i64> [#uses=2] + %scevgep113 = getelementptr float* %I, i64 %tmp112 ; <float*> [#uses=1] + %scevgep113114 = bitcast float* %scevgep113 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp116 = add i64 %tmp115, %tmp104 ; <i64> [#uses=2] + %scevgep117 = getelementptr float* %I, i64 %tmp116 ; <float*> [#uses=1] + %scevgep117118 = bitcast float* %scevgep117 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp120 = add i64 %tmp119, %tmp104 ; <i64> [#uses=2] + %scevgep121 = getelementptr float* %I, i64 %tmp120 ; <float*> [#uses=1] + %scevgep121122 = bitcast float* %scevgep121 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep123 = getelementptr float* %O, i64 %tmp105 ; <float*> [#uses=1] + %scevgep123124 = bitcast float* %scevgep123 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep126 = getelementptr float* %O, i64 %tmp112 ; <float*> [#uses=1] + %scevgep126127 = bitcast float* %scevgep126 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep128 = getelementptr float* %O, i64 %tmp116 ; <float*> [#uses=1] + %scevgep128129 = bitcast float* %scevgep128 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep130 = getelementptr float* %O, i64 %tmp120 ; <float*> [#uses=1] + %scevgep130131 = bitcast float* %scevgep130 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp132 = mul i64 %indvar102, -16 ; <i64> [#uses=1] + %tmp136 = add i64 %tmp135, %tmp132 ; <i64> [#uses=2] + %36 = load <4 x float>* %scevgep106107, align 16 ; <<4 x float>> [#uses=1] + %37 = load <4 x float>* %scevgep113114, align 16 ; <<4 x float>> [#uses=1] + %38 = load <4 x float>* %scevgep117118, align 16 ; <<4 x float>> [#uses=1] + %39 = load <4 x float>* %scevgep121122, align 16 ; <<4 x float>> [#uses=1] + %40 = fmul <4 x float> %36, %vX0.039 ; <<4 x float>> [#uses=1] + %41 = fadd <4 x float> %vX0.039, %asmtmp.i18 ; <<4 x float>> [#uses=2] + %42 = fmul <4 x float> %37, %vX1.036 ; <<4 x float>> [#uses=1] + %43 = fmul <4 x float> %38, %vX2.037 ; <<4 x float>> [#uses=1] + %44 = fmul <4 x float> %39, %vX3.041 ; <<4 x float>> [#uses=1] + store <4 x float> %40, <4 x float>* %scevgep123124, align 16 + store <4 x float> %42, <4 x float>* %scevgep126127, align 16 + store <4 x float> %43, <4 x float>* %scevgep128129, align 16 + store <4 x float> %44, <4 x float>* %scevgep130131, align 16 + %45 = fadd <4 x float> %vX3.041, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %46 = fadd <4 x float> %vX2.037, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %47 = fadd <4 x float> %vX1.036, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %48 = icmp sgt i64 %tmp136, 15 ; <i1> [#uses=1] + %indvar.next103 = add i64 %indvar102, 1 ; <i64> [#uses=1] + br i1 %48, label %bb5, label %bb6.bb7_crit_edge + +bb6.bb7_crit_edge: ; preds = %bb5 + call void asm sideeffect "# Stop.", "~{dirflag},~{fpsr},~{flags}"() nounwind + %scevgep110 = getelementptr float* %I, i64 %tmp109 ; <float*> [#uses=1] + %scevgep125 = getelementptr float* %O, i64 %tmp109 ; <float*> [#uses=1] + br label %bb7 + +bb7: ; preds = %bb6.bb7_crit_edge, %bb6.preheader + %I_addr.1.lcssa = phi float* [ %scevgep110, %bb6.bb7_crit_edge ], [ %I_addr.0, %bb6.preheader ] ; <float*> [#uses=1] + %O_addr.1.lcssa = phi float* [ %scevgep125, %bb6.bb7_crit_edge ], [ %O_addr.0, %bb6.preheader ] ; <float*> [#uses=1] + %vX0.0.lcssa = phi <4 x float> [ %41, %bb6.bb7_crit_edge ], [ %31, %bb6.preheader ] ; <<4 x float>> [#uses=1] + %N_addr.1.lcssa = phi i64 [ %tmp136, %bb6.bb7_crit_edge ], [ %N_addr.0, %bb6.preheader ] ; <i64> [#uses=1] + %asmtmp.i17 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %times4) nounwind ; <<4 x float>> [#uses=0] + br label %bb11 + +bb8: ; preds = %bb4 + br i1 %35, label %bb.nph, label %bb11 + +bb.nph: ; preds = %bb8 + %I_addr.0.sum = add i64 %14, -1 ; <i64> [#uses=1] + %49 = getelementptr inbounds float* %I, i64 %I_addr.0.sum ; <float*> [#uses=1] + %50 = bitcast float* %49 to <4 x float>* ; <<4 x float>*> [#uses=1] + %51 = load <4 x float>* %50, align 16 ; <<4 x float>> [#uses=1] + %tmp54 = add i64 %14, 16 ; <i64> [#uses=1] + %tmp56 = add i64 %14, 3 ; <i64> [#uses=1] + %tmp60 = add i64 %14, 7 ; <i64> [#uses=1] + %tmp64 = add i64 %14, 11 ; <i64> [#uses=1] + %tmp68 = add i64 %14, 15 ; <i64> [#uses=1] + %tmp76 = add i64 %14, 4 ; <i64> [#uses=1] + %tmp80 = add i64 %14, 8 ; <i64> [#uses=1] + %tmp84 = add i64 %14, 12 ; <i64> [#uses=1] + %tmp90 = add i64 %N, -16 ; <i64> [#uses=1] + %tmp91 = sub i64 %tmp90, %14 ; <i64> [#uses=1] + br label %bb9 + +bb9: ; preds = %bb.nph, %bb9 + %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb9 ] ; <i64> [#uses=3] + %vX3.125 = phi <4 x float> [ %34, %bb.nph ], [ %69, %bb9 ] ; <<4 x float>> [#uses=2] + %vX0.223 = phi <4 x float> [ %31, %bb.nph ], [ %65, %bb9 ] ; <<4 x float>> [#uses=2] + %vX2.121 = phi <4 x float> [ %33, %bb.nph ], [ %70, %bb9 ] ; <<4 x float>> [#uses=2] + %vX1.120 = phi <4 x float> [ %32, %bb.nph ], [ %71, %bb9 ] ; <<4 x float>> [#uses=2] + %vI0.019 = phi <4 x float> [ %51, %bb.nph ], [ %55, %bb9 ] ; <<4 x float>> [#uses=1] + %tmp51 = shl i64 %indvar, 4 ; <i64> [#uses=9] + %tmp55 = add i64 %tmp54, %tmp51 ; <i64> [#uses=2] + %tmp57 = add i64 %tmp56, %tmp51 ; <i64> [#uses=1] + %scevgep58 = getelementptr float* %I, i64 %tmp57 ; <float*> [#uses=1] + %scevgep5859 = bitcast float* %scevgep58 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp61 = add i64 %tmp60, %tmp51 ; <i64> [#uses=1] + %scevgep62 = getelementptr float* %I, i64 %tmp61 ; <float*> [#uses=1] + %scevgep6263 = bitcast float* %scevgep62 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp65 = add i64 %tmp64, %tmp51 ; <i64> [#uses=1] + %scevgep66 = getelementptr float* %I, i64 %tmp65 ; <float*> [#uses=1] + %scevgep6667 = bitcast float* %scevgep66 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp69 = add i64 %tmp68, %tmp51 ; <i64> [#uses=1] + %scevgep70 = getelementptr float* %I, i64 %tmp69 ; <float*> [#uses=1] + %scevgep7071 = bitcast float* %scevgep70 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp72 = add i64 %14, %tmp51 ; <i64> [#uses=1] + %scevgep73 = getelementptr float* %O, i64 %tmp72 ; <float*> [#uses=1] + %scevgep7374 = bitcast float* %scevgep73 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp77 = add i64 %tmp76, %tmp51 ; <i64> [#uses=1] + %scevgep78 = getelementptr float* %O, i64 %tmp77 ; <float*> [#uses=1] + %scevgep7879 = bitcast float* %scevgep78 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp81 = add i64 %tmp80, %tmp51 ; <i64> [#uses=1] + %scevgep82 = getelementptr float* %O, i64 %tmp81 ; <float*> [#uses=1] + %scevgep8283 = bitcast float* %scevgep82 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp85 = add i64 %tmp84, %tmp51 ; <i64> [#uses=1] + %scevgep86 = getelementptr float* %O, i64 %tmp85 ; <float*> [#uses=1] + %scevgep8687 = bitcast float* %scevgep86 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp88 = mul i64 %indvar, -16 ; <i64> [#uses=1] + %tmp92 = add i64 %tmp91, %tmp88 ; <i64> [#uses=2] + %52 = load <4 x float>* %scevgep5859, align 16 ; <<4 x float>> [#uses=2] + %53 = load <4 x float>* %scevgep6263, align 16 ; <<4 x float>> [#uses=2] + %54 = load <4 x float>* %scevgep6667, align 16 ; <<4 x float>> [#uses=2] + %55 = load <4 x float>* %scevgep7071, align 16 ; <<4 x float>> [#uses=2] + %56 = shufflevector <4 x float> %vI0.019, <4 x float> %52, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %57 = shufflevector <4 x float> %56, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %58 = shufflevector <4 x float> %52, <4 x float> %53, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %59 = shufflevector <4 x float> %58, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %60 = shufflevector <4 x float> %53, <4 x float> %54, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %61 = shufflevector <4 x float> %60, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %62 = shufflevector <4 x float> %54, <4 x float> %55, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %63 = shufflevector <4 x float> %62, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %64 = fmul <4 x float> %57, %vX0.223 ; <<4 x float>> [#uses=1] + %65 = fadd <4 x float> %vX0.223, %asmtmp.i18 ; <<4 x float>> [#uses=2] + %66 = fmul <4 x float> %59, %vX1.120 ; <<4 x float>> [#uses=1] + %67 = fmul <4 x float> %61, %vX2.121 ; <<4 x float>> [#uses=1] + %68 = fmul <4 x float> %63, %vX3.125 ; <<4 x float>> [#uses=1] + store <4 x float> %64, <4 x float>* %scevgep7374, align 16 + store <4 x float> %66, <4 x float>* %scevgep7879, align 16 + store <4 x float> %67, <4 x float>* %scevgep8283, align 16 + store <4 x float> %68, <4 x float>* %scevgep8687, align 16 + %69 = fadd <4 x float> %vX3.125, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %70 = fadd <4 x float> %vX2.121, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %71 = fadd <4 x float> %vX1.120, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %72 = icmp sgt i64 %tmp92, 15 ; <i1> [#uses=1] + %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1] + br i1 %72, label %bb9, label %bb10.bb11.loopexit_crit_edge + +bb10.bb11.loopexit_crit_edge: ; preds = %bb9 + %scevgep = getelementptr float* %I, i64 %tmp55 ; <float*> [#uses=1] + %scevgep75 = getelementptr float* %O, i64 %tmp55 ; <float*> [#uses=1] + br label %bb11 + +bb11: ; preds = %bb8, %bb10.bb11.loopexit_crit_edge, %bb7 + %N_addr.2 = phi i64 [ %N_addr.1.lcssa, %bb7 ], [ %tmp92, %bb10.bb11.loopexit_crit_edge ], [ %N_addr.0, %bb8 ] ; <i64> [#uses=2] + %vX0.1 = phi <4 x float> [ %vX0.0.lcssa, %bb7 ], [ %65, %bb10.bb11.loopexit_crit_edge ], [ %31, %bb8 ] ; <<4 x float>> [#uses=1] + %O_addr.2 = phi float* [ %O_addr.1.lcssa, %bb7 ], [ %scevgep75, %bb10.bb11.loopexit_crit_edge ], [ %O_addr.0, %bb8 ] ; <float*> [#uses=1] + %I_addr.2 = phi float* [ %I_addr.1.lcssa, %bb7 ], [ %scevgep, %bb10.bb11.loopexit_crit_edge ], [ %I_addr.0, %bb8 ] ; <float*> [#uses=1] + %73 = extractelement <4 x float> %vX0.1, i32 0 ; <float> [#uses=2] + %74 = icmp sgt i64 %N_addr.2, 0 ; <i1> [#uses=1] + br i1 %74, label %bb12, label %bb14 + +bb12: ; preds = %bb11, %bb12 + %indvar94 = phi i64 [ %indvar.next95, %bb12 ], [ 0, %bb11 ] ; <i64> [#uses=3] + %x.130 = phi float [ %77, %bb12 ], [ %73, %bb11 ] ; <float> [#uses=2] + %I_addr.433 = getelementptr float* %I_addr.2, i64 %indvar94 ; <float*> [#uses=1] + %O_addr.432 = getelementptr float* %O_addr.2, i64 %indvar94 ; <float*> [#uses=1] + %75 = load float* %I_addr.433, align 4 ; <float> [#uses=1] + %76 = fmul float %75, %x.130 ; <float> [#uses=1] + store float %76, float* %O_addr.432, align 4 + %77 = fadd float %x.130, %0 ; <float> [#uses=2] + %indvar.next95 = add i64 %indvar94, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %indvar.next95, %N_addr.2 ; <i1> [#uses=1] + br i1 %exitcond, label %bb14, label %bb12 + +bb14: ; preds = %bb12, %bb11 + %x.1.lcssa = phi float [ %73, %bb11 ], [ %77, %bb12 ] ; <float> [#uses=1] + store float %x.1.lcssa, float* %Start, align 4 + ret void + +return: ; preds = %entry + ret void +} + +; Codegen shouldn't crash on this testcase. + +define void @bar(i32 %a, i32 %b) nounwind { +entry: ; preds = %bb1, %entry, %for.end204 + br label %outer + +outer: ; preds = %bb1, %entry + %i6 = phi i32 [ %storemerge171, %bb1 ], [ %a, %entry ] ; <i32> [#uses=2] + %storemerge171 = add i32 %i6, 1 ; <i32> [#uses=1] + br label %inner + +inner: ; preds = %bb0, %if.end275 + %i8 = phi i32 [ %a, %outer ], [ %indvar.next159, %bb0 ] ; <i32> [#uses=2] + %t338 = load i32* undef ; <i32> [#uses=1] + %t191 = mul i32 %i8, %t338 ; <i32> [#uses=1] + %t179 = add i32 %i6, %t191 ; <i32> [#uses=1] + br label %bb0 + +bb0: ; preds = %for.body332 + %indvar.next159 = add i32 %i8, 1 ; <i32> [#uses=1] + br i1 undef, label %bb1, label %inner + +bb1: ; preds = %bb0, %outer + %midx.4 = phi i32 [ %t179, %bb0 ] ; <i32> [#uses=0] + br label %outer +} diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll new file mode 100644 index 000000000000..bf8bfa28dafd --- /dev/null +++ b/test/CodeGen/X86/optimize-max-3.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; LSR's OptimizeMax should eliminate the select (max). + +; CHECK: foo: +; CHECK-NOT: cmov +; CHECK: jle + +define void @foo(i64 %n, double* nocapture %p) nounwind { +entry: + %cmp6 = icmp slt i64 %n, 0 ; <i1> [#uses=1] + br i1 %cmp6, label %for.end, label %for.body.preheader + +for.body.preheader: ; preds = %entry + %tmp = icmp sgt i64 %n, 0 ; <i1> [#uses=1] + %n.op = add i64 %n, 1 ; <i64> [#uses=1] + %tmp1 = select i1 %tmp, i64 %n.op, i64 1 ; <i64> [#uses=1] + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i = phi i64 [ %i.next, %for.body ], [ 0, %for.body.preheader ] ; <i64> [#uses=2] + %arrayidx = getelementptr double* %p, i64 %i ; <double*> [#uses=2] + %t4 = load double* %arrayidx ; <double> [#uses=1] + %mul = fmul double %t4, 2.200000e+00 ; <double> [#uses=1] + store double %mul, double* %arrayidx + %i.next = add nsw i64 %i, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %i.next, %tmp1 ; <i1> [#uses=1] + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/CodeGen/X86/or-address.ll b/test/CodeGen/X86/or-address.ll new file mode 100644 index 000000000000..6447680e623b --- /dev/null +++ b/test/CodeGen/X86/or-address.ll @@ -0,0 +1,90 @@ +; PR1135 +; RUN: llc %s -o - | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.3" + + +; CHECK: movl %{{.*}}, (%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 8(%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 4(%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 12(%rdi,%rdx,4) + +define void @test(i32* nocapture %array, i32 %r0) nounwind ssp noredzone { +bb.nph: + br label %bb + +bb: ; preds = %bb, %bb.nph + %j.010 = phi i8 [ 0, %bb.nph ], [ %14, %bb ] ; <i8> [#uses=1] + %k.19 = phi i8 [ 0, %bb.nph ], [ %.k.1, %bb ] ; <i8> [#uses=1] + %i0.08 = phi i8 [ 0, %bb.nph ], [ %15, %bb ] ; <i8> [#uses=3] + %0 = icmp slt i8 %i0.08, 4 ; <i1> [#uses=1] + %iftmp.0.0 = select i1 %0, i8 %i0.08, i8 0 ; <i8> [#uses=2] + %1 = icmp eq i8 %i0.08, 4 ; <i1> [#uses=1] + %2 = zext i1 %1 to i8 ; <i8> [#uses=1] + %.k.1 = add i8 %2, %k.19 ; <i8> [#uses=2] + %3 = shl i8 %.k.1, 2 ; <i8> [#uses=1] + %4 = add i8 %3, %iftmp.0.0 ; <i8> [#uses=1] + %5 = shl i8 %4, 2 ; <i8> [#uses=1] + %6 = zext i8 %5 to i64 ; <i64> [#uses=4] + %7 = getelementptr inbounds i32* %array, i64 %6 ; <i32*> [#uses=1] + store i32 %r0, i32* %7, align 4 + %8 = or i64 %6, 2 ; <i64> [#uses=1] + %9 = getelementptr inbounds i32* %array, i64 %8 ; <i32*> [#uses=1] + store i32 %r0, i32* %9, align 4 + %10 = or i64 %6, 1 ; <i64> [#uses=1] + %11 = getelementptr inbounds i32* %array, i64 %10 ; <i32*> [#uses=1] + store i32 %r0, i32* %11, align 4 + %12 = or i64 %6, 3 ; <i64> [#uses=1] + %13 = getelementptr inbounds i32* %array, i64 %12 ; <i32*> [#uses=1] + store i32 %r0, i32* %13, align 4 + %14 = add nsw i8 %j.010, 1 ; <i8> [#uses=2] + %15 = add i8 %iftmp.0.0, 1 ; <i8> [#uses=1] + %exitcond = icmp eq i8 %14, 32 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} + +; CHECK: test1: +; CHECK: movl %{{.*}}, (%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 8(%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 4(%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 12(%rdi,%rcx,4) + +define void @test1(i32* nocapture %array, i32 %r0, i8 signext %k, i8 signext %i0) nounwind { +bb.nph: + br label %for.body + +for.body: ; preds = %for.body, %bb.nph + %j.065 = phi i8 [ 0, %bb.nph ], [ %inc52, %for.body ] ; <i8> [#uses=1] + %i0.addr.064 = phi i8 [ %i0, %bb.nph ], [ %add, %for.body ] ; <i8> [#uses=3] + %k.addr.163 = phi i8 [ %k, %bb.nph ], [ %inc.k.addr.1, %for.body ] ; <i8> [#uses=1] + %cmp5 = icmp slt i8 %i0.addr.064, 4 ; <i1> [#uses=1] + %cond = select i1 %cmp5, i8 %i0.addr.064, i8 0 ; <i8> [#uses=2] + %cmp12 = icmp eq i8 %i0.addr.064, 4 ; <i1> [#uses=1] + %inc = zext i1 %cmp12 to i8 ; <i8> [#uses=1] + %inc.k.addr.1 = add i8 %inc, %k.addr.163 ; <i8> [#uses=2] + %mul = shl i8 %cond, 2 ; <i8> [#uses=1] + %mul22 = shl i8 %inc.k.addr.1, 4 ; <i8> [#uses=1] + %add23 = add i8 %mul22, %mul ; <i8> [#uses=1] + %idxprom = zext i8 %add23 to i64 ; <i64> [#uses=4] + %arrayidx = getelementptr inbounds i32* %array, i64 %idxprom ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx + %add3356 = or i64 %idxprom, 2 ; <i64> [#uses=1] + %arrayidx36 = getelementptr inbounds i32* %array, i64 %add3356 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx36 + %add4058 = or i64 %idxprom, 1 ; <i64> [#uses=1] + %arrayidx43 = getelementptr inbounds i32* %array, i64 %add4058 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx43 + %add4760 = or i64 %idxprom, 3 ; <i64> [#uses=1] + %arrayidx50 = getelementptr inbounds i32* %array, i64 %add4760 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx50 + %inc52 = add nsw i8 %j.065, 1 ; <i8> [#uses=2] + %add = add i8 %cond, 1 ; <i8> [#uses=1] + %exitcond = icmp eq i8 %inc52, 32 ; <i1> [#uses=1] + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index 35b172509c95..9506c9b5db11 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -4,18 +4,18 @@ @dst = external global i32 @src = external global i32 -define void @test1() nounwind { +define void @test0() nounwind { entry: store i32* @dst, i32** @ptr %tmp.s = load i32* @src store i32 %tmp.s, i32* @dst ret void -; LINUX: test1: -; LINUX: call .L1$pb -; LINUX-NEXT: .L1$pb: +; LINUX: test0: +; LINUX: call .L0$pb +; LINUX-NEXT: .L0$pb: ; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L0$pb), ; LINUX: movl dst@GOT(%eax), ; LINUX: movl ptr@GOT(%eax), ; LINUX: movl src@GOT(%eax), @@ -26,18 +26,18 @@ entry: @dst2 = global i32 0 @src2 = global i32 0 -define void @test2() nounwind { +define void @test1() nounwind { entry: store i32* @dst2, i32** @ptr2 %tmp.s = load i32* @src2 store i32 %tmp.s, i32* @dst2 ret void -; LINUX: test2: -; LINUX: call .L2$pb -; LINUX-NEXT: .L2$pb: +; LINUX: test1: +; LINUX: call .L1$pb +; LINUX-NEXT: .L1$pb: ; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %eax +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), %eax ; LINUX: movl dst2@GOT(%eax), ; LINUX: movl ptr2@GOT(%eax), ; LINUX: movl src2@GOT(%eax), @@ -47,17 +47,17 @@ entry: declare i8* @malloc(i32) -define void @test3() nounwind { +define void @test2() nounwind { entry: %ptr = call i8* @malloc(i32 40) ret void -; LINUX: test3: +; LINUX: test2: ; LINUX: pushl %ebx ; LINUX-NEXT: subl $8, %esp -; LINUX-NEXT: call .L3$pb -; LINUX-NEXT: .L3$pb: +; LINUX-NEXT: call .L2$pb +; LINUX-NEXT: .L2$pb: ; LINUX-NEXT: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %ebx +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %ebx ; LINUX: movl $40, (%esp) ; LINUX: call malloc@PLT ; LINUX: addl $8, %esp @@ -67,18 +67,18 @@ entry: @pfoo = external global void(...)* -define void @test4() nounwind { +define void @test3() nounwind { entry: %tmp = call void(...)*(...)* @afoo() store void(...)* %tmp, void(...)** @pfoo %tmp1 = load void(...)** @pfoo call void(...)* %tmp1() ret void -; LINUX: test4: -; LINUX: call .L4$pb -; LINUX-NEXT: .L4$pb: +; LINUX: test3: +; LINUX: call .L3$pb +; LINUX-NEXT: .L3$pb: ; LINUX: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), ; LINUX: movl pfoo@GOT(%esi), ; LINUX: call afoo@PLT ; LINUX: call * @@ -86,14 +86,14 @@ entry: declare void(...)* @afoo(...) -define void @test5() nounwind { +define void @test4() nounwind { entry: call void(...)* @foo() ret void -; LINUX: test5: -; LINUX: call .L5$pb +; LINUX: test4: +; LINUX: call .L4$pb ; LINUX: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %ebx +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx ; LINUX: call foo@PLT } @@ -104,18 +104,18 @@ declare void @foo(...) @dst6 = internal global i32 0 @src6 = internal global i32 0 -define void @test6() nounwind { +define void @test5() nounwind { entry: store i32* @dst6, i32** @ptr6 %tmp.s = load i32* @src6 store i32 %tmp.s, i32* @dst6 ret void -; LINUX: test6: -; LINUX: call .L6$pb -; LINUX-NEXT: .L6$pb: +; LINUX: test5: +; LINUX: call .L5$pb +; LINUX-NEXT: .L5$pb: ; LINUX-NEXT: popl %eax -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), %eax +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %eax ; LINUX: leal dst6@GOTOFF(%eax), %ecx ; LINUX: movl %ecx, ptr6@GOTOFF(%eax) ; LINUX: movl src6@GOTOFF(%eax), %ecx @@ -125,24 +125,24 @@ entry: ;; Test constant pool references. -define double @test7(i32 %a.u) nounwind { +define double @test6(i32 %a.u) nounwind { entry: %tmp = icmp eq i32 %a.u,0 %retval = select i1 %tmp, double 4.561230e+02, double 1.234560e+02 ret double %retval -; LINUX: .LCPI7_0: +; LINUX: .LCPI6_0: -; LINUX: test7: -; LINUX: call .L7$pb -; LINUX: .L7$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), -; LINUX: fldl .LCPI7_0@GOTOFF( +; LINUX: test6: +; LINUX: call .L6$pb +; LINUX: .L6$pb: +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), +; LINUX: fldl .LCPI6_0@GOTOFF( } ;; Test jump table references. -define void @test8(i32 %n.u) nounwind { +define void @test7(i32 %n.u) nounwind { entry: switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ] bb: @@ -185,19 +185,19 @@ bb12: tail call void(...)* @foo6() ret void -; LINUX: test8: -; LINUX: call .L8$pb -; LINUX: .L8$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L8$pb), -; LINUX: addl .LJTI8_0@GOTOFF( +; LINUX: test7: +; LINUX: call .L7$pb +; LINUX: .L7$pb: +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), +; LINUX: addl .LJTI7_0@GOTOFF( ; LINUX: jmpl * -; LINUX: .LJTI8_0: -; LINUX: .long .LBB8_2@GOTOFF -; LINUX: .long .LBB8_8@GOTOFF -; LINUX: .long .LBB8_14@GOTOFF -; LINUX: .long .LBB8_9@GOTOFF -; LINUX: .long .LBB8_10@GOTOFF +; LINUX: .LJTI7_0: +; LINUX: .long .LBB7_2@GOTOFF +; LINUX: .long .LBB7_8@GOTOFF +; LINUX: .long .LBB7_14@GOTOFF +; LINUX: .long .LBB7_9@GOTOFF +; LINUX: .long .LBB7_10@GOTOFF } declare void @foo1(...) diff --git a/test/CodeGen/X86/pic_jumptable.ll b/test/CodeGen/X86/pic_jumptable.ll index b3750c1e8e67..31071bc74a78 100644 --- a/test/CodeGen/X86/pic_jumptable.ll +++ b/test/CodeGen/X86/pic_jumptable.ll @@ -1,13 +1,18 @@ ; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | not grep -F .text -; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | not grep lea -; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | grep add | count 2 +; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep 'lJTI' ; rdar://6971437 +; rdar://7738756 declare void @_Z3bari(i32) define linkonce void @_Z3fooILi1EEvi(i32 %Y) nounwind { entry: +; CHECK: L0$pb +; CHECK-NOT: leal +; CHECK: Ltmp0 = LJTI0_0-L0$pb +; CHECK-NEXT: addl Ltmp0(%eax,%ecx,4) +; CHECK-NEXT: jmpl *%eax %Y_addr = alloca i32 ; <i32*> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store i32 %Y, i32* %Y_addr diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll new file mode 100644 index 000000000000..97cc7b4977cf --- /dev/null +++ b/test/CodeGen/X86/postra-licm.ll @@ -0,0 +1,185 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=X86-32 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=X86-64 + +; MachineLICM should be able to hoist loop invariant reload out of the loop. +; rdar://7233099 + +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } +%struct.epoch_t = type { %struct.trans_t*, %struct.trans_t*, i32, i32, i32, i32, i32 } +%struct.trans_t = type { i32, i32, i32, i8* } + +@.str12 = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1] +@.str19 = external constant [7 x i8], align 1 ; <[7 x i8]*> [#uses=1] +@.str24 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] + +define i32 @t1(i32 %c, i8** nocapture %v) nounwind ssp { +; X86-32: t1: +entry: + br i1 undef, label %bb, label %bb3 + +bb: ; preds = %entry + unreachable + +bb3: ; preds = %entry + br i1 undef, label %bb.i, label %bb.nph41 + +bb.i: ; preds = %bb3 + unreachable + +bb.nph41: ; preds = %bb3 + %0 = call %struct.FILE* @"\01_fopen$UNIX2003"(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str12, i32 0, i32 0)) nounwind ; <%struct.FILE*> [#uses=3] + br i1 undef, label %bb4, label %bb5.preheader + +bb5.preheader: ; preds = %bb.nph41 + br label %bb5 + +bb4: ; preds = %bb.nph41 + unreachable + +bb5: ; preds = %bb5, %bb5.preheader + br i1 undef, label %bb7, label %bb5 + +bb7: ; preds = %bb5 + br i1 undef, label %bb9, label %bb12 + +bb9: ; preds = %bb7 + unreachable + +bb12: ; preds = %bb7 + br i1 undef, label %bb16, label %bb22 + +bb16: ; preds = %bb12 + unreachable + +bb22: ; preds = %bb12 + br label %bb.i1 + +bb.i1: ; preds = %bb.i1, %bb22 + %1 = icmp eq i8 undef, 69 ; <i1> [#uses=1] + br i1 %1, label %imix_test.exit, label %bb.i1 + +imix_test.exit: ; preds = %bb.i1 + br i1 undef, label %bb23, label %bb26.preheader + +bb26.preheader: ; preds = %imix_test.exit + br i1 undef, label %bb28, label %bb30 + +bb23: ; preds = %imix_test.exit + unreachable +; X86-32: %bb26.preheader.bb28_crit_edge +; X86-32: movl -16(%ebp), +; X86-32-NEXT: .align 4 +; X86-32-NEXT: %bb28 + +bb28: ; preds = %bb28, %bb26.preheader + %counter.035 = phi i32 [ %3, %bb28 ], [ 0, %bb26.preheader ] ; <i32> [#uses=2] + %tmp56 = shl i32 %counter.035, 2 ; <i32> [#uses=0] + %2 = call i8* @fgets(i8* undef, i32 50, %struct.FILE* %0) nounwind ; <i8*> [#uses=0] + %3 = add nsw i32 %counter.035, 1 ; <i32> [#uses=1] + %4 = call i32 @feof(%struct.FILE* %0) nounwind ; <i32> [#uses=0] + br label %bb28 + +bb30: ; preds = %bb26.preheader + %5 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([7 x i8]* @.str19, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0] + br i1 undef, label %bb34, label %bb70 + +bb32.loopexit: ; preds = %bb45 + %6 = icmp eq i32 undef, 0 ; <i1> [#uses=1] + %indvar.next55 = add i32 %indvar54, 1 ; <i32> [#uses=1] + br i1 %6, label %bb34, label %bb70 + +bb34: ; preds = %bb32.loopexit, %bb30 + %indvar54 = phi i32 [ %indvar.next55, %bb32.loopexit ], [ 0, %bb30 ] ; <i32> [#uses=3] + br i1 false, label %bb35, label %bb39.preheader + +bb35: ; preds = %bb34 + unreachable + +bb39.preheader: ; preds = %bb34 + %7 = getelementptr inbounds %struct.epoch_t* undef, i32 %indvar54, i32 3 ; <i32*> [#uses=1] + %8 = getelementptr inbounds %struct.epoch_t* undef, i32 %indvar54, i32 2 ; <i32*> [#uses=0] + br i1 false, label %bb42, label %bb45 + +bb42: ; preds = %bb39.preheader + unreachable + +bb45: ; preds = %bb39.preheader + %9 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([4 x i8]* @.str24, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0] + br i1 false, label %bb47, label %bb32.loopexit + +bb47: ; preds = %bb45 + %10 = load i32* %7, align 4 ; <i32> [#uses=0] + unreachable + +bb70: ; preds = %bb32.loopexit, %bb30 + br i1 undef, label %bb78, label %bb76 + +bb76: ; preds = %bb70 + unreachable + +bb78: ; preds = %bb70 + br i1 undef, label %bb83, label %bb79 + +bb79: ; preds = %bb78 + unreachable + +bb83: ; preds = %bb78 + call void @rewind(%struct.FILE* %0) nounwind + unreachable +} + +declare %struct.FILE* @"\01_fopen$UNIX2003"(i8*, i8*) + +declare i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind + +declare void @rewind(%struct.FILE* nocapture) nounwind + +declare i32 @feof(%struct.FILE* nocapture) nounwind + +declare i32 @strcmp(i8* nocapture, i8* nocapture) nounwind readonly + +@map_4_to_16 = external constant [16 x i16], align 32 ; <[16 x i16]*> [#uses=2] + +define void @t2(i8* nocapture %bufp, i8* nocapture %data, i32 %dsize) nounwind ssp { +; X86-64: t2: +entry: + br i1 undef, label %return, label %bb.nph + +bb.nph: ; preds = %entry +; X86-64: movq _map_4_to_16@GOTPCREL(%rip) +; X86-64: .align 4 + %tmp5 = zext i32 undef to i64 ; <i64> [#uses=1] + %tmp6 = add i64 %tmp5, 1 ; <i64> [#uses=1] + %tmp11 = shl i64 undef, 1 ; <i64> [#uses=1] + %tmp14 = mul i64 undef, 3 ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph + %tmp9 = mul i64 undef, undef ; <i64> [#uses=2] + %tmp12 = add i64 %tmp11, %tmp9 ; <i64> [#uses=1] + %scevgep13 = getelementptr i8* %bufp, i64 %tmp12 ; <i8*> [#uses=1] + %tmp15 = add i64 %tmp14, %tmp9 ; <i64> [#uses=1] + %scevgep16 = getelementptr i8* %bufp, i64 %tmp15 ; <i8*> [#uses=1] + %0 = load i8* undef, align 1 ; <i8> [#uses=1] + %1 = zext i8 %0 to i32 ; <i32> [#uses=1] + %2 = getelementptr inbounds [16 x i16]* @map_4_to_16, i64 0, i64 0 ; <i16*> [#uses=1] + %3 = load i16* %2, align 2 ; <i16> [#uses=1] + %4 = trunc i16 %3 to i8 ; <i8> [#uses=1] + store i8 %4, i8* undef, align 1 + %5 = and i32 %1, 15 ; <i32> [#uses=1] + %6 = zext i32 %5 to i64 ; <i64> [#uses=1] + %7 = getelementptr inbounds [16 x i16]* @map_4_to_16, i64 0, i64 %6 ; <i16*> [#uses=1] + %8 = load i16* %7, align 2 ; <i16> [#uses=2] + %9 = lshr i16 %8, 8 ; <i16> [#uses=1] + %10 = trunc i16 %9 to i8 ; <i8> [#uses=1] + store i8 %10, i8* %scevgep13, align 1 + %11 = trunc i16 %8 to i8 ; <i8> [#uses=1] + store i8 %11, i8* %scevgep16, align 1 + %exitcond = icmp eq i64 undef, %tmp6 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/X86/promote-i16.ll b/test/CodeGen/X86/promote-i16.ll new file mode 100644 index 000000000000..101bb29593cc --- /dev/null +++ b/test/CodeGen/X86/promote-i16.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=x86 | FileCheck %s + +define signext i16 @foo(i16 signext %x) nounwind { +entry: +; CHECK: foo: +; CHECK: movzwl 4(%esp), %eax +; CHECK: xorl $21998, %eax +; CHECK: movswl %ax, %eax + %0 = xor i16 %x, 21998 + ret i16 %0 +} diff --git a/test/CodeGen/X86/rot16.ll b/test/CodeGen/X86/rot16.ll index 42ece47b0300..de23dcb78f10 100644 --- a/test/CodeGen/X86/rot16.ll +++ b/test/CodeGen/X86/rot16.ll @@ -1,11 +1,9 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep rol %t | count 3 -; RUN: grep ror %t | count 1 -; RUN: grep shld %t | count 2 -; RUN: grep shrd %t | count 2 +; RUN: llc < %s -march=x86 | FileCheck %s define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: foo: +; CHECK: rolw %cl %0 = shl i16 %x, %z %1 = sub i16 16, %z %2 = lshr i16 %x, %1 @@ -15,6 +13,8 @@ entry: define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: bar: +; CHECK: shldw %cl %0 = shl i16 %y, %z %1 = sub i16 16, %z %2 = lshr i16 %x, %1 @@ -24,6 +24,8 @@ entry: define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: un: +; CHECK: rorw %cl %0 = lshr i16 %x, %z %1 = sub i16 16, %z %2 = shl i16 %x, %1 @@ -33,6 +35,8 @@ entry: define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: bu: +; CHECK: shrdw %0 = lshr i16 %y, %z %1 = sub i16 16, %z %2 = shl i16 %x, %1 @@ -42,6 +46,8 @@ entry: define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xfoo: +; CHECK: rolw $5 %0 = lshr i16 %x, 11 %1 = shl i16 %x, 5 %2 = or i16 %0, %1 @@ -50,6 +56,8 @@ entry: define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xbar: +; CHECK: shldw $5 %0 = shl i16 %y, 5 %1 = lshr i16 %x, 11 %2 = or i16 %0, %1 @@ -58,6 +66,8 @@ entry: define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xun: +; CHECK: rolw $11 %0 = lshr i16 %x, 5 %1 = shl i16 %x, 11 %2 = or i16 %0, %1 @@ -66,6 +76,8 @@ entry: define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xbu: +; CHECK: shldw $11 %0 = lshr i16 %y, 5 %1 = shl i16 %x, 11 %2 = or i16 %0, %1 diff --git a/test/CodeGen/X86/rot32.ll b/test/CodeGen/X86/rot32.ll index 655ed272837a..99602fd64ff5 100644 --- a/test/CodeGen/X86/rot32.ll +++ b/test/CodeGen/X86/rot32.ll @@ -1,11 +1,9 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep rol %t | count 3 -; RUN: grep ror %t | count 1 -; RUN: grep shld %t | count 2 -; RUN: grep shrd %t | count 2 +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: foo: +; CHECK: roll %cl %0 = shl i32 %x, %z %1 = sub i32 32, %z %2 = lshr i32 %x, %1 @@ -15,6 +13,8 @@ entry: define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: bar: +; CHECK: shldl %cl %0 = shl i32 %y, %z %1 = sub i32 32, %z %2 = lshr i32 %x, %1 @@ -24,6 +24,8 @@ entry: define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: un: +; CHECK: rorl %cl %0 = lshr i32 %x, %z %1 = sub i32 32, %z %2 = shl i32 %x, %1 @@ -33,6 +35,8 @@ entry: define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: bu: +; CHECK: shrdl %cl %0 = lshr i32 %y, %z %1 = sub i32 32, %z %2 = shl i32 %x, %1 @@ -42,6 +46,8 @@ entry: define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xfoo: +; CHECK: roll $7 %0 = lshr i32 %x, 25 %1 = shl i32 %x, 7 %2 = or i32 %0, %1 @@ -50,6 +56,8 @@ entry: define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xbar: +; CHECK: shldl $7 %0 = shl i32 %y, 7 %1 = lshr i32 %x, 25 %2 = or i32 %0, %1 @@ -58,6 +66,8 @@ entry: define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xun: +; CHECK: roll $25 %0 = lshr i32 %x, 7 %1 = shl i32 %x, 25 %2 = or i32 %0, %1 @@ -66,6 +76,8 @@ entry: define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xbu: +; CHECK: shldl %0 = lshr i32 %y, 7 %1 = shl i32 %x, 25 %2 = or i32 %0, %1 diff --git a/test/CodeGen/X86/shl_elim.ll b/test/CodeGen/X86/shl_elim.ll index 445889166bd5..0827221875b1 100644 --- a/test/CodeGen/X86/shl_elim.ll +++ b/test/CodeGen/X86/shl_elim.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=x86 | grep {shrl .eax} ; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax} -define i32 @test1(i64 %a) { +define i32 @test1(i64 %a) nounwind { %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] %tmp23 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1] %tmp410 = lshr i32 %tmp23, 9 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/sibcall-2.ll b/test/CodeGen/X86/sibcall-2.ll new file mode 100644 index 000000000000..f8a746563b51 --- /dev/null +++ b/test/CodeGen/X86/sibcall-2.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim | FileCheck %s -check-prefix=32 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s -check-prefix=64 + +; Tail call should not use ebp / rbp after it's popped. Use esp / rsp. + +define void @t1(i8* nocapture %value) nounwind { +entry: +; 32: t1: +; 32: jmpl *4(%esp) + +; 64: t1: +; 64: jmpq *%rdi + %0 = bitcast i8* %value to void ()* + tail call void %0() nounwind + ret void +} + +define void @t2(i32 %a, i8* nocapture %value) nounwind { +entry: +; 32: t2: +; 32: jmpl *8(%esp) + +; 64: t2: +; 64: jmpq *%rsi + %0 = bitcast i8* %value to void ()* + tail call void %0() nounwind + ret void +} + +define void @t3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i8* nocapture %value) nounwind { +entry: +; 32: t3: +; 32: jmpl *28(%esp) + +; 64: t3: +; 64: jmpq *8(%rsp) + %0 = bitcast i8* %value to void ()* + tail call void %0() nounwind + ret void +} + +define void @t4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i8* nocapture %value) nounwind { +entry: +; 32: t4: +; 32: jmpl *32(%esp) + +; 64: t4: +; 64: jmpq *16(%rsp) + %0 = bitcast i8* %value to void ()* + tail call void %0() nounwind + ret void +} diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index 8e52a7cbfe78..4b27f2edb759 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -asm-verbose=false | FileCheck %s -check-prefix=32 -; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s -check-prefix=64 +; RUN: llc < %s -march=x86 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=32 +; RUN: llc < %s -march=x86-64 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=64 define void @t1(i32 %x) nounwind ssp { entry: @@ -313,3 +313,21 @@ entry: } declare void @foo() + +; If caller / callee calling convention mismatch then check if the return +; values are returned in the same registers. +; rdar://7874780 + +define double @t20(double %x) nounwind { +entry: +; 32: t20: +; 32: call {{_?}}foo20 +; 32: fldl (%esp) + +; 64: t20: +; 64: jmp {{_?}}foo20 + %0 = tail call fastcc double @foo20(double %x) nounwind + ret double %0 +} + +declare fastcc double @foo20(double) nounwind diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 01d73736d6c2..031c01e9af7d 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -61,9 +61,9 @@ entry: ; Codegen should hoist and CSE these constants. ; CHECK: vv: -; CHECK: LCPI4_0(%rip), %xmm0 -; CHECK: LCPI4_1(%rip), %xmm1 -; CHECK: LCPI4_2(%rip), %xmm2 +; CHECK: LCPI3_0(%rip), %xmm0 +; CHECK: LCPI3_1(%rip), %xmm1 +; CHECK: LCPI3_2(%rip), %xmm2 ; CHECK: align ; CHECK-NOT: LCPI ; CHECK: ret diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll index a734c05b8686..ef66d1a44a18 100644 --- a/test/CodeGen/X86/sse41.ll +++ b/test/CodeGen/X86/sse41.ll @@ -123,11 +123,11 @@ define float @ext_1(<4 x float> %v) nounwind { ; X32: _ext_1: ; X32: pshufd $3, %xmm0, %xmm0 -; X32: addss LCPI8_0, %xmm0 +; X32: addss LCPI7_0, %xmm0 ; X64: _ext_1: ; X64: pshufd $3, %xmm0, %xmm0 -; X64: addss LCPI8_0(%rip), %xmm0 +; X64: addss LCPI7_0(%rip), %xmm0 } define float @ext_2(<4 x float> %v) nounwind { %s = extractelement <4 x float> %v, i32 3 diff --git a/test/CodeGen/X86/stack-align.ll b/test/CodeGen/X86/stack-align.ll index e971ef70dbd4..271ad1aad0ba 100644 --- a/test/CodeGen/X86/stack-align.ll +++ b/test/CodeGen/X86/stack-align.ll @@ -31,7 +31,7 @@ define <2 x double> @test3(<2 x double> %x, <2 x double> %y) alignstack(32) { entry: ; CHECK: andl{{.*}}$-32, %esp call void @test2() - %A = mul <2 x double> %x, %y + %A = fmul <2 x double> %x, %y ret <2 x double> %A } diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll index 83f56c10bb75..001a54096408 100644 --- a/test/CodeGen/X86/stack-color-with-reg.ll +++ b/test/CodeGen/X86/stack-color-with-reg.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t -; RUN: grep asm-printer %t | grep 156 -; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 4 +; RUN: grep asm-printer %t | grep 166 +; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll new file mode 100644 index 000000000000..b1100fa960c0 --- /dev/null +++ b/test/CodeGen/X86/store-narrow.ll @@ -0,0 +1,127 @@ +; rdar://7860110 +; RUN: llc < %s | FileCheck %s -check-prefix=X64 +; RUN: llc -march=x86 < %s | FileCheck %s -check-prefix=X32 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.2" + +define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -256 ; 0xFFFFFF00 + %C = zext i8 %a1 to i32 + %D = or i32 %C, %B + store i32 %D, i32* %a0, align 4 + ret void + +; X64: test1: +; X64: movb %sil, (%rdi) + +; X32: test1: +; X32: movb 8(%esp), %al +; X32: movb %al, (%{{.*}}) +} + +define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -65281 ; 0xFFFF00FF + %C = zext i8 %a1 to i32 + %CS = shl i32 %C, 8 + %D = or i32 %B, %CS + store i32 %D, i32* %a0, align 4 + ret void +; X64: test2: +; X64: movb %sil, 1(%rdi) + +; X32: test2: +; X32: movb 8(%esp), %al +; X32: movb %al, 1(%{{.*}}) +} + +define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -65536 ; 0xFFFF0000 + %C = zext i16 %a1 to i32 + %D = or i32 %B, %C + store i32 %D, i32* %a0, align 4 + ret void +; X64: test3: +; X64: movw %si, (%rdi) + +; X32: test3: +; X32: movw 8(%esp), %ax +; X32: movw %ax, (%{{.*}}) +} + +define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, 65535 ; 0x0000FFFF + %C = zext i16 %a1 to i32 + %CS = shl i32 %C, 16 + %D = or i32 %B, %CS + store i32 %D, i32* %a0, align 4 + ret void +; X64: test4: +; X64: movw %si, 2(%rdi) + +; X32: test4: +; X32: movzwl 8(%esp), %eax +; X32: movw %ax, 2(%{{.*}}) +} + +define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i64* %a0, align 4 + %B = and i64 %A, -4294901761 ; 0xFFFFFFFF0000FFFF + %C = zext i16 %a1 to i64 + %CS = shl i64 %C, 16 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret void +; X64: test5: +; X64: movw %si, 2(%rdi) + +; X32: test5: +; X32: movzwl 8(%esp), %eax +; X32: movw %ax, 2(%{{.*}}) +} + +define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i64* %a0, align 4 + %B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF + %C = zext i8 %a1 to i64 + %CS = shl i64 %C, 40 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret void +; X64: test6: +; X64: movb %sil, 5(%rdi) + + +; X32: test6: +; X32: movb 8(%esp), %al +; X32: movb %al, 5(%{{.*}}) +} + +define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind { +entry: + %OtherLoad = load i32 *%P2 + %A = load i64* %a0, align 4 + %B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF + %C = zext i8 %a1 to i64 + %CS = shl i64 %C, 40 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret i32 %OtherLoad +; X64: test7: +; X64: movb %sil, 5(%rdi) + + +; X32: test7: +; X32: movb 8(%esp), %cl +; X32: movb %cl, 5(%{{.*}}) +} + diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 7b21e1bd7209..9662ad6cd740 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -110,16 +110,16 @@ altret: ; CHECK: dont_merge_oddly: ; CHECK-NOT: ret ; CHECK: ucomiss %xmm1, %xmm2 -; CHECK-NEXT: jbe .LBB3_3 +; CHECK-NEXT: jbe .LBB2_3 ; CHECK-NEXT: ucomiss %xmm0, %xmm1 -; CHECK-NEXT: ja .LBB3_4 -; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: ja .LBB2_4 +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: .LBB2_3: ; CHECK-NEXT: ucomiss %xmm0, %xmm2 -; CHECK-NEXT: jbe .LBB3_2 -; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: jbe .LBB2_2 +; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: xorb %al, %al ; CHECK-NEXT: ret @@ -153,19 +153,19 @@ bb30: ; an unconditional jump to complete a two-way conditional branch. ; CHECK: c_expand_expr_stmt: -; CHECK: jmp .LBB4_7 -; CHECK-NEXT: .LBB4_12: +; CHECK: jmp .LBB3_7 +; CHECK-NEXT: .LBB3_12: ; CHECK-NEXT: movq 8(%rax), %rax ; CHECK-NEXT: movb 16(%rax), %al ; CHECK-NEXT: cmpb $16, %al -; CHECK-NEXT: je .LBB4_6 +; CHECK-NEXT: je .LBB3_6 ; CHECK-NEXT: cmpb $23, %al -; CHECK-NEXT: je .LBB4_6 -; CHECK-NEXT: jmp .LBB4_15 -; CHECK-NEXT: .LBB4_14: +; CHECK-NEXT: je .LBB3_6 +; CHECK-NEXT: jmp .LBB3_15 +; CHECK-NEXT: .LBB3_14: ; CHECK-NEXT: cmpb $23, %bl -; CHECK-NEXT: jne .LBB4_15 -; CHECK-NEXT: .LBB4_15: +; CHECK-NEXT: jne .LBB3_15 +; CHECK-NEXT: .LBB3_15: %0 = type { %struct.rtx_def* } %struct.lang_decl = type opaque @@ -275,7 +275,7 @@ declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind ; CHECK: foo: ; CHECK: callq func -; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: .LBB4_2: ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: ret @@ -406,3 +406,26 @@ bb12: return: ret void } + +; Tail-merging should merge the two ret instructions since one side +; can fall-through into the ret and the other side has to branch anyway. + +; CHECK: TESTE: +; CHECK: imulq +; CHECK-NEXT: LBB8_2: +; CHECK-NEXT: ret + +define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone { +entry: + %cmp = icmp slt i64 %parami, 1 ; <i1> [#uses=1] + %varx.0 = select i1 %cmp, i64 1, i64 %parami ; <i64> [#uses=1] + %cmp410 = icmp slt i64 %paraml, 1 ; <i1> [#uses=1] + br i1 %cmp410, label %for.end, label %bb.nph + +bb.nph: ; preds = %entry + %tmp15 = mul i64 %paraml, %parami ; <i64> [#uses=1] + ret i64 %tmp15 + +for.end: ; preds = %entry + ret i64 %varx.0 +} diff --git a/test/CodeGen/X86/tls11.ll b/test/CodeGen/X86/tls11.ll index a2c1a1f75deb..514a168c5387 100644 --- a/test/CodeGen/X86/tls11.ll +++ b/test/CodeGen/X86/tls11.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t -; RUN: grep {movw %gs:i@NTPOFF, %ax} %t +; RUN: grep {movzwl %gs:i@NTPOFF, %eax} %t ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2 -; RUN: grep {movw %fs:i@TPOFF, %ax} %t2 +; RUN: grep {movzwl %fs:i@TPOFF, %eax} %t2 @i = thread_local global i16 15 diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll index 47b7896bb8f1..a99af0605b12 100644 --- a/test/CodeGen/X86/unaligned-load.ll +++ b/test/CodeGen/X86/unaligned-load.ll @@ -13,9 +13,7 @@ entry: bb: %String2Loc9 = getelementptr inbounds [31 x i8]* %String2Loc, i64 0, i64 0 call void @llvm.memcpy.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1) -; I386: movsd _.str3+16 -; I386: movsd _.str3+8 -; I386: movsd _.str3 +; I386: call {{_?}}memcpy ; CORE2: movabsq ; CORE2: movabsq @@ -30,8 +28,9 @@ return: declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind -; CORE2: .align 3 +; CORE2: .section +; CORE2: .align 4 ; CORE2-NEXT: _.str1: ; CORE2-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" -; CORE2: .align 3 +; CORE2: .align 4 ; CORE2-NEXT: _.str3: diff --git a/test/CodeGen/X86/vec_shuffle-36.ll b/test/CodeGen/X86/vec_shuffle-36.ll index 1ea37c881e71..8090afc7434d 100644 --- a/test/CodeGen/X86/vec_shuffle-36.ll +++ b/test/CodeGen/X86/vec_shuffle-36.ll @@ -13,4 +13,4 @@ define <8 x i16> @shuf7(<8 x i16> %t0) { ; CHECK: pshufd %tmp10 = shufflevector <8 x i16> %t0, <8 x i16> undef, <8 x i32> < i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 undef, i32 undef > ret <8 x i16> %tmp10 -}
\ No newline at end of file +} diff --git a/test/CodeGen/X86/vec_ss_load_fold.ll b/test/CodeGen/X86/vec_ss_load_fold.ll index c8b2927b71f3..3bd3f7b60b3b 100644 --- a/test/CodeGen/X86/vec_ss_load_fold.ll +++ b/test/CodeGen/X86/vec_ss_load_fold.ll @@ -16,9 +16,9 @@ define i16 @test1(float %f) nounwind { %tmp69 = trunc i32 %tmp.upgrd.1 to i16 ; <i16> [#uses=1] ret i16 %tmp69 ; CHECK: test1: -; CHECK: subss LCPI1_ -; CHECK: mulss LCPI1_ -; CHECK: minss LCPI1_ +; CHECK: subss LCPI0_ +; CHECK: mulss LCPI0_ +; CHECK: minss LCPI0_ } define i16 @test2(float %f) nounwind { @@ -31,9 +31,9 @@ define i16 @test2(float %f) nounwind { %tmp69 = trunc i32 %tmp to i16 ; <i16> [#uses=1] ret i16 %tmp69 ; CHECK: test2: -; CHECK: addss LCPI2_ -; CHECK: mulss LCPI2_ -; CHECK: minss LCPI2_ +; CHECK: addss LCPI1_ +; CHECK: mulss LCPI1_ +; CHECK: minss LCPI1_ } declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll index 658c05143e84..551704c498fa 100644 --- a/test/CodeGen/X86/widen_load-2.ll +++ b/test/CodeGen/X86/widen_load-2.ll @@ -24,10 +24,10 @@ define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { ; CHECK: paddd ; CHECK: pextrd ; CHECK: movq - %a = load %i32vec3* %ap - %b = load %i32vec3* %bp + %a = load %i32vec3* %ap, align 8 + %b = load %i32vec3* %bp, align 8 %x = add %i32vec3 %a, %b - store %i32vec3 %x, %i32vec3* %ret + store %i32vec3 %x, %i32vec3* %ret, align 8 ret void } diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index f270d9d56e21..6c623cb15538 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -80,11 +80,11 @@ bb: bb12: ret i16 %tmp3 ; X64: test5: -; X64: notw [[REG:%[a-z]+]] -; X64: andw {{.*}}[[REG]] +; X64: notl [[REG:%[a-z]+]] +; X64: andl {{.*}}[[REG]] ; X32: test5: -; X32: notw [[REG:%[a-z]+]] -; X32: andw {{.*}}[[REG]] +; X32: notl [[REG:%[a-z]+]] +; X32: andl {{.*}}[[REG]] } define i8 @test6(i8 %a, i8 %b) nounwind { |