vendor/llvm/llvm-r142614

6 files changed, 148 insertions, 2 deletions

diff --git a/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
new file mode 100644
index 000000000000..7d6d7bac3d6e
--- /dev/null
+++ b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+declare void @g()
+declare i8* @llvm.stacksave() nounwind
+declare void @llvm.stackrestore(i8*) nounwind
+
+define void @f(i32** %p, i32 %size) {
+allocas:
+  %0 = call i8* @llvm.stacksave()
+  %a = alloca i32, i32 %size
+  store i32* %a, i32** %p
+  call void @g()
+  call void @llvm.stackrestore(i8* %0)
+  ret void
+}
+; CHECK: f:
+; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1]
+; CHECK: set sp, [[REGISTER]]
+; CHECK extsp 1
+; CHECK bl g
diff --git a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
new file mode 100644
index 000000000000..2076057441e8
--- /dev/null
+++ b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+define void @_Z1fz(...) {
+entry:
+; CHECK: _Z1fz:
+; CHECK: extsp 3
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: ldaw sp, sp[3]
+; CHECK: retsp 0
+  ret void
+}
diff --git a/test/CodeGen/XCore/licm-ldwcp.ll b/test/CodeGen/XCore/licm-ldwcp.ll
new file mode 100644
index 000000000000..4884f70e736b
--- /dev/null
+++ b/test/CodeGen/XCore/licm-ldwcp.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s
+
+; MachineLICM should hoist the LDWCP out of the loop.
+
+; CHECK: f:
+; CHECK-NEXT: ldw [[REG:r[0-9]+]], cp[.LCPI0_0]
+; CHECK-NEXT: .LBB0_1:
+; CHECK-NEXT: stw [[REG]], r0[0]
+; CHECK-NEXT: bu .LBB0_1
+
+define void @f(i32* nocapture %p) noreturn nounwind {
+entry:
+  br label %bb
+
+bb:                                               ; preds = %bb, %entry
+  volatile store i32 525509670, i32* %p, align 4
+  br label %bb
+}
diff --git a/test/CodeGen/XCore/misc-intrinsics.ll b/test/CodeGen/XCore/misc-intrinsics.ll
index f504a2ed7246..6d39d77929a7 100644
--- a/test/CodeGen/XCore/misc-intrinsics.ll
+++ b/test/CodeGen/XCore/misc-intrinsics.ll
@@ -4,6 +4,10 @@
 declare i32 @llvm.xcore.bitrev(i32)
 declare i32 @llvm.xcore.crc32(i32, i32, i32)
 declare %0 @llvm.xcore.crc8(i32, i32, i32)
+declare i32 @llvm.xcore.zext(i32, i32)
+declare i32 @llvm.xcore.sext(i32, i32)
+declare i32 @llvm.xcore.geted()
+declare i32 @llvm.xcore.getet()
 
 define i32 @bitrev(i32 %val) {
 ; CHECK: bitrev:
@@ -25,3 +29,47 @@ define %0 @crc8(i32 %crc, i32 %data, i32 %poly) {
 	%result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly)
 	ret %0 %result
 }
+
+define i32 @zext(i32 %a, i32 %b) {
+; CHECK: zext:
+; CHECK: zext r0, r1
+	%result = call i32 @llvm.xcore.zext(i32 %a, i32 %b)
+	ret i32 %result
+}
+
+define i32 @zexti(i32 %a) {
+; CHECK: zexti:
+; CHECK: zext r0, 4
+	%result = call i32 @llvm.xcore.zext(i32 %a, i32 4)
+	ret i32 %result
+}
+
+define i32 @sext(i32 %a, i32 %b) {
+; CHECK: sext:
+; CHECK: sext r0, r1
+	%result = call i32 @llvm.xcore.sext(i32 %a, i32 %b)
+	ret i32 %result
+}
+
+define i32 @sexti(i32 %a) {
+; CHECK: sexti:
+; CHECK: sext r0, 4
+	%result = call i32 @llvm.xcore.sext(i32 %a, i32 4)
+	ret i32 %result
+}
+
+define i32 @geted() {
+; CHECK: geted:
+; CHECK: get r11, ed
+; CHECK-NEXT: mov r0, r11
+	%result = call i32 @llvm.xcore.geted()
+	ret i32 %result
+}
+
+define i32 @getet() {
+; CHECK: getet:
+; CHECK: get r11, et
+; CHECK-NEXT: mov r0, r11
+	%result = call i32 @llvm.xcore.getet()
+	ret i32 %result
+}
diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll
index bd0492c88ee8..8f00fed160b8 100644
--- a/test/CodeGen/XCore/resources.ll
+++ b/test/CodeGen/XCore/resources.ll
@@ -9,6 +9,8 @@ declare void @llvm.xcore.out.p1i8(i8 addrspace(1)* %r, i32 %value)
 declare void @llvm.xcore.outt.p1i8(i8 addrspace(1)* %r, i32 %value)
 declare void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value)
 declare void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value)
+declare i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r)
+declare i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r)
 declare void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value)
 declare void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value)
 declare i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value)
@@ -18,10 +20,13 @@ declare i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r)
 declare void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r)
 declare void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value)
 declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p)
+declare void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p)
 declare void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r)
 declare void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b)
 declare void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b)
 declare void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value)
+declare i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
+declare i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
 
 define i8 addrspace(1)* @getr() {
 ; CHECK: getr:
@@ -171,6 +176,14 @@ define void @setv(i8 addrspace(1)* %r, i8* %p) {
 	ret void
 }
 
+define void @setev(i8 addrspace(1)* %r, i8* %p) {
+; CHECK: setev:
+; CHECK: mov r11, r1
+; CHECK-NEXT: setev res[r0], r11
+	call void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p)
+	ret void
+}
+
 define void @eeu(i8 addrspace(1)* %r) {
 ; CHECK: eeu:
 ; CHECK: eeu res[r0]
@@ -198,3 +211,31 @@ define void @setpsc(i8 addrspace(1)* %r, i32 %value) {
 	call void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
+
+define i32 @peek(i8 addrspace(1)* %r) {
+; CHECK: peek:
+; CHECK: peek r0, res[r0]
+	%result = call i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
+	ret i32 %result
+}
+
+define i32 @endin(i8 addrspace(1)* %r) {
+; CHECK: endin:
+; CHECK: endin r0, res[r0]
+	%result = call i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
+	ret i32 %result
+}
+
+define i32 @testct(i8 addrspace(1)* %r) {
+; CHECK: testct:
+; CHECK: testct r0, res[r0]
+	%result = call i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r)
+	ret i32 %result
+}
+
+define i32 @testwct(i8 addrspace(1)* %r) {
+; CHECK: testwct:
+; CHECK: testwct r0, res[r0]
+	%result = call i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r)
+	ret i32 %result
+}
diff --git a/test/CodeGen/XCore/trampoline.ll b/test/CodeGen/XCore/trampoline.ll
index 4e1aba025b2f..6b42134997bf 100644
--- a/test/CodeGen/XCore/trampoline.ll
+++ b/test/CodeGen/XCore/trampoline.ll
@@ -11,7 +11,8 @@ entry:
   %FRAME.0 = alloca %struct.FRAME.f, align 4
   %TRAMP.23.sub = getelementptr inbounds [20 x i8]* %TRAMP.23, i32 0, i32 0
   %FRAME.02 = bitcast %struct.FRAME.f* %FRAME.0 to i8*
-  %tramp = call i8* @llvm.init.trampoline(i8* %TRAMP.23.sub, i8* bitcast (i32 (%struct.FRAME.f*)* @g.1101 to i8*), i8* %FRAME.02)
+  call void @llvm.init.trampoline(i8* %TRAMP.23.sub, i8* bitcast (i32 (%struct.FRAME.f*)* @g.1101 to i8*), i8* %FRAME.02)
+  %tramp = call i8* @llvm.adjust.trampoline(i8* %TRAMP.23.sub)
   %0 = getelementptr inbounds %struct.FRAME.f* %FRAME.0, i32 0, i32 1
   %1 = bitcast i8* %tramp to i32 ()*
   store i32 ()* %1, i32 ()** %0, align 4
@@ -32,6 +33,7 @@ entry:
   ret i32 %1
 }
 
-declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind
+declare void @llvm.init.trampoline(i8*, i8*, i8*) nounwind
+declare i8* @llvm.adjust.trampoline(i8*) nounwind
 
 declare void @h(i32 ()*)