diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-06-03 15:20:36 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-06-03 15:20:36 +0000 |
| commit | d288ef4c1788d3a951a7558c68312c2d320612b1 (patch) | |
| tree | ece909a5200f95f85f0813599a9500620f4d9217 /test/CodeGen | |
| parent | f382538d471e38a9b98f016c4caebd24c8d60b62 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen')
71 files changed, 2382 insertions, 465 deletions
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir index 0557008ceb4f..b3e41c7751c5 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir @@ -10,18 +10,27 @@ entry: ret void } + + declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 + + attributes #1 = { nounwind } + ... --- name: test_constant registers: - { id: 0, class: _ } + - { id: 1, class: _ } body: | bb.0.entry: ; CHECK-LABEL: name: test_constant ; CHECK: %0(s32) = G_CONSTANT i32 5 + ; CHECK: %1(s1) = G_CONSTANT i1 false %0(s32) = G_CONSTANT i32 5 + %1(s1) = G_CONSTANT i1 0 + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1; ... --- diff --git a/test/CodeGen/AMDGPU/basic-branch.ll b/test/CodeGen/AMDGPU/basic-branch.ll index e245e4296df2..d8f9e4f51ff4 100644 --- a/test/CodeGen/AMDGPU/basic-branch.ll +++ b/test/CodeGen/AMDGPU/basic-branch.ll @@ -34,8 +34,6 @@ end: ; GCN: s_cbranch_vccnz [[END:BB[0-9]+_[0-9]+]] ; GCN: buffer_store_dword -; GCNOPT-NEXT: s_waitcnt vmcnt(0) expcnt(0) -; TODO: This waitcnt can be eliminated ; GCN: {{^}}[[END]]: ; GCN: s_endpgm diff --git a/test/CodeGen/AMDGPU/branch-condition-and.ll b/test/CodeGen/AMDGPU/branch-condition-and.ll index 68b77ea3490e..662ea37a2b99 100644 --- a/test/CodeGen/AMDGPU/branch-condition-and.ll +++ b/test/CodeGen/AMDGPU/branch-condition-and.ll @@ -19,9 +19,8 @@ ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %bb4 ; GCN: ds_write_b32 -; GCN: s_waitcnt -; GCN-NEXT: [[BB5]] +; GCN: [[BB5]] ; GCN: s_or_b64 exec, exec ; GCN-NEXT: s_endpgm ; GCN-NEXT: .Lfunc_end diff --git a/test/CodeGen/AMDGPU/branch-relaxation.ll b/test/CodeGen/AMDGPU/branch-relaxation.ll index 263059d4a6ed..d3f835bdf163 100644 --- a/test/CodeGen/AMDGPU/branch-relaxation.ll +++ b/test/CodeGen/AMDGPU/branch-relaxation.ll @@ -223,7 +223,6 @@ bb3: ; GCN-NEXT: [[BB2]]: ; %bb2 ; GCN: v_mov_b32_e32 [[BB2_K:v[0-9]+]], 17 ; GCN: buffer_store_dword [[BB2_K]] -; GCN: s_waitcnt vmcnt(0) ; GCN-NEXT: [[LONG_JUMP1:BB[0-9]+_[0-9]+]]: ; %bb2 ; GCN-NEXT: s_getpc_b64 vcc @@ -393,7 +392,6 @@ bb3: ; GCN-NEXT: ; BB#2: ; %if_uniform ; GCN: buffer_store_dword -; GCN: s_waitcnt vmcnt(0) ; GCN-NEXT: [[ENDIF]]: ; %endif ; GCN-NEXT: s_or_b64 exec, exec, [[MASK]] diff --git a/test/CodeGen/AMDGPU/commute-compares.ll b/test/CodeGen/AMDGPU/commute-compares.ll index 66148a43a271..caba83c50428 100644 --- a/test/CodeGen/AMDGPU/commute-compares.ll +++ b/test/CodeGen/AMDGPU/commute-compares.ll @@ -35,7 +35,7 @@ define amdgpu_kernel void @commute_ne_64_i32(i32 addrspace(1)* %out, i32 addrspa ; FIXME: Why isn't this being folded as a constant? ; GCN-LABEL: {{^}}commute_ne_litk_i32: ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3039 -; GCN: v_cmp_ne_u32_e32 vcc, [[K]], v{{[0-9]+}} +; GCN: v_cmp_ne_u32_e32 vcc, v{{[0-9]+}}, [[K]] define amdgpu_kernel void @commute_ne_litk_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid @@ -99,11 +99,9 @@ define amdgpu_kernel void @commute_ule_63_i32(i32 addrspace(1)* %out, i32 addrsp ret void } -; FIXME: Undo canonicalization to gt (x + 1) since it doesn't use the inline imm - ; GCN-LABEL: {{^}}commute_ule_64_i32: ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x41{{$}} -; GCN: v_cmp_gt_u32_e32 vcc, [[K]], v{{[0-9]+}} +; GCN: v_cmp_lt_u32_e32 vcc, v{{[0-9]+}}, [[K]] define amdgpu_kernel void @commute_ule_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid @@ -702,7 +700,7 @@ define amdgpu_kernel void @commute_uno_2.0_f64(i32 addrspace(1)* %out, double ad ; XGCN: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} -; GCN: v_cmp_eq_u32_e32 vcc, [[FI]], v{{[0-9]+}} +; GCN: v_cmp_eq_u32_e32 vcc, v{{[0-9]+}}, [[FI]] define amdgpu_kernel void @commute_frameindex(i32 addrspace(1)* nocapture %out) #0 { entry: %stack0 = alloca i32 diff --git a/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll index d3e6c11ef908..79d9b1691878 100644 --- a/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll +++ b/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll @@ -37,22 +37,21 @@ ; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}} -; GCN: s_waitcnt vmcnt(0) expcnt(0) ; GCN: mask branch [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: {{^}}BB{{[0-9]+}}_1: ; %if ; GCN: s_mov_b32 m0, -1 ; GCN: ds_read_b32 [[LOAD1:v[0-9]+]] +; GCN: s_waitcnt lgkmcnt(0) ; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload -; GCN: s_waitcnt vmcnt(0) ; Spill val register ; GCN: v_add_i32_e32 [[VAL:v[0-9]+]], vcc, [[LOAD1]], [[RELOAD_LOAD0]] ; GCN: buffer_store_dword [[VAL]], off, s[0:3], s7 offset:[[VAL_OFFSET:[0-9]+]] ; 4-byte Folded Spill -; GCN: s_waitcnt vmcnt(0) ; VMEM: [[ENDIF]]: ; Reload and restore exec mask +; VGPR: s_waitcnt lgkmcnt(0) ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]] ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]] @@ -119,7 +118,6 @@ endif: ; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}} -; GCN: s_waitcnt vmcnt(0) expcnt(0) ; GCN-NEXT: ; mask branch [[END:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execz [[END]] @@ -130,7 +128,6 @@ endif: ; GCN: v_cmp_ne_u32_e32 vcc, ; GCN: s_and_b64 vcc, exec, vcc ; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], s7 offset:[[VAL_SUB_OFFSET:[0-9]+]] ; 4-byte Folded Spill -; GCN: s_waitcnt vmcnt(0) expcnt(0) ; GCN-NEXT: s_cbranch_vccnz [[LOOP]] @@ -197,7 +194,6 @@ end: ; VMEM: buffer_store_dword v[[V_SAVEEXEC_HI]], off, s[0:3], s7 offset:[[SAVEEXEC_HI_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; GCN: s_mov_b64 exec, [[CMP0]] -; GCN: s_waitcnt vmcnt(0) expcnt(0) ; FIXME: It makes no sense to put this skip here ; GCN-NEXT: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]] @@ -235,7 +231,6 @@ end: ; GCN: buffer_store_dword [[FLOW_VAL]], off, s[0:3], s7 offset:[[RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; GCN: s_xor_b64 exec, exec, s{{\[}}[[FLOW_S_RELOAD_SAVEEXEC_LO]]:[[FLOW_S_RELOAD_SAVEEXEC_HI]]{{\]}} -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN-NEXT: s_cbranch_execz [[ENDIF]] @@ -245,14 +240,12 @@ end: ; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], s7 offset:4 ; 4-byte Folded Reload ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]] ; GCN: buffer_store_dword [[ADD]], off, s[0:3], s7 offset:[[RESULT_OFFSET]] ; 4-byte Folded Spill -; GCN: s_waitcnt vmcnt(0) expcnt(0) ; GCN-NEXT: s_branch [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: [[ELSE]]: ; %else ; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], s7 offset:4 ; 4-byte Folded Reload ; GCN: v_subrev_i32_e32 [[SUB:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]] ; GCN: buffer_store_dword [[ADD]], off, s[0:3], s7 offset:[[FLOW_RESULT_OFFSET:[0-9]+]] ; 4-byte Folded Spill -; GCN: s_waitcnt vmcnt(0) expcnt(0) ; GCN-NEXT: s_branch [[FLOW]] ; GCN: [[ENDIF]]: diff --git a/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/test/CodeGen/AMDGPU/indirect-addressing-si.ll index b18ae353ca4c..fab1f8d12253 100644 --- a/test/CodeGen/AMDGPU/indirect-addressing-si.ll +++ b/test/CodeGen/AMDGPU/indirect-addressing-si.ll @@ -120,8 +120,7 @@ entry: ; FIXME: The waitcnt for the argument load can go after the loop ; IDXMODE: s_set_gpr_idx_on 0, src0 ; GCN: s_mov_b64 s{{\[[0-9]+:[0-9]+\]}}, exec -; GCN: s_waitcnt lgkmcnt(0) - +; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]: ; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v{{[0-9]+}} ; MOVREL: s_add_i32 m0, [[READLANE]], 0xfffffe0 @@ -250,8 +249,6 @@ entry: ; GCN-DAG: v_mov_b32_e32 [[VEC_ELT3:v[0-9]+]], 4{{$}} ; GCN: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec -; GCN: s_waitcnt lgkmcnt(0) - ; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]: ; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]] @@ -290,7 +287,6 @@ entry: ; IDXMODE: s_set_gpr_idx_on 0, dst ; GCN: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec -; GCN: s_waitcnt lgkmcnt(0) ; The offset depends on the register that holds the first element of the vector. ; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]] @@ -330,9 +326,9 @@ entry: ; IDXMODE: s_set_gpr_idx_on 0, src0 ; GCN: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec -; GCN: s_waitcnt vmcnt(0) ; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]: +; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]] ; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]] @@ -411,6 +407,7 @@ bb2: ; IDXMODE: s_set_gpr_idx_on 0, dst ; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]: +; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]] ; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]] diff --git a/test/CodeGen/AMDGPU/infinite-loop.ll b/test/CodeGen/AMDGPU/infinite-loop.ll index 73482756b8c8..3caffc342c7e 100644 --- a/test/CodeGen/AMDGPU/infinite-loop.ll +++ b/test/CodeGen/AMDGPU/infinite-loop.ll @@ -4,8 +4,8 @@ ; SI-LABEL: {{^}}infinite_loop: ; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7 ; SI: BB0_1: +; SI: s_waitcnt lgkmcnt(0) ; SI: buffer_store_dword [[REG]] -; SI: s_waitcnt vmcnt(0) expcnt(0) ; SI: s_branch BB0_1 define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) { entry: diff --git a/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll b/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll index 350dd38ef583..1edccff3bf15 100644 --- a/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll +++ b/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll @@ -421,11 +421,10 @@ define amdgpu_kernel void @v_insertelement_v2i16_dynamic_sgpr(<2 x i16> addrspac } ; GCN-LABEL: {{^}}v_insertelement_v2i16_dynamic_vgpr: -; GFX89: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} -; CI: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 ; GCN: flat_load_dword [[IDX:v[0-9]+]] ; GCN: flat_load_dword [[VEC:v[0-9]+]] -; GFX89-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 +; GFX89-DAG: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} +; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 ; GFX89-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 16, [[IDX]] ; GFX89-DAG: v_lshlrev_b32_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], [[MASKK]] @@ -449,11 +448,10 @@ define amdgpu_kernel void @v_insertelement_v2i16_dynamic_vgpr(<2 x i16> addrspac } ; GCN-LABEL: {{^}}v_insertelement_v2f16_dynamic_vgpr: -; GFX89: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} -; CI: v_mov_b32_e32 [[K:v[0-9]+]], 0x1234 ; GCN: flat_load_dword [[IDX:v[0-9]+]] ; GCN: flat_load_dword [[VEC:v[0-9]+]] -; GFX89-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1234 +; GFX89-DAG: s_mov_b32 [[MASKK:s[0-9]+]], 0xffff{{$}} +; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1234 ; GFX89-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 16, [[IDX]] ; GFX89-DAG: v_lshlrev_b32_e64 [[MASK:v[0-9]+]], [[SCALED_IDX]], [[MASKK]] diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll index 555a1d23ebe9..e50455f6f9a1 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll @@ -58,7 +58,7 @@ main_body: ; ;CHECK-LABEL: {{^}}buffer_store_wait: ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen -;CHECK: s_waitcnt vmcnt(0) expcnt(0) +;CHECK: s_waitcnt expcnt(0) ;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen ;CHECK: s_waitcnt vmcnt(0) ;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll index 5ae255c7a26c..81597516d5f2 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll @@ -58,7 +58,7 @@ main_body: ; ;CHECK-LABEL: {{^}}buffer_store_wait: ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen -;CHECK: s_waitcnt vmcnt(0) expcnt(0) +;CHECK: s_waitcnt expcnt(0) ;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen ;CHECK: s_waitcnt vmcnt(0) ;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll index 02642142ae2c..d97644262016 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll @@ -5,7 +5,6 @@ declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0 ; FUNC-LABEL: {{^}}ds_swizzle: ; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:swizzle(BITMASK_PERM,"00p11") -; CHECK: s_waitcnt lgkmcnt define amdgpu_kernel void @ds_swizzle(i32 addrspace(1)* %out, i32 %src) nounwind { %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0 store i32 %swizzle, i32 addrspace(1)* %out, align 4 diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll index c74c0fa15855..a289f7b0cfb1 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll @@ -130,7 +130,7 @@ main_body: ; ; GCN-LABEL: {{^}}image_store_wait: ; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm -; GCN: s_waitcnt vmcnt(0) expcnt(0) +; GCN: s_waitcnt expcnt(0) ; GCN: image_load v[0:3], v4, s[8:15] dmask:0xf unorm ; GCN: s_waitcnt vmcnt(0) ; GCN: image_store v[0:3], v4, s[16:23] dmask:0xf unorm diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll index 055dddbfa8af..9a27809f37bb 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll @@ -2,6 +2,8 @@ ; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s +; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s +; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s ; ALL-LABEL: {{^}}test: ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1 diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll index ef9cda142850..3d815cca5be2 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll @@ -1,10 +1,13 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=NOAUTO %s +; RUN: llc -march=amdgcn -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX8 -check-prefix=AUTO %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=NOAUTO %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=AUTO %s ; GCN-LABEL: {{^}}test_barrier: ; GFX8: buffer_store_dword ; GFX9: flat_store_dword -; GCN: s_waitcnt +; NOAUTO: s_waitcnt +; AUTO-NOT: s_waitcnt ; GCN: s_barrier define amdgpu_kernel void @test_barrier(i32 addrspace(1)* %out, i32 %size) #0 { entry: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll index b488565c6b3a..224b2ed72e3b 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll @@ -20,7 +20,7 @@ define amdgpu_kernel void @test_s_dcache_inv() #0 { ; GCN: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_inv_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.inv() - call void @llvm.amdgcn.s.waitcnt(i32 0) + call void @llvm.amdgcn.s.waitcnt(i32 127) br label %end end: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll index a3a5c329f411..f96d5db5794a 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll @@ -20,7 +20,7 @@ define amdgpu_kernel void @test_s_dcache_inv_vol() #0 { ; GCN: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_inv_vol_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.inv.vol() - call void @llvm.amdgcn.s.waitcnt(i32 0) + call void @llvm.amdgcn.s.waitcnt(i32 127) br label %end end: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll index 909a85dda3e8..99b651350439 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll @@ -18,7 +18,7 @@ define amdgpu_kernel void @test_s_dcache_wb() #0 { ; VI: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_wb_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.wb() - call void @llvm.amdgcn.s.waitcnt(i32 0) + call void @llvm.amdgcn.s.waitcnt(i32 127) br label %end end: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll index 217bf97c41a4..844fcecdb48b 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll @@ -18,7 +18,7 @@ define amdgpu_kernel void @test_s_dcache_wb_vol() #0 { ; VI: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_wb_vol_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.wb.vol() - call void @llvm.amdgcn.s.waitcnt(i32 0) + call void @llvm.amdgcn.s.waitcnt(i32 127) br label %end end: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll index 6083ec885a86..ee58d359a935 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll @@ -18,8 +18,8 @@ define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <4 x float> %d0, <4 x float> ; ; CHECK-LABEL: {{^}}test2: ; CHECK: image_load -; CHECK-NOT: s_waitcnt vmcnt(0){{$}} -; CHECK: s_waitcnt +; CHECK-NEXT: s_waitcnt +; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: image_store define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, i32 %c) { %t = call <4 x float> @llvm.amdgcn.image.load.v4f32.i32.v8i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) diff --git a/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll b/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll index 9d0b6b395996..82c27f204a47 100644 --- a/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll +++ b/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll @@ -362,6 +362,7 @@ exit1: ; preds = %LeafBlock, %LeafBlock1 ; GCN: {{^BB[0-9]+_[0-9]+}}: ; %UnifiedReturnBlock ; GCN-NEXT: s_or_b64 exec, exec +; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ; return define amdgpu_ps float @uniform_branch_to_multi_divergent_region_exit_ret_ret_return_value(i32 inreg %sgpr, i32 %vgpr) #0 { diff --git a/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll b/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll new file mode 100644 index 000000000000..bced3c408c52 --- /dev/null +++ b/test/CodeGen/AMDGPU/not-scalarize-volatile-load.ll @@ -0,0 +1,15 @@ +; RUN: llc -mtriple amdgcn--amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: @volatile_load +; GCN: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0 +; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] +; GCN: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] +; GCN: flat_load_dword v{{[0-9]+}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} + +define amdgpu_kernel void @volatile_load(i32 addrspace(1)* %arg, i32 addrspace(1)* nocapture %arg1) { +bb: + %tmp18 = load volatile i32, i32 addrspace(1)* %arg, align 4 + %tmp26 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 5 + store i32 %tmp18, i32 addrspace(1)* %tmp26, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/ret_jump.ll b/test/CodeGen/AMDGPU/ret_jump.ll index f2fbacbab82e..e7a05d94cdc4 100644 --- a/test/CodeGen/AMDGPU/ret_jump.ll +++ b/test/CodeGen/AMDGPU/ret_jump.ll @@ -65,7 +65,6 @@ ret.bb: ; preds = %else, %main_body ; GCN-NEXT: ; %unreachable.bb ; GCN: ds_write_b32 -; GCN: s_waitcnt ; GCN: ; divergent unreachable ; GCN: ; %ret.bb @@ -73,6 +72,7 @@ ret.bb: ; preds = %else, %main_body ; GCN: ; %UnifiedReturnBlock ; GCN-NEXT: s_or_b64 exec, exec +; GCN-NEXT: s_waitcnt ; GCN-NEXT: ; return ; GCN-NEXT: .Lfunc_end define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <8 x i32>] addrspace(2)* byval %arg2, i32 addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 inreg %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 { diff --git a/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll b/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll index cb010cf15300..5b0d5274d5bc 100644 --- a/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll +++ b/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll @@ -9,7 +9,6 @@ ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %unreachable ; GCN: ds_write_b32 ; GCN: ; divergent unreachable -; GCN: s_waitcnt ; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock ; GCN-NEXT: s_or_b64 exec, exec @@ -38,7 +37,6 @@ ret: ; GCN-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %unreachable ; GCN: ds_write_b32 ; GCN: ; divergent unreachable -; GCN: s_waitcnt ; GCN: [[RETURN]]: ; GCN-NEXT: s_or_b64 exec, exec @@ -66,7 +64,6 @@ unreachable: ; GCN: [[UNREACHABLE]]: ; GCN: ds_write_b32 -; GCN: s_waitcnt define amdgpu_kernel void @uniform_lower_control_flow_unreachable_terminator(i32 %arg0) #0 { bb: %tmp63 = icmp eq i32 %arg0, 32 diff --git a/test/CodeGen/AMDGPU/smrd-vccz-bug.ll b/test/CodeGen/AMDGPU/smrd-vccz-bug.ll index 343211b0219c..333113e8a9b6 100644 --- a/test/CodeGen/AMDGPU/smrd-vccz-bug.ll +++ b/test/CodeGen/AMDGPU/smrd-vccz-bug.ll @@ -5,7 +5,7 @@ ; GCN-FUNC: {{^}}vccz_workaround: ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0 ; GCN: v_cmp_neq_f32_e64 vcc, s{{[0-9]+}}, 0{{$}} -; GCN: s_waitcnt lgkmcnt(0) +; VCCZ-BUG: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VCCZ-BUG: s_mov_b64 vcc, vcc ; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc ; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]] diff --git a/test/CodeGen/AMDGPU/spill-m0.ll b/test/CodeGen/AMDGPU/spill-m0.ll index 8f1aebfe9ceb..7e8fa118c2c2 100644 --- a/test/CodeGen/AMDGPU/spill-m0.ll +++ b/test/CodeGen/AMDGPU/spill-m0.ll @@ -18,13 +18,11 @@ ; TOVMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0 ; TOVMEM-DAG: v_mov_b32_e32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]] ; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4 ; 4-byte Folded Spill -; TOVMEM: s_waitcnt vmcnt(0) ; TOSMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0 ; TOSMEM: s_add_u32 m0, s3, 0x100{{$}} ; TOSMEM-NOT: [[M0_COPY]] ; TOSMEM: s_buffer_store_dword [[M0_COPY]], s{{\[}}[[LO]]:[[HI]]], m0 ; 4-byte Folded Spill -; TOSMEM: s_waitcnt lgkmcnt(0) ; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]] diff --git a/test/CodeGen/AMDGPU/sub.i16.ll b/test/CodeGen/AMDGPU/sub.i16.ll index cf9e714ea6d3..1d407ea9bcda 100644 --- a/test/CodeGen/AMDGPU/sub.i16.ll +++ b/test/CodeGen/AMDGPU/sub.i16.ll @@ -85,9 +85,9 @@ define amdgpu_kernel void @v_test_sub_i16_zext_to_i32(i32 addrspace(1)* %out, i1 ; FIXME: Need to handle non-uniform case for function below (load without gep). ; GCN-LABEL: {{^}}v_test_sub_i16_zext_to_i64: +; VI: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0 ; VI: flat_load_ushort [[A:v[0-9]+]] ; VI: flat_load_ushort [[B:v[0-9]+]] -; VI-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0 ; VI-DAG: v_subrev_u16_e32 v[[ADD:[0-9]+]], [[B]], [[A]] ; VI: buffer_store_dwordx2 v{{\[}}[[ADD]]:[[VZERO]]{{\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}} define amdgpu_kernel void @v_test_sub_i16_zext_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in0, i16 addrspace(1)* %in1) #1 { diff --git a/test/CodeGen/AMDGPU/valu-i1.ll b/test/CodeGen/AMDGPU/valu-i1.ll index 85a8929ebe58..a67f36d0a7e8 100644 --- a/test/CodeGen/AMDGPU/valu-i1.ll +++ b/test/CodeGen/AMDGPU/valu-i1.ll @@ -11,7 +11,6 @@ declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; SI: v_cmp_lt_i32_e32 vcc, 0, ; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc ; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]] -; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: ; mask branch [[FLOW_BB:BB[0-9]+_[0-9]+]] ; SI-NEXT: s_cbranch_execz [[FLOW_BB]] @@ -72,7 +71,6 @@ end: ; SI-NEXT: BB{{[0-9]+_[0-9]+}}: ; SI: buffer_store_dword -; SI-NEXT: s_waitcnt ; SI-NEXT: {{^}}[[EXIT]]: ; SI: s_or_b64 exec, exec, [[BR_SREG]] @@ -101,7 +99,6 @@ exit: ; SI-NEXT: BB{{[0-9]+_[0-9]+}}: ; SI: buffer_store_dword -; SI-NEXT: s_waitcnt ; SI-NEXT: {{^}}[[EXIT]]: ; SI: s_or_b64 exec, exec, [[BR_SREG]] @@ -132,7 +129,6 @@ exit: ; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %exit ; SI: ds_write_b32 -; SI: s_waitcnt ; SI-NEXT: {{^}}[[FLOW]]: ; SI-NEXT: s_or_saveexec_b64 @@ -140,8 +136,8 @@ exit: ; SI-NEXT: ; mask branch [[UNIFIED_RETURN:BB[0-9]+_[0-9]+]] ; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %then -; SI: buffer_store_dword -; SI-NEXT: s_waitcnt +; SI: s_waitcnt +; SI-NEXT: buffer_store_dword ; SI-NEXT: {{^}}[[UNIFIED_RETURN]]: ; %UnifiedReturnBlock ; SI: s_or_b64 exec, exec diff --git a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll index f4aba880ff76..1c7769894a27 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -974,6 +974,68 @@ entry: ret [2 x i32*] %r } +declare arm_aapcscc {i32, i32} @structs_target({i32, i32}, {i32*, float, i32, double}) + +define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x, {i32*, float, i32, double} %y) { +; CHECK-LABEL: test_structs +; CHECK: fixedStack: +; CHECK-DAG: id: [[Y2_ID:[0-9]+]], offset: 0, size: 4 +; CHECK-DAG: id: [[Y3_ID:[0-9]+]], offset: 8, size: 8 +; CHECK: liveins: %r0, %r1, %r2, %r3 +; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 +; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 +; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 +; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 +; CHECK: [[Y2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Y2_ID]] +; CHECK: [[Y2:%[0-9]+]](s32) = G_LOAD [[Y2_ADDR]](p0){{.*}}load 4 +; CHECK: [[Y3_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Y3_ID]] +; CHECK: [[Y3:%[0-9]+]](s64) = G_LOAD [[Y3_ADDR]](p0){{.*}}load 8 +; CHECK: [[X_0:%[0-9]+]](s64) = IMPLICIT_DEF +; CHECK: [[X_1:%[0-9]+]](s64) = G_INSERT [[X_0]], [[X0]](s32), 0 +; CHECK: [[X_2:%[0-9]+]](s64) = G_INSERT [[X_1]], [[X1]](s32), 32 +; CHECK: [[X:%[0-9]+]](s64) = COPY [[X_2]] +; CHECK: [[Y_0:%[0-9]+]](s192) = IMPLICIT_DEF +; CHECK: [[Y_1:%[0-9]+]](s192) = G_INSERT [[Y_0]], [[Y0]](s32), 0 +; CHECK: [[Y_2:%[0-9]+]](s192) = G_INSERT [[Y_1]], [[Y1]](s32), 32 +; CHECK: [[Y_3:%[0-9]+]](s192) = G_INSERT [[Y_2]], [[Y2]](s32), 64 +; CHECK: [[Y_4:%[0-9]+]](s192) = G_INSERT [[Y_3]], [[Y3]](s64), 128 +; CHECK: [[Y:%[0-9]+]](s192) = COPY [[Y_4]] +; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[X0:%[0-9]+]](s32) = G_EXTRACT [[X]](s64), 0 +; CHECK: [[X1:%[0-9]+]](s32) = G_EXTRACT [[X]](s64), 32 +; CHECK: [[Y0:%[0-9]+]](s32) = G_EXTRACT [[Y]](s192), 0 +; CHECK: [[Y1:%[0-9]+]](s32) = G_EXTRACT [[Y]](s192), 32 +; CHECK: [[Y2:%[0-9]+]](s32) = G_EXTRACT [[Y]](s192), 64 +; CHECK: [[Y3:%[0-9]+]](s64) = G_EXTRACT [[Y]](s192), 128 +; CHECK-DAG: %r0 = COPY [[X0]](s32) +; CHECK-DAG: %r1 = COPY [[X1]](s32) +; CHECK-DAG: %r2 = COPY [[Y0]](s32) +; CHECK-DAG: %r3 = COPY [[Y1]](s32) +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[Y2_OFF:%[0-9]+]](s32) = G_CONSTANT i32 0 +; CHECK: [[Y2_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Y2_OFF]](s32) +; CHECK: G_STORE [[Y2]](s32), [[Y2_ADDR]](p0){{.*}}store 4 +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[Y3_OFF:%[0-9]+]](s32) = G_CONSTANT i32 8 +; CHECK: [[Y3_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Y3_OFF]](s32) +; CHECK: G_STORE [[Y3]](s64), [[Y3_ADDR]](p0){{.*}}store 8 +; CHECK: BLX @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 +; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 +; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 +; CHECK: [[R_0:%[0-9]+]](s64) = IMPLICIT_DEF +; CHECK: [[R_1:%[0-9]+]](s64) = G_INSERT [[R_0]], [[R0]](s32), 0 +; CHECK: [[R_2:%[0-9]+]](s64) = G_INSERT [[R_1]], [[R1]](s32), 32 +; CHECK: [[R:%[0-9]+]](s64) = COPY [[R_2]] +; CHECK: ADJCALLSTACKUP 16, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[R]](s64), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[R]](s64), 32 +; CHECK: %r0 = COPY [[R0]](s32) +; CHECK: %r1 = COPY [[R1]](s32) +; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 + %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x, {i32*, float, i32, double} %y) + ret {i32, i32} %r +} + define i32 @test_shufflevector_s32_v2s32(i32 %arg) { ; CHECK-LABEL: name: test_shufflevector_s32_v2s32 ; CHECK: [[ARG:%[0-9]+]](s32) = COPY %r0 diff --git a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll index ef30cb1063f8..34f00aebe1be 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll @@ -54,10 +54,15 @@ define [16 x i32] @test_ret_demotion() { ret [16 x i32] %res } -define void @test_structs({i32, i32} %struct) { -; CHECK: remark: {{.*}} unable to lower arguments: void ({ i32, i32 })* -; CHECK-LABEL: warning: Instruction selection used fallback path for test_structs - ret void +%large.struct = type { i32, i32, i32, i32, i32} ; Doesn't fit in R0-R3 + +declare %large.struct @large_struct_return_target() + +define %large.struct @test_large_struct_return() { +; CHECK: remark: {{.*}} unable to translate instruction: call{{.*}} @large_struct_return_target +; CHECK-LABEL: warning: Instruction selection used fallback path for test_large_struct_return + %r = call %large.struct @large_struct_return_target() + ret %large.struct %r } define void @test_vararg_definition(i32 %a, ...) { diff --git a/test/CodeGen/ARM/cortex-a57-misched-alu.ll b/test/CodeGen/ARM/cortex-a57-misched-alu.ll new file mode 100644 index 000000000000..960ee87532b0 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-alu.ll @@ -0,0 +1,81 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s + +; Check the latency for ALU shifted operand variants. +; +; CHECK: ********** MI Scheduling ********** +; CHECK: foo:BB#0 entry + +; ALU, basic - 1 cyc I0/I1 +; CHECK: EORrr +; CHECK: rdefs left +; CHECK-NEXT: Latency : 1 + +; ALU, shift by immed - 2 cyc M +; CHECK: ADDrsi +; CHECK: rdefs left +; CHECK-NEXT: Latency : 2 + +; ALU, shift by register, unconditional - 2 cyc M +; CHECK: RSBrsr +; CHECK: rdefs left +; CHECK-NEXT: Latency : 2 + +; ALU, shift by register, conditional - 2 cyc I0/I1 +; CHECK: ANDrsr +; CHECK: rdefs left +; CHECK-NEXT: Latency : 2 + +; Checking scheduling units + +; CHECK: ** ScheduleDAGMILive::schedule picking next node +; Skipping COPY +; CHECK: ** ScheduleDAGMILive::schedule picking next node +; CHECK: Scheduling +; CHECK-SAME: ANDrsr +; CHECK: Ready +; CHECK-NEXT: A57UnitI + +; CHECK: ** ScheduleDAGMILive::schedule picking next node +; CHECK: Scheduling +; CHECK-SAME: CMPri +; CHECK: Ready +; CHECK-NEXT: A57UnitI + +; CHECK: ** ScheduleDAGMILive::schedule picking next node +; CHECK: Scheduling +; CHECK-SAME: RSBrsr +; CHECK: Ready +; CHECK-NEXT: A57UnitM + +; CHECK: ** ScheduleDAGMILive::schedule picking next node +; CHECK: Scheduling +; CHECK-SAME: ADDrsi +; CHECK: Ready +; CHECK-NEXT: A57UnitM + +; CHECK: ** ScheduleDAGMILive::schedule picking next node +; CHECK: Scheduling +; CHECK-SAME: EORrr +; CHECK: Ready +; CHECK-NEXT: A57UnitI + + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv8r-arm-none-eabi" + +; Function Attrs: norecurse nounwind readnone +define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 { +entry: + %xor = xor i32 %a, %b + %xor_shl = shl i32 %xor, 2 + %add = add i32 %xor_shl, %d + %add_ashr = ashr i32 %add, %a + %sub = sub i32 %add_ashr, %a + %sub_lshr_pred = lshr i32 %sub, %c + %pred = icmp sgt i32 %a, 4 + %and = and i32 %sub_lshr_pred, %b + %rv = select i1 %pred, i32 %and, i32 %d + ret i32 %rv +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-basic.ll b/test/CodeGen/ARM/cortex-a57-misched-basic.ll new file mode 100644 index 000000000000..2ec50b9d3343 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-basic.ll @@ -0,0 +1,53 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC + +; Check the latency for instructions for both generic and cortex-a57. +; SDIV should be scheduled at the block's begin (20 cyc of independent M unit). +; +; CHECK: ********** MI Scheduling ********** +; CHECK: foo:BB#0 entry + +; GENERIC: SDIV +; GENERIC: Latency : 1 +; GENERIC: EORrr +; GENERIC: Latency : 1 +; GENERIC: LDRi12 +; GENERIC: Latency : 4 +; GENERIC: ADDrr +; GENERIC: Latency : 1 +; GENERIC: SUBrr +; GENERIC: Latency : 1 + +; A57_SCHED: SDIV +; A57_SCHED: Latency : 20 +; A57_SCHED: EORrr +; A57_SCHED: Latency : 1 +; A57_SCHED: LDRi12 +; A57_SCHED: Latency : 4 +; A57_SCHED: ADDrr +; A57_SCHED: Latency : 1 +; A57_SCHED: SUBrr +; A57_SCHED: Latency : 1 + +; CHECK: ** Final schedule for BB#0 *** +; GENERIC: LDRi12 +; GENERIC: SDIV +; A57_SCHED: SDIV +; A57_SCHED: LDRi12 +; CHECK: ********** INTERVALS ********** + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv8r-arm-none-eabi" + +; Function Attrs: norecurse nounwind readnone +define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr #0 { +entry: + %xor = xor i32 %c, %b + %ld = load i32, i32* %d + %add = add nsw i32 %xor, %ld + %div = sdiv i32 %a, %b + %sub = sub i32 %div, %add + ret i32 %sub +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll b/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll new file mode 100644 index 000000000000..d54848a6bcf1 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll @@ -0,0 +1,37 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; + +@a = global i32 0, align 4 +@b = global i32 0, align 4 +@c = global i32 0, align 4 + +; CHECK: ********** MI Scheduling ********** +; We need second, post-ra scheduling to have LDM instruction combined from single-loads +; CHECK: ********** MI Scheduling ********** +; CHECK: LDMIA_UPD +; CHECK: rdefs left +; CHECK-NEXT: Latency : 4 +; CHECK: Successors: +; CHECK: data +; CHECK-SAME: Latency=1 +; CHECK-NEXT: data +; CHECK-SAME: Latency=3 +; CHECK-NEXT: data +; CHECK-SAME: Latency=3 +; CHECK-NEXT: data +; CHECK-SAME: Latency=4 +define i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize { + %1 = load i32, i32* @a, align 4 + %2 = load i32, i32* @b, align 4 + %3 = load i32, i32* @c, align 4 + + %ptr_after = getelementptr i32, i32* @a, i32 3 + + %ptr_val = ptrtoint i32* %ptr_after to i32 + %mul1 = mul i32 %ptr_val, %1 + %mul2 = mul i32 %mul1, %2 + %mul3 = mul i32 %mul2, %3 + ret i32 %mul3 +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-ldm.ll b/test/CodeGen/ARM/cortex-a57-misched-ldm.ll new file mode 100644 index 000000000000..9cb076651f5b --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-ldm.ll @@ -0,0 +1,28 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s + +; CHECK: ********** MI Scheduling ********** +; We need second, post-ra scheduling to have LDM instruction combined from single-loads +; CHECK: ********** MI Scheduling ********** +; CHECK: LDMIA +; CHECK: rdefs left +; CHECK-NEXT: Latency : 3 +; CHECK: Successors: +; CHECK: data +; CHECK-SAME: Latency=3 +; CHECK-NEXT: data +; CHECK-SAME: Latency=3 + +define i32 @foo(i32* %a) nounwind optsize { +entry: + %b = getelementptr i32, i32* %a, i32 1 + %c = getelementptr i32, i32* %a, i32 2 + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %2 = load i32, i32* %c, align 4 + + %mul1 = mul i32 %0, %1 + %mul2 = mul i32 %mul1, %2 + ret i32 %mul2 +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll b/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll new file mode 100644 index 000000000000..774b0a907e39 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll @@ -0,0 +1,36 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc + +; CHECK: ********** MI Scheduling ********** +; We need second, post-ra scheduling to have STM instruction combined from single-stores +; CHECK: ********** MI Scheduling ********** +; CHECK: schedule starting +; CHECK: STMIA_UPD +; CHECK: rdefs left +; CHECK-NEXT: Latency : 2 +; CHECK: Successors +; CHECK: data +; CHECK-SAME: Latency=1 + +define i32 @bar(i32 %v0, i32 %v1, i32 %v2, i32* %addr) { + + %addr.1 = getelementptr i32, i32* %addr, i32 0 + store i32 %v0, i32* %addr.1 + + %addr.2 = getelementptr i32, i32* %addr, i32 1 + store i32 %v1, i32* %addr.2 + + %addr.3 = getelementptr i32, i32* %addr, i32 2 + store i32 %v2, i32* %addr.3 + + %ptr_after = getelementptr i32, i32* %addr, i32 3 + %val = ptrtoint i32* %ptr_after to i32 + + %rv1 = mul i32 %val, %v0 + %rv2 = mul i32 %rv1, %v1 + %rv3 = mul i32 %rv2, %v2 + + ret i32 %rv3 +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-stm.ll b/test/CodeGen/ARM/cortex-a57-misched-stm.ll new file mode 100644 index 000000000000..474f39d84bae --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-stm.ll @@ -0,0 +1,29 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; N=3 STMIB should have latency 2cyc + +; CHECK: ********** MI Scheduling ********** +; We need second, post-ra scheduling to have STM instruction combined from single-stores +; CHECK: ********** MI Scheduling ********** +; CHECK: schedule starting +; CHECK: STMIB +; CHECK: rdefs left +; CHECK-NEXT: Latency : 2 + +define i32 @test_stm(i32 %v0, i32 %v1, i32* %addr) { + + %addr.1 = getelementptr i32, i32* %addr, i32 1 + store i32 %v0, i32* %addr.1 + + %addr.2 = getelementptr i32, i32* %addr, i32 2 + store i32 %v1, i32* %addr.2 + + %addr.3 = getelementptr i32, i32* %addr, i32 3 + %val = ptrtoint i32* %addr to i32 + store i32 %val, i32* %addr.3 + + %rv = add i32 %v0, %v1 + + ret i32 %rv +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-vfma.ll b/test/CodeGen/ARM/cortex-a57-misched-vfma.ll new file mode 100644 index 000000000000..a9223e1e2a99 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-vfma.ll @@ -0,0 +1,77 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; Check latencies of vmul/vfma accumulate chains. + +define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) { +; CHECK: ********** MI Scheduling ********** +; CHECK: Test1:BB#0 + +; CHECK: VMULS +; > VMULS common latency = 5 +; CHECK: Latency : 5 +; CHECK: Successors: +; CHECK: data +; > VMULS read-advanced latency to VMLAS = 0 +; CHECK-SAME: Latency=0 + +; CHECK: VMLAS +; > VMLAS common latency = 9 +; CHECK: Latency : 9 +; CHECK: Successors: +; CHECK: data +; > VMLAS read-advanced latency to the next VMLAS = 4 +; CHECK-SAME: Latency=4 + +; CHECK: VMLAS +; CHECK: Latency : 9 +; CHECK: Successors: +; CHECK: data +; > VMLAS not-optimized latency to VMOVRS = 9 +; CHECK-SAME: Latency=9 + +; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS + %mul1 = fmul float %f1, %f2 + %mul2 = fmul float %f3, %f4 + %mul3 = fmul float %f5, %f6 + %add1 = fadd float %mul1, %mul2 + %add2 = fadd float %add1, %mul3 + ret float %add2 +} + +; ASIMD form +define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) { +; CHECK: ********** MI Scheduling ********** +; CHECK: Test2:BB#0 + +; CHECK: VMULfd +; > VMULfd common latency = 5 +; CHECK: Latency : 5 +; CHECK: Successors: +; CHECK: data +; VMULfd read-advanced latency to VMLAfd = 0 +; CHECK-SAME: Latency=0 + +; CHECK: VMLAfd +; > VMLAfd common latency = 9 +; CHECK: Latency : 9 +; CHECK: Successors: +; CHECK: data +; > VMLAfd read-advanced latency to the next VMLAfd = 4 +; CHECK-SAME: Latency=4 + +; CHECK: VMLAfd +; CHECK: Latency : 9 +; CHECK: Successors: +; CHECK: data +; > VMLAfd not-optimized latency to VMOVRRD = 9 +; CHECK-SAME: Latency=9 + +; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS + %mul1 = fmul <2 x float> %f1, %f2 + %mul2 = fmul <2 x float> %f3, %f4 + %mul3 = fmul <2 x float> %f5, %f6 + %add1 = fadd <2 x float> %mul1, %mul2 + %add2 = fadd <2 x float> %add1, %mul3 + ret <2 x float> %add2 +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll b/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll new file mode 100644 index 000000000000..6cfa823fb969 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll @@ -0,0 +1,50 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; + +@a = global double 0.0, align 4 +@b = global double 0.0, align 4 +@c = global double 0.0, align 4 + +; CHECK: ********** MI Scheduling ********** +; We need second, post-ra scheduling to have VLDM instruction combined from single-loads +; CHECK: ********** MI Scheduling ********** +; CHECK: VLDMDIA_UPD +; CHECK: rdefs left +; CHECK-NEXT: Latency : 6 +; CHECK: Successors: +; CHECK: data +; CHECK-SAME: Latency=1 +; CHECK-NEXT: data +; CHECK-SAME: Latency=1 +; CHECK-NEXT: data +; CHECK-SAME: Latency=5 +; CHECK-NEXT: data +; CHECK-SAME: Latency=5 +; CHECK-NEXT: data +; CHECK-SAME: Latency=6 +define i32 @bar(i32* %iptr) minsize optsize { + %1 = load double, double* @a, align 8 + %2 = load double, double* @b, align 8 + %3 = load double, double* @c, align 8 + + %ptr_after = getelementptr double, double* @a, i32 3 + + %ptr_new_ival = ptrtoint double* %ptr_after to i32 + %ptr_new = inttoptr i32 %ptr_new_ival to i32* + + store i32 %ptr_new_ival, i32* %iptr, align 8 + + %v1 = fptoui double %1 to i32 + + %mul1 = mul i32 %ptr_new_ival, %v1 + + %v2 = fptoui double %2 to i32 + %v3 = fptoui double %3 to i32 + + %mul2 = mul i32 %mul1, %v2 + %mul3 = mul i32 %mul2, %v3 + + ret i32 %mul3 +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-vldm.ll b/test/CodeGen/ARM/cortex-a57-misched-vldm.ll new file mode 100644 index 000000000000..218b5b41a7e4 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-vldm.ll @@ -0,0 +1,30 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s + +; CHECK: ********** MI Scheduling ********** +; We need second, post-ra scheduling to have VLDM instruction combined from single-loads +; CHECK: ********** MI Scheduling ********** +; CHECK: VLDMDIA +; CHECK: rdefs left +; CHECK-NEXT: Latency : 6 +; CHECK: Successors: +; CHECK: data +; CHECK-SAME: Latency=5 +; CHECK-NEXT: data +; CHECK-SAME: Latency=5 +; CHECK-NEXT: data +; CHECK-SAME: Latency=6 + +define double @foo(double* %a) nounwind optsize { +entry: + %b = getelementptr double, double* %a, i32 1 + %c = getelementptr double, double* %a, i32 2 + %0 = load double, double* %a, align 4 + %1 = load double, double* %b, align 4 + %2 = load double, double* %c, align 4 + + %mul1 = fmul double %0, %1 + %mul2 = fmul double %mul1, %2 + ret double %mul2 +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll b/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll new file mode 100644 index 000000000000..af1c469d4443 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll @@ -0,0 +1,43 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s + +; CHECK: ********** MI Scheduling ********** +; We need second, post-ra scheduling to have VSTM instruction combined from single-stores +; CHECK: ********** MI Scheduling ********** +; CHECK: schedule starting +; CHECK: VSTMDIA_UPD +; CHECK: rdefs left +; CHECK-NEXT: Latency : 4 +; CHECK: Successors: +; CHECK: data +; CHECK-SAME: Latency=1 + +@a = global double 0.0, align 4 +@b = global double 0.0, align 4 +@c = global double 0.0, align 4 + +define i32 @bar(double* %vptr, i32 %iv1, i32* %iptr) minsize { + + %vp2 = getelementptr double, double* %vptr, i32 1 + %vp3 = getelementptr double, double* %vptr, i32 2 + + %v1 = load double, double* %vptr, align 8 + %v2 = load double, double* %vp2, align 8 + %v3 = load double, double* %vp3, align 8 + + store double %v1, double* @a, align 8 + store double %v2, double* @b, align 8 + store double %v3, double* @c, align 8 + + %ptr_after = getelementptr double, double* @a, i32 3 + + %ptr_new_ival = ptrtoint double* %ptr_after to i32 + %ptr_new = inttoptr i32 %ptr_new_ival to i32* + + store i32 %ptr_new_ival, i32* %iptr, align 8 + + %mul1 = mul i32 %ptr_new_ival, %iv1 + + ret i32 %mul1 +} + diff --git a/test/CodeGen/ARM/cortex-a57-misched-vstm.ll b/test/CodeGen/ARM/cortex-a57-misched-vstm.ll new file mode 100644 index 000000000000..f31474f66558 --- /dev/null +++ b/test/CodeGen/ARM/cortex-a57-misched-vstm.ll @@ -0,0 +1,23 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s + +; CHECK: ********** MI Scheduling ********** +; We need second, post-ra scheduling to have VSTM instruction combined from single-stores +; CHECK: ********** MI Scheduling ********** +; CHECK: schedule starting +; CHECK: VSTMDIA +; CHECK: rdefs left +; CHECK-NEXT: Latency : 2 + +%bigVec = type [2 x double] + +@var = global %bigVec zeroinitializer + +define void @bar(%bigVec* %ptr) { + + %tmp = load %bigVec, %bigVec* %ptr + store %bigVec %tmp, %bigVec* @var + + ret void +} + diff --git a/test/CodeGen/ARM/global-merge-external.ll b/test/CodeGen/ARM/global-merge-external.ll index a9e0d199705a..03c977614320 100644 --- a/test/CodeGen/ARM/global-merge-external.ll +++ b/test/CodeGen/ARM/global-merge-external.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -mtriple=arm-eabi -arm-global-merge -global-merge-on-external=true | FileCheck %s --check-prefix=CHECK-MERGE ; RUN: llc < %s -mtriple=arm-eabi -arm-global-merge -global-merge-on-external=false | FileCheck %s --check-prefix=CHECK-NO-MERGE ; RUN: llc < %s -mtriple=arm-macho -arm-global-merge | FileCheck %s --check-prefix=CHECK-NO-MERGE +; RUN: llc < %s -mtriple=arm-eabi -arm-global-merge -relocation-model=pic | FileCheck %s --check-prefix=CHECK-NO-MERGE @x = global i32 0, align 4 @y = global i32 0, align 4 diff --git a/test/CodeGen/Hexagon/newify-crash.ll b/test/CodeGen/Hexagon/newify-crash.ll new file mode 100644 index 000000000000..705170b13a59 --- /dev/null +++ b/test/CodeGen/Hexagon/newify-crash.ll @@ -0,0 +1,44 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; +; Check that this testcase doesn't crash. +; CHECK: vadd + +target triple = "hexagon" + +define void @fred() #0 { +b0: + br label %b1 + +b1: ; preds = %b7, %b0 + %v2 = phi i32 [ 0, %b0 ], [ %v16, %b7 ] + %v3 = phi <32 x i32> [ undef, %b0 ], [ %v15, %b7 ] + %v4 = icmp slt i32 %v2, undef + br i1 %v4, label %b5, label %b7 + +b5: ; preds = %b1 + %v6 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v3, <32 x i32> undef) + br label %b7 + +b7: ; preds = %b5, %b1 + %v8 = phi <32 x i32> [ %v6, %b5 ], [ %v3, %b1 ] + %v9 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v8, <32 x i32> undef) + %v10 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v9, <32 x i32> undef) + %v11 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v10, <32 x i32> undef) + %v12 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v11, <32 x i32> undef) + %v13 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v12, <32 x i32> zeroinitializer) + %v14 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v13, <32 x i32> undef) + %v15 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> %v14, <32 x i32> undef) + %v16 = add nsw i32 %v2, 8 + %v17 = icmp eq i32 %v16, 64 + br i1 %v17, label %b18, label %b1 + +b18: ; preds = %b7 + tail call void @f0() #0 + ret void +} + +declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1 +declare void @f0() #0 + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/MIR/Generic/runPass.mir b/test/CodeGen/MIR/Generic/runPass.mir index eeef9d526510..33380d4c6bb4 100644 --- a/test/CodeGen/MIR/Generic/runPass.mir +++ b/test/CodeGen/MIR/Generic/runPass.mir @@ -1,4 +1,5 @@ # RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s | FileCheck %s +# RUN: llc -run-pass=regallocbasic -debug-pass=Arguments -o - %s | FileCheck %s # Check that passes are initialized correctly, so that it's possible to # use -run-pass. diff --git a/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll b/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll new file mode 100644 index 000000000000..804ea1e5c438 --- /dev/null +++ b/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s + +define void @f1(i8* %p) { +entry: +; CHECK-LABEL: f1: +; CHECK: lbu16 +; CHECK: sb16 + %0 = load i8, i8* %p, align 4 + %a = zext i8 %0 to i32 + %and = and i32 %a, 1 + %cmp = icmp eq i32 %and, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + store i8 0, i8* %p, align 1 + br label %if.end + +if.end: + ret void +} + +define void @f2(i16* %p) { +entry: +; CHECK-LABEL: f2: +; CHECK: lhu16 +; CHECK: sh16 + %0 = load i16, i16* %p, align 2 + %a = zext i16 %0 to i32 + %and = and i32 %a, 2 + %cmp = icmp eq i32 %and, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + store i16 0, i16* %p, align 2 + br label %if.end + +if.end: + ret void +} + diff --git a/test/CodeGen/PowerPC/scavenging.mir b/test/CodeGen/PowerPC/scavenging.mir new file mode 100644 index 000000000000..8b5c26230bc6 --- /dev/null +++ b/test/CodeGen/PowerPC/scavenging.mir @@ -0,0 +1,149 @@ +# RUN: llc -mtriple=ppc64-- -run-pass scavenger-test -verify-machineinstrs -o - %s | FileCheck %s +--- +# CHECK-LABEL: name: noscav0 +name: noscav0 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK: [[REG0:%r[0-9]+]] = LI 42 + ; CHECK-NEXT: NOP implicit [[REG0]] + %0 : gprc = LI 42 + NOP implicit %0 + + ; CHECK: [[REG1:%r[0-9]+]] = LI 42 + ; CHECK-NEXT: NOP + ; CHECK-NEXT: NOP implicit [[REG1]] + ; CHECK-NEXT: NOP + ; CHECK-NEXT: NOP implicit [[REG1]] + %1 : gprc = LI 42 + NOP + NOP implicit %1 + NOP + NOP implicit %1 + + ; CHECK: [[REG2:%r[0-9]+]] = LI 42 + ; CHECK-NEXT: NOP implicit [[REG2]] + %2 : gprc = LI 42 + NOP implicit %2 + + %x0 = IMPLICIT_DEF + %x1 = IMPLICIT_DEF + %x2 = IMPLICIT_DEF + %x3 = IMPLICIT_DEF + %x4 = IMPLICIT_DEF + %x27 = IMPLICIT_DEF + %x28 = IMPLICIT_DEF + %x29 = IMPLICIT_DEF + %x30 = IMPLICIT_DEF + + ; CHECK-NOT: %x0 = LI 42 + ; CHECK-NOT: %x1 = LI 42 + ; CHECK-NOT: %x2 = LI 42 + ; CHECK-NOT: %x3 = LI 42 + ; CHECK-NOT: %x4 = LI 42 + ; CHECK-NOT: %x5 = LI 42 + ; CHECK-NOT: %x27 = LI 42 + ; CHECK-NOT: %x28 = LI 42 + ; CHECK-NOT: %x29 = LI 42 + ; CHECK-NOT: %x30 = LI 42 + ; CHECK: [[REG3:%r[0-9]+]] = LI 42 + ; CHECK-NEXT: %x5 = IMPLICIT_DEF + ; CHECK-NEXT: NOP implicit [[REG2]] + ; CHECK-NEXT: NOP implicit [[REG3]] + %3 : gprc = LI 42 + %x5 = IMPLICIT_DEF + NOP implicit %2 + NOP implicit %3 + + NOP implicit %x0 + NOP implicit %x1 + NOP implicit %x2 + NOP implicit %x3 + NOP implicit %x4 + NOP implicit %x5 + NOP implicit %x27 + NOP implicit %x28 + NOP implicit %x29 + NOP implicit %x30 +... +--- +# CHECK-LABEL: name: scav0 +name: scav0 +tracksRegLiveness: true +stack: + # variable-sized object should be a reason to reserve an emergency spillslot + # in the RegScavenger + - { id: 0, type: variable-sized, offset: -32, alignment: 1 } +body: | + bb.0: + %x0 = IMPLICIT_DEF + %x1 = IMPLICIT_DEF + %x2 = IMPLICIT_DEF + %x3 = IMPLICIT_DEF + %x4 = IMPLICIT_DEF + %x5 = IMPLICIT_DEF + %x6 = IMPLICIT_DEF + %x7 = IMPLICIT_DEF + %x8 = IMPLICIT_DEF + %x9 = IMPLICIT_DEF + %x10 = IMPLICIT_DEF + %x11 = IMPLICIT_DEF + %x12 = IMPLICIT_DEF + %x13 = IMPLICIT_DEF + %x14 = IMPLICIT_DEF + %x15 = IMPLICIT_DEF + %x16 = IMPLICIT_DEF + %x17 = IMPLICIT_DEF + %x18 = IMPLICIT_DEF + %x19 = IMPLICIT_DEF + %x20 = IMPLICIT_DEF + %x21 = IMPLICIT_DEF + %x22 = IMPLICIT_DEF + %x23 = IMPLICIT_DEF + %x24 = IMPLICIT_DEF + %x25 = IMPLICIT_DEF + %x26 = IMPLICIT_DEF + %x27 = IMPLICIT_DEF + %x28 = IMPLICIT_DEF + %x29 = IMPLICIT_DEF + %x30 = IMPLICIT_DEF + + ; CHECK: STD killed [[SPILLEDREG:%x[0-9]+]] + ; CHECK: [[SPILLEDREG]] = LI8 42 + ; CHECK: NOP implicit [[SPILLEDREG]] + ; CHECK: [[SPILLEDREG]] = LD + %0 : g8rc = LI8 42 + NOP implicit %0 + + NOP implicit %x0 + NOP implicit %x1 + NOP implicit %x2 + NOP implicit %x3 + NOP implicit %x4 + NOP implicit %x5 + NOP implicit %x6 + NOP implicit %x7 + NOP implicit %x8 + NOP implicit %x9 + NOP implicit %x10 + NOP implicit %x11 + NOP implicit %x12 + NOP implicit %x13 + NOP implicit %x14 + NOP implicit %x15 + NOP implicit %x16 + NOP implicit %x17 + NOP implicit %x18 + NOP implicit %x19 + NOP implicit %x20 + NOP implicit %x21 + NOP implicit %x22 + NOP implicit %x23 + NOP implicit %x24 + NOP implicit %x25 + NOP implicit %x26 + NOP implicit %x27 + NOP implicit %x28 + NOP implicit %x29 + NOP implicit %x30 +... diff --git a/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir b/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir new file mode 100644 index 000000000000..2f532f0a5efb --- /dev/null +++ b/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir @@ -0,0 +1,267 @@ +# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -run-pass=regallocbasic %s -o - | FileCheck %s +# This test used to assert in RABasic. The problem was when we split live-ranges, +# we were not updating the LiveRegMatrix properly and the interference calculation +# wouldn't match what the assignment thought it could do. +# In other words, this test case needs to trigger live-range splitting to exercise +# the problem. +# +# PR33057 +--- | + target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" + target triple = "s390x--linux-gnu" + + define void @autogen_SD21418() #0 { + ret void + } + + attributes #0 = { "target-cpu"="z13" } + +... + +# CHECK: name: autogen_SD21418 +# Check that at least one live-range has been split +# CHECK: id: 114, class +--- +name: autogen_SD21418 +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: vr128bit } + - { id: 1, class: vr128bit } + - { id: 2, class: vr128bit } + - { id: 3, class: vr64bit } + - { id: 4, class: gr64bit } + - { id: 5, class: vr128bit } + - { id: 6, class: grx32bit } + - { id: 7, class: vr128bit } + - { id: 8, class: vr128bit } + - { id: 9, class: gr32bit } + - { id: 10, class: gr64bit } + - { id: 11, class: vr128bit } + - { id: 12, class: fp64bit } + - { id: 13, class: vr64bit } + - { id: 14, class: vr64bit } + - { id: 15, class: gr64bit } + - { id: 16, class: gr128bit } + - { id: 17, class: gr64bit } + - { id: 18, class: gr32bit } + - { id: 19, class: gr32bit } + - { id: 20, class: gr128bit } + - { id: 21, class: gr32bit } + - { id: 22, class: gr64bit } + - { id: 23, class: gr32bit } + - { id: 24, class: gr32bit } + - { id: 25, class: gr128bit } + - { id: 26, class: grx32bit } + - { id: 27, class: gr64bit } + - { id: 28, class: gr64bit } + - { id: 29, class: vr128bit } + - { id: 30, class: vr128bit } + - { id: 31, class: gr64bit } + - { id: 32, class: gr32bit } + - { id: 33, class: gr32bit } + - { id: 34, class: gr128bit } + - { id: 35, class: gr32bit } + - { id: 36, class: vr128bit } + - { id: 37, class: gr64bit } + - { id: 38, class: gr32bit } + - { id: 39, class: gr32bit } + - { id: 40, class: gr128bit } + - { id: 41, class: gr32bit } + - { id: 42, class: addr64bit } + - { id: 43, class: grx32bit } + - { id: 44, class: addr64bit } + - { id: 45, class: vr64bit } + - { id: 46, class: vr64bit } + - { id: 47, class: gr32bit } + - { id: 48, class: gr32bit } + - { id: 49, class: grx32bit } + - { id: 50, class: vr64bit } + - { id: 51, class: gr64bit } + - { id: 52, class: grx32bit } + - { id: 53, class: gr32bit } + - { id: 54, class: gr64bit } + - { id: 55, class: grx32bit } + - { id: 56, class: gr32bit } + - { id: 57, class: gr128bit } + - { id: 58, class: gr128bit } + - { id: 59, class: gr32bit } + - { id: 60, class: gr64bit } + - { id: 61, class: grx32bit } + - { id: 62, class: gr32bit } + - { id: 63, class: gr64bit } + - { id: 64, class: grx32bit } + - { id: 65, class: gr32bit } + - { id: 66, class: gr128bit } + - { id: 67, class: gr128bit } + - { id: 68, class: grx32bit } + - { id: 69, class: gr64bit } + - { id: 70, class: gr64bit } + - { id: 71, class: vr128bit } + - { id: 72, class: vr128bit } + - { id: 73, class: gr64bit } + - { id: 74, class: grx32bit } + - { id: 75, class: gr32bit } + - { id: 76, class: gr64bit } + - { id: 77, class: grx32bit } + - { id: 78, class: gr32bit } + - { id: 79, class: gr128bit } + - { id: 80, class: gr128bit } + - { id: 81, class: gr32bit } + - { id: 82, class: vr128bit } + - { id: 83, class: gr64bit } + - { id: 84, class: grx32bit } + - { id: 85, class: gr32bit } + - { id: 86, class: gr64bit } + - { id: 87, class: grx32bit } + - { id: 88, class: gr32bit } + - { id: 89, class: gr128bit } + - { id: 90, class: gr128bit } + - { id: 91, class: gr32bit } + - { id: 92, class: grx32bit } + - { id: 93, class: gr64bit } + - { id: 94, class: gr32bit } + - { id: 95, class: gr32bit } + - { id: 96, class: gr32bit } + - { id: 97, class: gr64bit } + - { id: 98, class: gr64bit } + - { id: 99, class: grx32bit } + - { id: 100, class: grx32bit } + - { id: 101, class: gr128bit } + - { id: 102, class: gr128bit } + - { id: 103, class: gr128bit } + - { id: 104, class: gr64bit } + - { id: 105, class: gr128bit } + - { id: 106, class: gr128bit } + - { id: 107, class: gr64bit } + - { id: 108, class: gr128bit } + - { id: 109, class: gr128bit } + - { id: 110, class: gr64bit } + - { id: 111, class: gr128bit } + - { id: 112, class: gr128bit } + - { id: 113, class: gr64bit } +constants: + - id: 0 + value: double 0xD55960F86F577076 + alignment: 8 +body: | + bb.0: + %11 = VGBM 0 + %43 = LHIMux 0 + %44 = LARL %const.0 + %45 = VL64 %44, 0, _ :: (load 8 from constant-pool) + + bb.1: + ADJCALLSTACKDOWN 0, 0 + %12 = LZDR + %f0d = COPY %12 + CallBRASL $fmod, killed %f0d, undef %f2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def %f0d + ADJCALLSTACKUP 0, 0 + KILL killed %f0d + + bb.2: + %17 = VLGVH %11, _, 0 + %19 = LHR %17.subreg_l32 + undef %20.subreg_l64 = LGHI 0 + %20 = DSGFR %20, %19 + %22 = VLGVH %11, _, 3 + %24 = LHR %22.subreg_l32 + undef %25.subreg_l64 = LGHI 0 + %25 = DSGFR %25, %24 + %31 = VLGVH %11, _, 1 + %33 = LHR %31.subreg_l32 + undef %34.subreg_l64 = LGHI 0 + %34 = DSGFR %34, %33 + %37 = VLGVH %11, _, 2 + %39 = LHR %37.subreg_l32 + undef %40.subreg_l64 = LGHI 0 + %40 = DSGFR %40, %39 + CHIMux %43, 0, implicit-def %cc + BRC 14, 6, %bb.2, implicit killed %cc + J %bb.3 + + bb.3: + WFCDB undef %46, %45, implicit-def %cc + %48 = IPM implicit killed %cc + %48 = AFIMux %48, 268435456, implicit-def dead %cc + %6 = RISBMux undef %6, %48, 31, 159, 35 + WFCDB undef %50, %45, implicit-def %cc + BRC 15, 6, %bb.1, implicit killed %cc + J %bb.4 + + bb.4: + %36 = VLVGP %25.subreg_l64, %25.subreg_l64 + %36 = VLVGH %36, %20.subreg_l32, _, 0 + %36 = VLVGH %36, %34.subreg_l32, _, 1 + dead %36 = VLVGH %36, %40.subreg_l32, _, 2 + %4 = LG undef %42, 0, _ :: (load 8 from `i64* undef`) + undef %57.subreg_h64 = LLILL 0 + undef %66.subreg_h64 = LLILL 0 + undef %79.subreg_h64 = LLILL 0 + undef %89.subreg_h64 = LLILL 0 + %92 = LHIMux 0 + + bb.5: + + bb.6: + %51 = VLGVH undef %7, _, 0 + %53 = LLHRMux %51.subreg_l32 + %54 = VLGVH undef %1, _, 0 + %57.subreg_l32 = LLHRMux %54.subreg_l32 + %58 = COPY %57 + %58 = DLR %58, %53 + %60 = VLGVH undef %7, _, 3 + %62 = LLHRMux %60.subreg_l32 + %63 = VLGVH undef %1, _, 3 + %66.subreg_l32 = LLHRMux %63.subreg_l32 + %67 = COPY %66 + %67 = DLR %67, %62 + %73 = VLGVH undef %7, _, 1 + %75 = LLHRMux %73.subreg_l32 + %76 = VLGVH undef %1, _, 1 + %79.subreg_l32 = LLHRMux %76.subreg_l32 + %80 = COPY %79 + %80 = DLR %80, %75 + %83 = VLGVH undef %7, _, 2 + %85 = LLHRMux %83.subreg_l32 + %86 = VLGVH undef %1, _, 2 + %89.subreg_l32 = LLHRMux %86.subreg_l32 + %90 = COPY %89 + %90 = DLR %90, %85 + CHIMux %92, 0, implicit-def %cc + BRC 14, 6, %bb.7, implicit killed %cc + J %bb.6 + + bb.7: + CGHI undef %93, 0, implicit-def %cc + %96 = IPM implicit killed %cc + CGHI undef %97, 0, implicit-def %cc + BRC 14, 6, %bb.6, implicit killed %cc + + bb.8: + CHIMux %6, 0, implicit-def %cc + %10 = LLILL 41639 + dead %10 = LOCGR %10, %4, 14, 6, implicit killed %cc + CHIMux %92, 0, implicit-def %cc + BRC 14, 6, %bb.5, implicit killed %cc + J %bb.9 + + bb.9: + %82 = VLVGP %67.subreg_h64, %67.subreg_h64 + %82 = VLVGH %82, %58.subreg_hl32, _, 0 + %82 = VLVGH %82, %80.subreg_hl32, _, 1 + dead %82 = VLVGH %82, %90.subreg_hl32, _, 2 + %96 = AFIMux %96, 1879048192, implicit-def dead %cc + %96 = SRL %96, _, 31 + dead %11 = VLVGF %11, %96, _, 1 + %100 = LHIMux 0 + + bb.10: + CHIMux %100, 0, implicit-def %cc + BRC 14, 6, %bb.10, implicit killed %cc + J %bb.11 + + bb.11: + Return + +... diff --git a/test/CodeGen/X86/and-sink.ll b/test/CodeGen/X86/and-sink.ll index 46e50f2a6a74..0f877e778c70 100644 --- a/test/CodeGen/X86/and-sink.ll +++ b/test/CodeGen/X86/and-sink.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=i686-unknown -verify-machineinstrs < %s | FileCheck %s ; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK-CGP %s @@ -8,12 +9,20 @@ ; Test that 'and' is sunk into bb0. define i32 @and_sink1(i32 %a, i1 %c) { ; CHECK-LABEL: and_sink1: -; CHECK: testb $1, -; CHECK: je -; CHECK-NOT: andl $4, -; CHECK: movl $0, A -; CHECK: testb $4, -; CHECK: jne +; CHECK: # BB#0: +; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: # BB#1: # %bb0 +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movl $0, A +; CHECK-NEXT: testb $4, %al +; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: # BB#2: # %bb1 +; CHECK-NEXT: movl $1, %eax +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB0_3: # %bb2 +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retl ; CHECK-CGP-LABEL: @and_sink1( ; CHECK-CGP-NOT: and i32 @@ -37,16 +46,30 @@ bb2: ; Test that both 'and' and cmp get sunk to bb1. define i32 @and_sink2(i32 %a, i1 %c, i1 %c2) { ; CHECK-LABEL: and_sink2: -; CHECK: movl $0, A -; CHECK: testb $1, -; CHECK: je -; CHECK-NOT: andl $4, -; CHECK: movl $0, B -; CHECK: testb $1, -; CHECK: je -; CHECK: movl $0, C -; CHECK: testb $4, -; CHECK: jne +; CHECK: # BB#0: +; CHECK-NEXT: movl $0, A +; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) +; CHECK-NEXT: je .LBB1_5 +; CHECK-NEXT: # BB#1: # %bb0.preheader +; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB1_2: # %bb0 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: movl $0, B +; CHECK-NEXT: testb $1, %al +; CHECK-NEXT: je .LBB1_5 +; CHECK-NEXT: # BB#3: # %bb1 +; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: movl $0, C +; CHECK-NEXT: testb $4, %cl +; CHECK-NEXT: jne .LBB1_2 +; CHECK-NEXT: # BB#4: # %bb2 +; CHECK-NEXT: movl $1, %eax +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB1_5: # %bb3 +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retl ; CHECK-CGP-LABEL: @and_sink2( ; CHECK-CGP-NOT: and i32 @@ -77,12 +100,21 @@ bb3: ; Test that CodeGenPrepare doesn't get stuck in a loop sinking and hoisting a masked load. define i32 @and_sink3(i1 %c, i32* %p) { ; CHECK-LABEL: and_sink3: -; CHECK: testb $1, -; CHECK: je -; CHECK: movzbl -; CHECK-DAG: movl $0, A -; CHECK-DAG: testl % -; CHECK: je +; CHECK: # BB#0: +; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) +; CHECK-NEXT: je .LBB2_3 +; CHECK-NEXT: # BB#1: # %bb0 +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movzbl (%eax), %eax +; CHECK-NEXT: testl %eax, %eax +; CHECK-NEXT: movl $0, A +; CHECK-NEXT: je .LBB2_2 +; CHECK-NEXT: .LBB2_3: # %bb2 +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB2_2: # %bb1 +; CHECK-NEXT: movl $1, %eax +; CHECK-NEXT: retl ; CHECK-CGP-LABEL: @and_sink3( ; CHECK-CGP: load i32 @@ -106,15 +138,26 @@ bb2: ; Test that CodeGenPrepare sinks/duplicates non-immediate 'and'. define i32 @and_sink4(i32 %a, i32 %b, i1 %c) { ; CHECK-LABEL: and_sink4: -; CHECK: testb $1, -; CHECK: je -; CHECK-NOT: andl -; CHECK-DAG: movl $0, A -; CHECK-DAG: testl [[REG1:%[a-z0-9]+]], [[REG2:%[a-z0-9]+]] -; CHECK: jne -; CHECK-DAG: movl {{%[a-z0-9]+}}, B -; CHECK-DAG: testl [[REG1]], [[REG2]] -; CHECK: je +; CHECK: # BB#0: +; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) +; CHECK-NEXT: je .LBB3_4 +; CHECK-NEXT: # BB#1: # %bb0 +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx +; CHECK-NEXT: testl %eax, %ecx +; CHECK-NEXT: movl $0, A +; CHECK-NEXT: jne .LBB3_4 +; CHECK-NEXT: # BB#2: # %bb1 +; CHECK-NEXT: leal (%ecx,%eax), %edx +; CHECK-NEXT: testl %eax, %ecx +; CHECK-NEXT: movl %edx, B +; CHECK-NEXT: je .LBB3_3 +; CHECK-NEXT: .LBB3_4: # %bb3 +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB3_3: # %bb2 +; CHECK-NEXT: movl $1, %eax +; CHECK-NEXT: retl ; CHECK-CGP-LABEL: @and_sink4( ; CHECK-CGP-NOT: and i32 @@ -146,14 +189,26 @@ bb3: ; when it would increase register pressure. define i32 @and_sink5(i32 %a, i32 %b, i32 %a2, i32 %b2, i1 %c) { ; CHECK-LABEL: and_sink5: -; CHECK: testb $1, -; CHECK: je -; CHECK-DAG: andl {{[0-9]+\(%[a-z0-9]+\)}}, [[REG:%[a-z0-9]+]] -; CHECK-DAG: movl $0, A -; CHECK: jne -; CHECK-DAG: movl {{%[a-z0-9]+}}, B -; CHECK-DAG: testl [[REG]], [[REG]] -; CHECK: je +; CHECK: # BB#0: +; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) +; CHECK-NEXT: je .LBB4_4 +; CHECK-NEXT: # BB#1: # %bb0 +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: andl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: movl $0, A +; CHECK-NEXT: jne .LBB4_4 +; CHECK-NEXT: # BB#2: # %bb1 +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx +; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx +; CHECK-NEXT: testl %eax, %eax +; CHECK-NEXT: movl %ecx, B +; CHECK-NEXT: je .LBB4_3 +; CHECK-NEXT: .LBB4_4: # %bb3 +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retl +; CHECK-NEXT: .LBB4_3: # %bb2 +; CHECK-NEXT: movl $1, %eax +; CHECK-NEXT: retl ; CHECK-CGP-LABEL: @and_sink5( ; CHECK-CGP: and i32 diff --git a/test/CodeGen/X86/avx512-cvt.ll b/test/CodeGen/X86/avx512-cvt.ll index 33ac15de9de9..8f6afa8785d0 100644 --- a/test/CodeGen/X86/avx512-cvt.ll +++ b/test/CodeGen/X86/avx512-cvt.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=ALL --check-prefix=NOVL --check-prefix=NODQ --check-prefix=NOVLDQ --check-prefix=KNL -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=DQ --check-prefix=VL --check-prefix=VLDQ --check-prefix=VLBW --check-prefix=SKX -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=NODQ --check-prefix=VL --check-prefix=VLNODQ --check-prefix=VLNOBW --check-prefix=AVX512VL -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=NOVL --check-prefix=DQ --check-prefix=AVX512DQ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=NOVL --check-prefix=NODQ --check-prefix=NOVLDQ --check-prefix=AVX512BW -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx512vl,avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=DQ --check-prefix=VL --check-prefix=VLDQ --check-prefix=VLNOBW --check-prefix=AVX512VLDQ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx512vl,avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=NODQ --check-prefix=VL --check-prefix=VLNODQ --check-prefix=VLBW --check-prefix=AVX512VLBW +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl | FileCheck %s --check-prefix=ALL --check-prefix=NOVL --check-prefix=NODQ --check-prefix=NOVLDQ --check-prefix=KNL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=DQ --check-prefix=VL --check-prefix=VLDQ --check-prefix=VLBW --check-prefix=SKX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=NODQ --check-prefix=VL --check-prefix=VLNODQ --check-prefix=VLNOBW --check-prefix=AVX512VL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=NOVL --check-prefix=DQ --check-prefix=AVX512DQ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=NOVL --check-prefix=NODQ --check-prefix=NOVLDQ --check-prefix=AVX512BW +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512vl,avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=DQ --check-prefix=VL --check-prefix=VLDQ --check-prefix=VLNOBW --check-prefix=AVX512VLDQ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512vl,avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=NODQ --check-prefix=VL --check-prefix=VLNODQ --check-prefix=VLBW --check-prefix=AVX512VLBW define <16 x float> @sitof32(<16 x i32> %a) nounwind { ; ALL-LABEL: sitof32: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvtdq2ps %zmm0, %zmm0 ; ALL-NEXT: retq %b = sitofp <16 x i32> %a to <16 x float> @@ -19,7 +19,7 @@ define <16 x float> @sitof32(<16 x i32> %a) nounwind { define <8 x double> @sltof864(<8 x i64> %a) { ; NODQ-LABEL: sltof864: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NODQ-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 @@ -49,7 +49,7 @@ define <8 x double> @sltof864(<8 x i64> %a) { ; NODQ-NEXT: retq ; ; DQ-LABEL: sltof864: -; DQ: ## BB#0: +; DQ: # BB#0: ; DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 ; DQ-NEXT: retq %b = sitofp <8 x i64> %a to <8 x double> @@ -58,7 +58,7 @@ define <8 x double> @sltof864(<8 x i64> %a) { define <4 x double> @sltof464(<4 x i64> %a) { ; NODQ-LABEL: sltof464: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm1 ; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NODQ-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 @@ -74,15 +74,15 @@ define <4 x double> @sltof464(<4 x i64> %a) { ; NODQ-NEXT: retq ; ; VLDQ-LABEL: sltof464: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vcvtqq2pd %ymm0, %ymm0 ; VLDQ-NEXT: retq ; ; AVX512DQ-LABEL: sltof464: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512DQ-NEXT: retq %b = sitofp <4 x i64> %a to <4 x double> ret <4 x double> %b @@ -90,7 +90,7 @@ define <4 x double> @sltof464(<4 x i64> %a) { define <2 x float> @sltof2f32(<2 x i64> %a) { ; NODQ-LABEL: sltof2f32: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NODQ-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 ; NODQ-NEXT: vmovq %xmm0, %rax @@ -101,15 +101,15 @@ define <2 x float> @sltof2f32(<2 x i64> %a) { ; NODQ-NEXT: retq ; ; VLDQ-LABEL: sltof2f32: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vcvtqq2ps %xmm0, %xmm0 ; VLDQ-NEXT: retq ; ; AVX512DQ-LABEL: sltof2f32: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %b = sitofp <2 x i64> %a to <2 x float> @@ -118,7 +118,7 @@ define <2 x float> @sltof2f32(<2 x i64> %a) { define <4 x float> @sltof4f32_mem(<4 x i64>* %a) { ; KNL-LABEL: sltof4f32_mem: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: vmovdqu (%rdi), %ymm0 ; KNL-NEXT: vpextrq $1, %xmm0, %rax ; KNL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 @@ -135,12 +135,12 @@ define <4 x float> @sltof4f32_mem(<4 x i64>* %a) { ; KNL-NEXT: retq ; ; VLDQ-LABEL: sltof4f32_mem: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vcvtqq2psy (%rdi), %xmm0 ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sltof4f32_mem: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vmovdqu (%rdi), %ymm0 ; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax ; VLNODQ-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 @@ -158,15 +158,15 @@ define <4 x float> @sltof4f32_mem(<4 x i64>* %a) { ; VLNODQ-NEXT: retq ; ; AVX512DQ-LABEL: sltof4f32_mem: -; AVX512DQ: ## BB#0: +; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovups (%rdi), %ymm0 ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: sltof4f32_mem: -; AVX512BW: ## BB#0: +; AVX512BW: # BB#0: ; AVX512BW-NEXT: vmovdqu (%rdi), %ymm0 ; AVX512BW-NEXT: vpextrq $1, %xmm0, %rax ; AVX512BW-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 @@ -189,7 +189,7 @@ define <4 x float> @sltof4f32_mem(<4 x i64>* %a) { define <4 x i64> @f64tosl(<4 x double> %a) { ; NODQ-LABEL: f64tosl: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vextractf128 $1, %ymm0, %xmm1 ; NODQ-NEXT: vcvttsd2si %xmm1, %rax ; NODQ-NEXT: vmovq %rax, %xmm2 @@ -207,15 +207,15 @@ define <4 x i64> @f64tosl(<4 x double> %a) { ; NODQ-NEXT: retq ; ; VLDQ-LABEL: f64tosl: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vcvttpd2qq %ymm0, %ymm0 ; VLDQ-NEXT: retq ; ; AVX512DQ-LABEL: f64tosl: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vcvttpd2qq %zmm0, %zmm0 -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512DQ-NEXT: retq %b = fptosi <4 x double> %a to <4 x i64> ret <4 x i64> %b @@ -223,7 +223,7 @@ define <4 x i64> @f64tosl(<4 x double> %a) { define <4 x i64> @f32tosl(<4 x float> %a) { ; NODQ-LABEL: f32tosl: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[3,1,2,3] ; NODQ-NEXT: vcvttss2si %xmm1, %rax ; NODQ-NEXT: vmovq %rax, %xmm1 @@ -241,15 +241,15 @@ define <4 x i64> @f32tosl(<4 x float> %a) { ; NODQ-NEXT: retq ; ; VLDQ-LABEL: f32tosl: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vcvttps2qq %xmm0, %ymm0 ; VLDQ-NEXT: retq ; ; AVX512DQ-LABEL: f32tosl: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0 -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; AVX512DQ-NEXT: retq %b = fptosi <4 x float> %a to <4 x i64> ret <4 x i64> %b @@ -257,7 +257,7 @@ define <4 x i64> @f32tosl(<4 x float> %a) { define <4 x float> @sltof432(<4 x i64> %a) { ; KNL-LABEL: sltof432: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: vpextrq $1, %xmm0, %rax ; KNL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 ; KNL-NEXT: vmovq %xmm0, %rax @@ -273,13 +273,13 @@ define <4 x float> @sltof432(<4 x i64> %a) { ; KNL-NEXT: retq ; ; VLDQ-LABEL: sltof432: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vcvtqq2ps %ymm0, %xmm0 ; VLDQ-NEXT: vzeroupper ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sltof432: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax ; VLNODQ-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 ; VLNODQ-NEXT: vmovq %xmm0, %rax @@ -296,15 +296,15 @@ define <4 x float> @sltof432(<4 x i64> %a) { ; VLNODQ-NEXT: retq ; ; AVX512DQ-LABEL: sltof432: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: sltof432: -; AVX512BW: ## BB#0: +; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpextrq $1, %xmm0, %rax ; AVX512BW-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 ; AVX512BW-NEXT: vmovq %xmm0, %rax @@ -325,7 +325,7 @@ define <4 x float> @sltof432(<4 x i64> %a) { define <4 x float> @ultof432(<4 x i64> %a) { ; KNL-LABEL: ultof432: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: vpextrq $1, %xmm0, %rax ; KNL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 ; KNL-NEXT: vmovq %xmm0, %rax @@ -341,13 +341,13 @@ define <4 x float> @ultof432(<4 x i64> %a) { ; KNL-NEXT: retq ; ; VLDQ-LABEL: ultof432: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vcvtuqq2ps %ymm0, %xmm0 ; VLDQ-NEXT: vzeroupper ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: ultof432: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax ; VLNODQ-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 ; VLNODQ-NEXT: vmovq %xmm0, %rax @@ -364,15 +364,15 @@ define <4 x float> @ultof432(<4 x i64> %a) { ; VLNODQ-NEXT: retq ; ; AVX512DQ-LABEL: ultof432: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: ultof432: -; AVX512BW: ## BB#0: +; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpextrq $1, %xmm0, %rax ; AVX512BW-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 ; AVX512BW-NEXT: vmovq %xmm0, %rax @@ -393,7 +393,7 @@ define <4 x float> @ultof432(<4 x i64> %a) { define <8 x double> @ultof64(<8 x i64> %a) { ; NODQ-LABEL: ultof64: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NODQ-NEXT: vcvtusi2sdq %rax, %xmm2, %xmm2 @@ -423,7 +423,7 @@ define <8 x double> @ultof64(<8 x i64> %a) { ; NODQ-NEXT: retq ; ; DQ-LABEL: ultof64: -; DQ: ## BB#0: +; DQ: # BB#0: ; DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 ; DQ-NEXT: retq %b = uitofp <8 x i64> %a to <8 x double> @@ -432,7 +432,7 @@ define <8 x double> @ultof64(<8 x i64> %a) { define <16 x i32> @fptosi00(<16 x float> %a) nounwind { ; ALL-LABEL: fptosi00: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvttps2dq %zmm0, %zmm0 ; ALL-NEXT: retq %b = fptosi <16 x float> %a to <16 x i32> @@ -441,7 +441,7 @@ define <16 x i32> @fptosi00(<16 x float> %a) nounwind { define <16 x i32> @fptoui00(<16 x float> %a) nounwind { ; ALL-LABEL: fptoui00: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvttps2udq %zmm0, %zmm0 ; ALL-NEXT: retq %b = fptoui <16 x float> %a to <16 x i32> @@ -450,14 +450,14 @@ define <16 x i32> @fptoui00(<16 x float> %a) nounwind { define <8 x i32> @fptoui_256(<8 x float> %a) nounwind { ; NOVL-LABEL: fptoui_256: -; NOVL: ## BB#0: -; NOVL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL: # BB#0: +; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NOVL-NEXT: vcvttps2udq %zmm0, %zmm0 -; NOVL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; NOVL-NEXT: retq ; ; VL-LABEL: fptoui_256: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vcvttps2udq %ymm0, %ymm0 ; VL-NEXT: retq %b = fptoui <8 x float> %a to <8 x i32> @@ -466,30 +466,30 @@ define <8 x i32> @fptoui_256(<8 x float> %a) nounwind { define <4 x i32> @fptoui_128(<4 x float> %a) nounwind { ; KNL-LABEL: fptoui_128: -; KNL: ## BB#0: -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL: # BB#0: +; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; KNL-NEXT: vcvttps2udq %zmm0, %zmm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> ; KNL-NEXT: retq ; ; VL-LABEL: fptoui_128: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vcvttps2udq %xmm0, %xmm0 ; VL-NEXT: retq ; ; AVX512DQ-LABEL: fptoui_128: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vcvttps2udq %zmm0, %zmm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: fptoui_128: -; AVX512BW: ## BB#0: -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW: # BB#0: +; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; AVX512BW-NEXT: vcvttps2udq %zmm0, %zmm0 -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %b = fptoui <4 x float> %a to <4 x i32> @@ -498,7 +498,7 @@ define <4 x i32> @fptoui_128(<4 x float> %a) nounwind { define <8 x i32> @fptoui01(<8 x double> %a) nounwind { ; ALL-LABEL: fptoui01: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvttpd2udq %zmm0, %ymm0 ; ALL-NEXT: retq %b = fptoui <8 x double> %a to <8 x i32> @@ -507,31 +507,31 @@ define <8 x i32> @fptoui01(<8 x double> %a) nounwind { define <4 x i32> @fptoui_256d(<4 x double> %a) nounwind { ; KNL-LABEL: fptoui_256d: -; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL: # BB#0: +; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; KNL-NEXT: vcvttpd2udq %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; KNL-NEXT: retq ; ; VL-LABEL: fptoui_256d: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vcvttpd2udq %ymm0, %xmm0 ; VL-NEXT: vzeroupper ; VL-NEXT: retq ; ; AVX512DQ-LABEL: fptoui_256d: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vcvttpd2udq %zmm0, %ymm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: fptoui_256d: -; AVX512BW: ## BB#0: -; AVX512BW-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW: # BB#0: +; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512BW-NEXT: vcvttpd2udq %zmm0, %ymm0 -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %b = fptoui <4 x double> %a to <4 x i32> @@ -540,7 +540,7 @@ define <4 x i32> @fptoui_256d(<4 x double> %a) nounwind { define <8 x double> @sitof64(<8 x i32> %a) { ; ALL-LABEL: sitof64: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvtdq2pd %ymm0, %zmm0 ; ALL-NEXT: retq %b = sitofp <8 x i32> %a to <8 x double> @@ -548,31 +548,31 @@ define <8 x double> @sitof64(<8 x i32> %a) { } define <8 x double> @sitof64_mask(<8 x double> %a, <8 x i32> %b, i8 %c) nounwind { ; KNL-LABEL: sitof64_mask: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: kmovw %edi, %k1 ; KNL-NEXT: vcvtdq2pd %ymm1, %zmm0 {%k1} ; KNL-NEXT: retq ; ; VLBW-LABEL: sitof64_mask: -; VLBW: ## BB#0: +; VLBW: # BB#0: ; VLBW-NEXT: kmovd %edi, %k1 ; VLBW-NEXT: vcvtdq2pd %ymm1, %zmm0 {%k1} ; VLBW-NEXT: retq ; ; VLNOBW-LABEL: sitof64_mask: -; VLNOBW: ## BB#0: +; VLNOBW: # BB#0: ; VLNOBW-NEXT: kmovw %edi, %k1 ; VLNOBW-NEXT: vcvtdq2pd %ymm1, %zmm0 {%k1} ; VLNOBW-NEXT: retq ; ; AVX512DQ-LABEL: sitof64_mask: -; AVX512DQ: ## BB#0: +; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: kmovw %edi, %k1 ; AVX512DQ-NEXT: vcvtdq2pd %ymm1, %zmm0 {%k1} ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: sitof64_mask: -; AVX512BW: ## BB#0: +; AVX512BW: # BB#0: ; AVX512BW-NEXT: kmovd %edi, %k1 ; AVX512BW-NEXT: vcvtdq2pd %ymm1, %zmm0 {%k1} ; AVX512BW-NEXT: retq @@ -583,31 +583,31 @@ define <8 x double> @sitof64_mask(<8 x double> %a, <8 x i32> %b, i8 %c) nounwind } define <8 x double> @sitof64_maskz(<8 x i32> %a, i8 %b) nounwind { ; KNL-LABEL: sitof64_maskz: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: kmovw %edi, %k1 ; KNL-NEXT: vcvtdq2pd %ymm0, %zmm0 {%k1} {z} ; KNL-NEXT: retq ; ; VLBW-LABEL: sitof64_maskz: -; VLBW: ## BB#0: +; VLBW: # BB#0: ; VLBW-NEXT: kmovd %edi, %k1 ; VLBW-NEXT: vcvtdq2pd %ymm0, %zmm0 {%k1} {z} ; VLBW-NEXT: retq ; ; VLNOBW-LABEL: sitof64_maskz: -; VLNOBW: ## BB#0: +; VLNOBW: # BB#0: ; VLNOBW-NEXT: kmovw %edi, %k1 ; VLNOBW-NEXT: vcvtdq2pd %ymm0, %zmm0 {%k1} {z} ; VLNOBW-NEXT: retq ; ; AVX512DQ-LABEL: sitof64_maskz: -; AVX512DQ: ## BB#0: +; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: kmovw %edi, %k1 ; AVX512DQ-NEXT: vcvtdq2pd %ymm0, %zmm0 {%k1} {z} ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: sitof64_maskz: -; AVX512BW: ## BB#0: +; AVX512BW: # BB#0: ; AVX512BW-NEXT: kmovd %edi, %k1 ; AVX512BW-NEXT: vcvtdq2pd %ymm0, %zmm0 {%k1} {z} ; AVX512BW-NEXT: retq @@ -619,7 +619,7 @@ define <8 x double> @sitof64_maskz(<8 x i32> %a, i8 %b) nounwind { define <8 x i32> @fptosi01(<8 x double> %a) { ; ALL-LABEL: fptosi01: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvttpd2dq %zmm0, %ymm0 ; ALL-NEXT: retq %b = fptosi <8 x double> %a to <8 x i32> @@ -628,12 +628,12 @@ define <8 x i32> @fptosi01(<8 x double> %a) { define <4 x i32> @fptosi03(<4 x double> %a) { ; KNL-LABEL: fptosi03: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: vcvttpd2dq %ymm0, %xmm0 ; KNL-NEXT: retq ; ; AVX512-LABEL: fptosi03: -; AVX512: ## BB#0: +; AVX512: # BB#0: ; AVX512-NEXT: vcvttpd2dq %ymm0, %xmm0 ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq @@ -643,14 +643,14 @@ define <4 x i32> @fptosi03(<4 x double> %a) { define <16 x float> @fptrunc00(<16 x double> %b) nounwind { ; NODQ-LABEL: fptrunc00: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vcvtpd2ps %zmm0, %ymm0 ; NODQ-NEXT: vcvtpd2ps %zmm1, %ymm1 ; NODQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; NODQ-NEXT: retq ; ; DQ-LABEL: fptrunc00: -; DQ: ## BB#0: +; DQ: # BB#0: ; DQ-NEXT: vcvtpd2ps %zmm0, %ymm0 ; DQ-NEXT: vcvtpd2ps %zmm1, %ymm1 ; DQ-NEXT: vinsertf32x8 $1, %ymm1, %zmm0, %zmm0 @@ -661,12 +661,12 @@ define <16 x float> @fptrunc00(<16 x double> %b) nounwind { define <4 x float> @fptrunc01(<4 x double> %b) { ; KNL-LABEL: fptrunc01: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: vcvtpd2ps %ymm0, %xmm0 ; KNL-NEXT: retq ; ; AVX512-LABEL: fptrunc01: -; AVX512: ## BB#0: +; AVX512: # BB#0: ; AVX512-NEXT: vcvtpd2ps %ymm0, %xmm0 ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq @@ -676,7 +676,7 @@ define <4 x float> @fptrunc01(<4 x double> %b) { define <4 x float> @fptrunc02(<4 x double> %b, <4 x i1> %mask) { ; KNL-LABEL: fptrunc02: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL-NEXT: vcvtpd2ps %ymm0, %xmm0 @@ -684,7 +684,7 @@ define <4 x float> @fptrunc02(<4 x double> %b, <4 x i1> %mask) { ; KNL-NEXT: retq ; ; VL-LABEL: fptrunc02: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vpslld $31, %xmm1, %xmm1 ; VL-NEXT: vptestmd %xmm1, %xmm1, %k1 ; VL-NEXT: vcvtpd2ps %ymm0, %xmm0 {%k1} {z} @@ -692,7 +692,7 @@ define <4 x float> @fptrunc02(<4 x double> %b, <4 x i1> %mask) { ; VL-NEXT: retq ; ; AVX512DQ-LABEL: fptrunc02: -; AVX512DQ: ## BB#0: +; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vpslld $31, %xmm1, %xmm1 ; AVX512DQ-NEXT: vpsrad $31, %xmm1, %xmm1 ; AVX512DQ-NEXT: vcvtpd2ps %ymm0, %xmm0 @@ -701,7 +701,7 @@ define <4 x float> @fptrunc02(<4 x double> %b, <4 x i1> %mask) { ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: fptrunc02: -; AVX512BW: ## BB#0: +; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpslld $31, %xmm1, %xmm1 ; AVX512BW-NEXT: vpsrad $31, %xmm1, %xmm1 ; AVX512BW-NEXT: vcvtpd2ps %ymm0, %xmm0 @@ -715,7 +715,7 @@ define <4 x float> @fptrunc02(<4 x double> %b, <4 x i1> %mask) { define <4 x float> @fptrunc03(<2 x double> %a0, <4 x float> %a1) nounwind { ; ALL-LABEL: fptrunc03: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvtsd2ss %xmm0, %xmm1, %xmm0 ; ALL-NEXT: retq %ext = extractelement <2 x double> %a0, i32 0 @@ -726,7 +726,7 @@ define <4 x float> @fptrunc03(<2 x double> %a0, <4 x float> %a1) nounwind { define <8 x double> @fpext00(<8 x float> %b) nounwind { ; ALL-LABEL: fpext00: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvtps2pd %ymm0, %zmm0 ; ALL-NEXT: retq %a = fpext <8 x float> %b to <8 x double> @@ -735,14 +735,14 @@ define <8 x double> @fpext00(<8 x float> %b) nounwind { define <4 x double> @fpext01(<4 x float> %b, <4 x double>%b1, <4 x double>%a1) { ; NOVL-LABEL: fpext01: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vcvtps2pd %xmm0, %ymm0 ; NOVL-NEXT: vcmpltpd %ymm2, %ymm1, %ymm1 ; NOVL-NEXT: vandpd %ymm0, %ymm1, %ymm0 ; NOVL-NEXT: retq ; ; VL-LABEL: fpext01: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vcmpltpd %ymm2, %ymm1, %k1 ; VL-NEXT: vcvtps2pd %xmm0, %ymm0 {%k1} {z} ; VL-NEXT: retq @@ -754,7 +754,7 @@ define <4 x double> @fpext01(<4 x float> %b, <4 x double>%b1, <4 x double>%a1) { define <2 x double> @fpext02(<2 x double> %a0, <4 x float> %a1) nounwind { ; ALL-LABEL: fpext02: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm0 ; ALL-NEXT: retq %ext = extractelement <4 x float> %a1, i32 0 @@ -765,7 +765,7 @@ define <2 x double> @fpext02(<2 x double> %a0, <4 x float> %a1) nounwind { define double @funcA(i64* nocapture %e) { ; ALL-LABEL: funcA: -; ALL: ## BB#0: ## %entry +; ALL: # BB#0: # %entry ; ALL-NEXT: vcvtsi2sdq (%rdi), %xmm0, %xmm0 ; ALL-NEXT: retq entry: @@ -776,7 +776,7 @@ entry: define double @funcB(i32* %e) { ; ALL-LABEL: funcB: -; ALL: ## BB#0: ## %entry +; ALL: # BB#0: # %entry ; ALL-NEXT: vcvtsi2sdl (%rdi), %xmm0, %xmm0 ; ALL-NEXT: retq entry: @@ -787,7 +787,7 @@ entry: define float @funcC(i32* %e) { ; ALL-LABEL: funcC: -; ALL: ## BB#0: ## %entry +; ALL: # BB#0: # %entry ; ALL-NEXT: vcvtsi2ssl (%rdi), %xmm0, %xmm0 ; ALL-NEXT: retq entry: @@ -798,7 +798,7 @@ entry: define float @i64tof32(i64* %e) { ; ALL-LABEL: i64tof32: -; ALL: ## BB#0: ## %entry +; ALL: # BB#0: # %entry ; ALL-NEXT: vcvtsi2ssq (%rdi), %xmm0, %xmm0 ; ALL-NEXT: retq entry: @@ -809,7 +809,7 @@ entry: define void @fpext() { ; ALL-LABEL: fpext: -; ALL: ## BB#0: ## %entry +; ALL: # BB#0: # %entry ; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; ALL-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 ; ALL-NEXT: vmovsd %xmm0, -{{[0-9]+}}(%rsp) @@ -825,7 +825,7 @@ entry: define void @fpround_scalar() nounwind uwtable { ; ALL-LABEL: fpround_scalar: -; ALL: ## BB#0: ## %entry +; ALL: # BB#0: # %entry ; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; ALL-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 ; ALL-NEXT: vmovss %xmm0, -{{[0-9]+}}(%rsp) @@ -841,7 +841,7 @@ entry: define double @long_to_double(i64 %x) { ; ALL-LABEL: long_to_double: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vmovq %rdi, %xmm0 ; ALL-NEXT: retq %res = bitcast i64 %x to double @@ -850,7 +850,7 @@ define double @long_to_double(i64 %x) { define i64 @double_to_long(double %x) { ; ALL-LABEL: double_to_long: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vmovq %xmm0, %rax ; ALL-NEXT: retq %res = bitcast double %x to i64 @@ -859,7 +859,7 @@ define i64 @double_to_long(double %x) { define float @int_to_float(i32 %x) { ; ALL-LABEL: int_to_float: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vmovd %edi, %xmm0 ; ALL-NEXT: retq %res = bitcast i32 %x to float @@ -868,7 +868,7 @@ define float @int_to_float(i32 %x) { define i32 @float_to_int(float %x) { ; ALL-LABEL: float_to_int: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vmovd %xmm0, %eax ; ALL-NEXT: retq %res = bitcast float %x to i32 @@ -877,7 +877,7 @@ define i32 @float_to_int(float %x) { define <16 x double> @uitof64(<16 x i32> %a) nounwind { ; NODQ-LABEL: uitof64: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vcvtudq2pd %ymm0, %zmm2 ; NODQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0 ; NODQ-NEXT: vcvtudq2pd %ymm0, %zmm1 @@ -885,7 +885,7 @@ define <16 x double> @uitof64(<16 x i32> %a) nounwind { ; NODQ-NEXT: retq ; ; DQ-LABEL: uitof64: -; DQ: ## BB#0: +; DQ: # BB#0: ; DQ-NEXT: vcvtudq2pd %ymm0, %zmm2 ; DQ-NEXT: vextracti32x8 $1, %zmm0, %ymm0 ; DQ-NEXT: vcvtudq2pd %ymm0, %zmm1 @@ -896,31 +896,31 @@ define <16 x double> @uitof64(<16 x i32> %a) nounwind { } define <8 x double> @uitof64_mask(<8 x double> %a, <8 x i32> %b, i8 %c) nounwind { ; KNL-LABEL: uitof64_mask: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: kmovw %edi, %k1 ; KNL-NEXT: vcvtudq2pd %ymm1, %zmm0 {%k1} ; KNL-NEXT: retq ; ; VLBW-LABEL: uitof64_mask: -; VLBW: ## BB#0: +; VLBW: # BB#0: ; VLBW-NEXT: kmovd %edi, %k1 ; VLBW-NEXT: vcvtudq2pd %ymm1, %zmm0 {%k1} ; VLBW-NEXT: retq ; ; VLNOBW-LABEL: uitof64_mask: -; VLNOBW: ## BB#0: +; VLNOBW: # BB#0: ; VLNOBW-NEXT: kmovw %edi, %k1 ; VLNOBW-NEXT: vcvtudq2pd %ymm1, %zmm0 {%k1} ; VLNOBW-NEXT: retq ; ; AVX512DQ-LABEL: uitof64_mask: -; AVX512DQ: ## BB#0: +; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: kmovw %edi, %k1 ; AVX512DQ-NEXT: vcvtudq2pd %ymm1, %zmm0 {%k1} ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: uitof64_mask: -; AVX512BW: ## BB#0: +; AVX512BW: # BB#0: ; AVX512BW-NEXT: kmovd %edi, %k1 ; AVX512BW-NEXT: vcvtudq2pd %ymm1, %zmm0 {%k1} ; AVX512BW-NEXT: retq @@ -931,31 +931,31 @@ define <8 x double> @uitof64_mask(<8 x double> %a, <8 x i32> %b, i8 %c) nounwind } define <8 x double> @uitof64_maskz(<8 x i32> %a, i8 %b) nounwind { ; KNL-LABEL: uitof64_maskz: -; KNL: ## BB#0: +; KNL: # BB#0: ; KNL-NEXT: kmovw %edi, %k1 ; KNL-NEXT: vcvtudq2pd %ymm0, %zmm0 {%k1} {z} ; KNL-NEXT: retq ; ; VLBW-LABEL: uitof64_maskz: -; VLBW: ## BB#0: +; VLBW: # BB#0: ; VLBW-NEXT: kmovd %edi, %k1 ; VLBW-NEXT: vcvtudq2pd %ymm0, %zmm0 {%k1} {z} ; VLBW-NEXT: retq ; ; VLNOBW-LABEL: uitof64_maskz: -; VLNOBW: ## BB#0: +; VLNOBW: # BB#0: ; VLNOBW-NEXT: kmovw %edi, %k1 ; VLNOBW-NEXT: vcvtudq2pd %ymm0, %zmm0 {%k1} {z} ; VLNOBW-NEXT: retq ; ; AVX512DQ-LABEL: uitof64_maskz: -; AVX512DQ: ## BB#0: +; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: kmovw %edi, %k1 ; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 {%k1} {z} ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: uitof64_maskz: -; AVX512BW: ## BB#0: +; AVX512BW: # BB#0: ; AVX512BW-NEXT: kmovd %edi, %k1 ; AVX512BW-NEXT: vcvtudq2pd %ymm0, %zmm0 {%k1} {z} ; AVX512BW-NEXT: retq @@ -967,14 +967,14 @@ define <8 x double> @uitof64_maskz(<8 x i32> %a, i8 %b) nounwind { define <4 x double> @uitof64_256(<4 x i32> %a) nounwind { ; NOVL-LABEL: uitof64_256: -; NOVL: ## BB#0: -; NOVL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; NOVL: # BB#0: +; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> ; NOVL-NEXT: vcvtudq2pd %ymm0, %zmm0 -; NOVL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; NOVL-NEXT: retq ; ; VL-LABEL: uitof64_256: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vcvtudq2pd %xmm0, %ymm0 ; VL-NEXT: retq %b = uitofp <4 x i32> %a to <4 x double> @@ -983,7 +983,7 @@ define <4 x double> @uitof64_256(<4 x i32> %a) nounwind { define <16 x float> @uitof32(<16 x i32> %a) nounwind { ; ALL-LABEL: uitof32: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvtudq2ps %zmm0, %zmm0 ; ALL-NEXT: retq %b = uitofp <16 x i32> %a to <16 x float> @@ -992,14 +992,14 @@ define <16 x float> @uitof32(<16 x i32> %a) nounwind { define <8 x float> @uitof32_256(<8 x i32> %a) nounwind { ; NOVL-LABEL: uitof32_256: -; NOVL: ## BB#0: -; NOVL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL: # BB#0: +; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0 -; NOVL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; NOVL-NEXT: retq ; ; VL-LABEL: uitof32_256: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vcvtudq2ps %ymm0, %ymm0 ; VL-NEXT: retq %b = uitofp <8 x i32> %a to <8 x float> @@ -1008,30 +1008,30 @@ define <8 x float> @uitof32_256(<8 x i32> %a) nounwind { define <4 x float> @uitof32_128(<4 x i32> %a) nounwind { ; KNL-LABEL: uitof32_128: -; KNL: ## BB#0: -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL: # BB#0: +; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; KNL-NEXT: vcvtudq2ps %zmm0, %zmm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> ; KNL-NEXT: retq ; ; VL-LABEL: uitof32_128: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vcvtudq2ps %xmm0, %xmm0 ; VL-NEXT: retq ; ; AVX512DQ-LABEL: uitof32_128: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: uitof32_128: -; AVX512BW: ## BB#0: -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW: # BB#0: +; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> ; AVX512BW-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %b = uitofp <4 x i32> %a to <4 x float> @@ -1040,7 +1040,7 @@ define <4 x float> @uitof32_128(<4 x i32> %a) nounwind { define i32 @fptosi02(float %a) nounwind { ; ALL-LABEL: fptosi02: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvttss2si %xmm0, %eax ; ALL-NEXT: retq %b = fptosi float %a to i32 @@ -1049,7 +1049,7 @@ define i32 @fptosi02(float %a) nounwind { define i32 @fptoui02(float %a) nounwind { ; ALL-LABEL: fptoui02: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvttss2usi %xmm0, %eax ; ALL-NEXT: retq %b = fptoui float %a to i32 @@ -1058,7 +1058,7 @@ define i32 @fptoui02(float %a) nounwind { define float @uitofp02(i32 %a) nounwind { ; ALL-LABEL: uitofp02: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvtusi2ssl %edi, %xmm0, %xmm0 ; ALL-NEXT: retq %b = uitofp i32 %a to float @@ -1067,7 +1067,7 @@ define float @uitofp02(i32 %a) nounwind { define double @uitofp03(i32 %a) nounwind { ; ALL-LABEL: uitofp03: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vcvtusi2sdl %edi, %xmm0, %xmm0 ; ALL-NEXT: retq %b = uitofp i32 %a to double @@ -1076,7 +1076,7 @@ define double @uitofp03(i32 %a) nounwind { define <16 x float> @sitofp_16i1_float(<16 x i32> %a) { ; NODQ-LABEL: sitofp_16i1_float: -; NODQ: ## BB#0: +; NODQ: # BB#0: ; NODQ-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; NODQ-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; NODQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} @@ -1084,7 +1084,7 @@ define <16 x float> @sitofp_16i1_float(<16 x i32> %a) { ; NODQ-NEXT: retq ; ; DQ-LABEL: sitofp_16i1_float: -; DQ: ## BB#0: +; DQ: # BB#0: ; DQ-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; DQ-NEXT: vpcmpgtd %zmm0, %zmm1, %k0 ; DQ-NEXT: vpmovm2d %k0, %zmm0 @@ -1097,7 +1097,7 @@ define <16 x float> @sitofp_16i1_float(<16 x i32> %a) { define <16 x float> @sitofp_16i8_float(<16 x i8> %a) { ; ALL-LABEL: sitofp_16i8_float: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vpmovsxbd %xmm0, %zmm0 ; ALL-NEXT: vcvtdq2ps %zmm0, %zmm0 ; ALL-NEXT: retq @@ -1107,7 +1107,7 @@ define <16 x float> @sitofp_16i8_float(<16 x i8> %a) { define <16 x float> @sitofp_16i16_float(<16 x i16> %a) { ; ALL-LABEL: sitofp_16i16_float: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vpmovsxwd %ymm0, %zmm0 ; ALL-NEXT: vcvtdq2ps %zmm0, %zmm0 ; ALL-NEXT: retq @@ -1117,7 +1117,7 @@ define <16 x float> @sitofp_16i16_float(<16 x i16> %a) { define <8 x double> @sitofp_8i16_double(<8 x i16> %a) { ; ALL-LABEL: sitofp_8i16_double: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vpmovsxwd %xmm0, %ymm0 ; ALL-NEXT: vcvtdq2pd %ymm0, %zmm0 ; ALL-NEXT: retq @@ -1127,7 +1127,7 @@ define <8 x double> @sitofp_8i16_double(<8 x i16> %a) { define <8 x double> @sitofp_8i8_double(<8 x i8> %a) { ; ALL-LABEL: sitofp_8i8_double: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; ALL-NEXT: vpslld $24, %ymm0, %ymm0 ; ALL-NEXT: vpsrad $24, %ymm0, %ymm0 @@ -1139,7 +1139,7 @@ define <8 x double> @sitofp_8i8_double(<8 x i8> %a) { define <16 x double> @sitofp_16i1_double(<16 x double> %a) { ; NOVLDQ-LABEL: sitofp_16i1_double: -; NOVLDQ: ## BB#0: +; NOVLDQ: # BB#0: ; NOVLDQ-NEXT: vpxord %zmm2, %zmm2, %zmm2 ; NOVLDQ-NEXT: vcmpltpd %zmm1, %zmm2, %k1 ; NOVLDQ-NEXT: vcmpltpd %zmm0, %zmm2, %k2 @@ -1152,7 +1152,7 @@ define <16 x double> @sitofp_16i1_double(<16 x double> %a) { ; NOVLDQ-NEXT: retq ; ; VLDQ-LABEL: sitofp_16i1_double: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vxorpd %zmm2, %zmm2, %zmm2 ; VLDQ-NEXT: vcmpltpd %zmm1, %zmm2, %k0 ; VLDQ-NEXT: vcmpltpd %zmm0, %zmm2, %k1 @@ -1163,7 +1163,7 @@ define <16 x double> @sitofp_16i1_double(<16 x double> %a) { ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sitofp_16i1_double: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpxord %zmm2, %zmm2, %zmm2 ; VLNODQ-NEXT: vcmpltpd %zmm1, %zmm2, %k1 ; VLNODQ-NEXT: vcmpltpd %zmm0, %zmm2, %k2 @@ -1175,7 +1175,7 @@ define <16 x double> @sitofp_16i1_double(<16 x double> %a) { ; VLNODQ-NEXT: retq ; ; AVX512DQ-LABEL: sitofp_16i1_double: -; AVX512DQ: ## BB#0: +; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vxorpd %zmm2, %zmm2, %zmm2 ; AVX512DQ-NEXT: vcmpltpd %zmm1, %zmm2, %k0 ; AVX512DQ-NEXT: vcmpltpd %zmm0, %zmm2, %k1 @@ -1191,7 +1191,7 @@ define <16 x double> @sitofp_16i1_double(<16 x double> %a) { define <8 x double> @sitofp_8i1_double(<8 x double> %a) { ; NOVLDQ-LABEL: sitofp_8i1_double: -; NOVLDQ: ## BB#0: +; NOVLDQ: # BB#0: ; NOVLDQ-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; NOVLDQ-NEXT: vcmpltpd %zmm0, %zmm1, %k1 ; NOVLDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} @@ -1200,7 +1200,7 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) { ; NOVLDQ-NEXT: retq ; ; VLDQ-LABEL: sitofp_8i1_double: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vxorpd %zmm1, %zmm1, %zmm1 ; VLDQ-NEXT: vcmpltpd %zmm0, %zmm1, %k0 ; VLDQ-NEXT: vpmovm2d %k0, %ymm0 @@ -1208,7 +1208,7 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) { ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sitofp_8i1_double: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; VLNODQ-NEXT: vcmpltpd %zmm0, %zmm1, %k1 ; VLNODQ-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 @@ -1217,7 +1217,7 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) { ; VLNODQ-NEXT: retq ; ; AVX512DQ-LABEL: sitofp_8i1_double: -; AVX512DQ: ## BB#0: +; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vxorpd %zmm1, %zmm1, %zmm1 ; AVX512DQ-NEXT: vcmpltpd %zmm0, %zmm1, %k0 ; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0 @@ -1230,8 +1230,8 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) { define <8 x float> @sitofp_8i1_float(<8 x float> %a) { ; NOVLDQ-LABEL: sitofp_8i1_float: -; NOVLDQ: ## BB#0: -; NOVLDQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVLDQ: # BB#0: +; NOVLDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NOVLDQ-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; NOVLDQ-NEXT: vcmpltps %zmm0, %zmm1, %k1 ; NOVLDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} @@ -1240,7 +1240,7 @@ define <8 x float> @sitofp_8i1_float(<8 x float> %a) { ; NOVLDQ-NEXT: retq ; ; VLDQ-LABEL: sitofp_8i1_float: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; VLDQ-NEXT: vcmpltps %ymm0, %ymm1, %k0 ; VLDQ-NEXT: vpmovm2d %k0, %ymm0 @@ -1248,7 +1248,7 @@ define <8 x float> @sitofp_8i1_float(<8 x float> %a) { ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sitofp_8i1_float: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; VLNODQ-NEXT: vcmpltps %ymm0, %ymm1, %k1 ; VLNODQ-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 @@ -1257,8 +1257,8 @@ define <8 x float> @sitofp_8i1_float(<8 x float> %a) { ; VLNODQ-NEXT: retq ; ; AVX512DQ-LABEL: sitofp_8i1_float: -; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ: # BB#0: +; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; AVX512DQ-NEXT: vxorps %ymm1, %ymm1, %ymm1 ; AVX512DQ-NEXT: vcmpltps %zmm0, %zmm1, %k0 ; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0 @@ -1271,14 +1271,14 @@ define <8 x float> @sitofp_8i1_float(<8 x float> %a) { define <4 x float> @sitofp_4i1_float(<4 x float> %a) { ; NOVL-LABEL: sitofp_4i1_float: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vcmpltps %xmm0, %xmm1, %xmm0 ; NOVL-NEXT: vcvtdq2ps %xmm0, %xmm0 ; NOVL-NEXT: retq ; ; VLDQ-LABEL: sitofp_4i1_float: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; VLDQ-NEXT: vcmpltps %xmm0, %xmm1, %k0 ; VLDQ-NEXT: vpmovm2d %k0, %xmm0 @@ -1286,7 +1286,7 @@ define <4 x float> @sitofp_4i1_float(<4 x float> %a) { ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sitofp_4i1_float: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; VLNODQ-NEXT: vcmpltps %xmm0, %xmm1, %k1 ; VLNODQ-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 @@ -1300,7 +1300,7 @@ define <4 x float> @sitofp_4i1_float(<4 x float> %a) { define <4 x double> @sitofp_4i1_double(<4 x double> %a) { ; NOVL-LABEL: sitofp_4i1_double: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; NOVL-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; NOVL-NEXT: vpmovqd %zmm0, %ymm0 @@ -1308,7 +1308,7 @@ define <4 x double> @sitofp_4i1_double(<4 x double> %a) { ; NOVL-NEXT: retq ; ; VLDQ-LABEL: sitofp_4i1_double: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vxorpd %ymm1, %ymm1, %ymm1 ; VLDQ-NEXT: vcmpltpd %ymm0, %ymm1, %k0 ; VLDQ-NEXT: vpmovm2d %k0, %xmm0 @@ -1316,7 +1316,7 @@ define <4 x double> @sitofp_4i1_double(<4 x double> %a) { ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sitofp_4i1_double: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; VLNODQ-NEXT: vcmpltpd %ymm0, %ymm1, %k1 ; VLNODQ-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 @@ -1330,14 +1330,14 @@ define <4 x double> @sitofp_4i1_double(<4 x double> %a) { define <2 x float> @sitofp_2i1_float(<2 x float> %a) { ; NOVL-LABEL: sitofp_2i1_float: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vcmpltps %xmm0, %xmm1, %xmm0 ; NOVL-NEXT: vcvtdq2ps %xmm0, %xmm0 ; NOVL-NEXT: retq ; ; VLDQ-LABEL: sitofp_2i1_float: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; VLDQ-NEXT: vcmpltps %xmm0, %xmm1, %k0 ; VLDQ-NEXT: vpmovm2d %k0, %xmm0 @@ -1345,7 +1345,7 @@ define <2 x float> @sitofp_2i1_float(<2 x float> %a) { ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sitofp_2i1_float: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; VLNODQ-NEXT: vcmpltps %xmm0, %xmm1, %k1 ; VLNODQ-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 @@ -1359,7 +1359,7 @@ define <2 x float> @sitofp_2i1_float(<2 x float> %a) { define <2 x double> @sitofp_2i1_double(<2 x double> %a) { ; NOVL-LABEL: sitofp_2i1_double: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0 ; NOVL-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -1367,7 +1367,7 @@ define <2 x double> @sitofp_2i1_double(<2 x double> %a) { ; NOVL-NEXT: retq ; ; VLDQ-LABEL: sitofp_2i1_double: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; VLDQ-NEXT: vcmpltpd %xmm0, %xmm1, %k0 ; VLDQ-NEXT: vpmovm2q %k0, %xmm0 @@ -1375,7 +1375,7 @@ define <2 x double> @sitofp_2i1_double(<2 x double> %a) { ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: sitofp_2i1_double: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; VLNODQ-NEXT: vcmpltpd %xmm0, %xmm1, %k1 ; VLNODQ-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 @@ -1393,7 +1393,7 @@ define <2 x double> @sitofp_2i1_double(<2 x double> %a) { define <16 x float> @uitofp_16i8(<16 x i8>%a) { ; ALL-LABEL: uitofp_16i8: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; ALL-NEXT: vcvtdq2ps %zmm0, %zmm0 ; ALL-NEXT: retq @@ -1403,7 +1403,7 @@ define <16 x float> @uitofp_16i8(<16 x i8>%a) { define <16 x float> @uitofp_16i16(<16 x i16>%a) { ; ALL-LABEL: uitofp_16i16: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; ALL-NEXT: vcvtdq2ps %zmm0, %zmm0 ; ALL-NEXT: retq @@ -1413,7 +1413,7 @@ define <16 x float> @uitofp_16i16(<16 x i16>%a) { define <16 x float> @uitofp_16i1_float(<16 x i32> %a) { ; ALL-LABEL: uitofp_16i1_float: -; ALL: ## BB#0: +; ALL: # BB#0: ; ALL-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; ALL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; ALL-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z} @@ -1426,7 +1426,7 @@ define <16 x float> @uitofp_16i1_float(<16 x i32> %a) { define <16 x double> @uitofp_16i1_double(<16 x i32> %a) { ; NOVL-LABEL: uitofp_16i1_double: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; NOVL-NEXT: movq {{.*}}(%rip), %rax @@ -1440,7 +1440,7 @@ define <16 x double> @uitofp_16i1_double(<16 x i32> %a) { ; NOVL-NEXT: retq ; ; VL-LABEL: uitofp_16i1_double: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; VL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; VL-NEXT: movl {{.*}}(%rip), %eax @@ -1457,18 +1457,18 @@ define <16 x double> @uitofp_16i1_double(<16 x i32> %a) { define <8 x float> @uitofp_8i1_float(<8 x i32> %a) { ; NOVL-LABEL: uitofp_8i1_float: -; NOVL: ## BB#0: -; NOVL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL: # BB#0: +; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NOVL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; NOVL-NEXT: vpmovqd %zmm0, %ymm0 ; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0 -; NOVL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> ; NOVL-NEXT: retq ; ; VL-LABEL: uitofp_8i1_float: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; VL-NEXT: vpcmpgtd %ymm0, %ymm1, %k1 ; VL-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z} @@ -1481,8 +1481,8 @@ define <8 x float> @uitofp_8i1_float(<8 x i32> %a) { define <8 x double> @uitofp_8i1_double(<8 x i32> %a) { ; NOVL-LABEL: uitofp_8i1_double: -; NOVL: ## BB#0: -; NOVL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL: # BB#0: +; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> ; NOVL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} @@ -1491,7 +1491,7 @@ define <8 x double> @uitofp_8i1_double(<8 x i32> %a) { ; NOVL-NEXT: retq ; ; VL-LABEL: uitofp_8i1_double: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; VL-NEXT: vpcmpgtd %ymm0, %ymm1, %k1 ; VL-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z} @@ -1504,7 +1504,7 @@ define <8 x double> @uitofp_8i1_double(<8 x i32> %a) { define <4 x float> @uitofp_4i1_float(<4 x i32> %a) { ; NOVL-LABEL: uitofp_4i1_float: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NOVL-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 @@ -1512,7 +1512,7 @@ define <4 x float> @uitofp_4i1_float(<4 x i32> %a) { ; NOVL-NEXT: retq ; ; VL-LABEL: uitofp_4i1_float: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; VL-NEXT: vpcmpgtd %xmm0, %xmm1, %k1 ; VL-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z} @@ -1525,7 +1525,7 @@ define <4 x float> @uitofp_4i1_float(<4 x i32> %a) { define <4 x double> @uitofp_4i1_double(<4 x i32> %a) { ; NOVL-LABEL: uitofp_4i1_double: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 ; NOVL-NEXT: vpsrld $31, %xmm0, %xmm0 @@ -1533,7 +1533,7 @@ define <4 x double> @uitofp_4i1_double(<4 x i32> %a) { ; NOVL-NEXT: retq ; ; VL-LABEL: uitofp_4i1_double: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; VL-NEXT: vpcmpgtd %xmm0, %xmm1, %k1 ; VL-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z} @@ -1546,7 +1546,7 @@ define <4 x double> @uitofp_4i1_double(<4 x i32> %a) { define <2 x float> @uitofp_2i1_float(<2 x i32> %a) { ; NOVL-LABEL: uitofp_2i1_float: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] ; NOVL-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808] @@ -1562,7 +1562,7 @@ define <2 x float> @uitofp_2i1_float(<2 x i32> %a) { ; NOVL-NEXT: retq ; ; VL-LABEL: uitofp_2i1_float: -; VL: ## BB#0: +; VL: # BB#0: ; VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] ; VL-NEXT: vpcmpltuq %xmm1, %xmm0, %k1 @@ -1576,7 +1576,7 @@ define <2 x float> @uitofp_2i1_float(<2 x i32> %a) { define <2 x double> @uitofp_2i1_double(<2 x i32> %a) { ; NOVL-LABEL: uitofp_2i1_double: -; NOVL: ## BB#0: +; NOVL: # BB#0: ; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] ; NOVL-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808] @@ -1586,7 +1586,7 @@ define <2 x double> @uitofp_2i1_double(<2 x i32> %a) { ; NOVL-NEXT: retq ; ; VLDQ-LABEL: uitofp_2i1_double: -; VLDQ: ## BB#0: +; VLDQ: # BB#0: ; VLDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; VLDQ-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] ; VLDQ-NEXT: vpcmpltuq %xmm1, %xmm0, %k1 @@ -1595,7 +1595,7 @@ define <2 x double> @uitofp_2i1_double(<2 x i32> %a) { ; VLDQ-NEXT: retq ; ; VLNODQ-LABEL: uitofp_2i1_double: -; VLNODQ: ## BB#0: +; VLNODQ: # BB#0: ; VLNODQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; VLNODQ-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] ; VLNODQ-NEXT: vpcmpltuq %xmm1, %xmm0, %k1 diff --git a/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll b/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll index b13965a30ed8..bbe31c5c2ac5 100644 --- a/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll +++ b/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll @@ -1203,3 +1203,35 @@ define <8 x double> @f8xf64_f256(<8 x double> %a) { ret <8 x double> %res2 } + + +; ALL: .LCPI38 +; ALL-NEXT: .long 4290379776 # 0xffba0000 + +; AVX: .LCPI38 +; AVX-NEXT: .long 4290379776 # float NaN + +define <8 x i16> @f8xi16_i32_NaN(<8 x i16> %a) { +; ALL32-LABEL: f8xi16_i32_NaN: +; ALL32: # BB#0: +; ALL32-NEXT: vpbroadcastd {{\.LCPI.*}}, %xmm1 +; ALL32-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; ALL32-NEXT: vpand %xmm1, %xmm0, %xmm0 +; ALL32-NEXT: retl +; +; ALL64-LABEL: f8xi16_i32_NaN: +; ALL64: # BB#0: +; ALL64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 +; ALL64-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; ALL64-NEXT: vpand %xmm1, %xmm0, %xmm0 +; ALL64-NEXT: retq +; +; AVX-LABEL: f8xi16_i32_NaN: +; AVX: # BB#0: +; AVX-NEXT: vbroadcastss {{\.LCPI.*}}, %xmm1 +; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0 + %res1 = add <8 x i16> <i16 0, i16 -70, i16 0, i16 -70, i16 0, i16 -70, i16 0, i16 -70>, %a + %res2 = and <8 x i16> <i16 0, i16 -70, i16 0, i16 -70, i16 0, i16 -70, i16 0, i16 -70>, %res1 + ret <8 x i16> %res2 +} diff --git a/test/CodeGen/X86/clear_upper_vector_element_bits.ll b/test/CodeGen/X86/clear_upper_vector_element_bits.ll index ae0f4406ba0d..1218b68b1be4 100644 --- a/test/CodeGen/X86/clear_upper_vector_element_bits.ll +++ b/test/CodeGen/X86/clear_upper_vector_element_bits.ll @@ -405,12 +405,7 @@ define <16 x i8> @_clearupper16xi8a(<16 x i8>) nounwind { ; ; AVX-LABEL: _clearupper16xi8a: ; AVX: # BB#0: -; AVX-NEXT: vpextrb $0, %xmm0, %eax -; AVX-NEXT: vpextrb $1, %xmm0, %ecx -; AVX-NEXT: vmovd %eax, %xmm1 -; AVX-NEXT: vpinsrb $1, %ecx, %xmm1, %xmm1 -; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7] -; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq %x0 = extractelement <16 x i8> %0, i32 0 %x1 = extractelement <16 x i8> %0, i32 1 @@ -575,39 +570,10 @@ define <32 x i8> @_clearupper32xi8a(<32 x i8>) nounwind { ; SSE-NEXT: pand %xmm2, %xmm1 ; SSE-NEXT: retq ; -; AVX1-LABEL: _clearupper32xi8a: -; AVX1: # BB#0: -; AVX1-NEXT: vpextrb $0, %xmm0, %eax -; AVX1-NEXT: vpextrb $1, %xmm0, %ecx -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vpextrb $0, %xmm1, %edx -; AVX1-NEXT: vpextrb $1, %xmm1, %esi -; AVX1-NEXT: vmovd %edx, %xmm2 -; AVX1-NEXT: vpinsrb $1, %esi, %xmm2, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3,4,5,6,7] -; AVX1-NEXT: vmovd %eax, %xmm2 -; AVX1-NEXT: vpinsrb $1, %ecx, %xmm2, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5,6,7] -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 -; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 -; AVX1-NEXT: retq -; -; AVX2-LABEL: _clearupper32xi8a: -; AVX2: # BB#0: -; AVX2-NEXT: vpextrb $0, %xmm0, %eax -; AVX2-NEXT: vpextrb $1, %xmm0, %ecx -; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX2-NEXT: vpextrb $0, %xmm1, %edx -; AVX2-NEXT: vpextrb $1, %xmm1, %esi -; AVX2-NEXT: vmovd %edx, %xmm2 -; AVX2-NEXT: vpinsrb $1, %esi, %xmm2, %xmm2 -; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3,4,5,6,7] -; AVX2-NEXT: vmovd %eax, %xmm2 -; AVX2-NEXT: vpinsrb $1, %ecx, %xmm2, %xmm2 -; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5,6,7] -; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 -; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 -; AVX2-NEXT: retq +; AVX-LABEL: _clearupper32xi8a: +; AVX: # BB#0: +; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 +; AVX-NEXT: retq %x0 = extractelement <32 x i8> %0, i32 0 %x1 = extractelement <32 x i8> %0, i32 1 %x2 = extractelement <32 x i8> %0, i32 2 diff --git a/test/CodeGen/X86/scavenger.mir b/test/CodeGen/X86/scavenger.mir new file mode 100644 index 000000000000..8d97aeb22cb9 --- /dev/null +++ b/test/CodeGen/X86/scavenger.mir @@ -0,0 +1,54 @@ +# RUN: llc -mtriple=i386-- -run-pass scavenger-test -verify-machineinstrs -o - %s | FileCheck %s +--- +# CHECK-LABEL: name: func0 +name: func0 +tracksRegLiveness: true +body: | + bb.0: + %0 : gr32 = MOV32ri 42 + %ebp = COPY %0 +... +--- +# CHECK-LABEL: name: func2 +name: func2 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-NOT: %eax = MOV32ri 42 + ; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42 + ; CHECK: %ebp = COPY [[REG0]] + %eax = MOV32ri 13 + %0 : gr32 = MOV32ri 42 + %ebp = COPY %0 + + ; CHECK: [[REG1:%e[a-z]+]] = MOV32ri 23 + ; CHECK: [[REG2:%e[a-z]+]] = MOV32ri 7 + ; CHECK: [[REG1]] = ADD32ri8 [[REG1]], 5, implicit-def dead %eflags + %1 : gr32 = MOV32ri 23 + %2 : gr32 = MOV32ri 7 + %1 = ADD32ri8 %1, 5, implicit-def dead %eflags + + NOOP implicit %ebp + + ; CHECK: NOOP implicit [[REG2]] + ; CHECK: NOOP implicit [[REG1]] + NOOP implicit %2 + NOOP implicit %1 + RETQ %eax +... +--- +# Defs without uses are currently broken +#name: func3 +#tracksRegLiveness: true +#body: | +# bb.0: +# dead %0 : gr32 = MOV32ri 42 +... +--- +# Uses without defs are currently broken (and honestly not that useful). +#name: func3 +#tracksRegLiveness: true +#body: | +# bb.0: +# NOOP undef implicit %0 : gr32 +... diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll index 1afef86a5f11..7c2937936313 100644 --- a/test/CodeGen/X86/select.ll +++ b/test/CodeGen/X86/select.ll @@ -15,6 +15,7 @@ define i32 @test1(%0* %p, %0* %q, i1 %r) nounwind { ; CHECK-NEXT: cmovneq %rdi, %rsi ; CHECK-NEXT: movl (%rsi), %eax ; CHECK-NEXT: retq +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test1: ; MCU: # BB#0: @@ -55,6 +56,7 @@ define i32 @test2() nounwind { ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: retq ; CHECK-NEXT: LBB1_1: ## %bb90 +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test2: ; MCU: # BB#0: # %entry @@ -100,6 +102,7 @@ define float @test3(i32 %x) nounwind readnone { ; CHECK-NEXT: leaq {{.*}}(%rip), %rcx ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: retq +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test3: ; MCU: # BB#0: # %entry @@ -123,6 +126,7 @@ define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly { ; CHECK-NEXT: seta %al ; CHECK-NEXT: movsbl (%rdi,%rax,4), %eax ; CHECK-NEXT: retq +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test4: ; MCU: # BB#0: # %entry @@ -157,6 +161,7 @@ define void @test5(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) nounwind { ; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] ; CHECK-NEXT: movd %xmm0, (%rsi) ; CHECK-NEXT: retq +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test5: ; MCU: # BB#0: @@ -196,6 +201,7 @@ define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-NEXT: mulps %xmm0, %xmm0 ; CHECK-NEXT: movaps %xmm0, (%rsi) ; CHECK-NEXT: retq +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test6: ; MCU: # BB#0: @@ -267,6 +273,7 @@ define x86_fp80 @test7(i32 %tmp8) nounwind { ; CHECK-NEXT: leaq {{.*}}(%rip), %rcx ; CHECK-NEXT: fldt (%rax,%rcx) ; CHECK-NEXT: retq +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test7: ; MCU: # BB#0: @@ -319,6 +326,7 @@ define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2) ; GENERIC-NEXT: movq %xmm0, 16(%rsi) ; GENERIC-NEXT: movdqa %xmm1, (%rsi) ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test8: ; ATOM: ## BB#0: @@ -358,6 +366,7 @@ define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2) ; ATOM-NEXT: movq %xmm0, 16(%rsi) ; ATOM-NEXT: movdqa %xmm1, (%rsi) ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test8: ; MCU: # BB#0: @@ -448,6 +457,7 @@ define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; GENERIC-NEXT: sbbq %rax, %rax ; GENERIC-NEXT: orq %rsi, %rax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test9: ; ATOM: ## BB#0: @@ -457,6 +467,7 @@ define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test9: ; MCU: # BB#0: @@ -483,6 +494,7 @@ define i64 @test9a(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; GENERIC-NEXT: sbbq %rax, %rax ; GENERIC-NEXT: orq %rsi, %rax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test9a: ; ATOM: ## BB#0: @@ -492,6 +504,7 @@ define i64 @test9a(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test9a: ; MCU: # BB#0: @@ -516,6 +529,7 @@ define i64 @test9b(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; GENERIC-NEXT: sbbq %rax, %rax ; GENERIC-NEXT: orq %rsi, %rax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test9b: ; ATOM: ## BB#0: @@ -525,6 +539,7 @@ define i64 @test9b(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test9b: ; MCU: # BB#0: @@ -552,6 +567,7 @@ define i64 @test10(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; GENERIC-NEXT: sbbq %rax, %rax ; GENERIC-NEXT: orq $1, %rax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test10: ; ATOM: ## BB#0: @@ -561,6 +577,7 @@ define i64 @test10(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test10: ; MCU: # BB#0: @@ -586,6 +603,7 @@ define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; CHECK-NEXT: notq %rax ; CHECK-NEXT: orq %rsi, %rax ; CHECK-NEXT: retq +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test11: ; MCU: # BB#0: @@ -612,6 +630,7 @@ define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; CHECK-NEXT: notq %rax ; CHECK-NEXT: orq %rsi, %rax ; CHECK-NEXT: retq +; CHECK-NEXT: ## -- End function ; ; MCU-LABEL: test11a: ; MCU: # BB#0: @@ -641,6 +660,7 @@ define noalias i8* @test12(i64 %count) nounwind ssp noredzone { ; GENERIC-NEXT: movq $-1, %rdi ; GENERIC-NEXT: cmovnoq %rax, %rdi ; GENERIC-NEXT: jmp __Znam ## TAILCALL +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test12: ; ATOM: ## BB#0: ## %entry @@ -650,6 +670,7 @@ define noalias i8* @test12(i64 %count) nounwind ssp noredzone { ; ATOM-NEXT: movq $-1, %rdi ; ATOM-NEXT: cmovnoq %rax, %rdi ; ATOM-NEXT: jmp __Znam ## TAILCALL +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test12: ; MCU: # BB#0: # %entry @@ -700,6 +721,7 @@ define i32 @test13(i32 %a, i32 %b) nounwind { ; GENERIC-NEXT: cmpl %esi, %edi ; GENERIC-NEXT: sbbl %eax, %eax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test13: ; ATOM: ## BB#0: @@ -710,6 +732,7 @@ define i32 @test13(i32 %a, i32 %b) nounwind { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test13: ; MCU: # BB#0: @@ -728,6 +751,7 @@ define i32 @test14(i32 %a, i32 %b) nounwind { ; GENERIC-NEXT: sbbl %eax, %eax ; GENERIC-NEXT: notl %eax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test14: ; ATOM: ## BB#0: @@ -737,6 +761,7 @@ define i32 @test14(i32 %a, i32 %b) nounwind { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test14: ; MCU: # BB#0: @@ -756,6 +781,7 @@ define i32 @test15(i32 %x) nounwind { ; GENERIC-NEXT: negl %edi ; GENERIC-NEXT: sbbl %eax, %eax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test15: ; ATOM: ## BB#0: ## %entry @@ -766,6 +792,7 @@ define i32 @test15(i32 %x) nounwind { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test15: ; MCU: # BB#0: # %entry @@ -817,6 +844,7 @@ define i16 @test17(i16 %x) nounwind { ; GENERIC-NEXT: negw %di ; GENERIC-NEXT: sbbw %ax, %ax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test17: ; ATOM: ## BB#0: ## %entry @@ -827,6 +855,7 @@ define i16 @test17(i16 %x) nounwind { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test17: ; MCU: # BB#0: # %entry @@ -846,6 +875,7 @@ define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind { ; GENERIC-NEXT: cmovgel %edx, %esi ; GENERIC-NEXT: movl %esi, %eax ; GENERIC-NEXT: retq +; GENERIC-NEXT: ## -- End function ; ; ATOM-LABEL: test18: ; ATOM: ## BB#0: @@ -855,6 +885,7 @@ define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind { ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: retq +; ATOM-NEXT: ## -- End function ; ; MCU-LABEL: test18: ; MCU: # BB#0: diff --git a/test/CodeGen/X86/shrink-compare.ll b/test/CodeGen/X86/shrink-compare.ll index 41f5d2d5be23..7f35258377ec 100644 --- a/test/CodeGen/X86/shrink-compare.ll +++ b/test/CodeGen/X86/shrink-compare.ll @@ -1,8 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s declare void @bar() define void @test1(i32* nocapture %X) nounwind minsize { +; CHECK-LABEL: test1: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $47, (%rdi) +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %tmp1 = load i32, i32* %X, align 4 %and = and i32 %tmp1, 255 @@ -15,11 +22,15 @@ if.then: if.end: ret void -; CHECK-LABEL: test1: -; CHECK: cmpb $47, (%{{rdi|rcx}}) } define void @test2(i32 %X) nounwind minsize { +; CHECK-LABEL: test2: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $47, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %and = and i32 %X, 255 %cmp = icmp eq i32 %and, 47 @@ -31,11 +42,15 @@ if.then: if.end: ret void -; CHECK-LABEL: test2: -; CHECK: cmpb $47, %{{dil|cl}} } define void @test3(i32 %X) nounwind minsize { +; CHECK-LABEL: test3: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $-1, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %and = and i32 %X, 255 %cmp = icmp eq i32 %and, 255 @@ -47,12 +62,22 @@ if.then: if.end: ret void -; CHECK-LABEL: test3: -; CHECK: cmpb $-1, %{{dil|cl}} } ; PR16083 define i1 @test4(i64 %a, i32 %b) { +; CHECK-LABEL: test4: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: testl %esi, %esi +; CHECK-NEXT: je .LBB3_1 +; CHECK-NEXT: # BB#2: # %lor.end +; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: retq +; CHECK-NEXT: .LBB3_1: # %lor.rhs +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: retq entry: %tobool = icmp ne i32 %b, 0 br i1 %tobool, label %lor.end, label %lor.rhs @@ -71,6 +96,16 @@ lor.end: ; preds = %lor.rhs, %entry ; PR16551 define void @test5(i32 %X) nounwind minsize { +; CHECK-LABEL: test5: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: movzbl x+{{.*}}(%rip), %eax +; CHECK-NEXT: shll $16, %eax +; CHECK-NEXT: movzwl x+{{.*}}(%rip), %ecx +; CHECK-NEXT: orl %eax, %ecx +; CHECK-NEXT: cmpl $1, %ecx +; CHECK-NEXT: jne bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %bf.load = load i56, i56* bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @x to i56*), align 4 %bf.lshr = lshr i56 %bf.load, 32 @@ -84,17 +119,16 @@ if.then: if.end: ret void - -; CHECK-LABEL: test5: -; CHECK-NOT: cmpl $1,{{.*}}x+4 -; CHECK: ret } -; CHECK-LABEL: test2_1: -; CHECK: movzbl -; CHECK: cmpl $256 -; CHECK: je bar define void @test2_1(i32 %X) nounwind minsize { +; CHECK-LABEL: test2_1: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: cmpl $256, %eax # imm = 0x100 +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %and = and i32 %X, 255 %cmp = icmp eq i32 %and, 256 @@ -108,9 +142,13 @@ if.end: ret void } -; CHECK-LABEL: test_sext_i8_icmp_1: -; CHECK: cmpb $1, %{{dil|cl}} define void @test_sext_i8_icmp_1(i8 %x) nounwind minsize { +; CHECK-LABEL: test_sext_i8_icmp_1: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $1, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %sext = sext i8 %x to i32 %cmp = icmp eq i32 %sext, 1 @@ -124,9 +162,13 @@ if.end: ret void } -; CHECK-LABEL: test_sext_i8_icmp_47: -; CHECK: cmpb $47, %{{dil|cl}} define void @test_sext_i8_icmp_47(i8 %x) nounwind minsize { +; CHECK-LABEL: test_sext_i8_icmp_47: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $47, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %sext = sext i8 %x to i32 %cmp = icmp eq i32 %sext, 47 @@ -140,9 +182,13 @@ if.end: ret void } -; CHECK-LABEL: test_sext_i8_icmp_127: -; CHECK: cmpb $127, %{{dil|cl}} define void @test_sext_i8_icmp_127(i8 %x) nounwind minsize { +; CHECK-LABEL: test_sext_i8_icmp_127: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $127, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %sext = sext i8 %x to i32 %cmp = icmp eq i32 %sext, 127 @@ -156,9 +202,13 @@ if.end: ret void } -; CHECK-LABEL: test_sext_i8_icmp_neg1: -; CHECK: cmpb $-1, %{{dil|cl}} define void @test_sext_i8_icmp_neg1(i8 %x) nounwind minsize { +; CHECK-LABEL: test_sext_i8_icmp_neg1: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $-1, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %sext = sext i8 %x to i32 %cmp = icmp eq i32 %sext, -1 @@ -172,9 +222,13 @@ if.end: ret void } -; CHECK-LABEL: test_sext_i8_icmp_neg2: -; CHECK: cmpb $-2, %{{dil|cl}} define void @test_sext_i8_icmp_neg2(i8 %x) nounwind minsize { +; CHECK-LABEL: test_sext_i8_icmp_neg2: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $-2, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %sext = sext i8 %x to i32 %cmp = icmp eq i32 %sext, -2 @@ -188,9 +242,13 @@ if.end: ret void } -; CHECK-LABEL: test_sext_i8_icmp_neg127: -; CHECK: cmpb $-127, %{{dil|cl}} define void @test_sext_i8_icmp_neg127(i8 %x) nounwind minsize { +; CHECK-LABEL: test_sext_i8_icmp_neg127: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $-127, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %sext = sext i8 %x to i32 %cmp = icmp eq i32 %sext, -127 @@ -204,9 +262,13 @@ if.end: ret void } -; CHECK-LABEL: test_sext_i8_icmp_neg128: -; CHECK: cmpb $-128, %{{dil|cl}} define void @test_sext_i8_icmp_neg128(i8 %x) nounwind minsize { +; CHECK-LABEL: test_sext_i8_icmp_neg128: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: cmpb $-128, %dil +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %sext = sext i8 %x to i32 %cmp = icmp eq i32 %sext, -128 @@ -220,11 +282,14 @@ if.end: ret void } -; CHECK-LABEL: test_sext_i8_icmp_255: -; CHECK: movb $1, -; CHECK: testb -; CHECK: je bar define void @test_sext_i8_icmp_255(i8 %x) nounwind minsize { +; CHECK-LABEL: test_sext_i8_icmp_255: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: je bar # TAILCALL +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: retq entry: %sext = sext i8 %x to i32 %cmp = icmp eq i32 %sext, 255 diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 6d51fb54f8b8..79b949a6ccb1 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -14,6 +14,7 @@ define void @t0(<8 x i16>* %dest, <8 x i16>* %old) nounwind { ; X64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3] ; X64-NEXT: movdqa %xmm0, (%rdi) ; X64-NEXT: retq +; X64-NEXT: ## -- End function entry: %tmp3 = load <8 x i16>, <8 x i16>* %old %tmp6 = shufflevector <8 x i16> %tmp3, @@ -32,6 +33,7 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; X64-NEXT: andps (%rdi), %xmm0 ; X64-NEXT: orps %xmm1, %xmm0 ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > @@ -48,6 +50,7 @@ define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind { ; X64-NEXT: pandn %xmm1, %xmm2 ; X64-NEXT: por %xmm2, %xmm0 ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 > ret <8 x i16> %tmp } @@ -61,6 +64,7 @@ define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind { ; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7] ; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 > ret <8 x i16> %tmp } @@ -73,6 +77,7 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind { ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0] ; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,7,4,7] ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 > ret <8 x i16> %tmp } @@ -83,6 +88,7 @@ define <8 x i16> @t5(<8 x i16> %A, <8 x i16> %B) nounwind { ; X64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; X64-NEXT: movdqa %xmm1, %xmm0 ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 0, i32 1, i32 10, i32 11, i32 2, i32 3 > ret <8 x i16> %tmp } @@ -92,6 +98,7 @@ define <8 x i16> @t6(<8 x i16> %A, <8 x i16> %B) nounwind { ; X64: ## BB#0: ; X64-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > ret <8 x i16> %tmp } @@ -102,6 +109,7 @@ define <8 x i16> @t7(<8 x i16> %A, <8 x i16> %B) nounwind { ; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,3,2,4,5,6,7] ; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,4,7] ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 > ret <8 x i16> %tmp } @@ -113,6 +121,7 @@ define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind { ; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,4,7] ; X64-NEXT: movdqa %xmm0, (%rdi) ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp = load <2 x i64>, <2 x i64>* %A %tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16> %tmp0 = extractelement <8 x i16> %tmp.upgrd.1, i32 0 @@ -143,6 +152,7 @@ define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind { ; X64-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0] ; X64-NEXT: movapd %xmm0, (%rdi) ; X64-NEXT: retq +; X64-NEXT: ## -- End function %tmp = load <4 x float>, <4 x float>* %r %tmp.upgrd.3 = bitcast <2 x i32>* %A to double* %tmp.upgrd.4 = load double, double* %tmp.upgrd.3 @@ -179,6 +189,7 @@ define void @t10() nounwind { ; X64-NEXT: movq _g2@{{.*}}(%rip), %rax ; X64-NEXT: movq %xmm0, (%rax) ; X64-NEXT: retq +; X64-NEXT: ## -- End function load <4 x i32>, <4 x i32>* @g1, align 16 bitcast <4 x i32> %1 to <8 x i16> shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef > @@ -196,6 +207,7 @@ define <8 x i16> @t11(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { ; X64-NEXT: psrld $16, %xmm0 ; X64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; X64-NEXT: retq +; X64-NEXT: ## -- End function entry: %tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > ret <8 x i16> %tmp7 @@ -209,6 +221,7 @@ define <8 x i16> @t12(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { ; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,3] ; X64-NEXT: retq +; X64-NEXT: ## -- End function entry: %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef > ret <8 x i16> %tmp9 @@ -222,6 +235,7 @@ define <8 x i16> @t13(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { ; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7] ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,3] ; X64-NEXT: retq +; X64-NEXT: ## -- End function entry: %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef > ret <8 x i16> %tmp9 @@ -234,6 +248,7 @@ define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { ; X64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; X64-NEXT: movdqa %xmm1, %xmm0 ; X64-NEXT: retq +; X64-NEXT: ## -- End function entry: %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef > ret <8 x i16> %tmp9 @@ -247,6 +262,7 @@ define <8 x i16> @t15(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { ; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,1,2,4,5,6,7] ; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; X64-NEXT: retq +; X64-NEXT: ## -- End function entry: %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef > ret <8 x i16> %tmp8 @@ -260,6 +276,7 @@ define <16 x i8> @t16(<16 x i8> %T0) nounwind readnone { ; X64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; X64-NEXT: movdqa %xmm1, %xmm0 ; X64-NEXT: retq +; X64-NEXT: ## -- End function entry: %tmp8 = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > @@ -275,6 +292,7 @@ define <4 x i32> @t17() nounwind { ; X64-NEXT: pxor %xmm1, %xmm1 ; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X64-NEXT: retq +; X64-NEXT: ## -- End function entry: %tmp1 = load <4 x float>, <4 x float>* undef, align 16 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3> diff --git a/test/CodeGen/X86/stack-folding-fp-avx1.ll b/test/CodeGen/X86/stack-folding-fp-avx1.ll index a00d47bb13e9..f937d484ce0d 100644 --- a/test/CodeGen/X86/stack-folding-fp-avx1.ll +++ b/test/CodeGen/X86/stack-folding-fp-avx1.ll @@ -1926,5 +1926,19 @@ define <8 x float> @stack_fold_xorps_ymm(<8 x float> %a0, <8 x float> %a1) { ret <8 x float> %6 } +define <4 x float> @stack_nofold_insertps(<8 x float> %a0, <8 x float> %a1) { +; Cannot fold this without changing the immediate. +; CHECK-LABEL: stack_nofold_insertps +; CHECK: 32-byte Spill +; CHECK: nop +; CHECK: 32-byte Reload +; CHECK: vinsertps $179, {{%xmm., %xmm., %xmm.}} + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"() + %v0 = shufflevector <8 x float> %a0, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %v1 = shufflevector <8 x float> %a1, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v0, <4 x float> %v1, i8 179) + ret <4 x float> %res +} + attributes #0 = { "unsafe-fp-math"="false" } attributes #1 = { "unsafe-fp-math"="true" } diff --git a/test/CodeGen/X86/statepoint-allocas.ll b/test/CodeGen/X86/statepoint-allocas.ll index 9f5418432abc..b8e5c82913a5 100644 --- a/test/CodeGen/X86/statepoint-allocas.ll +++ b/test/CodeGen/X86/statepoint-allocas.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; Check that we can lower a use of an alloca both as a deopt value (where the ; exact meaning is up to the consumer of the stackmap) and as an explicit spill ; slot used for GC. diff --git a/test/CodeGen/X86/statepoint-call-lowering.ll b/test/CodeGen/X86/statepoint-call-lowering.ll index 6e5cdd605122..bd2dd53b654a 100644 --- a/test/CodeGen/X86/statepoint-call-lowering.ll +++ b/test/CodeGen/X86/statepoint-call-lowering.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; This file contains a collection of basic tests to ensure we didn't ; screw up normal call lowering when there are no deopt or gc arguments. diff --git a/test/CodeGen/X86/statepoint-far-call.ll b/test/CodeGen/X86/statepoint-far-call.ll index dc49061f6461..9f9b684efae8 100644 --- a/test/CodeGen/X86/statepoint-far-call.ll +++ b/test/CodeGen/X86/statepoint-far-call.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; Test to check that Statepoints with X64 far-immediate targets ; are lowered correctly to an indirect call via a scratch register. diff --git a/test/CodeGen/X86/statepoint-forward.ll b/test/CodeGen/X86/statepoint-forward.ll index d97bc0c75602..bee4b5ac884e 100644 --- a/test/CodeGen/X86/statepoint-forward.ll +++ b/test/CodeGen/X86/statepoint-forward.ll @@ -1,5 +1,5 @@ ; RUN: opt -O3 -S < %s | FileCheck --check-prefix=CHECK-OPT %s -; RUN: llc < %s | FileCheck --check-prefix=CHECK-LLC %s +; RUN: llc -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LLC %s ; These tests are targetted at making sure we don't retain information ; about memory which contains potential gc references across a statepoint. ; They're carefully written to only outlaw forwarding of references. diff --git a/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll b/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll index 11dbe9e2e6c1..b88ca03805f2 100644 --- a/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll +++ b/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; This file contains a collection of basic tests to ensure we didn't ; screw up normal call lowering when a statepoint is a GC transition. diff --git a/test/CodeGen/X86/statepoint-invoke.ll b/test/CodeGen/X86/statepoint-invoke.ll index 3e8b8ca49f1d..29f8e3ed4f78 100644 --- a/test/CodeGen/X86/statepoint-invoke.ll +++ b/test/CodeGen/X86/statepoint-invoke.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s 2>&1 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s 2>&1 | FileCheck %s target triple = "x86_64-pc-linux-gnu" diff --git a/test/CodeGen/X86/statepoint-live-in.ll b/test/CodeGen/X86/statepoint-live-in.ll index abe2b0a7acc8..aaa4d7c8422a 100644 --- a/test/CodeGen/X86/statepoint-live-in.ll +++ b/test/CodeGen/X86/statepoint-live-in.ll @@ -1,4 +1,5 @@ -; RUN: llc -O3 < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: llc -verify-machineinstrs -O3 < %s | FileCheck %s target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" @@ -6,38 +7,70 @@ declare void @bar() #0 declare void @baz() define void @test1(i32 %a) gc "statepoint-example" { +; CHECK-LABEL: test1: +; CHECK: ## BB#0: ## %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: Lcfi0: +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: callq _bar +; CHECK-NEXT: Ltmp0: +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq +; entry: ; We expect the argument to be passed in an extra register to bar -; CHECK-LABEL: test1 -; CHECK: pushq %rax -; CHECK-NEXT: Lcfi0: -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: callq _bar %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a) ret void } define void @test2(i32 %a, i32 %b) gc "statepoint-example" { +; CHECK-LABEL: test2: +; CHECK: ## BB#0: ## %entry +; CHECK-NEXT: pushq %rbp +; CHECK-NEXT: Lcfi1: +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: Lcfi2: +; CHECK-NEXT: .cfi_def_cfa_offset 24 +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: Lcfi3: +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: Lcfi4: +; CHECK-NEXT: .cfi_offset %rbx, -24 +; CHECK-NEXT: Lcfi5: +; CHECK-NEXT: .cfi_offset %rbp, -16 +; CHECK-NEXT: movl %esi, %ebx +; CHECK-NEXT: movl %edi, %ebp +; CHECK-NEXT: callq _bar +; CHECK-NEXT: Ltmp1: +; CHECK-NEXT: callq _bar +; CHECK-NEXT: Ltmp2: +; CHECK-NEXT: addq $8, %rsp +; CHECK-NEXT: popq %rbx +; CHECK-NEXT: popq %rbp +; CHECK-NEXT: retq +; entry: ; Because the first call clobbers esi, we have to move the values into ; new registers. Note that they stay in the registers for both calls. -; CHECK-LABEL: @test2 -; CHECK: movl %esi, %ebx -; CHECK-NEXT: movl %edi, %ebp -; CHECK-NEXT: callq _bar call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 2, i32 %a, i32 %b) call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 2, i32 %b, i32 %a) ret void } define void @test3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i) gc "statepoint-example" { +; CHECK-LABEL: test3: +; CHECK: ## BB#0: ## %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: Lcfi6: +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: callq _bar +; CHECK-NEXT: Ltmp3: +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq +; entry: -; TODO: We should have folded the reload into the statepoint. -; CHECK-LABEL: @test3 -; CHECK: pushq %rax -; CHECK-NEXT: Lcfi -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: callq _bar +; We directly reference the argument slot %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 9, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i) ret void } @@ -47,25 +80,39 @@ entry: ; also ends up being a good test of whether we can fold loads from immutable ; stack slots into the statepoint. define void @test4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q, i32 %r, i32 %s, i32 %t, i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z) gc "statepoint-example" { +; CHECK-LABEL: test4: +; CHECK: ## BB#0: ## %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: Lcfi7: +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: callq _bar +; CHECK-NEXT: Ltmp4: +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq +; entry: -; CHECK-LABEL: test4 -; CHECK: pushq %rax -; CHECK-NEXT: Lcfi -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: callq _bar %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 26, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q, i32 %r, i32 %s, i32 %t, i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z) ret void } ; A live-through gc-value must be spilled even if it is also a live-in deopt ; value. For live-in, we could technically report the register copy, but from -; a code quality perspective it's better to reuse the required stack slot so +; a code quality perspective it's better to reuse the required stack slot so ; as to put less stress on the register allocator for no benefit. define i32 addrspace(1)* @test5(i32 %a, i32 addrspace(1)* %p) gc "statepoint-example" { +; CHECK-LABEL: test5: +; CHECK: ## BB#0: ## %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: Lcfi8: +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: movq %rsi, (%rsp) +; CHECK-NEXT: callq _bar +; CHECK-NEXT: Ltmp5: +; CHECK-NEXT: movq (%rsp), %rax +; CHECK-NEXT: popq %rcx +; CHECK-NEXT: retq +; entry: -; CHECK-LABEL: test5 -; CHECK: movq %rsi, (%rsp) -; CHECK-NEXT: callq _bar %token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a, i32 addrspace(1)* %p, i32 addrspace(1)* %p) %p2 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %token, i32 9, i32 9) ret i32 addrspace(1)* %p2 @@ -73,14 +120,27 @@ entry: ; Show the interaction of live-through spilling followed by live-in. define void @test6(i32 %a) gc "statepoint-example" { +; CHECK-LABEL: test6: +; CHECK: ## BB#0: ## %entry +; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: Lcfi9: +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: subq $16, %rsp +; CHECK-NEXT: Lcfi10: +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: Lcfi11: +; CHECK-NEXT: .cfi_offset %rbx, -16 +; CHECK-NEXT: movl %edi, %ebx +; CHECK-NEXT: movl %ebx, {{[0-9]+}}(%rsp) +; CHECK-NEXT: callq _baz +; CHECK-NEXT: Ltmp6: +; CHECK-NEXT: callq _bar +; CHECK-NEXT: Ltmp7: +; CHECK-NEXT: addq $16, %rsp +; CHECK-NEXT: popq %rbx +; CHECK-NEXT: retq +; entry: -; TODO: We could have reused the previous spill slot at zero additional cost. -; CHECK-LABEL: test6 -; CHECK: movl %edi, %ebx -; CHECK: movl %ebx, 12(%rsp) -; CHECK-NEXT: callq _baz -; CHECK-NEXT: Ltmp -; CHECK-NEXT: callq _bar call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @baz, i32 0, i32 0, i32 0, i32 1, i32 %a) call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a) ret void diff --git a/test/CodeGen/X86/statepoint-stack-usage.ll b/test/CodeGen/X86/statepoint-stack-usage.ll index 5c27898f284a..b16426eae3d5 100644 --- a/test/CodeGen/X86/statepoint-stack-usage.ll +++ b/test/CodeGen/X86/statepoint-stack-usage.ll @@ -1,4 +1,4 @@ -; RUN: llc -stack-symbol-ordering=0 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -stack-symbol-ordering=0 < %s | FileCheck %s target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-linux-gnu" diff --git a/test/CodeGen/X86/statepoint-stackmap-format.ll b/test/CodeGen/X86/statepoint-stackmap-format.ll index 0506381b9ec2..966f66815f92 100644 --- a/test/CodeGen/X86/statepoint-stackmap-format.ll +++ b/test/CodeGen/X86/statepoint-stackmap-format.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -stack-symbol-ordering=0 -mtriple="x86_64-pc-linux-gnu" | FileCheck %s -; RUN: llc < %s -stack-symbol-ordering=0 -mtriple="x86_64-pc-unknown-elf" | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -stack-symbol-ordering=0 -mtriple="x86_64-pc-linux-gnu" | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -stack-symbol-ordering=0 -mtriple="x86_64-pc-unknown-elf" | FileCheck %s ; This test is a sanity check to ensure statepoints are generating StackMap ; sections correctly. This is not intended to be a rigorous test of the diff --git a/test/CodeGen/X86/statepoint-uniqueing.ll b/test/CodeGen/X86/statepoint-uniqueing.ll index e791bc6b2333..a5fa1f2d99c9 100644 --- a/test/CodeGen/X86/statepoint-uniqueing.ll +++ b/test/CodeGen/X86/statepoint-uniqueing.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; Checks for a crash we had when two gc.relocate calls would ; relocating identical values diff --git a/test/CodeGen/X86/statepoint-vector-bad-spill.ll b/test/CodeGen/X86/statepoint-vector-bad-spill.ll index 848988589cb0..7c55491bb1be 100644 --- a/test/CodeGen/X86/statepoint-vector-bad-spill.ll +++ b/test/CodeGen/X86/statepoint-vector-bad-spill.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -O3 < %s | FileCheck %s ; This is checking for a crash. diff --git a/test/CodeGen/X86/statepoint-vector.ll b/test/CodeGen/X86/statepoint-vector.ll index 000e88742880..5bc8f983ff06 100644 --- a/test/CodeGen/X86/statepoint-vector.ll +++ b/test/CodeGen/X86/statepoint-vector.ll @@ -1,4 +1,4 @@ -; RUN: llc -stack-symbol-ordering=0 -mcpu=nehalem -debug-only=stackmaps < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -stack-symbol-ordering=0 -mcpu=nehalem -debug-only=stackmaps < %s | FileCheck %s ; REQUIRES: asserts target triple = "x86_64-pc-linux-gnu" diff --git a/test/CodeGen/X86/vector-unsigned-cmp.ll b/test/CodeGen/X86/vector-unsigned-cmp.ll new file mode 100644 index 000000000000..fc246669992c --- /dev/null +++ b/test/CodeGen/X86/vector-unsigned-cmp.ll @@ -0,0 +1,519 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 + +; PR33276 - https://bugs.llvm.org/show_bug.cgi?id=33276 +; If both operands of an unsigned icmp are known non-negative, then +; we don't need to flip the sign bits in order to map to signed pcmpgt*. + +define <2 x i1> @ugt_v2i64(<2 x i64> %x, <2 x i64> %y) { +; SSE-LABEL: ugt_v2i64: +; SSE: # BB#0: +; SSE-NEXT: psrlq $1, %xmm0 +; SSE-NEXT: psrlq $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE-NEXT: pxor %xmm2, %xmm1 +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: pcmpgtd %xmm1, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; SSE-NEXT: pand %xmm3, %xmm1 +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] +; SSE-NEXT: por %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ugt_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlq $1, %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; AVX-NEXT: vpor %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <2 x i64> %x, <i64 1, i64 1> + %sh2 = lshr <2 x i64> %y, <i64 1, i64 1> + %cmp = icmp ugt <2 x i64> %sh1, %sh2 + ret <2 x i1> %cmp +} + +define <2 x i1> @ult_v2i64(<2 x i64> %x, <2 x i64> %y) { +; SSE-LABEL: ult_v2i64: +; SSE: # BB#0: +; SSE-NEXT: psrlq $1, %xmm0 +; SSE-NEXT: psrlq $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: pxor %xmm2, %xmm1 +; SSE-NEXT: movdqa %xmm1, %xmm2 +; SSE-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm0, %xmm1 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; SSE-NEXT: pand %xmm3, %xmm1 +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] +; SSE-NEXT: por %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ult_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlq $1, %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; AVX-NEXT: vpor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpor %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <2 x i64> %x, <i64 1, i64 1> + %sh2 = lshr <2 x i64> %y, <i64 1, i64 1> + %cmp = icmp ult <2 x i64> %sh1, %sh2 + ret <2 x i1> %cmp +} + +define <2 x i1> @uge_v2i64(<2 x i64> %x, <2 x i64> %y) { +; SSE-LABEL: uge_v2i64: +; SSE: # BB#0: +; SSE-NEXT: psrlq $1, %xmm0 +; SSE-NEXT: psrlq $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: pxor %xmm2, %xmm1 +; SSE-NEXT: movdqa %xmm1, %xmm2 +; SSE-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm0, %xmm1 +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] +; SSE-NEXT: pand %xmm3, %xmm0 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] +; SSE-NEXT: por %xmm0, %xmm1 +; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: pxor %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: uge_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlq $1, %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; AVX-NEXT: vpor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpor %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0 +; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <2 x i64> %x, <i64 1, i64 1> + %sh2 = lshr <2 x i64> %y, <i64 1, i64 1> + %cmp = icmp uge <2 x i64> %sh1, %sh2 + ret <2 x i1> %cmp +} + +define <2 x i1> @ule_v2i64(<2 x i64> %x, <2 x i64> %y) { +; SSE-LABEL: ule_v2i64: +; SSE: # BB#0: +; SSE-NEXT: psrlq $1, %xmm0 +; SSE-NEXT: psrlq $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE-NEXT: pxor %xmm2, %xmm1 +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: pcmpgtd %xmm1, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE-NEXT: pand %xmm3, %xmm0 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] +; SSE-NEXT: por %xmm0, %xmm1 +; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: pxor %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ule_v2i64: +; AVX: # BB#0: +; AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlq $1, %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; AVX-NEXT: vpor %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <2 x i64> %x, <i64 1, i64 1> + %sh2 = lshr <2 x i64> %y, <i64 1, i64 1> + %cmp = icmp ule <2 x i64> %sh1, %sh2 + ret <2 x i1> %cmp +} + +define <4 x i1> @ugt_v4i32(<4 x i32> %x, <4 x i32> %y) { +; SSE-LABEL: ugt_v4i32: +; SSE: # BB#0: +; SSE-NEXT: psrld $1, %xmm0 +; SSE-NEXT: psrld $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE-NEXT: pxor %xmm2, %xmm1 +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: pcmpgtd %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: ugt_v4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: ugt_v4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrld $1, %xmm0, %xmm0 +; AVX2-NEXT: vpsrld $1, %xmm1, %xmm1 +; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %sh1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1> + %sh2 = lshr <4 x i32> %y, <i32 1, i32 1, i32 1, i32 1> + %cmp = icmp ugt <4 x i32> %sh1, %sh2 + ret <4 x i1> %cmp +} + +define <4 x i1> @ult_v4i32(<4 x i32> %x, <4 x i32> %y) { +; SSE-LABEL: ult_v4i32: +; SSE: # BB#0: +; SSE-NEXT: psrld $1, %xmm0 +; SSE-NEXT: psrld $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: pxor %xmm1, %xmm2 +; SSE-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: ult_v4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0 +; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: ult_v4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vpsrld $1, %xmm0, %xmm0 +; AVX2-NEXT: vpsrld $1, %xmm1, %xmm1 +; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: retq + %sh1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1> + %sh2 = lshr <4 x i32> %y, <i32 1, i32 1, i32 1, i32 1> + %cmp = icmp ult <4 x i32> %sh1, %sh2 + ret <4 x i1> %cmp +} + +define <4 x i1> @uge_v4i32(<4 x i32> %x, <4 x i32> %y) { +; SSE2-LABEL: uge_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: psrld $1, %xmm0 +; SSE2-NEXT: psrld $1, %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE2-NEXT: pxor %xmm2, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm2 +; SSE2-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE2-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE2-NEXT: pxor %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: uge_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: psrld $1, %xmm0 +; SSE41-NEXT: psrld $1, %xmm1 +; SSE41-NEXT: pmaxud %xmm0, %xmm1 +; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: uge_v4i32: +; AVX: # BB#0: +; AVX-NEXT: vpsrld $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrld $1, %xmm1, %xmm1 +; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1> + %sh2 = lshr <4 x i32> %y, <i32 1, i32 1, i32 1, i32 1> + %cmp = icmp uge <4 x i32> %sh1, %sh2 + ret <4 x i1> %cmp +} + +define <4 x i1> @ule_v4i32(<4 x i32> %x, <4 x i32> %y) { +; SSE2-LABEL: ule_v4i32: +; SSE2: # BB#0: +; SSE2-NEXT: psrld $1, %xmm0 +; SSE2-NEXT: psrld $1, %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; SSE2-NEXT: pxor %xmm2, %xmm1 +; SSE2-NEXT: pxor %xmm2, %xmm0 +; SSE2-NEXT: pcmpgtd %xmm1, %xmm0 +; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: ule_v4i32: +; SSE41: # BB#0: +; SSE41-NEXT: psrld $1, %xmm0 +; SSE41-NEXT: psrld $1, %xmm1 +; SSE41-NEXT: pminud %xmm0, %xmm1 +; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: ule_v4i32: +; AVX: # BB#0: +; AVX-NEXT: vpsrld $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrld $1, %xmm1, %xmm1 +; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1> + %sh2 = lshr <4 x i32> %y, <i32 1, i32 1, i32 1, i32 1> + %cmp = icmp ule <4 x i32> %sh1, %sh2 + ret <4 x i1> %cmp +} + +define <8 x i1> @ugt_v8i16(<8 x i16> %x, <8 x i16> %y) { +; SSE-LABEL: ugt_v8i16: +; SSE: # BB#0: +; SSE-NEXT: psrlw $1, %xmm0 +; SSE-NEXT: psrlw $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] +; SSE-NEXT: pxor %xmm2, %xmm1 +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: pcmpgtw %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ugt_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] +; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %sh2 = lshr <8 x i16> %y, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %cmp = icmp ugt <8 x i16> %sh1, %sh2 + ret <8 x i1> %cmp +} + +define <8 x i1> @ult_v8i16(<8 x i16> %x, <8 x i16> %y) { +; SSE-LABEL: ult_v8i16: +; SSE: # BB#0: +; SSE-NEXT: psrlw $1, %xmm0 +; SSE-NEXT: psrlw $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: pxor %xmm1, %xmm2 +; SSE-NEXT: pcmpgtw %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ult_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] +; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %sh2 = lshr <8 x i16> %y, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %cmp = icmp ult <8 x i16> %sh1, %sh2 + ret <8 x i1> %cmp +} + +define <8 x i1> @uge_v8i16(<8 x i16> %x, <8 x i16> %y) { +; SSE2-LABEL: uge_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: psrlw $1, %xmm0 +; SSE2-NEXT: psrlw $1, %xmm1 +; SSE2-NEXT: psubusw %xmm0, %xmm1 +; SSE2-NEXT: pxor %xmm0, %xmm0 +; SSE2-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: uge_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: psrlw $1, %xmm0 +; SSE41-NEXT: psrlw $1, %xmm1 +; SSE41-NEXT: pmaxuw %xmm0, %xmm1 +; SSE41-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: uge_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %sh2 = lshr <8 x i16> %y, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %cmp = icmp uge <8 x i16> %sh1, %sh2 + ret <8 x i1> %cmp +} + +define <8 x i1> @ule_v8i16(<8 x i16> %x, <8 x i16> %y) { +; SSE2-LABEL: ule_v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: psrlw $1, %xmm0 +; SSE2-NEXT: psrlw $1, %xmm1 +; SSE2-NEXT: psubusw %xmm1, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: ule_v8i16: +; SSE41: # BB#0: +; SSE41-NEXT: psrlw $1, %xmm0 +; SSE41-NEXT: psrlw $1, %xmm1 +; SSE41-NEXT: pminuw %xmm0, %xmm1 +; SSE41-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: ule_v8i16: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %sh2 = lshr <8 x i16> %y, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %cmp = icmp ule <8 x i16> %sh1, %sh2 + ret <8 x i1> %cmp +} + +define <16 x i1> @ugt_v16i8(<16 x i8> %x, <16 x i8> %y) { +; SSE-LABEL: ugt_v16i8: +; SSE: # BB#0: +; SSE-NEXT: psrlw $1, %xmm0 +; SSE-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE-NEXT: psrlw $1, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] +; SSE-NEXT: por %xmm2, %xmm1 +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: pcmpgtb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ugt_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] +; AVX-NEXT: vpor %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %sh2 = lshr <16 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %cmp = icmp ugt <16 x i8> %sh1, %sh2 + ret <16 x i1> %cmp +} + +define <16 x i1> @ult_v16i8(<16 x i8> %x, <16 x i8> %y) { +; SSE-LABEL: ult_v16i8: +; SSE: # BB#0: +; SSE-NEXT: psrlw $1, %xmm0 +; SSE-NEXT: psrlw $1, %xmm1 +; SSE-NEXT: pand {{.*}}(%rip), %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] +; SSE-NEXT: por %xmm2, %xmm0 +; SSE-NEXT: pxor %xmm1, %xmm2 +; SSE-NEXT: pcmpgtb %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ult_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] +; AVX-NEXT: vpor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %sh2 = lshr <16 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %cmp = icmp ult <16 x i8> %sh1, %sh2 + ret <16 x i1> %cmp +} + +define <16 x i1> @uge_v16i8(<16 x i8> %x, <16 x i8> %y) { +; SSE-LABEL: uge_v16i8: +; SSE: # BB#0: +; SSE-NEXT: psrlw $1, %xmm0 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; SSE-NEXT: pand %xmm2, %xmm0 +; SSE-NEXT: psrlw $1, %xmm1 +; SSE-NEXT: pand %xmm2, %xmm1 +; SSE-NEXT: pmaxub %xmm0, %xmm1 +; SSE-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: uge_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX-NEXT: vpand %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %sh2 = lshr <16 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %cmp = icmp uge <16 x i8> %sh1, %sh2 + ret <16 x i1> %cmp +} + +define <16 x i1> @ule_v16i8(<16 x i8> %x, <16 x i8> %y) { +; SSE-LABEL: ule_v16i8: +; SSE: # BB#0: +; SSE-NEXT: psrlw $1, %xmm0 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; SSE-NEXT: pand %xmm2, %xmm0 +; SSE-NEXT: psrlw $1, %xmm1 +; SSE-NEXT: pand %xmm2, %xmm1 +; SSE-NEXT: pminub %xmm0, %xmm1 +; SSE-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ule_v16i8: +; AVX: # BB#0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX-NEXT: vpand %xmm2, %xmm1, %xmm1 +; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %sh1 = lshr <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %sh2 = lshr <16 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %cmp = icmp ule <16 x i8> %sh1, %sh2 + ret <16 x i1> %cmp +} + diff --git a/test/CodeGen/X86/wide-fma-contraction.ll b/test/CodeGen/X86/wide-fma-contraction.ll index f51f917fbac9..99e03c891c00 100644 --- a/test/CodeGen/X86/wide-fma-contraction.ll +++ b/test/CodeGen/X86/wide-fma-contraction.ll @@ -1,26 +1,48 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma -mtriple=x86_64-apple-darwin < %s | FileCheck %s ; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA ; CHECK-LABEL: fmafunc ; CHECK-NOFMA-LABEL: fmafunc define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) { +; CHECK-LABEL: fmafunc: +; CHECK: ## BB#0: +; CHECK-NEXT: pushl %ebp +; CHECK-NEXT: Lcfi0: +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: Lcfi1: +; CHECK-NEXT: .cfi_offset %ebp, -8 +; CHECK-NEXT: movl %esp, %ebp +; CHECK-NEXT: Lcfi2: +; CHECK-NEXT: .cfi_def_cfa_register %ebp +; CHECK-NEXT: andl $-32, %esp +; CHECK-NEXT: subl $32, %esp +; CHECK-NEXT: vfmaddps 8(%ebp), %ymm2, %ymm0, %ymm0 +; CHECK-NEXT: vfmaddps 40(%ebp), %ymm3, %ymm1, %ymm1 +; CHECK-NEXT: movl %ebp, %esp +; CHECK-NEXT: popl %ebp +; CHECK-NEXT: retl +; +; CHECK-NOFMA-LABEL: fmafunc: +; CHECK-NOFMA: ## BB#0: +; CHECK-NOFMA-NEXT: pushl %ebp +; CHECK-NOFMA-NEXT: Lcfi0: +; CHECK-NOFMA-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NOFMA-NEXT: Lcfi1: +; CHECK-NOFMA-NEXT: .cfi_offset %ebp, -8 +; CHECK-NOFMA-NEXT: movl %esp, %ebp +; CHECK-NOFMA-NEXT: Lcfi2: +; CHECK-NOFMA-NEXT: .cfi_def_cfa_register %ebp +; CHECK-NOFMA-NEXT: andl $-32, %esp +; CHECK-NOFMA-NEXT: subl $32, %esp +; CHECK-NOFMA-NEXT: vmulps %ymm2, %ymm0, %ymm0 +; CHECK-NOFMA-NEXT: vaddps 8(%ebp), %ymm0, %ymm0 +; CHECK-NOFMA-NEXT: vmulps %ymm3, %ymm1, %ymm1 +; CHECK-NOFMA-NEXT: vaddps 40(%ebp), %ymm1, %ymm1 +; CHECK-NOFMA-NEXT: movl %ebp, %esp +; CHECK-NOFMA-NEXT: popl %ebp +; CHECK-NOFMA-NEXT: retl -; CHECK-NOT: vmulps -; CHECK-NOT: vaddps -; CHECK: vfmaddps -; CHECK-NOT: vmulps -; CHECK-NOT: vaddps -; CHECK: vfmaddps -; CHECK-NOT: vmulps -; CHECK-NOT: vaddps - -; CHECK-NOFMA-NOT: calll -; CHECK-NOFMA: vmulps -; CHECK-NOFMA: vaddps -; CHECK-NOFMA-NOT: calll -; CHECK-NOFMA: vmulps -; CHECK-NOFMA: vaddps -; CHECK-NOFMA-NOT: calll %ret = tail call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c) ret <16 x float> %ret diff --git a/test/CodeGen/X86/xor-icmp.ll b/test/CodeGen/X86/xor-icmp.ll index 397e5bc10f5b..cd58dd1e7604 100644 --- a/test/CodeGen/X86/xor-icmp.ll +++ b/test/CodeGen/X86/xor-icmp.ll @@ -1,21 +1,33 @@ -; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 -; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s -check-prefix=X64 ; rdar://7367229 define i32 @t(i32 %a, i32 %b) nounwind ssp { +; X32-LABEL: t: +; X32: # BB#0: # %entry +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: xorb {{[0-9]+}}(%esp), %al +; X32-NEXT: testb $64, %al +; X32-NEXT: je .LBB0_1 +; X32-NEXT: # BB#2: # %bb1 +; X32-NEXT: jmp bar # TAILCALL +; X32-NEXT: .LBB0_1: # %bb +; X32-NEXT: jmp foo # TAILCALL +; +; X64-LABEL: t: +; X64: # BB#0: # %entry +; X64-NEXT: movl %edi, %eax +; X64-NEXT: xorl %esi, %eax +; X64-NEXT: testb $64, %ah +; X64-NEXT: je .LBB0_1 +; X64-NEXT: # BB#2: # %bb1 +; X64-NEXT: xorl %eax, %eax +; X64-NEXT: jmp bar # TAILCALL +; X64-NEXT: .LBB0_1: # %bb +; X64-NEXT: xorl %eax, %eax +; X64-NEXT: jmp foo # TAILCALL entry: -; X32-LABEL: t: -; X32: xorb -; X32-NOT: andb -; X32-NOT: shrb -; X32: testb $64 -; X32: je - -; X64-LABEL: t: -; X64-NOT: setne -; X64: xorl -; X64: testb $64 -; X64: je %0 = and i32 %a, 16384 %1 = icmp ne i32 %0, 0 %2 = and i32 %b, 16384 @@ -38,20 +50,32 @@ declare i32 @bar(...) define i32 @t2(i32 %x, i32 %y) nounwind ssp { ; X32-LABEL: t2: -; X32: cmpl -; X32: sete -; X32: cmpl -; X32: sete -; X32-NOT: xor -; X32: je - +; X32: # BB#0: # %entry +; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp) +; X32-NEXT: sete %al +; X32-NEXT: cmpl $0, {{[0-9]+}}(%esp) +; X32-NEXT: sete %cl +; X32-NEXT: cmpb %al, %cl +; X32-NEXT: je .LBB1_1 +; X32-NEXT: # BB#2: # %bb +; X32-NEXT: jmp foo # TAILCALL +; X32-NEXT: .LBB1_1: # %return +; X32-NEXT: retl +; ; X64-LABEL: t2: -; X64: testl -; X64: sete -; X64: testl -; X64: sete -; X64-NOT: xor -; X64: je +; X64: # BB#0: # %entry +; X64-NEXT: testl %edi, %edi +; X64-NEXT: sete %al +; X64-NEXT: testl %esi, %esi +; X64-NEXT: sete %cl +; X64-NEXT: cmpb %al, %cl +; X64-NEXT: je .LBB1_1 +; X64-NEXT: # BB#2: # %bb +; X64-NEXT: xorl %eax, %eax +; X64-NEXT: jmp foo # TAILCALL +; X64-NEXT: .LBB1_1: # %return +; X64-NEXT: retq + entry: %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1] %1 = icmp eq i32 %y, 0 ; <i1> [#uses=1] |