diff options
| author | Roman Divacky <rdivacky@FreeBSD.org> | 2010-04-02 08:54:30 +0000 |
|---|---|---|
| committer | Roman Divacky <rdivacky@FreeBSD.org> | 2010-04-02 08:54:30 +0000 |
| commit | 104bd8179fb5f6551c65c94ebcd0a4918b060189 (patch) | |
| tree | cf5763d092b81cecc168fa28032247ee495d06e2 /test/CodeGen | |
| parent | 2f12f10af369d468b14617276446166383d692ed (diff) | |
Notes
Diffstat (limited to 'test/CodeGen')
68 files changed, 495 insertions, 171 deletions
diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll index e5b5791b3cda..f03282bdab7f 100644 --- a/test/CodeGen/ARM/fabss.ll +++ b/test/CodeGen/ARM/fabss.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index db18a86eccd8..749690e98d0f 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll index a5c86bf26343..0c3149579297 100644 --- a/test/CodeGen/ARM/fdivs.ll +++ b/test/CodeGen/ARM/fdivs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index 904a58739370..f8b47b5bac0d 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll index 7b9e029b676e..7a70543dee6c 100644 --- a/test/CodeGen/ARM/fmscs.ll +++ b/test/CodeGen/ARM/fmscs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index d3c9c82e9745..ef4e3e52818e 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll index d6c22f14a4ca..c15005e6e8ab 100644 --- a/test/CodeGen/ARM/fnegs.ll +++ b/test/CodeGen/ARM/fnegs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll index 724947ea04d3..1d1d06a70ea6 100644 --- a/test/CodeGen/ARM/fnmacs.ll +++ b/test/CodeGen/ARM/fnmacs.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEONFP +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEONFP define float @test(float %acc, float %a, float %b) { entry: diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll index ad2188218e4d..6b7cefa6414d 100644 --- a/test/CodeGen/ARM/fnmscs.ll +++ b/test/CodeGen/ARM/fnmscs.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll index 2adac78cf806..1ef9f7f32164 100644 --- a/test/CodeGen/ARM/fp_convert.ll +++ b/test/CodeGen/ARM/fp_convert.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2 diff --git a/test/CodeGen/ARM/fsubs.ll b/test/CodeGen/ARM/fsubs.ll index ae98be307892..bea8d5f4f30b 100644 --- a/test/CodeGen/ARM/fsubs.ll +++ b/test/CodeGen/ARM/fsubs.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 define float @test(float %a, float %b) { entry: diff --git a/test/CodeGen/CellSPU/bigstack.ll b/test/CodeGen/CellSPU/bigstack.ll new file mode 100644 index 000000000000..5483f463732b --- /dev/null +++ b/test/CodeGen/CellSPU/bigstack.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=cellspu -o %t1.s +; RUN: grep lqx %t1.s | count 4 +; RUN: grep il %t1.s | grep -v file | count 7 +; RUN: grep stqx %t1.s | count 2 + +define i32 @bigstack() nounwind { +entry: + %avar = alloca i32 + %big_data = alloca [2048 x i32] + store i32 3840, i32* %avar, align 4 + br label %return + +return: + %retval = load i32* %avar + ret i32 %retval +} + diff --git a/test/CodeGen/Generic/2010-ZeroSizedArg.ll b/test/CodeGen/Generic/2010-ZeroSizedArg.ll new file mode 100644 index 000000000000..ba40bd08e8e9 --- /dev/null +++ b/test/CodeGen/Generic/2010-ZeroSizedArg.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s +; PR4975 + +%0 = type <{ [0 x i32] }> +%union.T0 = type { } + +@.str = private constant [1 x i8] c" " + +define arm_apcscc void @t(%0) nounwind { +entry: + %arg0 = alloca %union.T0 + %1 = bitcast %union.T0* %arg0 to %0* + store %0 %0, %0* %1, align 1 + ret void +} + +declare arm_apcscc i32 @printf(i8*, ...) diff --git a/test/CodeGen/Generic/addr-label.ll b/test/CodeGen/Generic/addr-label.ll index 51741110e072..0dbe5021bbf0 100644 --- a/test/CodeGen/Generic/addr-label.ll +++ b/test/CodeGen/Generic/addr-label.ll @@ -56,3 +56,26 @@ ret: ret i32 -1 } + +; PR6673 + +define i64 @test4a() { + %target = bitcast i8* blockaddress(@test4b, %usermain) to i8* + %ret = call i64 @test4b(i8* %target) + + ret i64 %ret +} + +define i64 @test4b(i8* %Code) { +entry: + indirectbr i8* %Code, [label %usermain] +usermain: + br label %label_line_0 + +label_line_0: + br label %label_line_1 + +label_line_1: + %target = ptrtoint i8* blockaddress(@test4b, %label_line_0) to i64 + ret i64 %target +} diff --git a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll index b508026c21f6..5b5e11f2df0c 100644 --- a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll +++ b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 | FileCheck %s +; XFAIL: vg_leak target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-f32:32:32" target triple = "pic16-" diff --git a/test/CodeGen/PIC16/2009-11-20-NewNode.ll b/test/CodeGen/PIC16/2009-11-20-NewNode.ll index d68f0f41c4a5..f9d66ca63471 100644 --- a/test/CodeGen/PIC16/2009-11-20-NewNode.ll +++ b/test/CodeGen/PIC16/2009-11-20-NewNode.ll @@ -1,5 +1,6 @@ ; RUN: llc -march=pic16 < %s ; PR5558 +; XFAIL: vg_leak define i64 @_strtoll_r(i16 %base) nounwind { entry: diff --git a/test/CodeGen/PIC16/C16-15.ll b/test/CodeGen/PIC16/C16-15.ll index 5ca2d4a9bd63..020b0dd6743e 100644 --- a/test/CodeGen/PIC16/C16-15.ll +++ b/test/CodeGen/PIC16/C16-15.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 | grep "extern" | grep "@.lib.unordered.f32" | count 3 +; XFAIL: vg_leak @pc = global i8* inttoptr (i64 160 to i8*), align 1 ; <i8**> [#uses=2] @aa = common global i16 0, align 1 ; <i16*> [#uses=0] diff --git a/test/CodeGen/PIC16/global-in-user-section.ll b/test/CodeGen/PIC16/global-in-user-section.ll index 74c9d9d256cd..6cdb64864ad5 100644 --- a/test/CodeGen/PIC16/global-in-user-section.ll +++ b/test/CodeGen/PIC16/global-in-user-section.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 | FileCheck %s +; XFAIL: vg_leak @G1 = common global i16 0, section "usersection", align 1 ; CHECK: usersection UDATA diff --git a/test/CodeGen/PIC16/globals.ll b/test/CodeGen/PIC16/globals.ll index 432c291078d3..3ee2e25265d3 100644 --- a/test/CodeGen/PIC16/globals.ll +++ b/test/CodeGen/PIC16/globals.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 | FileCheck %s +; XFAIL: vg_leak @G1 = global i32 4712, section "Address=412" ; CHECK: @G1.412..user_section.# IDATA 412 diff --git a/test/CodeGen/PIC16/sext.ll b/test/CodeGen/PIC16/sext.ll index b49925ffb7c3..e51a54287ce6 100644 --- a/test/CodeGen/PIC16/sext.ll +++ b/test/CodeGen/PIC16/sext.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=pic16 +; XFAIL: vg_leak @main.auto.c = internal global i8 0 ; <i8*> [#uses=1] diff --git a/test/CodeGen/PowerPC/2010-04-01-MachineCSEBug.ll b/test/CodeGen/PowerPC/2010-04-01-MachineCSEBug.ll new file mode 100644 index 000000000000..8fd05502ba86 --- /dev/null +++ b/test/CodeGen/PowerPC/2010-04-01-MachineCSEBug.ll @@ -0,0 +1,70 @@ +; RUN: llc < %s -mtriple=powerpc-apple-darwin10.0 +; rdar://7819990 + +%0 = type { i32 } +%1 = type { i64 } +%struct.Buffer = type { [1024 x i8], i64, i64, i64 } +%struct.InStream = type { %struct.Buffer, %0, %1, i32*, %struct.InStreamMethods* } +%struct.InStreamMethods = type { void (%struct.InStream*, i8*, i32)*, void (%struct.InStream*, i64)*, i64 (%struct.InStream*)*, void (%struct.InStream*)* } + +define i64 @t(%struct.InStream* %is) nounwind optsize ssp { +entry: + br i1 undef, label %is_read_byte.exit, label %bb.i + +bb.i: ; preds = %entry + br label %is_read_byte.exit + +is_read_byte.exit: ; preds = %bb.i, %entry + br i1 undef, label %is_read_byte.exit22, label %bb.i21 + +bb.i21: ; preds = %is_read_byte.exit + unreachable + +is_read_byte.exit22: ; preds = %is_read_byte.exit + br i1 undef, label %is_read_byte.exit19, label %bb.i18 + +bb.i18: ; preds = %is_read_byte.exit22 + br label %is_read_byte.exit19 + +is_read_byte.exit19: ; preds = %bb.i18, %is_read_byte.exit22 + br i1 undef, label %is_read_byte.exit16, label %bb.i15 + +bb.i15: ; preds = %is_read_byte.exit19 + unreachable + +is_read_byte.exit16: ; preds = %is_read_byte.exit19 + %0 = shl i64 undef, 32 ; <i64> [#uses=1] + br i1 undef, label %is_read_byte.exit13, label %bb.i12 + +bb.i12: ; preds = %is_read_byte.exit16 + unreachable + +is_read_byte.exit13: ; preds = %is_read_byte.exit16 + %1 = shl i64 undef, 24 ; <i64> [#uses=1] + br i1 undef, label %is_read_byte.exit10, label %bb.i9 + +bb.i9: ; preds = %is_read_byte.exit13 + unreachable + +is_read_byte.exit10: ; preds = %is_read_byte.exit13 + %2 = shl i64 undef, 16 ; <i64> [#uses=1] + br i1 undef, label %is_read_byte.exit7, label %bb.i6 + +bb.i6: ; preds = %is_read_byte.exit10 + br label %is_read_byte.exit7 + +is_read_byte.exit7: ; preds = %bb.i6, %is_read_byte.exit10 + %3 = shl i64 undef, 8 ; <i64> [#uses=1] + br i1 undef, label %is_read_byte.exit4, label %bb.i3 + +bb.i3: ; preds = %is_read_byte.exit7 + unreachable + +is_read_byte.exit4: ; preds = %is_read_byte.exit7 + %4 = or i64 0, %0 ; <i64> [#uses=1] + %5 = or i64 %4, %1 ; <i64> [#uses=1] + %6 = or i64 %5, %2 ; <i64> [#uses=1] + %7 = or i64 %6, %3 ; <i64> [#uses=1] + %8 = or i64 %7, 0 ; <i64> [#uses=1] + ret i64 %8 +} diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll index 558fd1b3199b..f99089b3bb02 100644 --- a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll +++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll @@ -9,66 +9,66 @@ ; RUN: llc < %s -march=ppc32 | \ ; RUN: grep nand | count 1 -define i32 @EQV1(i32 %X, i32 %Y) { +define i32 @EQV1(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, %Y ; <i32> [#uses=1] %B = xor i32 %A, -1 ; <i32> [#uses=1] ret i32 %B } -define i32 @EQV2(i32 %X, i32 %Y) { +define i32 @EQV2(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, -1 ; <i32> [#uses=1] %B = xor i32 %A, %Y ; <i32> [#uses=1] ret i32 %B } -define i32 @EQV3(i32 %X, i32 %Y) { +define i32 @EQV3(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, -1 ; <i32> [#uses=1] %B = xor i32 %Y, %A ; <i32> [#uses=1] ret i32 %B } -define i32 @ANDC1(i32 %X, i32 %Y) { +define i32 @ANDC1(i32 %X, i32 %Y) nounwind { %A = xor i32 %Y, -1 ; <i32> [#uses=1] %B = and i32 %X, %A ; <i32> [#uses=1] ret i32 %B } -define i32 @ANDC2(i32 %X, i32 %Y) { +define i32 @ANDC2(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, -1 ; <i32> [#uses=1] %B = and i32 %A, %Y ; <i32> [#uses=1] ret i32 %B } -define i32 @ORC1(i32 %X, i32 %Y) { +define i32 @ORC1(i32 %X, i32 %Y) nounwind { %A = xor i32 %Y, -1 ; <i32> [#uses=1] %B = or i32 %X, %A ; <i32> [#uses=1] ret i32 %B } -define i32 @ORC2(i32 %X, i32 %Y) { +define i32 @ORC2(i32 %X, i32 %Y) nounwind { %A = xor i32 %X, -1 ; <i32> [#uses=1] %B = or i32 %A, %Y ; <i32> [#uses=1] ret i32 %B } -define i32 @NOR1(i32 %X) { +define i32 @NOR1(i32 %X) nounwind { %Y = xor i32 %X, -1 ; <i32> [#uses=1] ret i32 %Y } -define i32 @NOR2(i32 %X, i32 %Y) { +define i32 @NOR2(i32 %X, i32 %Y) nounwind { %Z = or i32 %X, %Y ; <i32> [#uses=1] %R = xor i32 %Z, -1 ; <i32> [#uses=1] ret i32 %R } -define i32 @NAND1(i32 %X, i32 %Y) { +define i32 @NAND1(i32 %X, i32 %Y) nounwind { %Z = and i32 %X, %Y ; <i32> [#uses=1] %W = xor i32 %Z, -1 ; <i32> [#uses=1] ret i32 %W } -define void @VNOR(<4 x float>* %P, <4 x float>* %Q) { +define void @VNOR(<4 x float>* %P, <4 x float>* %Q) nounwind { %tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1] %tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1] %tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1] @@ -80,7 +80,7 @@ define void @VNOR(<4 x float>* %P, <4 x float>* %Q) { ret void } -define void @VANDC(<4 x float>* %P, <4 x float>* %Q) { +define void @VANDC(<4 x float>* %P, <4 x float>* %Q) nounwind { %tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1] %tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1] %tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll index 8a1288afa40c..6f103462664f 100644 --- a/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll +++ b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s +; RN: llc < %s +; RUN: false +; XFAIL: * ; PR4534 ; ModuleID = 'tango.net.ftp.FtpClient.bc' diff --git a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll index 319d29b790e8..9c1fdb32e836 100644 --- a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll +++ b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim type { %struct.GAP } ; type %0 type { i16, i8, i8 } ; type %1 diff --git a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll index a62b61290a5a..317db64ae45c 100644 --- a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll +++ b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim -O3 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -O3 type { i16, i8, i8 } ; type %0 type { [2 x i32], [2 x i32] } ; type %1 diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll index 76474746ee48..2bbc231f9622 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | not grep fcpys +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | not grep fcpys ; rdar://7117307 %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll index acf562c74a2a..82944847663a 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 ; rdar://7117307 %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll index 3ada02676bfc..b18c972aeddc 100644 --- a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll +++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 ; rdar://7117307 %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } diff --git a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll index 090ed2d81f60..96bcbad77146 100644 --- a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll +++ b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -arm-use-neon-fp +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } %struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 } diff --git a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll index 5e7c0a7ee2b7..a2288986362e 100644 --- a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll +++ b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86-64 > %t -; RUN: grep leaq %t ; RUN: not grep {,%rsp)} %t ; PR1103 diff --git a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll index 113d0eb8647f..c39b82a1fe36 100644 --- a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll +++ b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll @@ -1,12 +1,16 @@ -; RUN: llc < %s -o - -march=x86 -mattr=+mmx | grep paddq | count 2 -; RUN: llc < %s -o - -march=x86 -mattr=+mmx | grep movq | count 2 +; RUN: llc < %s -o - -march=x86 -mattr=+mmx | FileCheck %s -define <1 x i64> @unsigned_add3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) { +define <1 x i64> @unsigned_add3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) nounwind { entry: %tmp2942 = icmp eq i32 %count, 0 ; <i1> [#uses=1] br i1 %tmp2942, label %bb31, label %bb26 bb26: ; preds = %bb26, %entry + +; CHECK: movq ({{.*}},8), %mm +; CHECK: paddq ({{.*}},8), %mm +; CHECK: paddq %mm{{[0-7]}}, %mm + %i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ] ; <i32> [#uses=3] %sum.035.0 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ] ; <<1 x i64>> [#uses=1] %tmp13 = getelementptr <1 x i64>* %b, i32 %i.037.0 ; <<1 x i64>*> [#uses=1] diff --git a/test/CodeGen/X86/2009-02-05-CoalescerBug.ll b/test/CodeGen/X86/2009-02-05-CoalescerBug.ll index 0ffa8fdc30dd..a46a20b1da65 100644 --- a/test/CodeGen/X86/2009-02-05-CoalescerBug.ll +++ b/test/CodeGen/X86/2009-02-05-CoalescerBug.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movss | count 2 -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movaps | count 4 +; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 -o %t +; RUN: grep movss %t | count 2 +; RUN: grep movaps %t | count 2 +; RUN: grep movdqa %t | count 2 define i1 @t([2 x float]* %y, [2 x float]* %w, i32, [2 x float]* %x.pn59, i32 %smax190, i32 %j.1180, <4 x float> %wu.2179, <4 x float> %wr.2178, <4 x float>* %tmp89.out, <4 x float>* %tmp107.out, i32* %indvar.next218.out) nounwind { newFuncRoot: diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll index a4d642b40354..d9655fd19b3c 100644 --- a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll +++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& not grep {machine-licm} +; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {2 machine-licm} +; RUN: llc < %s -march=x86-64 -mattr=+sse3 | FileCheck %s ; rdar://6627786 +; rdar://7792037 target triple = "x86_64-apple-darwin10.0" %struct.Key = type { i64 } @@ -11,6 +13,13 @@ entry: br label %bb4 bb4: ; preds = %bb.i, %bb26, %bb4, %entry +; CHECK: %bb4 +; CHECK: xorb +; CHECK: callq +; CHECK: movq +; CHECK: xorl +; CHECK: xorb + %0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind ; <i32> [#uses=0] %ins = or i64 %p, 2097152 ; <i64> [#uses=1] %1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll index 3ce9edb5db44..26bf09c723a0 100644 --- a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll +++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s ; rdar://7396984 @str = private constant [28 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 1 diff --git a/test/CodeGen/X86/byval7.ll b/test/CodeGen/X86/byval7.ll index 0da93bad04e1..686ed9c74dde 100644 --- a/test/CodeGen/X86/byval7.ll +++ b/test/CodeGen/X86/byval7.ll @@ -1,10 +1,17 @@ -; RUN: llc < %s -march=x86 -mcpu=yonah | egrep {add|lea} | grep 16 +; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s %struct.S = type { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, + <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } define i32 @main() nounwind { entry: +; CHECK: main: +; CHECK: movl $1, (%esp) +; CHECK: leal 16(%esp), %edi +; CHECK: movl $36, %ecx +; CHECK: leal 160(%esp), %esi +; CHECK: rep;movsl %s = alloca %struct.S ; <%struct.S*> [#uses=2] %tmp15 = getelementptr %struct.S* %s, i32 0, i32 0 ; <<2 x i64>*> [#uses=1] store <2 x i64> < i64 8589934595, i64 1 >, <2 x i64>* %tmp15, align 16 diff --git a/test/CodeGen/X86/coalesce-esp.ll b/test/CodeGen/X86/coalesce-esp.ll index 0fe4e56c97ca..e0f2796f9dce 100644 --- a/test/CodeGen/X86/coalesce-esp.ll +++ b/test/CodeGen/X86/coalesce-esp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep {movl %esp, %eax} +; RUN: llc < %s | grep {movl %esp, %ecx} ; PR4572 ; Don't coalesce with %esp if it would end up putting %esp in diff --git a/test/CodeGen/X86/dagcombine-buildvector.ll b/test/CodeGen/X86/dagcombine-buildvector.ll index c0ee2ac3386b..5cc6eaa405ad 100644 --- a/test/CodeGen/X86/dagcombine-buildvector.ll +++ b/test/CodeGen/X86/dagcombine-buildvector.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx -o %t -; RUN: grep unpcklpd %t | count 1 -; RUN: grep movapd %t | count 1 -; RUN: grep movaps %t | count 1 +; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx | FileCheck %s ; Shows a dag combine bug that will generate an illegal build vector ; with v2i64 build_vector i32, i32. +; CHECK: test: +; CHECK: unpcklpd +; CHECK: movapd define void @test(<2 x double>* %dst, <4 x double> %src) nounwind { entry: %tmp7.i = shufflevector <4 x double> %src, <4 x double> undef, <2 x i32> < i32 0, i32 2 > @@ -13,6 +13,8 @@ entry: ret void } +; CHECK: test2: +; CHECK: movdqa define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind { entry: %tmp1 = load <4 x i16>* %src diff --git a/test/CodeGen/X86/gather-addresses.ll b/test/CodeGen/X86/gather-addresses.ll index 3e730de0a8e5..134ee28df6c8 100644 --- a/test/CodeGen/X86/gather-addresses.ll +++ b/test/CodeGen/X86/gather-addresses.ll @@ -5,7 +5,7 @@ ; bounce the vector off of cache rather than shuffling each individual ; element out of the index vector. -; CHECK: pand (%rdx), %xmm0 +; CHECK: andps (%rdx), %xmm0 ; CHECK: movaps %xmm0, -24(%rsp) ; CHECK: movslq -24(%rsp), %rax ; CHECK: movsd (%rdi,%rax,8), %xmm0 diff --git a/test/CodeGen/X86/licm-symbol.ll b/test/CodeGen/X86/licm-symbol.ll index d61bbfccbc96..08306c2950e2 100644 --- a/test/CodeGen/X86/licm-symbol.ll +++ b/test/CodeGen/X86/licm-symbol.ll @@ -3,7 +3,7 @@ ; MachineLICM should be able to hoist the sF reference out of the loop. ; CHECK: pushl %esi -; CHECK: subl $8, %esp +; CHECK: subl $4, %esp ; CHECK: movl $176, %esi ; CHECK: addl L___sF$non_lazy_ptr, %esi ; CHECK: .align 4, 0x90 diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll index 2dc939e666ff..4fe32d974d05 100644 --- a/test/CodeGen/X86/memcpy-2.ll +++ b/test/CodeGen/X86/memcpy-2.ll @@ -1,15 +1,122 @@ -; RUN: llc < %s -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 7 -; RUN: llc < %s -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 5 +; RUN: llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE2 +; RUN: llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1 +; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64 %struct.ParmT = type { [25 x i8], i8, i8* } @.str12 = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" ; <[25 x i8]*> [#uses=1] -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind - -define void @t(i32 %argc, i8** %argv) nounwind { +define void @t1(i32 %argc, i8** %argv) nounwind { entry: +; SSE2: t1: +; SSE2: movaps _.str12, %xmm0 +; SSE2: movaps %xmm0 +; SSE2: movb $0 +; SSE2: movl $0 +; SSE2: movl $0 + +; SSE1: t1: +; SSE1: movaps _.str12, %xmm0 +; SSE1: movaps %xmm0 +; SSE1: movb $0 +; SSE1: movl $0 +; SSE1: movl $0 + +; NOSSE: t1: +; NOSSE: movb $0 +; NOSSE: movl $0 +; NOSSE: movl $0 +; NOSSE: movl $0 +; NOSSE: movl $0 +; NOSSE: movl $101 +; NOSSE: movl $1734438249 + +; X86-64: t1: +; X86-64: movaps _.str12(%rip), %xmm0 +; X86-64: movaps %xmm0 +; X86-64: movb $0 +; X86-64: movq $0 %parms.i = alloca [13 x %struct.ParmT] ; <[13 x %struct.ParmT]*> [#uses=1] %parms1.i = getelementptr [13 x %struct.ParmT]* %parms.i, i32 0, i32 0, i32 0, i32 0 ; <i8*> [#uses=1] call void @llvm.memcpy.i32( i8* %parms1.i, i8* getelementptr ([25 x i8]* @.str12, i32 0, i32 0), i32 25, i32 1 ) nounwind unreachable } + +;rdar://7774704 +%struct.s0 = type { [2 x double] } + +define void @t2(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp { +entry: +; SSE2: t2: +; SSE2: movaps (%eax), %xmm0 +; SSE2: movaps %xmm0, (%eax) + +; SSE1: t2: +; SSE1: movaps (%eax), %xmm0 +; SSE1: movaps %xmm0, (%eax) + +; NOSSE: t2: +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl + +; X86-64: t2: +; X86-64: movaps (%rsi), %xmm0 +; X86-64: movaps %xmm0, (%rdi) + %tmp2 = bitcast %struct.s0* %a to i8* ; <i8*> [#uses=1] + %tmp3 = bitcast %struct.s0* %b to i8* ; <i8*> [#uses=1] + tail call void @llvm.memcpy.i32(i8* %tmp2, i8* %tmp3, i32 16, i32 16) + ret void +} + +define void @t3(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp { +entry: +; SSE2: t3: +; SSE2: movsd (%eax), %xmm0 +; SSE2: movsd 8(%eax), %xmm1 +; SSE2: movsd %xmm1, 8(%eax) +; SSE2: movsd %xmm0, (%eax) + +; SSE1: t3: +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl +; SSE1: movl + +; NOSSE: t3: +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl +; NOSSE: movl + +; X86-64: t3: +; X86-64: movq (%rsi), %rax +; X86-64: movq 8(%rsi), %rcx +; X86-64: movq %rcx, 8(%rdi) +; X86-64: movq %rax, (%rdi) + %tmp2 = bitcast %struct.s0* %a to i8* ; <i8*> [#uses=1] + %tmp3 = bitcast %struct.s0* %b to i8* ; <i8*> [#uses=1] + tail call void @llvm.memcpy.i32(i8* %tmp2, i8* %tmp3, i32 16, i32 8) + ret void +} + +declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind diff --git a/test/CodeGen/X86/memset-2.ll b/test/CodeGen/X86/memset-2.ll index 7deb52f8078e..702632cde965 100644 --- a/test/CodeGen/X86/memset-2.ll +++ b/test/CodeGen/X86/memset-2.ll @@ -1,47 +1,21 @@ -; RUN: llc < %s | not grep rep -; RUN: llc < %s | grep memset +; RUN: llc < %s | FileCheck %s target triple = "i386" declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind -define fastcc i32 @cli_scanzip(i32 %desc) nounwind { +define fastcc void @t1() nounwind { entry: - br label %bb8.i.i.i.i - -bb8.i.i.i.i: ; preds = %bb8.i.i.i.i, %entry - icmp eq i32 0, 0 ; <i1>:0 [#uses=1] - br i1 %0, label %bb61.i.i.i, label %bb8.i.i.i.i - -bb32.i.i.i: ; preds = %bb61.i.i.i - ptrtoint i8* %tail.0.i.i.i to i32 ; <i32>:1 [#uses=1] - sub i32 0, %1 ; <i32>:2 [#uses=1] - icmp sgt i32 %2, 19 ; <i1>:3 [#uses=1] - br i1 %3, label %bb34.i.i.i, label %bb61.i.i.i - -bb34.i.i.i: ; preds = %bb32.i.i.i - load i32* null, align 4 ; <i32>:4 [#uses=1] - icmp eq i32 %4, 101010256 ; <i1>:5 [#uses=1] - br i1 %5, label %bb8.i11.i.i.i, label %bb61.i.i.i - -bb8.i11.i.i.i: ; preds = %bb8.i11.i.i.i, %bb34.i.i.i - icmp eq i32 0, 0 ; <i1>:6 [#uses=1] - br i1 %6, label %cli_dbgmsg.exit49.i, label %bb8.i11.i.i.i - -cli_dbgmsg.exit49.i: ; preds = %bb8.i11.i.i.i - icmp eq [32768 x i8]* null, null ; <i1>:7 [#uses=1] - br i1 %7, label %bb1.i28.i, label %bb8.i.i - -bb61.i.i.i: ; preds = %bb61.i.i.i, %bb34.i.i.i, %bb32.i.i.i, %bb8.i.i.i.i - %tail.0.i.i.i = getelementptr [1024 x i8]* null, i32 0, i32 0 ; <i8*> [#uses=2] - load i8* %tail.0.i.i.i, align 1 ; <i8>:8 [#uses=1] - icmp eq i8 %8, 80 ; <i1>:9 [#uses=1] - br i1 %9, label %bb32.i.i.i, label %bb61.i.i.i - -bb1.i28.i: ; preds = %cli_dbgmsg.exit49.i - call void @llvm.memset.i32( i8* null, i8 0, i32 88, i32 1 ) nounwind - unreachable +; CHECK: t1: +; CHECK: call memset + call void @llvm.memset.i32( i8* null, i8 0, i32 188, i32 1 ) nounwind + unreachable +} -bb8.i.i: ; preds = %bb8.i.i, %cli_dbgmsg.exit49.i - br label %bb8.i.i +define fastcc void @t2(i8 signext %c) nounwind { +entry: +; CHECK: t2: +; CHECK: call memset + call void @llvm.memset.i32( i8* undef, i8 %c, i32 76, i32 1 ) nounwind + unreachable } diff --git a/test/CodeGen/X86/memset64-on-x86-32.ll b/test/CodeGen/X86/memset64-on-x86-32.ll index da8fc51da8e1..c0cd271d985e 100644 --- a/test/CodeGen/X86/memset64-on-x86-32.ll +++ b/test/CodeGen/X86/memset64-on-x86-32.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin | grep stosl -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movq | count 10 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=nehalem | grep movaps | count 5 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=core2 | grep movl | count 20 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | grep movq | count 10 define void @bork() nounwind { entry: diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index e997233a5194..35b172509c95 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -194,10 +194,10 @@ bb12: ; LINUX: .LJTI8_0: ; LINUX: .long .LBB8_2@GOTOFF -; LINUX: .long .LBB8_2@GOTOFF -; LINUX: .long .LBB8_7@GOTOFF -; LINUX: .long .LBB8_3@GOTOFF -; LINUX: .long .LBB8_7@GOTOFF +; LINUX: .long .LBB8_8@GOTOFF +; LINUX: .long .LBB8_14@GOTOFF +; LINUX: .long .LBB8_9@GOTOFF +; LINUX: .long .LBB8_10@GOTOFF } declare void @foo1(...) diff --git a/test/CodeGen/X86/pmul.ll b/test/CodeGen/X86/pmul.ll index e2746a8c0638..bf5229aa1ee8 100644 --- a/test/CodeGen/X86/pmul.ll +++ b/test/CodeGen/X86/pmul.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=sse41 -stack-alignment=16 > %t ; RUN: grep pmul %t | count 12 -; RUN: grep mov %t | count 12 +; RUN: grep mov %t | count 11 define <4 x i32> @a(<4 x i32> %i) nounwind { %A = mul <4 x i32> %i, < i32 117, i32 117, i32 117, i32 117 > diff --git a/test/CodeGen/X86/pmulld.ll b/test/CodeGen/X86/pmulld.ll new file mode 100644 index 000000000000..3ef594112b45 --- /dev/null +++ b/test/CodeGen/X86/pmulld.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=x86-64 -mattr=+sse41 -asm-verbose=0 | FileCheck %s + +define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: test1: +; CHECK-NEXT: pmulld + %C = mul <4 x i32> %A, %B + ret <4 x i32> %C +} + +define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind { +; CHECK: test1a: +; CHECK-NEXT: pmulld + %B = load <4 x i32>* %Bp + %C = mul <4 x i32> %A, %B + ret <4 x i32> %C +} diff --git a/test/CodeGen/X86/postalloc-coalescing.ll b/test/CodeGen/X86/postalloc-coalescing.ll index a171436543c6..fe6f521f4d32 100644 --- a/test/CodeGen/X86/postalloc-coalescing.ll +++ b/test/CodeGen/X86/postalloc-coalescing.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 | grep mov | count 3 -define fastcc i32 @_Z18yy_get_next_bufferv() { +define fastcc i32 @_Z18yy_get_next_bufferv() nounwind { entry: br label %bb131 diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll index 0760e4c7fd5b..27047dfdfd8c 100644 --- a/test/CodeGen/X86/pr2659.ll +++ b/test/CodeGen/X86/pr2659.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5 +; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | FileCheck %s ; PR2659 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" @@ -13,6 +14,11 @@ forcond.preheader: ; preds = %entry %cmp44 = icmp eq i32 %k, 0 ; <i1> [#uses=1] br i1 %cmp44, label %afterfor, label %forbody +; CHECK: %forcond.preheader.forbody_crit_edge +; CHECK: movl $1 +; CHECK-NOT: xorl +; CHECK-NEXT: movl $1 + ifthen: ; preds = %entry ret i32 0 diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index ce35b4545184..8e52a7cbfe78 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -271,3 +271,45 @@ entry: } declare double @bar4() + +; rdar://6283267 +define void @t17() nounwind ssp { +entry: +; 32: t17: +; 32: jmp {{_?}}bar5 + +; 64: t17: +; 64: xorb %al, %al +; 64: jmp {{_?}}bar5 + tail call void (...)* @bar5() nounwind + ret void +} + +declare void @bar5(...) + +; rdar://7774847 +define void @t18() nounwind ssp { +entry: +; 32: t18: +; 32: call {{_?}}bar6 +; 32: fstp %st(0) + +; 64: t18: +; 64: xorb %al, %al +; 64: jmp {{_?}}bar6 + %0 = tail call double (...)* @bar6() nounwind + ret void +} + +declare double @bar6(...) + +define void @t19() alignstack(32) nounwind { +entry: +; CHECK: t19: +; CHECK: andl $-32 +; CHECK: call {{_?}}foo + tail call void @foo() nounwind + ret void +} + +declare void @foo() diff --git a/test/CodeGen/X86/small-byval-memcpy.ll b/test/CodeGen/X86/small-byval-memcpy.ll index 9ec9182e5e3c..1b596b589899 100644 --- a/test/CodeGen/X86/small-byval-memcpy.ll +++ b/test/CodeGen/X86/small-byval-memcpy.ll @@ -1,7 +1,5 @@ -; RUN: llc < %s | not grep movs - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-apple-darwin8" +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=core2 | grep movsd | count 8 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=nehalem | grep movups | count 2 define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 }* byval align 4 %z) nounwind { entry: diff --git a/test/CodeGen/X86/sse-align-12.ll b/test/CodeGen/X86/sse-align-12.ll index 4f025b916fd9..118e393b7baa 100644 --- a/test/CodeGen/X86/sse-align-12.ll +++ b/test/CodeGen/X86/sse-align-12.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=x86-64 > %t -; RUN: grep unpck %t | count 2 -; RUN: grep shuf %t | count 2 -; RUN: grep ps %t | count 4 -; RUN: grep pd %t | count 4 -; RUN: grep movup %t | count 4 +; RUN: llc < %s -march=x86-64 | FileCheck %s +; CHECK: a: +; CHECK: movdqu +; CHECK: pshufd define <4 x float> @a(<4 x float>* %y) nounwind { %x = load <4 x float>* %y, align 4 %a = extractelement <4 x float> %x, i32 0 @@ -17,6 +15,10 @@ define <4 x float> @a(<4 x float>* %y) nounwind { %s = insertelement <4 x float> %r, float %a, i32 3 ret <4 x float> %s } + +; CHECK: b: +; CHECK: movups +; CHECK: unpckhps define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind { %x = load <4 x float>* %y, align 4 %a = extractelement <4 x float> %x, i32 2 @@ -29,6 +31,10 @@ define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind { %s = insertelement <4 x float> %r, float %b, i32 3 ret <4 x float> %s } + +; CHECK: c: +; CHECK: movupd +; CHECK: shufpd define <2 x double> @c(<2 x double>* %y) nounwind { %x = load <2 x double>* %y, align 8 %a = extractelement <2 x double> %x, i32 0 @@ -37,6 +43,10 @@ define <2 x double> @c(<2 x double>* %y) nounwind { %r = insertelement <2 x double> %p, double %a, i32 1 ret <2 x double> %r } + +; CHECK: d: +; CHECK: movupd +; CHECK: unpckhpd define <2 x double> @d(<2 x double>* %y, <2 x double> %z) nounwind { %x = load <2 x double>* %y, align 8 %a = extractelement <2 x double> %x, i32 1 diff --git a/test/CodeGen/X86/sse-align-6.ll b/test/CodeGen/X86/sse-align-6.ll index 0bbf4228a40b..fcea1b102a20 100644 --- a/test/CodeGen/X86/sse-align-6.ll +++ b/test/CodeGen/X86/sse-align-6.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | grep movups | count 1 +; RUN: llc < %s -march=x86-64 | grep movdqu | count 1 define <2 x i64> @bar(<2 x i64>* %p, <2 x i64> %x) nounwind { %t = load <2 x i64>* %p, align 8 diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index e9c2c01a9e44..b969ecb41420 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -20,7 +20,7 @@ entry: ; X64: pshuflw $0, %xmm0, %xmm0 ; X64: xorl %eax, %eax ; X64: pinsrw $0, %eax, %xmm0 -; X64: movaps %xmm0, (%rdi) +; X64: movdqa %xmm0, (%rdi) ; X64: ret } @@ -32,7 +32,7 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; X64: t1: ; X64: movl (%rsi), %eax -; X64: movaps (%rdi), %xmm0 +; X64: movdqa (%rdi), %xmm0 ; X64: pinsrw $0, %eax, %xmm0 ; X64: ret } @@ -66,7 +66,7 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind { ; X64: pshufhw $100, %xmm0, %xmm2 ; X64: pinsrw $1, %eax, %xmm2 ; X64: pextrw $1, %xmm0, %eax -; X64: movaps %xmm2, %xmm0 +; X64: movdqa %xmm2, %xmm0 ; X64: pinsrw $4, %eax, %xmm0 ; X64: ret } @@ -122,7 +122,7 @@ define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind { ; X64: t8: ; X64: pshuflw $-58, (%rsi), %xmm0 ; X64: pshufhw $-58, %xmm0, %xmm0 -; X64: movaps %xmm0, (%rdi) +; X64: movdqa %xmm0, (%rdi) ; X64: ret } diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll index b61803d10ce4..47b7896bb8f1 100644 --- a/test/CodeGen/X86/unaligned-load.ll +++ b/test/CodeGen/X86/unaligned-load.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10.0 -mcpu=core2 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck -check-prefix=I386 %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -mcpu=core2 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck -check-prefix=CORE2 %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -mcpu=corei7 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck -check-prefix=COREI7 %s @.str1 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 8 @.str3 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, 2'ND STRING\00", align 8 @@ -11,7 +13,15 @@ entry: bb: %String2Loc9 = getelementptr inbounds [31 x i8]* %String2Loc, i64 0, i64 0 call void @llvm.memcpy.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1) -; CHECK: movups _.str3 +; I386: movsd _.str3+16 +; I386: movsd _.str3+8 +; I386: movsd _.str3 + +; CORE2: movabsq +; CORE2: movabsq +; CORE2: movabsq + +; COREI7: movups _.str3 br label %bb return: @@ -20,8 +30,8 @@ return: declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind -; CHECK: .align 3 -; CHECK-NEXT: _.str1: -; CHECK-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" -; CHECK: .align 3 -; CHECK-NEXT: _.str3: +; CORE2: .align 3 +; CORE2-NEXT: _.str1: +; CORE2-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" +; CORE2: .align 3 +; CORE2-NEXT: _.str3: diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll index c8c7257cbb9c..39c9b770d5f4 100644 --- a/test/CodeGen/X86/vec_compare.ll +++ b/test/CodeGen/X86/vec_compare.ll @@ -15,7 +15,7 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { ; CHECK: test2: ; CHECK: pcmp ; CHECK: pcmp -; CHECK: xorps +; CHECK: pxor ; CHECK: ret %C = icmp sge <4 x i32> %A, %B %D = sext <4 x i1> %C to <4 x i32> @@ -25,7 +25,7 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { ; CHECK: test3: ; CHECK: pcmpgtd -; CHECK: movaps +; CHECK: movdqa ; CHECK: ret %C = icmp slt <4 x i32> %A, %B %D = sext <4 x i1> %C to <4 x i32> @@ -34,7 +34,7 @@ define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind { ; CHECK: test4: -; CHECK: movaps +; CHECK: movdqa ; CHECK: pcmpgtd ; CHECK: ret %C = icmp ugt <4 x i32> %A, %B diff --git a/test/CodeGen/X86/vec_insert_4.ll b/test/CodeGen/X86/vec_insert-4.ll index 2c31e56b4af6..2c31e56b4af6 100644 --- a/test/CodeGen/X86/vec_insert_4.ll +++ b/test/CodeGen/X86/vec_insert-4.ll diff --git a/test/CodeGen/X86/vec_insert-9.ll b/test/CodeGen/X86/vec_insert-9.ll new file mode 100644 index 000000000000..2e829df1f8df --- /dev/null +++ b/test/CodeGen/X86/vec_insert-9.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=x86 -mattr=+sse41 > %t +; RUN: grep pinsrd %t | count 2 + +define <4 x i32> @var_insert2(<4 x i32> %x, i32 %val, i32 %idx) nounwind { +entry: + %tmp3 = insertelement <4 x i32> undef, i32 %val, i32 0 ; <<4 x i32>> [#uses=1] + %tmp4 = insertelement <4 x i32> %tmp3, i32 %idx, i32 3 ; <<4 x i32>> [#uses=1] + ret <4 x i32> %tmp4 +} diff --git a/test/CodeGen/X86/vec_return.ll b/test/CodeGen/X86/vec_return.ll index 66762b4a0604..676be9b7179c 100644 --- a/test/CodeGen/X86/vec_return.ll +++ b/test/CodeGen/X86/vec_return.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 > %t -; RUN: grep xorps %t | count 1 +; RUN: grep pxor %t | count 1 ; RUN: grep movaps %t | count 1 ; RUN: not grep shuf %t diff --git a/test/CodeGen/X86/vec_set.ll b/test/CodeGen/X86/vec_set.ll index c316df887c16..7f5f8dd213a5 100644 --- a/test/CodeGen/X86/vec_set.ll +++ b/test/CodeGen/X86/vec_set.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep punpckl | count 7 +; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep punpckl | count 7 define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind { %tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1] diff --git a/test/CodeGen/X86/vec_shuffle-7.ll b/test/CodeGen/X86/vec_shuffle-7.ll index 4cdca09c72f5..64bd6a3c83b8 100644 --- a/test/CodeGen/X86/vec_shuffle-7.ll +++ b/test/CodeGen/X86/vec_shuffle-7.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t -; RUN: grep xorps %t | count 1 +; RUN: grep pxor %t | count 1 ; RUN: not grep shufps %t define void @test() { diff --git a/test/CodeGen/X86/vec_shuffle-9.ll b/test/CodeGen/X86/vec_shuffle-9.ll index fc16a26b6154..07195869b8cf 100644 --- a/test/CodeGen/X86/vec_shuffle-9.ll +++ b/test/CodeGen/X86/vec_shuffle-9.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define <4 x i32> @test(i8** %ptr) { -; CHECK: xorps +; CHECK: pxor ; CHECK: punpcklbw ; CHECK: punpcklwd diff --git a/test/CodeGen/X86/vec_shuffle.ll b/test/CodeGen/X86/vec_shuffle.ll index c05b79a54a15..2a48de22098f 100644 --- a/test/CodeGen/X86/vec_shuffle.ll +++ b/test/CodeGen/X86/vec_shuffle.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mcpu=core2 -o %t -; RUN: grep shufp %t | count 1 +; RUN: grep movq %t | count 1 +; RUN: grep pshufd %t | count 1 ; RUN: grep movupd %t | count 1 ; RUN: grep pshufhw %t | count 1 diff --git a/test/CodeGen/X86/vec_zero.ll b/test/CodeGen/X86/vec_zero.ll index ae5af586cdc3..4d1f05629b41 100644 --- a/test/CodeGen/X86/vec_zero.ll +++ b/test/CodeGen/X86/vec_zero.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xorps | count 2 +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; CHECK: xorps define void @foo(<4 x float>* %P) { %T = load <4 x float>* %P ; <<4 x float>> [#uses=1] %S = fadd <4 x float> zeroinitializer, %T ; <<4 x float>> [#uses=1] @@ -7,6 +8,7 @@ define void @foo(<4 x float>* %P) { ret void } +; CHECK: pxor define void @bar(<4 x i32>* %P) { %T = load <4 x i32>* %P ; <<4 x i32>> [#uses=1] %S = add <4 x i32> zeroinitializer, %T ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/X86/vec_zero_cse.ll b/test/CodeGen/X86/vec_zero_cse.ll index 296378c6e9f5..3b15d4cc407b 100644 --- a/test/CodeGen/X86/vec_zero_cse.ll +++ b/test/CodeGen/X86/vec_zero_cse.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1 -; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1 +; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 2 ; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 2 @M1 = external global <1 x i64> diff --git a/test/CodeGen/X86/widen_arith-5.ll b/test/CodeGen/X86/widen_arith-5.ll index f7f340873624..bae5c54eea64 100644 --- a/test/CodeGen/X86/widen_arith-5.ll +++ b/test/CodeGen/X86/widen_arith-5.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s -; CHECK: movaps +; CHECK: movdqa ; CHECK: pmulld ; CHECK: psubd diff --git a/test/CodeGen/X86/widen_cast-2.ll b/test/CodeGen/X86/widen_cast-2.ll index 1e626a2f8822..14e8f7562482 100644 --- a/test/CodeGen/X86/widen_cast-2.ll +++ b/test/CodeGen/X86/widen_cast-2.ll @@ -2,7 +2,7 @@ ; CHECK: pextrd ; CHECK: pextrd ; CHECK: movd -; CHECK: movaps +; CHECK: movdqa ; bitcast v14i16 to v7i32 diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll index 58b557a7915c..658c05143e84 100644 --- a/test/CodeGen/X86/widen_load-2.ll +++ b/test/CodeGen/X86/widen_load-2.ll @@ -5,7 +5,7 @@ %i32vec3 = type <3 x i32> define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { -; CHECK: movaps +; CHECK: movdqa ; CHECK: paddd ; CHECK: pextrd ; CHECK: movq @@ -33,13 +33,13 @@ define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { %i32vec7 = type <7 x i32> define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddd ; CHECK: paddd ; CHECK: pextrd ; CHECK: movq -; CHECK: movaps +; CHECK: movdqa %a = load %i32vec7* %ap, align 16 %b = load %i32vec7* %bp, align 16 %x = add %i32vec7 %a, %b @@ -49,15 +49,15 @@ define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { %i32vec12 = type <12 x i32> define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { -; CHECK: movaps -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddd ; CHECK: paddd ; CHECK: paddd -; CHECK: movaps -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa +; CHECK: movdqa %a = load %i32vec12* %ap, align 16 %b = load %i32vec12* %bp, align 16 %x = add %i32vec12 %a, %b @@ -68,7 +68,7 @@ define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { %i16vec3 = type <3 x i16> define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { -; CHECK: movaps +; CHECK: movdqa ; CHECK: paddw ; CHECK: movd ; CHECK: pextrw @@ -81,7 +81,7 @@ define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp %i16vec4 = type <4 x i16> define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind { -; CHECK: movaps +; CHECK: movdqa ; CHECK: paddw ; CHECK: movq %a = load %i16vec4* %ap, align 16 @@ -93,12 +93,12 @@ define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp %i16vec12 = type <12 x i16> define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind { -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddw ; CHECK: paddw ; CHECK: movq -; CHECK: movaps +; CHECK: movdqa %a = load %i16vec12* %ap, align 16 %b = load %i16vec12* %bp, align 16 %x = add %i16vec12 %a, %b @@ -108,15 +108,15 @@ define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %i16vec18 = type <18 x i16> define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind { -; CHECK: movaps -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddw ; CHECK: paddw ; CHECK: paddw ; CHECK: movd -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa %a = load %i16vec18* %ap, align 16 %b = load %i16vec18* %bp, align 16 %x = add %i16vec18 %a, %b @@ -127,7 +127,7 @@ define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %i8vec3 = type <3 x i8> define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { -; CHECK: movaps +; CHECK: movdqa ; CHECK: paddb ; CHECK: pextrb ; CHECK: movb @@ -140,8 +140,8 @@ define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) no %i8vec31 = type <31 x i8> define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind { -; CHECK: movaps -; CHECK: movaps +; CHECK: movdqa +; CHECK: movdqa ; CHECK: paddb ; CHECK: paddb ; CHECK: movq diff --git a/test/CodeGen/X86/xor-icmp.ll b/test/CodeGen/X86/xor-icmp.ll index 2d75c5d76201..34875ed89957 100644 --- a/test/CodeGen/X86/xor-icmp.ll +++ b/test/CodeGen/X86/xor-icmp.ll @@ -43,7 +43,7 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp { ; X32: cmpl ; X32: sete ; X32-NOT: xor -; X32: je +; X32: jne ; X64: t2: ; X64: testl @@ -51,7 +51,7 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp { ; X64: testl ; X64: sete ; X64-NOT: xor -; X64: je +; X64: jne entry: %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1] %1 = icmp eq i32 %y, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index 9bfff8a06a86..f270d9d56e21 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -7,7 +7,7 @@ define <4 x i32> @test1() nounwind { ret <4 x i32> %tmp ; X32: test1: -; X32: xorps %xmm0, %xmm0 +; X32: pxor %xmm0, %xmm0 ; X32: ret } |