diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-02 18:30:13 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-02 18:30:13 +0000 |
| commit | a303c417bbdb53703c2c17398b08486bde78f1f6 (patch) | |
| tree | 98366d6b93d863cefdc53f16c66c0c5ae7fb2261 /test/CodeGen | |
| parent | 12f3ca4cdb95b193af905a00e722a4dcb40b3de3 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen')
84 files changed, 5680 insertions, 2340 deletions
diff --git a/test/CodeGen/AArch64/arm64-anyregcc.ll b/test/CodeGen/AArch64/arm64-anyregcc.ll index 1af310383243..10989a07990c 100644 --- a/test/CodeGen/AArch64/arm64-anyregcc.ll +++ b/test/CodeGen/AArch64/arm64-anyregcc.ll @@ -4,7 +4,7 @@ ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -48,18 +48,24 @@ ; CHECK-NEXT: .short 3 ; Loc 0: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Constant 3 ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 3 define i64 @test() nounwind ssp uwtable { entry: @@ -69,18 +75,22 @@ entry: ; property access 1 - %obj is an anyreg call argument and should therefore be in a register ; CHECK-LABEL: .long L{{.*}}-_property_access1 -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @property_access1(i8* %obj) nounwind ssp uwtable { entry: @@ -91,18 +101,22 @@ entry: ; property access 2 - %obj is an anyreg call argument and should therefore be in a register ; CHECK-LABEL: .long L{{.*}}-_property_access2 -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @property_access2() nounwind ssp uwtable { entry: @@ -114,18 +128,22 @@ entry: ; property access 3 - %obj is a frame index ; CHECK-LABEL: .long L{{.*}}-_property_access3 -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Direct FP - 8 ; CHECK-NEXT: .byte 2 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 29 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -8 define i64 @property_access3() nounwind ssp uwtable { entry: @@ -137,78 +155,106 @@ entry: ; anyreg_test1 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test1 -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 14 locations ; CHECK-NEXT: .short 14 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 4: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 5: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 6: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 7: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 8: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 9: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 10: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 11: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 12: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 13: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: @@ -219,78 +265,106 @@ entry: ; anyreg_test2 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test2 -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 14 locations ; CHECK-NEXT: .short 14 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 4: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 5: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 6: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 7: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 8: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 9: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 10: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 11: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 12: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 13: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: @@ -308,18 +382,24 @@ entry: ; CHECK-NEXT: .short 3 ; Loc 0: Register (some register that will be spilled to the stack) ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: @@ -337,28 +417,38 @@ entry: ; CHECK-NEXT: .short 5 ; Loc 0: Return a register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Arg0 in a Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Arg1 in a Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Arg2 spilled to FP -96 ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 29 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -96 ; Loc 4: Arg3 spilled to FP - 88 ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 29 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -88 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: diff --git a/test/CodeGen/AArch64/arm64-stackmap.ll b/test/CodeGen/AArch64/arm64-stackmap.ll index 0b2e9776263d..e12a35a93e22 100644 --- a/test/CodeGen/AArch64/arm64-stackmap.ll +++ b/test/CodeGen/AArch64/arm64-stackmap.ll @@ -10,7 +10,7 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -67,22 +67,30 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" ; CHECK-NEXT: .short 4 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 65535 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 65536 ; SmallConstant ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; LargeConstant at index 0 ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 1 @@ -99,12 +107,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @osrinline(i64 %a, i64 %b) { entry: @@ -123,12 +135,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @osrcold(i64 %a, i64 %b) { entry: @@ -163,12 +179,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) { entry: @@ -185,12 +205,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: @@ -207,12 +231,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: @@ -233,8 +261,11 @@ entry: ; Check that at least one is a spilled entry from RBP. ; Location: Indirect FP + ... ; CHECK: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short ; CHECK-NEXT: .short 29 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) { entry: call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) @@ -252,8 +283,11 @@ entry: ; Check that at least one is a spilled entry from RBP. ; Location: Indirect FP + ... ; CHECK: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short ; CHECK-NEXT: .short 29 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) { entry: call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) @@ -269,7 +303,9 @@ entry: ; CHECK-NEXT: .short 1 ; Loc 0: SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 33 @@ -286,8 +322,10 @@ define void @liveConstant() { ; CHECK-NEXT: .short 1 ; Loc 0: Indirect FP (r29) - offset ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 29 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -{{[0-9]+}} define void @clobberLR(i32 %a) { tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x31}"() nounwind diff --git a/test/CodeGen/AArch64/arm64-tls-dynamics.ll b/test/CodeGen/AArch64/arm64-tls-dynamics.ll index 88700a153437..17979f4036cb 100644 --- a/test/CodeGen/AArch64/arm64-tls-dynamics.ll +++ b/test/CodeGen/AArch64/arm64-tls-dynamics.ll @@ -30,13 +30,13 @@ define i32 @test_generaldynamic() { ; CHECK-NOLD: ldr w0, [x[[TP]], x0] ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } @@ -56,13 +56,13 @@ define i32* @test_generaldynamic_addr() { ; CHECK: add x0, [[TP]], x0 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } @@ -95,15 +95,15 @@ define i32 @test_localdynamic() { ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12 ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } @@ -131,15 +131,15 @@ define i32* @test_localdynamic_addr() { ret i32* @local_dynamic_var ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12 ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC -; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } diff --git a/test/CodeGen/AArch64/stackmap-liveness.ll b/test/CodeGen/AArch64/stackmap-liveness.ll index 4b04276ac226..b66dbfae6c8a 100644 --- a/test/CodeGen/AArch64/stackmap-liveness.ll +++ b/test/CodeGen/AArch64/stackmap-liveness.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -25,6 +25,7 @@ define i64 @stackmap_liveness(i1 %c) { ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; Padding +; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .short 0 ; Num LiveOut Entries: 1 ; CHECK-NEXT: .short 2 diff --git a/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll index e2620ce353c6..f7461b925ca1 100644 --- a/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll +++ b/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll @@ -221,10 +221,10 @@ define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* ret void } -attributes #0 = { nounwind readnone } +attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } -; HSA: attributes #0 = { nounwind readnone } +; HSA: attributes #0 = { nounwind readnone speculatable } ; HSA: attributes #1 = { nounwind } ; HSA: attributes #2 = { nounwind "amdgpu-work-group-id-y" } ; HSA: attributes #3 = { nounwind "amdgpu-work-group-id-z" } diff --git a/test/CodeGen/AMDGPU/inline-asm.ll b/test/CodeGen/AMDGPU/inline-asm.ll index 0d7e07b9a624..636b45db698d 100644 --- a/test/CodeGen/AMDGPU/inline-asm.ll +++ b/test/CodeGen/AMDGPU/inline-asm.ll @@ -232,3 +232,17 @@ entry: call void asm sideeffect "; use $0 $1 ", "{VGPR0}, {VGPR1}"(i1 %val0, i1 %val1) ret void } + +; CHECK-LABEL: {{^}}muliple_def_phys_vgpr: +; CHECK: ; def v0 +; CHECK: v_mov_b32_e32 v1, v0 +; CHECK: ; def v0 +; CHECK: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1 +define amdgpu_kernel void @muliple_def_phys_vgpr() { +entry: + %def0 = call i32 asm sideeffect "; def $0 ", "={VGPR0}"() + %def1 = call i32 asm sideeffect "; def $0 ", "={VGPR0}"() + %add = shl i32 %def0, %def1 + store i32 %add, i32 addrspace(1)* undef + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll new file mode 100644 index 000000000000..617f1f19e360 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll @@ -0,0 +1,80 @@ +;RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s --check-prefix=GCN + +; GCN-LABEL: {{^}}full_mask: +; GCN: s_mov_b64 exec, -1 +; GCN: v_add_f32_e32 v0, +define amdgpu_ps float @full_mask(float %a, float %b) { +main_body: + %s = fadd float %a, %b + call void @llvm.amdgcn.init.exec(i64 -1) + ret float %s +} + +; GCN-LABEL: {{^}}partial_mask: +; GCN: s_mov_b64 exec, 0x1e240 +; GCN: v_add_f32_e32 v0, +define amdgpu_ps float @partial_mask(float %a, float %b) { +main_body: + %s = fadd float %a, %b + call void @llvm.amdgcn.init.exec(i64 123456) + ret float %s +} + +; GCN-LABEL: {{^}}input_s3off8: +; GCN: s_bfe_u32 s0, s3, 0x70008 +; GCN: s_bfm_b64 exec, s0, 0 +; GCN: s_cmp_eq_u32 s0, 64 +; GCN: s_cmov_b64 exec, -1 +; GCN: v_add_f32_e32 v0, +define amdgpu_ps float @input_s3off8(i32 inreg, i32 inreg, i32 inreg, i32 inreg %count, float %a, float %b) { +main_body: + %s = fadd float %a, %b + call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 8) + ret float %s +} + +; GCN-LABEL: {{^}}input_s0off19: +; GCN: s_bfe_u32 s0, s0, 0x70013 +; GCN: s_bfm_b64 exec, s0, 0 +; GCN: s_cmp_eq_u32 s0, 64 +; GCN: s_cmov_b64 exec, -1 +; GCN: v_add_f32_e32 v0, +define amdgpu_ps float @input_s0off19(i32 inreg %count, float %a, float %b) { +main_body: + %s = fadd float %a, %b + call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19) + ret float %s +} + +; GCN-LABEL: {{^}}reuse_input: +; GCN: s_bfe_u32 s1, s0, 0x70013 +; GCN: s_bfm_b64 exec, s1, 0 +; GCN: s_cmp_eq_u32 s1, 64 +; GCN: s_cmov_b64 exec, -1 +; GCN: v_add_i32_e32 v0, vcc, s0, v0 +define amdgpu_ps float @reuse_input(i32 inreg %count, i32 %a) { +main_body: + call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19) + %s = add i32 %a, %count + %f = sitofp i32 %s to float + ret float %f +} + +; GCN-LABEL: {{^}}reuse_input2: +; GCN: s_bfe_u32 s1, s0, 0x70013 +; GCN: s_bfm_b64 exec, s1, 0 +; GCN: s_cmp_eq_u32 s1, 64 +; GCN: s_cmov_b64 exec, -1 +; GCN: v_add_i32_e32 v0, vcc, s0, v0 +define amdgpu_ps float @reuse_input2(i32 inreg %count, i32 %a) { +main_body: + %s = add i32 %a, %count + %f = sitofp i32 %s to float + call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19) + ret float %f +} + +declare void @llvm.amdgcn.init.exec(i64) #1 +declare void @llvm.amdgcn.init.exec.from.input(i32, i32) #1 + +attributes #1 = { convergent } diff --git a/test/CodeGen/AMDGPU/zext-lid.ll b/test/CodeGen/AMDGPU/zext-lid.ll index 8eeff53ff99f..066f29277270 100644 --- a/test/CodeGen/AMDGPU/zext-lid.ll +++ b/test/CodeGen/AMDGPU/zext-lid.ll @@ -4,19 +4,19 @@ ; CHECK-NOT: and_b32 ; OPT-LABEL: @zext_grp_size_128 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.x() #2, !range !0 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.y() #2, !range !0 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.z() #2, !range !0 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !0 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !0 define amdgpu_kernel void @zext_grp_size_128(i32 addrspace(1)* nocapture %arg) #0 { bb: - %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #2 + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = and i32 %tmp, 127 store i32 %tmp1, i32 addrspace(1)* %arg, align 4 - %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y() #2 + %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y() %tmp3 = and i32 %tmp2, 127 %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1 store i32 %tmp3, i32 addrspace(1)* %tmp4, align 4 - %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z() #2 + %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z() %tmp6 = and i32 %tmp5, 127 %tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2 store i32 %tmp6, i32 addrspace(1)* %tmp7, align 4 @@ -24,19 +24,19 @@ bb: } ; OPT-LABEL: @zext_grp_size_32x4x1 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.x() #2, !range !2 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.y() #2, !range !3 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.z() #2, !range !4 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !2 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !3 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !4 define amdgpu_kernel void @zext_grp_size_32x4x1(i32 addrspace(1)* nocapture %arg) #0 !reqd_work_group_size !0 { bb: - %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #2 + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = and i32 %tmp, 31 store i32 %tmp1, i32 addrspace(1)* %arg, align 4 - %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y() #2 + %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y() %tmp3 = and i32 %tmp2, 3 %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1 store i32 %tmp3, i32 addrspace(1)* %tmp4, align 4 - %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z() #2 + %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z() %tmp6 = and i32 %tmp5, 1 %tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2 store i32 %tmp6, i32 addrspace(1)* %tmp7, align 4 @@ -44,19 +44,19 @@ bb: } ; OPT-LABEL: @zext_grp_size_512 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.x() #2, !range !5 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.y() #2, !range !5 -; OPT: tail call i32 @llvm.amdgcn.workitem.id.z() #2, !range !5 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !5 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !5 +; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !5 define amdgpu_kernel void @zext_grp_size_512(i32 addrspace(1)* nocapture %arg) #1 { bb: - %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #2 + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = and i32 %tmp, 65535 store i32 %tmp1, i32 addrspace(1)* %arg, align 4 - %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y() #2 + %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y() %tmp3 = and i32 %tmp2, 65535 %tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1 store i32 %tmp3, i32 addrspace(1)* %tmp4, align 4 - %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z() #2 + %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z() %tmp6 = and i32 %tmp5, 65535 %tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2 store i32 %tmp6, i32 addrspace(1)* %tmp7, align 4 @@ -71,7 +71,8 @@ declare i32 @llvm.amdgcn.workitem.id.z() #2 attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,128" } attributes #1 = { nounwind "amdgpu-flat-work-group-size"="512,512" } -attributes #2 = { nounwind readnone } +attributes #2 = { nounwind readnone speculatable } +attributes #3 = { nounwind readnone } !0 = !{i32 32, i32 4, i32 1} diff --git a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll index cf77ce352074..44fe7410b42c 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -128,10 +128,10 @@ define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4 ; CHECK: liveins: %r0, %r1, %r2, %r3 -; CHECK: [[VREGP2:%[0-9]+]]{{.*}} = COPY %r2 -; CHECK: [[FIP5:%[0-9]+]]{{.*}} = G_FRAME_INDEX %fixed-stack.[[P5]] -; CHECK: [[VREGP5:%[0-9]+]]{{.*}} = G_LOAD [[FIP5]] -; CHECK: [[SUM:%[0-9]+]]{{.*}} = G_ADD [[VREGP2]], [[VREGP5]] +; CHECK: [[VREGP2:%[0-9]+]](s32) = COPY %r2 +; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]] +; CHECK: [[VREGP5:%[0-9]+]](s32) = G_LOAD [[FIP5]]{{.*}}load 4 +; CHECK: [[SUM:%[0-9]+]](s32) = G_ADD [[VREGP2]], [[VREGP5]] ; CHECK: %r0 = COPY [[SUM]] ; CHECK: BX_RET 14, _, implicit %r0 entry: @@ -146,10 +146,11 @@ define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK: liveins: %r0, %r1, %r2, %r3 -; CHECK: [[VREGP1:%[0-9]+]]{{.*}} = COPY %r1 -; CHECK: [[FIP5:%[0-9]+]]{{.*}} = G_FRAME_INDEX %fixed-stack.[[P5]] -; CHECK: [[VREGP5:%[0-9]+]]{{.*}} = G_LOAD [[FIP5]](p0) -; CHECK: [[SUM:%[0-9]+]]{{.*}} = G_ADD [[VREGP1]], [[VREGP5]] +; CHECK: [[VREGP1:%[0-9]+]](s16) = COPY %r1 +; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]] +; CHECK: [[VREGP5EXT:%[0-9]+]](s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 +; CHECK: [[VREGP5:%[0-9]+]](s16) = G_TRUNC [[VREGP5EXT]] +; CHECK: [[SUM:%[0-9]+]](s16) = G_ADD [[VREGP1]], [[VREGP5]] ; CHECK: %r0 = COPY [[SUM]] ; CHECK: BX_RET 14, _, implicit %r0 entry: @@ -164,10 +165,29 @@ define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK: liveins: %r0, %r1, %r2, %r3 -; CHECK: [[VREGP2:%[0-9]+]]{{.*}} = COPY %r2 -; CHECK: [[FIP4:%[0-9]+]]{{.*}} = G_FRAME_INDEX %fixed-stack.[[P4]] -; CHECK: [[VREGP4:%[0-9]+]]{{.*}} = G_LOAD [[FIP4]](p0) -; CHECK: [[SUM:%[0-9]+]]{{.*}} = G_ADD [[VREGP2]], [[VREGP4]] +; CHECK: [[VREGP2:%[0-9]+]](s8) = COPY %r2 +; CHECK: [[FIP4:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P4]] +; CHECK: [[VREGP4EXT:%[0-9]+]](s32) = G_LOAD [[FIP4]](p0){{.*}}load 4 +; CHECK: [[VREGP4:%[0-9]+]](s8) = G_TRUNC [[VREGP4EXT]] +; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[VREGP2]], [[VREGP4]] +; CHECK: %r0 = COPY [[SUM]] +; CHECK: BX_RET 14, _, implicit %r0 +entry: + %sum = add i8 %p2, %p4 + ret i8 %sum +} + +define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, + i8 %p4, i16 %p5) { +; CHECK-LABEL: name: test_stack_args_noext +; CHECK: fixedStack: +; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 +; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 +; CHECK: liveins: %r0, %r1, %r2, %r3 +; CHECK: [[VREGP2:%[0-9]+]](s8) = COPY %r2 +; CHECK: [[FIP4:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P4]] +; CHECK: [[VREGP4:%[0-9]+]](s8) = G_LOAD [[FIP4]](p0){{.*}}load 1 +; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: %r0 = COPY [[SUM]] ; CHECK: BX_RET 14, _, implicit %r0 entry: @@ -175,11 +195,28 @@ entry: ret i8 %sum } +define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2, i1 %p3, + i8 signext %p4, i16 signext %p5) { +; CHECK-LABEL: name: test_stack_args_extend_the_extended +; CHECK: fixedStack: +; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 +; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 +; CHECK: liveins: %r0, %r1, %r2, %r3 +; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]] +; CHECK: [[VREGP5SEXT:%[0-9]+]](s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 +; CHECK: [[VREGP5:%[0-9]+]](s16) = G_TRUNC [[VREGP5SEXT]] +; CHECK: [[VREGP5ZEXT:%[0-9]+]](s32) = G_ZEXT [[VREGP5]] +; CHECK: %r0 = COPY [[VREGP5ZEXT]] +; CHECK: BX_RET 14, _, implicit %r0 +entry: + ret i16 %p5 +} + define i16 @test_ptr_arg(i16* %p) { ; CHECK-LABEL: name: test_ptr_arg ; CHECK: liveins: %r0 ; CHECK: [[VREGP:%[0-9]+]](p0) = COPY %r0 -; CHECK: [[VREGV:%[0-9]+]](s16) = G_LOAD [[VREGP]](p0) +; CHECK: [[VREGV:%[0-9]+]](s16) = G_LOAD [[VREGP]](p0){{.*}}load 2 entry: %v = load i16, i16* %p ret i16 %v @@ -190,7 +227,7 @@ define i32* @test_ptr_ret(i32** %p) { ; CHECK-LABEL: name: test_ptr_ret ; CHECK: liveins: %r0 ; CHECK: [[VREGP:%[0-9]+]](p0) = COPY %r0 -; CHECK: [[VREGV:%[0-9]+]](p0) = G_LOAD [[VREGP]](p0) +; CHECK: [[VREGV:%[0-9]+]](p0) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: %r0 = COPY [[VREGV]] ; CHECK: BX_RET 14, _, implicit %r0 entry: @@ -203,9 +240,9 @@ define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) { ; CHECK: fixedStack: ; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK: liveins: %r0, %r1, %r2, %r3 -; CHECK: [[FIP:%[0-9]+]]{{.*}} = G_FRAME_INDEX %fixed-stack.[[P]] -; CHECK: [[VREGP:%[0-9]+]](p0) = G_LOAD [[FIP]](p0) -; CHECK: [[VREGV:%[0-9]+]](s32) = G_LOAD [[VREGP]](p0) +; CHECK: [[FIP:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P]] +; CHECK: [[VREGP:%[0-9]+]](p0) = G_LOAD [[FIP]](p0){{.*}}load 4 +; CHECK: [[VREGV:%[0-9]+]](s32) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: %r0 = COPY [[VREGV]] ; CHECK: BX_RET 14, _, implicit %r0 entry: @@ -222,7 +259,7 @@ define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2, ; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: [[VREGP1:%[0-9]+]](s32) = COPY %r1 ; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]] -; CHECK: [[VREGP5:%[0-9]+]](s32) = G_LOAD [[FIP5]](p0) +; CHECK: [[VREGP5:%[0-9]+]](s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]](s32) = G_FADD [[VREGP1]], [[VREGP5]] ; CHECK: %r0 = COPY [[VREGV]] ; CHECK: BX_RET 14, _, implicit %r0 @@ -251,7 +288,7 @@ define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2, ; CHECK: liveins: %s0, %s1, %s2, %s3, %s4, %s5, %s6, %s7, %s8, %s9, %s10, %s11, %s12, %s13, %s14, %s15 ; CHECK: [[VREGP1:%[0-9]+]](s32) = COPY %s1 ; CHECK: [[FIQ1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] -; CHECK: [[VREGQ1:%[0-9]+]](s32) = G_LOAD [[FIQ1]](p0) +; CHECK: [[VREGQ1:%[0-9]+]](s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]](s32) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: %s0 = COPY [[VREGV]] ; CHECK: BX_RET 14, _, implicit %s0 @@ -272,7 +309,7 @@ define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double ; CHECK: liveins: %d0, %d1, %d2, %d3, %d4, %d5, %d6, %d7 ; CHECK: [[VREGP1:%[0-9]+]](s64) = COPY %d1 ; CHECK: [[FIQ1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] -; CHECK: [[VREGQ1:%[0-9]+]](s64) = G_LOAD [[FIQ1]](p0) +; CHECK: [[VREGQ1:%[0-9]+]](s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: %d0 = COPY [[VREGV]] ; CHECK: BX_RET 14, _, implicit %d0 @@ -295,7 +332,7 @@ define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p ; LITTLE: [[VREGP1:%[0-9]+]](s64) = G_SEQUENCE [[VREGP1LO]](s32), 0, [[VREGP1HI]](s32), 32 ; BIG: [[VREGP1:%[0-9]+]](s64) = G_SEQUENCE [[VREGP1HI]](s32), 0, [[VREGP1LO]](s32), 32 ; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]] -; CHECK: [[VREGP5:%[0-9]+]](s64) = G_LOAD [[FIP5]](p0) +; CHECK: [[VREGP5:%[0-9]+]](s64) = G_LOAD [[FIP5]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP1]], [[VREGP5]] ; LITTLE: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0 ; LITTLE: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32 @@ -322,7 +359,7 @@ define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler, ; CHECK: liveins: %d0, %d2, %d3, %d4, %d5, %d6, %d7, %s2 ; CHECK: [[VREGP1:%[0-9]+]](s64) = COPY %d2 ; CHECK: [[FIQ1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] -; CHECK: [[VREGQ1:%[0-9]+]](s64) = G_LOAD [[FIQ1]](p0) +; CHECK: [[VREGQ1:%[0-9]+]](s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: %d0 = COPY [[VREGV]] ; CHECK: BX_RET 14, _, implicit %d0 @@ -342,7 +379,7 @@ define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0, ; LITTLE: [[VREGP0:%[0-9]+]](s64) = G_SEQUENCE [[VREGP0LO]](s32), 0, [[VREGP0HI]](s32), 32 ; BIG: [[VREGP0:%[0-9]+]](s64) = G_SEQUENCE [[VREGP0HI]](s32), 0, [[VREGP0LO]](s32), 32 ; CHECK: [[FIP1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P1]] -; CHECK: [[VREGP1:%[0-9]+]](s64) = G_LOAD [[FIP1]](p0) +; CHECK: [[VREGP1:%[0-9]+]](s64) = G_LOAD [[FIP1]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP0]], [[VREGP1]] ; LITTLE: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0 ; LITTLE: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32 @@ -367,7 +404,7 @@ define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler, ; LITTLE: [[VREGP0:%[0-9]+]](s64) = G_SEQUENCE [[VREGP0LO]](s32), 0, [[VREGP0HI]](s32), 32 ; BIG: [[VREGP0:%[0-9]+]](s64) = G_SEQUENCE [[VREGP0HI]](s32), 0, [[VREGP0LO]](s32), 32 ; CHECK: [[FIP1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P1]] -; CHECK: [[VREGP1:%[0-9]+]](s64) = G_LOAD [[FIP1]](p0) +; CHECK: [[VREGP1:%[0-9]+]](s64) = G_LOAD [[FIP1]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP0]], [[VREGP1]] ; LITTLE: [[VREGVLO:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 0 ; LITTLE: [[VREGVHI:%[0-9]+]](s32) = G_EXTRACT [[VREGV]](s64), 32 diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/test/CodeGen/ARM/GlobalISel/arm-isel.ll index da02bfe68519..57ccff90c0bb 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-isel.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-isel.ll @@ -197,6 +197,17 @@ entry: ret i8 %sum } +define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4) { +; CHECK-LABEL: test_stack_args_noext: +; CHECK: mov [[P4ADDR:r[0-9]+]], sp +; CHECK: ldrb [[P4:r[0-9]+]], {{.*}}[[P4ADDR]] +; CHECK: add r0, r2, [[P4]] +; CHECK: bx lr +entry: + %sum = add i8 %p2, %p4 + ret i8 %sum +} + define i32 @test_ptr_arg_in_reg(i32* %p) { ; CHECK-LABEL: test_ptr_arg_in_reg: ; CHECK: ldr r0, [r0] diff --git a/test/CodeGen/ARM/bool-ext-inc.ll b/test/CodeGen/ARM/bool-ext-inc.ll index b91b9b258991..5f2ba8b109a7 100644 --- a/test/CodeGen/ARM/bool-ext-inc.ll +++ b/test/CodeGen/ARM/bool-ext-inc.ll @@ -4,7 +4,7 @@ define i32 @sext_inc(i1 zeroext %x) { ; CHECK-LABEL: sext_inc: ; CHECK: @ BB#0: -; CHECK-NEXT: rsb r0, r0, #1 +; CHECK-NEXT: eor r0, r0, #1 ; CHECK-NEXT: mov pc, lr %ext = sext i1 %x to i32 %add = add i32 %ext, 1 @@ -14,14 +14,12 @@ define i32 @sext_inc(i1 zeroext %x) { define <4 x i32> @sext_inc_vec(<4 x i1> %x) { ; CHECK-LABEL: sext_inc_vec: ; CHECK: @ BB#0: -; CHECK-NEXT: vmov d16, r0, r1 -; CHECK-NEXT: vmov.i32 q9, #0x1f -; CHECK-NEXT: vmov.i32 q10, #0x1 +; CHECK-NEXT: vmov.i16 d16, #0x1 +; CHECK-NEXT: vmov d17, r0, r1 +; CHECK-NEXT: vmov.i32 q9, #0x1 +; CHECK-NEXT: veor d16, d17, d16 ; CHECK-NEXT: vmovl.u16 q8, d16 -; CHECK-NEXT: vneg.s32 q9, q9 -; CHECK-NEXT: vshl.i32 q8, q8, #31 -; CHECK-NEXT: vshl.s32 q8, q8, q9 -; CHECK-NEXT: vadd.i32 q8, q8, q10 +; CHECK-NEXT: vand q8, q8, q9 ; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: mov pc, lr @@ -38,8 +36,8 @@ define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-NEXT: vmov.i32 q10, #0x1 ; CHECK-NEXT: vld1.64 {d16, d17}, [r12] ; CHECK-NEXT: vmov d18, r0, r1 -; CHECK-NEXT: vcgt.s32 q8, q9, q8 -; CHECK-NEXT: vadd.i32 q8, q8, q10 +; CHECK-NEXT: vcge.s32 q8, q8, q9 +; CHECK-NEXT: vand q8, q8, q10 ; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: mov pc, lr @@ -54,12 +52,11 @@ define <4 x i32> @cmpne_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK: @ BB#0: ; CHECK-NEXT: mov r12, sp ; CHECK-NEXT: vmov d19, r2, r3 +; CHECK-NEXT: vmov.i32 q10, #0x1 ; CHECK-NEXT: vld1.64 {d16, d17}, [r12] ; CHECK-NEXT: vmov d18, r0, r1 ; CHECK-NEXT: vceq.i32 q8, q9, q8 -; CHECK-NEXT: vmov.i32 q9, #0x1 -; CHECK-NEXT: vmvn q8, q8 -; CHECK-NEXT: vadd.i32 q8, q8, q9 +; CHECK-NEXT: vand q8, q8, q10 ; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: vmov r2, r3, d17 ; CHECK-NEXT: mov pc, lr diff --git a/test/CodeGen/AVR/calling-conv/c/stack.ll b/test/CodeGen/AVR/calling-conv/c/stack.ll index 00ff7d1acd80..52b6427476ab 100644 --- a/test/CodeGen/AVR/calling-conv/c/stack.ll +++ b/test/CodeGen/AVR/calling-conv/c/stack.ll @@ -11,15 +11,15 @@ define void @ret_void_args_i64_i64_i32(i64 %a, i64 %b, i32 %c) { ; CHECK-NEXT: in r29, 62 ; Load the top two bytes from the 32-bit int. - ; CHECK-NEXT: ldd r24, Y+7 - ; CHECK-NEXT: ldd r25, Y+8 + ; CHECK-NEXT: ldd r24, Y+5 + ; CHECK-NEXT: ldd r25, Y+6 ; Store the top two bytes of the 32-bit int to memory. ; CHECK-NEXT: sts 7, r25 ; CHECK-NEXT: sts 6, r24 ; Load the bottom two bytes from the 32-bit int. - ; CHECK-NEXT: ldd r24, Y+5 - ; CHECK-NEXT: ldd r25, Y+6 + ; CHECK-NEXT: ldd r24, Y+3 + ; CHECK-NEXT: ldd r25, Y+4 ; Store the bottom two bytes of the 32-bit int to memory. ; CHECK-NEXT: sts 5, r25 ; CHECK-NEXT: sts 4, r24 diff --git a/test/CodeGen/AVR/return.ll b/test/CodeGen/AVR/return.ll index d57f435fd11c..1f80576af288 100644 --- a/test/CodeGen/AVR/return.ll +++ b/test/CodeGen/AVR/return.ll @@ -96,14 +96,14 @@ define i64 @return64_arg2(i64 %x, i64 %y, i64 %z) { ; CHECK-LABEL: return64_arg2: ; CHECK: push r28 ; CHECK: push r29 -; CHECK: ldd r18, Y+5 -; CHECK: ldd r19, Y+6 -; CHECK: ldd r20, Y+7 -; CHECK: ldd r21, Y+8 -; CHECK: ldd r22, Y+9 -; CHECK: ldd r23, Y+10 -; CHECK: ldd r24, Y+11 -; CHECK: ldd r25, Y+12 +; CHECK: ldd r18, Y+3 +; CHECK: ldd r19, Y+4 +; CHECK: ldd r20, Y+5 +; CHECK: ldd r21, Y+6 +; CHECK: ldd r22, Y+7 +; CHECK: ldd r23, Y+8 +; CHECK: ldd r24, Y+9 +; CHECK: ldd r25, Y+10 ; CHECK: pop r29 ; CHECK: pop r28 ret i64 %z @@ -113,10 +113,10 @@ define i32 @return64_trunc(i32 %a, i32 %b, i32 %c, i64 %d) { ; CHECK-LABEL: return64_trunc: ; CHECK: push r28 ; CHECK: push r29 -; CHECK: ldd r22, Y+5 -; CHECK: ldd r23, Y+6 -; CHECK: ldd r24, Y+7 -; CHECK: ldd r25, Y+8 +; CHECK: ldd r22, Y+3 +; CHECK: ldd r23, Y+4 +; CHECK: ldd r24, Y+5 +; CHECK: ldd r25, Y+6 ; CHECK: pop r29 ; CHECK: pop r28 %result = trunc i64 %d to i32 diff --git a/test/CodeGen/AVR/rot.ll b/test/CodeGen/AVR/rot.ll new file mode 100644 index 000000000000..e43daf3e6aa8 --- /dev/null +++ b/test/CodeGen/AVR/rot.ll @@ -0,0 +1,55 @@ +; RUN: llc < %s -march=avr | FileCheck %s + +; Bit rotation tests. + +; CHECK-LABEL: rol8: +define i8 @rol8(i8 %val, i8 %amt) { + ; CHECK: andi r22, 7 + + ; CHECK-NEXT: cp r22, r0 + ; CHECK-NEXT: breq LBB0_2 + +; CHECK-NEXT: LBB0_1: + ; CHECK-NEXT: rol r24 + ; CHECK-NEXT: subi r22, 1 + ; CHECK-NEXT: brne LBB0_1 + +; CHECK-NEXT:LBB0_2: + ; CHECK-NEXT: ret + %mod = urem i8 %amt, 8 + + %inv = sub i8 8, %mod + %parta = shl i8 %val, %mod + %partb = lshr i8 %val, %inv + + %rotl = or i8 %parta, %partb + + ret i8 %rotl +} + + +; CHECK-LABEL: ror8: +define i8 @ror8(i8 %val, i8 %amt) { + ; CHECK: andi r22, 7 + + ; CHECK-NEXT: cp r22, r0 + ; CHECK-NEXT: breq LBB1_2 + +; CHECK-NEXT: LBB1_1: + ; CHECK-NEXT: ror r24 + ; CHECK-NEXT: subi r22, 1 + ; CHECK-NEXT: brne LBB1_1 + +; CHECK-NEXT:LBB1_2: + ; CHECK-NEXT: ret + %mod = urem i8 %amt, 8 + + %inv = sub i8 8, %mod + %parta = lshr i8 %val, %mod + %partb = shl i8 %val, %inv + + %rotr = or i8 %parta, %partb + + ret i8 %rotr +} + diff --git a/test/CodeGen/AVR/varargs.ll b/test/CodeGen/AVR/varargs.ll index 4959f2d880c8..6f727cda582d 100644 --- a/test/CodeGen/AVR/varargs.ll +++ b/test/CodeGen/AVR/varargs.ll @@ -7,12 +7,12 @@ declare void @llvm.va_end(i8*) define i16 @varargs1(i8* nocapture %x, ...) { ; CHECK-LABEL: varargs1: ; CHECK: movw r20, r28 -; CHECK: subi r20, 215 +; CHECK: subi r20, 217 ; CHECK: sbci r21, 255 ; CHECK: movw r24, r28 ; CHECK: adiw r24, 3 -; CHECK: ldd r22, Y+39 -; CHECK: ldd r23, Y+40 +; CHECK: ldd r22, Y+37 +; CHECK: ldd r23, Y+38 ; CHECK: call %buffer = alloca [32 x i8] %ap = alloca i8* diff --git a/test/CodeGen/BPF/mem_offset_be.ll b/test/CodeGen/BPF/mem_offset_be.ll new file mode 100644 index 000000000000..e5e352783d70 --- /dev/null +++ b/test/CodeGen/BPF/mem_offset_be.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=bpfeb -show-mc-encoding < %s | FileCheck %s + +; Function Attrs: nounwind +define i32 @bpf_prog1(i8* nocapture readnone) local_unnamed_addr #0 { +; CHECK: r1 = 590618314553ll # encoding: [0x18,0x10,0x00,0x00,0x83,0x98,0x47,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x89] +; CHECK: r1 += -1879113726 # encoding: [0x07,0x10,0x00,0x00,0x8f,0xff,0x00,0x02] +; CHECK: r0 = *(u64 *)(r1 + 0) # encoding: [0x79,0x01,0x00,0x00,0x00,0x00,0x00,0x00] + %2 = alloca i64, align 8 + %3 = bitcast i64* %2 to i8* + store volatile i64 590618314553, i64* %2, align 8 + %4 = load volatile i64, i64* %2, align 8 + %5 = add i64 %4, -1879113726 + %6 = inttoptr i64 %5 to i64* + %7 = load i64, i64* %6, align 8 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + diff --git a/test/CodeGen/Hexagon/cfgopt-fall-through.ll b/test/CodeGen/Hexagon/cfgopt-fall-through.ll new file mode 100644 index 000000000000..be234aafc0bb --- /dev/null +++ b/test/CodeGen/Hexagon/cfgopt-fall-through.ll @@ -0,0 +1,71 @@ +; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; REQUIRES: asserts + +; Check for some sane output. This test used to crash. +; CHECK: jumpr r31 + + +define i32 @fred(i32 %a0, i8 zeroext %a1) local_unnamed_addr #0 { +b2: + br i1 undef, label %b4, label %b3 + +b3: ; preds = %b2 + unreachable + +b4: ; preds = %b2 + br i1 undef, label %b19, label %b5 + +b5: ; preds = %b4 + br i1 undef, label %b6, label %b12 + +b6: ; preds = %b5 + switch i8 %a1, label %b17 [ + i8 2, label %b7 + i8 5, label %b7 + i8 1, label %b7 + i8 3, label %b8 + ] + +b7: ; preds = %b6, %b6, %b6 + unreachable + +b8: ; preds = %b6 + br i1 undef, label %b11, label %b9 + +b9: ; preds = %b8 + %v10 = or i32 undef, 0 + br label %b15 + +b11: ; preds = %b8 + unreachable + +b12: ; preds = %b5 + switch i8 %a1, label %b17 [ + i8 5, label %b13 + i8 1, label %b13 + i8 2, label %b14 + i8 3, label %b15 + ] + +b13: ; preds = %b12, %b12 + store i32 %a0, i32* undef, align 4 + br label %b17 + +b14: ; preds = %b12 + store i16 undef, i16* undef, align 4 + br label %b17 + +b15: ; preds = %b12, %b9 + %v16 = phi i32 [ 0, %b12 ], [ %v10, %b9 ] + store i32 undef, i32* undef, align 4 + br label %b17 + +b17: ; preds = %b15, %b14, %b13, %b12, %b6 + %v18 = phi i32 [ 0, %b13 ], [ 0, %b12 ], [ %v16, %b15 ], [ 0, %b14 ], [ 0, %b6 ] + ret i32 %v18 + +b19: ; preds = %b4 + unreachable +} + +attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } diff --git a/test/CodeGen/Hexagon/rdf-def-mask.ll b/test/CodeGen/Hexagon/rdf-def-mask.ll new file mode 100644 index 000000000000..3d65968911ed --- /dev/null +++ b/test/CodeGen/Hexagon/rdf-def-mask.ll @@ -0,0 +1,52 @@ +; RUN: llc -march=hexagon -O3 -verify-machineinstrs < %s | FileCheck %s +; REQUIRES: asserts + +; Check for sane output. This testcase used to crash. +; CHECK: jumpr r31 + +target triple = "hexagon" + +@g0 = external hidden unnamed_addr constant [9 x i16], align 8 + +; Function Attrs: nounwind readnone +define i64 @fred(i32 %a0) local_unnamed_addr #0 { +b1: + %v2 = icmp slt i32 %a0, 1 + br i1 %v2, label %b26, label %b3 + +b3: ; preds = %b1 + %v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a0) + %v5 = add nsw i32 %v4, -12 + %v6 = add nsw i32 %v4, -28 + %v7 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 %v6) + %v8 = add nsw i32 %v7, -8 + %v9 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 %v5) + %v10 = getelementptr inbounds [9 x i16], [9 x i16]* @g0, i32 0, i32 %v8 + %v11 = load i16, i16* %v10, align 2 + %v12 = sext i16 %v11 to i32 + %v13 = shl nsw i32 %v12, 16 + %v14 = add nsw i32 %v7, -7 + %v15 = getelementptr inbounds [9 x i16], [9 x i16]* @g0, i32 0, i32 %v14 + %v16 = load i16, i16* %v15, align 2 + %v17 = sub i16 %v11, %v16 + %v18 = and i32 %v9, 65535 + %v19 = zext i16 %v17 to i32 + %v20 = tail call i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32 %v13, i32 %v18, i32 %v19) #1 + %v21 = add nsw i32 %v4, -32 + %v22 = zext i32 %v21 to i64 + %v23 = shl nuw i64 %v22, 32 + %v24 = zext i32 %v20 to i64 + %v25 = or i64 %v23, %v24 + br label %b26 + +b26: ; preds = %b3, %b1 + %v27 = phi i64 [ %v25, %b3 ], [ 2147483648, %b1 ] + ret i64 %v27 +} + +declare i32 @llvm.hexagon.S2.clb(i32) #1 +declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1 +declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1 + +attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir b/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir new file mode 100644 index 000000000000..6d6549201abf --- /dev/null +++ b/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir @@ -0,0 +1,25 @@ +# RUN: llc -march=hexagon -run-pass unreachable-mbb-elimination %s -o - | FileCheck %s + +--- +name: fred +tracksRegLiveness: true +body: | + bb.0: + liveins: %d0 + successors: %bb.2 + + %0 : doubleregs = COPY %d0 + J2_jump %bb.2, implicit-def %pc + + bb.1: + successors: %bb.2 + A2_nop + + bb.2: + ; Make sure that the subregister from the PHI operand is preserved. + ; CHECK: %[[REG:[0-9]+]] = COPY %0.isub_lo + ; CHECK: %r0 = COPY %[[REG]] + %1 : intregs = PHI %0.isub_lo, %bb.0, %0.isub_hi, %bb.1 + %r0 = COPY %1 +... + diff --git a/test/CodeGen/MIR/Generic/frame-info.mir b/test/CodeGen/MIR/Generic/frame-info.mir index 7c6e6ebbfeee..157eb99e149e 100644 --- a/test/CodeGen/MIR/Generic/frame-info.mir +++ b/test/CodeGen/MIR/Generic/frame-info.mir @@ -36,7 +36,6 @@ tracksRegLiveness: true # CHECK-NEXT: maxAlignment: # CHECK-NEXT: adjustsStack: false # CHECK-NEXT: hasCalls: false -# CHECK-NEXT: maxCallFrameSize: 0 # CHECK-NEXT: hasOpaqueSPAdjustment: false # CHECK-NEXT: hasVAStart: false # CHECK-NEXT: hasMustTailInVarArgFunc: false diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll index eece03091044..a5ecdda94ce2 100644 --- a/test/CodeGen/Mips/llvm-ir/add.ll +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -24,7 +24,7 @@ ; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 @@ -117,7 +117,7 @@ entry: ; GP64: daddu $2, $4, $5 - ; MM32: addu $3, $5, $7 + ; MM32: addu16 $3, $5, $7 ; MM32: sltu $[[T0:[0-9]+]], $3, $7 ; MM32: addu $[[T1:[0-9]+]], $[[T0]], $6 ; MM32: addu $2, $4, $[[T1]] @@ -158,16 +158,16 @@ entry: ; MM32: addu $[[T1:[0-9]+]], $7, $[[T0]] ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] ; MM32: lw $[[T3:[0-9]+]], 24($sp) - ; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]] + ; MM32: addu16 $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MM32: addu16 $[[T5:[0-9]+]], $6, $[[T4]] ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] ; MM32: lw $[[T7:[0-9]+]], 20($sp) - ; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] + ; MM32: addu16 $[[T8:[0-9]+]], $[[T6]], $[[T7]] ; MM32: lw $[[T9:[0-9]+]], 16($sp) - ; MM32: addu $[[T10:[0-9]+]], $5, $[[T8]] + ; MM32: addu16 $[[T10:[0-9]+]], $5, $[[T8]] ; MM32: sltu $[[T11:[0-9]+]], $[[T10]], $[[T7]] ; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T9]] - ; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]] + ; MM32: addu16 $[[T13:[0-9]+]], $4, $[[T12]] ; MM32: move $4, $[[T5]] ; MM32: move $5, $[[T1]] @@ -289,12 +289,12 @@ define signext i128 @add_i128_4(i128 signext %a) { ; MM32: addiu $[[T0:[0-9]+]], $7, 4 ; MM32: li16 $[[T1:[0-9]+]], 4 ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] - ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; MM32: addu16 $[[T2:[0-9]+]], $6, $[[T1]] ; MM32: li16 $[[T1]], 0 ; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MM32: addu $[[T3]], $5, $[[T3]] + ; MM32: addu16 $[[T3]], $5, $[[T3]] ; MM32: sltu $[[T1]], $[[T3]], $[[T1]] - ; MM32: addu $[[T1]], $4, $[[T1]] + ; MM32: addu16 $[[T1]], $4, $[[T1]] ; MM32: move $4, $[[T2]] ; MM32: move $5, $[[T0]] @@ -419,12 +419,12 @@ define signext i128 @add_i128_3(i128 signext %a) { ; MM32: addiu $[[T0:[0-9]+]], $7, 3 ; MM32: li16 $[[T1:[0-9]+]], 3 ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] - ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; MM32: addu16 $[[T2:[0-9]+]], $6, $[[T1]] ; MM32: li16 $[[T3:[0-9]+]], 0 ; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; MM32: addu $[[T4]], $5, $[[T4]] + ; MM32: addu16 $[[T4]], $5, $[[T4]] ; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]] - ; MM32: addu $[[T5]], $4, $[[T5]] + ; MM32: addu16 $[[T5]], $4, $[[T5]] ; MM32: move $4, $[[T2]] ; MM32: move $5, $[[T0]] diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll index 617ab3c1a21c..a730063c552f 100644 --- a/test/CodeGen/Mips/llvm-ir/sub.ll +++ b/test/CodeGen/Mips/llvm-ir/sub.ll @@ -10,7 +10,7 @@ ; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=GP32-MM,GP32,MM ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=GP32-MM,GP32,MM @@ -100,7 +100,7 @@ define signext i64 @sub_i64(i64 signext %a, i64 signext %b) { entry: ; ALL-LABEL: sub_i64: - ; GP32: subu $3, $5, $7 + ; GP32-NOT-MM subu $3, $5, $7 ; GP32: sltu $[[T0:[0-9]+]], $5, $7 ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 ; GP32: subu $2, $4, $[[T1]] @@ -138,13 +138,13 @@ entry: ; GP32-MM: lw $[[T4:[0-9]+]], 24($sp) ; GP32-MM: lw $[[T5:[0-9]+]], 28($sp) ; GP32-MM: subu $[[T1]], $7, $[[T5]] - ; GP32-MM: subu $[[T3]], $[[T6:[0-9]+]], $[[T3]] + ; GP32-MM: subu16 $[[T3]], $[[T6:[0-9]+]], $[[T3]] ; GP32-MM: sltu $[[T6]], $6, $[[T4]] - ; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]] - ; GP32-MM: subu $[[T0]], $5, $[[T0]] + ; GP32-MM: addu16 $[[T0]], $[[T6]], $[[T0]] + ; GP32-MM: subu16 $[[T0]], $5, $[[T0]] ; GP32-MM: sltu $[[T6]], $7, $[[T5]] ; GP32-MM: addu $[[T6]], $[[T6]], $[[T4]] - ; GP32-MM: subu $[[T6]], $6, $[[T6]] + ; GP32-MM: subu16 $[[T6]], $6, $[[T6]] ; GP32-MM: move $[[T2]], $[[T1]] ; GP64: dsubu $3, $5, $7 diff --git a/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll b/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll new file mode 100644 index 000000000000..b92554854c04 --- /dev/null +++ b/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -asm-show-inst -verify-machineinstrs < %s | FileCheck %s + +; Function Attrs: nounwind +define i32 @function1(i32 (i32)* %f) { +entry: +; CHECK-LABEL: function1: +; CHECK: SWSP_MM +; CHECK: LWSP_MM + %call = call i32 %f(i32 0) + ret i32 0 +} diff --git a/test/CodeGen/NVPTX/f16-instructions.ll b/test/CodeGen/NVPTX/f16-instructions.ll index 403a67f02f80..3d4140820794 100644 --- a/test/CodeGen/NVPTX/f16-instructions.ll +++ b/test/CodeGen/NVPTX/f16-instructions.ll @@ -36,6 +36,21 @@ define half @test_fadd(half %a, half %b) #0 { ret half %r } +; CHECK-LABEL: test_fadd_v1f16( +; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fadd_v1f16_param_0]; +; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_v1f16_param_1]; +; CHECK-F16-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]]; +; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] +; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] +; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]]; +; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] +; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; +; CHECK-NEXT: ret; +define <1 x half> @test_fadd_v1f16(<1 x half> %a, <1 x half> %b) #0 { + %r = fadd <1 x half> %a, %b + ret <1 x half> %r +} + ; Check that we can lower fadd with immediate arguments. ; CHECK-LABEL: test_fadd_imm_0( ; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_imm_0_param_0]; diff --git a/test/CodeGen/PowerPC/build-vector-tests.ll b/test/CodeGen/PowerPC/build-vector-tests.ll index fa4d212932f6..1bce9d4cb439 100644 --- a/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/test/CodeGen/PowerPC/build-vector-tests.ll @@ -875,8 +875,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -942,8 +942,7 @@ entry: ; P8BE: vperm ; P8BE: blr ; P8LE: lxvd2x -; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd +; P8LE-DAG: lvx ; P8LE: xxswapd ; P8LE: vperm ; P8LE: blr @@ -1036,7 +1035,6 @@ entry: ; P8LE: sldi {{r[0-9]+}}, r4, 2 ; P8LE-DAG: lxvd2x ; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd ; P8LE: xxswapd ; P8LE: vperm ; P8LE: blr @@ -1289,8 +1287,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -1315,7 +1313,7 @@ entry: ; P8BE: xvcvspsxws v2, [[REG1]] ; P8BE: blr ; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 -; P8LE: xxswapd v2, [[REG1]] +; P8LE: xxswapd ; P8LE: xvcvspsxws v2, v2 ; P8LE: blr } @@ -1359,8 +1357,7 @@ entry: ; P8BE: xvcvspsxws ; P8BE: blr ; P8LE: lxvd2x -; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd +; P8LE-DAG: lvx ; P8LE: xxswapd ; P8LE: vperm ; P8LE: xvcvspsxws @@ -1566,8 +1563,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -2036,8 +2033,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -2103,8 +2100,8 @@ entry: ; P8BE: vperm ; P8BE: blr ; P8LE: lxvd2x -; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd +; P8LE-DAG: lvx +; P8LE-NOT: xxswapd ; P8LE: xxswapd ; P8LE: vperm ; P8LE: blr @@ -2195,10 +2192,8 @@ entry: ; P8BE: vperm ; P8BE: blr ; P8LE-DAG: sldi {{r[0-9]+}}, r4, 2 -; P8LE-DAG: lxvd2x -; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd -; P8LE: xxswapd +; P8LE-DAG: lvx +; P8LE-DAG: lvx ; P8LE: vperm ; P8LE: blr } @@ -2450,8 +2445,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } @@ -2519,9 +2514,8 @@ entry: ; P8BE: vperm ; P8BE: xvcvspuxws ; P8BE: blr -; P8LE: lxvd2x ; P8LE-DAG: lxvd2x -; P8LE-DAG: xxswapd +; P8LE-DAG: lvx ; P8LE: xxswapd ; P8LE: vperm ; P8LE: xvcvspuxws @@ -2727,8 +2721,8 @@ entry: ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr -; P8LE: lxvd2x -; P8LE: xxswapd +; P8LE: lvx +; P8LE-NOT: xxswapd ; P8LE: blr } diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/test/CodeGen/PowerPC/ppc64-anyregcc.ll index 4af118b567b2..06ec561a45dd 100644 --- a/test/CodeGen/PowerPC/ppc64-anyregcc.ll +++ b/test/CodeGen/PowerPC/ppc64-anyregcc.ll @@ -31,7 +31,7 @@ target triple = "powerpc64-unknown-linux-gnu" ; CHECK-LABEL: .section .llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -75,18 +75,24 @@ target triple = "powerpc64-unknown-linux-gnu" ; CHECK-NEXT: .short 3 ; Loc 0: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Constant 3 ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 3 define i64 @test() nounwind ssp uwtable { entry: @@ -96,18 +102,22 @@ entry: ; property access 1 - %obj is an anyreg call argument and should therefore be in a register ; CHECK: .long .L{{.*}}-.L[[property_access1_BEGIN]] -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @property_access1(i8* %obj) nounwind ssp uwtable { entry: @@ -118,18 +128,22 @@ entry: ; property access 2 - %obj is an anyreg call argument and should therefore be in a register ; CHECK: .long .L{{.*}}-.L[[property_access2_BEGIN]] -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @property_access2() nounwind ssp uwtable { entry: @@ -141,18 +155,22 @@ entry: ; property access 3 - %obj is a frame index ; CHECK: .long .L{{.*}}-.L[[property_access3_BEGIN]] -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 2 locations ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Direct FP - 8 ; CHECK-NEXT: .byte 2 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 31 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 112 define i64 @property_access3() nounwind ssp uwtable { entry: @@ -164,78 +182,106 @@ entry: ; anyreg_test1 ; CHECK: .long .L{{.*}}-.L[[anyreg_test1_BEGIN]] -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 14 locations ; CHECK-NEXT: .short 14 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 4: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 5: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 6: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 7: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 8: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 9: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 10: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 11: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 12: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 13: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: @@ -246,78 +292,106 @@ entry: ; anyreg_test2 ; CHECK: .long .L{{.*}}-.L[[anyreg_test2_BEGIN]] -; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; 14 locations ; CHECK-NEXT: .short 14 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 4: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 5: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 6: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 7: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 8: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 9: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 10: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 11: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 12: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 13: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: @@ -335,18 +409,24 @@ entry: ; CHECK-NEXT: .short 3 ; Loc 0: Register (some register that will be spilled to the stack) ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: @@ -365,28 +445,38 @@ entry: ; CHECK-NEXT: .short 5 ; Loc 0: Return a register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Arg0 in a Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Arg1 in a Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Arg2 spilled to FP -96 ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 31 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 128 ; Loc 4: Arg3 spilled to FP - 88 ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 31 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 136 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: diff --git a/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/test/CodeGen/PowerPC/ppc64-i128-abi.ll index 924e04a34a95..4a8fd90db3eb 100644 --- a/test/CodeGen/PowerPC/ppc64-i128-abi.ll +++ b/test/CodeGen/PowerPC/ppc64-i128-abi.ll @@ -1,5 +1,6 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE +; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \ +; RUN: --implicit-check-not xxswapd ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE @@ -8,13 +9,15 @@ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX +; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ +; RUN: --implicit-check-not xxswapd ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-LE-NOVSX +; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr < %s | FileCheck %s \ @@ -26,7 +29,7 @@ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \ -; RUN: FileCheck %s -check-prefix=CHECK-LE +; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd @x = common global <1 x i128> zeroinitializer, align 16 @y = common global <1 x i128> zeroinitializer, align 16 @@ -199,8 +202,7 @@ define <1 x i128> @call_v1i128_increment_by_one() nounwind { ret <1 x i128> %ret ; CHECK-LE-LABEL: @call_v1i128_increment_by_one -; CHECK-LE: lxvd2x [[PARAM:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK-LE: xxswapd 34, [[PARAM]] +; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}} ; CHECK-LE: bl v1i128_increment_by_one ; CHECK-LE: blr @@ -229,10 +231,8 @@ define <1 x i128> @call_v1i128_increment_by_val() nounwind { ret <1 x i128> %ret ; CHECK-LE-LABEL: @call_v1i128_increment_by_val -; CHECK-LE: lxvd2x [[PARAM1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK-LE: lxvd2x [[PARAM2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} -; CHECK-LE-DAG: xxswapd 34, [[PARAM1]] -; CHECK-LE-DAG: xxswapd 35, [[PARAM2]] +; CHECK-LE: lvx 2, {{[0-9]+}}, {{[0-9]+}} +; CHECK-LE: lvx 3, {{[0-9]+}}, {{[0-9]+}} ; CHECK-LE: bl v1i128_increment_by_val ; CHECK-LE: blr diff --git a/test/CodeGen/PowerPC/ppc64-stackmap.ll b/test/CodeGen/PowerPC/ppc64-stackmap.ll index 854cee22c342..5abc2a2a2173 100644 --- a/test/CodeGen/PowerPC/ppc64-stackmap.ll +++ b/test/CodeGen/PowerPC/ppc64-stackmap.ll @@ -44,7 +44,7 @@ target triple = "powerpc64-unknown-linux-gnu" ; CHECK-LABEL: .section .llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -101,22 +101,30 @@ target triple = "powerpc64-unknown-linux-gnu" ; CHECK-NEXT: .short 4 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 65535 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 65536 ; SmallConstant ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; LargeConstant at index 0 ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 1 @@ -133,12 +141,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @osrinline(i64 %a, i64 %b) { entry: @@ -157,12 +169,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @osrcold(i64 %a, i64 %b) { entry: @@ -197,12 +213,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) { entry: @@ -219,12 +239,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: @@ -241,12 +265,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: @@ -267,8 +295,11 @@ entry: ; Check that at least one is a spilled entry from r31. ; Location: Indirect FP + ... ; CHECK: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short ; CHECK-NEXT: .short 31 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) { entry: call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 40, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) @@ -286,8 +317,11 @@ entry: ; Check that at least one is a spilled entry from r31. ; Location: Indirect FP + ... ; CHECK: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short ; CHECK-NEXT: .short 31 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) { entry: call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) @@ -303,7 +337,9 @@ entry: ; CHECK-NEXT: .short 1 ; Loc 0: SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 33 @@ -320,8 +356,10 @@ define void @liveConstant() { ; CHECK-NEXT: .short 1 ; Loc 0: Indirect FP (r31) - offset ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 31 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long {{[0-9]+}} define void @clobberLR(i32 %a) { tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind diff --git a/test/CodeGen/PowerPC/swaps-le-1.ll b/test/CodeGen/PowerPC/swaps-le-1.ll index f3db4f5c4823..762640552703 100644 --- a/test/CodeGen/PowerPC/swaps-le-1.ll +++ b/test/CodeGen/PowerPC/swaps-le-1.ll @@ -13,6 +13,12 @@ ; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s \ ; RUN: | FileCheck -check-prefix=NOOPTSWAP %s +; LH: 2016-11-17 +; Updated align attritue from 16 to 8 to keep swap instructions tests. +; Changes have been made on little-endian to use lvx and stvx +; instructions instead of lxvd2x/xxswapd and xxswapd/stxvd2x for +; aligned vectors with elements up to 4 bytes + ; This test was generated from the following source: ; ; #define N 4096 @@ -29,10 +35,10 @@ ; } ; } -@cb = common global [4096 x i32] zeroinitializer, align 16 -@cc = common global [4096 x i32] zeroinitializer, align 16 -@cd = common global [4096 x i32] zeroinitializer, align 16 -@ca = common global [4096 x i32] zeroinitializer, align 16 +@cb = common global [4096 x i32] zeroinitializer, align 8 +@cc = common global [4096 x i32] zeroinitializer, align 8 +@cd = common global [4096 x i32] zeroinitializer, align 8 +@ca = common global [4096 x i32] zeroinitializer, align 8 define void @foo() { entry: @@ -42,63 +48,63 @@ vector.body: %index = phi i64 [ 0, %entry ], [ %index.next.3, %vector.body ] %0 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index %1 = bitcast i32* %0 to <4 x i32>* - %wide.load = load <4 x i32>, <4 x i32>* %1, align 16 + %wide.load = load <4 x i32>, <4 x i32>* %1, align 8 %2 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index %3 = bitcast i32* %2 to <4 x i32>* - %wide.load13 = load <4 x i32>, <4 x i32>* %3, align 16 + %wide.load13 = load <4 x i32>, <4 x i32>* %3, align 8 %4 = add nsw <4 x i32> %wide.load13, %wide.load %5 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index %6 = bitcast i32* %5 to <4 x i32>* - %wide.load14 = load <4 x i32>, <4 x i32>* %6, align 16 + %wide.load14 = load <4 x i32>, <4 x i32>* %6, align 8 %7 = mul nsw <4 x i32> %4, %wide.load14 %8 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index %9 = bitcast i32* %8 to <4 x i32>* - store <4 x i32> %7, <4 x i32>* %9, align 16 + store <4 x i32> %7, <4 x i32>* %9, align 8 %index.next = add nuw nsw i64 %index, 4 %10 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next %11 = bitcast i32* %10 to <4 x i32>* - %wide.load.1 = load <4 x i32>, <4 x i32>* %11, align 16 + %wide.load.1 = load <4 x i32>, <4 x i32>* %11, align 8 %12 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next %13 = bitcast i32* %12 to <4 x i32>* - %wide.load13.1 = load <4 x i32>, <4 x i32>* %13, align 16 + %wide.load13.1 = load <4 x i32>, <4 x i32>* %13, align 8 %14 = add nsw <4 x i32> %wide.load13.1, %wide.load.1 %15 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next %16 = bitcast i32* %15 to <4 x i32>* - %wide.load14.1 = load <4 x i32>, <4 x i32>* %16, align 16 + %wide.load14.1 = load <4 x i32>, <4 x i32>* %16, align 8 %17 = mul nsw <4 x i32> %14, %wide.load14.1 %18 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next %19 = bitcast i32* %18 to <4 x i32>* - store <4 x i32> %17, <4 x i32>* %19, align 16 + store <4 x i32> %17, <4 x i32>* %19, align 8 %index.next.1 = add nuw nsw i64 %index.next, 4 %20 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next.1 %21 = bitcast i32* %20 to <4 x i32>* - %wide.load.2 = load <4 x i32>, <4 x i32>* %21, align 16 + %wide.load.2 = load <4 x i32>, <4 x i32>* %21, align 8 %22 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next.1 %23 = bitcast i32* %22 to <4 x i32>* - %wide.load13.2 = load <4 x i32>, <4 x i32>* %23, align 16 + %wide.load13.2 = load <4 x i32>, <4 x i32>* %23, align 8 %24 = add nsw <4 x i32> %wide.load13.2, %wide.load.2 %25 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next.1 %26 = bitcast i32* %25 to <4 x i32>* - %wide.load14.2 = load <4 x i32>, <4 x i32>* %26, align 16 + %wide.load14.2 = load <4 x i32>, <4 x i32>* %26, align 8 %27 = mul nsw <4 x i32> %24, %wide.load14.2 %28 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next.1 %29 = bitcast i32* %28 to <4 x i32>* - store <4 x i32> %27, <4 x i32>* %29, align 16 + store <4 x i32> %27, <4 x i32>* %29, align 8 %index.next.2 = add nuw nsw i64 %index.next.1, 4 %30 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next.2 %31 = bitcast i32* %30 to <4 x i32>* - %wide.load.3 = load <4 x i32>, <4 x i32>* %31, align 16 + %wide.load.3 = load <4 x i32>, <4 x i32>* %31, align 8 %32 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next.2 %33 = bitcast i32* %32 to <4 x i32>* - %wide.load13.3 = load <4 x i32>, <4 x i32>* %33, align 16 + %wide.load13.3 = load <4 x i32>, <4 x i32>* %33, align 8 %34 = add nsw <4 x i32> %wide.load13.3, %wide.load.3 %35 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next.2 %36 = bitcast i32* %35 to <4 x i32>* - %wide.load14.3 = load <4 x i32>, <4 x i32>* %36, align 16 + %wide.load14.3 = load <4 x i32>, <4 x i32>* %36, align 8 %37 = mul nsw <4 x i32> %34, %wide.load14.3 %38 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next.2 %39 = bitcast i32* %38 to <4 x i32>* - store <4 x i32> %37, <4 x i32>* %39, align 16 + store <4 x i32> %37, <4 x i32>* %39, align 8 %index.next.3 = add nuw nsw i64 %index.next.2, 4 %40 = icmp eq i64 %index.next.3, 4096 br i1 %40, label %for.end, label %vector.body diff --git a/test/CodeGen/PowerPC/swaps-le-2.ll b/test/CodeGen/PowerPC/swaps-le-2.ll index 0963b92609f7..e7751a194f7f 100644 --- a/test/CodeGen/PowerPC/swaps-le-2.ll +++ b/test/CodeGen/PowerPC/swaps-le-2.ll @@ -2,6 +2,13 @@ ; Test swap removal when a vector splat must be adjusted to make it legal. ; + +; LH: 2016-11-17 +; Updated align attritue from 16 to 8 to keep swap instructions tests. +; Changes have been made on little-endian to use lvx and stvx +; instructions instead of lxvd2x/xxswapd and xxswapd/stxvd2x for +; aligned vectors with elements up to 4 bytes + ; Test generated from following C code: ; ; vector char vc = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; @@ -28,37 +35,37 @@ ; vir = (vector int){vi[1], vi[1], vi[1], vi[1]}; ; } -@vc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 -@vs = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 -@vi = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 -@vcr = common global <16 x i8> zeroinitializer, align 16 -@vsr = common global <8 x i16> zeroinitializer, align 16 -@vir = common global <4 x i32> zeroinitializer, align 16 +@vc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 8 +@vs = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 8 +@vi = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 8 +@vcr = common global <16 x i8> zeroinitializer, align 8 +@vsr = common global <8 x i16> zeroinitializer, align 8 +@vir = common global <4 x i32> zeroinitializer, align 8 ; Function Attrs: nounwind define void @cfoo() { entry: - %0 = load <16 x i8>, <16 x i8>* @vc, align 16 + %0 = load <16 x i8>, <16 x i8>* @vc, align 8 %vecinit30 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5> - store <16 x i8> %vecinit30, <16 x i8>* @vcr, align 16 + store <16 x i8> %vecinit30, <16 x i8>* @vcr, align 8 ret void } ; Function Attrs: nounwind define void @sfoo() { entry: - %0 = load <8 x i16>, <8 x i16>* @vs, align 16 + %0 = load <8 x i16>, <8 x i16>* @vs, align 8 %vecinit14 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6> - store <8 x i16> %vecinit14, <8 x i16>* @vsr, align 16 + store <8 x i16> %vecinit14, <8 x i16>* @vsr, align 8 ret void } ; Function Attrs: nounwind define void @ifoo() { entry: - %0 = load <4 x i32>, <4 x i32>* @vi, align 16 + %0 = load <4 x i32>, <4 x i32>* @vi, align 8 %vecinit6 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> - store <4 x i32> %vecinit6, <4 x i32>* @vir, align 16 + store <4 x i32> %vecinit6, <4 x i32>* @vir, align 8 ret void } diff --git a/test/CodeGen/PowerPC/vsx-ldst.ll b/test/CodeGen/PowerPC/vsx-ldst.ll index a146182de99b..d8dd635aab5f 100644 --- a/test/CodeGen/PowerPC/vsx-ldst.ll +++ b/test/CodeGen/PowerPC/vsx-ldst.ll @@ -14,8 +14,10 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t -; RUN: grep lxvd2x < %t | count 6 -; RUN: grep stxvd2x < %t | count 6 +; RUN: grep lxvd2x < %t | count 3 +; RUN: grep lvx < %t | count 3 +; RUN: grep stxvd2x < %t | count 3 +; RUN: grep stvx < %t | count 3 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index a5dd494a7cc3..cfea3e5696de 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -645,8 +645,8 @@ define <4 x float> @test32(<4 x float>* %a) { ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test32 -; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 -; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: lvx 2, 0, 3 +; CHECK-LE-NOT: xxswapd ; CHECK-LE: blr } @@ -663,8 +663,8 @@ define void @test33(<4 x float>* %a, <4 x float> %b) { ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test33 -; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 -; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE-NOT: xxswapd +; CHECK-LE: stvx 2, 0, 3 ; CHECK-LE: blr } @@ -716,8 +716,8 @@ define <4 x i32> @test34(<4 x i32>* %a) { ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test34 -; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 -; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: lvx 2, 0, 3 +; CHECK-LE-NOT: xxswapd ; CHECK-LE: blr } @@ -734,8 +734,8 @@ define void @test35(<4 x i32>* %a, <4 x i32> %b) { ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test35 -; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 -; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE-NOT: xxswapd +; CHECK-LE: stvx 2, 0, 3 ; CHECK-LE: blr } @@ -1150,9 +1150,9 @@ define <2 x i32> @test80(i32 %v) { ; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3 ; CHECK-LE-DAG: xxswapd [[V1:[0-9]+]], [[R1]] ; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI -; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]] +; CHECK-LE-DAG: lvx 3, 0, [[R2]] ; CHECK-LE-DAG: xxspltw 34, [[V1]] -; CHECK-LE-DAG: xxswapd 35, [[V2]] +; CHECK-LE-NOT: xxswapd 35, [[V2]] ; CHECK-LE: vadduwm 2, 2, 3 ; CHECK-LE: blr } diff --git a/test/CodeGen/X86/GlobalISel/binop.ll b/test/CodeGen/X86/GlobalISel/binop.ll index 8499dd958447..bf4c42cb4292 100644 --- a/test/CodeGen/X86/GlobalISel/binop.ll +++ b/test/CodeGen/X86/GlobalISel/binop.ll @@ -24,6 +24,28 @@ define i32 @test_add_i32(i32 %arg1, i32 %arg2) { ret i32 %ret } +define i16 @test_add_i16(i16 %arg1, i16 %arg2) { +; ALL-LABEL: test_add_i16: +; ALL: # BB#0: +; ALL-NEXT: # kill: %DI<def> %DI<kill> %RDI<def> +; ALL-NEXT: # kill: %SI<def> %SI<kill> %RSI<def> +; ALL-NEXT: leal (%rsi,%rdi), %eax +; ALL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ALL-NEXT: retq + %ret = add i16 %arg1, %arg2 + ret i16 %ret +} + +define i8 @test_add_i8(i8 %arg1, i8 %arg2) { +; ALL-LABEL: test_add_i8: +; ALL: # BB#0: +; ALL-NEXT: addb %dil, %sil +; ALL-NEXT: movl %esi, %eax +; ALL-NEXT: retq + %ret = add i8 %arg1, %arg2 + ret i8 %ret +} + define i64 @test_sub_i64(i64 %arg1, i64 %arg2) { ; ALL-LABEL: test_sub_i64: ; ALL: # BB#0: diff --git a/test/CodeGen/X86/GlobalISel/callingconv.ll b/test/CodeGen/X86/GlobalISel/callingconv.ll index ec62ece6d408..c7e4d91ac3c7 100644 --- a/test/CodeGen/X86/GlobalISel/callingconv.ll +++ b/test/CodeGen/X86/GlobalISel/callingconv.ll @@ -37,6 +37,44 @@ define i64 @test_ret_i64() { ret i64 68719476735 } +define i8 @test_arg_i8(i8 %a) { +; X32_GISEL-LABEL: test_arg_i8: +; X32_GISEL: # BB#0: +; X32_GISEL-NEXT: leal 4(%esp), %eax +; X32_GISEL-NEXT: movb (%eax), %al +; X32_GISEL-NEXT: retl +; +; X32_ISEL-LABEL: test_arg_i8: +; X32_ISEL: # BB#0: +; X32_ISEL-NEXT: movb 4(%esp), %al +; X32_ISEL-NEXT: retl +; +; X64-LABEL: test_arg_i8: +; X64: # BB#0: +; X64-NEXT: movl %edi, %eax +; X64-NEXT: retq + ret i8 %a +} + +define i16 @test_arg_i16(i16 %a) { +; X32_GISEL-LABEL: test_arg_i16: +; X32_GISEL: # BB#0: +; X32_GISEL-NEXT: leal 4(%esp), %eax +; X32_GISEL-NEXT: movzwl (%eax), %eax +; X32_GISEL-NEXT: retl +; +; X32_ISEL-LABEL: test_arg_i16: +; X32_ISEL: # BB#0: +; X32_ISEL-NEXT: movzwl 4(%esp), %eax +; X32_ISEL-NEXT: retl +; +; X64-LABEL: test_arg_i16: +; X64: # BB#0: +; X64-NEXT: movl %edi, %eax +; X64-NEXT: retq + ret i16 %a +} + define i32 @test_arg_i32(i32 %a) { ; X32_GISEL-LABEL: test_arg_i32: ; X32_GISEL: # BB#0: diff --git a/test/CodeGen/X86/GlobalISel/ext-x86-64.ll b/test/CodeGen/X86/GlobalISel/ext-x86-64.ll new file mode 100644 index 000000000000..c4d3566008b1 --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/ext-x86-64.ll @@ -0,0 +1,29 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=X64 + +; TODO merge with ext.ll after i64 sext suported on 32bit platform + +define i64 @test_sext_i8(i8 %val) { +; X64-LABEL: test_sext_i8: +; X64: # BB#0: +; X64-NEXT: movsbq %dil, %rax +; X64-NEXT: retq + %r = sext i8 %val to i64 + ret i64 %r +} + +define i64 @test_sext_i16(i16 %val) { +; X64-LABEL: test_sext_i16: +; X64: # BB#0: +; X64-NEXT: movswq %di, %rax +; X64-NEXT: retq + %r = sext i16 %val to i64 + ret i64 %r +} + +; TODO enable after selection supported +;define i64 @test_sext_i32(i32 %val) { +; %r = sext i32 %val to i64 +; ret i64 %r +;} + diff --git a/test/CodeGen/X86/GlobalISel/ext.ll b/test/CodeGen/X86/GlobalISel/ext.ll new file mode 100644 index 000000000000..3c032686130e --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/ext.ll @@ -0,0 +1,64 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=X64 +; RUN: llc -mtriple=i386-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=X32 + +define i32 @test_zext_i8(i8 %val) { +; X64-LABEL: test_zext_i8: +; X64: # BB#0: +; X64-NEXT: movzbl %dil, %eax +; X64-NEXT: retq +; +; X32-LABEL: test_zext_i8: +; X32: # BB#0: +; X32-NEXT: leal 4(%esp), %eax +; X32-NEXT: movzbl (%eax), %eax +; X32-NEXT: retl + %r = zext i8 %val to i32 + ret i32 %r +} + +define i32 @test_zext_i16(i16 %val) { +; X64-LABEL: test_zext_i16: +; X64: # BB#0: +; X64-NEXT: movzwl %di, %eax +; X64-NEXT: retq +; +; X32-LABEL: test_zext_i16: +; X32: # BB#0: +; X32-NEXT: leal 4(%esp), %eax +; X32-NEXT: movzwl (%eax), %eax +; X32-NEXT: retl + %r = zext i16 %val to i32 + ret i32 %r +} + +define i32 @test_sext_i8(i8 %val) { +; X64-LABEL: test_sext_i8: +; X64: # BB#0: +; X64-NEXT: movsbl %dil, %eax +; X64-NEXT: retq +; +; X32-LABEL: test_sext_i8: +; X32: # BB#0: +; X32-NEXT: leal 4(%esp), %eax +; X32-NEXT: movsbl (%eax), %eax +; X32-NEXT: retl + %r = sext i8 %val to i32 + ret i32 %r +} + +define i32 @test_sext_i16(i16 %val) { +; X64-LABEL: test_sext_i16: +; X64: # BB#0: +; X64-NEXT: movswl %di, %eax +; X64-NEXT: retq +; +; X32-LABEL: test_sext_i16: +; X32: # BB#0: +; X32-NEXT: leal 4(%esp), %eax +; X32-NEXT: movswl (%eax), %eax +; X32-NEXT: retl + %r = sext i16 %val to i32 + ret i32 %r +} + diff --git a/test/CodeGen/X86/GlobalISel/irtranslator-call.ll b/test/CodeGen/X86/GlobalISel/irtranslator-call.ll index c1bf44417666..bc394f6e156f 100644 --- a/test/CodeGen/X86/GlobalISel/irtranslator-call.ll +++ b/test/CodeGen/X86/GlobalISel/irtranslator-call.ll @@ -20,7 +20,6 @@ define void @test_void_return() { ; CHECK-NEXT: maxAlignment: 0 ; CHECK-NEXT: adjustsStack: false ; CHECK-NEXT: hasCalls: false -; CHECK-NEXT: maxCallFrameSize: 0 ; CHECK-NEXT: hasOpaqueSPAdjustment: false ; CHECK-NEXT: hasVAStart: false ; CHECK-NEXT: hasMustTailInVarArgFunc: false diff --git a/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir b/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir new file mode 100644 index 000000000000..25af600f2299 --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir @@ -0,0 +1,172 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s + +--- | + define i64 @test_sext_i8(i8 %val) { + %r = sext i8 %val to i64 + ret i64 %r + } + + define i64 @test_sext_i16(i16 %val) { + %r = sext i16 %val to i64 + ret i64 %r + } + + define i64 @test_sext_i32(i32 %val) { + %r = sext i32 %val to i64 + ret i64 %r + } + + define i64 @test_zext_i8(i8 %val) { + %r = zext i8 %val to i64 + ret i64 %r + } + + define i64 @test_zext_i16(i16 %val) { + %r = zext i16 %val to i64 + ret i64 %r + } + + define i64 @test_zext_i32(i32 %val) { + %r = zext i32 %val to i64 + ret i64 %r + } + +... +--- +name: test_sext_i8 +# CHECK-LABEL: name: test_sext_i8 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# CHECK: %0(s8) = COPY %edi +# CHECK-NEXT: %1(s64) = G_SEXT %0(s8) +# CHECK-NEXT: %rax = COPY %1(s64) +# CHECK-NEXT: RET 0, implicit %rax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s8) = COPY %edi + %1(s64) = G_SEXT %0(s8) + %rax = COPY %1(s64) + RET 0, implicit %rax + +... +--- +name: test_sext_i16 +# CHECK-LABEL: name: test_sext_i16 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# CHECK: %0(s16) = COPY %edi +# CHECK-NEXT: %1(s64) = G_SEXT %0(s16) +# CHECK-NEXT: %rax = COPY %1(s64) +# CHECK-NEXT: RET 0, implicit %rax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s16) = COPY %edi + %1(s64) = G_SEXT %0(s16) + %rax = COPY %1(s64) + RET 0, implicit %rax + +... +--- +name: test_sext_i32 +# CHECK-LABEL: name: test_sext_i32 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# CHECK: %0(s32) = COPY %edi +# CHECK-NEXT: %1(s64) = G_SEXT %0(s32) +# CHECK-NEXT: %rax = COPY %1(s64) +# CHECK-NEXT: RET 0, implicit %rax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s32) = COPY %edi + %1(s64) = G_SEXT %0(s32) + %rax = COPY %1(s64) + RET 0, implicit %rax + +... +--- +name: test_zext_i8 +# CHECK-LABEL: name: test_zext_i8 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# CHECK: %0(s8) = COPY %edi +# CHECK-NEXT: %1(s64) = G_ZEXT %0(s8) +# CHECK-NEXT: %rax = COPY %1(s64) +# CHECK-NEXT: RET 0, implicit %rax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s8) = COPY %edi + %1(s64) = G_ZEXT %0(s8) + %rax = COPY %1(s64) + RET 0, implicit %rax + +... +--- +name: test_zext_i16 +# CHECK-LABEL: name: test_zext_i16 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# CHECK: %0(s16) = COPY %edi +# CHECK-NEXT: %1(s64) = G_ZEXT %0(s16) +# CHECK-NEXT: %rax = COPY %1(s64) +# CHECK-NEXT: RET 0, implicit %rax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s16) = COPY %edi + %1(s64) = G_ZEXT %0(s16) + %rax = COPY %1(s64) + RET 0, implicit %rax + +... +--- +name: test_zext_i32 +# CHECK-LABEL: name: test_zext_i32 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# CHECK: %0(s32) = COPY %edi +# CHECK-NEXT: %1(s64) = G_ZEXT %0(s32) +# CHECK-NEXT: %rax = COPY %1(s64) +# CHECK-NEXT: RET 0, implicit %rax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s32) = COPY %edi + %1(s64) = G_ZEXT %0(s32) + %rax = COPY %1(s64) + RET 0, implicit %rax + +... diff --git a/test/CodeGen/X86/GlobalISel/legalize-ext.mir b/test/CodeGen/X86/GlobalISel/legalize-ext.mir new file mode 100644 index 000000000000..46457e0fff59 --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/legalize-ext.mir @@ -0,0 +1,116 @@ +# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 +--- | + define i32 @test_zext_i8(i8 %val) { + %r = zext i8 %val to i32 + ret i32 %r + } + + define i32 @test_zext_i16(i16 %val) { + %r = zext i16 %val to i32 + ret i32 %r + } + + define i32 @test_sext_i8(i8 %val) { + %r = sext i8 %val to i32 + ret i32 %r + } + + define i32 @test_sext_i16(i16 %val) { + %r = sext i16 %val to i32 + ret i32 %r + } + +... +--- +name: test_zext_i8 +# ALL-LABEL: name: test_zext_i8 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# ALL: %0(s8) = COPY %edi +# ALL-NEXT: %1(s32) = G_ZEXT %0(s8) +# ALL-NEXT: %eax = COPY %1(s32) +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s8) = COPY %edi + %1(s32) = G_ZEXT %0(s8) + %eax = COPY %1(s32) + RET 0, implicit %eax + +... +--- +name: test_zext_i16 +# ALL-LABEL: name: test_zext_i16 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# ALL: %0(s16) = COPY %edi +# ALL-NEXT: %1(s32) = G_ZEXT %0(s16) +# ALL-NEXT: %eax = COPY %1(s32) +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s16) = COPY %edi + %1(s32) = G_ZEXT %0(s16) + %eax = COPY %1(s32) + RET 0, implicit %eax + +... +--- +name: test_sext_i8 +# ALL-LABEL: name: test_sext_i8 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# ALL: %0(s8) = COPY %edi +# ALL-NEXT: %1(s32) = G_SEXT %0(s8) +# ALL-NEXT: %eax = COPY %1(s32) +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s8) = COPY %edi + %1(s32) = G_SEXT %0(s8) + %eax = COPY %1(s32) + RET 0, implicit %eax + +... +--- +name: test_sext_i16 +# ALL-LABEL: name: test_sext_i16 +alignment: 4 +legalized: false +regBankSelected: false +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +# ALL: %0(s16) = COPY %edi +# ALL-NEXT: %1(s32) = G_SEXT %0(s16) +# ALL-NEXT: %eax = COPY %1(s32) +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s16) = COPY %edi + %1(s32) = G_SEXT %0(s16) + %eax = COPY %1(s32) + RET 0, implicit %eax + +... diff --git a/test/CodeGen/X86/GlobalISel/memop-x32.ll b/test/CodeGen/X86/GlobalISel/memop-x32.ll new file mode 100644 index 000000000000..49a7fd79f8b2 --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/memop-x32.ll @@ -0,0 +1,101 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=i386-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_FAST +; RUN: llc -mtriple=i386-linux-gnu -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_GREEDY + +;TODO merge with x86-64 tests (many operations not suppored yet) + +define i8 @test_load_i8(i8 * %p1) { +; ALL-LABEL: test_load_i8: +; ALL: # BB#0: +; ALL-NEXT: leal 4(%esp), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: movb (%eax), %al +; ALL-NEXT: retl + %r = load i8, i8* %p1 + ret i8 %r +} + +define i16 @test_load_i16(i16 * %p1) { +; ALL-LABEL: test_load_i16: +; ALL: # BB#0: +; ALL-NEXT: leal 4(%esp), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: movzwl (%eax), %eax +; ALL-NEXT: retl + %r = load i16, i16* %p1 + ret i16 %r +} + +define i32 @test_load_i32(i32 * %p1) { +; ALL-LABEL: test_load_i32: +; ALL: # BB#0: +; ALL-NEXT: leal 4(%esp), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: retl + %r = load i32, i32* %p1 + ret i32 %r +} + +define i8 * @test_store_i8(i8 %val, i8 * %p1) { +; ALL-LABEL: test_store_i8: +; ALL: # BB#0: +; ALL-NEXT: leal 4(%esp), %eax +; ALL-NEXT: movb (%eax), %cl +; ALL-NEXT: leal 8(%esp), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: movb %cl, (%eax) +; ALL-NEXT: retl + store i8 %val, i8* %p1 + ret i8 * %p1; +} + +define i16 * @test_store_i16(i16 %val, i16 * %p1) { +; ALL-LABEL: test_store_i16: +; ALL: # BB#0: +; ALL-NEXT: leal 4(%esp), %eax +; ALL-NEXT: movzwl (%eax), %ecx +; ALL-NEXT: leal 8(%esp), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: movw %cx, (%eax) +; ALL-NEXT: retl + store i16 %val, i16* %p1 + ret i16 * %p1; +} + +define i32 * @test_store_i32(i32 %val, i32 * %p1) { +; ALL-LABEL: test_store_i32: +; ALL: # BB#0: +; ALL-NEXT: leal 4(%esp), %eax +; ALL-NEXT: movl (%eax), %ecx +; ALL-NEXT: leal 8(%esp), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: movl %ecx, (%eax) +; ALL-NEXT: retl + store i32 %val, i32* %p1 + ret i32 * %p1; +} + +define i32* @test_load_ptr(i32** %ptr1) { +; ALL-LABEL: test_load_ptr: +; ALL: # BB#0: +; ALL-NEXT: leal 4(%esp), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: retl + %p = load i32*, i32** %ptr1 + ret i32* %p +} + +define void @test_store_ptr(i32** %ptr1, i32* %a) { +; ALL-LABEL: test_store_ptr: +; ALL: # BB#0: +; ALL-NEXT: leal 4(%esp), %eax +; ALL-NEXT: movl (%eax), %eax +; ALL-NEXT: leal 8(%esp), %ecx +; ALL-NEXT: movl (%ecx), %ecx +; ALL-NEXT: movl %ecx, (%eax) +; ALL-NEXT: retl + store i32* %a, i32** %ptr1 + ret void +} diff --git a/test/CodeGen/X86/GlobalISel/memop.ll b/test/CodeGen/X86/GlobalISel/memop.ll index f793e36026b1..a7407c0e6b75 100644 --- a/test/CodeGen/X86/GlobalISel/memop.ll +++ b/test/CodeGen/X86/GlobalISel/memop.ll @@ -187,3 +187,20 @@ define double * @test_store_double(double %val, double * %p1) { ret double * %p1; } +define i32* @test_load_ptr(i32** %ptr1) { +; ALL-LABEL: test_load_ptr: +; ALL: # BB#0: +; ALL-NEXT: movq (%rdi), %rax +; ALL-NEXT: retq + %p = load i32*, i32** %ptr1 + ret i32* %p +} + +define void @test_store_ptr(i32** %ptr1, i32* %a) { +; ALL-LABEL: test_store_ptr: +; ALL: # BB#0: +; ALL-NEXT: movq %rsi, (%rdi) +; ALL-NEXT: retq + store i32* %a, i32** %ptr1 + ret void +} diff --git a/test/CodeGen/X86/GlobalISel/X86-regbankselect.mir b/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir index 8e04239041a8..8e04239041a8 100644 --- a/test/CodeGen/X86/GlobalISel/X86-regbankselect.mir +++ b/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir diff --git a/test/CodeGen/X86/GlobalISel/select-add.mir b/test/CodeGen/X86/GlobalISel/select-add.mir index 27fcc223d2bb..7337ce12c395 100644 --- a/test/CodeGen/X86/GlobalISel/select-add.mir +++ b/test/CodeGen/X86/GlobalISel/select-add.mir @@ -14,6 +14,16 @@ ret i32 %ret } + define i16 @test_add_i16(i16 %arg1, i16 %arg2) { + %ret = add i16 %arg1, %arg2 + ret i16 %ret + } + + define i8 @test_add_i8(i8 %arg1, i8 %arg2) { + %ret = add i8 %arg1, %arg2 + ret i8 %ret + } + define float @test_add_float(float %arg1, float %arg2) { %ret = fadd float %arg1, %arg2 ret float %ret @@ -37,6 +47,7 @@ --- name: test_add_i64 +# ALL-LABEL: name: test_add_i64 legalized: true regBankSelected: true # ALL: registers: @@ -63,6 +74,7 @@ body: | --- name: test_add_i32 +# ALL-LABEL: name: test_add_i32 legalized: true regBankSelected: true # ALL: registers: @@ -87,7 +99,66 @@ body: | ... --- +name: test_add_i16 +# ALL-LABEL: name: test_add_i16 +alignment: 4 +legalized: true +regBankSelected: true +selected: false +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr16 } +# ALL-NEXT: - { id: 1, class: gr16 } +# ALL-NEXT: - { id: 2, class: gr16 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +# ALL: %0 = COPY %di +# ALL: %1 = COPY %si +# ALL: %2 = ADD16rr %0, %1, implicit-def %eflags +body: | + bb.1 (%ir-block.0): + liveins: %edi, %esi + + %0(s16) = COPY %edi + %1(s16) = COPY %esi + %2(s16) = G_ADD %0, %1 + %ax = COPY %2(s16) + RET 0, implicit %ax + +... +--- +name: test_add_i8 +# ALL-LABEL: name: test_add_i8 +alignment: 4 +legalized: true +regBankSelected: true +selected: false +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr8 } +# ALL-NEXT: - { id: 1, class: gr8 } +# ALL-NEXT: - { id: 2, class: gr8 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +# ALL: %0 = COPY %dil +# ALL: %1 = COPY %sil +# ALL: %2 = ADD8rr %0, %1, implicit-def %eflags +body: | + bb.1 (%ir-block.0): + liveins: %edi, %esi + + %0(s8) = COPY %edi + %1(s8) = COPY %esi + %2(s8) = G_ADD %0, %1 + %al = COPY %2(s8) + RET 0, implicit %al + +... +--- name: test_add_float +# ALL-LABEL: name: test_add_float alignment: 4 legalized: true regBankSelected: true @@ -122,6 +193,7 @@ body: | ... --- name: test_add_double +# ALL-LABEL: name: test_add_double alignment: 4 legalized: true regBankSelected: true @@ -156,6 +228,7 @@ body: | ... --- name: test_add_v4i32 +# ALL-LABEL: name: test_add_v4i32 alignment: 4 legalized: true regBankSelected: true @@ -191,6 +264,7 @@ body: | ... --- name: test_add_v4f32 +# ALL-LABEL: name: test_add_v4f32 alignment: 4 legalized: true regBankSelected: true diff --git a/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir new file mode 100644 index 000000000000..85b3f61a9e44 --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -0,0 +1,66 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 + +--- | + define i64 @test_sext_i8(i8 %val) { + %r = sext i8 %val to i64 + ret i64 %r + } + + define i64 @test_sext_i16(i16 %val) { + %r = sext i16 %val to i64 + ret i64 %r + } + +... +--- +name: test_sext_i8 +# ALL-LABEL: name: test_sext_i8 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr8 } +# ALL-NEXT: - { id: 1, class: gr64 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +# ALL: %0 = COPY %dil +# ALL-NEXT: %1 = MOVSX64rr8 %0 +# ALL-NEXT: %rax = COPY %1 +# ALL-NEXT: RET 0, implicit %rax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s8) = COPY %edi + %1(s64) = G_SEXT %0(s8) + %rax = COPY %1(s64) + RET 0, implicit %rax + +... +--- +name: test_sext_i16 +# ALL-LABEL: name: test_sext_i16 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr16 } +# ALL-NEXT: - { id: 1, class: gr64 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +# ALL: %0 = COPY %di +# ALL-NEXT: %1 = MOVSX64rr16 %0 +# ALL-NEXT: %rax = COPY %1 +# ALL-NEXT: RET 0, implicit %rax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s16) = COPY %edi + %1(s64) = G_SEXT %0(s16) + %rax = COPY %1(s64) + RET 0, implicit %rax + +... diff --git a/test/CodeGen/X86/GlobalISel/select-ext.mir b/test/CodeGen/X86/GlobalISel/select-ext.mir new file mode 100644 index 000000000000..63aeae89bd1a --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -0,0 +1,129 @@ +# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32 +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 + +--- | + define i32 @test_zext_i8(i8 %val) { + %r = zext i8 %val to i32 + ret i32 %r + } + + define i32 @test_zext_i16(i16 %val) { + %r = zext i16 %val to i32 + ret i32 %r + } + + define i32 @test_sext_i8(i8 %val) { + %r = sext i8 %val to i32 + ret i32 %r + } + + define i32 @test_sext_i16(i16 %val) { + %r = sext i16 %val to i32 + ret i32 %r + } + +... +--- +name: test_zext_i8 +# ALL-LABEL: name: test_zext_i8 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr8 } +# ALL-NEXT: - { id: 1, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +# ALL: %0 = COPY %dil +# ALL-NEXT: %1 = MOVZX32rr8 %0 +# ALL-NEXT: %eax = COPY %1 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s8) = COPY %edi + %1(s32) = G_ZEXT %0(s8) + %eax = COPY %1(s32) + RET 0, implicit %eax + +... +--- +name: test_zext_i16 +# ALL-LABEL: name: test_zext_i16 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr16 } +# ALL-NEXT: - { id: 1, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +# ALL: %0 = COPY %di +# ALL-NEXT: %1 = MOVZX32rr16 %0 +# ALL-NEXT: %eax = COPY %1 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s16) = COPY %edi + %1(s32) = G_ZEXT %0(s16) + %eax = COPY %1(s32) + RET 0, implicit %eax + +... +--- +name: test_sext_i8 +# ALL-LABEL: name: test_sext_i8 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr8 } +# ALL-NEXT: - { id: 1, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +# ALL: %0 = COPY %dil +# ALL-NEXT: %1 = MOVSX32rr8 %0 +# ALL-NEXT: %eax = COPY %1 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s8) = COPY %edi + %1(s32) = G_SEXT %0(s8) + %eax = COPY %1(s32) + RET 0, implicit %eax + +... +--- +name: test_sext_i16 +# ALL-LABEL: name: test_sext_i16 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr16 } +# ALL-NEXT: - { id: 1, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +# ALL: %0 = COPY %di +# ALL-NEXT: %1 = MOVSX32rr16 %0 +# ALL-NEXT: %eax = COPY %1 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + liveins: %edi + + %0(s16) = COPY %edi + %1(s32) = G_SEXT %0(s16) + %eax = COPY %1(s32) + RET 0, implicit %eax + +... diff --git a/test/CodeGen/X86/GlobalISel/select-inc.mir b/test/CodeGen/X86/GlobalISel/select-inc.mir new file mode 100644 index 000000000000..7a77864091d3 --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/select-inc.mir @@ -0,0 +1,37 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,INC +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+slow-incdec -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,ADD + +--- | + define i8 @test_add_i8(i8 %arg1) { + %ret = add i8 %arg1, 1 + ret i8 %ret + } +... + +--- +name: test_add_i8 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr8 } +# INC-NEXT: - { id: 1, class: gpr } +# ADD-NEXT: - { id: 1, class: gr8 } +# ALL-NEXT: - { id: 2, class: gr8 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +# ALL: %0 = COPY %al +# INC-NEXT: %2 = INC8r %0 +# ADD-NEXT: %1 = MOV8ri 1 +# ADD-NEXT: %2 = ADD8rr %0, %1 +body: | + bb.1 (%ir-block.0): + liveins: %al + + %0(s8) = COPY %al + %1(s8) = G_CONSTANT i8 1 + %2(s8) = G_ADD %0, %1 + %al = COPY %2(s8) + +... diff --git a/test/CodeGen/X86/GlobalISel/select-memop-x32.mir b/test/CodeGen/X86/GlobalISel/select-memop-x32.mir new file mode 100644 index 000000000000..8e6a2771db6e --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/select-memop-x32.mir @@ -0,0 +1,310 @@ +# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL + +--- | + define i8 @test_load_i8(i8* %p1) { + %r = load i8, i8* %p1 + ret i8 %r + } + + define i16 @test_load_i16(i16* %p1) { + %r = load i16, i16* %p1 + ret i16 %r + } + + define i32 @test_load_i32(i32* %p1) { + %r = load i32, i32* %p1 + ret i32 %r + } + + define i8* @test_store_i8(i8 %val, i8* %p1) { + store i8 %val, i8* %p1 + ret i8* %p1 + } + + define i16* @test_store_i16(i16 %val, i16* %p1) { + store i16 %val, i16* %p1 + ret i16* %p1 + } + + define i32* @test_store_i32(i32 %val, i32* %p1) { + store i32 %val, i32* %p1 + ret i32* %p1 + } + + define i32* @test_load_ptr(i32** %ptr1) { + %p = load i32*, i32** %ptr1 + ret i32* %p + } + + define void @test_store_ptr(i32** %ptr1, i32* %a) { + store i32* %a, i32** %ptr1 + ret void + } + +... +--- +name: test_load_i8 +# ALL-LABEL: name: test_load_i8 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr32 } +# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 2, class: gr8 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +fixedStack: + - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +# ALL: %1 = LEA32r %fixed-stack.0, 1, _, 0, _ +# ALL-NEXT: %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) +# ALL-NEXT: %2 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1) +# ALL-NEXT: %al = COPY %2 +# ALL-NEXT: RET 0, implicit %al +body: | + bb.1 (%ir-block.0): + %1(p0) = G_FRAME_INDEX %fixed-stack.0 + %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + %2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1) + %al = COPY %2(s8) + RET 0, implicit %al + +... +--- +name: test_load_i16 +# ALL-LABEL: name: test_load_i16 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr32 } +# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 2, class: gr16 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +fixedStack: + - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +# ALL: %1 = LEA32r %fixed-stack.0, 1, _, 0, _ +# ALL-NEXT: %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) +# ALL-NEXT: %2 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1) +# ALL-NEXT: %ax = COPY %2 +# ALL-NEXT: RET 0, implicit %ax +body: | + bb.1 (%ir-block.0): + %1(p0) = G_FRAME_INDEX %fixed-stack.0 + %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + %2(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1) + %ax = COPY %2(s16) + RET 0, implicit %ax + +... +--- +name: test_load_i32 +# ALL-LABEL: name: test_load_i32 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr32 } +# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 2, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +fixedStack: + - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +# ALL: %1 = LEA32r %fixed-stack.0, 1, _, 0, _ +# ALL-NEXT: %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) +# ALL-NEXT: %2 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1) +# ALL-NEXT: %eax = COPY %2 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + %1(p0) = G_FRAME_INDEX %fixed-stack.0 + %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + %2(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) + %eax = COPY %2(s32) + RET 0, implicit %eax + +... +--- +name: test_store_i8 +# ALL-LABEL: name: test_store_i8 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr8 } +# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 3, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } +fixedStack: + - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } + - { id: 1, offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false } +# ALL: %2 = LEA32r %fixed-stack.0, 1, _, 0, _ +# ALL-NEXT: %0 = MOV8rm %2, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0) +# ALL-NEXT: %3 = LEA32r %fixed-stack.1, 1, _, 0, _ +# ALL-NEXT: %1 = MOV32rm %3, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0) +# ALL-NEXT: MOV8mr %1, 1, _, 0, _, %0 :: (store 1 into %ir.p1) +# ALL-NEXT: %eax = COPY %1 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + %2(p0) = G_FRAME_INDEX %fixed-stack.1 + %0(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0) + %3(p0) = G_FRAME_INDEX %fixed-stack.0 + %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + G_STORE %0(s8), %1(p0) :: (store 1 into %ir.p1) + %eax = COPY %1(p0) + RET 0, implicit %eax + +... +--- +name: test_store_i16 +# ALL-LABEL: name: test_store_i16 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr16 } +# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 3, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } +fixedStack: + - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } + - { id: 1, offset: 0, size: 2, alignment: 16, isImmutable: true, isAliased: false } +# ALL: %2 = LEA32r %fixed-stack.0, 1, _, 0, _ +# ALL-NEXT: %0 = MOV16rm %2, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0) +# ALL-NEXT: %3 = LEA32r %fixed-stack.1, 1, _, 0, _ +# ALL-NEXT: %1 = MOV32rm %3, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0) +# ALL-NEXT: MOV16mr %1, 1, _, 0, _, %0 :: (store 2 into %ir.p1) +# ALL-NEXT: %eax = COPY %1 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + %2(p0) = G_FRAME_INDEX %fixed-stack.1 + %0(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0) + %3(p0) = G_FRAME_INDEX %fixed-stack.0 + %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p1) + %eax = COPY %1(p0) + RET 0, implicit %eax + +... +--- +name: test_store_i32 +# ALL-LABEL: name: test_store_i32 +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr32 } +# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 3, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } +fixedStack: + - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } + - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +# ALL: %2 = LEA32r %fixed-stack.0, 1, _, 0, _ +# ALL-NEXT: %0 = MOV32rm %2, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) +# ALL-NEXT: %3 = LEA32r %fixed-stack.1, 1, _, 0, _ +# ALL-NEXT: %1 = MOV32rm %3, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0) +# ALL-NEXT: MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1) +# ALL-NEXT: %eax = COPY %1 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + %2(p0) = G_FRAME_INDEX %fixed-stack.1 + %0(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0) + %3(p0) = G_FRAME_INDEX %fixed-stack.0 + %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) + %eax = COPY %1(p0) + RET 0, implicit %eax + +... +--- +name: test_load_ptr +# ALL-LABEL: name: test_load_ptr +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr32 } +# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 2, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } +fixedStack: + - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +# ALL: %1 = LEA32r %fixed-stack.0, 1, _, 0, _ +# ALL-NEXT: %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) +# ALL-NEXT: %2 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.ptr1) +# ALL-NEXT: %eax = COPY %2 +# ALL-NEXT: RET 0, implicit %eax +body: | + bb.1 (%ir-block.0): + %1(p0) = G_FRAME_INDEX %fixed-stack.0 + %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + %2(p0) = G_LOAD %0(p0) :: (load 4 from %ir.ptr1) + %eax = COPY %2(p0) + RET 0, implicit %eax + +... +--- +name: test_store_ptr +# ALL-LABEL: name: test_store_ptr +alignment: 4 +legalized: true +regBankSelected: true +# ALL: registers: +# ALL-NEXT: - { id: 0, class: gr32 } +# ALL-NEXT: - { id: 1, class: gr32 } +# ALL-NEXT: - { id: 2, class: gr32 } +# ALL-NEXT: - { id: 3, class: gr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } +fixedStack: + - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } + - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } +# ALL: %2 = LEA32r %fixed-stack.0, 1, _, 0, _ +# ALL-NEXT: %0 = MOV32rm %2, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) +# ALL-NEXT: %3 = LEA32r %fixed-stack.1, 1, _, 0, _ +# ALL-NEXT: %1 = MOV32rm %3, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0) +# ALL-NEXT: MOV32mr %0, 1, _, 0, _, %1 :: (store 4 into %ir.ptr1) +# ALL-NEXT: RET 0 +body: | + bb.1 (%ir-block.0): + %2(p0) = G_FRAME_INDEX %fixed-stack.1 + %0(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0) + %3(p0) = G_FRAME_INDEX %fixed-stack.0 + %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) + G_STORE %1(p0), %0(p0) :: (store 4 into %ir.ptr1) + RET 0 + +... diff --git a/test/CodeGen/X86/GlobalISel/select-memop.mir b/test/CodeGen/X86/GlobalISel/select-memop.mir index 943c9aceb4d1..817dc3cc9764 100644 --- a/test/CodeGen/X86/GlobalISel/select-memop.mir +++ b/test/CodeGen/X86/GlobalISel/select-memop.mir @@ -95,6 +95,15 @@ ret <4 x i32>* %p1 } + define i32* @test_load_ptr(i32** %ptr1) { + %p = load i32*, i32** %ptr1 + ret i32* %p + } + + define void @test_store_ptr(i32** %ptr1, i32* %a) { + store i32* %a, i32** %ptr1 + ret void + } ... --- # ALL-LABEL: name: test_load_i8 @@ -580,3 +589,49 @@ body: | RET 0, implicit %rax ... +--- +# ALL-LABEL: name: test_load_ptr +name: test_load_ptr +alignment: 4 +legalized: true +regBankSelected: true +selected: false +registers: +# ALL: - { id: 0, class: gr64 } +# ALL: - { id: 1, class: gr64 } + - { id: 0, class: gpr } + - { id: 1, class: gpr } +# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1) +body: | + bb.1 (%ir-block.0): + liveins: %rdi + + %0(p0) = COPY %rdi + %1(p0) = G_LOAD %0(p0) :: (load 8 from %ir.ptr1) + %rax = COPY %1(p0) + RET 0, implicit %rax + +... +--- +# ALL-LABEL: name: test_store_ptr +name: test_store_ptr +alignment: 4 +legalized: true +regBankSelected: true +selected: false +registers: +# ALL: - { id: 0, class: gr64 } +# ALL: - { id: 1, class: gr64 } + - { id: 0, class: gpr } + - { id: 1, class: gpr } +# ALL: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.ptr1) +body: | + bb.1 (%ir-block.0): + liveins: %rdi, %rsi + + %0(p0) = COPY %rdi + %1(p0) = COPY %rsi + G_STORE %1(p0), %0(p0) :: (store 8 into %ir.ptr1) + RET 0 + +... diff --git a/test/CodeGen/X86/adde-carry.ll b/test/CodeGen/X86/addcarry.ll index 9483a6b492c5..6fc07cd84dea 100644 --- a/test/CodeGen/X86/adde-carry.ll +++ b/test/CodeGen/X86/addcarry.ll @@ -47,7 +47,7 @@ define void @c(i16* nocapture %r, i64 %a, i64 %b, i16 %c) nounwind { ; CHECK-LABEL: c: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: addq %rdx, %rsi -; CHECK-NEXT: adcl $0, %ecx +; CHECK-NEXT: adcw $0, %cx ; CHECK-NEXT: movw %cx, (%rdi) ; CHECK-NEXT: retq entry: @@ -66,7 +66,7 @@ define void @d(i8* nocapture %r, i64 %a, i64 %b, i8 %c) nounwind { ; CHECK-LABEL: d: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: addq %rdx, %rsi -; CHECK-NEXT: adcl $0, %ecx +; CHECK-NEXT: adcb $0, %cl ; CHECK-NEXT: movb %cl, (%rdi) ; CHECK-NEXT: retq entry: @@ -86,25 +86,21 @@ entry: define %scalar @pr31719(%scalar* nocapture readonly %this, %scalar %arg.b) { ; CHECK-LABEL: pr31719: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: addq (%rsi), %rdx +; CHECK-NEXT: addq 8(%rsi), %rcx ; CHECK-NEXT: sbbq %r10, %r10 ; CHECK-NEXT: andl $1, %r10d -; CHECK-NEXT: addq 8(%rsi), %rcx -; CHECK-NEXT: sbbq %r11, %r11 -; CHECK-NEXT: andl $1, %r11d -; CHECK-NEXT: addq %r10, %rcx -; CHECK-NEXT: adcq $0, %r11 ; CHECK-NEXT: addq 16(%rsi), %r8 ; CHECK-NEXT: sbbq %rax, %rax ; CHECK-NEXT: andl $1, %eax -; CHECK-NEXT: addq %r11, %r8 -; CHECK-NEXT: adcq $0, %rax ; CHECK-NEXT: addq 24(%rsi), %r9 -; CHECK-NEXT: addq %rax, %r9 +; CHECK-NEXT: addq (%rsi), %rdx +; CHECK-NEXT: adcq $0, %rcx +; CHECK-NEXT: adcq %r8, %r10 +; CHECK-NEXT: adcq %r9, %rax ; CHECK-NEXT: movq %rdx, (%rdi) ; CHECK-NEXT: movq %rcx, 8(%rdi) -; CHECK-NEXT: movq %r8, 16(%rdi) -; CHECK-NEXT: movq %r9, 24(%rdi) +; CHECK-NEXT: movq %r10, 16(%rdi) +; CHECK-NEXT: movq %rax, 24(%rdi) ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: retq entry: @@ -159,12 +155,10 @@ define void @muladd(%accumulator* nocapture %this, i64 %arg.a, i64 %arg.b) { ; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: mulq %rsi ; CHECK-NEXT: addq (%rdi), %rax -; CHECK-NEXT: adcq $0, %rdx ; CHECK-NEXT: movq %rax, (%rdi) -; CHECK-NEXT: addq 8(%rdi), %rdx +; CHECK-NEXT: adcq 8(%rdi), %rdx ; CHECK-NEXT: movq %rdx, 8(%rdi) -; CHECK-NEXT: sbbl %eax, %eax -; CHECK-NEXT: subl %eax, 16(%rdi) +; CHECK-NEXT: adcl $0, 16(%rdi) ; CHECK-NEXT: retq entry: %0 = zext i64 %arg.a to i128 @@ -192,3 +186,21 @@ entry: store i32 %19, i32* %15, align 4 ret void } + +define i64 @shiftadd(i64 %a, i64 %b, i64 %c, i64 %d) { +; CHECK-LABEL: shiftadd: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: leaq (%rdx,%rcx), %rax +; CHECK-NEXT: addq %rsi, %rdi +; CHECK-NEXT: adcq $0, %rax +; CHECK-NEXT: retq +entry: + %0 = zext i64 %a to i128 + %1 = zext i64 %b to i128 + %2 = add i128 %0, %1 + %3 = lshr i128 %2, 64 + %4 = trunc i128 %3 to i64 + %5 = add i64 %c, %d + %6 = add i64 %4, %5 + ret i64 %6 +} diff --git a/test/CodeGen/X86/all-ones-vector.ll b/test/CodeGen/X86/all-ones-vector.ll index 8e050ee2404c..35f488ea448c 100644 --- a/test/CodeGen/X86/all-ones-vector.ll +++ b/test/CodeGen/X86/all-ones-vector.ll @@ -10,368 +10,442 @@ ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=knl | FileCheck %s --check-prefix=X64-AVX --check-prefix=X64-AVX256 --check-prefix=X64-AVX512 --check-prefix=X64-KNL ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s --check-prefix=X64-AVX --check-prefix=X64-AVX256 --check-prefix=X64-AVX512 --check-prefix=X64-SKX -define <16 x i8> @coo() nounwind { -; X32-SSE-LABEL: coo: +define <16 x i8> @allones_v16i8() nounwind { +; X32-SSE-LABEL: allones_v16i8: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: retl ; -; X32-AVX-LABEL: coo: +; X32-AVX-LABEL: allones_v16i8: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX-NEXT: retl ; -; X64-SSE-LABEL: coo: +; X64-SSE-LABEL: allones_v16i8: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: retq ; -; X64-AVX-LABEL: coo: +; X64-AVX-LABEL: allones_v16i8: ; X64-AVX: # BB#0: ; X64-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: retq ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> } -define <8 x i16> @soo() nounwind { -; X32-SSE-LABEL: soo: +define <8 x i16> @allones_v8i16() nounwind { +; X32-SSE-LABEL: allones_v8i16: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: retl ; -; X32-AVX-LABEL: soo: +; X32-AVX-LABEL: allones_v8i16: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX-NEXT: retl ; -; X64-SSE-LABEL: soo: +; X64-SSE-LABEL: allones_v8i16: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: retq ; -; X64-AVX-LABEL: soo: +; X64-AVX-LABEL: allones_v8i16: ; X64-AVX: # BB#0: ; X64-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: retq ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> } -define <4 x i32> @ioo() nounwind { -; X32-SSE-LABEL: ioo: +define <4 x i32> @allones_v4i32() nounwind { +; X32-SSE-LABEL: allones_v4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: retl ; -; X32-AVX-LABEL: ioo: +; X32-AVX-LABEL: allones_v4i32: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX-NEXT: retl ; -; X64-SSE-LABEL: ioo: +; X64-SSE-LABEL: allones_v4i32: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: retq ; -; X64-AVX-LABEL: ioo: +; X64-AVX-LABEL: allones_v4i32: ; X64-AVX: # BB#0: ; X64-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: retq ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> } -define <2 x i64> @loo() nounwind { -; X32-SSE-LABEL: loo: +define <2 x i64> @allones_v2i64() nounwind { +; X32-SSE-LABEL: allones_v2i64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: retl ; -; X32-AVX-LABEL: loo: +; X32-AVX-LABEL: allones_v2i64: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX-NEXT: retl ; -; X64-SSE-LABEL: loo: +; X64-SSE-LABEL: allones_v2i64: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: retq ; -; X64-AVX-LABEL: loo: +; X64-AVX-LABEL: allones_v2i64: ; X64-AVX: # BB#0: ; X64-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: retq ret <2 x i64> <i64 -1, i64 -1> } -define <2 x double> @doo() nounwind { -; X32-SSE-LABEL: doo: +define <2 x double> @allones_v2f64() nounwind { +; X32-SSE-LABEL: allones_v2f64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: retl ; -; X32-AVX-LABEL: doo: +; X32-AVX-LABEL: allones_v2f64: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX-NEXT: retl ; -; X64-SSE-LABEL: doo: +; X64-SSE-LABEL: allones_v2f64: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: retq ; -; X64-AVX-LABEL: doo: +; X64-AVX-LABEL: allones_v2f64: ; X64-AVX: # BB#0: ; X64-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: retq ret <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff> } -define <4 x float> @foo() nounwind { -; X32-SSE-LABEL: foo: +define <4 x float> @allones_v4f32() nounwind { +; X32-SSE-LABEL: allones_v4f32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: retl ; -; X32-AVX-LABEL: foo: +; X32-AVX-LABEL: allones_v4f32: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX-NEXT: retl ; -; X64-SSE-LABEL: foo: +; X64-SSE-LABEL: allones_v4f32: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: retq ; -; X64-AVX-LABEL: foo: +; X64-AVX-LABEL: allones_v4f32: ; X64-AVX: # BB#0: ; X64-AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: retq ret <4 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> } -define <32 x i8> @coo256() nounwind { -; X32-SSE-LABEL: coo256: +define <32 x i8> @allones_v32i8() nounwind { +; X32-SSE-LABEL: allones_v32i8: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: coo256: +; X32-AVX1-LABEL: allones_v32i8: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: retl ; -; X32-AVX256-LABEL: coo256: +; X32-AVX256-LABEL: allones_v32i8: ; X32-AVX256: # BB#0: ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: retl ; -; X64-SSE-LABEL: coo256: +; X64-SSE-LABEL: allones_v32i8: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: coo256: +; X64-AVX1-LABEL: allones_v32i8: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: retq ; -; X64-AVX256-LABEL: coo256: +; X64-AVX256-LABEL: allones_v32i8: ; X64-AVX256: # BB#0: ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: retq ret <32 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> } -define <16 x i16> @soo256() nounwind { -; X32-SSE-LABEL: soo256: +define <16 x i16> @allones_v16i16() nounwind { +; X32-SSE-LABEL: allones_v16i16: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: soo256: +; X32-AVX1-LABEL: allones_v16i16: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: retl ; -; X32-AVX256-LABEL: soo256: +; X32-AVX256-LABEL: allones_v16i16: ; X32-AVX256: # BB#0: ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: retl ; -; X64-SSE-LABEL: soo256: +; X64-SSE-LABEL: allones_v16i16: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: soo256: +; X64-AVX1-LABEL: allones_v16i16: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: retq ; -; X64-AVX256-LABEL: soo256: +; X64-AVX256-LABEL: allones_v16i16: ; X64-AVX256: # BB#0: ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: retq ret <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> } -define <8 x i32> @ioo256() nounwind { -; X32-SSE-LABEL: ioo256: +define <8 x i32> @allones_v8i32() nounwind { +; X32-SSE-LABEL: allones_v8i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: ioo256: +; X32-AVX1-LABEL: allones_v8i32: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: retl ; -; X32-AVX256-LABEL: ioo256: +; X32-AVX256-LABEL: allones_v8i32: ; X32-AVX256: # BB#0: ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: retl ; -; X64-SSE-LABEL: ioo256: +; X64-SSE-LABEL: allones_v8i32: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: ioo256: +; X64-AVX1-LABEL: allones_v8i32: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: retq ; -; X64-AVX256-LABEL: ioo256: +; X64-AVX256-LABEL: allones_v8i32: ; X64-AVX256: # BB#0: ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: retq ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> } -define <4 x i64> @loo256() nounwind { -; X32-SSE-LABEL: loo256: +define <4 x i64> @allones_v4i64() nounwind { +; X32-SSE-LABEL: allones_v4i64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: loo256: +; X32-AVX1-LABEL: allones_v4i64: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: retl ; -; X32-AVX256-LABEL: loo256: +; X32-AVX256-LABEL: allones_v4i64: ; X32-AVX256: # BB#0: ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: retl ; -; X64-SSE-LABEL: loo256: +; X64-SSE-LABEL: allones_v4i64: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: loo256: +; X64-AVX1-LABEL: allones_v4i64: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: retq ; -; X64-AVX256-LABEL: loo256: +; X64-AVX256-LABEL: allones_v4i64: ; X64-AVX256: # BB#0: ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: retq ret <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> } -define <4 x double> @doo256() nounwind { -; X32-SSE-LABEL: doo256: +define <4 x double> @allones_v4f64() nounwind { +; X32-SSE-LABEL: allones_v4f64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: doo256: +; X32-AVX1-LABEL: allones_v4f64: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: retl ; -; X32-AVX256-LABEL: doo256: +; X32-AVX256-LABEL: allones_v4f64: ; X32-AVX256: # BB#0: ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: retl ; -; X64-SSE-LABEL: doo256: +; X64-SSE-LABEL: allones_v4f64: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: doo256: +; X64-AVX1-LABEL: allones_v4f64: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: retq ; -; X64-AVX256-LABEL: doo256: +; X64-AVX256-LABEL: allones_v4f64: ; X64-AVX256: # BB#0: ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: retq ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff> } -define <8 x float> @foo256() nounwind { -; X32-SSE-LABEL: foo256: +define <4 x double> @allones_v4f64_optsize() nounwind optsize { +; X32-SSE-LABEL: allones_v4f64_optsize: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: foo256: +; X32-AVX1-LABEL: allones_v4f64_optsize: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: retl ; -; X32-AVX256-LABEL: foo256: +; X32-AVX256-LABEL: allones_v4f64_optsize: ; X32-AVX256: # BB#0: ; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX256-NEXT: retl ; -; X64-SSE-LABEL: foo256: +; X64-SSE-LABEL: allones_v4f64_optsize: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: foo256: +; X64-AVX1-LABEL: allones_v4f64_optsize: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: retq ; -; X64-AVX256-LABEL: foo256: +; X64-AVX256-LABEL: allones_v4f64_optsize: +; X64-AVX256: # BB#0: +; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 +; X64-AVX256-NEXT: retq + ret <4 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff> +} + +define <8 x float> @allones_v8f32() nounwind { +; X32-SSE-LABEL: allones_v8f32: +; X32-SSE: # BB#0: +; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; X32-SSE-NEXT: retl +; +; X32-AVX1-LABEL: allones_v8f32: +; X32-AVX1: # BB#0: +; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; X32-AVX1-NEXT: retl +; +; X32-AVX256-LABEL: allones_v8f32: +; X32-AVX256: # BB#0: +; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 +; X32-AVX256-NEXT: retl +; +; X64-SSE-LABEL: allones_v8f32: +; X64-SSE: # BB#0: +; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; X64-SSE-NEXT: retq +; +; X64-AVX1-LABEL: allones_v8f32: +; X64-AVX1: # BB#0: +; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; X64-AVX1-NEXT: retq +; +; X64-AVX256-LABEL: allones_v8f32: +; X64-AVX256: # BB#0: +; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 +; X64-AVX256-NEXT: retq + ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> +} + +define <8 x float> @allones_v8f32_optsize() nounwind optsize { +; X32-SSE-LABEL: allones_v8f32_optsize: +; X32-SSE: # BB#0: +; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; X32-SSE-NEXT: retl +; +; X32-AVX1-LABEL: allones_v8f32_optsize: +; X32-AVX1: # BB#0: +; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; X32-AVX1-NEXT: retl +; +; X32-AVX256-LABEL: allones_v8f32_optsize: +; X32-AVX256: # BB#0: +; X32-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 +; X32-AVX256-NEXT: retl +; +; X64-SSE-LABEL: allones_v8f32_optsize: +; X64-SSE: # BB#0: +; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; X64-SSE-NEXT: retq +; +; X64-AVX1-LABEL: allones_v8f32_optsize: +; X64-AVX1: # BB#0: +; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 +; X64-AVX1-NEXT: retq +; +; X64-AVX256-LABEL: allones_v8f32_optsize: ; X64-AVX256: # BB#0: ; X64-AVX256-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX256-NEXT: retq ret <8 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000> } -define <64 x i8> @coo512() nounwind { -; X32-SSE-LABEL: coo512: +define <64 x i8> @allones_v64i8() nounwind { +; X32-SSE-LABEL: allones_v64i8: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -379,31 +453,31 @@ define <64 x i8> @coo512() nounwind { ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: coo512: +; X32-AVX1-LABEL: allones_v64i8: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: retl ; -; X32-AVX2-LABEL: coo512: +; X32-AVX2-LABEL: allones_v64i8: ; X32-AVX2: # BB#0: ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: retl ; -; X32-KNL-LABEL: coo512: +; X32-KNL-LABEL: allones_v64i8: ; X32-KNL: # BB#0: ; X32-KNL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-KNL-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-KNL-NEXT: retl ; -; X32-SKX-LABEL: coo512: +; X32-SKX-LABEL: allones_v64i8: ; X32-SKX: # BB#0: ; X32-SKX-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-SKX-NEXT: retl ; -; X64-SSE-LABEL: coo512: +; X64-SSE-LABEL: allones_v64i8: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -411,34 +485,34 @@ define <64 x i8> @coo512() nounwind { ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: coo512: +; X64-AVX1-LABEL: allones_v64i8: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: retq ; -; X64-AVX2-LABEL: coo512: +; X64-AVX2-LABEL: allones_v64i8: ; X64-AVX2: # BB#0: ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: retq ; -; X64-KNL-LABEL: coo512: +; X64-KNL-LABEL: allones_v64i8: ; X64-KNL: # BB#0: ; X64-KNL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-KNL-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-KNL-NEXT: retq ; -; X64-SKX-LABEL: coo512: +; X64-SKX-LABEL: allones_v64i8: ; X64-SKX: # BB#0: ; X64-SKX-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X64-SKX-NEXT: retq ret <64 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> } -define <32 x i16> @soo512() nounwind { -; X32-SSE-LABEL: soo512: +define <32 x i16> @allones_v32i16() nounwind { +; X32-SSE-LABEL: allones_v32i16: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -446,31 +520,31 @@ define <32 x i16> @soo512() nounwind { ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: soo512: +; X32-AVX1-LABEL: allones_v32i16: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: retl ; -; X32-AVX2-LABEL: soo512: +; X32-AVX2-LABEL: allones_v32i16: ; X32-AVX2: # BB#0: ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: retl ; -; X32-KNL-LABEL: soo512: +; X32-KNL-LABEL: allones_v32i16: ; X32-KNL: # BB#0: ; X32-KNL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-KNL-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-KNL-NEXT: retl ; -; X32-SKX-LABEL: soo512: +; X32-SKX-LABEL: allones_v32i16: ; X32-SKX: # BB#0: ; X32-SKX-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-SKX-NEXT: retl ; -; X64-SSE-LABEL: soo512: +; X64-SSE-LABEL: allones_v32i16: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -478,34 +552,34 @@ define <32 x i16> @soo512() nounwind { ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: soo512: +; X64-AVX1-LABEL: allones_v32i16: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: retq ; -; X64-AVX2-LABEL: soo512: +; X64-AVX2-LABEL: allones_v32i16: ; X64-AVX2: # BB#0: ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: retq ; -; X64-KNL-LABEL: soo512: +; X64-KNL-LABEL: allones_v32i16: ; X64-KNL: # BB#0: ; X64-KNL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-KNL-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-KNL-NEXT: retq ; -; X64-SKX-LABEL: soo512: +; X64-SKX-LABEL: allones_v32i16: ; X64-SKX: # BB#0: ; X64-SKX-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X64-SKX-NEXT: retq ret <32 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> } -define <16 x i32> @ioo512() nounwind { -; X32-SSE-LABEL: ioo512: +define <16 x i32> @allones_v16i32() nounwind { +; X32-SSE-LABEL: allones_v16i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -513,25 +587,25 @@ define <16 x i32> @ioo512() nounwind { ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: ioo512: +; X32-AVX1-LABEL: allones_v16i32: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: retl ; -; X32-AVX2-LABEL: ioo512: +; X32-AVX2-LABEL: allones_v16i32: ; X32-AVX2: # BB#0: ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: retl ; -; X32-AVX512-LABEL: ioo512: +; X32-AVX512-LABEL: allones_v16i32: ; X32-AVX512: # BB#0: ; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; -; X64-SSE-LABEL: ioo512: +; X64-SSE-LABEL: allones_v16i32: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -539,28 +613,28 @@ define <16 x i32> @ioo512() nounwind { ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: ioo512: +; X64-AVX1-LABEL: allones_v16i32: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: retq ; -; X64-AVX2-LABEL: ioo512: +; X64-AVX2-LABEL: allones_v16i32: ; X64-AVX2: # BB#0: ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: retq ; -; X64-AVX512-LABEL: ioo512: +; X64-AVX512-LABEL: allones_v16i32: ; X64-AVX512: # BB#0: ; X64-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq ret <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> } -define <8 x i64> @loo512() nounwind { -; X32-SSE-LABEL: loo512: +define <8 x i64> @allones_v8i64() nounwind { +; X32-SSE-LABEL: allones_v8i64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -568,25 +642,25 @@ define <8 x i64> @loo512() nounwind { ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: loo512: +; X32-AVX1-LABEL: allones_v8i64: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: retl ; -; X32-AVX2-LABEL: loo512: +; X32-AVX2-LABEL: allones_v8i64: ; X32-AVX2: # BB#0: ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: retl ; -; X32-AVX512-LABEL: loo512: +; X32-AVX512-LABEL: allones_v8i64: ; X32-AVX512: # BB#0: ; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; -; X64-SSE-LABEL: loo512: +; X64-SSE-LABEL: allones_v8i64: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -594,28 +668,28 @@ define <8 x i64> @loo512() nounwind { ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: loo512: +; X64-AVX1-LABEL: allones_v8i64: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: retq ; -; X64-AVX2-LABEL: loo512: +; X64-AVX2-LABEL: allones_v8i64: ; X64-AVX2: # BB#0: ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: retq ; -; X64-AVX512-LABEL: loo512: +; X64-AVX512-LABEL: allones_v8i64: ; X64-AVX512: # BB#0: ; X64-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq ret <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1> } -define <8 x double> @doo512() nounwind { -; X32-SSE-LABEL: doo512: +define <8 x double> @allones_v8f64() nounwind { +; X32-SSE-LABEL: allones_v8f64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -623,25 +697,25 @@ define <8 x double> @doo512() nounwind { ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: doo512: +; X32-AVX1-LABEL: allones_v8f64: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: retl ; -; X32-AVX2-LABEL: doo512: +; X32-AVX2-LABEL: allones_v8f64: ; X32-AVX2: # BB#0: ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: retl ; -; X32-AVX512-LABEL: doo512: +; X32-AVX512-LABEL: allones_v8f64: ; X32-AVX512: # BB#0: ; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; -; X64-SSE-LABEL: doo512: +; X64-SSE-LABEL: allones_v8f64: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -649,28 +723,28 @@ define <8 x double> @doo512() nounwind { ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: doo512: +; X64-AVX1-LABEL: allones_v8f64: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: retq ; -; X64-AVX2-LABEL: doo512: +; X64-AVX2-LABEL: allones_v8f64: ; X64-AVX2: # BB#0: ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: retq ; -; X64-AVX512-LABEL: doo512: +; X64-AVX512-LABEL: allones_v8f64: ; X64-AVX512: # BB#0: ; X64-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq ret <8 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff, double 0xffffffffffffffff> } -define <16 x float> @foo512() nounwind { -; X32-SSE-LABEL: foo512: +define <16 x float> @allones_v16f32() nounwind { +; X32-SSE-LABEL: allones_v16f32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X32-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -678,25 +752,25 @@ define <16 x float> @foo512() nounwind { ; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X32-SSE-NEXT: retl ; -; X32-AVX1-LABEL: foo512: +; X32-AVX1-LABEL: allones_v16f32: ; X32-AVX1: # BB#0: ; X32-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX1-NEXT: retl ; -; X32-AVX2-LABEL: foo512: +; X32-AVX2-LABEL: allones_v16f32: ; X32-AVX2: # BB#0: ; X32-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X32-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X32-AVX2-NEXT: retl ; -; X32-AVX512-LABEL: foo512: +; X32-AVX512-LABEL: allones_v16f32: ; X32-AVX512: # BB#0: ; X32-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; -; X64-SSE-LABEL: foo512: +; X64-SSE-LABEL: allones_v16f32: ; X64-SSE: # BB#0: ; X64-SSE-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-SSE-NEXT: pcmpeqd %xmm1, %xmm1 @@ -704,20 +778,20 @@ define <16 x float> @foo512() nounwind { ; X64-SSE-NEXT: pcmpeqd %xmm3, %xmm3 ; X64-SSE-NEXT: retq ; -; X64-AVX1-LABEL: foo512: +; X64-AVX1-LABEL: allones_v16f32: ; X64-AVX1: # BB#0: ; X64-AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX1-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX1-NEXT: retq ; -; X64-AVX2-LABEL: foo512: +; X64-AVX2-LABEL: allones_v16f32: ; X64-AVX2: # BB#0: ; X64-AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; X64-AVX2-NEXT: retq ; -; X64-AVX512-LABEL: foo512: +; X64-AVX512-LABEL: allones_v16f32: ; X64-AVX512: # BB#0: ; X64-AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq diff --git a/test/CodeGen/X86/anyregcc.ll b/test/CodeGen/X86/anyregcc.ll index 1b51b53bd226..b75774ab12c0 100644 --- a/test/CodeGen/X86/anyregcc.ll +++ b/test/CodeGen/X86/anyregcc.ll @@ -7,7 +7,7 @@ ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -53,18 +53,24 @@ ; CHECK-NEXT: .short 3 ; Loc 0: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Constant 3 ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 3 define i64 @test() nounwind ssp uwtable { entry: @@ -79,13 +85,17 @@ entry: ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @property_access1(i8* %obj) nounwind ssp uwtable { entry: @@ -101,13 +111,17 @@ entry: ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @property_access2() nounwind ssp uwtable { entry: @@ -124,13 +138,17 @@ entry: ; CHECK-NEXT: .short 2 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Direct RBP - ofs ; CHECK-NEXT: .byte 2 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long define i64 @property_access3() nounwind ssp uwtable { entry: @@ -147,73 +165,101 @@ entry: ; CHECK-NEXT: .short 14 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 4: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 5: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 6: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 7: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 8: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 9: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 10: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 11: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 12: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 13: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: @@ -229,73 +275,101 @@ entry: ; CHECK-NEXT: .short 14 ; Loc 0: Register <-- this is the return register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 4: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 5: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 6: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 7: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 8: Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 9: Argument, still on stack ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long ; Loc 10: Argument, still on stack ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long ; Loc 11: Argument, still on stack ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long ; Loc 12: Argument, still on stack ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long ; Loc 13: Argument, still on stack ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: @@ -313,18 +387,24 @@ entry: ; CHECK-NEXT: .short 3 ; Loc 0: Register (some register that will be spilled to the stack) ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register RDI ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 5 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Register RSI ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 4 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: @@ -342,28 +422,38 @@ entry: ; CHECK-NEXT: .short 5 ; Loc 0: Return a register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 1: Arg0 in a Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 2: Arg1 in a Register ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; Loc 3: Arg2 spilled to RBP + ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long ; Loc 4: Arg3 spilled to RBP + ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: diff --git a/test/CodeGen/X86/avx-intrinsics-fast-isel.ll b/test/CodeGen/X86/avx-intrinsics-fast-isel.ll index 4a86fa22f081..1d925ff8e9bd 100644 --- a/test/CodeGen/X86/avx-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/avx-intrinsics-fast-isel.ll @@ -3774,4 +3774,58 @@ define void @test_mm256_zeroupper() nounwind { } declare void @llvm.x86.avx.vzeroupper() nounwind readnone +define <4 x double> @test_mm256_zextpd128_pd256(<2 x double> %a0) nounwind { +; X32-LABEL: test_mm256_zextpd128_pd256: +; X32: # BB#0: +; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm256_zextpd128_pd256: +; X64: # BB#0: +; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X64-NEXT: retq + %res = shufflevector <2 x double> %a0, <2 x double> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x double> %res +} + +define <8 x float> @test_mm256_zextps128_ps256(<4 x float> %a0) nounwind { +; X32-LABEL: test_mm256_zextps128_ps256: +; X32: # BB#0: +; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm256_zextps128_ps256: +; X64: # BB#0: +; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X64-NEXT: retq + %res = shufflevector <4 x float> %a0, <4 x float> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x float> %res +} + +define <4 x i64> @test_mm256_zextsi128_si256(<2 x i64> %a0) nounwind { +; X32-LABEL: test_mm256_zextsi128_si256: +; X32: # BB#0: +; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm256_zextsi128_si256: +; X64: # BB#0: +; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X64-NEXT: retq + %res = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x i64> %res +} + !0 = !{i32 1} diff --git a/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll b/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll index 2d4bf6ebb257..652f85d8833b 100644 --- a/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll @@ -1130,5 +1130,125 @@ define <16 x float> @test_mm512_maskz_unpacklo_ps(i16 %a0, <16 x float> %a1, <16 ret <16 x float> %res1 } +define <8 x double> @test_mm512_zextpd128_pd512(<2 x double> %a0) nounwind { +; X32-LABEL: test_mm512_zextpd128_pd512: +; X32: # BB#0: +; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X32-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm2 +; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X32-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm512_zextpd128_pd512: +; X64: # BB#0: +; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm2 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X64-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 +; X64-NEXT: retq + %res = shufflevector <2 x double> %a0, <2 x double> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3> + ret <8 x double> %res +} + +define <8 x double> @test_mm512_zextpd256_pd512(<4 x double> %a0) nounwind { +; X32-LABEL: test_mm512_zextpd256_pd512: +; X32: # BB#0: +; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; X32-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm512_zextpd256_pd512: +; X64: # BB#0: +; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; X64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 +; X64-NEXT: retq + %res = shufflevector <4 x double> %a0, <4 x double> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x double> %res +} + +define <16 x float> @test_mm512_zextps128_ps512(<4 x float> %a0) nounwind { +; X32-LABEL: test_mm512_zextps128_ps512: +; X32: # BB#0: +; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X32-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm2 +; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X32-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm512_zextps128_ps512: +; X64: # BB#0: +; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm2 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X64-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0 +; X64-NEXT: retq + %res = shufflevector <4 x float> %a0, <4 x float> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7> + ret <16 x float> %res +} + +define <16 x float> @test_mm512_zextps256_ps512(<8 x float> %a0) nounwind { +; X32-LABEL: test_mm512_zextps256_ps512: +; X32: # BB#0: +; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; X32-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm512_zextps256_ps512: +; X64: # BB#0: +; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-NEXT: vxorpd %ymm1, %ymm1, %ymm1 +; X64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 +; X64-NEXT: retq + %res = shufflevector <8 x float> %a0, <8 x float> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x float> %res +} + +define <8 x i64> @test_mm512_zextsi128_si512(<2 x i64> %a0) nounwind { +; X32-LABEL: test_mm512_zextsi128_si512: +; X32: # BB#0: +; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X32-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm2 +; X32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 +; X32-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm512_zextsi128_si512: +; X64: # BB#0: +; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm2 +; X64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 +; X64-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 +; X64-NEXT: retq + %res = shufflevector <2 x i64> %a0, <2 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3> + ret <8 x i64> %res +} + +define <8 x i64> @test_mm512_zextsi256_si512(<4 x i64> %a0) nounwind { +; X32-LABEL: test_mm512_zextsi256_si512: +; X32: # BB#0: +; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; X32-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 +; X32-NEXT: retl +; +; X64-LABEL: test_mm512_zextsi256_si512: +; X64: # BB#0: +; X64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; X64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 +; X64-NEXT: retq + %res = shufflevector <4 x i64> %a0, <4 x i64> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i64> %res +} + !0 = !{i32 1} diff --git a/test/CodeGen/X86/bool-ext-inc.ll b/test/CodeGen/X86/bool-ext-inc.ll index 1b69b5542556..e292ccd0be11 100644 --- a/test/CodeGen/X86/bool-ext-inc.ll +++ b/test/CodeGen/X86/bool-ext-inc.ll @@ -1,29 +1,26 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s -; FIXME: add (sext i1 X), 1 -> zext (not i1 X) +; add (sext i1 X), 1 -> zext (not i1 X) define i32 @sext_inc(i1 zeroext %x) nounwind { ; CHECK-LABEL: sext_inc: ; CHECK: # BB#0: -; CHECK-NEXT: movzbl %dil, %ecx -; CHECK-NEXT: movl $1, %eax -; CHECK-NEXT: subl %ecx, %eax +; CHECK-NEXT: xorb $1, %dil +; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: retq %ext = sext i1 %x to i32 %add = add i32 %ext, 1 ret i32 %add } -; FIXME: add (sext i1 X), 1 -> zext (not i1 X) +; add (sext i1 X), 1 -> zext (not i1 X) define <4 x i32> @sext_inc_vec(<4 x i1> %x) nounwind { ; CHECK-LABEL: sext_inc_vec: ; CHECK: # BB#0: -; CHECK-NEXT: vpslld $31, %xmm0, %xmm0 -; CHECK-NEXT: vpsrad $31, %xmm0, %xmm0 -; CHECK-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 -; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %xmm1 +; CHECK-NEXT: vandnps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq %ext = sext <4 x i1> %x to <4 x i32> %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1> @@ -35,7 +32,7 @@ define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; CHECK: # BB#0: ; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 -; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq %cmp = icmp sgt <4 x i32> %x, %y %ext = sext <4 x i1> %cmp to <4 x i32> @@ -47,10 +44,7 @@ define <4 x i32> @cmpne_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; CHECK-LABEL: cmpne_sext_inc_vec: ; CHECK: # BB#0: ; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 -; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-NEXT: retq %cmp = icmp ne <4 x i32> %x, %y %ext = sext <4 x i1> %cmp to <4 x i32> @@ -63,7 +57,7 @@ define <4 x i64> @cmpgt_sext_inc_vec256(<4 x i64> %x, <4 x i64> %y) nounwind { ; CHECK: # BB#0: ; CHECK-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vpbroadcastq {{.*}}(%rip), %ymm1 -; CHECK-NEXT: vpaddq %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: vpandn %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retq %cmp = icmp sgt <4 x i64> %x, %y %ext = sext <4 x i1> %cmp to <4 x i64> @@ -75,13 +69,11 @@ define i32 @bool_logic_and_math(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK-LABEL: bool_logic_and_math: ; CHECK: # BB#0: ; CHECK-NEXT: cmpl %esi, %edi -; CHECK-NEXT: setne %al +; CHECK-NEXT: sete %al ; CHECK-NEXT: cmpl %ecx, %edx -; CHECK-NEXT: setne %cl -; CHECK-NEXT: andb %al, %cl -; CHECK-NEXT: movzbl %cl, %ecx -; CHECK-NEXT: movl $1, %eax -; CHECK-NEXT: subl %ecx, %eax +; CHECK-NEXT: sete %cl +; CHECK-NEXT: orb %al, %cl +; CHECK-NEXT: movzbl %cl, %eax ; CHECK-NEXT: retq %cmp1 = icmp ne i32 %a, %b %cmp2 = icmp ne i32 %c, %d @@ -95,12 +87,12 @@ define <4 x i32> @bool_logic_and_math_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> ; CHECK-LABEL: bool_logic_and_math_vec: ; CHECK: # BB#0: ; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; CHECK-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2 -; CHECK-NEXT: vpxor %xmm1, %xmm2, %xmm1 +; CHECK-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm1 +; CHECK-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; CHECK-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 -; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq %cmp1 = icmp ne <4 x i32> %a, %b %cmp2 = icmp ne <4 x i32> %c, %d diff --git a/test/CodeGen/X86/bswap_tree.ll b/test/CodeGen/X86/bswap_tree.ll index 35a28af85579..c217879d4386 100644 --- a/test/CodeGen/X86/bswap_tree.ll +++ b/test/CodeGen/X86/bswap_tree.ll @@ -13,32 +13,16 @@ define i32 @test1(i32 %x) nounwind { ; CHECK-LABEL: test1: ; CHECK: # BB#0: -; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx -; CHECK-NEXT: movl %ecx, %edx -; CHECK-NEXT: andl $16711680, %edx # imm = 0xFF0000 -; CHECK-NEXT: movl %ecx, %eax -; CHECK-NEXT: andl $-16777216, %eax # imm = 0xFF000000 -; CHECK-NEXT: shll $8, %edx -; CHECK-NEXT: shrl $8, %eax -; CHECK-NEXT: bswapl %ecx -; CHECK-NEXT: shrl $16, %ecx -; CHECK-NEXT: orl %edx, %eax -; CHECK-NEXT: orl %ecx, %eax +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: bswapl %eax +; CHECK-NEXT: roll $16, %eax ; CHECK-NEXT: retl ; ; CHECK64-LABEL: test1: ; CHECK64: # BB#0: -; CHECK64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; CHECK64-NEXT: movl %edi, %eax -; CHECK64-NEXT: andl $16711680, %eax # imm = 0xFF0000 -; CHECK64-NEXT: movl %edi, %ecx -; CHECK64-NEXT: andl $-16777216, %ecx # imm = 0xFF000000 -; CHECK64-NEXT: shll $8, %eax -; CHECK64-NEXT: shrl $8, %ecx ; CHECK64-NEXT: bswapl %edi -; CHECK64-NEXT: shrl $16, %edi -; CHECK64-NEXT: orl %eax, %ecx -; CHECK64-NEXT: leal (%rcx,%rdi), %eax +; CHECK64-NEXT: roll $16, %edi +; CHECK64-NEXT: movl %edi, %eax ; CHECK64-NEXT: retq %byte0 = and i32 %x, 255 ; 0x000000ff %byte1 = and i32 %x, 65280 ; 0x0000ff00 @@ -62,33 +46,16 @@ define i32 @test1(i32 %x) nounwind { define i32 @test2(i32 %x) nounwind { ; CHECK-LABEL: test2: ; CHECK: # BB#0: -; CHECK-NEXT: pushl %esi ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: movl %eax, %ecx -; CHECK-NEXT: shll $8, %ecx -; CHECK-NEXT: shrl $8, %eax -; CHECK-NEXT: movzwl %cx, %edx -; CHECK-NEXT: movzbl %al, %esi -; CHECK-NEXT: andl $-16777216, %ecx # imm = 0xFF000000 -; CHECK-NEXT: andl $16711680, %eax # imm = 0xFF0000 -; CHECK-NEXT: orl %edx, %esi -; CHECK-NEXT: orl %ecx, %eax -; CHECK-NEXT: orl %esi, %eax -; CHECK-NEXT: popl %esi +; CHECK-NEXT: bswapl %eax +; CHECK-NEXT: roll $16, %eax ; CHECK-NEXT: retl ; ; CHECK64-LABEL: test2: ; CHECK64: # BB#0: -; CHECK64-NEXT: movl %edi, %ecx -; CHECK64-NEXT: shll $8, %ecx -; CHECK64-NEXT: shrl $8, %edi -; CHECK64-NEXT: movzwl %cx, %edx -; CHECK64-NEXT: movzbl %dil, %eax -; CHECK64-NEXT: andl $-16777216, %ecx # imm = 0xFF000000 -; CHECK64-NEXT: andl $16711680, %edi # imm = 0xFF0000 -; CHECK64-NEXT: orl %edx, %eax -; CHECK64-NEXT: orl %ecx, %edi -; CHECK64-NEXT: orl %edi, %eax +; CHECK64-NEXT: bswapl %edi +; CHECK64-NEXT: roll $16, %edi +; CHECK64-NEXT: movl %edi, %eax ; CHECK64-NEXT: retq %byte1 = shl i32 %x, 8 %byte0 = lshr i32 %x, 8 diff --git a/test/CodeGen/X86/cast-vsel.ll b/test/CodeGen/X86/cast-vsel.ll new file mode 100644 index 000000000000..1e44aec99fc5 --- /dev/null +++ b/test/CodeGen/X86/cast-vsel.ll @@ -0,0 +1,611 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 + +; If we have a cmp and a sel with different-sized operands followed by a size-changing cast, +; we may want to pull the cast ahead of the select operands to create a select with matching op sizes: +; ext (sel (cmp a, b), c, d) --> sel (cmp a, b), (ext c), (ext d) + +define <8 x i32> @sext(<8 x float> %a, <8 x float> %b, <8 x i16> %c, <8 x i16> %d) { +; SSE2-LABEL: sext: +; SSE2: # BB#0: +; SSE2-NEXT: cmpltps %xmm3, %xmm1 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: cmpltps %xmm2, %xmm0 +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] +; SSE2-NEXT: pand %xmm2, %xmm4 +; SSE2-NEXT: pandn %xmm5, %xmm2 +; SSE2-NEXT: por %xmm4, %xmm2 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] +; SSE2-NEXT: psrad $16, %xmm0 +; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] +; SSE2-NEXT: psrad $16, %xmm1 +; SSE2-NEXT: retq +; +; SSE41-LABEL: sext: +; SSE41: # BB#0: +; SSE41-NEXT: cmpltps %xmm3, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: pshufb %xmm3, %xmm1 +; SSE41-NEXT: cmpltps %xmm2, %xmm0 +; SSE41-NEXT: pshufb %xmm3, %xmm0 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE41-NEXT: pand %xmm0, %xmm4 +; SSE41-NEXT: pandn %xmm5, %xmm0 +; SSE41-NEXT: por %xmm4, %xmm0 +; SSE41-NEXT: pmovsxwd %xmm0, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE41-NEXT: pmovsxwd %xmm0, %xmm1 +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: sext: +; AVX1: # BB#0: +; AVX1-NEXT: vcmpltps %ymm1, %ymm0, %ymm0 +; AVX1-NEXT: vpmovsxwd %xmm2, %xmm1 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] +; AVX1-NEXT: vpmovsxwd %xmm2, %xmm2 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 +; AVX1-NEXT: vpmovsxwd %xmm3, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,3,0,1] +; AVX1-NEXT: vpmovsxwd %xmm3, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 +; AVX1-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: sext: +; AVX2: # BB#0: +; AVX2-NEXT: vcmpltps %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpmovsxwd %xmm2, %ymm1 +; AVX2-NEXT: vpmovsxwd %xmm3, %ymm2 +; AVX2-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0 +; AVX2-NEXT: retq + %cmp = fcmp olt <8 x float> %a, %b + %sel = select <8 x i1> %cmp, <8 x i16> %c, <8 x i16> %d + %ext = sext <8 x i16> %sel to <8 x i32> + ret <8 x i32> %ext +} + +define <8 x i32> @zext(<8 x float> %a, <8 x float> %b, <8 x i16> %c, <8 x i16> %d) { +; SSE2-LABEL: zext: +; SSE2: # BB#0: +; SSE2-NEXT: cmpltps %xmm3, %xmm1 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,2,2,3] +; SSE2-NEXT: cmpltps %xmm2, %xmm0 +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] +; SSE2-NEXT: pand %xmm1, %xmm4 +; SSE2-NEXT: pandn %xmm5, %xmm1 +; SSE2-NEXT: por %xmm4, %xmm1 +; SSE2-NEXT: xorps %xmm2, %xmm2 +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] +; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] +; SSE2-NEXT: retq +; +; SSE41-LABEL: zext: +; SSE41: # BB#0: +; SSE41-NEXT: cmpltps %xmm3, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: pshufb %xmm3, %xmm1 +; SSE41-NEXT: cmpltps %xmm2, %xmm0 +; SSE41-NEXT: pshufb %xmm3, %xmm0 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE41-NEXT: pand %xmm0, %xmm4 +; SSE41-NEXT: pandn %xmm5, %xmm0 +; SSE41-NEXT: por %xmm4, %xmm0 +; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero +; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: zext: +; AVX1: # BB#0: +; AVX1-NEXT: vcmpltps %ymm1, %ymm0, %ymm0 +; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] +; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 +; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero +; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,3,0,1] +; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 +; AVX1-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: zext: +; AVX2: # BB#0: +; AVX2-NEXT: vcmpltps %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero +; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero,xmm3[4],zero,xmm3[5],zero,xmm3[6],zero,xmm3[7],zero +; AVX2-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0 +; AVX2-NEXT: retq + %cmp = fcmp olt <8 x float> %a, %b + %sel = select <8 x i1> %cmp, <8 x i16> %c, <8 x i16> %d + %ext = zext <8 x i16> %sel to <8 x i32> + ret <8 x i32> %ext +} + +define <4 x double> @fpext(<4 x double> %a, <4 x double> %b, <4 x float> %c, <4 x float> %d) { +; SSE2-LABEL: fpext: +; SSE2: # BB#0: +; SSE2-NEXT: cmpltpd %xmm3, %xmm1 +; SSE2-NEXT: cmpltpd %xmm2, %xmm0 +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] +; SSE2-NEXT: andps %xmm0, %xmm4 +; SSE2-NEXT: andnps %xmm5, %xmm0 +; SSE2-NEXT: orps %xmm4, %xmm0 +; SSE2-NEXT: cvtps2pd %xmm0, %xmm2 +; SSE2-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero +; SSE2-NEXT: cvtps2pd %xmm0, %xmm1 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: fpext: +; SSE41: # BB#0: +; SSE41-NEXT: cmpltpd %xmm3, %xmm1 +; SSE41-NEXT: cmpltpd %xmm2, %xmm0 +; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] +; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm5 +; SSE41-NEXT: cvtps2pd %xmm5, %xmm0 +; SSE41-NEXT: movhlps {{.*#+}} xmm5 = xmm5[1,1] +; SSE41-NEXT: cvtps2pd %xmm5, %xmm1 +; SSE41-NEXT: retq +; +; AVX-LABEL: fpext: +; AVX: # BB#0: +; AVX-NEXT: vcmpltpd %ymm1, %ymm0, %ymm0 +; AVX-NEXT: vcvtps2pd %xmm2, %ymm1 +; AVX-NEXT: vcvtps2pd %xmm3, %ymm2 +; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0 +; AVX-NEXT: retq + %cmp = fcmp olt <4 x double> %a, %b + %sel = select <4 x i1> %cmp, <4 x float> %c, <4 x float> %d + %ext = fpext <4 x float> %sel to <4 x double> + ret <4 x double> %ext +} + +define <8 x i16> @trunc(<8 x i16> %a, <8 x i16> %b, <8 x i32> %c, <8 x i32> %d) { +; SSE2-LABEL: trunc: +; SSE2: # BB#0: +; SSE2-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE2-NEXT: pslld $16, %xmm5 +; SSE2-NEXT: psrad $16, %xmm5 +; SSE2-NEXT: pslld $16, %xmm4 +; SSE2-NEXT: psrad $16, %xmm4 +; SSE2-NEXT: packssdw %xmm5, %xmm4 +; SSE2-NEXT: pslld $16, %xmm3 +; SSE2-NEXT: psrad $16, %xmm3 +; SSE2-NEXT: pslld $16, %xmm2 +; SSE2-NEXT: psrad $16, %xmm2 +; SSE2-NEXT: packssdw %xmm3, %xmm2 +; SSE2-NEXT: pand %xmm0, %xmm2 +; SSE2-NEXT: pandn %xmm4, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: trunc: +; SSE41: # BB#0: +; SSE41-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: pshufb %xmm1, %xmm5 +; SSE41-NEXT: pshufb %xmm1, %xmm4 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] +; SSE41-NEXT: pshufb %xmm1, %xmm3 +; SSE41-NEXT: pshufb %xmm1, %xmm2 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] +; SSE41-NEXT: pand %xmm0, %xmm2 +; SSE41-NEXT: pandn %xmm4, %xmm0 +; SSE41-NEXT: por %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; AVX1-LABEL: trunc: +; AVX1: # BB#0: +; AVX1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; AVX1-NEXT: vpshufb %xmm4, %xmm1, %xmm1 +; AVX1-NEXT: vpshufb %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0] +; AVX1-NEXT: vpandn %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3 +; AVX1-NEXT: vpshufb %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpshufb %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] +; AVX1-NEXT: vpand %xmm0, %xmm2, %xmm0 +; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: trunc: +; AVX2: # BB#0: +; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] +; AVX2-NEXT: vpshufb %ymm1, %ymm3, %ymm3 +; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3] +; AVX2-NEXT: vpandn %xmm3, %xmm0, %xmm3 +; AVX2-NEXT: vpshufb %ymm1, %ymm2, %ymm1 +; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] +; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vpor %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %cmp = icmp eq <8 x i16> %a, %b + %sel = select <8 x i1> %cmp, <8 x i32> %c, <8 x i32> %d + %tr = trunc <8 x i32> %sel to <8 x i16> + ret <8 x i16> %tr +} + +define <4 x float> @fptrunc(<4 x float> %a, <4 x float> %b, <4 x double> %c, <4 x double> %d) { +; SSE2-LABEL: fptrunc: +; SSE2: # BB#0: +; SSE2-NEXT: cmpltps %xmm1, %xmm0 +; SSE2-NEXT: cvtpd2ps %xmm5, %xmm1 +; SSE2-NEXT: cvtpd2ps %xmm4, %xmm4 +; SSE2-NEXT: unpcklpd {{.*#+}} xmm4 = xmm4[0],xmm1[0] +; SSE2-NEXT: cvtpd2ps %xmm3, %xmm1 +; SSE2-NEXT: cvtpd2ps %xmm2, %xmm2 +; SSE2-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm1[0] +; SSE2-NEXT: andpd %xmm0, %xmm2 +; SSE2-NEXT: andnpd %xmm4, %xmm0 +; SSE2-NEXT: orpd %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: fptrunc: +; SSE41: # BB#0: +; SSE41-NEXT: cmpltps %xmm1, %xmm0 +; SSE41-NEXT: cvtpd2ps %xmm3, %xmm1 +; SSE41-NEXT: cvtpd2ps %xmm2, %xmm2 +; SSE41-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm1[0] +; SSE41-NEXT: cvtpd2ps %xmm5, %xmm3 +; SSE41-NEXT: cvtpd2ps %xmm4, %xmm1 +; SSE41-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0] +; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1 +; SSE41-NEXT: movaps %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: fptrunc: +; AVX: # BB#0: +; AVX-NEXT: vcmpltps %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vcvtpd2ps %ymm2, %xmm1 +; AVX-NEXT: vcvtpd2ps %ymm3, %xmm2 +; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0 +; AVX-NEXT: vzeroupper +; AVX-NEXT: retq + %cmp = fcmp olt <4 x float> %a, %b + %sel = select <4 x i1> %cmp, <4 x double> %c, <4 x double> %d + %tr = fptrunc <4 x double> %sel to <4 x float> + ret <4 x float> %tr +} + +; PR14657 - avoid truncation/extension of comparison results +; These tests demonstrate the same issue as the simpler cases above, +; but also include multi-BB to show potentially larger transforms/codegen issues. + +@da = common global [1024 x float] zeroinitializer, align 32 +@db = common global [1024 x float] zeroinitializer, align 32 +@dc = common global [1024 x float] zeroinitializer, align 32 +@dd = common global [1024 x float] zeroinitializer, align 32 +@dj = common global [1024 x i32] zeroinitializer, align 32 + +define void @example25() nounwind { +; SSE2-LABEL: example25: +; SSE2: # BB#0: # %vector.ph +; SSE2-NEXT: movq $-4096, %rax # imm = 0xF000 +; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [1,1,1,1] +; SSE2-NEXT: .p2align 4, 0x90 +; SSE2-NEXT: .LBB5_1: # %vector.body +; SSE2-NEXT: # =>This Inner Loop Header: Depth=1 +; SSE2-NEXT: movaps da+4096(%rax), %xmm1 +; SSE2-NEXT: movaps da+4112(%rax), %xmm2 +; SSE2-NEXT: cmpltps db+4112(%rax), %xmm2 +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: cmpltps db+4096(%rax), %xmm1 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] +; SSE2-NEXT: psllw $15, %xmm1 +; SSE2-NEXT: psraw $15, %xmm1 +; SSE2-NEXT: movaps dc+4096(%rax), %xmm2 +; SSE2-NEXT: movaps dc+4112(%rax), %xmm3 +; SSE2-NEXT: cmpltps dd+4112(%rax), %xmm3 +; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] +; SSE2-NEXT: cmpltps dd+4096(%rax), %xmm2 +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] +; SSE2-NEXT: psllw $15, %xmm2 +; SSE2-NEXT: psraw $15, %xmm2 +; SSE2-NEXT: pand %xmm1, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; SSE2-NEXT: pand %xmm0, %xmm1 +; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] +; SSE2-NEXT: pand %xmm0, %xmm2 +; SSE2-NEXT: movdqa %xmm2, dj+4112(%rax) +; SSE2-NEXT: movdqa %xmm1, dj+4096(%rax) +; SSE2-NEXT: addq $32, %rax +; SSE2-NEXT: jne .LBB5_1 +; SSE2-NEXT: # BB#2: # %for.end +; SSE2-NEXT: retq +; +; SSE41-LABEL: example25: +; SSE41: # BB#0: # %vector.ph +; SSE41-NEXT: movq $-4096, %rax # imm = 0xF000 +; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,1,1,1] +; SSE41-NEXT: .p2align 4, 0x90 +; SSE41-NEXT: .LBB5_1: # %vector.body +; SSE41-NEXT: # =>This Inner Loop Header: Depth=1 +; SSE41-NEXT: movaps da+4096(%rax), %xmm2 +; SSE41-NEXT: movaps da+4112(%rax), %xmm3 +; SSE41-NEXT: cmpltps db+4112(%rax), %xmm3 +; SSE41-NEXT: pshufb %xmm0, %xmm3 +; SSE41-NEXT: cmpltps db+4096(%rax), %xmm2 +; SSE41-NEXT: pshufb %xmm0, %xmm2 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] +; SSE41-NEXT: psllw $15, %xmm2 +; SSE41-NEXT: psraw $15, %xmm2 +; SSE41-NEXT: movaps dc+4096(%rax), %xmm3 +; SSE41-NEXT: movaps dc+4112(%rax), %xmm4 +; SSE41-NEXT: cmpltps dd+4112(%rax), %xmm4 +; SSE41-NEXT: pshufb %xmm0, %xmm4 +; SSE41-NEXT: cmpltps dd+4096(%rax), %xmm3 +; SSE41-NEXT: pshufb %xmm0, %xmm3 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0] +; SSE41-NEXT: psllw $15, %xmm3 +; SSE41-NEXT: psraw $15, %xmm3 +; SSE41-NEXT: pand %xmm2, %xmm3 +; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero +; SSE41-NEXT: pand %xmm1, %xmm2 +; SSE41-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] +; SSE41-NEXT: pand %xmm1, %xmm3 +; SSE41-NEXT: movdqa %xmm3, dj+4112(%rax) +; SSE41-NEXT: movdqa %xmm2, dj+4096(%rax) +; SSE41-NEXT: addq $32, %rax +; SSE41-NEXT: jne .LBB5_1 +; SSE41-NEXT: # BB#2: # %for.end +; SSE41-NEXT: retq +; +; AVX1-LABEL: example25: +; AVX1: # BB#0: # %vector.ph +; AVX1-NEXT: movq $-4096, %rax # imm = 0xF000 +; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [1,1,1,1,1,1,1,1] +; AVX1-NEXT: .p2align 4, 0x90 +; AVX1-NEXT: .LBB5_1: # %vector.body +; AVX1-NEXT: # =>This Inner Loop Header: Depth=1 +; AVX1-NEXT: vmovups da+4096(%rax), %ymm1 +; AVX1-NEXT: vcmpltps db+4096(%rax), %ymm1, %ymm1 +; AVX1-NEXT: vmovups dc+4096(%rax), %ymm2 +; AVX1-NEXT: vcmpltps dd+4096(%rax), %ymm2, %ymm2 +; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1 +; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm1 +; AVX1-NEXT: vmovups %ymm1, dj+4096(%rax) +; AVX1-NEXT: addq $32, %rax +; AVX1-NEXT: jne .LBB5_1 +; AVX1-NEXT: # BB#2: # %for.end +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: example25: +; AVX2: # BB#0: # %vector.ph +; AVX2-NEXT: movq $-4096, %rax # imm = 0xF000 +; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm0 +; AVX2-NEXT: .p2align 4, 0x90 +; AVX2-NEXT: .LBB5_1: # %vector.body +; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 +; AVX2-NEXT: vmovups da+4096(%rax), %ymm1 +; AVX2-NEXT: vcmpltps db+4096(%rax), %ymm1, %ymm1 +; AVX2-NEXT: vmovups dc+4096(%rax), %ymm2 +; AVX2-NEXT: vcmpltps dd+4096(%rax), %ymm2, %ymm2 +; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1 +; AVX2-NEXT: vandps %ymm0, %ymm1, %ymm1 +; AVX2-NEXT: vmovups %ymm1, dj+4096(%rax) +; AVX2-NEXT: addq $32, %rax +; AVX2-NEXT: jne .LBB5_1 +; AVX2-NEXT: # BB#2: # %for.end +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +vector.ph: + br label %vector.body + +vector.body: + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds [1024 x float], [1024 x float]* @da, i64 0, i64 %index + %1 = bitcast float* %0 to <8 x float>* + %2 = load <8 x float>, <8 x float>* %1, align 16 + %3 = getelementptr inbounds [1024 x float], [1024 x float]* @db, i64 0, i64 %index + %4 = bitcast float* %3 to <8 x float>* + %5 = load <8 x float>, <8 x float>* %4, align 16 + %6 = fcmp olt <8 x float> %2, %5 + %7 = getelementptr inbounds [1024 x float], [1024 x float]* @dc, i64 0, i64 %index + %8 = bitcast float* %7 to <8 x float>* + %9 = load <8 x float>, <8 x float>* %8, align 16 + %10 = getelementptr inbounds [1024 x float], [1024 x float]* @dd, i64 0, i64 %index + %11 = bitcast float* %10 to <8 x float>* + %12 = load <8 x float>, <8 x float>* %11, align 16 + %13 = fcmp olt <8 x float> %9, %12 + %14 = and <8 x i1> %6, %13 + %15 = zext <8 x i1> %14 to <8 x i32> + %16 = getelementptr inbounds [1024 x i32], [1024 x i32]* @dj, i64 0, i64 %index + %17 = bitcast i32* %16 to <8 x i32>* + store <8 x i32> %15, <8 x i32>* %17, align 16 + %index.next = add i64 %index, 8 + %18 = icmp eq i64 %index.next, 1024 + br i1 %18, label %for.end, label %vector.body + +for.end: + ret void +} + +define void @example24(i16 signext %x, i16 signext %y) nounwind { +; SSE2-LABEL: example24: +; SSE2: # BB#0: # %vector.ph +; SSE2-NEXT: movd %edi, %xmm0 +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] +; SSE2-NEXT: movd %esi, %xmm1 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] +; SSE2-NEXT: movq $-4096, %rax # imm = 0xF000 +; SSE2-NEXT: .p2align 4, 0x90 +; SSE2-NEXT: .LBB6_1: # %vector.body +; SSE2-NEXT: # =>This Inner Loop Header: Depth=1 +; SSE2-NEXT: movaps da+4096(%rax), %xmm2 +; SSE2-NEXT: movaps da+4112(%rax), %xmm3 +; SSE2-NEXT: cmpltps db+4112(%rax), %xmm3 +; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] +; SSE2-NEXT: cmpltps db+4096(%rax), %xmm2 +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: pand %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm1, %xmm2 +; SSE2-NEXT: por %xmm3, %xmm2 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] +; SSE2-NEXT: psrad $16, %xmm3 +; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7] +; SSE2-NEXT: psrad $16, %xmm2 +; SSE2-NEXT: movdqa %xmm2, dj+4112(%rax) +; SSE2-NEXT: movdqa %xmm3, dj+4096(%rax) +; SSE2-NEXT: addq $32, %rax +; SSE2-NEXT: jne .LBB6_1 +; SSE2-NEXT: # BB#2: # %for.end +; SSE2-NEXT: retq +; +; SSE41-LABEL: example24: +; SSE41: # BB#0: # %vector.ph +; SSE41-NEXT: movd %edi, %xmm0 +; SSE41-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] +; SSE41-NEXT: movd %esi, %xmm1 +; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] +; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] +; SSE41-NEXT: movq $-4096, %rax # imm = 0xF000 +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: .p2align 4, 0x90 +; SSE41-NEXT: .LBB6_1: # %vector.body +; SSE41-NEXT: # =>This Inner Loop Header: Depth=1 +; SSE41-NEXT: movaps da+4096(%rax), %xmm3 +; SSE41-NEXT: movaps da+4112(%rax), %xmm4 +; SSE41-NEXT: cmpltps db+4112(%rax), %xmm4 +; SSE41-NEXT: pshufb %xmm2, %xmm4 +; SSE41-NEXT: cmpltps db+4096(%rax), %xmm3 +; SSE41-NEXT: pshufb %xmm2, %xmm3 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0] +; SSE41-NEXT: movdqa %xmm0, %xmm4 +; SSE41-NEXT: pand %xmm3, %xmm4 +; SSE41-NEXT: pandn %xmm1, %xmm3 +; SSE41-NEXT: por %xmm4, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[2,3,0,1] +; SSE41-NEXT: pmovsxwd %xmm4, %xmm4 +; SSE41-NEXT: pmovsxwd %xmm3, %xmm3 +; SSE41-NEXT: movdqa %xmm3, dj+4096(%rax) +; SSE41-NEXT: movdqa %xmm4, dj+4112(%rax) +; SSE41-NEXT: addq $32, %rax +; SSE41-NEXT: jne .LBB6_1 +; SSE41-NEXT: # BB#2: # %for.end +; SSE41-NEXT: retq +; +; AVX1-LABEL: example24: +; AVX1: # BB#0: # %vector.ph +; AVX1-NEXT: vmovd %edi, %xmm0 +; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] +; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] +; AVX1-NEXT: vmovd %esi, %xmm1 +; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] +; AVX1-NEXT: movq $-4096, %rax # imm = 0xF000 +; AVX1-NEXT: vpmovsxwd %xmm0, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 +; AVX1-NEXT: vpmovsxwd %xmm1, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; AVX1-NEXT: vpmovsxwd %xmm1, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 +; AVX1-NEXT: .p2align 4, 0x90 +; AVX1-NEXT: .LBB6_1: # %vector.body +; AVX1-NEXT: # =>This Inner Loop Header: Depth=1 +; AVX1-NEXT: vmovups da+4096(%rax), %ymm2 +; AVX1-NEXT: vcmpltps db+4096(%rax), %ymm2, %ymm2 +; AVX1-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm2 +; AVX1-NEXT: vmovups %ymm2, dj+4096(%rax) +; AVX1-NEXT: addq $32, %rax +; AVX1-NEXT: jne .LBB6_1 +; AVX1-NEXT: # BB#2: # %for.end +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: example24: +; AVX2: # BB#0: # %vector.ph +; AVX2-NEXT: vmovd %edi, %xmm0 +; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0 +; AVX2-NEXT: vmovd %esi, %xmm1 +; AVX2-NEXT: vpbroadcastw %xmm1, %xmm1 +; AVX2-NEXT: movq $-4096, %rax # imm = 0xF000 +; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 +; AVX2-NEXT: vpmovsxwd %xmm1, %ymm1 +; AVX2-NEXT: .p2align 4, 0x90 +; AVX2-NEXT: .LBB6_1: # %vector.body +; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 +; AVX2-NEXT: vmovups da+4096(%rax), %ymm2 +; AVX2-NEXT: vcmpltps db+4096(%rax), %ymm2, %ymm2 +; AVX2-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm2 +; AVX2-NEXT: vmovups %ymm2, dj+4096(%rax) +; AVX2-NEXT: addq $32, %rax +; AVX2-NEXT: jne .LBB6_1 +; AVX2-NEXT: # BB#2: # %for.end +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +vector.ph: + %0 = insertelement <8 x i16> undef, i16 %x, i32 0 + %broadcast11 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer + %1 = insertelement <8 x i16> undef, i16 %y, i32 0 + %broadcast12 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> zeroinitializer + br label %vector.body + +vector.body: + %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %2 = getelementptr inbounds [1024 x float], [1024 x float]* @da, i64 0, i64 %index + %3 = bitcast float* %2 to <8 x float>* + %4 = load <8 x float>, <8 x float>* %3, align 16 + %5 = getelementptr inbounds [1024 x float], [1024 x float]* @db, i64 0, i64 %index + %6 = bitcast float* %5 to <8 x float>* + %7 = load <8 x float>, <8 x float>* %6, align 16 + %8 = fcmp olt <8 x float> %4, %7 + %9 = select <8 x i1> %8, <8 x i16> %broadcast11, <8 x i16> %broadcast12 + %10 = sext <8 x i16> %9 to <8 x i32> + %11 = getelementptr inbounds [1024 x i32], [1024 x i32]* @dj, i64 0, i64 %index + %12 = bitcast i32* %11 to <8 x i32>* + store <8 x i32> %10, <8 x i32>* %12, align 16 + %index.next = add i64 %index, 8 + %13 = icmp eq i64 %index.next, 1024 + br i1 %13, label %for.end, label %vector.body + +for.end: + ret void +} + diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll index cffc67327288..9d827fc88b34 100644 --- a/test/CodeGen/X86/clz.ll +++ b/test/CodeGen/X86/clz.ll @@ -778,3 +778,88 @@ define i32 @ctlz_bsr_zero_test(i32 %n) { %bsr = xor i32 %ctlz, 31 ret i32 %bsr } + +define i8 @cttz_i8_knownbits(i8 %x) { +; X32-LABEL: cttz_i8_knownbits: +; X32: # BB#0: +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: orb $2, %al +; X32-NEXT: movzbl %al, %eax +; X32-NEXT: bsfl %eax, %eax +; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: retl +; +; X64-LABEL: cttz_i8_knownbits: +; X64: # BB#0: +; X64-NEXT: orb $2, %dil +; X64-NEXT: movzbl %dil, %eax +; X64-NEXT: bsfl %eax, %eax +; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: retq +; +; X32-CLZ-LABEL: cttz_i8_knownbits: +; X32-CLZ: # BB#0: +; X32-CLZ-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-CLZ-NEXT: orb $2, %al +; X32-CLZ-NEXT: movzbl %al, %eax +; X32-CLZ-NEXT: tzcntl %eax, %eax +; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-CLZ-NEXT: retl +; +; X64-CLZ-LABEL: cttz_i8_knownbits: +; X64-CLZ: # BB#0: +; X64-CLZ-NEXT: orb $2, %dil +; X64-CLZ-NEXT: movzbl %dil, %eax +; X64-CLZ-NEXT: tzcntl %eax, %eax +; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-CLZ-NEXT: retq + %x2 = or i8 %x, 2 + %tmp = call i8 @llvm.cttz.i8(i8 %x2, i1 true ) + %tmp2 = and i8 %tmp, 1 + ret i8 %tmp2 +} + +define i8 @ctlz_i8_knownbits(i8 %x) { +; X32-LABEL: ctlz_i8_knownbits: +; X32: # BB#0: +; X32-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-NEXT: orb $64, %al +; X32-NEXT: movzbl %al, %eax +; X32-NEXT: bsrl %eax, %eax +; X32-NEXT: xorl $7, %eax +; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: retl +; +; X64-LABEL: ctlz_i8_knownbits: +; X64: # BB#0: +; X64-NEXT: orb $64, %dil +; X64-NEXT: movzbl %dil, %eax +; X64-NEXT: bsrl %eax, %eax +; X64-NEXT: xorl $7, %eax +; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: retq +; +; X32-CLZ-LABEL: ctlz_i8_knownbits: +; X32-CLZ: # BB#0: +; X32-CLZ-NEXT: movb {{[0-9]+}}(%esp), %al +; X32-CLZ-NEXT: orb $64, %al +; X32-CLZ-NEXT: movzbl %al, %eax +; X32-CLZ-NEXT: lzcntl %eax, %eax +; X32-CLZ-NEXT: addl $-24, %eax +; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-CLZ-NEXT: retl +; +; X64-CLZ-LABEL: ctlz_i8_knownbits: +; X64-CLZ: # BB#0: +; X64-CLZ-NEXT: orb $64, %dil +; X64-CLZ-NEXT: movzbl %dil, %eax +; X64-CLZ-NEXT: lzcntl %eax, %eax +; X64-CLZ-NEXT: addl $-24, %eax +; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-CLZ-NEXT: retq + + %x2 = or i8 %x, 64 + %tmp = call i8 @llvm.ctlz.i8(i8 %x2, i1 true ) + %tmp2 = and i8 %tmp, 1 + ret i8 %tmp2 +} diff --git a/test/CodeGen/X86/deopt-bundles.ll b/test/CodeGen/X86/deopt-bundles.ll index 1fb73ea252ee..9745330c9acd 100644 --- a/test/CodeGen/X86/deopt-bundles.ll +++ b/test/CodeGen/X86/deopt-bundles.ll @@ -9,48 +9,47 @@ target triple = "x86_64-apple-macosx10.11.0" ; STACKMAPS: Stack Maps: callsite 2882400015 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers ; STACKMAPS-NEXT: Stack Maps: callsite 4242 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers ; STACKMAPS-NEXT: Stack Maps: callsite 4243 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 16 [encoding: .byte 4, .byte 8, .short 0, .int 16] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 16 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 16] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 2 [encoding: .byte 4, .byte 8, .short 0, .int 2] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 2 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 2] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 3 [encoding: .byte 4, .byte 8, .short 0, .int 3] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 3 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 3] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers ; STACKMAPS-NEXT: Stack Maps: callsite 4243 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 55 [encoding: .byte 4, .byte 8, .short 0, .int 55] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 55 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 55] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers - declare i32 @callee_0() declare i32 @callee_1(i32) declare i32 @callee_vararg(...) @@ -159,3 +158,42 @@ define void @f_0(i64 %n) { } declare void @g_0(i64* %vl) + +define void @vector_deopt_bundle(<32 x i64 addrspace(1)*> %val) { +; CHECK-LABEL: _vector_deopt_bundle: +; CHECK: movaps 16(%rbp), %xmm8 +; CHECK-NEXT: movaps 32(%rbp), %xmm9 +; CHECK-NEXT: movaps 48(%rbp), %xmm10 +; CHECK-NEXT: movaps 64(%rbp), %xmm11 +; CHECK-NEXT: movaps 80(%rbp), %xmm12 +; CHECK-NEXT: movaps 96(%rbp), %xmm13 +; CHECK-NEXT: movaps 112(%rbp), %xmm14 +; CHECK-NEXT: movaps 128(%rbp), %xmm15 +; CHECK-NEXT: movaps %xmm15, 240(%rsp) +; CHECK-NEXT: movaps %xmm14, 224(%rsp) +; CHECK-NEXT: movaps %xmm13, 208(%rsp) +; CHECK-NEXT: movaps %xmm12, 192(%rsp) +; CHECK-NEXT: movaps %xmm11, 176(%rsp) +; CHECK-NEXT: movaps %xmm10, 160(%rsp) +; CHECK-NEXT: movaps %xmm9, 144(%rsp) +; CHECK-NEXT: movaps %xmm8, 128(%rsp) +; CHECK-NEXT: movaps %xmm7, 112(%rsp) +; CHECK-NEXT: movaps %xmm6, 96(%rsp) +; CHECK-NEXT: movaps %xmm5, 80(%rsp) +; CHECK-NEXT: movaps %xmm4, 64(%rsp) +; CHECK-NEXT: movaps %xmm3, 48(%rsp) +; CHECK-NEXT: movaps %xmm2, 32(%rsp) +; CHECK-NEXT: movaps %xmm1, 16(%rsp) +; CHECK-NEXT: movaps %xmm0, (%rsp) + call void @unknown() [ "deopt"(<32 x i64 addrspace(1)*> %val) ] + ret void +; STACKMAPS: Stack Maps: callsite 2882400015 +; STACKMAPS-NEXT: Stack Maps: has 4 locations +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 256, .short 7, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers +} + +declare void @unknown() diff --git a/test/CodeGen/X86/deopt-intrinsic-cconv.ll b/test/CodeGen/X86/deopt-intrinsic-cconv.ll index c382d66cee64..97bca1f69dbf 100644 --- a/test/CodeGen/X86/deopt-intrinsic-cconv.ll +++ b/test/CodeGen/X86/deopt-intrinsic-cconv.ll @@ -27,8 +27,8 @@ entry: ; STACKMAPS: Stack Maps: callsites: ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 12 [encoding: .byte 4, .byte 8, .short 0, .int 12] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 3 [encoding: .byte 4, .byte 8, .short 0, .int 3] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 12 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 12] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 3 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 3] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers diff --git a/test/CodeGen/X86/deopt-intrinsic.ll b/test/CodeGen/X86/deopt-intrinsic.ll index 1254e1160290..0e894516ffa3 100644 --- a/test/CodeGen/X86/deopt-intrinsic.ll +++ b/test/CodeGen/X86/deopt-intrinsic.ll @@ -42,15 +42,15 @@ entry: ; STACKMAPS: Stack Maps: callsites: ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers ; STACKMAPS-NEXT: Stack Maps: callsite 2882400015 ; STACKMAPS-NEXT: Stack Maps: has 4 locations -; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 8, .short 0, .int 0] -; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] -; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 1 [encoding: .byte 4, .byte 8, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 0: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 1: Constant 0 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 0] +; STACKMAPS-NEXT: Stack Maps: Loc 2: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] +; STACKMAPS-NEXT: Stack Maps: Loc 3: Constant 1 [encoding: .byte 4, .byte 0, .short 8, .short 0, .short 0, .int 1] ; STACKMAPS-NEXT: Stack Maps: has 0 live-out registers diff --git a/test/CodeGen/X86/inline-0bh.ll b/test/CodeGen/X86/inline-0bh.ll new file mode 100644 index 000000000000..ceef395aa147 --- /dev/null +++ b/test/CodeGen/X86/inline-0bh.ll @@ -0,0 +1,17 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s + +; Function Attrs: noinline nounwind +define i32 @PR31007() { +; CHECK-LABEL: PR31007: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: #APP +; CHECK : addb $11, %al +; CHECK: #NO_APP +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq +entry: + call void asm sideeffect inteldialect "add al,$$0bH", "~{al},~{flags},~{dirflag},~{fpsr},~{flags}"() + ret i32 0 +} + diff --git a/test/CodeGen/X86/known-bits.ll b/test/CodeGen/X86/known-bits.ll index 81a60cdee3ac..90f6e9301389 100644 --- a/test/CodeGen/X86/known-bits.ll +++ b/test/CodeGen/X86/known-bits.ll @@ -173,8 +173,8 @@ define {i32, i1} @knownbits_uaddo_saddo(i64 %a0, i64 %a1) nounwind { ; X32-NEXT: pushl %ebx ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: leal (%ecx,%eax), %edx -; X32-NEXT: cmpl %ecx, %edx +; X32-NEXT: movl %ecx, %edx +; X32-NEXT: addl %eax, %edx ; X32-NEXT: setb %bl ; X32-NEXT: testl %eax, %eax ; X32-NEXT: setns %al @@ -226,19 +226,19 @@ define {i32, i1} @knownbits_usubo_ssubo(i64 %a0, i64 %a1) nounwind { ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl %ecx, %edx ; X32-NEXT: subl %eax, %edx -; X32-NEXT: setns %bl -; X32-NEXT: cmpl %edx, %ecx -; X32-NEXT: setb %dh -; X32-NEXT: testl %ecx, %ecx -; X32-NEXT: setns %cl -; X32-NEXT: cmpb %bl, %cl -; X32-NEXT: setne %ch +; X32-NEXT: setb %bl ; X32-NEXT: testl %eax, %eax ; X32-NEXT: setns %al +; X32-NEXT: testl %ecx, %ecx +; X32-NEXT: setns %cl ; X32-NEXT: cmpb %al, %cl +; X32-NEXT: setne %al +; X32-NEXT: testl %edx, %edx +; X32-NEXT: setns %dl +; X32-NEXT: cmpb %dl, %cl ; X32-NEXT: setne %dl -; X32-NEXT: andb %ch, %dl -; X32-NEXT: orb %dh, %dl +; X32-NEXT: andb %al, %dl +; X32-NEXT: orb %bl, %dl ; X32-NEXT: xorl %eax, %eax ; X32-NEXT: popl %ebx ; X32-NEXT: retl diff --git a/test/CodeGen/X86/known-signbits-vector.ll b/test/CodeGen/X86/known-signbits-vector.ll index 4c3c8bbd793e..cea9ac26edbc 100644 --- a/test/CodeGen/X86/known-signbits-vector.ll +++ b/test/CodeGen/X86/known-signbits-vector.ll @@ -100,27 +100,21 @@ define float @signbits_ashr_extract_sitofp(<2 x i64> %a0) nounwind { define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwind { ; X32-LABEL: signbits_ashr_insert_ashr_extract_sitofp: ; X32: # BB#0: -; X32-NEXT: pushl %ebp -; X32-NEXT: movl %esp, %ebp -; X32-NEXT: andl $-8, %esp -; X32-NEXT: subl $16, %esp -; X32-NEXT: movl 8(%ebp), %eax -; X32-NEXT: movl 12(%ebp), %ecx +; X32-NEXT: pushl %eax +; X32-NEXT: movl {{[0-9]+}}(%esp), %eax +; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: shrdl $30, %ecx, %eax ; X32-NEXT: sarl $30, %ecx ; X32-NEXT: vmovd %eax, %xmm0 ; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0 -; X32-NEXT: vpinsrd $2, 16(%ebp), %xmm0, %xmm0 -; X32-NEXT: vpinsrd $3, 20(%ebp), %xmm0, %xmm0 -; X32-NEXT: vpsrad $3, %xmm0, %xmm1 +; X32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0 +; X32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0 ; X32-NEXT: vpsrlq $3, %xmm0, %xmm0 -; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] -; X32-NEXT: vmovq %xmm0, {{[0-9]+}}(%esp) -; X32-NEXT: fildll {{[0-9]+}}(%esp) -; X32-NEXT: fstps {{[0-9]+}}(%esp) -; X32-NEXT: flds {{[0-9]+}}(%esp) -; X32-NEXT: movl %ebp, %esp -; X32-NEXT: popl %ebp +; X32-NEXT: vmovd %xmm0, %eax +; X32-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0 +; X32-NEXT: vmovss %xmm0, (%esp) +; X32-NEXT: flds (%esp) +; X32-NEXT: popl %eax ; X32-NEXT: retl ; ; X64-LABEL: signbits_ashr_insert_ashr_extract_sitofp: @@ -133,7 +127,7 @@ define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwin ; X64-NEXT: vpsrlq $3, %xmm0, %xmm0 ; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; X64-NEXT: vmovq %xmm0, %rax -; X64-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 +; X64-NEXT: vcvtsi2ssl %eax, %xmm2, %xmm0 ; X64-NEXT: retq %1 = ashr i64 %a0, 30 %2 = insertelement <2 x i64> undef, i64 %1, i32 0 diff --git a/test/CodeGen/X86/lea-opt-with-debug.mir b/test/CodeGen/X86/lea-opt-with-debug.mir index ebf86ff718db..0a477706df15 100644 --- a/test/CodeGen/X86/lea-opt-with-debug.mir +++ b/test/CodeGen/X86/lea-opt-with-debug.mir @@ -1,7 +1,8 @@ -# RUN: llc -mtriple=x86_64-unknown-unknown -start-after peephole-opt -stop-before detect-dead-lanes -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64-unknown-unknown -start-after=peephole-opt -stop-before=detect-dead-lanes -o - %s | FileCheck %s -# Test that pass optimize LEA can remove a redundant LEA even when it is also -# used by a DBG_VALUE. +# Test that the optimize LEA pass can remove a redundant LEA even when it is +# also used by a DBG_VALUE. Check that the uses of the replaced LEA are updated +# correctly. --- | target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" @@ -13,22 +14,22 @@ @d = common local_unnamed_addr global i32 0, align 4 @b = common local_unnamed_addr global i32 0, align 4 - define i32 @fn1() local_unnamed_addr !dbg !8 { - %1 = load %struct.A*, %struct.A** @c, align 8, !dbg !13 - %2 = load i32, i32* @a, align 4, !dbg !13 - %3 = sext i32 %2 to i64, !dbg !13 - %4 = getelementptr inbounds %struct.A, %struct.A* %1, i64 %3, !dbg !13 - %5 = ptrtoint %struct.A* %4 to i64, !dbg !13 - %6 = trunc i64 %5 to i32, !dbg !13 - store i32 %6, i32* @d, align 4, !dbg !13 - %7 = getelementptr inbounds %struct.A, %struct.A* %1, i64 %3, i32 2, !dbg !14 - tail call void @llvm.dbg.value(metadata i32* %7, i64 0, metadata !11, metadata !15), !dbg !16 - br label %8, !dbg !17 + define i32 @fn1() local_unnamed_addr !dbg !9 { + %1 = load %struct.A*, %struct.A** @c, align 8, !dbg !14 + %2 = load i32, i32* @a, align 4, !dbg !14 + %3 = sext i32 %2 to i64, !dbg !14 + %4 = getelementptr inbounds %struct.A, %struct.A* %1, i64 %3, !dbg !14 + %5 = ptrtoint %struct.A* %4 to i64, !dbg !14 + %6 = trunc i64 %5 to i32, !dbg !14 + store i32 %6, i32* @d, align 4, !dbg !14 + %7 = getelementptr inbounds %struct.A, %struct.A* %1, i64 %3, i32 2, !dbg !15 + tail call void @llvm.dbg.value(metadata i32* %7, i64 0, metadata !12, metadata !16), !dbg !17 + br label %8, !dbg !18 ; <label>:8: ; preds = %8, %0 - %9 = load i32, i32* %7, align 4, !dbg !18 - store i32 %9, i32* @d, align 4, !dbg !18 - br label %8, !dbg !19 + %9 = load i32, i32* %7, align 4, !dbg !19 + store i32 %9, i32* @d, align 4, !dbg !19 + br label %8, !dbg !20 } ; Function Attrs: nounwind readnone @@ -38,6 +39,7 @@ !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!5, !6, !7} + !misc = !{!8} !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, globals: !2) !1 = !DIFile(filename: "test.c", directory: "") @@ -47,18 +49,19 @@ !5 = !{i32 2, !"Dwarf Version", i32 4} !6 = !{i32 2, !"Debug Info Version", i32 3} !7 = !{i32 1, !"PIC Level", i32 2} - !8 = distinct !DISubprogram(name: "fn1", scope: !1, file: !1, line: 7, type: !9, isLocal: false, isDefinition: true, scopeLine: 7, isOptimized: true, unit: !0, variables: !10) - !9 = !DISubroutineType(types: !3) - !10 = !{!11} - !11 = !DILocalVariable(name: "e", scope: !8, file: !1, line: 8, type: !12) - !12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64) - !13 = !DILocation(line: 9, scope: !8) - !14 = !DILocation(line: 10, scope: !8) - !15 = !DIExpression() - !16 = !DILocation(line: 8, scope: !8) - !17 = !DILocation(line: 11, scope: !8) - !18 = !DILocation(line: 13, scope: !8) - !19 = !DILocation(line: 14, scope: !8) + !8 = !DIExpression(DW_OP_plus, 8, DW_OP_stack_value) + !9 = distinct !DISubprogram(name: "fn1", scope: !1, file: !1, line: 7, type: !10, isLocal: false, isDefinition: true, scopeLine: 7, isOptimized: true, unit: !0, variables: !11) + !10 = !DISubroutineType(types: !3) + !11 = !{!12} + !12 = !DILocalVariable(name: "e", scope: !9, file: !1, line: 8, type: !13) + !13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !4, size: 64) + !14 = !DILocation(line: 9, scope: !9) + !15 = !DILocation(line: 10, scope: !9) + !16 = !DIExpression() + !17 = !DILocation(line: 8, scope: !9) + !18 = !DILocation(line: 11, scope: !9) + !19 = !DILocation(line: 13, scope: !9) + !20 = !DILocation(line: 14, scope: !9) ... --- @@ -95,28 +98,28 @@ body: | bb.0 (%ir-block.0): successors: %bb.1(0x80000000) - ; CHECK: %3 = LEA64r %2, 2, %2, 0, _, debug-location !13 - ; CHECK-NEXT: %4 = LEA64r %1, 4, %3, 0, _, debug-location !13 - ; CHECK-NOT: %0 = LEA64r %1, 4, %3, 8, _, debug-location !14 - ; CHECK: DBG_VALUE debug-use _, debug-use _, !11, !15, debug-location !16 + ; CHECK: %3 = LEA64r %2, 2, %2, 0, _, debug-location !14 + ; CHECK-NEXT: %4 = LEA64r %1, 4, %3, 0, _, debug-location !14 + ; CHECK-NOT: %0 = LEA64r %1, 4, %3, 8, _, debug-location !15 + ; CHECK: DBG_VALUE debug-use %4, debug-use _, !12, !8, debug-location !17 - %1 = MOV64rm %rip, 1, _, @c, _, debug-location !13 :: (dereferenceable load 8 from @c) - %2 = MOVSX64rm32 %rip, 1, _, @a, _, debug-location !13 :: (dereferenceable load 4 from @a) - %3 = LEA64r %2, 2, %2, 0, _, debug-location !13 - %4 = LEA64r %1, 4, %3, 0, _, debug-location !13 - %5 = COPY %4.sub_32bit, debug-location !13 - MOV32mr %rip, 1, _, @d, _, killed %5, debug-location !13 :: (store 4 into @d) - %0 = LEA64r %1, 4, %3, 8, _, debug-location !14 - DBG_VALUE debug-use %0, debug-use _, !11, !15, debug-location !16 + %1 = MOV64rm %rip, 1, _, @c, _, debug-location !14 :: (dereferenceable load 8 from @c) + %2 = MOVSX64rm32 %rip, 1, _, @a, _, debug-location !14 :: (dereferenceable load 4 from @a) + %3 = LEA64r %2, 2, %2, 0, _, debug-location !14 + %4 = LEA64r %1, 4, %3, 0, _, debug-location !14 + %5 = COPY %4.sub_32bit, debug-location !14 + MOV32mr %rip, 1, _, @d, _, killed %5, debug-location !14 :: (store 4 into @d) + %0 = LEA64r %1, 4, %3, 8, _, debug-location !15 + DBG_VALUE debug-use %0, debug-use _, !12, !16, debug-location !17 ; CHECK-LABEL: bb.1 (%ir-block.8): - ; CHECK: %6 = MOV32rm %4, 1, _, 8, _, debug-location !18 :: (load 4 from %ir.7) + ; CHECK: %6 = MOV32rm %4, 1, _, 8, _, debug-location !19 :: (load 4 from %ir.7) bb.1 (%ir-block.8): successors: %bb.1(0x80000000) - %6 = MOV32rm %0, 1, _, 0, _, debug-location !18 :: (load 4 from %ir.7) - MOV32mr %rip, 1, _, @d, _, killed %6, debug-location !18 :: (store 4 into @d) - JMP_1 %bb.1, debug-location !19 + %6 = MOV32rm %0, 1, _, 0, _, debug-location !19 :: (load 4 from %ir.7) + MOV32mr %rip, 1, _, @d, _, killed %6, debug-location !19 :: (store 4 into @d) + JMP_1 %bb.1, debug-location !20 ... diff --git a/test/CodeGen/X86/mul-i1024.ll b/test/CodeGen/X86/mul-i1024.ll index 93d55a001287..340aa047c022 100644 --- a/test/CodeGen/X86/mul-i1024.ll +++ b/test/CodeGen/X86/mul-i1024.ll @@ -4388,732 +4388,720 @@ define void @test_1024(i1024* %a, i1024* %b, i1024* %out) nounwind { ; X64-NEXT: pushq %r13 ; X64-NEXT: pushq %r12 ; X64-NEXT: pushq %rbx -; X64-NEXT: subq $360, %rsp # imm = 0x168 +; X64-NEXT: subq $352, %rsp # imm = 0x160 ; X64-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq 48(%rdi), %r9 -; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq 48(%rdi), %r8 +; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq 40(%rdi), %rcx ; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq 32(%rdi), %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rdi, %r10 -; X64-NEXT: xorl %r8d, %r8d -; X64-NEXT: mulq %r8 -; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: movq %rdi, %r13 +; X64-NEXT: xorl %r9d, %r9d +; X64-NEXT: mulq %r9 +; X64-NEXT: movq %rdx, %rbx ; X64-NEXT: movq %rax, %r11 ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: mulq %r8 +; X64-NEXT: mulq %r9 ; X64-NEXT: movq %rax, %rcx -; X64-NEXT: addq %rdi, %rcx -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: adcq $0, %rbx +; X64-NEXT: addq %rbx, %rcx +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: adcq $0, %rbp ; X64-NEXT: addq %r11, %rcx ; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rdi, %rbp -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %rbx, %rbp +; X64-NEXT: adcq %rbx, %rbp +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: sbbq %rbx, %rbx ; X64-NEXT: andl $1, %ebx ; X64-NEXT: addq %rax, %rbp ; X64-NEXT: adcq %rdx, %rbx -; X64-NEXT: movq %r9, %rax -; X64-NEXT: mulq %r8 +; X64-NEXT: movq %r8, %rax +; X64-NEXT: mulq %r9 ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r11, %r13 -; X64-NEXT: addq %rax, %r13 -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: movq %rdi, %r15 -; X64-NEXT: movq %r15, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %r11, %r12 +; X64-NEXT: addq %rax, %r12 +; X64-NEXT: movq %rcx, %rax +; X64-NEXT: movq %rcx, %r8 +; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq %rdx, %rax -; X64-NEXT: addq %rbp, %r13 -; X64-NEXT: movq %r13, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: addq %rbp, %r12 +; X64-NEXT: movq %r12, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq %rbx, %rax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rsi, %r8 -; X64-NEXT: movq (%r8), %rax +; X64-NEXT: movq (%rsi), %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: xorl %ebp, %ebp ; X64-NEXT: mulq %rbp -; X64-NEXT: movq %rax, %r14 +; X64-NEXT: movq %rax, %r10 ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq 8(%r8), %rax +; X64-NEXT: movq 8(%rsi), %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: mulq %rbp ; X64-NEXT: xorl %r9d, %r9d -; X64-NEXT: movq %rax, %r12 -; X64-NEXT: addq %rcx, %r12 +; X64-NEXT: movq %rax, %r15 +; X64-NEXT: addq %rcx, %r15 ; X64-NEXT: movq %rdx, %rbp ; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %r14, %r12 -; X64-NEXT: movq %rcx, %rbx -; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rbx -; X64-NEXT: addq %rbp, %rbx -; X64-NEXT: sbbq %rbp, %rbp -; X64-NEXT: andl $1, %ebp -; X64-NEXT: addq %rax, %rbx -; X64-NEXT: adcq %rdx, %rbp -; X64-NEXT: movq 16(%r8), %rax -; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: addq %r10, %r15 +; X64-NEXT: adcq %rcx, %rbp +; X64-NEXT: movq %rcx, %rdi +; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: sbbq %rbx, %rbx +; X64-NEXT: andl $1, %ebx +; X64-NEXT: addq %rax, %rbp +; X64-NEXT: adcq %rdx, %rbx +; X64-NEXT: movq 16(%rsi), %rax +; X64-NEXT: movq %rsi, %r14 +; X64-NEXT: movq %r14, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: mulq %r9 ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r14, %r9 -; X64-NEXT: addq %rax, %r9 -; X64-NEXT: movq %rcx, %rax -; X64-NEXT: adcq %rdx, %rax -; X64-NEXT: addq %rbx, %r9 -; X64-NEXT: adcq %rbp, %rax -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: movq %r11, %rax +; X64-NEXT: movq %r10, %rcx +; X64-NEXT: movq %rcx, %rsi +; X64-NEXT: addq %rax, %rsi +; X64-NEXT: movq %rdi, %r9 +; X64-NEXT: adcq %rdx, %r9 +; X64-NEXT: addq %rbp, %rsi +; X64-NEXT: movq %rsi, %r10 +; X64-NEXT: adcq %rbx, %r9 ; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: addq %r14, %rax -; X64-NEXT: adcq %rcx, %r15 -; X64-NEXT: movq %r15, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq (%r10), %rax +; X64-NEXT: movq %r11, %rax +; X64-NEXT: addq %rcx, %rax +; X64-NEXT: adcq %rdi, %r8 +; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %r13, %rbp +; X64-NEXT: movq (%rbp), %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: xorl %r15d, %r15d -; X64-NEXT: mulq %r15 +; X64-NEXT: xorl %r8d, %r8d +; X64-NEXT: mulq %r8 ; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rbx -; X64-NEXT: addq %r14, %rax -; X64-NEXT: movq %r14, %rdi +; X64-NEXT: addq %rcx, %rax ; X64-NEXT: movq %rsi, %rax -; X64-NEXT: adcq %rcx, %rax +; X64-NEXT: adcq %rdi, %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq 32(%r8), %rax +; X64-NEXT: movq 32(%r14), %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %r15 -; X64-NEXT: xorl %r8d, %r8d -; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rax, %r13 +; X64-NEXT: movq %rdx, (%rsp) # 8-byte Spill +; X64-NEXT: movq %rbx, %rax ; X64-NEXT: movq %rbx, %r14 -; X64-NEXT: addq %rax, %rcx +; X64-NEXT: addq %r13, %rax ; X64-NEXT: movq %rsi, %rax ; X64-NEXT: adcq %rdx, %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: addq %rdi, %r11 +; X64-NEXT: addq %rcx, %r11 ; X64-NEXT: movq %r11, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rdi, %r11 -; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rcx, %r8 +; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: adcq %r12, %rax +; X64-NEXT: adcq %r15, %rax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r9, %r13 -; X64-NEXT: movq %r13, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r9, %rdi +; X64-NEXT: adcq %r10, %r12 +; X64-NEXT: movq %r12, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %r10, %rcx ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: adcq %rbp, %rax +; X64-NEXT: adcq %r9, %rax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rbp, %r9 -; X64-NEXT: movq 8(%r10), %rax +; X64-NEXT: movq %r9, %r10 +; X64-NEXT: movq 8(%rbp), %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r10, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %r8 -; X64-NEXT: xorl %ecx, %ecx -; X64-NEXT: movq %rax, %r15 -; X64-NEXT: addq %rsi, %r15 -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: adcq $0, %rbx -; X64-NEXT: addq %r14, %r15 -; X64-NEXT: movq %rsi, %rbp -; X64-NEXT: movq %rsi, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %rbx, %rbp -; X64-NEXT: sbbq %r8, %r8 -; X64-NEXT: andl $1, %r8d -; X64-NEXT: addq %rax, %rbp -; X64-NEXT: adcq %rdx, %r8 -; X64-NEXT: movq 16(%r10), %rax -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r14, %rbx -; X64-NEXT: addq %rax, %rbx -; X64-NEXT: movq %rsi, %r10 -; X64-NEXT: adcq %rdx, %r10 -; X64-NEXT: addq %rbp, %rbx -; X64-NEXT: adcq %r8, %r10 -; X64-NEXT: movq %r14, %rax -; X64-NEXT: movq %r14, (%rsp) # 8-byte Spill -; X64-NEXT: addq %r11, %rax -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r15, %rcx -; X64-NEXT: adcq %rcx, %r12 -; X64-NEXT: movq %r12, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %rbx, %rdi +; X64-NEXT: movq %rbp, %rdi ; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rbx, %r8 -; X64-NEXT: adcq %r10, %r9 -; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r13 # 8-byte Reload -; X64-NEXT: movq 40(%r13), %rax -; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: mulq %rdx -; X64-NEXT: xorl %r11d, %r11d -; X64-NEXT: movq %rax, %rsi -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r9 # 8-byte Reload -; X64-NEXT: addq %r9, %rsi -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: adcq $0, %rbx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: addq %rdi, %rsi -; X64-NEXT: movq %r9, %rbp +; X64-NEXT: xorl %r9d, %r9d +; X64-NEXT: movq %rax, %r12 +; X64-NEXT: addq %rsi, %r12 +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: adcq $0, %rbp +; X64-NEXT: addq %r14, %r12 +; X64-NEXT: adcq %rsi, %rbp +; X64-NEXT: movq %rsi, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: sbbq %rbx, %rbx +; X64-NEXT: andl $1, %ebx +; X64-NEXT: addq %rax, %rbp +; X64-NEXT: adcq %rdx, %rbx +; X64-NEXT: movq 16(%rdi), %rax +; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: mulq %r9 +; X64-NEXT: xorl %edi, %edi +; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %r14, %r9 +; X64-NEXT: addq %rax, %r9 +; X64-NEXT: adcq %rdx, %rsi +; X64-NEXT: addq %rbp, %r9 +; X64-NEXT: movq %r9, %rdx +; X64-NEXT: adcq %rbx, %rsi +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %r14, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: addq %r8, %rsi +; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r12, %r15 +; X64-NEXT: movq %r15, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %rdx, %rcx +; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rdx, %r15 +; X64-NEXT: adcq %rax, %r10 +; X64-NEXT: movq %r10, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rax, %r10 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq 40(%rsi), %rax +; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: mulq %rdi +; X64-NEXT: xorl %r8d, %r8d +; X64-NEXT: movq %rax, %rcx +; X64-NEXT: movq (%rsp), %rdi # 8-byte Reload +; X64-NEXT: addq %rdi, %rcx +; X64-NEXT: movq %rdx, %rbp ; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %rbx, %rbp +; X64-NEXT: addq %r13, %rcx +; X64-NEXT: adcq %rdi, %rbp ; X64-NEXT: sbbq %rbx, %rbx ; X64-NEXT: andl $1, %ebx ; X64-NEXT: addq %rax, %rbp ; X64-NEXT: adcq %rdx, %rbx -; X64-NEXT: movq 48(%r13), %rax +; X64-NEXT: movq 48(%rsi), %rax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %r11 +; X64-NEXT: mulq %r8 ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rdi, %r15 -; X64-NEXT: movq %rdi, %r11 -; X64-NEXT: addq %rax, %r15 -; X64-NEXT: movq %r9, %rdi -; X64-NEXT: adcq %rdx, %rdi -; X64-NEXT: addq %rbp, %r15 -; X64-NEXT: adcq %rbx, %rdi -; X64-NEXT: addq %r11, %r14 +; X64-NEXT: movq %r13, %r8 +; X64-NEXT: addq %rax, %r8 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: adcq %rdx, %rax +; X64-NEXT: addq %rbp, %r8 +; X64-NEXT: adcq %rbx, %rax +; X64-NEXT: movq %r13, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: addq %r13, %r14 ; X64-NEXT: movq %r14, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %rsi, %rcx -; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r15, %r8 -; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %rdi, %r10 +; X64-NEXT: adcq %rcx, %r12 +; X64-NEXT: movq %r12, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r8, %r15 +; X64-NEXT: movq %r15, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %rax, %r10 ; X64-NEXT: movq %r10, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r14 # 8-byte Reload -; X64-NEXT: movq %r14, %rax -; X64-NEXT: addq %r11, %rax +; X64-NEXT: movq %rax, %rdx +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: addq %r13, %rax ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: adcq %r9, %rax +; X64-NEXT: adcq %rdi, %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r14, %rax -; X64-NEXT: addq %r11, %rax +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: addq %r13, %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload -; X64-NEXT: movq %rsi, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload -; X64-NEXT: movq %r15, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload -; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload +; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r8 # 8-byte Folded Reload +; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdx # 8-byte Folded Reload +; X64-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: movq %rcx, %rax ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rax, %r9 -; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: movq %rax, %r8 +; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: movq 56(%rax), %rsi -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq 56(%rax), %r11 +; X64-NEXT: movq %r11, %rax ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdi, %r10 -; X64-NEXT: movq %rdx, %rdi -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %rbx, %rbp -; X64-NEXT: adcq $0, %rdi +; X64-NEXT: movq %rdi, %r9 +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %rsi, %rbx +; X64-NEXT: adcq $0, %rbp ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: movq %rax, %r8 -; X64-NEXT: addq %rbp, %r8 -; X64-NEXT: adcq $0, %rbx -; X64-NEXT: addq %rdi, %rbx -; X64-NEXT: sbbq %rdi, %rdi -; X64-NEXT: andl $1, %edi -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rcx, %r11 -; X64-NEXT: addq %rbx, %rax -; X64-NEXT: adcq %rdi, %rdx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: mulq %rdi +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rax, %r10 +; X64-NEXT: addq %rbx, %r10 +; X64-NEXT: adcq %rbp, %rsi +; X64-NEXT: sbbq %rcx, %rcx +; X64-NEXT: andl $1, %ecx +; X64-NEXT: movq %r11, %rax +; X64-NEXT: mulq %rdi +; X64-NEXT: movq %rdi, %r14 +; X64-NEXT: addq %rsi, %rax +; X64-NEXT: adcq %rcx, %rdx ; X64-NEXT: movq {{[0-9]+}}(%rsp), %r15 # 8-byte Reload -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload +; X64-NEXT: addq {{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload ; X64-NEXT: movq {{[0-9]+}}(%rsp), %r12 # 8-byte Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r12 # 8-byte Folded Reload ; X64-NEXT: addq %rax, %r15 ; X64-NEXT: adcq %rdx, %r12 ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload ; X64-NEXT: movq %rdi, %rax -; X64-NEXT: movq %r10, %rsi -; X64-NEXT: mulq %rsi -; X64-NEXT: movq %rdx, %r10 -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: movq %rcx, %rax -; X64-NEXT: mulq %rsi +; X64-NEXT: movq %r9, %rcx +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rdx, %r9 +; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rdx, %rbp ; X64-NEXT: movq %rax, %rbx -; X64-NEXT: addq %r10, %rbx +; X64-NEXT: addq %r9, %rbx ; X64-NEXT: adcq $0, %rbp ; X64-NEXT: movq %rdi, %rax -; X64-NEXT: movq %rdi, %r10 -; X64-NEXT: mulq %r11 -; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: mulq %r14 +; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: addq %rbx, %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: addq %rbp, %rdi +; X64-NEXT: adcq %rbp, %rcx ; X64-NEXT: sbbq %rbp, %rbp ; X64-NEXT: andl $1, %ebp -; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq %rcx, %rsi -; X64-NEXT: mulq %r11 +; X64-NEXT: movq %rsi, %rbx +; X64-NEXT: movq %rbx, %rax +; X64-NEXT: mulq %r14 ; X64-NEXT: movq %rdx, %r13 -; X64-NEXT: movq %rax, %rbx -; X64-NEXT: addq %rdi, %rbx +; X64-NEXT: movq %rax, %rsi +; X64-NEXT: addq %rcx, %rsi ; X64-NEXT: adcq %rbp, %r13 -; X64-NEXT: addq {{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload -; X64-NEXT: addq %r9, %rbx -; X64-NEXT: adcq %r8, %r13 +; X64-NEXT: addq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload +; X64-NEXT: addq %r8, %rsi +; X64-NEXT: adcq %r10, %r13 ; X64-NEXT: adcq $0, %r15 ; X64-NEXT: adcq $0, %r12 -; X64-NEXT: movq %r10, %rbp +; X64-NEXT: movq %rdi, %rbp ; X64-NEXT: movq %rbp, %rax -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: mulq %rdi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r9 # 8-byte Reload +; X64-NEXT: mulq %r9 ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %r9 -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: movq %rsi, %r8 -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rdi -; X64-NEXT: addq %rcx, %rdi -; X64-NEXT: adcq $0, %rsi -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: movq 24(%rax), %r14 +; X64-NEXT: movq %rax, %r10 +; X64-NEXT: movq %rbx, %rax +; X64-NEXT: movq %rbx, %r14 +; X64-NEXT: mulq %r9 +; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %rcx, %rbx +; X64-NEXT: adcq $0, %rdi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload +; X64-NEXT: movq 24(%rax), %rcx ; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %r14 +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rcx, %rbp +; X64-NEXT: movq %rbp, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: addq %rdi, %rax -; X64-NEXT: movq %rax, %rdi -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rsi, %rcx -; X64-NEXT: sbbq %rsi, %rsi -; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %r8, %rax -; X64-NEXT: mulq %r14 +; X64-NEXT: movq %rax, %r8 +; X64-NEXT: addq %rbx, %r8 +; X64-NEXT: adcq %rdi, %rcx +; X64-NEXT: sbbq %rdi, %rdi +; X64-NEXT: andl $1, %edi +; X64-NEXT: movq %r14, %rax +; X64-NEXT: mulq %rbp ; X64-NEXT: addq %rcx, %rax -; X64-NEXT: adcq %rsi, %rdx +; X64-NEXT: adcq %rdi, %rdx +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbx # 8-byte Reload +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r11 # 8-byte Reload -; X64-NEXT: addq %r11, %rbp -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload -; X64-NEXT: addq %rax, %rbp -; X64-NEXT: adcq %rdx, %rsi -; X64-NEXT: addq %rbx, %r9 -; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r13, %rdi -; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r14 # 8-byte Reload +; X64-NEXT: adcq %r14, %rbp +; X64-NEXT: addq %rax, %rbx +; X64-NEXT: adcq %rdx, %rbp +; X64-NEXT: addq %rsi, %r10 +; X64-NEXT: movq %r10, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r13, %r8 +; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq $0, %rbx ; X64-NEXT: adcq $0, %rbp -; X64-NEXT: adcq $0, %rsi -; X64-NEXT: addq %r15, %rbp -; X64-NEXT: adcq %r12, %rsi -; X64-NEXT: movl $0, %r10d -; X64-NEXT: adcq $0, %r10 -; X64-NEXT: sbbq %r15, %r15 -; X64-NEXT: andl $1, %r15d +; X64-NEXT: addq %r15, %rbx +; X64-NEXT: adcq %r12, %rbp +; X64-NEXT: movl $0, %r8d +; X64-NEXT: adcq $0, %r8 +; X64-NEXT: sbbq %r10, %r10 +; X64-NEXT: andl $1, %r10d ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %r12 -; X64-NEXT: movq %rax, %r13 -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8 # 8-byte Reload -; X64-NEXT: movq %r8, %rax -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: movq %r9, %rsi +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rdx, %r9 +; X64-NEXT: movq %rax, %r15 +; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %r11, %rax +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rdi -; X64-NEXT: addq %r12, %rdi -; X64-NEXT: adcq $0, %rbx +; X64-NEXT: addq %r9, %rdi +; X64-NEXT: adcq $0, %rsi ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: mulq %r14 -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %r9 -; X64-NEXT: addq %rdi, %r9 -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rbx, %rcx -; X64-NEXT: sbbq %rdi, %rdi -; X64-NEXT: andl $1, %edi -; X64-NEXT: movq %r8, %rax -; X64-NEXT: mulq %r14 -; X64-NEXT: movq %r14, %r12 -; X64-NEXT: addq %rcx, %rax -; X64-NEXT: adcq %rdi, %rdx +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rdx, %r9 +; X64-NEXT: movq %rax, %r13 +; X64-NEXT: addq %rdi, %r13 +; X64-NEXT: adcq %rsi, %r9 +; X64-NEXT: sbbq %rsi, %rsi +; X64-NEXT: andl $1, %esi +; X64-NEXT: movq %r11, %rax +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rcx, %r12 +; X64-NEXT: addq %r9, %rax +; X64-NEXT: adcq %rsi, %rdx ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: addq %r11, %rcx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: adcq %r14, %rsi ; X64-NEXT: addq %rax, %rcx -; X64-NEXT: adcq %rdx, %rdi -; X64-NEXT: addq %rbp, %r13 -; X64-NEXT: adcq %rsi, %r9 -; X64-NEXT: adcq %r10, %rcx -; X64-NEXT: adcq %r15, %rdi -; X64-NEXT: addq {{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload +; X64-NEXT: adcq %rdx, %rsi +; X64-NEXT: addq %rbx, %r15 +; X64-NEXT: adcq %rbp, %r13 +; X64-NEXT: adcq %r8, %rcx +; X64-NEXT: adcq %r10, %rsi +; X64-NEXT: addq {{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload +; X64-NEXT: movq %r15, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload ; X64-NEXT: movq %r13, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r9 # 8-byte Folded Reload -; X64-NEXT: movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload -; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload -; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: movq %rsi, %rax +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload +; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rax, %r11 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rax, %r9 ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: movq 24(%rax), %r8 -; X64-NEXT: movq %r8, %rax -; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdi, %r13 -; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: movq 24(%rax), %rbp +; X64-NEXT: movq %rbp, %rax +; X64-NEXT: movq %rbp, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rsi, %r14 +; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rbx ; X64-NEXT: addq %rcx, %rbx -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: mulq %rbp +; X64-NEXT: adcq $0, %rsi +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: mulq %rdi ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rax, %r15 ; X64-NEXT: addq %rbx, %r15 -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rdi, %rcx +; X64-NEXT: adcq %rsi, %rcx ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %r8, %rax -; X64-NEXT: mulq %rbp -; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: movq %rbp, %rax +; X64-NEXT: mulq %rdi +; X64-NEXT: movq %rdi, %r11 ; X64-NEXT: addq %rcx, %rax ; X64-NEXT: adcq %rsi, %rdx -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8 # 8-byte Reload -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r8 # 8-byte Folded Reload -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 # 8-byte Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r8 # 8-byte Reload +; X64-NEXT: addq {{[0-9]+}}(%rsp), %r8 # 8-byte Folded Reload +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r10 # 8-byte Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload ; X64-NEXT: addq %rax, %r8 ; X64-NEXT: adcq %rdx, %r10 -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: mulq %r13 +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: mulq %rsi ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %r13 -; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r14 # 8-byte Reload +; X64-NEXT: movq %r14, %rax +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rbx ; X64-NEXT: addq %rcx, %rbx -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: movq %rsi, %r9 -; X64-NEXT: mulq %r14 -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: addq %rbx, %rax -; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq $0, %rsi -; X64-NEXT: addq %rdi, %rsi -; X64-NEXT: sbbq %rdi, %rdi -; X64-NEXT: andl $1, %edi -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %r14 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r11 ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %rbx -; X64-NEXT: addq %rsi, %rbx -; X64-NEXT: adcq %rdi, %rcx -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload -; X64-NEXT: addq %r11, %rbx -; X64-NEXT: adcq %r15, %rcx +; X64-NEXT: addq %rbx, %rax +; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %rsi, %rcx +; X64-NEXT: sbbq %rbx, %rbx +; X64-NEXT: andl $1, %ebx +; X64-NEXT: movq %r14, %rax +; X64-NEXT: mulq %r11 +; X64-NEXT: movq %rdx, %r11 +; X64-NEXT: movq %rax, %rsi +; X64-NEXT: addq %rcx, %rsi +; X64-NEXT: adcq %rbx, %r11 +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload +; X64-NEXT: addq %r9, %rsi +; X64-NEXT: adcq %r15, %r11 ; X64-NEXT: adcq $0, %r8 ; X64-NEXT: adcq $0, %r10 -; X64-NEXT: movq %r9, %rsi -; X64-NEXT: movq %rsi, %rax +; X64-NEXT: movq %rdi, %rbx +; X64-NEXT: movq %rbx, %rax ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %r9 -; X64-NEXT: movq %rax, %r11 -; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: movq %rax, %r9 ; X64-NEXT: movq %r14, %rax ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdi, %r13 +; X64-NEXT: movq %rdi, %r15 ; X64-NEXT: movq %rdx, %rdi ; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %r9, %rbp +; X64-NEXT: addq %rcx, %rbp ; X64-NEXT: adcq $0, %rdi -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: mulq %r12 -; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rbx, %rax +; X64-NEXT: movq %r12, %r13 +; X64-NEXT: mulq %r13 +; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: addq %rbp, %rax -; X64-NEXT: movq %rax, %r15 -; X64-NEXT: adcq $0, %rsi -; X64-NEXT: addq %rdi, %rsi +; X64-NEXT: movq %rax, %rbp +; X64-NEXT: adcq %rdi, %rcx ; X64-NEXT: sbbq %rdi, %rdi ; X64-NEXT: andl $1, %edi ; X64-NEXT: movq %r14, %rax -; X64-NEXT: mulq %r12 -; X64-NEXT: addq %rsi, %rax +; X64-NEXT: mulq %r13 +; X64-NEXT: addq %rcx, %rax ; X64-NEXT: adcq %rdi, %rdx -; X64-NEXT: movq (%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbx # 8-byte Reload ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r14 # 8-byte Reload -; X64-NEXT: addq %r14, %rsi +; X64-NEXT: addq %r14, %rbx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload +; X64-NEXT: addq %rax, %rbx +; X64-NEXT: adcq %rdx, %rcx +; X64-NEXT: addq %rsi, %r9 +; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r11, %rbp +; X64-NEXT: movq %rbp, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq $0, %rbx +; X64-NEXT: adcq $0, %rcx +; X64-NEXT: addq %r8, %rbx +; X64-NEXT: adcq %r10, %rcx +; X64-NEXT: movl $0, %r12d +; X64-NEXT: adcq $0, %r12 +; X64-NEXT: sbbq %r9, %r9 +; X64-NEXT: andl $1, %r9d ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rbp # 8-byte Folded Reload -; X64-NEXT: addq %rax, %rsi -; X64-NEXT: adcq %rdx, %rbp -; X64-NEXT: addq %rbx, %r11 -; X64-NEXT: movq %r11, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %rcx, %r15 -; X64-NEXT: movq %r15, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rbp, %rax +; X64-NEXT: mulq %r15 +; X64-NEXT: movq %rdx, %r8 +; X64-NEXT: movq %rax, %r11 +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 # 8-byte Reload +; X64-NEXT: movq %r10, %rax +; X64-NEXT: mulq %r15 +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: addq %r8, %rdi ; X64-NEXT: adcq $0, %rsi -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %r8, %rsi -; X64-NEXT: adcq %r10, %rbp -; X64-NEXT: movl $0, %r10d -; X64-NEXT: adcq $0, %r10 -; X64-NEXT: sbbq %r15, %r15 -; X64-NEXT: andl $1, %r15d -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: movq %rcx, %rax +; X64-NEXT: movq %rbp, %rax ; X64-NEXT: mulq %r13 -; X64-NEXT: movq %rdx, %r9 -; X64-NEXT: movq %rax, %r11 -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r8 # 8-byte Reload -; X64-NEXT: movq %r8, %rax +; X64-NEXT: movq %rdx, %r8 +; X64-NEXT: movq %rax, %r15 +; X64-NEXT: addq %rdi, %r15 +; X64-NEXT: adcq %rsi, %r8 +; X64-NEXT: sbbq %rsi, %rsi +; X64-NEXT: andl $1, %esi +; X64-NEXT: movq %r10, %rax +; X64-NEXT: movq %r10, %rbp ; X64-NEXT: mulq %r13 -; X64-NEXT: movq %rdx, %rdi -; X64-NEXT: movq %rax, %rbx -; X64-NEXT: addq %r9, %rbx -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq %r12, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %r12 -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %r9 -; X64-NEXT: addq %rbx, %r9 -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rdi, %rcx -; X64-NEXT: sbbq %rdi, %rdi -; X64-NEXT: andl $1, %edi -; X64-NEXT: movq %r8, %rax -; X64-NEXT: mulq %r12 -; X64-NEXT: addq %rcx, %rax -; X64-NEXT: adcq %rdi, %rdx -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: addq %r14, %rcx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r12 # 8-byte Reload -; X64-NEXT: movq %r12, %r13 -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload -; X64-NEXT: addq %rax, %rcx -; X64-NEXT: adcq %rdx, %r13 -; X64-NEXT: addq %rsi, %r11 -; X64-NEXT: adcq %rbp, %r9 -; X64-NEXT: adcq %r10, %rcx -; X64-NEXT: adcq %r15, %r13 -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r9 # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload +; X64-NEXT: addq %r8, %rax +; X64-NEXT: adcq %rsi, %rdx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 # 8-byte Reload +; X64-NEXT: movq %r10, %rsi +; X64-NEXT: addq %r14, %rsi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8 # 8-byte Reload +; X64-NEXT: movq %r8, %rdi +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: addq %rax, %rsi +; X64-NEXT: adcq %rdx, %rdi +; X64-NEXT: addq %rbx, %r11 +; X64-NEXT: adcq %rcx, %r15 +; X64-NEXT: adcq %r12, %rsi +; X64-NEXT: adcq %r9, %rdi ; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: addq {{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload ; X64-NEXT: movq %r11, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r9 # 8-byte Folded Reload -; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload -; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload +; X64-NEXT: movq %r15, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: movq %rsi, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq $0, -{{[0-9]+}}(%rsp) # 8-byte Folded Spill ; X64-NEXT: adcq $0, -{{[0-9]+}}(%rsp) # 8-byte Folded Spill -; X64-NEXT: adcq $0, {{[0-9]+}}(%rsp) # 8-byte Folded Spill ; X64-NEXT: adcq $0, -{{[0-9]+}}(%rsp) # 8-byte Folded Spill -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: movq %rsi, %rax +; X64-NEXT: adcq $0, -{{[0-9]+}}(%rsp) # 8-byte Folded Spill +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %rdi -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r8, %rax +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rax, %r14 +; X64-NEXT: movq %rbp, %rax ; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rcx, %r11 +; X64-NEXT: movq %rcx, %r13 ; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %rdi, %rbp +; X64-NEXT: movq %rax, %rcx +; X64-NEXT: addq %rsi, %rcx ; X64-NEXT: adcq $0, %rbx -; X64-NEXT: movq %rsi, %rax +; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %r10 -; X64-NEXT: addq %rbp, %r10 -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rbx, %rcx -; X64-NEXT: sbbq %rsi, %rsi -; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %r8, %rax +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rax, %r11 +; X64-NEXT: addq %rcx, %r11 +; X64-NEXT: adcq %rbx, %rsi +; X64-NEXT: sbbq %rcx, %rcx +; X64-NEXT: andl $1, %ecx +; X64-NEXT: movq %rbp, %rax ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdi, %r14 -; X64-NEXT: addq %rcx, %rax -; X64-NEXT: adcq %rsi, %rdx -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r9 # 8-byte Reload +; X64-NEXT: movq %rdi, %r15 +; X64-NEXT: addq %rsi, %rax +; X64-NEXT: adcq %rcx, %rdx +; X64-NEXT: movq %r10, %r9 ; X64-NEXT: addq {{[0-9]+}}(%rsp), %r9 # 8-byte Folded Reload -; X64-NEXT: movq %r12, %r15 -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload +; X64-NEXT: movq %r8, %r12 +; X64-NEXT: adcq (%rsp), %r12 # 8-byte Folded Reload ; X64-NEXT: addq %rax, %r9 -; X64-NEXT: adcq %rdx, %r15 +; X64-NEXT: adcq %rdx, %r12 ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq %r11, %rdi -; X64-NEXT: mulq %rdi +; X64-NEXT: movq %r13, %rbp +; X64-NEXT: mulq %rbp ; X64-NEXT: movq %rdx, %r8 ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r11 # 8-byte Reload -; X64-NEXT: movq %r11, %rax -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %r8, %rbp -; X64-NEXT: adcq $0, %rbx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r13 # 8-byte Reload +; X64-NEXT: movq %r13, %rax +; X64-NEXT: mulq %rbp +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %r8, %rbx +; X64-NEXT: adcq $0, %rsi ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq %rcx, %r8 -; X64-NEXT: mulq %r14 +; X64-NEXT: movq %rcx, %rbp +; X64-NEXT: mulq %r15 ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: addq %rbp, %rax +; X64-NEXT: addq %rbx, %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rbx, %rcx -; X64-NEXT: sbbq %rbp, %rbp -; X64-NEXT: andl $1, %ebp -; X64-NEXT: movq %r11, %rax -; X64-NEXT: mulq %r14 -; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: adcq %rsi, %rcx +; X64-NEXT: sbbq %rsi, %rsi +; X64-NEXT: andl $1, %esi +; X64-NEXT: movq %r13, %rax +; X64-NEXT: mulq %r15 +; X64-NEXT: movq %rdx, %r8 ; X64-NEXT: movq %rax, %rbx ; X64-NEXT: addq %rcx, %rbx -; X64-NEXT: adcq %rbp, %rsi +; X64-NEXT: adcq %rsi, %r8 ; X64-NEXT: addq {{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: adcq %r10, %rsi +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r8 # 8-byte Folded Reload +; X64-NEXT: addq %r14, %rbx +; X64-NEXT: adcq %r11, %r8 ; X64-NEXT: adcq $0, %r9 -; X64-NEXT: adcq $0, %r15 -; X64-NEXT: movq %r8, %rbp -; X64-NEXT: movq %rbp, %rax +; X64-NEXT: adcq $0, %r12 +; X64-NEXT: movq %rbp, %rsi +; X64-NEXT: movq %rsi, %rax ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rdx, %r14 -; X64-NEXT: movq %rax, %r8 -; X64-NEXT: movq %r11, %rax +; X64-NEXT: movq %rax, %r10 +; X64-NEXT: movq %r13, %rax ; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %r12 +; X64-NEXT: movq %rdx, %rdi ; X64-NEXT: movq %rax, %rcx ; X64-NEXT: addq %r14, %rcx -; X64-NEXT: adcq $0, %r12 -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: movq 56(%rax), %rdi -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: adcq $0, %rdi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload +; X64-NEXT: movq 56(%rax), %r15 +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: mulq %r15 +; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: addq %rcx, %rax -; X64-NEXT: movq %rax, %r10 -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %r12, %rbp +; X64-NEXT: movq %rax, %r11 +; X64-NEXT: adcq %rdi, %rsi ; X64-NEXT: sbbq %rcx, %rcx ; X64-NEXT: andl $1, %ecx -; X64-NEXT: movq %r11, %rax -; X64-NEXT: mulq %rdi -; X64-NEXT: addq %rbp, %rax +; X64-NEXT: movq %r13, %rax +; X64-NEXT: mulq %r15 +; X64-NEXT: addq %rsi, %rax ; X64-NEXT: adcq %rcx, %rdx -; X64-NEXT: movq (%rsp), %rcx # 8-byte Reload -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r11 # 8-byte Reload -; X64-NEXT: addq %r11, %rcx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r12 # 8-byte Reload -; X64-NEXT: adcq %r12, %rdi -; X64-NEXT: addq %rax, %rcx -; X64-NEXT: adcq %rdx, %rdi -; X64-NEXT: addq %rbx, %r8 -; X64-NEXT: movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %rsi, %r10 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r13 # 8-byte Reload +; X64-NEXT: addq %r13, %rdi +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload +; X64-NEXT: adcq %rbp, %rsi +; X64-NEXT: addq %rax, %rdi +; X64-NEXT: adcq %rdx, %rsi +; X64-NEXT: addq %rbx, %r10 ; X64-NEXT: movq %r10, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rcx +; X64-NEXT: adcq %r8, %r11 +; X64-NEXT: movq %r11, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq $0, %rdi -; X64-NEXT: addq %r9, %rcx -; X64-NEXT: adcq %r15, %rdi -; X64-NEXT: movl $0, %r8d -; X64-NEXT: adcq $0, %r8 -; X64-NEXT: sbbq %r9, %r9 -; X64-NEXT: andl $1, %r9d -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbx # 8-byte Reload -; X64-NEXT: mulq %rbx -; X64-NEXT: movq %rdx, %r10 -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r14 # 8-byte Reload -; X64-NEXT: movq %r14, %rax -; X64-NEXT: mulq %rbx -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %r10, %rbp -; X64-NEXT: adcq $0, %rbx -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r10 # 8-byte Reload -; X64-NEXT: mulq %r10 -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %r15 -; X64-NEXT: addq %rbp, %r15 ; X64-NEXT: adcq $0, %rsi -; X64-NEXT: addq %rbx, %rsi -; X64-NEXT: sbbq %rbp, %rbp -; X64-NEXT: andl $1, %ebp -; X64-NEXT: movq %r14, %rax -; X64-NEXT: mulq %r10 -; X64-NEXT: addq %rsi, %rax -; X64-NEXT: adcq %rbp, %rdx -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r10 # 8-byte Reload -; X64-NEXT: addq %r11, %r10 -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r14 # 8-byte Reload -; X64-NEXT: adcq %r12, %r14 -; X64-NEXT: addq %rax, %r10 -; X64-NEXT: adcq %rdx, %r14 -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: addq %rcx, %rax -; X64-NEXT: adcq %rdi, %r15 -; X64-NEXT: adcq %r8, %r10 -; X64-NEXT: adcq %r9, %r14 -; X64-NEXT: addq {{[0-9]+}}(%rsp), %rax # 8-byte Folded Reload +; X64-NEXT: addq %r9, %rdi +; X64-NEXT: adcq %r12, %rsi +; X64-NEXT: movl $0, %r14d +; X64-NEXT: adcq $0, %r14 +; X64-NEXT: sbbq %r10, %r10 +; X64-NEXT: andl $1, %r10d +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbx # 8-byte Reload +; X64-NEXT: movq %rbx, %rax +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rdx, %r8 +; X64-NEXT: movq %rax, %r12 +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r9 # 8-byte Reload +; X64-NEXT: movq %r9, %rax +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rdx, %r11 +; X64-NEXT: movq %rax, %rcx +; X64-NEXT: addq %r8, %rcx +; X64-NEXT: adcq $0, %r11 +; X64-NEXT: movq %rbx, %rax +; X64-NEXT: movq %r15, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: mulq %r15 +; X64-NEXT: movq %rdx, %r8 +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %rcx, %rbx +; X64-NEXT: adcq %r11, %r8 +; X64-NEXT: sbbq %rcx, %rcx +; X64-NEXT: andl $1, %ecx +; X64-NEXT: movq %r9, %rax +; X64-NEXT: mulq %r15 +; X64-NEXT: addq %r8, %rax +; X64-NEXT: adcq %rcx, %rdx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r15 # 8-byte Reload +; X64-NEXT: addq %r13, %r15 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r11 # 8-byte Reload +; X64-NEXT: adcq %rbp, %r11 +; X64-NEXT: addq %rax, %r15 +; X64-NEXT: adcq %rdx, %r11 +; X64-NEXT: addq %rdi, %r12 +; X64-NEXT: adcq %rsi, %rbx +; X64-NEXT: adcq %r14, %r15 +; X64-NEXT: adcq %r10, %r11 +; X64-NEXT: addq {{[0-9]+}}(%rsp), %r12 # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r14 # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: addq %rcx, {{[0-9]+}}(%rsp) # 8-byte Folded Spill ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: adcq %rcx, {{[0-9]+}}(%rsp) # 8-byte Folded Spill ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: adcq %rcx, {{[0-9]+}}(%rsp) # 8-byte Folded Spill -; X64-NEXT: adcq %r13, {{[0-9]+}}(%rsp) # 8-byte Folded Spill -; X64-NEXT: adcq $0, %rax +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload +; X64-NEXT: adcq %rcx, {{[0-9]+}}(%rsp) # 8-byte Folded Spill +; X64-NEXT: adcq $0, %r12 +; X64-NEXT: adcq $0, %rbx ; X64-NEXT: adcq $0, %r15 -; X64-NEXT: adcq $0, %r10 -; X64-NEXT: adcq $0, %r14 -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rax # 8-byte Folded Reload -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq $0, %r11 +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r12 # 8-byte Folded Reload +; X64-NEXT: movq %r12, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload +; X64-NEXT: movq %rbx, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r15 # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r14 # 8-byte Folded Reload +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload ; X64-NEXT: movl $0, %eax ; X64-NEXT: adcq $0, %rax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill @@ -5122,124 +5110,124 @@ define void @test_1024(i1024* %a, i1024* %b, i1024* %out) nounwind { ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movl $0, %eax ; X64-NEXT: adcq $0, %rax -; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: sbbq %rax, %rax ; X64-NEXT: andl $1, %eax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rcx, %r9 -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: movq %rax, %rcx -; X64-NEXT: addq %rsi, %rcx -; X64-NEXT: adcq $0, %rbx -; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movq %rcx, %rax ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rdx, %r8 ; X64-NEXT: movq %rax, %r13 -; X64-NEXT: addq %rcx, %r13 -; X64-NEXT: adcq $0, %rsi -; X64-NEXT: addq %rbx, %rsi -; X64-NEXT: sbbq %rcx, %rcx -; X64-NEXT: andl $1, %ecx -; X64-NEXT: movq %rbp, %rax +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, %rax ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdi, %r11 -; X64-NEXT: addq %rsi, %rax -; X64-NEXT: adcq %rcx, %rdx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r12 # 8-byte Reload -; X64-NEXT: addq {{[0-9]+}}(%rsp), %r12 # 8-byte Folded Reload -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8 # 8-byte Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r8 # 8-byte Folded Reload -; X64-NEXT: addq %rax, %r12 -; X64-NEXT: adcq %rdx, %r8 +; X64-NEXT: movq %rdi, %r14 +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: movq %rax, %rbp +; X64-NEXT: addq %r8, %rbp +; X64-NEXT: adcq $0, %rbx +; X64-NEXT: movq %rcx, %rax +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r8 # 8-byte Reload +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: movq %rax, %r12 +; X64-NEXT: addq %rbp, %r12 +; X64-NEXT: adcq %rbx, %rcx +; X64-NEXT: sbbq %rbp, %rbp +; X64-NEXT: andl $1, %ebp +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: mulq %r8 +; X64-NEXT: addq %rcx, %rax +; X64-NEXT: adcq %rbp, %rdx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r9 # 8-byte Reload +; X64-NEXT: addq {{[0-9]+}}(%rsp), %r9 # 8-byte Folded Reload +; X64-NEXT: movq (%rsp), %r10 # 8-byte Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload +; X64-NEXT: addq %rax, %r9 +; X64-NEXT: adcq %rdx, %r10 ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload ; X64-NEXT: movq %rdi, %rax -; X64-NEXT: mulq %r9 +; X64-NEXT: movq %r14, %rbx +; X64-NEXT: mulq %rbx ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %r9 -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rbx -; X64-NEXT: addq %rcx, %rbx -; X64-NEXT: adcq $0, %rsi +; X64-NEXT: movq %rax, (%rsp) # 8-byte Spill +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: mulq %rbx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: movq %rax, %rbp +; X64-NEXT: addq %rcx, %rbp +; X64-NEXT: adcq $0, %rbx ; X64-NEXT: movq %rdi, %rax -; X64-NEXT: movq %rdi, %r9 -; X64-NEXT: mulq %r11 +; X64-NEXT: movq %rdi, %r14 +; X64-NEXT: mulq %r8 ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: addq %rbx, %rax +; X64-NEXT: addq %rbp, %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rsi, %rcx +; X64-NEXT: adcq %rbx, %rcx ; X64-NEXT: sbbq %rdi, %rdi ; X64-NEXT: andl $1, %edi -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %r11 -; X64-NEXT: movq %rdx, %r11 -; X64-NEXT: movq %rax, %rsi -; X64-NEXT: addq %rcx, %rsi -; X64-NEXT: adcq %rdi, %r11 -; X64-NEXT: addq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload -; X64-NEXT: adcq %r13, %r11 -; X64-NEXT: adcq $0, %r12 -; X64-NEXT: adcq $0, %r8 -; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r9, %rdi -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %r8 -; X64-NEXT: movq %rax, %r13 -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: movq %rbp, %r9 -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %rbp -; X64-NEXT: movq %rax, %rcx -; X64-NEXT: addq %r8, %rcx -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: movq %rax, %rbp +; X64-NEXT: addq %rcx, %rbp +; X64-NEXT: adcq %rdi, %rbx +; X64-NEXT: addq {{[0-9]+}}(%rsp), %rbp # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload +; X64-NEXT: addq %r13, %rbp +; X64-NEXT: adcq %r12, %rbx +; X64-NEXT: adcq $0, %r9 +; X64-NEXT: movq %r9, %r12 +; X64-NEXT: adcq $0, %r10 +; X64-NEXT: movq %r10, %r8 +; X64-NEXT: movq %r14, %rax ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload ; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: addq %rcx, %rax -; X64-NEXT: movq %rax, %r8 -; X64-NEXT: adcq $0, %rbx -; X64-NEXT: addq %rbp, %rbx -; X64-NEXT: sbbq %rcx, %rcx -; X64-NEXT: andl $1, %ecx -; X64-NEXT: movq %r9, %rax +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: movq %rax, %r9 +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: movq %rsi, %r10 ; X64-NEXT: mulq %rdi -; X64-NEXT: addq %rbx, %rax -; X64-NEXT: adcq %rcx, %rdx -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: addq {{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: addq %rcx, %rdi +; X64-NEXT: adcq $0, %rsi +; X64-NEXT: movq %r14, %rax ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload -; X64-NEXT: addq %rax, %rdi +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: addq %rdi, %rax +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: adcq %rsi, %r14 +; X64-NEXT: sbbq %rsi, %rsi +; X64-NEXT: andl $1, %esi +; X64-NEXT: movq %r10, %rax +; X64-NEXT: mulq %rcx +; X64-NEXT: addq %r14, %rax +; X64-NEXT: adcq %rsi, %rdx +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r14 # 8-byte Reload +; X64-NEXT: addq %r14, %rsi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r13 # 8-byte Reload +; X64-NEXT: adcq %r13, %rcx +; X64-NEXT: addq %rax, %rsi ; X64-NEXT: adcq %rdx, %rcx -; X64-NEXT: addq %rsi, %r13 -; X64-NEXT: adcq %r11, %r8 -; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %r12, %rdi +; X64-NEXT: addq %rbp, %r9 +; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %rbx, %rdi ; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload -; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movl $0, %r12d -; X64-NEXT: adcq $0, %r12 +; X64-NEXT: adcq $0, %rsi +; X64-NEXT: adcq $0, %rcx +; X64-NEXT: addq %r12, %rsi +; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r8, %rcx +; X64-NEXT: movq %rcx, %r12 +; X64-NEXT: movl $0, %r10d +; X64-NEXT: adcq $0, %r10 ; X64-NEXT: sbbq %r9, %r9 ; X64-NEXT: andl $1, %r9d ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbx # 8-byte Reload @@ -5247,678 +5235,679 @@ define void @test_1024(i1024* %a, i1024* %b, i1024* %out) nounwind { ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload ; X64-NEXT: mulq %rsi ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %r11 +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8 # 8-byte Reload ; X64-NEXT: movq %r8, %rax ; X64-NEXT: mulq %rsi ; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %rcx, %rbp +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: addq %rcx, %rdi ; X64-NEXT: adcq $0, %rsi ; X64-NEXT: movq %rbx, %rax -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: mulq %rdi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbp # 8-byte Reload +; X64-NEXT: mulq %rbp ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rax, %rbx -; X64-NEXT: addq %rbp, %rbx -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rsi, %rcx +; X64-NEXT: addq %rdi, %rbx +; X64-NEXT: adcq %rsi, %rcx ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi ; X64-NEXT: movq %r8, %rax -; X64-NEXT: mulq %rdi +; X64-NEXT: mulq %rbp ; X64-NEXT: addq %rcx, %rax ; X64-NEXT: adcq %rsi, %rdx ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: addq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: addq %r14, %rsi ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload +; X64-NEXT: adcq %r13, %rcx ; X64-NEXT: addq %rax, %rsi ; X64-NEXT: adcq %rdx, %rcx -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: adcq %r12, %rsi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r13 # 8-byte Reload +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload +; X64-NEXT: adcq %r12, %rbx +; X64-NEXT: adcq %r10, %rsi ; X64-NEXT: adcq %r9, %rcx -; X64-NEXT: addq {{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload +; X64-NEXT: addq {{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: addq %rax, {{[0-9]+}}(%rsp) # 8-byte Folded Spill +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload +; X64-NEXT: addq %rax, (%rsp) # 8-byte Folded Spill +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload +; X64-NEXT: adcq %rax, {{[0-9]+}}(%rsp) # 8-byte Folded Spill ; X64-NEXT: adcq %r15, {{[0-9]+}}(%rsp) # 8-byte Folded Spill -; X64-NEXT: adcq %r10, %r13 +; X64-NEXT: adcq %r11, -{{[0-9]+}}(%rsp) # 8-byte Folded Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload ; X64-NEXT: movq %r13, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r14, -{{[0-9]+}}(%rsp) # 8-byte Folded Spill -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload -; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: movq %rbx, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: movq %rbx, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload ; X64-NEXT: movq %rsi, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload ; X64-NEXT: movq %rcx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: movq 64(%rsi), %r14 -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %r14 +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r9 # 8-byte Reload +; X64-NEXT: movq 64(%r9), %r11 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r11 ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r8 # 8-byte Reload -; X64-NEXT: movq %r8, %rax -; X64-NEXT: mulq %r14 -; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r10 # 8-byte Reload +; X64-NEXT: movq %r10, %rax +; X64-NEXT: mulq %r11 +; X64-NEXT: movq %rdx, %rbp ; X64-NEXT: movq %rax, %rbx ; X64-NEXT: addq %rcx, %rbx -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: movq 72(%rsi), %rcx -; X64-NEXT: movq %rsi, %r13 -; X64-NEXT: movq %rbp, %rax +; X64-NEXT: adcq $0, %rbp +; X64-NEXT: movq 72(%r9), %rcx +; X64-NEXT: movq %rdi, %rax ; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rcx, %rsi ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %r10 -; X64-NEXT: addq %rbx, %r10 -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rdi, %rcx -; X64-NEXT: sbbq %rdi, %rdi -; X64-NEXT: andl $1, %edi -; X64-NEXT: movq %r8, %rax +; X64-NEXT: movq %rax, %r8 +; X64-NEXT: addq %rbx, %r8 +; X64-NEXT: adcq %rbp, %rcx +; X64-NEXT: sbbq %rbp, %rbp +; X64-NEXT: andl $1, %ebp +; X64-NEXT: movq %r10, %rax ; X64-NEXT: mulq %rsi -; X64-NEXT: movq %rsi, %r8 +; X64-NEXT: movq %rsi, %r10 +; X64-NEXT: movq %r10, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %rcx, %rbp -; X64-NEXT: adcq %rdi, %rsi -; X64-NEXT: movq %r14, %rax +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: addq %rcx, %rdi +; X64-NEXT: adcq %rbp, %rsi +; X64-NEXT: movq %r11, %rax ; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rax, %rbx -; X64-NEXT: movq %rdx, %r11 -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r15 # 8-byte Reload -; X64-NEXT: addq %rbx, %r15 +; X64-NEXT: movq %rdx, %r14 ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r12 # 8-byte Reload -; X64-NEXT: adcq %r11, %r12 -; X64-NEXT: addq %rbp, %r15 -; X64-NEXT: adcq %rsi, %r12 +; X64-NEXT: addq %rbx, %r12 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r15 # 8-byte Reload +; X64-NEXT: adcq %r14, %r15 +; X64-NEXT: addq %rdi, %r12 +; X64-NEXT: adcq %rsi, %r15 ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq %r14, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %r14 -; X64-NEXT: movq %rdx, %r9 +; X64-NEXT: movq %r11, %rsi +; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rdx, %r11 ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: mulq %r14 +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload +; X64-NEXT: movq %rbp, %rax +; X64-NEXT: mulq %rsi ; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %r9, %rbp +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: addq %r11, %rdi ; X64-NEXT: adcq $0, %rsi ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq %rcx, %r14 -; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rcx, %r11 +; X64-NEXT: mulq %r10 ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: addq %rbp, %rax +; X64-NEXT: addq %rdi, %rax ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rsi, %rcx +; X64-NEXT: adcq %rsi, %rcx ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: movq %rdi, %r9 -; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rbp, %rax +; X64-NEXT: movq %rbp, %rdi +; X64-NEXT: mulq %r10 ; X64-NEXT: addq %rcx, %rax ; X64-NEXT: adcq %rsi, %rdx -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload +; X64-NEXT: addq {{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r13 # 8-byte Reload +; X64-NEXT: adcq %r13, %r14 ; X64-NEXT: addq %rax, %rbx -; X64-NEXT: adcq %rdx, %r11 +; X64-NEXT: adcq %rdx, %r14 ; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: adcq %r10, %r11 -; X64-NEXT: adcq $0, %r15 +; X64-NEXT: adcq %r8, %r14 ; X64-NEXT: adcq $0, %r12 -; X64-NEXT: movq 80(%r13), %rbp -; X64-NEXT: movq %r14, %rsi -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: mulq %rbp -; X64-NEXT: movq %rdx, %r8 -; X64-NEXT: movq %rax, %r14 -; X64-NEXT: movq %r9, %rax -; X64-NEXT: mulq %rbp +; X64-NEXT: adcq $0, %r15 +; X64-NEXT: movq %r9, %rbp +; X64-NEXT: movq 80(%rbp), %r8 +; X64-NEXT: movq %r11, %rax +; X64-NEXT: movq %r11, %r9 +; X64-NEXT: mulq %r8 ; X64-NEXT: movq %rdx, %r10 +; X64-NEXT: movq %rax, %r11 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rcx -; X64-NEXT: addq %r8, %rcx -; X64-NEXT: adcq $0, %r10 -; X64-NEXT: movq 88(%r13), %r13 -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: mulq %r13 -; X64-NEXT: movq %rdx, %rdi -; X64-NEXT: movq %rax, %r8 -; X64-NEXT: addq %rcx, %r8 -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: addq %r10, %rdi +; X64-NEXT: addq %r10, %rcx +; X64-NEXT: adcq $0, %rsi +; X64-NEXT: movq 88(%rbp), %r10 +; X64-NEXT: movq %r9, %rax +; X64-NEXT: mulq %r10 +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rax, %r9 +; X64-NEXT: addq %rcx, %r9 +; X64-NEXT: adcq %rsi, %rbp ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %r9, %rax -; X64-NEXT: mulq %r13 -; X64-NEXT: movq %rdx, %r10 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r10 +; X64-NEXT: movq %rdx, %rdi ; X64-NEXT: movq %rax, %rcx -; X64-NEXT: addq %rdi, %rcx -; X64-NEXT: adcq %rsi, %r10 -; X64-NEXT: movq %rbp, %rax +; X64-NEXT: addq %rbp, %rcx +; X64-NEXT: adcq %rsi, %rdi +; X64-NEXT: movq %r8, %rax ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: mulq %rdx -; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rax, %rdi -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: addq %rdi, %rsi -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: addq %rax, %rsi +; X64-NEXT: movq %r13, %rax ; X64-NEXT: adcq %rdx, %rax +; X64-NEXT: movq %rdx, %r13 ; X64-NEXT: addq %rcx, %rsi -; X64-NEXT: adcq %r10, %rax -; X64-NEXT: addq %rbx, %r14 -; X64-NEXT: movq %r14, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r11, %r8 -; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %rdi, %rax +; X64-NEXT: addq %rbx, %r11 +; X64-NEXT: movq %r11, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r14, %r9 +; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq $0, %rsi ; X64-NEXT: adcq $0, %rax -; X64-NEXT: addq %r15, %rsi -; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r12, %rax -; X64-NEXT: movq %rax, %r10 -; X64-NEXT: movl $0, %r15d -; X64-NEXT: adcq $0, %r15 -; X64-NEXT: sbbq %r12, %r12 -; X64-NEXT: andl $1, %r12d -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: movq %rcx, %rax -; X64-NEXT: mulq %rbp -; X64-NEXT: movq %rdx, %r8 -; X64-NEXT: movq %rax, %r14 -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r11 # 8-byte Reload -; X64-NEXT: movq %r11, %rax -; X64-NEXT: mulq %rbp +; X64-NEXT: addq %r12, %rsi +; X64-NEXT: movq %rsi, %r14 +; X64-NEXT: adcq %r15, %rax +; X64-NEXT: movq %rax, %r9 +; X64-NEXT: movl $0, %r12d +; X64-NEXT: adcq $0, %r12 +; X64-NEXT: sbbq %r11, %r11 +; X64-NEXT: andl $1, %r11d +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: movq %rax, %r15 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbp # 8-byte Reload +; X64-NEXT: movq %rbp, %rax +; X64-NEXT: mulq %r8 ; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rbx -; X64-NEXT: addq %r8, %rbx +; X64-NEXT: addq %rcx, %rbx ; X64-NEXT: adcq $0, %rsi -; X64-NEXT: movq %rcx, %rax -; X64-NEXT: mulq %r13 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r10 ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: addq %rbx, %rax -; X64-NEXT: movq %rax, %rbx -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rsi, %rcx +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: adcq %rsi, %rcx ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %r11, %rax -; X64-NEXT: mulq %r13 +; X64-NEXT: movq %rbp, %rax +; X64-NEXT: mulq %r10 ; X64-NEXT: addq %rcx, %rax ; X64-NEXT: adcq %rsi, %rdx ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: addq %rdi, %rsi +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload +; X64-NEXT: adcq %r13, %rcx ; X64-NEXT: addq %rax, %rsi ; X64-NEXT: adcq %rdx, %rcx -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r14 # 8-byte Folded Reload -; X64-NEXT: movq %r14, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r10, %rbx -; X64-NEXT: movq %rbx, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r15, %rsi +; X64-NEXT: addq %r14, %r15 +; X64-NEXT: movq %r15, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r9, %rdi +; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r12, %rsi ; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r12, %rcx +; X64-NEXT: adcq %r11, %rcx ; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: imulq %rax, %r13 -; X64-NEXT: movq %rax, %r8 -; X64-NEXT: mulq %rbp +; X64-NEXT: imulq %rax, %r10 +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: mulq %r8 ; X64-NEXT: movq %rax, %r9 -; X64-NEXT: addq %r13, %rdx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: imulq %rdi, %rbp -; X64-NEXT: addq %rdx, %rbp +; X64-NEXT: addq %r10, %rdx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 # 8-byte Reload +; X64-NEXT: imulq %r10, %r8 +; X64-NEXT: addq %rdx, %r8 ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload ; X64-NEXT: movq %rax, %rsi -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r12 # 8-byte Reload -; X64-NEXT: imulq %r12, %rsi -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rax, %r10 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbx # 8-byte Reload +; X64-NEXT: imulq %rbx, %rsi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbp # 8-byte Reload +; X64-NEXT: mulq %rbp +; X64-NEXT: movq %rax, %r11 ; X64-NEXT: addq %rsi, %rdx ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: imulq %rcx, %rax +; X64-NEXT: imulq %rbp, %rax ; X64-NEXT: addq %rdx, %rax -; X64-NEXT: addq %r9, %r10 -; X64-NEXT: adcq %rbp, %rax -; X64-NEXT: movq %rax, %r9 -; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq %rcx, %rbp -; X64-NEXT: mulq %r8 +; X64-NEXT: addq %r9, %r11 +; X64-NEXT: adcq %r8, %rax +; X64-NEXT: movq %rax, %r14 +; X64-NEXT: movq %rbp, %rax +; X64-NEXT: mulq %rdi ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %r12, %rax -; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rbx, %rax +; X64-NEXT: movq %rbx, %r8 +; X64-NEXT: mulq %rdi ; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rbx ; X64-NEXT: addq %rcx, %rbx ; X64-NEXT: adcq $0, %rsi ; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdx, %rbp -; X64-NEXT: movq %rax, %r14 -; X64-NEXT: addq %rbx, %r14 -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %rsi, %rbp +; X64-NEXT: movq %r10, %rbp +; X64-NEXT: mulq %rbp +; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: movq %rax, %r15 +; X64-NEXT: addq %rbx, %r15 +; X64-NEXT: adcq %rsi, %rdi ; X64-NEXT: sbbq %rcx, %rcx ; X64-NEXT: andl $1, %ecx -; X64-NEXT: movq %r12, %rax -; X64-NEXT: mulq %rdi +; X64-NEXT: movq %r8, %rax +; X64-NEXT: mulq %rbp ; X64-NEXT: movq %rdx, %r12 -; X64-NEXT: movq %rax, %r8 -; X64-NEXT: addq %rbp, %r8 +; X64-NEXT: movq %rax, %r9 +; X64-NEXT: addq %rdi, %r9 ; X64-NEXT: adcq %rcx, %r12 -; X64-NEXT: addq %r10, %r8 -; X64-NEXT: adcq %r9, %r12 +; X64-NEXT: addq %r11, %r9 +; X64-NEXT: adcq %r14, %r12 ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdx # 8-byte Reload ; X64-NEXT: movq 120(%rdx), %rcx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r9 # 8-byte Reload -; X64-NEXT: imulq %r9, %rcx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 # 8-byte Reload +; X64-NEXT: imulq %r10, %rcx ; X64-NEXT: movq 112(%rdx), %rsi -; X64-NEXT: movq %rdx, %rdi -; X64-NEXT: movq %r9, %rax +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %r10, %rax ; X64-NEXT: mulq %rsi -; X64-NEXT: movq %rax, %r15 +; X64-NEXT: movq %rax, %r11 ; X64-NEXT: addq %rcx, %rdx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 # 8-byte Reload -; X64-NEXT: imulq %r10, %rsi +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r8 # 8-byte Reload +; X64-NEXT: imulq %r8, %rsi ; X64-NEXT: addq %rdx, %rsi -; X64-NEXT: movq 96(%rdi), %rbp -; X64-NEXT: movq 104(%rdi), %rbx +; X64-NEXT: movq 96(%rbp), %rdi +; X64-NEXT: movq 104(%rbp), %rbx ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload ; X64-NEXT: movq %rax, %rcx ; X64-NEXT: imulq %rbx, %rcx -; X64-NEXT: mulq %rbp +; X64-NEXT: mulq %rdi ; X64-NEXT: movq %rax, %r13 ; X64-NEXT: addq %rcx, %rdx -; X64-NEXT: imulq %rbp, %r11 -; X64-NEXT: addq %rdx, %r11 -; X64-NEXT: addq %r15, %r13 -; X64-NEXT: adcq %rsi, %r11 -; X64-NEXT: movq %r11, %r15 -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %r9 -; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload +; X64-NEXT: imulq %rdi, %rax +; X64-NEXT: addq %rdx, %rax +; X64-NEXT: addq %r11, %r13 +; X64-NEXT: adcq %rsi, %rax ; X64-NEXT: movq %rax, %r11 -; X64-NEXT: movq %rbx, %rax -; X64-NEXT: mulq %r9 -; X64-NEXT: movq %rdx, %rdi -; X64-NEXT: movq %rax, %rcx -; X64-NEXT: addq %rsi, %rcx -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: movq %rbp, %rax +; X64-NEXT: movq %rdi, %rax ; X64-NEXT: mulq %r10 -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %rcx, %rbp -; X64-NEXT: adcq $0, %rsi -; X64-NEXT: addq %rdi, %rsi -; X64-NEXT: sbbq %rcx, %rcx -; X64-NEXT: andl $1, %ecx +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: movq %rax, %r14 ; X64-NEXT: movq %rbx, %rax ; X64-NEXT: mulq %r10 -; X64-NEXT: addq %rsi, %rax -; X64-NEXT: adcq %rcx, %rdx +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rax, %rsi +; X64-NEXT: addq %rcx, %rsi +; X64-NEXT: adcq $0, %rbp +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: addq %rsi, %rdi +; X64-NEXT: adcq %rbp, %rcx +; X64-NEXT: sbbq %rsi, %rsi +; X64-NEXT: andl $1, %esi +; X64-NEXT: movq %rbx, %rax +; X64-NEXT: mulq %r8 +; X64-NEXT: addq %rcx, %rax +; X64-NEXT: adcq %rsi, %rdx ; X64-NEXT: addq %r13, %rax -; X64-NEXT: adcq %r15, %rdx -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload -; X64-NEXT: adcq %r14, %rbp -; X64-NEXT: adcq %r8, %rax +; X64-NEXT: adcq %r11, %rdx +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r14 # 8-byte Folded Reload +; X64-NEXT: adcq %r15, %rdi +; X64-NEXT: adcq %r9, %rax ; X64-NEXT: adcq %r12, %rdx -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload -; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rbp # 8-byte Folded Reload -; X64-NEXT: movq %rbp, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r14 # 8-byte Folded Reload +; X64-NEXT: movq %r14, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rax # 8-byte Folded Reload ; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdx # 8-byte Folded Reload ; X64-NEXT: movq %rdx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: movq 80(%rsi), %r9 -; X64-NEXT: movq %r9, %rax -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq 88(%rsi), %r8 -; X64-NEXT: movq %rsi, %r11 -; X64-NEXT: movq %r8, %rax -; X64-NEXT: movq %r8, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rdi, %rbx -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rdi -; X64-NEXT: addq %rcx, %rdi -; X64-NEXT: adcq $0, %rsi -; X64-NEXT: movq %r9, %rax +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq 80(%rsi), %rcx +; X64-NEXT: movq %rcx, %rax +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r8 # 8-byte Reload +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rdx, %r9 +; X64-NEXT: movq 88(%rsi), %r10 +; X64-NEXT: movq %rsi, %r12 +; X64-NEXT: movq %r10, %rax +; X64-NEXT: movq %r10, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %r9, %rbx +; X64-NEXT: adcq $0, %rbp +; X64-NEXT: movq %rcx, %rax +; X64-NEXT: movq %rcx, %r9 ; X64-NEXT: movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq {{[0-9]+}}(%rsp), %r15 # 8-byte Reload ; X64-NEXT: mulq %r15 -; X64-NEXT: movq %rdx, %rbp -; X64-NEXT: movq %rax, %r14 -; X64-NEXT: addq %rdi, %r14 -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %rsi, %rbp +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: addq %rbx, %rax +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %rbp, %rsi ; X64-NEXT: sbbq %rdi, %rdi ; X64-NEXT: andl $1, %edi -; X64-NEXT: movq %r8, %rax +; X64-NEXT: movq %r10, %rax ; X64-NEXT: mulq %r15 -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rcx -; X64-NEXT: addq %rbp, %rcx -; X64-NEXT: adcq %rdi, %rsi +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %rsi, %rbx +; X64-NEXT: adcq %rdi, %rbp ; X64-NEXT: movq %r9, %rax -; X64-NEXT: xorl %r13d, %r13d -; X64-NEXT: mulq %r13 -; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: xorl %ecx, %ecx +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rdx, %r11 +; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rax, %r10 +; X64-NEXT: movq %r10, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r9 # 8-byte Reload +; X64-NEXT: addq %r9, %r10 +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r13 # 8-byte Reload +; X64-NEXT: adcq %r13, %r11 +; X64-NEXT: addq %rbx, %r10 +; X64-NEXT: adcq %rbp, %r11 +; X64-NEXT: movq %r12, %rcx +; X64-NEXT: movq 64(%rcx), %rdi +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq 72(%rcx), %r14 +; X64-NEXT: movq %r14, %rax +; X64-NEXT: mulq %r8 +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %rsi, %rbx +; X64-NEXT: adcq $0, %rbp +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %r15 +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: addq %rbx, %rax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rax, %r12 -; X64-NEXT: movq (%rsp), %r10 # 8-byte Reload -; X64-NEXT: addq %r10, %r12 +; X64-NEXT: adcq %rbp, %rsi +; X64-NEXT: sbbq %rcx, %rcx +; X64-NEXT: andl $1, %ecx +; X64-NEXT: movq %r14, %rax +; X64-NEXT: mulq %r15 +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: movq %rax, %rbp +; X64-NEXT: addq %rsi, %rbp +; X64-NEXT: adcq %rcx, %rbx +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: xorl %ecx, %ecx +; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rdx, %r8 -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r9 # 8-byte Reload -; X64-NEXT: adcq %r9, %r8 -; X64-NEXT: addq %rcx, %r12 -; X64-NEXT: adcq %rsi, %r8 -; X64-NEXT: movq %r11, %rsi -; X64-NEXT: movq 64(%rsi), %r11 -; X64-NEXT: movq %r11, %rax -; X64-NEXT: movq %rbx, %rdi -; X64-NEXT: mulq %rdi -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rax, %r15 +; X64-NEXT: addq %r15, %r9 +; X64-NEXT: movq %r13, %rax +; X64-NEXT: adcq %r8, %rax +; X64-NEXT: addq %rbp, %r9 +; X64-NEXT: adcq %rbx, %rax +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r9 # 8-byte Folded Reload +; X64-NEXT: movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rax # 8-byte Folded Reload +; X64-NEXT: movq %rax, %r13 +; X64-NEXT: adcq $0, %r10 +; X64-NEXT: adcq $0, %r11 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: mulq %rsi ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq 72(%rsi), %rbx -; X64-NEXT: movq %rbx, %rax -; X64-NEXT: mulq %rdi +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: movq %r14, %rax +; X64-NEXT: movq %r14, %r12 +; X64-NEXT: movq %r12, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rsi, %r14 ; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rbp ; X64-NEXT: addq %rcx, %rbp ; X64-NEXT: adcq $0, %rsi -; X64-NEXT: movq %r11, %rax -; X64-NEXT: mulq %r15 -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: addq %rbp, %rax -; X64-NEXT: movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rsi, %rcx -; X64-NEXT: sbbq %rdi, %rdi -; X64-NEXT: andl $1, %edi -; X64-NEXT: movq %rbx, %rax -; X64-NEXT: mulq %r15 -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %rcx, %rbp -; X64-NEXT: adcq %rdi, %rsi -; X64-NEXT: movq %r11, %rdi -; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rdi, %rax -; X64-NEXT: mulq %r13 -; X64-NEXT: movq %rdx, %r11 -; X64-NEXT: movq %rax, %r13 -; X64-NEXT: addq %r13, %r10 -; X64-NEXT: adcq %r11, %r9 -; X64-NEXT: addq %rbp, %r10 -; X64-NEXT: adcq %rsi, %r9 -; X64-NEXT: addq {{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload -; X64-NEXT: movq %r10, (%rsp) # 8-byte Spill -; X64-NEXT: adcq %r14, %r9 -; X64-NEXT: movq %r9, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %r12 -; X64-NEXT: adcq $0, %r8 -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rdx, %r9 -; X64-NEXT: movq %rax, %r15 -; X64-NEXT: movq %rbx, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rbx, %rax -; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %rbp -; X64-NEXT: movq %rax, %rsi -; X64-NEXT: addq %r9, %rsi -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: movq %rdi, %rax -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 # 8-byte Reload -; X64-NEXT: mulq %r10 -; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rax, %rdi -; X64-NEXT: addq %rsi, %rdi -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rbp, %rcx +; X64-NEXT: addq %rbp, %rdi +; X64-NEXT: adcq %rsi, %r9 ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %rbx, %rax -; X64-NEXT: mulq %r10 -; X64-NEXT: addq %rcx, %rax +; X64-NEXT: movq %r12, %rax +; X64-NEXT: mulq %rcx +; X64-NEXT: movq %rcx, %rbp +; X64-NEXT: addq %r9, %rax ; X64-NEXT: adcq %rsi, %rdx -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r13 # 8-byte Folded Reload -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r14 # 8-byte Reload -; X64-NEXT: adcq %r14, %r11 -; X64-NEXT: addq %rax, %r13 -; X64-NEXT: adcq %rdx, %r11 -; X64-NEXT: addq (%rsp), %r15 # 8-byte Folded Reload -; X64-NEXT: movq %r15, (%rsp) # 8-byte Spill -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r12 # 8-byte Reload +; X64-NEXT: addq %r12, %r15 +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r8 # 8-byte Folded Reload +; X64-NEXT: addq %rax, %r15 +; X64-NEXT: adcq %rdx, %r8 +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload +; X64-NEXT: movq %rbx, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r13, %rdi ; X64-NEXT: movq %rdi, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %r13 -; X64-NEXT: adcq $0, %r11 -; X64-NEXT: addq %r12, %r13 -; X64-NEXT: adcq %r8, %r11 -; X64-NEXT: movl $0, %r8d +; X64-NEXT: adcq $0, %r15 ; X64-NEXT: adcq $0, %r8 -; X64-NEXT: sbbq %r9, %r9 -; X64-NEXT: andl $1, %r9d +; X64-NEXT: addq %r10, %r15 +; X64-NEXT: adcq %r11, %r8 +; X64-NEXT: movl $0, %r9d +; X64-NEXT: adcq $0, %r9 +; X64-NEXT: sbbq %r13, %r13 +; X64-NEXT: andl $1, %r13d ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r15 # 8-byte Reload -; X64-NEXT: mulq %r15 -; X64-NEXT: movq %rdx, %r12 -; X64-NEXT: movq %rax, %rdi -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbx # 8-byte Reload -; X64-NEXT: movq %rbx, %rax -; X64-NEXT: mulq %r15 +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rax, %r10 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rsi, %r11 ; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %r12, %rbp +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %r14, %rbx ; X64-NEXT: adcq $0, %rsi ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: mulq %r10 +; X64-NEXT: mulq %rbp ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: addq %rbp, %rax -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rsi, %rcx +; X64-NEXT: addq %rbx, %rax +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: adcq %rsi, %rcx ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %rbx, %rax -; X64-NEXT: mulq %r10 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movq %rdi, %r14 +; X64-NEXT: mulq %rbp ; X64-NEXT: addq %rcx, %rax ; X64-NEXT: adcq %rsi, %rdx ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: addq %r12, %rsi ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: adcq %r14, %rcx +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload ; X64-NEXT: addq %rax, %rsi ; X64-NEXT: adcq %rdx, %rcx -; X64-NEXT: addq %r13, %rdi -; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r11, %rbp -; X64-NEXT: movq %rbp, {{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r8, %rsi +; X64-NEXT: addq %r15, %r10 +; X64-NEXT: movq %r10, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r8, %rbx +; X64-NEXT: movq %rbx, {{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq %r9, %rsi ; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq %r9, %rcx +; X64-NEXT: adcq %r13, %rcx ; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: movq 96(%rbp), %rcx -; X64-NEXT: imulq %rcx, %r10 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq 96(%rsi), %rcx +; X64-NEXT: imulq %rcx, %rbp ; X64-NEXT: movq %rcx, %rax -; X64-NEXT: mulq %r15 +; X64-NEXT: movq %r11, %rdi +; X64-NEXT: mulq %rdi ; X64-NEXT: movq %rax, %r9 -; X64-NEXT: addq %r10, %rdx -; X64-NEXT: movq 104(%rbp), %r8 -; X64-NEXT: imulq %r8, %r15 -; X64-NEXT: addq %rdx, %r15 -; X64-NEXT: movq 112(%rbp), %rax -; X64-NEXT: movq %rbp, %rdi -; X64-NEXT: movq %rax, %rsi +; X64-NEXT: addq %rbp, %rdx +; X64-NEXT: movq 104(%rsi), %r8 +; X64-NEXT: imulq %r8, %rdi +; X64-NEXT: addq %rdx, %rdi +; X64-NEXT: movq %rdi, %r10 +; X64-NEXT: movq 112(%rsi), %rax +; X64-NEXT: movq %rsi, %rbp +; X64-NEXT: movq %rax, %rdi ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbx # 8-byte Reload -; X64-NEXT: imulq %rbx, %rsi -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: mulq %rbp -; X64-NEXT: movq %rax, %r13 -; X64-NEXT: addq %rsi, %rdx -; X64-NEXT: movq 120(%rdi), %rdi -; X64-NEXT: imulq %rbp, %rdi +; X64-NEXT: imulq %rbx, %rdi +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: mulq %rsi +; X64-NEXT: movq %rax, %r11 +; X64-NEXT: addq %rdi, %rdx +; X64-NEXT: movq 120(%rbp), %rdi +; X64-NEXT: imulq %rsi, %rdi ; X64-NEXT: addq %rdx, %rdi -; X64-NEXT: addq %r9, %r13 -; X64-NEXT: adcq %r15, %rdi -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: movq %rbp, %r9 +; X64-NEXT: addq %r9, %r11 +; X64-NEXT: adcq %r10, %rdi +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: movq %rsi, %r10 ; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rbx, %rax +; X64-NEXT: movq %rbx, %r9 ; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %rsi -; X64-NEXT: addq %rbp, %rsi +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %rsi, %rbx ; X64-NEXT: adcq $0, %rcx -; X64-NEXT: movq %r9, %rax +; X64-NEXT: movq %r10, %rax ; X64-NEXT: mulq %r8 -; X64-NEXT: movq %rdx, %rbp -; X64-NEXT: movq %rax, %r12 -; X64-NEXT: addq %rsi, %r12 -; X64-NEXT: adcq $0, %rbp -; X64-NEXT: addq %rcx, %rbp +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rax, %r15 +; X64-NEXT: addq %rbx, %r15 +; X64-NEXT: adcq %rcx, %rsi ; X64-NEXT: sbbq %rcx, %rcx ; X64-NEXT: andl $1, %ecx -; X64-NEXT: movq %rbx, %rax +; X64-NEXT: movq %r9, %rax ; X64-NEXT: mulq %r8 -; X64-NEXT: movq %rdx, %r8 -; X64-NEXT: movq %rax, %r9 -; X64-NEXT: addq %rbp, %r9 -; X64-NEXT: adcq %rcx, %r8 -; X64-NEXT: addq %r13, %r9 -; X64-NEXT: adcq %rdi, %r8 +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: movq %rax, %r8 +; X64-NEXT: addq %rsi, %r8 +; X64-NEXT: adcq %rcx, %rbx +; X64-NEXT: addq %r11, %r8 +; X64-NEXT: adcq %rdi, %rbx ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbx # 8-byte Reload -; X64-NEXT: imulq %rbx, %rsi -; X64-NEXT: movq %rbx, %rax +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload +; X64-NEXT: imulq %rax, %rsi +; X64-NEXT: movq %rax, %r9 ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rax, %r10 +; X64-NEXT: movq %rax, %r11 ; X64-NEXT: addq %rsi, %rdx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r11 # 8-byte Reload -; X64-NEXT: imulq %r11, %rcx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %r12 # 8-byte Reload +; X64-NEXT: imulq %r12, %rcx ; X64-NEXT: addq %rdx, %rcx -; X64-NEXT: movq %rcx, %rsi +; X64-NEXT: movq %rcx, %rbp ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload ; X64-NEXT: movq %rax, %rcx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %r14 # 8-byte Reload -; X64-NEXT: imulq %r14, %rcx -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: mulq %rbp -; X64-NEXT: movq %rax, %r13 +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: imulq %rsi, %rcx +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload +; X64-NEXT: mulq %rdi +; X64-NEXT: movq %rax, %r10 ; X64-NEXT: addq %rcx, %rdx -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload -; X64-NEXT: imulq %rbp, %rax -; X64-NEXT: addq %rdx, %rax -; X64-NEXT: addq %r10, %r13 -; X64-NEXT: adcq %rsi, %rax -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: movq %rbp, %r10 -; X64-NEXT: mulq %rbx -; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: movq %r14, %rax -; X64-NEXT: mulq %rbx -; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: movq %r14, %r13 +; X64-NEXT: imulq %rdi, %r13 +; X64-NEXT: addq %rdx, %r13 +; X64-NEXT: addq %r11, %r10 +; X64-NEXT: adcq %rbp, %r13 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: movq %rdi, %r11 +; X64-NEXT: mulq %r9 +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rax, %rdi +; X64-NEXT: movq %rsi, %rax +; X64-NEXT: movq %rsi, %r14 +; X64-NEXT: mulq %r9 +; X64-NEXT: movq %rdx, %r9 ; X64-NEXT: movq %rax, %rcx -; X64-NEXT: addq %rsi, %rcx -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: movq %r10, %rax -; X64-NEXT: mulq %r11 -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: movq %rax, %r10 -; X64-NEXT: addq %rcx, %r10 -; X64-NEXT: adcq $0, %r15 -; X64-NEXT: addq %rdi, %r15 +; X64-NEXT: addq %rbp, %rcx +; X64-NEXT: adcq $0, %r9 +; X64-NEXT: movq %r11, %rax +; X64-NEXT: movq %r12, %rbp +; X64-NEXT: mulq %rbp +; X64-NEXT: movq %rdx, %rsi +; X64-NEXT: movq %rax, %r11 +; X64-NEXT: addq %rcx, %r11 +; X64-NEXT: adcq %r9, %rsi ; X64-NEXT: sbbq %rcx, %rcx ; X64-NEXT: andl $1, %ecx ; X64-NEXT: movq %r14, %rax -; X64-NEXT: mulq %r11 -; X64-NEXT: addq %r15, %rax +; X64-NEXT: mulq %rbp +; X64-NEXT: addq %rsi, %rax ; X64-NEXT: adcq %rcx, %rdx -; X64-NEXT: addq %r13, %rax -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdx # 8-byte Folded Reload -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rbp # 8-byte Folded Reload -; X64-NEXT: adcq %r12, %r10 -; X64-NEXT: adcq %r9, %rax -; X64-NEXT: adcq %r8, %rdx -; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rbp # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload +; X64-NEXT: addq %r10, %rax +; X64-NEXT: adcq %r13, %rdx +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: adcq %r15, %r11 +; X64-NEXT: adcq %r8, %rax +; X64-NEXT: adcq %rbx, %rdx +; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rax # 8-byte Folded Reload ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdx # 8-byte Folded Reload -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: addq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload -; X64-NEXT: movq (%rsp), %rbx # 8-byte Reload +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbx # 8-byte Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rbp # 8-byte Folded Reload -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rbp # 8-byte Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rbp # 8-byte Folded Reload +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rax # 8-byte Folded Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rdx # 8-byte Folded Reload -; X64-NEXT: addq {{[0-9]+}}(%rsp), %rcx # 8-byte Folded Reload +; X64-NEXT: addq (%rsp), %rcx # 8-byte Folded Reload ; X64-NEXT: movq %rcx, %r8 -; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload -; X64-NEXT: movq %rdi, %r9 -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload +; X64-NEXT: movq %rsi, %r9 +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rbx # 8-byte Folded Reload ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rbp # 8-byte Folded Reload -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload +; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload +; X64-NEXT: adcq {{[0-9]+}}(%rsp), %r11 # 8-byte Folded Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rax # 8-byte Folded Reload ; X64-NEXT: adcq {{[0-9]+}}(%rsp), %rdx # 8-byte Folded Reload ; X64-NEXT: movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, (%rcx) -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, 8(%rcx) -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, 16(%rcx) -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, 24(%rcx) -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, 32(%rcx) -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, 40(%rcx) -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, 48(%rcx) -; X64-NEXT: movq {{[0-9]+}}(%rsp), %rdi # 8-byte Reload -; X64-NEXT: movq %rdi, 56(%rcx) +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, (%rcx) +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, 8(%rcx) +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, 16(%rcx) +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, 24(%rcx) +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, 32(%rcx) +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, 40(%rcx) +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, 48(%rcx) +; X64-NEXT: movq {{[0-9]+}}(%rsp), %rsi # 8-byte Reload +; X64-NEXT: movq %rsi, 56(%rcx) ; X64-NEXT: movq %r8, 64(%rcx) ; X64-NEXT: movq %r9, 72(%rcx) ; X64-NEXT: movq %rbx, 80(%rcx) -; X64-NEXT: movq %rsi, 88(%rcx) -; X64-NEXT: movq %rbp, 96(%rcx) -; X64-NEXT: movq %r10, 104(%rcx) +; X64-NEXT: movq %rbp, 88(%rcx) +; X64-NEXT: movq %rdi, 96(%rcx) +; X64-NEXT: movq %r11, 104(%rcx) ; X64-NEXT: movq %rax, 112(%rcx) ; X64-NEXT: movq %rdx, 120(%rcx) -; X64-NEXT: addq $360, %rsp # imm = 0x168 +; X64-NEXT: addq $352, %rsp # imm = 0x160 ; X64-NEXT: popq %rbx ; X64-NEXT: popq %r12 ; X64-NEXT: popq %r13 diff --git a/test/CodeGen/X86/mul-i256.ll b/test/CodeGen/X86/mul-i256.ll index bb2989b9298e..341484718652 100644 --- a/test/CodeGen/X86/mul-i256.ll +++ b/test/CodeGen/X86/mul-i256.ll @@ -219,7 +219,7 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 { ; X64-NEXT: .cfi_offset %r14, -24 ; X64-NEXT: .Lcfi7: ; X64-NEXT: .cfi_offset %r15, -16 -; X64-NEXT: movq %rdx, %r10 +; X64-NEXT: movq %rdx, %r9 ; X64-NEXT: movq (%rdi), %r14 ; X64-NEXT: movq 8(%rdi), %r8 ; X64-NEXT: movq 16(%rdi), %rcx @@ -230,7 +230,7 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 { ; X64-NEXT: imulq %r12, %rdi ; X64-NEXT: movq %r12, %rax ; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rax, %r9 +; X64-NEXT: movq %rax, %r10 ; X64-NEXT: addq %rdi, %rdx ; X64-NEXT: imulq %r15, %rcx ; X64-NEXT: addq %rdx, %rcx @@ -243,12 +243,12 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 { ; X64-NEXT: movq 24(%rsi), %rbx ; X64-NEXT: imulq %r14, %rbx ; X64-NEXT: addq %rdx, %rbx -; X64-NEXT: addq %r9, %r11 +; X64-NEXT: addq %r10, %r11 ; X64-NEXT: adcq %rcx, %rbx ; X64-NEXT: movq %r14, %rax ; X64-NEXT: mulq %r12 ; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: movq %rax, %r9 +; X64-NEXT: movq %rax, %r10 ; X64-NEXT: movq %r8, %rax ; X64-NEXT: mulq %r12 ; X64-NEXT: movq %rdx, %rcx @@ -260,8 +260,7 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 { ; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %r14 ; X64-NEXT: addq %rdi, %r14 -; X64-NEXT: adcq $0, %rsi -; X64-NEXT: addq %rcx, %rsi +; X64-NEXT: adcq %rcx, %rsi ; X64-NEXT: sbbq %rcx, %rcx ; X64-NEXT: andl $1, %ecx ; X64-NEXT: movq %r8, %rax @@ -270,10 +269,10 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 { ; X64-NEXT: adcq %rcx, %rdx ; X64-NEXT: addq %r11, %rax ; X64-NEXT: adcq %rbx, %rdx -; X64-NEXT: movq %r9, (%r10) -; X64-NEXT: movq %r14, 8(%r10) -; X64-NEXT: movq %rax, 16(%r10) -; X64-NEXT: movq %rdx, 24(%r10) +; X64-NEXT: movq %r10, (%r9) +; X64-NEXT: movq %r14, 8(%r9) +; X64-NEXT: movq %rax, 16(%r9) +; X64-NEXT: movq %rdx, 24(%r9) ; X64-NEXT: popq %rbx ; X64-NEXT: popq %r12 ; X64-NEXT: popq %r14 diff --git a/test/CodeGen/X86/mul-i512.ll b/test/CodeGen/X86/mul-i512.ll index d26040059e68..14fbeae52796 100644 --- a/test/CodeGen/X86/mul-i512.ll +++ b/test/CodeGen/X86/mul-i512.ll @@ -911,57 +911,57 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rax ; X64-NEXT: movq %rdx, (%rsp) # 8-byte Spill -; X64-NEXT: movq 24(%rdi), %rbp -; X64-NEXT: movq 16(%rdi), %r11 +; X64-NEXT: movq 24(%rdi), %r11 +; X64-NEXT: movq 16(%rdi), %r14 ; X64-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq (%rsi), %rdx -; X64-NEXT: movq 8(%rsi), %r8 -; X64-NEXT: movq %r11, %rax +; X64-NEXT: movq 8(%rsi), %rbp +; X64-NEXT: movq %r14, %rax ; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: mulq %rsi -; X64-NEXT: movq %rdx, %r10 +; X64-NEXT: movq %rdx, %r8 ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: movq %rbp, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %r11, %rax +; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: mulq %rsi -; X64-NEXT: movq %rsi, %r9 +; X64-NEXT: movq %rsi, %r10 ; X64-NEXT: movq %rdx, %rbx ; X64-NEXT: movq %rax, %rsi -; X64-NEXT: addq %r10, %rsi +; X64-NEXT: addq %r8, %rsi ; X64-NEXT: adcq $0, %rbx -; X64-NEXT: movq %r11, %rax -; X64-NEXT: movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: mulq %r8 +; X64-NEXT: movq %r14, %rax +; X64-NEXT: movq %r14, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: mulq %rbp ; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rax, %r12 -; X64-NEXT: addq %rsi, %r12 -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rbx, %rcx +; X64-NEXT: movq %rax, %r9 +; X64-NEXT: addq %rsi, %r9 +; X64-NEXT: adcq %rbx, %rcx ; X64-NEXT: sbbq %rbx, %rbx ; X64-NEXT: andl $1, %ebx -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: mulq %r8 +; X64-NEXT: movq %r11, %rax +; X64-NEXT: mulq %rbp +; X64-NEXT: movq %rbp, %r8 ; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rbp ; X64-NEXT: addq %rcx, %rbp ; X64-NEXT: adcq %rbx, %rsi ; X64-NEXT: xorl %ecx, %ecx -; X64-NEXT: movq %r9, %rbx +; X64-NEXT: movq %r10, %rbx ; X64-NEXT: movq %rbx, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rbx, %rax ; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rdx, %r13 ; X64-NEXT: movq %rax, %r10 -; X64-NEXT: movq %r11, %rax +; X64-NEXT: movq %r14, %rax ; X64-NEXT: mulq %rcx -; X64-NEXT: movq %rdx, %r9 -; X64-NEXT: movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: movq %rdx, %r12 +; X64-NEXT: movq %r12, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq %rax, %r15 ; X64-NEXT: movq %r15, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: addq %r10, %r15 -; X64-NEXT: adcq %r13, %r9 +; X64-NEXT: adcq %r13, %r12 ; X64-NEXT: addq %rbp, %r15 -; X64-NEXT: adcq %rsi, %r9 +; X64-NEXT: adcq %rsi, %r12 ; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq (%rdi), %r14 ; X64-NEXT: movq %r14, %rax @@ -982,8 +982,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: movq %rdx, %rbx ; X64-NEXT: addq %rsi, %rax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rbx -; X64-NEXT: addq %rbp, %rbx +; X64-NEXT: adcq %rbp, %rbx ; X64-NEXT: sbbq %rdi, %rdi ; X64-NEXT: andl $1, %edi ; X64-NEXT: movq %rcx, %rax @@ -1003,10 +1002,9 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: addq %rbp, %r10 ; X64-NEXT: adcq %rsi, %r13 ; X64-NEXT: addq -{{[0-9]+}}(%rsp), %r10 # 8-byte Folded Reload -; X64-NEXT: adcq %r12, %r13 +; X64-NEXT: adcq %r9, %r13 ; X64-NEXT: adcq $0, %r15 -; X64-NEXT: adcq $0, %r9 -; X64-NEXT: movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: adcq $0, %r12 ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload ; X64-NEXT: movq 16(%rsi), %r8 ; X64-NEXT: movq %rcx, %rax @@ -1014,22 +1012,21 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: mulq %r8 ; X64-NEXT: movq %rdx, %rdi -; X64-NEXT: movq %rax, %r12 +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload ; X64-NEXT: movq %rcx, %rax ; X64-NEXT: mulq %r8 -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: movq %rax, %rbp -; X64-NEXT: addq %rdi, %rbp -; X64-NEXT: adcq $0, %rbx +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %rax, %rbx +; X64-NEXT: addq %rdi, %rbx +; X64-NEXT: adcq $0, %rbp ; X64-NEXT: movq 24(%rsi), %rdi ; X64-NEXT: movq %r9, %rax ; X64-NEXT: mulq %rdi ; X64-NEXT: movq %rdx, %rsi -; X64-NEXT: addq %rbp, %rax +; X64-NEXT: addq %rbx, %rax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: adcq $0, %rsi -; X64-NEXT: addq %rbx, %rsi +; X64-NEXT: adcq %rbp, %rsi ; X64-NEXT: sbbq %rbp, %rbp ; X64-NEXT: andl $1, %ebp ; X64-NEXT: movq %rcx, %rax @@ -1047,13 +1044,12 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: adcq %rdx, %r14 ; X64-NEXT: addq %r9, %r11 ; X64-NEXT: adcq %rbx, %r14 -; X64-NEXT: addq %r10, %r12 -; X64-NEXT: movq %r12, -{{[0-9]+}}(%rsp) # 8-byte Spill +; X64-NEXT: addq %r10, -{{[0-9]+}}(%rsp) # 8-byte Folded Spill ; X64-NEXT: adcq %r13, -{{[0-9]+}}(%rsp) # 8-byte Folded Spill ; X64-NEXT: adcq $0, %r11 ; X64-NEXT: adcq $0, %r14 ; X64-NEXT: addq %r15, %r11 -; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %r14 # 8-byte Folded Reload +; X64-NEXT: adcq %r12, %r14 ; X64-NEXT: adcq $0, %rcx ; X64-NEXT: movq %rcx, %r13 ; X64-NEXT: sbbq %r9, %r9 @@ -1075,8 +1071,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: addq %rbx, %rax ; X64-NEXT: movq %rax, %rbx -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rsi, %rcx +; X64-NEXT: adcq %rsi, %rcx ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi ; X64-NEXT: movq %r10, %rax @@ -1102,7 +1097,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: imulq %rsi, %rdi ; X64-NEXT: movq %rsi, %rax ; X64-NEXT: mulq %r8 -; X64-NEXT: movq %rax, %r11 +; X64-NEXT: movq %rax, %r10 ; X64-NEXT: addq %rdi, %rdx ; X64-NEXT: movq 40(%rcx), %r9 ; X64-NEXT: imulq %r9, %r8 @@ -1110,60 +1105,58 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: movq 48(%rcx), %rax ; X64-NEXT: movq %rcx, %rbx ; X64-NEXT: movq %rax, %rdi +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r11 # 8-byte Reload +; X64-NEXT: imulq %r11, %rdi ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx # 8-byte Reload -; X64-NEXT: imulq %rcx, %rdi -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rbp # 8-byte Reload -; X64-NEXT: mulq %rbp +; X64-NEXT: mulq %rcx ; X64-NEXT: movq %rax, %r12 ; X64-NEXT: addq %rdi, %rdx ; X64-NEXT: movq 56(%rbx), %rbx -; X64-NEXT: imulq %rbp, %rbx +; X64-NEXT: imulq %rcx, %rbx ; X64-NEXT: addq %rdx, %rbx -; X64-NEXT: addq %r11, %r12 +; X64-NEXT: addq %r10, %r12 ; X64-NEXT: adcq %r8, %rbx -; X64-NEXT: movq %rbp, %rax -; X64-NEXT: movq %rbp, %r8 +; X64-NEXT: movq %rcx, %rax ; X64-NEXT: mulq %rsi ; X64-NEXT: movq %rdx, %rdi ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill -; X64-NEXT: movq %rcx, %rax +; X64-NEXT: movq %r11, %rax ; X64-NEXT: mulq %rsi ; X64-NEXT: movq %rdx, %rsi ; X64-NEXT: movq %rax, %rbp ; X64-NEXT: addq %rdi, %rbp ; X64-NEXT: adcq $0, %rsi -; X64-NEXT: movq %r8, %rax +; X64-NEXT: movq %rcx, %rax ; X64-NEXT: mulq %r9 ; X64-NEXT: movq %rdx, %rdi -; X64-NEXT: movq %rax, %r11 -; X64-NEXT: addq %rbp, %r11 -; X64-NEXT: adcq $0, %rdi -; X64-NEXT: addq %rsi, %rdi +; X64-NEXT: movq %rax, %r15 +; X64-NEXT: addq %rbp, %r15 +; X64-NEXT: adcq %rsi, %rdi ; X64-NEXT: sbbq %rsi, %rsi ; X64-NEXT: andl $1, %esi -; X64-NEXT: movq %rcx, %rax +; X64-NEXT: movq %r11, %rax ; X64-NEXT: mulq %r9 -; X64-NEXT: movq %rdx, %r14 -; X64-NEXT: movq %rax, %r15 -; X64-NEXT: addq %rdi, %r15 -; X64-NEXT: adcq %rsi, %r14 -; X64-NEXT: addq %r12, %r15 -; X64-NEXT: adcq %rbx, %r14 +; X64-NEXT: movq %rdx, %r11 +; X64-NEXT: movq %rax, %r14 +; X64-NEXT: addq %rdi, %r14 +; X64-NEXT: adcq %rsi, %r11 +; X64-NEXT: addq %r12, %r14 +; X64-NEXT: adcq %rbx, %r11 ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdx # 8-byte Reload ; X64-NEXT: movq 56(%rdx), %rcx -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8 # 8-byte Reload -; X64-NEXT: imulq %r8, %rcx -; X64-NEXT: movq 48(%rdx), %rbp -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: movq %r8, %rax -; X64-NEXT: mulq %rbp +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r10 # 8-byte Reload +; X64-NEXT: imulq %r10, %rcx +; X64-NEXT: movq 48(%rdx), %rbx +; X64-NEXT: movq %rdx, %rbp +; X64-NEXT: movq %r10, %rax +; X64-NEXT: mulq %rbx ; X64-NEXT: movq %rax, %rsi ; X64-NEXT: addq %rcx, %rdx -; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r10 # 8-byte Reload -; X64-NEXT: imulq %r10, %rbp -; X64-NEXT: addq %rdx, %rbp -; X64-NEXT: movq 32(%rbx), %rdi -; X64-NEXT: movq 40(%rbx), %r12 +; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8 # 8-byte Reload +; X64-NEXT: imulq %r8, %rbx +; X64-NEXT: addq %rdx, %rbx +; X64-NEXT: movq 32(%rbp), %rdi +; X64-NEXT: movq 40(%rbp), %r12 ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload ; X64-NEXT: movq %rax, %rcx ; X64-NEXT: imulq %r12, %rcx @@ -1174,36 +1167,35 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind { ; X64-NEXT: imulq %rdi, %r13 ; X64-NEXT: addq %rdx, %r13 ; X64-NEXT: addq %rsi, %r9 -; X64-NEXT: adcq %rbp, %r13 +; X64-NEXT: adcq %rbx, %r13 ; X64-NEXT: movq %rdi, %rax -; X64-NEXT: mulq %r8 +; X64-NEXT: mulq %r10 ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rax, %rsi ; X64-NEXT: movq %r12, %rax -; X64-NEXT: mulq %r8 +; X64-NEXT: mulq %r10 ; X64-NEXT: movq %rdx, %rbx ; X64-NEXT: movq %rax, %rbp ; X64-NEXT: addq %rcx, %rbp ; X64-NEXT: adcq $0, %rbx ; X64-NEXT: movq %rdi, %rax -; X64-NEXT: mulq %r10 +; X64-NEXT: mulq %r8 ; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rax, %rdi ; X64-NEXT: addq %rbp, %rdi -; X64-NEXT: adcq $0, %rcx -; X64-NEXT: addq %rbx, %rcx -; X64-NEXT: sbbq %rbp, %rbp -; X64-NEXT: andl $1, %ebp +; X64-NEXT: adcq %rbx, %rcx +; X64-NEXT: sbbq %rbx, %rbx +; X64-NEXT: andl $1, %ebx ; X64-NEXT: movq %r12, %rax -; X64-NEXT: mulq %r10 +; X64-NEXT: mulq %r8 ; X64-NEXT: addq %rcx, %rax -; X64-NEXT: adcq %rbp, %rdx +; X64-NEXT: adcq %rbx, %rdx ; X64-NEXT: addq %r9, %rax ; X64-NEXT: adcq %r13, %rdx ; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload -; X64-NEXT: adcq %r11, %rdi -; X64-NEXT: adcq %r15, %rax -; X64-NEXT: adcq %r14, %rdx +; X64-NEXT: adcq %r15, %rdi +; X64-NEXT: adcq %r14, %rax +; X64-NEXT: adcq %r11, %rdx ; X64-NEXT: addq -{{[0-9]+}}(%rsp), %rsi # 8-byte Folded Reload ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rdi # 8-byte Folded Reload ; X64-NEXT: adcq -{{[0-9]+}}(%rsp), %rax # 8-byte Folded Reload diff --git a/test/CodeGen/X86/patchpoint-invoke.ll b/test/CodeGen/X86/patchpoint-invoke.ll index c6dff3b78f16..9270bf2b06ba 100644 --- a/test/CodeGen/X86/patchpoint-invoke.ll +++ b/test/CodeGen/X86/patchpoint-invoke.ll @@ -45,7 +45,7 @@ threw: ; Verify that the stackmap section got emitted: ; CHECK-LABEL: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions diff --git a/test/CodeGen/X86/pr14657.ll b/test/CodeGen/X86/pr14657.ll deleted file mode 100644 index cc7d3e068d4a..000000000000 --- a/test/CodeGen/X86/pr14657.ll +++ /dev/null @@ -1,325 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 - -; PR14657 - avoid truncation/extension of comparison results - -@da = common global [1024 x float] zeroinitializer, align 32 -@db = common global [1024 x float] zeroinitializer, align 32 -@dc = common global [1024 x float] zeroinitializer, align 32 -@dd = common global [1024 x float] zeroinitializer, align 32 -@dj = common global [1024 x i32] zeroinitializer, align 32 - -define void @_Z9example25v() nounwind uwtable noinline ssp { -; SSE2-LABEL: _Z9example25v: -; SSE2: # BB#0: # %vector.ph -; SSE2-NEXT: movq $-4096, %rax # imm = 0xF000 -; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [1,1,1,1] -; SSE2-NEXT: .p2align 4, 0x90 -; SSE2-NEXT: .LBB0_1: # %vector.body -; SSE2-NEXT: # =>This Inner Loop Header: Depth=1 -; SSE2-NEXT: movaps da+4096(%rax), %xmm1 -; SSE2-NEXT: movaps da+4112(%rax), %xmm2 -; SSE2-NEXT: cmpltps db+4112(%rax), %xmm2 -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE2-NEXT: cmpltps db+4096(%rax), %xmm1 -; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] -; SSE2-NEXT: psllw $15, %xmm1 -; SSE2-NEXT: psraw $15, %xmm1 -; SSE2-NEXT: movaps dc+4096(%rax), %xmm2 -; SSE2-NEXT: movaps dc+4112(%rax), %xmm3 -; SSE2-NEXT: cmpltps dd+4112(%rax), %xmm3 -; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE2-NEXT: cmpltps dd+4096(%rax), %xmm2 -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] -; SSE2-NEXT: psllw $15, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: pand %xmm1, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm1 -; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] -; SSE2-NEXT: pand %xmm0, %xmm1 -; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] -; SSE2-NEXT: pand %xmm0, %xmm2 -; SSE2-NEXT: movdqa %xmm2, dj+4112(%rax) -; SSE2-NEXT: movdqa %xmm1, dj+4096(%rax) -; SSE2-NEXT: addq $32, %rax -; SSE2-NEXT: jne .LBB0_1 -; SSE2-NEXT: # BB#2: # %for.end -; SSE2-NEXT: retq -; -; SSE41-LABEL: _Z9example25v: -; SSE41: # BB#0: # %vector.ph -; SSE41-NEXT: movq $-4096, %rax # imm = 0xF000 -; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] -; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1,1,1,1] -; SSE41-NEXT: .p2align 4, 0x90 -; SSE41-NEXT: .LBB0_1: # %vector.body -; SSE41-NEXT: # =>This Inner Loop Header: Depth=1 -; SSE41-NEXT: movaps da+4096(%rax), %xmm2 -; SSE41-NEXT: movaps da+4112(%rax), %xmm3 -; SSE41-NEXT: cmpltps db+4112(%rax), %xmm3 -; SSE41-NEXT: pshufb %xmm0, %xmm3 -; SSE41-NEXT: cmpltps db+4096(%rax), %xmm2 -; SSE41-NEXT: pshufb %xmm0, %xmm2 -; SSE41-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] -; SSE41-NEXT: psllw $15, %xmm2 -; SSE41-NEXT: psraw $15, %xmm2 -; SSE41-NEXT: movaps dc+4096(%rax), %xmm3 -; SSE41-NEXT: movaps dc+4112(%rax), %xmm4 -; SSE41-NEXT: cmpltps dd+4112(%rax), %xmm4 -; SSE41-NEXT: pshufb %xmm0, %xmm4 -; SSE41-NEXT: cmpltps dd+4096(%rax), %xmm3 -; SSE41-NEXT: pshufb %xmm0, %xmm3 -; SSE41-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0] -; SSE41-NEXT: psllw $15, %xmm3 -; SSE41-NEXT: psraw $15, %xmm3 -; SSE41-NEXT: pand %xmm2, %xmm3 -; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero -; SSE41-NEXT: pand %xmm1, %xmm2 -; SSE41-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] -; SSE41-NEXT: pand %xmm1, %xmm3 -; SSE41-NEXT: movdqa %xmm3, dj+4112(%rax) -; SSE41-NEXT: movdqa %xmm2, dj+4096(%rax) -; SSE41-NEXT: addq $32, %rax -; SSE41-NEXT: jne .LBB0_1 -; SSE41-NEXT: # BB#2: # %for.end -; SSE41-NEXT: retq -; -; AVX1-LABEL: _Z9example25v: -; AVX1: # BB#0: # %vector.ph -; AVX1-NEXT: movq $-4096, %rax # imm = 0xF000 -; AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [1,1,1,1,1,1,1,1] -; AVX1-NEXT: .p2align 4, 0x90 -; AVX1-NEXT: .LBB0_1: # %vector.body -; AVX1-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX1-NEXT: vmovups da+4096(%rax), %ymm1 -; AVX1-NEXT: vcmpltps db+4096(%rax), %ymm1, %ymm1 -; AVX1-NEXT: vmovups dc+4096(%rax), %ymm2 -; AVX1-NEXT: vcmpltps dd+4096(%rax), %ymm2, %ymm2 -; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1 -; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm1 -; AVX1-NEXT: vmovups %ymm1, dj+4096(%rax) -; AVX1-NEXT: addq $32, %rax -; AVX1-NEXT: jne .LBB0_1 -; AVX1-NEXT: # BB#2: # %for.end -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: _Z9example25v: -; AVX2: # BB#0: # %vector.ph -; AVX2-NEXT: movq $-4096, %rax # imm = 0xF000 -; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm0 -; AVX2-NEXT: .p2align 4, 0x90 -; AVX2-NEXT: .LBB0_1: # %vector.body -; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX2-NEXT: vmovups da+4096(%rax), %ymm1 -; AVX2-NEXT: vcmpltps db+4096(%rax), %ymm1, %ymm1 -; AVX2-NEXT: vmovups dc+4096(%rax), %ymm2 -; AVX2-NEXT: vcmpltps dd+4096(%rax), %ymm2, %ymm2 -; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1 -; AVX2-NEXT: vandps %ymm0, %ymm1, %ymm1 -; AVX2-NEXT: vmovups %ymm1, dj+4096(%rax) -; AVX2-NEXT: addq $32, %rax -; AVX2-NEXT: jne .LBB0_1 -; AVX2-NEXT: # BB#2: # %for.end -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -vector.ph: - br label %vector.body - -vector.body: ; preds = %vector.body, %vector.ph - %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] - %0 = getelementptr inbounds [1024 x float], [1024 x float]* @da, i64 0, i64 %index - %1 = bitcast float* %0 to <8 x float>* - %2 = load <8 x float>, <8 x float>* %1, align 16 - %3 = getelementptr inbounds [1024 x float], [1024 x float]* @db, i64 0, i64 %index - %4 = bitcast float* %3 to <8 x float>* - %5 = load <8 x float>, <8 x float>* %4, align 16 - %6 = fcmp olt <8 x float> %2, %5 - %7 = getelementptr inbounds [1024 x float], [1024 x float]* @dc, i64 0, i64 %index - %8 = bitcast float* %7 to <8 x float>* - %9 = load <8 x float>, <8 x float>* %8, align 16 - %10 = getelementptr inbounds [1024 x float], [1024 x float]* @dd, i64 0, i64 %index - %11 = bitcast float* %10 to <8 x float>* - %12 = load <8 x float>, <8 x float>* %11, align 16 - %13 = fcmp olt <8 x float> %9, %12 - %14 = and <8 x i1> %6, %13 - %15 = zext <8 x i1> %14 to <8 x i32> - %16 = getelementptr inbounds [1024 x i32], [1024 x i32]* @dj, i64 0, i64 %index - %17 = bitcast i32* %16 to <8 x i32>* - store <8 x i32> %15, <8 x i32>* %17, align 16 - %index.next = add i64 %index, 8 - %18 = icmp eq i64 %index.next, 1024 - br i1 %18, label %for.end, label %vector.body - -for.end: ; preds = %vector.body - ret void -} - -define void @_Z9example24ss(i16 signext %x, i16 signext %y) nounwind uwtable noinline ssp { -; SSE2-LABEL: _Z9example24ss: -; SSE2: # BB#0: # %vector.ph -; SSE2-NEXT: movd %edi, %xmm0 -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] -; SSE2-NEXT: movd %esi, %xmm1 -; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] -; SSE2-NEXT: movq $-4096, %rax # imm = 0xF000 -; SSE2-NEXT: .p2align 4, 0x90 -; SSE2-NEXT: .LBB1_1: # %vector.body -; SSE2-NEXT: # =>This Inner Loop Header: Depth=1 -; SSE2-NEXT: movaps da+4096(%rax), %xmm2 -; SSE2-NEXT: movaps da+4112(%rax), %xmm3 -; SSE2-NEXT: cmpltps db+4112(%rax), %xmm3 -; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] -; SSE2-NEXT: cmpltps db+4096(%rax), %xmm2 -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] -; SSE2-NEXT: movdqa %xmm0, %xmm3 -; SSE2-NEXT: pand %xmm2, %xmm3 -; SSE2-NEXT: pandn %xmm1, %xmm2 -; SSE2-NEXT: por %xmm3, %xmm2 -; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] -; SSE2-NEXT: psrad $16, %xmm3 -; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7] -; SSE2-NEXT: psrad $16, %xmm2 -; SSE2-NEXT: movdqa %xmm2, dj+4112(%rax) -; SSE2-NEXT: movdqa %xmm3, dj+4096(%rax) -; SSE2-NEXT: addq $32, %rax -; SSE2-NEXT: jne .LBB1_1 -; SSE2-NEXT: # BB#2: # %for.end -; SSE2-NEXT: retq -; -; SSE41-LABEL: _Z9example24ss: -; SSE41: # BB#0: # %vector.ph -; SSE41-NEXT: movd %edi, %xmm0 -; SSE41-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] -; SSE41-NEXT: movd %esi, %xmm1 -; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] -; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] -; SSE41-NEXT: movq $-4096, %rax # imm = 0xF000 -; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] -; SSE41-NEXT: .p2align 4, 0x90 -; SSE41-NEXT: .LBB1_1: # %vector.body -; SSE41-NEXT: # =>This Inner Loop Header: Depth=1 -; SSE41-NEXT: movaps da+4096(%rax), %xmm3 -; SSE41-NEXT: movaps da+4112(%rax), %xmm4 -; SSE41-NEXT: cmpltps db+4112(%rax), %xmm4 -; SSE41-NEXT: pshufb %xmm2, %xmm4 -; SSE41-NEXT: cmpltps db+4096(%rax), %xmm3 -; SSE41-NEXT: pshufb %xmm2, %xmm3 -; SSE41-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0] -; SSE41-NEXT: movdqa %xmm0, %xmm4 -; SSE41-NEXT: pand %xmm3, %xmm4 -; SSE41-NEXT: pandn %xmm1, %xmm3 -; SSE41-NEXT: por %xmm4, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[2,3,0,1] -; SSE41-NEXT: pmovsxwd %xmm4, %xmm4 -; SSE41-NEXT: pmovsxwd %xmm3, %xmm3 -; SSE41-NEXT: movdqa %xmm3, dj+4096(%rax) -; SSE41-NEXT: movdqa %xmm4, dj+4112(%rax) -; SSE41-NEXT: addq $32, %rax -; SSE41-NEXT: jne .LBB1_1 -; SSE41-NEXT: # BB#2: # %for.end -; SSE41-NEXT: retq -; -; AVX1-LABEL: _Z9example24ss: -; AVX1: # BB#0: # %vector.ph -; AVX1-NEXT: vmovd %edi, %xmm0 -; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] -; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] -; AVX1-NEXT: vmovd %esi, %xmm1 -; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] -; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] -; AVX1-NEXT: movq $-4096, %rax # imm = 0xF000 -; AVX1-NEXT: .p2align 4, 0x90 -; AVX1-NEXT: .LBB1_1: # %vector.body -; AVX1-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX1-NEXT: vmovups da+4096(%rax), %ymm2 -; AVX1-NEXT: vcmpltps db+4096(%rax), %ymm2, %ymm2 -; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3 -; AVX1-NEXT: vpacksswb %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpandn %xmm1, %xmm2, %xmm3 -; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm2 -; AVX1-NEXT: vpor %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpmovsxwd %xmm2, %xmm3 -; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] -; AVX1-NEXT: vpmovsxwd %xmm2, %xmm2 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 -; AVX1-NEXT: vmovups %ymm2, dj+4096(%rax) -; AVX1-NEXT: addq $32, %rax -; AVX1-NEXT: jne .LBB1_1 -; AVX1-NEXT: # BB#2: # %for.end -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: _Z9example24ss: -; AVX2: # BB#0: # %vector.ph -; AVX2-NEXT: vmovd %edi, %xmm0 -; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0 -; AVX2-NEXT: vmovd %esi, %xmm1 -; AVX2-NEXT: vpbroadcastw %xmm1, %xmm1 -; AVX2-NEXT: movq $-4096, %rax # imm = 0xF000 -; AVX2-NEXT: .p2align 4, 0x90 -; AVX2-NEXT: .LBB1_1: # %vector.body -; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX2-NEXT: vmovups da+4096(%rax), %ymm2 -; AVX2-NEXT: vcmpltps db+4096(%rax), %ymm2, %ymm2 -; AVX2-NEXT: vextractf128 $1, %ymm2, %xmm3 -; AVX2-NEXT: vpacksswb %xmm3, %xmm2, %xmm2 -; AVX2-NEXT: vpandn %xmm1, %xmm2, %xmm3 -; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm2 -; AVX2-NEXT: vpor %xmm3, %xmm2, %xmm2 -; AVX2-NEXT: vpmovsxwd %xmm2, %ymm2 -; AVX2-NEXT: vmovdqu %ymm2, dj+4096(%rax) -; AVX2-NEXT: addq $32, %rax -; AVX2-NEXT: jne .LBB1_1 -; AVX2-NEXT: # BB#2: # %for.end -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -vector.ph: - %0 = insertelement <8 x i16> undef, i16 %x, i32 0 - %broadcast11 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer - %1 = insertelement <8 x i16> undef, i16 %y, i32 0 - %broadcast12 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> zeroinitializer - br label %vector.body - -vector.body: ; preds = %vector.body, %vector.ph - %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] - %2 = getelementptr inbounds [1024 x float], [1024 x float]* @da, i64 0, i64 %index - %3 = bitcast float* %2 to <8 x float>* - %4 = load <8 x float>, <8 x float>* %3, align 16 - %5 = getelementptr inbounds [1024 x float], [1024 x float]* @db, i64 0, i64 %index - %6 = bitcast float* %5 to <8 x float>* - %7 = load <8 x float>, <8 x float>* %6, align 16 - %8 = fcmp olt <8 x float> %4, %7 - %9 = select <8 x i1> %8, <8 x i16> %broadcast11, <8 x i16> %broadcast12 - %10 = sext <8 x i16> %9 to <8 x i32> - %11 = getelementptr inbounds [1024 x i32], [1024 x i32]* @dj, i64 0, i64 %index - %12 = bitcast i32* %11 to <8 x i32>* - store <8 x i32> %10, <8 x i32>* %12, align 16 - %index.next = add i64 %index, 8 - %13 = icmp eq i64 %index.next, 1024 - br i1 %13, label %for.end, label %vector.body - -for.end: ; preds = %vector.body - ret void -} diff --git a/test/CodeGen/X86/pr28129.ll b/test/CodeGen/X86/pr28129.ll new file mode 100644 index 000000000000..a155f71f79c3 --- /dev/null +++ b/test/CodeGen/X86/pr28129.ll @@ -0,0 +1,87 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64 + +define <4 x double> @cmp4f64_domain(<4 x double> %a) { +; X86-LABEL: cmp4f64_domain: +; X86: # BB#0: +; X86-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; X86-NEXT: retl +; +; X64-LABEL: cmp4f64_domain: +; X64: # BB#0: +; X64-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; X64-NEXT: retq + %cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer + %sext = sext <4 x i1> %cmp to <4 x i64> + %mask = bitcast <4 x i64> %sext to <4 x double> + %add = fadd <4 x double> %a, %mask + ret <4 x double> %add +} + +define <4 x double> @cmp4f64_domain_optsize(<4 x double> %a) optsize { +; X86-LABEL: cmp4f64_domain_optsize: +; X86: # BB#0: +; X86-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; X86-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; X86-NEXT: retl +; +; X64-LABEL: cmp4f64_domain_optsize: +; X64: # BB#0: +; X64-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; X64-NEXT: vaddpd %ymm1, %ymm0, %ymm0 +; X64-NEXT: retq + %cmp = fcmp oeq <4 x double> zeroinitializer, zeroinitializer + %sext = sext <4 x i1> %cmp to <4 x i64> + %mask = bitcast <4 x i64> %sext to <4 x double> + %add = fadd <4 x double> %a, %mask + ret <4 x double> %add +} + +define <8 x float> @cmp8f32_domain(<8 x float> %a) { +; X86-LABEL: cmp8f32_domain: +; X86: # BB#0: +; X86-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0 +; X86-NEXT: retl +; +; X64-LABEL: cmp8f32_domain: +; X64: # BB#0: +; X64-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0 +; X64-NEXT: retq + %cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer + %sext = sext <8 x i1> %cmp to <8 x i32> + %mask = bitcast <8 x i32> %sext to <8 x float> + %add = fadd <8 x float> %a, %mask + ret <8 x float> %add +} + +define <8 x float> @cmp8f32_domain_optsize(<8 x float> %a) optsize { +; X86-LABEL: cmp8f32_domain_optsize: +; X86: # BB#0: +; X86-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; X86-NEXT: vaddps %ymm1, %ymm0, %ymm0 +; X86-NEXT: retl +; +; X64-LABEL: cmp8f32_domain_optsize: +; X64: # BB#0: +; X64-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; X64-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 +; X64-NEXT: vaddps %ymm1, %ymm0, %ymm0 +; X64-NEXT: retq + %cmp = fcmp oeq <8 x float> zeroinitializer, zeroinitializer + %sext = sext <8 x i1> %cmp to <8 x i32> + %mask = bitcast <8 x i32> %sext to <8 x float> + %add = fadd <8 x float> %a, %mask + ret <8 x float> %add +} diff --git a/test/CodeGen/X86/pr31088.ll b/test/CodeGen/X86/pr31088.ll new file mode 100644 index 000000000000..0dd8eb0ece85 --- /dev/null +++ b/test/CodeGen/X86/pr31088.ll @@ -0,0 +1,162 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+f16c | FileCheck %s --check-prefix=F16C + +define <1 x half> @ir_fadd_v1f16(<1 x half> %arg0, <1 x half> %arg1) nounwind { +; X86-LABEL: ir_fadd_v1f16: +; X86: # BB#0: +; X86-NEXT: subl $28, %esp +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: calll __gnu_f2h_ieee +; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: calll __gnu_h2f_ieee +; X86-NEXT: fstpt {{[0-9]+}}(%esp) # 10-byte Folded Spill +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: calll __gnu_f2h_ieee +; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: fldt {{[0-9]+}}(%esp) # 10-byte Folded Reload +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: calll __gnu_h2f_ieee +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: addss {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: movss %xmm0, {{[0-9]+}}(%esp) +; X86-NEXT: flds {{[0-9]+}}(%esp) +; X86-NEXT: addl $28, %esp +; X86-NEXT: retl +; +; X64-LABEL: ir_fadd_v1f16: +; X64: # BB#0: +; X64-NEXT: pushq %rax +; X64-NEXT: movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill +; X64-NEXT: movaps %xmm1, %xmm0 +; X64-NEXT: callq __gnu_f2h_ieee +; X64-NEXT: movzwl %ax, %edi +; X64-NEXT: callq __gnu_h2f_ieee +; X64-NEXT: movss %xmm0, (%rsp) # 4-byte Spill +; X64-NEXT: movss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload +; X64-NEXT: # xmm0 = mem[0],zero,zero,zero +; X64-NEXT: callq __gnu_f2h_ieee +; X64-NEXT: movzwl %ax, %edi +; X64-NEXT: callq __gnu_h2f_ieee +; X64-NEXT: addss (%rsp), %xmm0 # 4-byte Folded Reload +; X64-NEXT: popq %rax +; X64-NEXT: retq +; +; F16C-LABEL: ir_fadd_v1f16: +; F16C: # BB#0: +; F16C-NEXT: vcvtps2ph $4, %xmm1, %xmm1 +; F16C-NEXT: vcvtph2ps %xmm1, %xmm1 +; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; F16C-NEXT: vcvtph2ps %xmm0, %xmm0 +; F16C-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; F16C-NEXT: retq + %retval = fadd <1 x half> %arg0, %arg1 + ret <1 x half> %retval +} + +define <2 x half> @ir_fadd_v2f16(<2 x half> %arg0, <2 x half> %arg1) nounwind { +; X86-LABEL: ir_fadd_v2f16: +; X86: # BB#0: +; X86-NEXT: subl $64, %esp +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: calll __gnu_f2h_ieee +; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: calll __gnu_h2f_ieee +; X86-NEXT: fstpt {{[0-9]+}}(%esp) # 10-byte Folded Spill +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: calll __gnu_f2h_ieee +; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: calll __gnu_h2f_ieee +; X86-NEXT: fstpt {{[0-9]+}}(%esp) # 10-byte Folded Spill +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: calll __gnu_f2h_ieee +; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: calll __gnu_h2f_ieee +; X86-NEXT: fstpt {{[0-9]+}}(%esp) # 10-byte Folded Spill +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: calll __gnu_f2h_ieee +; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: fldt {{[0-9]+}}(%esp) # 10-byte Folded Reload +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: fldt {{[0-9]+}}(%esp) # 10-byte Folded Reload +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: fldt {{[0-9]+}}(%esp) # 10-byte Folded Reload +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: calll __gnu_h2f_ieee +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X86-NEXT: addss {{[0-9]+}}(%esp), %xmm1 +; X86-NEXT: addss {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: movss %xmm0, {{[0-9]+}}(%esp) +; X86-NEXT: movss %xmm1, {{[0-9]+}}(%esp) +; X86-NEXT: flds {{[0-9]+}}(%esp) +; X86-NEXT: flds {{[0-9]+}}(%esp) +; X86-NEXT: addl $64, %esp +; X86-NEXT: retl +; +; X64-LABEL: ir_fadd_v2f16: +; X64: # BB#0: +; X64-NEXT: subq $24, %rsp +; X64-NEXT: movss %xmm2, {{[0-9]+}}(%rsp) # 4-byte Spill +; X64-NEXT: movss %xmm1, {{[0-9]+}}(%rsp) # 4-byte Spill +; X64-NEXT: movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill +; X64-NEXT: movaps %xmm3, %xmm0 +; X64-NEXT: callq __gnu_f2h_ieee +; X64-NEXT: movzwl %ax, %edi +; X64-NEXT: callq __gnu_h2f_ieee +; X64-NEXT: movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill +; X64-NEXT: movss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload +; X64-NEXT: # xmm0 = mem[0],zero,zero,zero +; X64-NEXT: callq __gnu_f2h_ieee +; X64-NEXT: movzwl %ax, %edi +; X64-NEXT: callq __gnu_h2f_ieee +; X64-NEXT: movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill +; X64-NEXT: movss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload +; X64-NEXT: # xmm0 = mem[0],zero,zero,zero +; X64-NEXT: callq __gnu_f2h_ieee +; X64-NEXT: movzwl %ax, %edi +; X64-NEXT: callq __gnu_h2f_ieee +; X64-NEXT: movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill +; X64-NEXT: movss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload +; X64-NEXT: # xmm0 = mem[0],zero,zero,zero +; X64-NEXT: callq __gnu_f2h_ieee +; X64-NEXT: movzwl %ax, %edi +; X64-NEXT: callq __gnu_h2f_ieee +; X64-NEXT: addss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Folded Reload +; X64-NEXT: movss {{[0-9]+}}(%rsp), %xmm1 # 4-byte Reload +; X64-NEXT: # xmm1 = mem[0],zero,zero,zero +; X64-NEXT: addss {{[0-9]+}}(%rsp), %xmm1 # 4-byte Folded Reload +; X64-NEXT: addq $24, %rsp +; X64-NEXT: retq +; +; F16C-LABEL: ir_fadd_v2f16: +; F16C: # BB#0: +; F16C-NEXT: vcvtps2ph $4, %xmm3, %xmm3 +; F16C-NEXT: vcvtph2ps %xmm3, %xmm3 +; F16C-NEXT: vcvtps2ph $4, %xmm1, %xmm1 +; F16C-NEXT: vcvtph2ps %xmm1, %xmm1 +; F16C-NEXT: vcvtps2ph $4, %xmm2, %xmm2 +; F16C-NEXT: vcvtph2ps %xmm2, %xmm2 +; F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; F16C-NEXT: vcvtph2ps %xmm0, %xmm0 +; F16C-NEXT: vaddss %xmm2, %xmm0, %xmm0 +; F16C-NEXT: vaddss %xmm3, %xmm1, %xmm1 +; F16C-NEXT: retq + %retval = fadd <2 x half> %arg0, %arg1 + ret <2 x half> %retval +} diff --git a/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll b/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll index 964037ea80af..20387ccd6b7a 100644 --- a/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll @@ -2318,6 +2318,22 @@ define <2 x double> @test_mm_set_pd(double %a0, double %a1) nounwind { ret <2 x double> %res1 } +define <2 x double> @test_mm_set_pd1(double %a0) nounwind { +; X32-LABEL: test_mm_set_pd1: +; X32: # BB#0: +; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; X32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0] +; X32-NEXT: retl +; +; X64-LABEL: test_mm_set_pd1: +; X64: # BB#0: +; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0] +; X64-NEXT: retq + %res0 = insertelement <2 x double> undef, double %a0, i32 0 + %res1 = insertelement <2 x double> %res0, double %a0, i32 1 + ret <2 x double> %res1 +} + define <2 x double> @test_mm_set_sd(double %a0) nounwind { ; X32-LABEL: test_mm_set_sd: ; X32: # BB#0: diff --git a/test/CodeGen/X86/stack-protector-dbginfo.ll b/test/CodeGen/X86/stack-protector-dbginfo.ll index 8413b8ef82cb..a685ed1f6784 100644 --- a/test/CodeGen/X86/stack-protector-dbginfo.ll +++ b/test/CodeGen/X86/stack-protector-dbginfo.ll @@ -49,7 +49,7 @@ attributes #0 = { sspreq } !22 = !{i64* getelementptr inbounds ({ i64, [56 x i8] }, { i64, [56 x i8] }* @a, i32 0, i32 0)} !23 = !DILocalVariable(name: "p2", line: 12, arg: 2, scope: !24, file: !10, type: !32) !24 = distinct !DISubprogram(name: "min<unsigned long long>", linkageName: "_ZN3__13minIyEERKT_S3_RS1_", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 12, file: !1, scope: !25, type: !27, templateParams: !33, variables: !35) -!25 = !DINamespace(name: "__1", line: 1, file: !26, scope: null) +!25 = !DINamespace(name: "__1", scope: null) !26 = !DIFile(filename: "main.cpp", directory: "/Users/matt/ryan_bug") !27 = !DISubroutineType(types: !28) !28 = !{!29, !29, !32} diff --git a/test/CodeGen/X86/stackmap-fast-isel.ll b/test/CodeGen/X86/stackmap-fast-isel.ll index 7afe966b77aa..ae10a37756bc 100644 --- a/test/CodeGen/X86/stackmap-fast-isel.ll +++ b/test/CodeGen/X86/stackmap-fast-isel.ll @@ -4,7 +4,7 @@ ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -42,62 +42,86 @@ ; CHECK-NEXT: .short 12 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 65536 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 2000000000 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 2147483647 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; LargeConstant at index 0 ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; LargeConstant at index 1 ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 1 ; LargeConstant at index 2 ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 2 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 @@ -115,7 +139,9 @@ entry: ; CHECK-NEXT: .short 1 ; Loc 0: SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 33 @@ -133,8 +159,10 @@ define void @liveConstant() { ; CHECK-NEXT: .short 1 ; Loc 0: Direct RBP - ofs ; CHECK-NEXT: .byte 2 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long define void @directFrameIdx() { diff --git a/test/CodeGen/X86/stackmap-large-constants.ll b/test/CodeGen/X86/stackmap-large-constants.ll index 99a2c11828e0..7de430b5393a 100644 --- a/test/CodeGen/X86/stackmap-large-constants.ll +++ b/test/CodeGen/X86/stackmap-large-constants.ll @@ -3,7 +3,7 @@ ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; version -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; reserved ; CHECK-NEXT: .byte 0 ; reserved @@ -38,12 +38,17 @@ ; ConstantIndex ; CHECK-NEXT: .byte 5 ; reserved -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; size +; CHECK-NEXT: .short 8 ; Dwarf RegNum ; CHECK-NEXT: .short 0 +; reserved +; CHECK-NEXT: .short 0 ; Offset ; CHECK-NEXT: .long 0 ; padding +; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .short 0 ; NumLiveOuts ; CHECK-NEXT: .short 0 @@ -68,12 +73,17 @@ define void @foo() { ; ConstantIndex ; CHECK-NEXT: .byte 5 ; reserved -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; size +; CHECK-NEXT: .short 8 ; Dwarf RegNum ; CHECK-NEXT: .short 0 +; reserved +; CHECK-NEXT: .short 0 ; Offset ; CHECK-NEXT: .long 1 ; padding +; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .short 0 ; NumLiveOuts ; CHECK-NEXT: .short 0 diff --git a/test/CodeGen/X86/stackmap-large-location-size.ll b/test/CodeGen/X86/stackmap-large-location-size.ll new file mode 100644 index 000000000000..6c90ddaedcc9 --- /dev/null +++ b/test/CodeGen/X86/stackmap-large-location-size.ll @@ -0,0 +1,172 @@ +; RUN: llc < %s -mtriple="x86_64-pc-linux-gnu" | FileCheck %s + +declare void @callee() + +define void @f_0(<1024 x i64> %val) { +; CHECK: .quad 2882400015 +; CHECK-NEXT: .long .Ltmp0-f_0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 4 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Constant(1) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 1 +; Indirect +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8192 +; CHECK-NEXT: .short 7 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Padding +; CHECK-NEXT: .p2align 3 + call void @callee() [ "deopt"(<1024 x i64> %val) ] + ret void +} + +define void @f_1(<1024 x i8*> %val) { +; CHECK: .quad 2882400015 +; CHECK-NEXT: .long .Ltmp1-f_1 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 4 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Constant(1) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 1 +; Indirect +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8192 +; CHECK-NEXT: .short 7 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Padding +; CHECK-NEXT: .p2align 3 + call void @callee() [ "deopt"(<1024 x i8*> %val) ] + ret void +} + +define void @f_2(<99 x i8*> %val) { +; CHECK: .quad 2882400015 +; CHECK-NEXT: .long .Ltmp2-f_2 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 4 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Constant(1) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 1 +; Indirect +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 792 +; CHECK-NEXT: .short 7 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .p2align 3 + call void @callee() [ "deopt"(<99 x i8*> %val) ] + ret void +} + + +define <400 x i8 addrspace(1)*> @f_3(<400 x i8 addrspace(1)*> %obj) gc "statepoint-example" { +; CHECK: .quad 4242 +; CHECK-NEXT: .long .Ltmp3-f_3 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 5 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Constant(0) +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Indirect +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 3200 +; CHECK-NEXT: .short 7 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Indirect +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 3200 +; CHECK-NEXT: .short 7 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; Padding +; CHECK-NEXT: .p2align 3 + %tok = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 4242, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0, <400 x i8 addrspace(1)*> %obj) + %obj.r = call coldcc <400 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v400p1i8(token %tok, i32 7, i32 7) + ret <400 x i8 addrspace(1)*> %obj.r +} + +declare void @do_safepoint() + +declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...) +declare <400 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v400p1i8(token, i32, i32) diff --git a/test/CodeGen/X86/stackmap-liveness.ll b/test/CodeGen/X86/stackmap-liveness.ll index a5809ace795b..eb95b9c8df4e 100644 --- a/test/CodeGen/X86/stackmap-liveness.ll +++ b/test/CodeGen/X86/stackmap-liveness.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -32,6 +32,7 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; Padding +; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .short 0 ; Num LiveOut Entries: 0 ; CHECK-NEXT: .short 0 @@ -43,6 +44,7 @@ entry: ; PATCH-NEXT: .short 0 ; PATCH-NEXT: .short 0 ; Padding +; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 1 ; PATCH-NEXT: .short 1 @@ -63,6 +65,7 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; Padding +; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .short 0 ; Num LiveOut Entries: 0 ; CHECK-NEXT: .short 0 @@ -74,6 +77,7 @@ entry: ; PATCH-NEXT: .short 0 ; PATCH-NEXT: .short 0 ; Padding +; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 5 ; PATCH-NEXT: .short 5 @@ -107,6 +111,7 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; Padding +; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .short 0 ; Num LiveOut Entries: 0 ; CHECK-NEXT: .short 0 @@ -118,6 +123,7 @@ entry: ; PATCH-NEXT: .short 0 ; PATCH-NEXT: .short 0 ; Padding +; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 2 ; PATCH-NEXT: .short 2 @@ -144,6 +150,7 @@ entry: ; PATCH-NEXT: .short 0 ; PATCH-NEXT: .short 0 ; Padding +; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 0 ; PATCH-NEXT: .short 0 @@ -155,6 +162,7 @@ entry: ; PATCH-NEXT: .short 0 ; PATCH-NEXT: .short 0 ; Padding +; PATCH-NEXT: .p2align 3 ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 2 ; PATCH-NEXT: .short 2 diff --git a/test/CodeGen/X86/stackmap.ll b/test/CodeGen/X86/stackmap.ll index 9818d3547fca..601100bd5705 100644 --- a/test/CodeGen/X86/stackmap.ll +++ b/test/CodeGen/X86/stackmap.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -79,62 +79,86 @@ ; CHECK-NEXT: .short 12 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 65536 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 2000000000 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 2147483647 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; LargeConstant at index 0 ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; LargeConstant at index 1 ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 1 ; LargeConstant at index 2 ; CHECK-NEXT: .byte 5 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 2 ; SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -1 @@ -151,12 +175,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @osrinline(i64 %a, i64 %b) { entry: @@ -175,12 +203,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @osrcold(i64 %a, i64 %b) { entry: @@ -200,12 +232,16 @@ ret: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @propertyRead(i64* %obj) { entry: @@ -220,12 +256,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) { entry: @@ -242,12 +282,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: @@ -264,12 +308,16 @@ entry: ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 2 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: @@ -290,8 +338,11 @@ entry: ; Check that at least one is a spilled entry from RBP. ; Location: Indirect RBP + ... ; CHECK: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) { entry: call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) @@ -309,8 +360,11 @@ entry: ; Check that at least one is a spilled entry from RBP. ; Location: Indirect RBP + ... ; CHECK: .byte 3 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) { entry: call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) @@ -327,8 +381,11 @@ entry: ; Check that the subregister operand is a 4-byte spill. ; Location: Indirect, 4-byte, RBP + ... ; CHECK: .byte 3 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long define void @spillSubReg(i64 %arg) #0 { bb: br i1 undef, label %bb1, label %bb2 @@ -367,14 +424,18 @@ bb61: ; Check that the subregister operands are 1-byte spills. ; Location 0: Register, 4-byte, AL ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 1 ; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; ; Location 1: Register, 4-byte, BL ; CHECK-NEXT: .byte 1 -; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 1 ; CHECK-NEXT: .short 3 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 define void @subRegOffset(i16 %arg) { %v = mul i16 %arg, 5 @@ -395,7 +456,9 @@ define void @subRegOffset(i16 %arg) { ; CHECK-NEXT: .short 1 ; Loc 0: SmallConstant ; CHECK-NEXT: .byte 4 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 33 @@ -413,8 +476,10 @@ define void @liveConstant() { ; CHECK-NEXT: .short 1 ; Loc 0: Direct RBP - ofs ; CHECK-NEXT: .byte 2 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long ; Callsite 17 @@ -424,13 +489,17 @@ define void @liveConstant() { ; CHECK-NEXT: .short 2 ; Loc 0: Direct RBP - ofs ; CHECK-NEXT: .byte 2 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long ; Loc 1: Direct RBP - ofs ; CHECK-NEXT: .byte 2 -; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 8 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long define void @directFrameIdx() { entry: @@ -473,8 +542,10 @@ entry: ; CHECK-NEXT: .short 1 ; Loc 0: Indirect fp - offset ; CHECK-NEXT: .byte 3 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -{{[0-9]+}} define void @clobberScratch(i32 %a) { tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r12},~{r13},~{r14},~{r15}"() nounwind diff --git a/test/CodeGen/X86/statepoint-allocas.ll b/test/CodeGen/X86/statepoint-allocas.ll index 95ce8f376170..9f5418432abc 100644 --- a/test/CodeGen/X86/statepoint-allocas.ll +++ b/test/CodeGen/X86/statepoint-allocas.ll @@ -48,7 +48,7 @@ declare token @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i3 ; CHECK-LABEL: .section .llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -77,23 +77,31 @@ declare token @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i3 ; CHECK: .short 4 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK: .byte 0 +; CHECK: .short 8 +; CHECK: .short 0 ; CHECK: .short 0 ; CHECK: .long 0 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK: .byte 0 +; CHECK: .short 8 +; CHECK: .short 0 ; CHECK: .short 0 ; CHECK: .long 0 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK: .byte 0 +; CHECK: .short 8 +; CHECK: .short 0 ; CHECK: .short 0 ; CHECK: .long 0 ; Direct Spill Slot [RSP+0] ; CHECK: .byte 2 -; CHECK: .byte 8 +; CHECK: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 0 ; No Padding or LiveOuts ; CHECK: .short 0 @@ -106,23 +114,31 @@ declare token @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i3 ; CHECK: .short 4 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK: .byte 0 +; CHECK: .short 8 +; CHECK: .short 0 ; CHECK: .short 0 ; CHECK: .long 0 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK: .byte 0 +; CHECK: .short 8 +; CHECK: .short 0 ; CHECK: .short 0 ; CHECK: .long 0 ; SmallConstant (1) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK: .byte 0 +; CHECK: .short 8 +; CHECK: .short 0 ; CHECK: .short 0 ; CHECK: .long 1 ; Direct Spill Slot [RSP+0] ; CHECK: .byte 2 -; CHECK: .byte 8 +; CHECK: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 0 ; No Padding or LiveOuts diff --git a/test/CodeGen/X86/statepoint-live-in.ll b/test/CodeGen/X86/statepoint-live-in.ll index b236393e9f49..abe2b0a7acc8 100644 --- a/test/CodeGen/X86/statepoint-live-in.ll +++ b/test/CodeGen/X86/statepoint-live-in.ll @@ -89,27 +89,37 @@ entry: ; CHECK: Ltmp0-_test1 ; CHECK: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 5 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK: Ltmp1-_test2 ; CHECK: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 3 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK: Ltmp2-_test2 ; CHECK: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 3 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 ; CHECK: .byte 1 -; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 4 ; CHECK-NEXT: .short 6 +; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long 0 declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...) diff --git a/test/CodeGen/X86/statepoint-stackmap-format.ll b/test/CodeGen/X86/statepoint-stackmap-format.ll index df6180de17a3..0506381b9ec2 100644 --- a/test/CodeGen/X86/statepoint-stackmap-format.ll +++ b/test/CodeGen/X86/statepoint-stackmap-format.ll @@ -79,7 +79,7 @@ declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32) ; CHECK-LABEL: .section .llvm_stackmaps ; CHECK-NEXT: __LLVM_StackMaps: ; Header -; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 3 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 0 ; Num Functions @@ -114,58 +114,80 @@ declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32) ; CHECK: .short 11 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; SmallConstant (2) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 2 ; Indirect Spill Slot [RSP+0] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 16 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; Indirect Spill Slot [RSP+16] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 16 ; Indirect Spill Slot [RSP+8] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 8 ; Indirect Spill Slot [RSP+16] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 16 ; Indirect Spill Slot [RSP+16] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 16 ; No Padding or LiveOuts @@ -186,53 +208,73 @@ declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32) ; CHECK: .short 11 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; SmallConstant (2) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 2 ; Indirect Spill Slot [RSP+0] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 16 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; SmallConstant (0) ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; Indirect Spill Slot [RSP+16] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 16 ; Indirect Spill Slot [RSP+8] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 8 ; Indirect Spill Slot [RSP+16] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 16 ; Indirect Spill Slot [RSP+16] ; CHECK: .byte 3 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 7 +; CHECK-NEXT: .short 0 ; CHECK: .long 16 ; No Padding or LiveOuts @@ -257,22 +299,28 @@ declare i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token, i32, i32) ; StkMapRecord[0]: ; SmallConstant(0): ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; StkMapRecord[1]: ; SmallConstant(0): ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; StkMapRecord[2]: ; SmallConstant(0): ; CHECK: .byte 4 -; CHECK: .byte 8 +; CHECK-NEXT: .byte 0 +; CHECK: .short 8 ; CHECK: .short 0 +; CHECK-NEXT: .short 0 ; CHECK: .long 0 ; No padding or LiveOuts diff --git a/test/CodeGen/X86/statepoint-vector.ll b/test/CodeGen/X86/statepoint-vector.ll index 15fb25777edd..000e88742880 100644 --- a/test/CodeGen/X86/statepoint-vector.ll +++ b/test/CodeGen/X86/statepoint-vector.ll @@ -108,51 +108,67 @@ entry: ; CHECK: .Ltmp0-test ; Check for the two spill slots -; Stack Maps: Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0] -; Stack Maps: Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0] +; Stack Maps: Loc 3: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 0] +; Stack Maps: Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 0] ; CHECK: .byte 3 -; CHECK: .byte 16 +; CHECK: .byte 0 +; CHECK: .short 16 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 0 ; CHECK: .byte 3 -; CHECK: .byte 16 +; CHECK: .byte 0 +; CHECK: .short 16 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 0 ; CHECK: .Ltmp1-test2 ; Check for the two spill slots -; Stack Maps: Loc 3: Indirect 7+16 [encoding: .byte 3, .byte 16, .short 7, .int 16] -; Stack Maps: Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0] +; Stack Maps: Loc 3: Indirect 7+16 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 16] +; Stack Maps: Loc 4: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 0] ; CHECK: .byte 3 -; CHECK: .byte 16 +; CHECK: .byte 0 +; CHECK: .short 16 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 16 ; CHECK: .byte 3 -; CHECK: .byte 16 +; CHECK: .byte 0 +; CHECK: .short 16 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 0 ; CHECK: .Ltmp2-test3 ; Check for the four spill slots -; Stack Maps: Loc 3: Indirect 7+16 [encoding: .byte 3, .byte 16, .short 7, .int 16] -; Stack Maps: Loc 4: Indirect 7+16 [encoding: .byte 3, .byte 16, .short 7, .int 16] -; Stack Maps: Loc 5: Indirect 7+16 [encoding: .byte 3, .byte 16, .short 7, .int 16] -; Stack Maps: Loc 6: Indirect 7+0 [encoding: .byte 3, .byte 16, .short 7, .int 0] +; Stack Maps: Loc 3: Indirect 7+16 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 16] +; Stack Maps: Loc 4: Indirect 7+16 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 16] +; Stack Maps: Loc 5: Indirect 7+16 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 16] +; Stack Maps: Loc 6: Indirect 7+0 [encoding: .byte 3, .byte 0, .short 16, .short 7, .short 0, .int 0] ; CHECK: .byte 3 -; CHECK: .byte 16 +; CHECK: .byte 0 +; CHECK: .short 16 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 16 ; CHECK: .byte 3 -; CHECK: .byte 16 +; CHECK: .byte 0 +; CHECK: .short 16 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 16 ; CHECK: .byte 3 -; CHECK: .byte 16 +; CHECK: .byte 0 +; CHECK: .short 16 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 16 ; CHECK: .byte 3 -; CHECK: .byte 16 +; CHECK: .byte 0 +; CHECK: .short 16 ; CHECK: .short 7 +; CHECK: .short 0 ; CHECK: .long 0 declare void @do_safepoint() diff --git a/test/CodeGen/X86/vector-shuffle-combining.ll b/test/CodeGen/X86/vector-shuffle-combining.ll index a65d830351e4..e04c5321fa25 100644 --- a/test/CodeGen/X86/vector-shuffle-combining.ll +++ b/test/CodeGen/X86/vector-shuffle-combining.ll @@ -2899,3 +2899,37 @@ entry: %s2 = shufflevector <8 x float> %s1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2> ret <8 x float> %s2 } + +define <4 x float> @PR30264(<4 x float> %x) { +; SSE2-LABEL: PR30264: +; SSE2: # BB#0: +; SSE2-NEXT: xorps %xmm1, %xmm1 +; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0] +; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[2,3] +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSSE3-LABEL: PR30264: +; SSSE3: # BB#0: +; SSSE3-NEXT: xorps %xmm1, %xmm1 +; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0] +; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[2,3] +; SSSE3-NEXT: movaps %xmm1, %xmm0 +; SSSE3-NEXT: retq +; +; SSE41-LABEL: PR30264: +; SSE41: # BB#0: +; SSE41-NEXT: movaps {{.*#+}} xmm1 = <u,u,4,1> +; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm0[0],zero,xmm1[2,3] +; SSE41-NEXT: movaps %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; AVX-LABEL: PR30264: +; AVX: # BB#0: +; AVX-NEXT: vmovaps {{.*#+}} xmm1 = <u,u,4,1> +; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x float> %x, <4 x float> <float undef, float 0.0, float undef, float undef>, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> + %shuf2 = shufflevector <4 x float> %shuf1, <4 x float> <float undef, float undef, float 4.0, float 1.0>, <4 x i32> <i32 0, i32 1, i32 6, i32 7> + ret <4 x float> %shuf2 +} diff --git a/test/CodeGen/X86/widened-broadcast.ll b/test/CodeGen/X86/widened-broadcast.ll index 900a7546f15b..6b2e4de5cdaa 100644 --- a/test/CodeGen/X86/widened-broadcast.ll +++ b/test/CodeGen/X86/widened-broadcast.ll @@ -579,3 +579,72 @@ entry: %ret = shufflevector <32 x i8> %ld, <32 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <32 x i8> %ret } + +define <4 x float> @load_splat_4f32_8f32_0000(<8 x float>* %ptr) nounwind uwtable readnone ssp { +; SSE-LABEL: load_splat_4f32_8f32_0000: +; SSE: # BB#0: # %entry +; SSE-NEXT: movaps (%rdi), %xmm0 +; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0] +; SSE-NEXT: retq +; +; AVX1-LABEL: load_splat_4f32_8f32_0000: +; AVX1: # BB#0: # %entry +; AVX1-NEXT: vmovaps (%rdi), %ymm0 +; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0] +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: load_splat_4f32_8f32_0000: +; AVX2: # BB#0: # %entry +; AVX2-NEXT: vmovaps (%rdi), %ymm0 +; AVX2-NEXT: vbroadcastss %xmm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_splat_4f32_8f32_0000: +; AVX512: # BB#0: # %entry +; AVX512-NEXT: vmovaps (%rdi), %ymm0 +; AVX512-NEXT: vbroadcastss %xmm0, %xmm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq +entry: + %ld = load <8 x float>, <8 x float>* %ptr + %ret = shufflevector <8 x float> %ld, <8 x float> undef, <4 x i32> zeroinitializer + ret <4 x float> %ret +} + +define <8 x float> @load_splat_8f32_16f32_89898989(<16 x float>* %ptr) nounwind uwtable readnone ssp { +; SSE2-LABEL: load_splat_8f32_16f32_89898989: +; SSE2: # BB#0: # %entry +; SSE2-NEXT: movaps 32(%rdi), %xmm0 +; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0] +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: retq +; +; SSE42-LABEL: load_splat_8f32_16f32_89898989: +; SSE42: # BB#0: # %entry +; SSE42-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] +; SSE42-NEXT: movapd %xmm0, %xmm1 +; SSE42-NEXT: retq +; +; AVX1-LABEL: load_splat_8f32_16f32_89898989: +; AVX1: # BB#0: # %entry +; AVX1-NEXT: vbroadcastsd 32(%rdi), %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: load_splat_8f32_16f32_89898989: +; AVX2: # BB#0: # %entry +; AVX2-NEXT: vbroadcastsd 32(%rdi), %ymm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: load_splat_8f32_16f32_89898989: +; AVX512: # BB#0: # %entry +; AVX512-NEXT: vmovapd (%rdi), %zmm0 +; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm0 +; AVX512-NEXT: vbroadcastsd %xmm0, %ymm0 +; AVX512-NEXT: retq +entry: + %ld = load <16 x float>, <16 x float>* %ptr + %ret = shufflevector <16 x float> %ld, <16 x float> undef, <8 x i32> <i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9> + ret <8 x float> %ret +} |