diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-29 16:25:25 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-29 16:25:25 +0000 |
| commit | ab44ce3d598882e51a25eb82eb7ae6308de85ae6 (patch) | |
| tree | 568d786a59d49bef961dcb9bd09d422701b9da5b /test/CodeGen | |
| parent | b5630dbadf9a2a06754194387d6b0fd9962a67f1 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen')
128 files changed, 3884 insertions, 972 deletions
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 71ea9d54f647..0298315a5510 100644 --- a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -43,7 +43,7 @@ define [1 x double] @constant() { ; The key problem here is that we may fail to create an MBB referenced by a ; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things ; happen. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %vreg4, %vreg2; mem:ST4[%addr] GPR:%vreg4,%vreg2 (in function: pending_phis) +; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %vreg5, %vreg2; mem:ST4[%addr] GPR:%vreg5,%vreg2 (in function: pending_phis) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for pending_phis ; FALLBACK-WITH-REPORT-OUT-LABEL: pending_phis: define i32 @pending_phis(i1 %tst, i32 %val, i32* %addr) { diff --git a/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll index 3ecdb7bbedfb..0972840de47b 100644 --- a/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll +++ b/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll @@ -1,10 +1,10 @@ ; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ ; RUN: -O0 -aarch64-enable-global-isel-at-O=0 \ -; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix NOFALLBACK +; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix ENABLED-O0 --check-prefix NOFALLBACK ; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ ; RUN: -O0 -aarch64-enable-global-isel-at-O=0 -global-isel-abort=2 \ -; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix FALLBACK +; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix ENABLED-O0 --check-prefix FALLBACK ; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ ; RUN: -global-isel \ @@ -32,6 +32,7 @@ ; ENABLED: IRTranslator ; ENABLED-NEXT: Legalizer ; ENABLED-NEXT: RegBankSelect +; ENABLED-O0-NEXT: Localizer ; ENABLED-NEXT: InstructionSelect ; ENABLED-NEXT: ResetMachineFunction diff --git a/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir b/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir new file mode 100644 index 000000000000..ea8a77ca3917 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir @@ -0,0 +1,96 @@ +# RUN: llc -O0 -mtriple aarch64-apple-ios %s -global-isel -start-after regbankselect \ +# RUN: -stop-before instruction-select -o - | FileCheck --check-prefix=CHECK --check-prefix=OPTNONE %s +# RUN: llc -mtriple aarch64-apple-ios %s -global-isel -start-after regbankselect \ +# RUN: -stop-before instruction-select -o - | FileCheck --check-prefix=CHECK --check-prefix=OPT %s +# +# Check that we are only running the localizer at O0 and that it runs +# between the regbankselect pass and the instruction-select. +# Moreover, check that it does what we expect. +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-apple-ios" + + define float @foo(float %arg, i1 %cond) { + br i1 %cond, label %true, label %false + + true: ; preds = %0 + br label %end + + false: ; preds = %0 + br label %end + + end: ; preds = %false, %true + %val = phi float [ 1.000000e+00, %true ], [ 2.000000e+00, %false ] + %res = fadd float %arg, %val + ret float %res + } + +... +--- +# CHECK-LABEL: name: foo +name: foo +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr } +# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 2, class: fpr } +# CHECK-NEXT: - { id: 3, class: fpr } +# CHECK-NEXT: - { id: 4, class: fpr } +# CHECK-NEXT: - { id: 5, class: fpr } +# The localizer will create two new values to materialize the constants. +# OPTNONE-NEXT: - { id: 6, class: fpr } +# OPTNONE-NEXT: - { id: 7, class: fpr } + - { id: 0, class: fpr } + - { id: 1, class: gpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } + - { id: 5, class: fpr } + +# First block remains untouched +# CHECK: body +# CHECK: %4(s32) = G_FCONSTANT float 1.000000e+00 +# CHECK: %5(s32) = G_FCONSTANT float 2.000000e+00 + +# Second block will get the constant 1.0 when the localizer is enabled. +# CHECK: bb.1.true: +# OPT-NOT: G_FCONSTANT +# OPTNONE: [[FONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00 +# CHECK: G_BR %bb.3.end + +# Thrid block will get the constant 2.0 when the localizer is enabled. +# CHECK: bb.2.false: +# OPT-NOT: G_FCONSTANT +# OPTNONE: [[FTWO:%[0-9]+]](s32) = G_FCONSTANT float 2.000000e+00 + +# CHECK: bb.3.end +# OPTNONE: %2(s32) = PHI [[FONE]](s32), %bb.1.true, [[FTWO]](s32), %bb.2.false +# OPT: %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false +# CHECK-NEXT: G_FADD %0, %2 +body: | + bb.0 (%ir-block.0): + liveins: %s0, %w0 + + %0(s32) = COPY %s0 + %1(s1) = COPY %w0 + %4(s32) = G_FCONSTANT float 1.000000e+00 + %5(s32) = G_FCONSTANT float 2.000000e+00 + G_BRCOND %1(s1), %bb.1.true + G_BR %bb.2.false + + bb.1.true: + G_BR %bb.3.end + + bb.2.false: + + bb.3.end: + %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false + %3(s32) = G_FADD %0, %2 + %s0 = COPY %3(s32) + RET_ReallyLR implicit %s0 + +... diff --git a/test/CodeGen/AArch64/GlobalISel/localizer.mir b/test/CodeGen/AArch64/GlobalISel/localizer.mir new file mode 100644 index 000000000000..8fbb2040157e --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/localizer.mir @@ -0,0 +1,312 @@ +# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=localizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK + +# Test the localizer. + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + + define void @local_use() { ret void } + define void @non_local_1use() { ret void } + define void @non_local_2uses() { ret void } + define void @non_local_phi_use() { ret void } + define void @non_local_phi_use_followed_by_use() { ret void } + define void @non_local_phi_use_followed_by_use_fi() { ret void } + define void @float_non_local_phi_use_followed_by_use_fi() { ret void } +... + +--- +# CHECK-LABEL: name: local_use +name: local_use +legalized: true +regBankSelected: true + +# CHECK: registers: +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0(s32) = G_CONSTANT 1 +# CHECK-NEXT: %1(s32) = G_ADD %0, %0 +body: | + bb.0: + %0(s32) = G_CONSTANT 1 + %1(s32) = G_ADD %0, %0 +... + +--- +# CHECK-LABEL: name: non_local_1use +name: non_local_1use +legalized: true +regBankSelected: true + +# CHECK: registers: +# Existing registers should be left untouched +# CHECK: - { id: 0, class: gpr } +#CHECK-NEXT: - { id: 1, class: gpr } +#CHECK-NEXT: - { id: 2, class: gpr } +# The newly created reg should be on the same regbank/regclass as its origin. +#CHECK-NEXT: - { id: 3, class: gpr } + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0(s32) = G_CONSTANT 1 +# CHECK-NEXT: %1(s32) = G_ADD %0, %0 + +# CHECK: bb.1: +# CHECK: %3(s32) = G_CONSTANT 1 +# CHECK-NEXT: %2(s32) = G_ADD %3, %1 +body: | + bb.0: + successors: %bb.1 + + %0(s32) = G_CONSTANT 1 + %1(s32) = G_ADD %0, %0 + + bb.1: + %2(s32) = G_ADD %0, %1 +... + + +--- +# CHECK-LABEL: name: non_local_2uses +name: non_local_2uses +legalized: true +regBankSelected: true + +# CHECK: registers: +# Existing registers should be left untouched +# CHECK: - { id: 0, class: gpr } +#CHECK-NEXT: - { id: 1, class: gpr } +#CHECK-NEXT: - { id: 2, class: gpr } +# The newly created reg should be on the same regbank/regclass as its origin. +#CHECK-NEXT: - { id: 3, class: gpr } + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %0(s32) = G_CONSTANT 1 +# CHECK-NEXT: %1(s32) = G_ADD %0, %0 + +# CHECK: bb.1: +# CHECK: %3(s32) = G_CONSTANT 1 +# CHECK-NEXT: %2(s32) = G_ADD %3, %3 +body: | + bb.0: + successors: %bb.1 + + %0(s32) = G_CONSTANT 1 + %1(s32) = G_ADD %0, %0 + + bb.1: + %2(s32) = G_ADD %0, %0 +... + +--- +# CHECK-LABEL: name: non_local_phi_use +name: non_local_phi_use +legalized: true +regBankSelected: true +tracksRegLiveness: true + +# CHECK: registers: +# Existing registers should be left untouched +# CHECK: - { id: 0, class: gpr } +#CHECK-NEXT: - { id: 1, class: gpr } +#CHECK-NEXT: - { id: 2, class: gpr } +#CHECK-NEXT: - { id: 3, class: gpr } +#CHECK-NEXT: - { id: 4, class: gpr } +# The newly created reg should be on the same regbank/regclass as its origin. +#CHECK-NEXT: - { id: 5, class: gpr } + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + +# CHECK: body: +# CHECK: %0(s32) = G_CONSTANT 1 +# CHECK-NEXT: %1(s32) = G_ADD %0, %0 + +# CHECK: bb.1: +# CHECK: %5(s32) = G_CONSTANT 1 + +# CHECK: bb.2: +# CHECK: %3(s32) = PHI %5(s32), %bb.1 +body: | + bb.0: + successors: %bb.1 + + %0(s32) = G_CONSTANT 1 + %1(s32) = G_ADD %0, %0 + + bb.1: + successors: %bb.2 + + bb.2: + %3(s32) = PHI %0(s32), %bb.1 + %2(s32) = G_ADD %3, %3 +... + +--- +# CHECK-LABEL: name: non_local_phi_use_followed_by_use +name: non_local_phi_use_followed_by_use +legalized: true +regBankSelected: true +tracksRegLiveness: true + +# CHECK: registers: +# Existing registers should be left untouched +# CHECK: - { id: 0, class: gpr } +#CHECK-NEXT: - { id: 1, class: gpr } +#CHECK-NEXT: - { id: 2, class: gpr } +#CHECK-NEXT: - { id: 3, class: gpr } +#CHECK-NEXT: - { id: 4, class: gpr } +# The newly created regs should be on the same regbank/regclass as its origin. +#CHECK-NEXT: - { id: 5, class: gpr } +#CHECK-NEXT: - { id: 6, class: gpr } + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + +# CHECK: body: +# CHECK: %0(s32) = G_CONSTANT 1 +# CHECK-NEXT: %1(s32) = G_ADD %0, %0 + +# CHECK: bb.1: +# CHECK: %5(s32) = G_CONSTANT 1 + +# CHECK: bb.2: +# CHECK: %3(s32) = PHI %5(s32), %bb.1 +# CHECK-NEXT: %6(s32) = G_CONSTANT 1 +# CHECK-NEXT: %2(s32) = G_ADD %3, %6 +body: | + bb.0: + successors: %bb.1 + + %0(s32) = G_CONSTANT 1 + %1(s32) = G_ADD %0, %0 + + bb.1: + successors: %bb.2 + + bb.2: + %3(s32) = PHI %0(s32), %bb.1 + %2(s32) = G_ADD %3, %0 +... + +--- +# CHECK-LABEL: name: non_local_phi_use_followed_by_use_fi +name: non_local_phi_use_followed_by_use_fi +legalized: true +regBankSelected: true +tracksRegLiveness: true + +# CHECK: registers: +# Existing registers should be left untouched +# CHECK: - { id: 0, class: gpr } +#CHECK-NEXT: - { id: 1, class: gpr } +#CHECK-NEXT: - { id: 2, class: gpr } +#CHECK-NEXT: - { id: 3, class: gpr } +#CHECK-NEXT: - { id: 4, class: gpr } +# The newly created reg should be on the same regbank/regclass as its origin. +#CHECK-NEXT: - { id: 5, class: gpr } +#CHECK-NEXT: - { id: 6, class: gpr } + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + +# CHECK: body: +# CHECK: %0(s32) = G_FRAME_INDEX 1 +# CHECK-NEXT: %1(s32) = G_ADD %0, %0 + +# CHECK: bb.1: +# CHECK: %5(s32) = G_FRAME_INDEX 1 + +# CHECK: bb.2: +# CHECK: %3(s32) = PHI %5(s32), %bb.1 +# CHECK-NEXT: %6(s32) = G_FRAME_INDEX 1 +# CHECK-NEXT: %2(s32) = G_ADD %3, %6 +body: | + bb.0: + successors: %bb.1 + + %0(s32) = G_FRAME_INDEX 1 + %1(s32) = G_ADD %0, %0 + + bb.1: + successors: %bb.2 + + bb.2: + %3(s32) = PHI %0(s32), %bb.1 + %2(s32) = G_ADD %3, %0 +... + +--- +# CHECK-LABEL: name: float_non_local_phi_use_followed_by_use_fi +name: float_non_local_phi_use_followed_by_use_fi +legalized: true +regBankSelected: true +tracksRegLiveness: true + +# CHECK: registers: +# Existing registers should be left untouched +# CHECK: - { id: 0, class: fpr } +#CHECK-NEXT: - { id: 1, class: fpr } +#CHECK-NEXT: - { id: 2, class: fpr } +#CHECK-NEXT: - { id: 3, class: fpr } +#CHECK-NEXT: - { id: 4, class: fpr } +# The newly created reg should be on the same regbank/regclass as its origin. +#CHECK-NEXT: - { id: 5, class: fpr } +#CHECK-NEXT: - { id: 6, class: fpr } + +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } + - { id: 3, class: fpr } + - { id: 4, class: fpr } + +# CHECK: body: +# CHECK: %0(s32) = G_FCONSTANT float 1.0 +# CHECK-NEXT: %1(s32) = G_FADD %0, %0 + +# CHECK: bb.1: +# CHECK: %5(s32) = G_FCONSTANT float 1.0 + +# CHECK: bb.2: +# CHECK: %3(s32) = PHI %5(s32), %bb.1 +# CHECK-NEXT: %6(s32) = G_FCONSTANT float 1.0 +# CHECK-NEXT: %2(s32) = G_FADD %3, %6 +body: | + bb.0: + successors: %bb.1 + + %0(s32) = G_FCONSTANT float 1.0 + %1(s32) = G_FADD %0, %0 + + bb.1: + successors: %bb.2 + + bb.2: + %3(s32) = PHI %0(s32), %bb.1 + %2(s32) = G_FADD %3, %0 +... diff --git a/test/CodeGen/AArch64/aarch64-stp-cluster.ll b/test/CodeGen/AArch64/aarch64-stp-cluster.ll index fe5abbf15eff..25cf313b81e7 100644 --- a/test/CodeGen/AArch64/aarch64-stp-cluster.ll +++ b/test/CodeGen/AArch64/aarch64-stp-cluster.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=misched -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s ; CHECK: ********** MI Scheduling ********** ; CHECK-LABEL: stp_i64_scale:BB#0 diff --git a/test/CodeGen/AArch64/arm64-csldst-mmo.ll b/test/CodeGen/AArch64/arm64-csldst-mmo.ll index 4930c493d62c..cfb8e3a38c49 100644 --- a/test/CodeGen/AArch64/arm64-csldst-mmo.ll +++ b/test/CodeGen/AArch64/arm64-csldst-mmo.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s ; REQUIRES: asserts @G = external global [0 x i32], align 4 diff --git a/test/CodeGen/AArch64/arm64-inline-asm.ll b/test/CodeGen/AArch64/arm64-inline-asm.ll index f28d0ab07c5a..f849df2a51ec 100644 --- a/test/CodeGen/AArch64/arm64-inline-asm.ll +++ b/test/CodeGen/AArch64/arm64-inline-asm.ll @@ -254,3 +254,10 @@ define void @test_constraint_w(i32 %a) { tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a) ret void } + +define void @test_inline_modifier_a(i8* %ptr) nounwind { + ; CHECK-LABEL: test_inline_modifier_a: + tail call void asm sideeffect "prfm pldl1keep, ${0:a}\0A", "r"(i8* %ptr) + ; CHECK: prfm pldl1keep, [x0] + ret void +} diff --git a/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/test/CodeGen/AArch64/arm64-ldp-cluster.ll index 0cfbe5958f4d..64e535ca7499 100644 --- a/test/CodeGen/AArch64/arm64-ldp-cluster.ll +++ b/test/CodeGen/AArch64/arm64-ldp-cluster.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s ; Test ldr clustering. ; CHECK: ********** MI Scheduling ********** diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll index 41287a17da86..307d1ec1aa8c 100644 --- a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll +++ b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -disable-machine-dce -o - 2>&1 > /dev/null | FileCheck %s -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -disable-machine-dce -o - -misched-limit=2 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -disable-machine-dce -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -disable-machine-dce -o - -misched-limit=2 2>&1 > /dev/null | FileCheck %s ; ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled ; much higher than the ADD instructions in order to hide latency. When not diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll index fac5f8ad2e9f..82ba18ce72ca 100644 --- a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll +++ b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll @@ -6,7 +6,7 @@ ; the loads to avoid unnecessary stalls. The generic machine model schedules 4 ; loads consecutively for this case and will cause stalls. ; -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s ; CHECK: ********** MI Scheduling ********** ; CHECK: main:BB#2 ; CHECK: LDR diff --git a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll index 0ee74d1f782e..cde62fcb3f95 100644 --- a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll +++ b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s ; ; For Cortex-A53, shiftable operands that are not actually shifted ; are not needed for an additional two cycles. diff --git a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll index 0ec754f97ec7..748a4762d82f 100644 --- a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll +++ b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s ; ; Test for bug in misched memory dependency calculation. ; diff --git a/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/test/CodeGen/AArch64/arm64-misched-multimmo.ll index 3593668e0156..75f45da0e48f 100644 --- a/test/CodeGen/AArch64/arm64-misched-multimmo.ll +++ b/test/CodeGen/AArch64/arm64-misched-multimmo.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s @G1 = common global [100 x i32] zeroinitializer, align 4 diff --git a/test/CodeGen/AArch64/arm64-vabs.ll b/test/CodeGen/AArch64/arm64-vabs.ll index ff7a0a8300e2..6b754b0a169e 100644 --- a/test/CodeGen/AArch64/arm64-vabs.ll +++ b/test/CodeGen/AArch64/arm64-vabs.ll @@ -33,7 +33,7 @@ define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @sabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sabdl2_8h: -;CHECK: sabdl2.8h +;CHECK: sabdl.8h %load1 = load <16 x i8>, <16 x i8>* %A %load2 = load <16 x i8>, <16 x i8>* %B %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -45,7 +45,7 @@ define <8 x i16> @sabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @sabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sabdl2_4s: -;CHECK: sabdl2.4s +;CHECK: sabdl.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> @@ -57,7 +57,7 @@ define <4 x i32> @sabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @sabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sabdl2_2d: -;CHECK: sabdl2.2d +;CHECK: sabdl.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> @@ -99,7 +99,7 @@ define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uabdl2_8h: -;CHECK: uabdl2.8h +;CHECK: uabdl.8h %load1 = load <16 x i8>, <16 x i8>* %A %load2 = load <16 x i8>, <16 x i8>* %B %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -112,7 +112,7 @@ define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uabdl2_4s: -;CHECK: uabdl2.4s +;CHECK: uabdl.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> @@ -124,7 +124,7 @@ define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uabdl2_2d: -;CHECK: uabdl2.2d +;CHECK: uabdl.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> @@ -561,7 +561,7 @@ define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind define <8 x i16> @sabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: sabal2_8h: -;CHECK: sabal2.8h +;CHECK: sabal.8h %load1 = load <16 x i8>, <16 x i8>* %A %load2 = load <16 x i8>, <16 x i8>* %B %tmp3 = load <8 x i16>, <8 x i16>* %C @@ -575,7 +575,7 @@ define <8 x i16> @sabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwin define <4 x i32> @sabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sabal2_4s: -;CHECK: sabal2.4s +;CHECK: sabal.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp3 = load <4 x i32>, <4 x i32>* %C @@ -589,7 +589,7 @@ define <4 x i32> @sabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwin define <2 x i64> @sabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sabal2_2d: -;CHECK: sabal2.2d +;CHECK: sabal.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp3 = load <2 x i64>, <2 x i64>* %C @@ -639,7 +639,7 @@ define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind define <8 x i16> @uabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: uabal2_8h: -;CHECK: uabal2.8h +;CHECK: uabal.8h %load1 = load <16 x i8>, <16 x i8>* %A %load2 = load <16 x i8>, <16 x i8>* %B %tmp3 = load <8 x i16>, <8 x i16>* %C @@ -653,7 +653,7 @@ define <8 x i16> @uabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwin define <4 x i32> @uabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: uabal2_4s: -;CHECK: uabal2.4s +;CHECK: uabal.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp3 = load <4 x i32>, <4 x i32>* %C @@ -667,7 +667,7 @@ define <4 x i32> @uabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwin define <2 x i64> @uabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: uabal2_2d: -;CHECK: uabal2.2d +;CHECK: uabal.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp3 = load <2 x i64>, <2 x i64>* %C diff --git a/test/CodeGen/AArch64/arm64-vadd.ll b/test/CodeGen/AArch64/arm64-vadd.ll index 9d09251524ea..2a25538250e4 100644 --- a/test/CodeGen/AArch64/arm64-vadd.ll +++ b/test/CodeGen/AArch64/arm64-vadd.ll @@ -318,7 +318,7 @@ define <2 x i64> @uaddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @uaddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uaddw2_8h: -;CHECK: uaddw2.8h +;CHECK: uaddw.8h %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = load <16 x i8>, <16 x i8>* %B @@ -331,7 +331,7 @@ define <8 x i16> @uaddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @uaddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uaddw2_4s: -;CHECK: uaddw2.4s +;CHECK: uaddw.4s %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = load <8 x i16>, <8 x i16>* %B @@ -344,7 +344,7 @@ define <4 x i32> @uaddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @uaddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uaddw2_2d: -;CHECK: uaddw2.2d +;CHECK: uaddw.2d %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = load <4 x i32>, <4 x i32>* %B @@ -387,7 +387,7 @@ define <2 x i64> @saddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @saddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: saddw2_8h: -;CHECK: saddw2.8h +;CHECK: saddw.8h %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = load <16 x i8>, <16 x i8>* %B @@ -400,7 +400,7 @@ define <8 x i16> @saddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @saddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: saddw2_4s: -;CHECK: saddw2.4s +;CHECK: saddw.4s %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = load <8 x i16>, <8 x i16>* %B @@ -413,7 +413,7 @@ define <4 x i32> @saddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @saddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: saddw2_2d: -;CHECK: saddw2.2d +;CHECK: saddw.2d %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = load <4 x i32>, <4 x i32>* %B diff --git a/test/CodeGen/AArch64/arm64-vmul.ll b/test/CodeGen/AArch64/arm64-vmul.ll index a7668ec97979..f70ed9a43427 100644 --- a/test/CodeGen/AArch64/arm64-vmul.ll +++ b/test/CodeGen/AArch64/arm64-vmul.ll @@ -83,7 +83,7 @@ define <2 x i64> @sqdmull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @sqdmull2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmull2_4s: -;CHECK: sqdmull2.4s +;CHECK: sqdmull.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> @@ -94,7 +94,7 @@ define <4 x i32> @sqdmull2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @sqdmull2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmull2_2d: -;CHECK: sqdmull2.2d +;CHECK: sqdmull.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> @@ -324,7 +324,7 @@ define <2 x i64> @sqdmlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwin define <4 x i32> @sqdmlal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sqdmlal2_4s: -;CHECK: sqdmlal2.4s +;CHECK: sqdmlal.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp3 = load <4 x i32>, <4 x i32>* %C @@ -337,7 +337,7 @@ define <4 x i32> @sqdmlal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounw define <2 x i64> @sqdmlal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sqdmlal2_2d: -;CHECK: sqdmlal2.2d +;CHECK: sqdmlal.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp3 = load <2 x i64>, <2 x i64>* %C @@ -372,7 +372,7 @@ define <2 x i64> @sqdmlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwin define <4 x i32> @sqdmlsl2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sqdmlsl2_4s: -;CHECK: sqdmlsl2.4s +;CHECK: sqdmlsl.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp3 = load <4 x i32>, <4 x i32>* %C @@ -385,7 +385,7 @@ define <4 x i32> @sqdmlsl2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounw define <2 x i64> @sqdmlsl2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sqdmlsl2_2d: -;CHECK: sqdmlsl2.2d +;CHECK: sqdmlsl.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp3 = load <2 x i64>, <2 x i64>* %C @@ -874,7 +874,7 @@ define <2 x i64> @sqdmull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @sqdmull2_lane_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmull2_lane_4s: ;CHECK-NOT: dup -;CHECK: sqdmull2.4s +;CHECK: sqdmull.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> @@ -886,7 +886,7 @@ define <4 x i32> @sqdmull2_lane_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @sqdmull2_lane_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmull2_lane_2d: ;CHECK-NOT: dup -;CHECK: sqdmull2.2d +;CHECK: sqdmull.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> @@ -994,7 +994,7 @@ define <2 x i64> @sqdmlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) n define <4 x i32> @sqdmlal2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sqdmlal2_lane_4s: ;CHECK-NOT: dup -;CHECK: sqdmlal2.4s +;CHECK: sqdmlal.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp3 = load <4 x i32>, <4 x i32>* %C @@ -1008,7 +1008,7 @@ define <4 x i32> @sqdmlal2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) define <2 x i64> @sqdmlal2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sqdmlal2_lane_2d: ;CHECK-NOT: dup -;CHECK: sqdmlal2.2d +;CHECK: sqdmlal.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp3 = load <2 x i64>, <2 x i64>* %C @@ -1147,7 +1147,7 @@ define <2 x i64> @sqdmlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) n define <4 x i32> @sqdmlsl2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sqdmlsl2_lane_4s: ;CHECK-NOT: dup -;CHECK: sqdmlsl2.4s +;CHECK: sqdmlsl.4s %load1 = load <8 x i16>, <8 x i16>* %A %load2 = load <8 x i16>, <8 x i16>* %B %tmp3 = load <4 x i32>, <4 x i32>* %C @@ -1161,7 +1161,7 @@ define <4 x i32> @sqdmlsl2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) define <2 x i64> @sqdmlsl2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sqdmlsl2_lane_2d: ;CHECK-NOT: dup -;CHECK: sqdmlsl2.2d +;CHECK: sqdmlsl.2d %load1 = load <4 x i32>, <4 x i32>* %A %load2 = load <4 x i32>, <4 x i32>* %B %tmp3 = load <2 x i64>, <2 x i64>* %C diff --git a/test/CodeGen/AArch64/arm64-vshift.ll b/test/CodeGen/AArch64/arm64-vshift.ll index c1c4649bd6a4..6b0fe40b5a09 100644 --- a/test/CodeGen/AArch64/arm64-vshift.ll +++ b/test/CodeGen/AArch64/arm64-vshift.ll @@ -1164,7 +1164,7 @@ define <2 x i64> @ushll2d(<2 x i32>* %A) nounwind { define <8 x i16> @ushll2_8h(<16 x i8>* %A) nounwind { ;CHECK-LABEL: ushll2_8h: -;CHECK: ushll2.8h v0, {{v[0-9]+}}, #1 +;CHECK: ushll.8h v0, {{v[0-9]+}}, #1 %load1 = load <16 x i8>, <16 x i8>* %A %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp2 = zext <8 x i8> %tmp1 to <8 x i16> @@ -1174,7 +1174,7 @@ define <8 x i16> @ushll2_8h(<16 x i8>* %A) nounwind { define <4 x i32> @ushll2_4s(<8 x i16>* %A) nounwind { ;CHECK-LABEL: ushll2_4s: -;CHECK: ushll2.4s v0, {{v[0-9]+}}, #1 +;CHECK: ushll.4s v0, {{v[0-9]+}}, #1 %load1 = load <8 x i16>, <8 x i16>* %A %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = zext <4 x i16> %tmp1 to <4 x i32> @@ -1184,7 +1184,7 @@ define <4 x i32> @ushll2_4s(<8 x i16>* %A) nounwind { define <2 x i64> @ushll2_2d(<4 x i32>* %A) nounwind { ;CHECK-LABEL: ushll2_2d: -;CHECK: ushll2.2d v0, {{v[0-9]+}}, #1 +;CHECK: ushll.2d v0, {{v[0-9]+}}, #1 %load1 = load <4 x i32>, <4 x i32>* %A %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = zext <2 x i32> %tmp1 to <2 x i64> @@ -1221,7 +1221,7 @@ define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind { define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind { ;CHECK-LABEL: sshll2_8h: -;CHECK: sshll2.8h v0, {{v[0-9]+}}, #1 +;CHECK: sshll.8h v0, {{v[0-9]+}}, #1 %load1 = load <16 x i8>, <16 x i8>* %A %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp2 = sext <8 x i8> %tmp1 to <8 x i16> @@ -1231,7 +1231,7 @@ define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind { define <4 x i32> @sshll2_4s(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sshll2_4s: -;CHECK: sshll2.4s v0, {{v[0-9]+}}, #1 +;CHECK: sshll.4s v0, {{v[0-9]+}}, #1 %load1 = load <8 x i16>, <8 x i16>* %A %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = sext <4 x i16> %tmp1 to <4 x i32> @@ -1241,7 +1241,7 @@ define <4 x i32> @sshll2_4s(<8 x i16>* %A) nounwind { define <2 x i64> @sshll2_2d(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sshll2_2d: -;CHECK: sshll2.2d v0, {{v[0-9]+}}, #1 +;CHECK: sshll.2d v0, {{v[0-9]+}}, #1 %load1 = load <4 x i32>, <4 x i32>* %A %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = sext <2 x i32> %tmp1 to <2 x i64> diff --git a/test/CodeGen/AArch64/arm64-vsub.ll b/test/CodeGen/AArch64/arm64-vsub.ll index 7af69118347e..6746e49989cb 100644 --- a/test/CodeGen/AArch64/arm64-vsub.ll +++ b/test/CodeGen/AArch64/arm64-vsub.ll @@ -157,7 +157,7 @@ define <2 x i64> @ssubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @ssubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: ssubl2_8h: -;CHECK: ssubl2.8h +;CHECK: ssubl.8h %tmp1 = load <16 x i8>, <16 x i8>* %A %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext1 = sext <8 x i8> %high1 to <8 x i16> @@ -172,7 +172,7 @@ define <8 x i16> @ssubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @ssubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: ssubl2_4s: -;CHECK: ssubl2.4s +;CHECK: ssubl.4s %tmp1 = load <8 x i16>, <8 x i16>* %A %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext1 = sext <4 x i16> %high1 to <4 x i32> @@ -187,7 +187,7 @@ define <4 x i32> @ssubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @ssubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: ssubl2_2d: -;CHECK: ssubl2.2d +;CHECK: ssubl.2d %tmp1 = load <4 x i32>, <4 x i32>* %A %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext1 = sext <2 x i32> %high1 to <2 x i64> @@ -235,7 +235,7 @@ define <2 x i64> @usubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @usubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: usubl2_8h: -;CHECK: usubl2.8h +;CHECK: usubl.8h %tmp1 = load <16 x i8>, <16 x i8>* %A %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext1 = zext <8 x i8> %high1 to <8 x i16> @@ -250,7 +250,7 @@ define <8 x i16> @usubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @usubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: usubl2_4s: -;CHECK: usubl2.4s +;CHECK: usubl.4s %tmp1 = load <8 x i16>, <8 x i16>* %A %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext1 = zext <4 x i16> %high1 to <4 x i32> @@ -265,7 +265,7 @@ define <4 x i32> @usubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @usubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: usubl2_2d: -;CHECK: usubl2.2d +;CHECK: usubl.2d %tmp1 = load <4 x i32>, <4 x i32>* %A %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext1 = zext <2 x i32> %high1 to <2 x i64> @@ -310,7 +310,7 @@ define <2 x i64> @ssubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @ssubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: ssubw2_8h: -;CHECK: ssubw2.8h +;CHECK: ssubw.8h %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = load <16 x i8>, <16 x i8>* %B @@ -323,7 +323,7 @@ define <8 x i16> @ssubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @ssubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: ssubw2_4s: -;CHECK: ssubw2.4s +;CHECK: ssubw.4s %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = load <8 x i16>, <8 x i16>* %B @@ -336,7 +336,7 @@ define <4 x i32> @ssubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @ssubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: ssubw2_2d: -;CHECK: ssubw2.2d +;CHECK: ssubw.2d %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = load <4 x i32>, <4 x i32>* %B @@ -379,7 +379,7 @@ define <2 x i64> @usubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @usubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: usubw2_8h: -;CHECK: usubw2.8h +;CHECK: usubw.8h %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = load <16 x i8>, <16 x i8>* %B @@ -392,7 +392,7 @@ define <8 x i16> @usubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @usubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: usubw2_4s: -;CHECK: usubw2.4s +;CHECK: usubw.4s %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = load <8 x i16>, <8 x i16>* %B @@ -405,7 +405,7 @@ define <4 x i32> @usubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @usubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: usubw2_2d: -;CHECK: usubw2.2d +;CHECK: usubw.2d %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = load <4 x i32>, <4 x i32>* %B diff --git a/test/CodeGen/AArch64/asm-print-comments.ll b/test/CodeGen/AArch64/asm-print-comments.ll new file mode 100644 index 000000000000..e997dce23583 --- /dev/null +++ b/test/CodeGen/AArch64/asm-print-comments.ll @@ -0,0 +1,17 @@ +; RUN: llc %s -mtriple=arm64-apple-darwin -o - | FileCheck %s + +; CHECK-LABEL: ; -- Begin function foo +; CHECK: foo: +define hidden i32 @foo() { + entry: + ret i32 30 +} +; CHECK: ; -- End function + +; CHECK-LABEL: ; -- Begin function bar +; CHECK: bar: +define i32 @bar() { + entry: + ret i32 30 +} +; CHECK: ; -- End function diff --git a/test/CodeGen/AArch64/cmpxchg-O0.ll b/test/CodeGen/AArch64/cmpxchg-O0.ll index 8432b15ea523..1bfbcf851c0e 100644 --- a/test/CodeGen/AArch64/cmpxchg-O0.ll +++ b/test/CodeGen/AArch64/cmpxchg-O0.ll @@ -3,10 +3,11 @@ define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind { ; CHECK-LABEL: test_cmpxchg_8: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: mov [[STATUS:w[3-9]+]], #0 ; CHECK: ldaxrb [[OLD:w[0-9]+]], [x0] ; CHECK: cmp [[OLD]], w1, uxtb ; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] -; CHECK: stlxrb [[STATUS:w[3-9]]], w2, [x0] +; CHECK: stlxrb [[STATUS]], w2, [x0] ; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: [[DONE]]: ; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 @@ -18,6 +19,7 @@ define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind { define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind { ; CHECK-LABEL: test_cmpxchg_16: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: mov [[STATUS:w[3-9]+]], #0 ; CHECK: ldaxrh [[OLD:w[0-9]+]], [x0] ; CHECK: cmp [[OLD]], w1, uxth ; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] @@ -33,10 +35,11 @@ define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind { ; CHECK-LABEL: test_cmpxchg_32: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: mov [[STATUS:w[3-9]+]], #0 ; CHECK: ldaxr [[OLD:w[0-9]+]], [x0] ; CHECK: cmp [[OLD]], w1 ; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] -; CHECK: stlxr [[STATUS:w[3-9]]], w2, [x0] +; CHECK: stlxr [[STATUS]], w2, [x0] ; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: [[DONE]]: ; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 @@ -48,10 +51,11 @@ define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind { ; CHECK-LABEL: test_cmpxchg_64: ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: mov [[STATUS:w[3-9]+]], #0 ; CHECK: ldaxr [[OLD:x[0-9]+]], [x0] ; CHECK: cmp [[OLD]], x1 ; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] -; CHECK: stlxr [[STATUS:w[3-9]]], x2, [x0] +; CHECK: stlxr [[STATUS]], x2, [x0] ; CHECK: cbnz [[STATUS]], [[RETRY]] ; CHECK: [[DONE]]: ; CHECK: subs {{x[0-9]+}}, [[OLD]], x1 diff --git a/test/CodeGen/AArch64/fast-isel-cmpxchg.ll b/test/CodeGen/AArch64/fast-isel-cmpxchg.ll index aa78210fae74..7ef625abab20 100644 --- a/test/CodeGen/AArch64/fast-isel-cmpxchg.ll +++ b/test/CodeGen/AArch64/fast-isel-cmpxchg.ll @@ -2,11 +2,12 @@ ; CHECK-LABEL: cmpxchg_monotonic_32: ; CHECK: [[RETRY:.LBB[0-9_]+]]: +; CHECK-NEXT: mov [[STATUS:w[0-9]+]], #0 ; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0] ; CHECK-NEXT: cmp [[OLD]], w1 ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] ; CHECK-NEXT: // BB#2: -; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w2, [x0] +; CHECK-NEXT: stlxr [[STATUS]], w2, [x0] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: [[DONE]]: ; CHECK-NEXT: cmp [[OLD]], w1 @@ -27,11 +28,12 @@ define i32 @cmpxchg_monotonic_32(i32* %p, i32 %cmp, i32 %new, i32* %ps) #0 { ; CHECK: // BB#0: ; CHECK: ldr [[NEW:w[0-9]+]], [x2] ; CHECK-NEXT: [[RETRY:.LBB[0-9_]+]]: +; CHECK-NEXT: mov [[STATUS:w[0-9]+]], #0 ; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0] ; CHECK-NEXT: cmp [[OLD]], w1 ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] ; CHECK-NEXT: // BB#2: -; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x0] +; CHECK-NEXT: stlxr [[STATUS]], [[NEW]], [x0] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: [[DONE]]: ; CHECK-NEXT: cmp [[OLD]], w1 @@ -51,11 +53,12 @@ define i32 @cmpxchg_acq_rel_32_load(i32* %p, i32 %cmp, i32* %pnew, i32* %ps) #0 ; CHECK-LABEL: cmpxchg_seq_cst_64: ; CHECK: [[RETRY:.LBB[0-9_]+]]: +; CHECK-NEXT: mov [[STATUS:w[0-9]+]], #0 ; CHECK-NEXT: ldaxr [[OLD:x[0-9]+]], [x0] ; CHECK-NEXT: cmp [[OLD]], x1 ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] ; CHECK-NEXT: // BB#2: -; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], x2, [x0] +; CHECK-NEXT: stlxr [[STATUS]], x2, [x0] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: [[DONE]]: ; CHECK-NEXT: cmp [[OLD]], x1 diff --git a/test/CodeGen/AArch64/live-interval-analysis.mir b/test/CodeGen/AArch64/live-interval-analysis.mir index d44300973566..93dfcf507fff 100644 --- a/test/CodeGen/AArch64/live-interval-analysis.mir +++ b/test/CodeGen/AArch64/live-interval-analysis.mir @@ -6,7 +6,7 @@ --- # CHECK-LABEL: ********** INTERVALS ********** # W29 is reserved, so we should only see dead defs -# CHECK-DAG: W29 [0B,0d:{{[0-9]+}})[32r,32d:{{[0-9]+}})[64r,64d:{{[0-9]+}}) +# CHECK-DAG: W29 [32r,32d:{{[0-9]+}})[64r,64d:{{[0-9]+}}) # For normal registers like x28 we should see the full intervals # CHECK-DAG: W28 [0B,16r:{{[0-9]+}})[32r,48r:{{[0-9]+}})[48r,48d:{{[0-9]+}}) # CHECK: # End machine code for function reserved_reg_liveness. @@ -14,7 +14,7 @@ name: reserved_reg_liveness tracksRegLiveness: true body: | bb.0: - liveins: %x28_fp + liveins: %x28 %6 : xseqpairsclass = COPY %x28_fp %x28_fp = COPY %6 %x28 = COPY %x28 diff --git a/test/CodeGen/AArch64/misched-fusion-aes.ll b/test/CodeGen/AArch64/misched-fusion-aes.ll index 4c682e594e66..1d8787212579 100644 --- a/test/CodeGen/AArch64/misched-fusion-aes.ll +++ b/test/CodeGen/AArch64/misched-fusion-aes.ll @@ -1,5 +1,5 @@ -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKA57 -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKA72 +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKA57A72 +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKA57A72 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKM1 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k) @@ -72,55 +72,40 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, ret void ; CHECK-LABEL: aesea: -; CHECKA57: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesmc {{v[0-7].16b}}, [[VC]] -; CHECKA57: aesmc {{v[0-7].16b}}, [[VA]] -; CHECKA57: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesmc {{v[0-7].16b}}, [[VD]] -; CHECKA57: aesmc {{v[0-7].16b}}, [[VB]] -; CHECKA57: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesmc {{v[0-7].16b}}, [[VE]] -; CHECKA57: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesmc {{v[0-7].16b}}, [[VF]] -; CHECKA57: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesmc {{v[0-7].16b}}, [[VG]] -; CHECKA57: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesmc {{v[0-7].16b}}, [[VH]] -; CHECKA72: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VA]] -; CHECKA72: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VB]] -; CHECKA72: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VC]] -; CHECKA72: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VD]] -; CHECKA72: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VE]] -; CHECKA72: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VF]] -; CHECKA72: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VG]] -; CHECKA72: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesmc {{v[0-7].16b}}, [[VH]] +; CHECKA57A72: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesmc {{v[0-7].16b}}, [[VA]] +; CHECKA57A72: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesmc {{v[0-7].16b}}, [[VB]] +; CHECKA57A72: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesmc {{v[0-7].16b}}, [[VC]] +; CHECKA57A72: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesmc {{v[0-7].16b}}, [[VD]] +; CHECKA57A72: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesmc {{v[0-7].16b}}, [[VE]] +; CHECKA57A72: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesmc {{v[0-7].16b}}, [[VF]] +; CHECKA57A72: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesmc {{v[0-7].16b}}, [[VG]] +; CHECKA57A72: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesmc {{v[0-7].16b}}, [[VH]] + ; CHECKM1: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1: aesmc {{v[0-7].16b}}, [[VA]] +; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VA]] +; CHECKM1: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VB]] ; CHECKM1: aese {{v[0-7].16b}}, {{v[0-7].16b}} ; CHECKM1: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VC]] ; CHECKM1: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1: aesmc {{v[0-7].16b}}, [[VD]] +; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VD]] +; CHECKM1: aesmc {{v[0-7].16b}}, [[VH]] ; CHECKM1: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VE]] ; CHECKM1: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VF]] ; CHECKM1: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VG]] -; CHECKM1: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VH]] } define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, <16 x i8> %e) { @@ -188,53 +173,65 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, ret void ; CHECK-LABEL: aesda: -; CHECKA57: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesimc {{v[0-7].16b}}, [[VC]] -; CHECKA57: aesimc {{v[0-7].16b}}, [[VA]] -; CHECKA57: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesimc {{v[0-7].16b}}, [[VD]] -; CHECKA57: aesimc {{v[0-7].16b}}, [[VB]] -; CHECKA57: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesimc {{v[0-7].16b}}, [[VE]] -; CHECKA57: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesimc {{v[0-7].16b}}, [[VF]] -; CHECKA57: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesimc {{v[0-7].16b}}, [[VG]] -; CHECKA57: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA57-NEXT: aesimc {{v[0-7].16b}}, [[VH]] -; CHECKA72: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VA]] -; CHECKA72: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VB]] -; CHECKA72: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VC]] -; CHECKA72: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VD]] -; CHECKA72: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VE]] -; CHECKA72: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VF]] -; CHECKA72: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VG]] -; CHECKA72: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKA72-NEXT: aesimc {{v[0-7].16b}}, [[VH]] +; CHECKA57A72: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesimc {{v[0-7].16b}}, [[VA]] +; CHECKA57A72: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesimc {{v[0-7].16b}}, [[VB]] +; CHECKA57A72: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesimc {{v[0-7].16b}}, [[VC]] +; CHECKA57A72: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesimc {{v[0-7].16b}}, [[VD]] +; CHECKA57A72: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesimc {{v[0-7].16b}}, [[VE]] +; CHECKA57A72: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesimc {{v[0-7].16b}}, [[VF]] +; CHECKA57A72: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesimc {{v[0-7].16b}}, [[VG]] +; CHECKA57A72: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} +; CHECKA57A72-NEXT: aesimc {{v[0-7].16b}}, [[VH]] + ; CHECKM1: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1: aesimc {{v[0-7].16b}}, [[VA]] +; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VA]] +; CHECKM1: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VB]] ; CHECKM1: aesd {{v[0-7].16b}}, {{v[0-7].16b}} ; CHECKM1: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VC]] ; CHECKM1: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1: aesimc {{v[0-7].16b}}, [[VD]] +; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VD]] +; CHECKM1: aesimc {{v[0-7].16b}}, [[VH]] ; CHECKM1: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VE]] ; CHECKM1: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VF]] ; CHECKM1: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VG]] -; CHECKM1: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VH]] +} + +define void @aes_load_store(<16 x i8> *%p1, <16 x i8> *%p2 , <16 x i8> *%p3) { +entry: + %x1 = alloca <16 x i8>, align 16 + %x2 = alloca <16 x i8>, align 16 + %x3 = alloca <16 x i8>, align 16 + %x4 = alloca <16 x i8>, align 16 + %x5 = alloca <16 x i8>, align 16 + %in1 = load <16 x i8>, <16 x i8>* %p1, align 16 + store <16 x i8> %in1, <16 x i8>* %x1, align 16 + %aese1 = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %in1, <16 x i8> %in1) #2 + store <16 x i8> %aese1, <16 x i8>* %x2, align 16 + %in2 = load <16 x i8>, <16 x i8>* %p2, align 16 + %aesmc1= call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %aese1) #2 + store <16 x i8> %aesmc1, <16 x i8>* %x3, align 16 + %aese2 = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %in1, <16 x i8> %in2) #2 + store <16 x i8> %aese2, <16 x i8>* %x4, align 16 + %aesmc2= call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %aese2) #2 + store <16 x i8> %aesmc2, <16 x i8>* %x5, align 16 + ret void + +; CHECK-LABEL: aes_load_store: +; CHECK: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc {{v[0-7].16b}}, [[VA]] +; CHECK: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc {{v[0-7].16b}}, [[VB]] } diff --git a/test/CodeGen/AArch64/optimize-imm.ll b/test/CodeGen/AArch64/optimize-imm.ll index a4725c65aa26..f960a3a95fc9 100644 --- a/test/CodeGen/AArch64/optimize-imm.ll +++ b/test/CodeGen/AArch64/optimize-imm.ll @@ -62,3 +62,22 @@ entry: %and = xor i32 %xor, 56 ret i32 %and } + +; Check that, when (and %t1, 129) is transformed to (and %t0, 0), +; (xor %arg, 129) doesn't get transformed to (xor %arg, 0). +; +; CHECK-LABEL: PR33100: +; CHECK: mov w[[R0:[0-9]+]], #129 +; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, x[[R0]] + +define i64 @PR33100(i64 %arg) { +entry: + %alloca0 = alloca i64 + store i64 8, i64* %alloca0, align 4 + %t0 = load i64, i64* %alloca0, align 4 + %t1 = shl i64 %arg, %t0 + %and0 = and i64 %t1, 129 + %xor0 = xor i64 %arg, 129 + %t2 = add i64 %and0, %xor0 + ret i64 %t2 +} diff --git a/test/CodeGen/AArch64/scheduledag-constreg.mir b/test/CodeGen/AArch64/scheduledag-constreg.mir index 23c785504f01..6b83dc715e0a 100644 --- a/test/CodeGen/AArch64/scheduledag-constreg.mir +++ b/test/CodeGen/AArch64/scheduledag-constreg.mir @@ -1,4 +1,4 @@ -# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=misched 2>&1 | FileCheck %s +# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=machine-scheduler 2>&1 | FileCheck %s # REQUIRES: asserts --- | define void @func() { ret void } diff --git a/test/CodeGen/AArch64/tailcall_misched_graph.ll b/test/CodeGen/AArch64/tailcall_misched_graph.ll index 0e4eb2b5fad9..4fbd8944f032 100644 --- a/test/CodeGen/AArch64/tailcall_misched_graph.ll +++ b/test/CodeGen/AArch64/tailcall_misched_graph.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=cyclone -debug-only=misched < %s 2>&1 | FileCheck %s +; RUN: llc -mcpu=cyclone -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s ; REQUIRES: asserts diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir index 8839ba8e0ab2..0557008ceb4f 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir @@ -5,6 +5,11 @@ entry: ret void } + + define void @test_fconstant() { + entry: + ret void + } ... --- @@ -18,3 +23,18 @@ body: | %0(s32) = G_CONSTANT i32 5 ... + +--- +name: test_fconstant +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0.entry: + ; CHECK-LABEL: name: test_fconstant + ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00 + ; CHECK: %1(s32) = G_FCONSTANT float 7.5 + + %0(s32) = G_FCONSTANT float 1.0 + %1(s32) = G_FCONSTANT float 7.5 +... diff --git a/test/CodeGen/AMDGPU/bfe-combine.ll b/test/CodeGen/AMDGPU/bfe-combine.ll new file mode 100644 index 000000000000..791b49f0e143 --- /dev/null +++ b/test/CodeGen/AMDGPU/bfe-combine.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI %s +; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck --check-prefix=GCN --check-prefix=CI %s + +; GCN-LABEL: {{^}}bfe_combine8: +; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8 +; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], 2, v[[BFE]] +; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 6, v{{[0-9]+}} +; CI: v_and_b32_e32 v[[ADDRLO:[0-9]+]], 0x3fc, v[[SHR]] +; VI: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] +; GCN: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: +define amdgpu_kernel void @bfe_combine8(i32 addrspace(1)* nocapture %arg, i32 %x) { + %id = tail call i32 @llvm.amdgcn.workitem.id.x() #2 + %idx = add i32 %x, %id + %srl = lshr i32 %idx, 8 + %and = and i32 %srl, 255 + %ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %and + %val = load i32, i32 addrspace(1)* %ptr, align 4 + store i32 %val, i32 addrspace(1)* %arg, align 4 + ret void +} + +; GCN-LABEL: {{^}}bfe_combine16: +; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 16, 16 +; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], {{[^,]+}}, v[[BFE]] +; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 1, v{{[0-9]+}} +; CI: v_and_b32_e32 v[[AND:[0-9]+]], 0x7fff8000, v[[SHR]] +; CI: v_lshl_b64 v{{\[}}[[ADDRLO:[0-9]+]]:{{[^\]+}}], v{{\[}}[[AND]]:{{[^\]+}}], 2 +; VI: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]] +; GCN: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: +define amdgpu_kernel void @bfe_combine16(i32 addrspace(1)* nocapture %arg, i32 %x) { + %id = tail call i32 @llvm.amdgcn.workitem.id.x() #2 + %idx = add i32 %x, %id + %srl = lshr i32 %idx, 1 + %and = and i32 %srl, 2147450880 + %ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %and + %val = load i32, i32 addrspace(1)* %ptr, align 4 + store i32 %val, i32 addrspace(1)* %arg, align 4 + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #1 diff --git a/test/CodeGen/AMDGPU/extload-align.ll b/test/CodeGen/AMDGPU/extload-align.ll index 4644800421d8..12cf27b918af 100644 --- a/test/CodeGen/AMDGPU/extload-align.ll +++ b/test/CodeGen/AMDGPU/extload-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -debug-only=misched -march=amdgcn -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s +; RUN: llc -debug-only=machine-scheduler -march=amdgcn -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s ; REQUIRES: asserts ; Verify that the extload generated from %eval has the default @@ -20,4 +20,4 @@ define amdgpu_kernel void @extload_align(i32* %out, i32 %index) #0 { %eval = sext i16 %val to i32 store i32 %eval, i32* %out ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AMDGPU/kernel-args.ll b/test/CodeGen/AMDGPU/kernel-args.ll index 6fa26cb38793..9441bf208829 100644 --- a/test/CodeGen/AMDGPU/kernel-args.ll +++ b/test/CodeGen/AMDGPU/kernel-args.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GCN,MESA-GCN,FUNC ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs | FileCheck %s --check-prefixes=VI,GCN,HSA-VI,FUNC -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC +; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefix=EG --check-prefix=FUNC +; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; FUNC-LABEL: {{^}}i8_arg: ; HSA-VI: kernarg_segment_alignment = 4 diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll new file mode 100644 index 000000000000..22e15e216805 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare i64 @llvm.amdgcn.s.getpc() #0 + +; GCN-LABEL: {{^}}test_s_getpc: +; GCN: s_load_dwordx2 +; GCN-DAG: s_getpc_b64 s{{\[[0-9]+:[0-9]+\]}} +; GCN: buffer_store_dwordx2 +define amdgpu_kernel void @test_s_getpc(i64 addrspace(1)* %out) #0 { + %tmp = call i64 @llvm.amdgcn.s.getpc() #1 + store volatile i64 %tmp, i64 addrspace(1)* %out, align 8 + ret void +} + +attributes #0 = { nounwind readnone speculatable } diff --git a/test/CodeGen/AMDGPU/load-constant-i16.ll b/test/CodeGen/AMDGPU/load-constant-i16.ll index 5dd2efdf6382..72fde04ba391 100644 --- a/test/CodeGen/AMDGPU/load-constant-i16.ll +++ b/test/CodeGen/AMDGPU/load-constant-i16.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}constant_load_i16: ; GCN-NOHSA: buffer_load_ushort v{{[0-9]+}} diff --git a/test/CodeGen/AMDGPU/load-constant-i8.ll b/test/CodeGen/AMDGPU/load-constant-i8.ll index 6e56b9f9b6d6..bdfc3caf9d01 100644 --- a/test/CodeGen/AMDGPU/load-constant-i8.ll +++ b/test/CodeGen/AMDGPU/load-constant-i8.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}constant_load_i8: diff --git a/test/CodeGen/AMDGPU/load-global-i16.ll b/test/CodeGen/AMDGPU/load-global-i16.ll index dcdd1a947cd4..e3415b9c47de 100644 --- a/test/CodeGen/AMDGPU/load-global-i16.ll +++ b/test/CodeGen/AMDGPU/load-global-i16.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-HSA,FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=EGCM -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=EGCM -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=EGCM -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=EGCM -check-prefix=FUNC %s ; FIXME: r600 is broken because the bigger testcases spill and it's not implemented diff --git a/test/CodeGen/AMDGPU/load-global-i8.ll b/test/CodeGen/AMDGPU/load-global-i8.ll index 71adf090532f..fc0cbf916b52 100644 --- a/test/CodeGen/AMDGPU/load-global-i8.ll +++ b/test/CodeGen/AMDGPU/load-global-i8.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,SI,FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-HSA,SI,FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,VI,FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}global_load_i8: diff --git a/test/CodeGen/AMDGPU/load-local-i16.ll b/test/CodeGen/AMDGPU/load-local-i16.ll index bbbb34e8d333..7de3f3b28c6d 100644 --- a/test/CodeGen/AMDGPU/load-local-i16.ll +++ b/test/CodeGen/AMDGPU/load-local-i16.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}local_load_i16: ; GCN: ds_read_u16 v{{[0-9]+}} diff --git a/test/CodeGen/AMDGPU/load-local-i8.ll b/test/CodeGen/AMDGPU/load-local-i8.ll index 731996ec6c45..16eb366a4b15 100644 --- a/test/CodeGen/AMDGPU/load-local-i8.ll +++ b/test/CodeGen/AMDGPU/load-local-i8.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}local_load_i8: diff --git a/test/CodeGen/AMDGPU/min.ll b/test/CodeGen/AMDGPU/min.ll index e85a724c1567..60e43f8fb2a7 100644 --- a/test/CodeGen/AMDGPU/min.ll +++ b/test/CodeGen/AMDGPU/min.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}v_test_imin_sle_i32: ; GCN: v_min_i32_e32 diff --git a/test/CodeGen/AMDGPU/parallelandifcollapse.ll b/test/CodeGen/AMDGPU/parallelandifcollapse.ll index a90f200f79e3..190d2b72ebaf 100644 --- a/test/CodeGen/AMDGPU/parallelandifcollapse.ll +++ b/test/CodeGen/AMDGPU/parallelandifcollapse.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck %s +; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck %s ; ; CFG flattening should use parallel-and mode to generate branch conditions and ; then merge if-regions with the same bodies. diff --git a/test/CodeGen/AMDGPU/r600.bitcast.ll b/test/CodeGen/AMDGPU/r600.bitcast.ll index acf7a66a357f..67431e6a4825 100644 --- a/test/CodeGen/AMDGPU/r600.bitcast.ll +++ b/test/CodeGen/AMDGPU/r600.bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; This test just checks that the compiler doesn't crash. diff --git a/test/CodeGen/AMDGPU/schedule-regpressure.mir b/test/CodeGen/AMDGPU/schedule-regpressure.mir index c71de87eeece..3a20ec732e5b 100644 --- a/test/CodeGen/AMDGPU/schedule-regpressure.mir +++ b/test/CodeGen/AMDGPU/schedule-regpressure.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -misched=converge -run-pass machine-scheduler %s -o - -debug-only=misched 2>&1 | FileCheck %s +# RUN: llc -march=amdgcn -misched=converge -run-pass machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s # REQUIRES: asserts # Check there is no SReg_32 pressure created by DS_* instructions because of M0 use diff --git a/test/CodeGen/AMDGPU/setcc.ll b/test/CodeGen/AMDGPU/setcc.ll index add90e9c2f3a..f63719d62a84 100644 --- a/test/CodeGen/AMDGPU/setcc.ll +++ b/test/CodeGen/AMDGPU/setcc.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s declare i32 @llvm.r600.read.tidig.x() nounwind readnone diff --git a/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll b/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll new file mode 100644 index 000000000000..1cdfec9fdb59 --- /dev/null +++ b/test/CodeGen/AMDGPU/shl-add-to-add-shl.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck %s + +; Check transformation shl (or|add x, c2), c1 => or|add (shl x, c1), (c2 << c1) +; Only one shift if expected, GEP shall not produce a separate shift + +; CHECK-LABEL: {{^}}add_const_offset: +; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0 +; CHECK: v_add_i32_e32 v[[ADD:[0-9]+]], vcc, 0xc80, v[[SHL]] +; CHECK-NOT: v_lshl +; CHECK: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADD]] +; CHECK: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: +define amdgpu_kernel void @add_const_offset(i32 addrspace(1)* nocapture %arg) { +bb: + %id = tail call i32 @llvm.amdgcn.workitem.id.x() + %add = add i32 %id, 200 + %shl = shl i32 %add, 2 + %ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %shl + %val = load i32, i32 addrspace(1)* %ptr, align 4 + store i32 %val, i32 addrspace(1)* %arg, align 4 + ret void +} + +; CHECK-LABEL: {{^}}or_const_offset: +; CHECK: v_lshlrev_b32_e32 v[[SHL:[0-9]+]], 4, v0 +; CHECK: v_or_b32_e32 v[[OR:[0-9]+]], 0x1000, v[[SHL]] +; CHECK-NOT: v_lshl +; CHECK: v_add_i32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[OR]] +; CHECK: load_dword v{{[0-9]+}}, v{{\[}}[[ADDRLO]]: +define amdgpu_kernel void @or_const_offset(i32 addrspace(1)* nocapture %arg) { +bb: + %id = tail call i32 @llvm.amdgcn.workitem.id.x() + %add = or i32 %id, 256 + %shl = shl i32 %add, 2 + %ptr = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %shl + %val = load i32, i32 addrspace(1)* %ptr, align 4 + store i32 %val, i32 addrspace(1)* %arg, align 4 + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() diff --git a/test/CodeGen/AMDGPU/shl.ll b/test/CodeGen/AMDGPU/shl.ll index ff666cc3653b..edc313ee323b 100644 --- a/test/CodeGen/AMDGPU/shl.ll +++ b/test/CodeGen/AMDGPU/shl.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare i32 @llvm.r600.read.tidig.x() #0 diff --git a/test/CodeGen/AMDGPU/sra.ll b/test/CodeGen/AMDGPU/sra.ll index b4355b76016a..44cfdf6398ae 100644 --- a/test/CodeGen/AMDGPU/sra.ll +++ b/test/CodeGen/AMDGPU/sra.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare i32 @llvm.r600.read.tidig.x() #0 diff --git a/test/CodeGen/AMDGPU/store-global.ll b/test/CodeGen/AMDGPU/store-global.ll index 160e921fc075..f61e524ee2e5 100644 --- a/test/CodeGen/AMDGPU/store-global.ll +++ b/test/CodeGen/AMDGPU/store-global.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}store_i1: ; EG: MEM_RAT MSKOR diff --git a/test/CodeGen/AMDGPU/store-private.ll b/test/CodeGen/AMDGPU/store-private.ll index ab73ada370ea..ce7656adc0b4 100644 --- a/test/CodeGen/AMDGPU/store-private.ll +++ b/test/CodeGen/AMDGPU/store-private.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}store_i1: ; EG: MOVA_INT diff --git a/test/CodeGen/AMDGPU/sub.ll b/test/CodeGen/AMDGPU/sub.ll index f366029fdea2..e7655df15520 100644 --- a/test/CodeGen/AMDGPU/sub.ll +++ b/test/CodeGen/AMDGPU/sub.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare i32 @llvm.r600.read.tidig.x() readnone diff --git a/test/CodeGen/AMDGPU/unknown-processor.ll b/test/CodeGen/AMDGPU/unknown-processor.ll index 25a700a943d2..e25f2235993f 100644 --- a/test/CodeGen/AMDGPU/unknown-processor.ll +++ b/test/CodeGen/AMDGPU/unknown-processor.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=unknown < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s -; RUN: llc -march=r600 -mcpu=unknown < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s +; RUN: llc -march=amdgcn -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s +; RUN: llc -march=r600 -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s ; Should not crash when the processor is not recognized and the ; wavefront size feature not set. diff --git a/test/CodeGen/AMDGPU/vector-alloca.ll b/test/CodeGen/AMDGPU/vector-alloca.ll index 03cf725601b7..a0aac8c1d9ba 100644 --- a/test/CodeGen/AMDGPU/vector-alloca.ll +++ b/test/CodeGen/AMDGPU/vector-alloca.ll @@ -138,3 +138,25 @@ entry: store float %tmp2, float addrspace(1)* %out ret void } + +; The pointer arguments in local address space should not affect promotion to vector. + +; OPT-LABEL: @vector_read_with_local_arg( +; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index +; OPT: store i32 %0, i32 addrspace(1)* %out, align 4 +define amdgpu_kernel void @vector_read_with_local_arg(i32 addrspace(3)* %stopper, i32 addrspace(1)* %out, i32 %index) { +entry: + %tmp = alloca [4 x i32] + %x = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0 + %y = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 1 + %z = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 2 + %w = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3 + store i32 0, i32* %x + store i32 1, i32* %y + store i32 2, i32* %z + store i32 3, i32* %w + %tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 %index + %tmp2 = load i32, i32* %tmp1 + store i32 %tmp2, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll index 1a0c7fd8e1d6..f4aba880ff76 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -620,6 +620,360 @@ entry: ret float %r } +declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32]) + +define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) { +; CHECK-LABEL: name: test_tiny_int_arrays +; CHECK: liveins: %r0, %r1 +; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 +; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 +; CHECK: [[ARG_ARR0:%[0-9]+]](s64) = IMPLICIT_DEF +; CHECK: [[ARG_ARR1:%[0-9]+]](s64) = G_INSERT [[ARG_ARR0]], [[R0]](s32), 0 +; CHECK: [[ARG_ARR2:%[0-9]+]](s64) = G_INSERT [[ARG_ARR1]], [[R1]](s32), 32 +; CHECK: [[ARG_ARR:%[0-9]+]](s64) = COPY [[ARG_ARR2]] +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s64), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s64), 32 +; CHECK: %r0 = COPY [[R0]] +; CHECK: %r1 = COPY [[R1]] +; CHECK: BLX @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 +; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 +; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 +; CHECK: [[R2:%[0-9]+]](s32) = COPY %r2 +; CHECK: [[RES_ARR0:%[0-9]+]](s96) = IMPLICIT_DEF +; CHECK: [[RES_ARR1:%[0-9]+]](s96) = G_INSERT [[RES_ARR0]], [[R0]](s32), 0 +; CHECK: [[RES_ARR2:%[0-9]+]](s96) = G_INSERT [[RES_ARR1]], [[R1]](s32), 32 +; CHECK: [[RES_ARR3:%[0-9]+]](s96) = G_INSERT [[RES_ARR2]], [[R2]](s32), 64 +; CHECK: [[RES_ARR:%[0-9]+]](s96) = COPY [[RES_ARR3]] +; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 32 +; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 64 +; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say +; that composite types larger than 4 bytes should be passed through memory), +; but it's what DAGISel does. We should fix it in the common code for both. +; CHECK: %r0 = COPY [[R0]] +; CHECK: %r1 = COPY [[R1]] +; CHECK: %r2 = COPY [[R2]] +; CHECK: BX_RET 14, _, implicit %r0, implicit %r1, implicit %r2 +entry: + %r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr) + ret [3 x i32] %r +} + +declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32]) + +define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) { +; CHECK-LABEL: name: test_multiple_int_arrays +; CHECK: liveins: %r0, %r1 +; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 +; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 +; CHECK: [[R2:%[0-9]+]](s32) = COPY %r2 +; CHECK: [[R3:%[0-9]+]](s32) = COPY %r3 +; CHECK: [[ARG_ARR0_0:%[0-9]+]](s64) = IMPLICIT_DEF +; CHECK: [[ARG_ARR0_1:%[0-9]+]](s64) = G_INSERT [[ARG_ARR0_0]], [[R0]](s32), 0 +; CHECK: [[ARG_ARR0_2:%[0-9]+]](s64) = G_INSERT [[ARG_ARR0_1]], [[R1]](s32), 32 +; CHECK: [[ARG_ARR0:%[0-9]+]](s64) = COPY [[ARG_ARR0_2]] +; CHECK: [[ARG_ARR1_0:%[0-9]+]](s64) = IMPLICIT_DEF +; CHECK: [[ARG_ARR1_1:%[0-9]+]](s64) = G_INSERT [[ARG_ARR1_0]], [[R2]](s32), 0 +; CHECK: [[ARG_ARR1_2:%[0-9]+]](s64) = G_INSERT [[ARG_ARR1_1]], [[R3]](s32), 32 +; CHECK: [[ARG_ARR1:%[0-9]+]](s64) = COPY [[ARG_ARR1_2]] +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR0]](s64), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR0]](s64), 32 +; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR1]](s64), 0 +; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR1]](s64), 32 +; CHECK: %r0 = COPY [[R0]] +; CHECK: %r1 = COPY [[R1]] +; CHECK: %r2 = COPY [[R2]] +; CHECK: %r3 = COPY [[R3]] +; CHECK: BLX @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 +; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: BX_RET 14, _ +entry: + notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1) + ret void +} + +declare arm_aapcscc void @large_int_arrays_target([20 x i32]) + +define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) { +; CHECK-LABEL: name: test_large_int_arrays +; CHECK: fixedStack: +; The parameters live in separate stack locations, one for each element that +; doesn't fit in the registers. +; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], offset: 0, size: 4 +; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], offset: 60, size: 4 +; CHECK: liveins: %r0, %r1, %r2, %r3 +; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0 +; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1 +; CHECK-DAG: [[R2:%[0-9]+]](s32) = COPY %r2 +; CHECK-DAG: [[R3:%[0-9]+]](s32) = COPY %r3 +; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]] +; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] +; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] +; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] +; CHECK: [[ARG_ARR0:%[0-9]+]](s640) = IMPLICIT_DEF +; CHECK: [[ARG_ARR1:%[0-9]+]](s640) = G_INSERT [[ARG_ARR0]], [[R0]](s32), 0 +; CHECK: [[ARG_ARR2:%[0-9]+]](s640) = G_INSERT [[ARG_ARR1]], [[R1]](s32), 32 +; CHECK: [[ARG_ARR3:%[0-9]+]](s640) = G_INSERT [[ARG_ARR2]], [[R2]](s32), 64 +; CHECK: [[ARG_ARR4:%[0-9]+]](s640) = G_INSERT [[ARG_ARR3]], [[R3]](s32), 96 +; CHECK: [[ARG_ARR5:%[0-9]+]](s640) = G_INSERT [[ARG_ARR4]], [[FIRST_STACK_ELEMENT]](s32), 128 +; CHECK: [[ARG_ARR6:%[0-9]+]](s640) = G_INSERT {{%[0-9]+}}, [[LAST_STACK_ELEMENT]](s32), 608 +; CHECK: [[ARG_ARR:%[0-9]+]](s640) = COPY [[ARG_ARR6]] +; CHECK: ADJCALLSTACKDOWN 64, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 32 +; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 64 +; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 96 +; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 128 +; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 608 +; CHECK: %r0 = COPY [[R0]] +; CHECK: %r1 = COPY [[R1]] +; CHECK: %r2 = COPY [[R2]] +; CHECK: %r3 = COPY [[R3]] +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 0 +; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32) +; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4 +; Match the second-to-last offset, so we can get the correct SP for the last element +; CHECK: G_CONSTANT i32 56 +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 60 +; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32) +; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 +; CHECK: BLX @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 +; CHECK: ADJCALLSTACKUP 64, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: BX_RET 14, _ +entry: + notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr) + ret void +} + +declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double]) + +define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) { +; CHECK-LABEL: name: test_fp_arrays_aapcs +; CHECK: fixedStack: +; CHECK: id: [[ARR2_ID:[0-9]+]], offset: 0, size: 8 +; CHECK: liveins: %r0, %r1, %r2, %r3 +; CHECK: [[ARR0_0:%[0-9]+]](s32) = COPY %r0 +; CHECK: [[ARR0_1:%[0-9]+]](s32) = COPY %r1 +; LITTLE: [[ARR0:%[0-9]+]](s64) = G_SEQUENCE [[ARR0_0]](s32), 0, [[ARR0_1]](s32), 32 +; BIG: [[ARR0:%[0-9]+]](s64) = G_SEQUENCE [[ARR0_1]](s32), 0, [[ARR0_0]](s32), 32 +; CHECK: [[ARR1_0:%[0-9]+]](s32) = COPY %r2 +; CHECK: [[ARR1_1:%[0-9]+]](s32) = COPY %r3 +; LITTLE: [[ARR1:%[0-9]+]](s64) = G_SEQUENCE [[ARR1_0]](s32), 0, [[ARR1_1]](s32), 32 +; BIG: [[ARR1:%[0-9]+]](s64) = G_SEQUENCE [[ARR1_1]](s32), 0, [[ARR1_0]](s32), 32 +; CHECK: [[ARR2_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]] +; CHECK: [[ARR2:%[0-9]+]](s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]] +; CHECK: [[ARR_MERGED_0:%[0-9]+]](s192) = IMPLICIT_DEF +; CHECK: [[ARR_MERGED_1:%[0-9]+]](s192) = G_INSERT [[ARR_MERGED_0]], [[ARR0]](s64), 0 +; CHECK: [[ARR_MERGED_2:%[0-9]+]](s192) = G_INSERT [[ARR_MERGED_1]], [[ARR1]](s64), 64 +; CHECK: [[ARR_MERGED_3:%[0-9]+]](s192) = G_INSERT [[ARR_MERGED_2]], [[ARR2]](s64), 128 +; CHECK: [[ARR_MERGED:%[0-9]+]](s192) = COPY [[ARR_MERGED_3]] +; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[ARR0:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 0 +; CHECK: [[ARR1:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 64 +; CHECK: [[ARR2:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 128 +; CHECK: [[ARR0_0:%[0-9]+]](s32) = G_EXTRACT [[ARR0]](s64), 0 +; CHECK: [[ARR0_1:%[0-9]+]](s32) = G_EXTRACT [[ARR0]](s64), 32 +; LITTLE: %r0 = COPY [[ARR0_0]](s32) +; LITTLE: %r1 = COPY [[ARR0_1]](s32) +; BIG: %r0 = COPY [[ARR0_1]](s32) +; BIG: %r1 = COPY [[ARR0_0]](s32) +; CHECK: [[ARR1_0:%[0-9]+]](s32) = G_EXTRACT [[ARR1]](s64), 0 +; CHECK: [[ARR1_1:%[0-9]+]](s32) = G_EXTRACT [[ARR1]](s64), 32 +; LITTLE: %r2 = COPY [[ARR1_0]](s32) +; LITTLE: %r3 = COPY [[ARR1_1]](s32) +; BIG: %r2 = COPY [[ARR1_1]](s32) +; BIG: %r3 = COPY [[ARR1_0]](s32) +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[ARR2_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 0 +; CHECK: [[ARR2_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32) +; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8 +; CHECK: BLX @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 +; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 +; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 +; CHECK: [[R_MERGED_0:%[0-9]+]](s64) = IMPLICIT_DEF +; CHECK: [[R_MERGED_1:%[0-9]+]](s64) = G_INSERT [[R_MERGED_0]], [[R0]](s32), 0 +; CHECK: [[R_MERGED_2:%[0-9]+]](s64) = G_INSERT [[R_MERGED_1]], [[R1]](s32), 32 +; CHECK: [[R_MERGED:%[0-9]+]](s64) = COPY [[R_MERGED_2]] +; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s64), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s64), 32 +; CHECK: %r0 = COPY [[R0]] +; CHECK: %r1 = COPY [[R1]] +; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +entry: + %r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr) + ret [2 x float] %r +} + +declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double]) + +define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) { +; CHECK-LABEL: name: test_fp_arrays_aapcs_vfp +; CHECK: fixedStack: +; CHECK-DAG: id: [[Z0_ID:[0-9]+]], offset: 0, size: 8 +; CHECK-DAG: id: [[Z1_ID:[0-9]+]], offset: 8, size: 8 +; CHECK-DAG: id: [[Z2_ID:[0-9]+]], offset: 16, size: 8 +; CHECK-DAG: id: [[Z3_ID:[0-9]+]], offset: 24, size: 8 +; CHECK: liveins: %d0, %d1, %d2, %s6, %s7, %s8 +; CHECK: [[X0:%[0-9]+]](s64) = COPY %d0 +; CHECK: [[X1:%[0-9]+]](s64) = COPY %d1 +; CHECK: [[X2:%[0-9]+]](s64) = COPY %d2 +; CHECK: [[Y0:%[0-9]+]](s32) = COPY %s6 +; CHECK: [[Y1:%[0-9]+]](s32) = COPY %s7 +; CHECK: [[Y2:%[0-9]+]](s32) = COPY %s8 +; CHECK: [[Z0_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]] +; CHECK: [[Z0:%[0-9]+]](s64) = G_LOAD [[Z0_FI]]{{.*}}load 8 +; CHECK: [[Z1_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]] +; CHECK: [[Z1:%[0-9]+]](s64) = G_LOAD [[Z1_FI]]{{.*}}load 8 +; CHECK: [[Z2_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]] +; CHECK: [[Z2:%[0-9]+]](s64) = G_LOAD [[Z2_FI]]{{.*}}load 8 +; CHECK: [[Z3_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]] +; CHECK: [[Z3:%[0-9]+]](s64) = G_LOAD [[Z3_FI]]{{.*}}load 8 +; CHECK: [[X_ARR_0:%[0-9]+]](s192) = IMPLICIT_DEF +; CHECK: [[X_ARR_1:%[0-9]+]](s192) = G_INSERT [[X_ARR_0]], [[X0]](s64), 0 +; CHECK: [[X_ARR_2:%[0-9]+]](s192) = G_INSERT [[X_ARR_1]], [[X1]](s64), 64 +; CHECK: [[X_ARR_3:%[0-9]+]](s192) = G_INSERT [[X_ARR_2]], [[X2]](s64), 128 +; CHECK: [[X_ARR:%[0-9]+]](s192) = COPY [[X_ARR_3]](s192) +; CHECK: [[Y_ARR_0:%[0-9]+]](s96) = IMPLICIT_DEF +; CHECK: [[Y_ARR_1:%[0-9]+]](s96) = G_INSERT [[Y_ARR_0]], [[Y0]](s32), 0 +; CHECK: [[Y_ARR_2:%[0-9]+]](s96) = G_INSERT [[Y_ARR_1]], [[Y1]](s32), 32 +; CHECK: [[Y_ARR_3:%[0-9]+]](s96) = G_INSERT [[Y_ARR_2]], [[Y2]](s32), 64 +; CHECK: [[Y_ARR:%[0-9]+]](s96) = COPY [[Y_ARR_3]](s96) +; CHECK: [[Z_ARR_0:%[0-9]+]](s256) = IMPLICIT_DEF +; CHECK: [[Z_ARR_1:%[0-9]+]](s256) = G_INSERT [[Z_ARR_0]], [[Z0]](s64), 0 +; CHECK: [[Z_ARR_2:%[0-9]+]](s256) = G_INSERT [[Z_ARR_1]], [[Z1]](s64), 64 +; CHECK: [[Z_ARR_3:%[0-9]+]](s256) = G_INSERT [[Z_ARR_2]], [[Z2]](s64), 128 +; CHECK: [[Z_ARR_4:%[0-9]+]](s256) = G_INSERT [[Z_ARR_3]], [[Z3]](s64), 192 +; CHECK: [[Z_ARR:%[0-9]+]](s256) = COPY [[Z_ARR_4]](s256) +; CHECK: ADJCALLSTACKDOWN 32, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[X0:%[0-9]+]](s64) = G_EXTRACT [[X_ARR]](s192), 0 +; CHECK: [[X1:%[0-9]+]](s64) = G_EXTRACT [[X_ARR]](s192), 64 +; CHECK: [[X2:%[0-9]+]](s64) = G_EXTRACT [[X_ARR]](s192), 128 +; CHECK: [[Y0:%[0-9]+]](s32) = G_EXTRACT [[Y_ARR]](s96), 0 +; CHECK: [[Y1:%[0-9]+]](s32) = G_EXTRACT [[Y_ARR]](s96), 32 +; CHECK: [[Y2:%[0-9]+]](s32) = G_EXTRACT [[Y_ARR]](s96), 64 +; CHECK: [[Z0:%[0-9]+]](s64) = G_EXTRACT [[Z_ARR]](s256), 0 +; CHECK: [[Z1:%[0-9]+]](s64) = G_EXTRACT [[Z_ARR]](s256), 64 +; CHECK: [[Z2:%[0-9]+]](s64) = G_EXTRACT [[Z_ARR]](s256), 128 +; CHECK: [[Z3:%[0-9]+]](s64) = G_EXTRACT [[Z_ARR]](s256), 192 +; CHECK: %d0 = COPY [[X0]](s64) +; CHECK: %d1 = COPY [[X1]](s64) +; CHECK: %d2 = COPY [[X2]](s64) +; CHECK: %s6 = COPY [[Y0]](s32) +; CHECK: %s7 = COPY [[Y1]](s32) +; CHECK: %s8 = COPY [[Y2]](s32) +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[Z0_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 0 +; CHECK: [[Z0_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z0_OFFSET]](s32) +; CHECK: G_STORE [[Z0]](s64), [[Z0_ADDR]](p0){{.*}}store 8 +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[Z1_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 8 +; CHECK: [[Z1_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z1_OFFSET]](s32) +; CHECK: G_STORE [[Z1]](s64), [[Z1_ADDR]](p0){{.*}}store 8 +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[Z2_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 16 +; CHECK: [[Z2_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z2_OFFSET]](s32) +; CHECK: G_STORE [[Z2]](s64), [[Z2_ADDR]](p0){{.*}}store 8 +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[Z3_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 24 +; CHECK: [[Z3_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32) +; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8 +; CHECK: BLX @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3 +; CHECK: [[R0:%[0-9]+]](s32) = COPY %s0 +; CHECK: [[R1:%[0-9]+]](s32) = COPY %s1 +; CHECK: [[R2:%[0-9]+]](s32) = COPY %s2 +; CHECK: [[R3:%[0-9]+]](s32) = COPY %s3 +; CHECK: [[R_MERGED_0:%[0-9]+]](s128) = IMPLICIT_DEF +; CHECK: [[R_MERGED_1:%[0-9]+]](s128) = G_INSERT [[R_MERGED_0]], [[R0]](s32), 0 +; CHECK: [[R_MERGED_2:%[0-9]+]](s128) = G_INSERT [[R_MERGED_1]], [[R1]](s32), 32 +; CHECK: [[R_MERGED_3:%[0-9]+]](s128) = G_INSERT [[R_MERGED_2]], [[R2]](s32), 64 +; CHECK: [[R_MERGED_4:%[0-9]+]](s128) = G_INSERT [[R_MERGED_3]], [[R3]](s32), 96 +; CHECK: [[R_MERGED:%[0-9]+]](s128) = COPY [[R_MERGED_4]] +; CHECK: ADJCALLSTACKUP 32, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 32 +; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 64 +; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 96 +; CHECK: %s0 = COPY [[R0]] +; CHECK: %s1 = COPY [[R1]] +; CHECK: %s2 = COPY [[R2]] +; CHECK: %s3 = COPY [[R3]] +; CHECK: BX_RET 14, _, implicit %s0, implicit %s1, implicit %s2, implicit %s3 +entry: + %r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z) + ret [4 x float] %r +} + +declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr) + +define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) { +; CHECK-LABEL: name: test_tough_arrays +; CHECK: fixedStack: +; The parameters live in separate stack locations, one for each element that +; doesn't fit in the registers. +; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], offset: 0, size: 4 +; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], offset: 76, size: 4 +; CHECK: liveins: %r0, %r1, %r2, %r3 +; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0 +; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1 +; CHECK-DAG: [[R2:%[0-9]+]](s32) = COPY %r2 +; CHECK-DAG: [[R3:%[0-9]+]](s32) = COPY %r3 +; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]] +; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] +; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] +; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] +; CHECK: [[ARG_ARR0:%[0-9]+]](s768) = IMPLICIT_DEF +; CHECK: [[ARG_ARR1:%[0-9]+]](s768) = G_INSERT [[ARG_ARR0]], [[R0]](s32), 0 +; CHECK: [[ARG_ARR2:%[0-9]+]](s768) = G_INSERT [[ARG_ARR1]], [[R1]](s32), 32 +; CHECK: [[ARG_ARR3:%[0-9]+]](s768) = G_INSERT [[ARG_ARR2]], [[R2]](s32), 64 +; CHECK: [[ARG_ARR4:%[0-9]+]](s768) = G_INSERT [[ARG_ARR3]], [[R3]](s32), 96 +; CHECK: [[ARG_ARR5:%[0-9]+]](s768) = G_INSERT [[ARG_ARR4]], [[FIRST_STACK_ELEMENT]](s32), 128 +; CHECK: [[ARG_ARR6:%[0-9]+]](s768) = G_INSERT {{%[0-9]+}}, [[LAST_STACK_ELEMENT]](s32), 736 +; CHECK: [[ARG_ARR:%[0-9]+]](s768) = COPY [[ARG_ARR6]] +; CHECK: ADJCALLSTACKDOWN 80, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 32 +; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 64 +; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 96 +; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 128 +; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 736 +; CHECK: %r0 = COPY [[R0]] +; CHECK: %r1 = COPY [[R1]] +; CHECK: %r2 = COPY [[R2]] +; CHECK: %r3 = COPY [[R3]] +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 0 +; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32) +; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4 +; Match the second-to-last offset, so we can get the correct SP for the last element +; CHECK: G_CONSTANT i32 72 +; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp +; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 76 +; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32) +; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 +; CHECK: BLX @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 +; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 +; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 +; CHECK: [[RES_ARR0:%[0-9]+]](s64) = IMPLICIT_DEF +; CHECK: [[RES_ARR1:%[0-9]+]](s64) = G_INSERT [[RES_ARR0]], [[R0]](s32), 0 +; CHECK: [[RES_ARR2:%[0-9]+]](s64) = G_INSERT [[RES_ARR1]], [[R1]](s32), 32 +; CHECK: [[RES_ARR:%[0-9]+]](s64) = COPY [[RES_ARR2]] +; CHECK: ADJCALLSTACKUP 80, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s64), 0 +; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s64), 32 +; CHECK: %r0 = COPY [[R0]] +; CHECK: %r1 = COPY [[R1]] +; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +entry: + %r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr) + ret [2 x i32*] %r +} + define i32 @test_shufflevector_s32_v2s32(i32 %arg) { ; CHECK-LABEL: name: test_shufflevector_s32_v2s32 ; CHECK: [[ARG:%[0-9]+]](s32) = COPY %r0 diff --git a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll index e3680ed2b929..ef30cb1063f8 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll @@ -45,11 +45,13 @@ define half @test_half(half %a, half %b) { ret half %res } -; On ARM, clang lowers structs to arrays. -define void @test_arrays([2 x i32] %this.could.come.from.a.struct) { -; CHECK: remark: {{.*}} unable to lower arguments: void ([2 x i32])* -; CHECK-LABEL: warning: Instruction selection used fallback path for test_arrays - ret void +declare [16 x i32] @ret_demotion_target() + +define [16 x i32] @test_ret_demotion() { +; CHECK: remark: {{.*}} unable to translate instruction: call{{.*}} @ret_demotion_target +; CHECK-LABEL: warning: Instruction selection used fallback path for test_ret_demotion + %res = call [16 x i32] @ret_demotion_target() + ret [16 x i32] %res } define void @test_structs({i32, i32} %struct) { diff --git a/test/CodeGen/ARM/arm-shrink-wrapping.ll b/test/CodeGen/ARM/arm-shrink-wrapping.ll index 9cce19417047..1985ff9b4a27 100644 --- a/test/CodeGen/ARM/arm-shrink-wrapping.ll +++ b/test/CodeGen/ARM/arm-shrink-wrapping.ll @@ -656,6 +656,9 @@ declare double @llvm.pow.f64(double, double) ; ; DISABLE: pop ; +; FIXME: This is flakey passing by finding 'bl' somewhere amongst the debug +; info (like labels named 'line_table) not because it's found a bl instruction. +; ; CHECK: bl define float @debug_info(float %gamma, float %slopeLimit, i1 %or.cond, double %tmp) "no-frame-pointer-elim"="true" { bb: @@ -681,7 +684,9 @@ bb13: ; preds = %bb3, %bb !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3} -!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "LLVM", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "LLVM", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !4, globals: !2, imports: !2) !1 = !DIFile(filename: "a.cpp", directory: "b") !2 = !{} !3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{!5} +!5 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) diff --git a/test/CodeGen/ARM/constantpool-promote-dbg.ll b/test/CodeGen/ARM/constantpool-promote-dbg.ll index ae765d26dcac..84386d2975f0 100644 --- a/test/CodeGen/ARM/constantpool-promote-dbg.ll +++ b/test/CodeGen/ARM/constantpool-promote-dbg.ll @@ -1,4 +1,4 @@ -; RUN: llc -relocation-model=static < %s | FileCheck %s +; RUN: llc -relocation-model=static -arm-promote-constant < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv7m--linux-gnu" diff --git a/test/CodeGen/ARM/constantpool-promote-ldrh.ll b/test/CodeGen/ARM/constantpool-promote-ldrh.ll index 9e369dc08c4b..59970495874b 100644 --- a/test/CodeGen/ARM/constantpool-promote-ldrh.ll +++ b/test/CodeGen/ARM/constantpool-promote-ldrh.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel=false | FileCheck %s -; RUN: llc < %s -O0 -fast-isel=false -filetype=obj +; RUN: llc < %s -O0 -fast-isel=false -arm-promote-constant | FileCheck %s +; RUN: llc < %s -O0 -fast-isel=false -filetype=obj -arm-promote-constant target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv6m-arm-linux-gnueabi" diff --git a/test/CodeGen/ARM/constantpool-promote.ll b/test/CodeGen/ARM/constantpool-promote.ll index 8df7e100c051..d5361f33a98b 100644 --- a/test/CodeGen/ARM/constantpool-promote.ll +++ b/test/CodeGen/ARM/constantpool-promote.ll @@ -1,15 +1,15 @@ -; RUN: llc -mtriple armv7--linux-gnueabihf -relocation-model=static < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7ARM -; RUN: llc -mtriple armv7--linux-gnueabihf -relocation-model=pic < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7ARM -; RUN: llc -mtriple armv7--linux-gnueabihf -relocation-model=ropi < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7ARM -; RUN: llc -mtriple armv7--linux-gnueabihf -relocation-model=rwpi < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7ARM -; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=static < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB -; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=pic < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB -; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=ropi < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB -; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=rwpi < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB -; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=static < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M -; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=pic < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M -; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=ropi < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M -; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=rwpi < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M +; RUN: llc -mtriple armv7--linux-gnueabihf -relocation-model=static -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7ARM +; RUN: llc -mtriple armv7--linux-gnueabihf -relocation-model=pic -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7ARM +; RUN: llc -mtriple armv7--linux-gnueabihf -relocation-model=ropi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7ARM +; RUN: llc -mtriple armv7--linux-gnueabihf -relocation-model=rwpi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7ARM +; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=static -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB +; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=pic -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB +; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=ropi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB +; RUN: llc -mtriple thumbv7--linux-gnueabihf -relocation-model=rwpi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V7,CHECK-V7THUMB +; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=static -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M +; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=pic -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M +; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=ropi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M +; RUN: llc -mtriple thumbv6m--linux-gnueabihf -relocation-model=rwpi -arm-promote-constant < %s | FileCheck %s --check-prefixes=CHECK,CHECK-V6M @.str = private unnamed_addr constant [2 x i8] c"s\00", align 1 @.str1 = private unnamed_addr constant [69 x i8] c"this string is far too long to fit in a literal pool by far and away\00", align 1 diff --git a/test/CodeGen/ARM/cortexr52-misched-basic.ll b/test/CodeGen/ARM/cortexr52-misched-basic.ll index 3ccb34d9fc90..eb2c29a3a5d1 100644 --- a/test/CodeGen/ARM/cortexr52-misched-basic.ll +++ b/test/CodeGen/ARM/cortexr52-misched-basic.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED -; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC ; ; Check the latency for instructions for both generic and cortex-r52. ; Cortex-r52 machine model will cause the div to be sceduled before eor diff --git a/test/CodeGen/ARM/fastisel-thumb-litpool.ll b/test/CodeGen/ARM/fastisel-thumb-litpool.ll index aa9e7260fb2e..53653a5a4f57 100644 --- a/test/CodeGen/ARM/fastisel-thumb-litpool.ll +++ b/test/CodeGen/ARM/fastisel-thumb-litpool.ll @@ -5,6 +5,7 @@ ; hence the CHECK-NOT. define i32 @test_thumb_ldrlit() minsize { +; CHECK-LABEL: test_thumb_ldrlit: ; CHECK: ldr r0, LCPI0_0 ; CHECK-NOT: ldr ret i32 12345678 diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll index fb204debf612..b447497b270a 100644 --- a/test/CodeGen/ARM/memcpy-inline.ll +++ b/test/CodeGen/ARM/memcpy-inline.ll @@ -35,6 +35,8 @@ entry: ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0], [[INC]] ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] +; CHECK-T1-LABEL: t1: +; CHECK-T1: bl _memcpy tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false) ret void } @@ -51,6 +53,8 @@ entry: ; CHECK: str [[REG2]], [r0] ; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r3] +; CHECK-T1-LABEL: t2: +; CHECK-T1: bl _memcpy tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false) ret void } @@ -62,6 +66,8 @@ entry: ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]! ; CHECK: vldr d{{[0-9]+}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}}, [r0] +; CHECK-T1-LABEL: t3: +; CHECK-T1: bl _memcpy tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false) ret void } @@ -72,6 +78,8 @@ entry: ; CHECK: vld1.64 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1] ; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]! ; CHECK: strh [[REG5:r[0-9]+]], [r0] +; CHECK-T1-LABEL: t4: +; CHECK-T1: bl _memcpy tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false) ret void } @@ -87,10 +95,7 @@ entry: ; CHECK: movt [[REG7:r[0-9]+]], #22866 ; CHECK: str [[REG7]] ; CHECK-T1-LABEL: t5: -; CHECK-T1: movs [[TREG3:r[0-9]]], -; CHECK-T1: strb [[TREG3]], -; CHECK-T1: movs [[TREG4:r[0-9]]], -; CHECK-T1: strb [[TREG4]], +; CHECK-T1: bl _memcpy tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false) ret void } diff --git a/test/CodeGen/ARM/memset-inline.ll b/test/CodeGen/ARM/memset-inline.ll index b86874692aca..b2bd257701d3 100644 --- a/test/CodeGen/ARM/memset-inline.ll +++ b/test/CodeGen/ARM/memset-inline.ll @@ -1,22 +1,36 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -pre-RA-sched=source -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -pre-RA-sched=source -disable-post-ra | FileCheck %s -check-prefix=CHECK-7A +; RUN: llc < %s -mtriple=thumbv6m -pre-RA-sched=source -disable-post-ra -mattr=+strict-align | FileCheck %s -check-prefix=CHECK-6M define void @t1(i8* nocapture %c) nounwind optsize { entry: -; CHECK-LABEL: t1: -; CHECK: movs r1, #0 -; CHECK: strd r1, r1, [r0] -; CHECK: str r1, [r0, #8] +; CHECK-7A-LABEL: t1: +; CHECK-7A: movs r1, #0 +; CHECK-7A: strd r1, r1, [r0] +; CHECK-7A: str r1, [r0, #8] +; CHECK-6M-LABEL: t1: +; CHECK-6M: movs r1, #0 +; CHECK-6M: str r1, [r0] +; CHECK-6M: str r1, [r0, #4] +; CHECK-6M: str r1, [r0, #8] call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false) ret void } define void @t2() nounwind ssp { entry: -; CHECK-LABEL: t2: -; CHECK: vmov.i32 {{q[0-9]+}}, #0x0 -; CHECK: movs r1, #10 -; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2], r1 -; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2] +; CHECK-7A-LABEL: t2: +; CHECK-7A: vmov.i32 {{q[0-9]+}}, #0x0 +; CHECK-7A: movs r1, #10 +; CHECK-7A: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2], r1 +; CHECK-7A: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2] +; CHECK-6M-LABEL: t2: +; CHECK-6M: movs [[REG:r[0-9]+]], #0 +; CHECK-6M: str [[REG]], [sp, #20] +; CHECK-6M: str [[REG]], [sp, #16] +; CHECK-6M: str [[REG]], [sp, #12] +; CHECK-6M: str [[REG]], [sp, #8] +; CHECK-6M: str [[REG]], [sp, #4] +; CHECK-6M: str [[REG]], [sp] %buf = alloca [26 x i8], align 1 %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0 call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false) @@ -24,6 +38,56 @@ entry: ret void } +define void @t3(i8* %p) { +entry: +; CHECK-7A-LABEL: t3: +; CHECK-7A: muls [[REG:r[0-9]+]], +; CHECK-7A: str [[REG]], +; CHECK-6M-LABEL: t3: +; CHECK-6M-NOT: muls +; CHECK-6M: strb [[REG:r[0-9]+]], +; CHECK-6M: strb [[REG]], +; CHECK-6M: strb [[REG]], +; CHECK-6M: strb [[REG]], + br label %for.body + +for.body: + %i = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %0 = trunc i32 %i to i8 + call void @llvm.memset.p0i8.i32(i8* %p, i8 %0, i32 4, i32 1, i1 false) + call void @something(i8* %p) + %inc = add nuw nsw i32 %i, 1 + %exitcond = icmp eq i32 %inc, 255 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret void +} + +define void @t4(i8* %p) { +entry: +; CHECK-7A-LABEL: t4: +; CHECK-7A: muls [[REG:r[0-9]+]], +; CHECK-7A: str [[REG]], +; CHECK-6M-LABEL: t4: +; CHECK-6M: muls [[REG:r[0-9]+]], +; CHECK-6M: strh [[REG]], +; CHECK-6M: strh [[REG]], + br label %for.body + +for.body: + %i = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %0 = trunc i32 %i to i8 + call void @llvm.memset.p0i8.i32(i8* %p, i8 %0, i32 4, i32 2, i1 false) + call void @something(i8* %p) + %inc = add nuw nsw i32 %i, 1 + %exitcond = icmp eq i32 %inc, 255 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret void +} + declare void @something(i8*) nounwind declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll index 330252a90d7c..53f8b8d15042 100644 --- a/test/CodeGen/ARM/misched-copy-arm.ll +++ b/test/CodeGen/ARM/misched-copy-arm.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -mtriple=thumb-eabi -mcpu=swift -pre-RA-sched=source -join-globalcopies -enable-misched -verify-misched -debug-only=misched -arm-atomic-cfg-tidy=0 %s -o - 2>&1 | FileCheck %s +; RUN: llc -mtriple=thumb-eabi -mcpu=swift -pre-RA-sched=source -join-globalcopies -enable-misched -verify-misched -debug-only=machine-scheduler -arm-atomic-cfg-tidy=0 %s -o - 2>&1 | FileCheck %s ; ; Loop counter copies should be eliminated. ; There is also a MUL here, but we don't care where it is scheduled. diff --git a/test/CodeGen/ARM/misched-fp-basic.ll b/test/CodeGen/ARM/misched-fp-basic.ll index 27ad2cec34fd..2f672b0cb540 100644 --- a/test/CodeGen/ARM/misched-fp-basic.ll +++ b/test/CodeGen/ARM/misched-fp-basic.ll @@ -1,9 +1,9 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \ +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ ; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \ +; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ ; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \ +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ ; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 ; ; Check the latency of instructions for processors with sched-models diff --git a/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/test/CodeGen/ARM/misched-int-basic-thumb2.mir index 86ef1e26f636..32d1e03d9a1b 100644 --- a/test/CodeGen/ARM/misched-int-basic-thumb2.mir +++ b/test/CodeGen/ARM/misched-int-basic-thumb2.mir @@ -1,10 +1,10 @@ # Basic machine sched model test for Thumb2 int instructions # RUN: llc -o /dev/null %s -mtriple=thumbv7-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \ -# RUN: -debug-only=misched 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT +# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT # RUN: llc -o /dev/null %s -mtriple=thumbv7--eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \ -# RUN: -debug-only=misched 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 +# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 # RUN: llc -o /dev/null %s -mtriple=thumbv8r-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \ -# RUN: -debug-only=misched 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 +# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 # REQUIRES: asserts --- | ; ModuleID = 'foo.ll' diff --git a/test/CodeGen/ARM/misched-int-basic.mir b/test/CodeGen/ARM/misched-int-basic.mir index f237c0a07b2e..d5231269d732 100644 --- a/test/CodeGen/ARM/misched-int-basic.mir +++ b/test/CodeGen/ARM/misched-int-basic.mir @@ -1,9 +1,9 @@ # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \ -# RUN: -debug-only=misched 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT +# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \ -# RUN: -debug-only=misched 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 +# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \ -# RUN: -debug-only=misched 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 +# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 # REQUIRES: asserts --- | ; ModuleID = 'foo.ll' diff --git a/test/CodeGen/ARM/single-issue-r52.mir b/test/CodeGen/ARM/single-issue-r52.mir index 6c95f7603e6e..1eba074dafb3 100644 --- a/test/CodeGen/ARM/single-issue-r52.mir +++ b/test/CodeGen/ARM/single-issue-r52.mir @@ -1,5 +1,5 @@ -# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=misched -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN -# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=misched -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP +# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN +# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP # REQUIRES: asserts --- | ; ModuleID = 'foo.ll' diff --git a/test/CodeGen/ARM/vcombine.ll b/test/CodeGen/ARM/vcombine.ll index 81b22ee12cdd..c08ed81d042a 100644 --- a/test/CodeGen/ARM/vcombine.ll +++ b/test/CodeGen/ARM/vcombine.ll @@ -99,7 +99,9 @@ define <4 x i16> @vget_low16(<8 x i16>* %A) nounwind { define <8 x i8> @vget_high8(<16 x i8>* %A) nounwind { ; CHECK: vget_high8 ; CHECK-NOT: vst -; CHECK-LE: vmov r0, r1, d17 +; CHECK-LE-NOT: vld1.64 {d16, d17}, [r0] +; CHECK-LE: vldr d16, [r0, #8] +; CHECK-LE: vmov r0, r1, d16 ; CHECK-BE: vmov r1, r0, d16 %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index e44e757a3169..5742dc314978 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -199,10 +199,10 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: test_undef: ; CHECK: @ BB#0: -; CHECK-NEXT: vld1.64 {d16, d17}, [r1] -; CHECK-NEXT: vld1.64 {d18, d19}, [r0] -; CHECK-NEXT: vzip.16 d19, d16 -; CHECK-NEXT: vmov r0, r1, d19 +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d17, [r0, #8] +; CHECK-NEXT: vzip.16 d17, d16 +; CHECK-NEXT: vmov r0, r1, d17 ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = load <8 x i16>, <8 x i16>* %B diff --git a/test/CodeGen/Hexagon/post-ra-kill-update.mir b/test/CodeGen/Hexagon/post-ra-kill-update.mir index c43624d7a8d3..ac46a70a68a5 100644 --- a/test/CodeGen/Hexagon/post-ra-kill-update.mir +++ b/test/CodeGen/Hexagon/post-ra-kill-update.mir @@ -6,7 +6,7 @@ # CHECK-LABEL: name: foo # Check for no-kill of r9 in the first instruction, after reordering: -# CHECK: %d7 = S2_lsr_r_p_or %d7, killed %d1, %r9 +# CHECK: %d7 = S2_lsr_r_p_or killed %d7, killed %d1, %r9 # CHECK: %d13 = S2_lsr_r_p killed %d0, killed %r9 --- | diff --git a/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll b/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll index 18cca5c356e3..242ee53f19f2 100644 --- a/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll +++ b/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc %s -mtriple=lanai-unknown-unknown -debug-only=misched -o /dev/null 2>&1 | FileCheck %s +; RUN: llc %s -mtriple=lanai-unknown-unknown -debug-only=machine-scheduler -o /dev/null 2>&1 | FileCheck %s ; Make sure there are no control dependencies between memory operations that ; are trivially disjoint. diff --git a/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir b/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir deleted file mode 100644 index 96801f5b0a37..000000000000 --- a/test/CodeGen/MIR/ARM/PR32721_ifcvt_triangle_unanalyzable.mir +++ /dev/null @@ -1,24 +0,0 @@ -# RUN: llc -mtriple=arm-apple-ios -run-pass=if-converter %s -o - | FileCheck %s ---- -name: foo -body: | - bb.0: - B %bb.2 - - bb.1: - BX_RET 14, 0 - - bb.2: - Bcc %bb.1, 1, %cpsr - - bb.3: - B %bb.1 - -... - -# We should get a single block containing the BX_RET, with no successors at all - -# CHECK: body: -# CHECK-NEXT: bb.0: -# CHECK-NEXT: BX_RET - diff --git a/test/CodeGen/MSP430/hwmult16.ll b/test/CodeGen/MSP430/hwmult16.ll index b23f1ad37d81..87b6a7aeacf5 100644 --- a/test/CodeGen/MSP430/hwmult16.ll +++ b/test/CodeGen/MSP430/hwmult16.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mhwmult=16bit < %s | FileCheck %s +; RUN: llc -O0 -mattr=+hwmult16 < %s | FileCheck %s target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16" target triple = "msp430---elf" diff --git a/test/CodeGen/MSP430/hwmult32.ll b/test/CodeGen/MSP430/hwmult32.ll index 6ffeb9698862..10c831e77ffb 100644 --- a/test/CodeGen/MSP430/hwmult32.ll +++ b/test/CodeGen/MSP430/hwmult32.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mhwmult=32bit < %s | FileCheck %s +; RUN: llc -O0 -mattr=+hwmult32 < %s | FileCheck %s target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16" target triple = "msp430---elf" diff --git a/test/CodeGen/MSP430/hwmultf5.ll b/test/CodeGen/MSP430/hwmultf5.ll index 51ca4be4a654..c57922ece7d0 100644 --- a/test/CodeGen/MSP430/hwmultf5.ll +++ b/test/CodeGen/MSP430/hwmultf5.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mhwmult=f5series < %s | FileCheck %s +; RUN: llc -O0 -mattr=+hwmultf5 < %s | FileCheck %s target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16" target triple = "msp430---elf" diff --git a/test/CodeGen/MSP430/vararg.ll b/test/CodeGen/MSP430/vararg.ll index a708b89cbd8f..4baf499848fd 100644 --- a/test/CodeGen/MSP430/vararg.ll +++ b/test/CodeGen/MSP430/vararg.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -verify-machineinstrs < %s | FileCheck %s target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16" target triple = "msp430---elf" diff --git a/test/CodeGen/Nios2/lit.local.cfg b/test/CodeGen/Nios2/lit.local.cfg new file mode 100644 index 000000000000..84c8b039391b --- /dev/null +++ b/test/CodeGen/Nios2/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'Nios2' in config.root.targets: + config.unsupported = True + diff --git a/test/CodeGen/Nios2/target_support.ll b/test/CodeGen/Nios2/target_support.ll new file mode 100644 index 000000000000..90e7020b2fcc --- /dev/null +++ b/test/CodeGen/Nios2/target_support.ll @@ -0,0 +1,11 @@ +; This tests that llc accepts Nios2 target. + +; RUN: not not llc < %s -asm-verbose=false -march=nios2 2>&1 | FileCheck %s --check-prefix=ARCH +; RUN: not not llc < %s -asm-verbose=false -mtriple=nios2 2>&1 | FileCheck %s --check-prefix=TRIPLE + +; ARCH-NOT: invalid target +; TRIPLE-NOT: unable to get target + +define i32 @f(i32 %i) { + ret i32 %i +} diff --git a/test/CodeGen/PowerPC/atomics-constant.ll b/test/CodeGen/PowerPC/atomics-constant.ll new file mode 100644 index 000000000000..a92ca813af85 --- /dev/null +++ b/test/CodeGen/PowerPC/atomics-constant.ll @@ -0,0 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target triple = "powerpc64le-unknown-linux-gnu" + +@a = constant i64 zeroinitializer + +define i64 @foo() { +; CHECK-LABEL: foo: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: li 4, 0 +; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: cmpw 7, 4, 4 +; CHECK-NEXT: ld 3, 0(3) +; CHECK-NEXT: bne- 7, .+4 +; CHECK-NEXT: isync +; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: blr +entry: + %value = load atomic i64, i64* @a acquire, align 8 + ret i64 %value +} diff --git a/test/CodeGen/PowerPC/build-vector-tests.ll b/test/CodeGen/PowerPC/build-vector-tests.ll index 1bce9d4cb439..c42f677d17ab 100644 --- a/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/test/CodeGen/PowerPC/build-vector-tests.ll @@ -869,9 +869,9 @@ entry: ; P9LE-LABEL: fromDiffConstsi ; P8BE-LABEL: fromDiffConstsi ; P8LE-LABEL: fromDiffConstsi -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr @@ -899,9 +899,9 @@ entry: ; P9LE-LABEL: fromDiffMemConsAi ; P8BE-LABEL: fromDiffMemConsAi ; P8LE-LABEL: fromDiffMemConsAi -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr @@ -929,12 +929,12 @@ entry: ; P9LE-LABEL: fromDiffMemConsDi ; P8BE-LABEL: fromDiffMemConsDi ; P8LE-LABEL: fromDiffMemConsDi -; P9BE: lxvx -; P9BE: lxvx +; P9BE: lxv +; P9BE: lxv ; P9BE: vperm ; P9BE: blr -; P9LE: lxvx -; P9LE: lxvx +; P9LE: lxv +; P9LE: lxv ; P9LE: vperm ; P9LE: blr ; P8BE: lxvw4x @@ -1018,13 +1018,13 @@ entry: ; P8BE-LABEL: fromDiffMemVarDi ; P8LE-LABEL: fromDiffMemVarDi ; P9BE: sldi {{r[0-9]+}}, r4, 2 -; P9BE-DAG: lxvx {{v[0-9]+}}, r3, -; P9BE-DAG: lxvx +; P9BE-DAG: lxv {{v[0-9]+}} +; P9BE-DAG: lxv ; P9BE: vperm ; P9BE: blr ; P9LE: sldi {{r[0-9]+}}, r4, 2 -; P9LE-DAG: lxvx {{v[0-9]+}}, r3, -; P9LE-DAG: lxvx +; P9LE-DAG: lxv {{v[0-9]+}} +; P9LE-DAG: lxv ; P9LE: vperm ; P9LE: blr ; P8BE: sldi {{r[0-9]+}}, r4, 2 @@ -1281,9 +1281,9 @@ entry: ; P9LE-LABEL: fromDiffConstsConvftoi ; P8BE-LABEL: fromDiffConstsConvftoi ; P8LE-LABEL: fromDiffConstsConvftoi -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr @@ -1303,10 +1303,10 @@ entry: ; P9LE-LABEL: fromDiffMemConsAConvftoi ; P8BE-LABEL: fromDiffMemConsAConvftoi ; P8LE-LABEL: fromDiffMemConsAConvftoi -; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3 +; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) ; P9BE: xvcvspsxws v2, [[REG1]] ; P9BE: blr -; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3 +; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) ; P9LE: xvcvspsxws v2, [[REG1]] ; P9LE: blr ; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 @@ -1341,13 +1341,13 @@ entry: ; P9LE-LABEL: fromDiffMemConsDConvftoi ; P8BE-LABEL: fromDiffMemConsDConvftoi ; P8LE-LABEL: fromDiffMemConsDConvftoi -; P9BE: lxvx -; P9BE: lxvx +; P9BE: lxv +; P9BE: lxv ; P9BE: vperm ; P9BE: xvcvspsxws ; P9BE: blr -; P9LE: lxvx -; P9LE: lxvx +; P9LE: lxv +; P9LE: lxv ; P9LE: vperm ; P9LE: xvcvspsxws ; P9LE: blr @@ -1557,9 +1557,9 @@ entry: ; P9LE-LABEL: fromDiffConstsConvdtoi ; P8BE-LABEL: fromDiffConstsConvdtoi ; P8LE-LABEL: fromDiffConstsConvdtoi -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr @@ -1584,16 +1584,16 @@ entry: ; P9LE-LABEL: fromDiffMemConsAConvdtoi ; P8BE-LABEL: fromDiffMemConsAConvdtoi ; P8LE-LABEL: fromDiffMemConsAConvdtoi -; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3 -; P9BE: lxvx [[REG2:[vs0-9]+]], r3, r4 +; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) +; P9BE: lxv [[REG2:[vs0-9]+]], 16(r3) ; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] ; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] ; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] ; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] ; P9BE: vmrgew v2, [[REG6]], [[REG5]] ; P9BE: xvcvspsxws v2, v2 -; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3 -; P9LE: lxvx [[REG2:[vs0-9]+]], r3, r4 +; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) +; P9LE: lxv [[REG2:[vs0-9]+]], 16(r3) ; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] ; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] ; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] @@ -2027,9 +2027,9 @@ entry: ; P9LE-LABEL: fromDiffConstsui ; P8BE-LABEL: fromDiffConstsui ; P8LE-LABEL: fromDiffConstsui -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr @@ -2057,9 +2057,9 @@ entry: ; P9LE-LABEL: fromDiffMemConsAui ; P8BE-LABEL: fromDiffMemConsAui ; P8LE-LABEL: fromDiffMemConsAui -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr @@ -2087,12 +2087,12 @@ entry: ; P9LE-LABEL: fromDiffMemConsDui ; P8BE-LABEL: fromDiffMemConsDui ; P8LE-LABEL: fromDiffMemConsDui -; P9BE: lxvx -; P9BE: lxvx +; P9BE: lxv +; P9BE: lxv ; P9BE: vperm ; P9BE: blr -; P9LE: lxvx -; P9LE: lxvx +; P9LE: lxv +; P9LE: lxv ; P9LE: vperm ; P9LE: blr ; P8BE: lxvw4x @@ -2177,13 +2177,13 @@ entry: ; P8BE-LABEL: fromDiffMemVarDui ; P8LE-LABEL: fromDiffMemVarDui ; P9BE-DAG: sldi {{r[0-9]+}}, r4, 2 -; P9BE-DAG: lxvx {{v[0-9]+}}, r3 -; P9BE-DAG: lxvx +; P9BE-DAG: lxv {{v[0-9]+}}, -12(r3) +; P9BE-DAG: lxv ; P9BE: vperm ; P9BE: blr ; P9LE-DAG: sldi {{r[0-9]+}}, r4, 2 -; P9LE-DAG: lxvx {{v[0-9]+}}, r3 -; P9LE-DAG: lxvx +; P9LE-DAG: lxv {{v[0-9]+}}, -12(r3) +; P9LE-DAG: lxv ; P9LE: vperm ; P9LE: blr ; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2 @@ -2439,9 +2439,9 @@ entry: ; P9LE-LABEL: fromDiffConstsConvftoui ; P8BE-LABEL: fromDiffConstsConvftoui ; P8LE-LABEL: fromDiffConstsConvftoui -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr @@ -2461,10 +2461,10 @@ entry: ; P9LE-LABEL: fromDiffMemConsAConvftoui ; P8BE-LABEL: fromDiffMemConsAConvftoui ; P8LE-LABEL: fromDiffMemConsAConvftoui -; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3 +; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) ; P9BE: xvcvspuxws v2, [[REG1]] ; P9BE: blr -; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3 +; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) ; P9LE: xvcvspuxws v2, [[REG1]] ; P9LE: blr ; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 @@ -2499,13 +2499,13 @@ entry: ; P9LE-LABEL: fromDiffMemConsDConvftoui ; P8BE-LABEL: fromDiffMemConsDConvftoui ; P8LE-LABEL: fromDiffMemConsDConvftoui -; P9BE: lxvx -; P9BE: lxvx +; P9BE: lxv +; P9BE: lxv ; P9BE: vperm ; P9BE: xvcvspuxws ; P9BE: blr -; P9LE: lxvx -; P9LE: lxvx +; P9LE: lxv +; P9LE: lxv ; P9LE: vperm ; P9LE: xvcvspuxws ; P9LE: blr @@ -2715,9 +2715,9 @@ entry: ; P9LE-LABEL: fromDiffConstsConvdtoui ; P8BE-LABEL: fromDiffConstsConvdtoui ; P8LE-LABEL: fromDiffConstsConvdtoui -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvw4x ; P8BE: blr @@ -2742,16 +2742,16 @@ entry: ; P9LE-LABEL: fromDiffMemConsAConvdtoui ; P8BE-LABEL: fromDiffMemConsAConvdtoui ; P8LE-LABEL: fromDiffMemConsAConvdtoui -; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3 -; P9BE: lxvx [[REG2:[vs0-9]+]], r3, r4 +; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) +; P9BE: lxv [[REG2:[vs0-9]+]], 16(r3) ; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] ; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] ; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] ; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] ; P9BE: vmrgew v2, [[REG6]], [[REG5]] ; P9BE: xvcvspuxws v2, v2 -; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3 -; P9LE: lxvx [[REG2:[vs0-9]+]], r3, r4 +; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) +; P9LE: lxv [[REG2:[vs0-9]+]], 16(r3) ; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] ; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] ; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] @@ -3087,9 +3087,9 @@ entry: ; P9LE-LABEL: spltConst1ll ; P8BE-LABEL: spltConst1ll ; P8LE-LABEL: spltConst1ll -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -3105,9 +3105,9 @@ entry: ; P9LE-LABEL: spltConst16kll ; P8BE-LABEL: spltConst16kll ; P8LE-LABEL: spltConst16kll -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -3123,9 +3123,9 @@ entry: ; P9LE-LABEL: spltConst32kll ; P8BE-LABEL: spltConst32kll ; P8LE-LABEL: spltConst32kll -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -3165,9 +3165,9 @@ entry: ; P9LE-LABEL: fromDiffConstsll ; P8BE-LABEL: fromDiffConstsll ; P8LE-LABEL: fromDiffConstsll -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -3188,9 +3188,9 @@ entry: ; P9LE-LABEL: fromDiffMemConsAll ; P8BE-LABEL: fromDiffMemConsAll ; P8LE-LABEL: fromDiffMemConsAll -; P9BE: lxvx v2 +; P9BE: lxv v2 ; P9BE: blr -; P9LE: lxvx v2 +; P9LE: lxv v2 ; P9LE: blr ; P8BE: lxvd2x v2 ; P8BE: blr @@ -3213,9 +3213,9 @@ entry: ; P9LE-LABEL: fromDiffMemConsDll ; P8BE-LABEL: fromDiffMemConsDll ; P8LE-LABEL: fromDiffMemConsDll -; P9BE: lxvx v2 +; P9BE: lxv v2 ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: xxswapd v2 ; P9LE: blr ; P8BE: lxvd2x @@ -3275,11 +3275,11 @@ entry: ; P8BE-LABEL: fromDiffMemVarDll ; P8LE-LABEL: fromDiffMemVarDll ; P9BE: sldi -; P9BE: lxvx +; P9BE: lxv ; P9BE: xxswapd v2 ; P9BE-NEXT: blr ; P9LE: sldi -; P9LE: lxvx +; P9LE: lxv ; P9LE: xxswapd v2 ; P9LE-NEXT: blr ; P8BE: sldi @@ -3422,9 +3422,9 @@ entry: ; P9LE-LABEL: spltCnstConvftoll ; P8BE-LABEL: spltCnstConvftoll ; P8LE-LABEL: spltCnstConvftoll -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -3466,9 +3466,9 @@ entry: ; P9LE-LABEL: fromDiffConstsConvftoll ; P8BE-LABEL: fromDiffConstsConvftoll ; P8LE-LABEL: fromDiffConstsConvftoll -; P9BE: lxvx v2 +; P9BE: lxv v2 ; P9BE: blr -; P9LE: lxvx v2 +; P9LE: lxv v2 ; P9LE: blr ; P8BE: lxvd2x v2 ; P8BE: blr @@ -3705,9 +3705,9 @@ entry: ; P9LE-LABEL: spltCnstConvdtoll ; P8BE-LABEL: spltCnstConvdtoll ; P8LE-LABEL: spltCnstConvdtoll -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -3749,9 +3749,9 @@ entry: ; P9LE-LABEL: fromDiffConstsConvdtoll ; P8BE-LABEL: fromDiffConstsConvdtoll ; P8LE-LABEL: fromDiffConstsConvdtoll -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -3770,10 +3770,10 @@ entry: ; P9LE-LABEL: fromDiffMemConsAConvdtoll ; P8BE-LABEL: fromDiffMemConsAConvdtoll ; P8LE-LABEL: fromDiffMemConsAConvdtoll -; P9BE: lxvx +; P9BE: lxv ; P9BE-NEXT: xvcvdpsxds v2 ; P9BE-NEXT: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE-NEXT: xvcvdpsxds v2 ; P9LE-NEXT: blr ; P8BE: lxvd2x @@ -3801,11 +3801,11 @@ entry: ; P9LE-LABEL: fromDiffMemConsDConvdtoll ; P8BE-LABEL: fromDiffMemConsDConvdtoll ; P8LE-LABEL: fromDiffMemConsDConvdtoll -; P9BE: lxvx +; P9BE: lxv ; P9BE-NEXT: xxswapd ; P9BE-NEXT: xvcvdpsxds v2 ; P9BE-NEXT: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE-NEXT: xxswapd ; P9LE-NEXT: xvcvdpsxds v2 ; P9LE-NEXT: blr @@ -3876,12 +3876,12 @@ entry: ; P8BE-LABEL: fromDiffMemVarDConvdtoll ; P8LE-LABEL: fromDiffMemVarDConvdtoll ; P9BE: sldi -; P9BE: lxvx +; P9BE: lxv ; P9BE-NEXT: xxswapd ; P9BE-NEXT: xvcvdpsxds v2 ; P9BE-NEXT: blr ; P9LE: sldi -; P9LE: lxvx +; P9LE: lxv ; P9LE-NEXT: xxswapd ; P9LE-NEXT: xvcvdpsxds v2 ; P9LE-NEXT: blr @@ -3991,9 +3991,9 @@ entry: ; P9LE-LABEL: spltConst1ull ; P8BE-LABEL: spltConst1ull ; P8LE-LABEL: spltConst1ull -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -4009,9 +4009,9 @@ entry: ; P9LE-LABEL: spltConst16kull ; P8BE-LABEL: spltConst16kull ; P8LE-LABEL: spltConst16kull -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -4027,9 +4027,9 @@ entry: ; P9LE-LABEL: spltConst32kull ; P8BE-LABEL: spltConst32kull ; P8LE-LABEL: spltConst32kull -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -4069,9 +4069,9 @@ entry: ; P9LE-LABEL: fromDiffConstsull ; P8BE-LABEL: fromDiffConstsull ; P8LE-LABEL: fromDiffConstsull -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -4092,9 +4092,9 @@ entry: ; P9LE-LABEL: fromDiffMemConsAull ; P8BE-LABEL: fromDiffMemConsAull ; P8LE-LABEL: fromDiffMemConsAull -; P9BE: lxvx v2 +; P9BE: lxv v2 ; P9BE: blr -; P9LE: lxvx v2 +; P9LE: lxv v2 ; P9LE: blr ; P8BE: lxvd2x v2 ; P8BE: blr @@ -4117,9 +4117,9 @@ entry: ; P9LE-LABEL: fromDiffMemConsDull ; P8BE-LABEL: fromDiffMemConsDull ; P8LE-LABEL: fromDiffMemConsDull -; P9BE: lxvx v2 +; P9BE: lxv v2 ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: xxswapd v2 ; P9LE: blr ; P8BE: lxvd2x @@ -4179,11 +4179,11 @@ entry: ; P8BE-LABEL: fromDiffMemVarDull ; P8LE-LABEL: fromDiffMemVarDull ; P9BE: sldi -; P9BE: lxvx +; P9BE: lxv ; P9BE: xxswapd v2 ; P9BE-NEXT: blr ; P9LE: sldi -; P9LE: lxvx +; P9LE: lxv ; P9LE: xxswapd v2 ; P9LE-NEXT: blr ; P8BE: sldi @@ -4326,9 +4326,9 @@ entry: ; P9LE-LABEL: spltCnstConvftoull ; P8BE-LABEL: spltCnstConvftoull ; P8LE-LABEL: spltCnstConvftoull -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -4370,9 +4370,9 @@ entry: ; P9LE-LABEL: fromDiffConstsConvftoull ; P8BE-LABEL: fromDiffConstsConvftoull ; P8LE-LABEL: fromDiffConstsConvftoull -; P9BE: lxvx v2 +; P9BE: lxv v2 ; P9BE: blr -; P9LE: lxvx v2 +; P9LE: lxv v2 ; P9LE: blr ; P8BE: lxvd2x v2 ; P8BE: blr @@ -4609,9 +4609,9 @@ entry: ; P9LE-LABEL: spltCnstConvdtoull ; P8BE-LABEL: spltCnstConvdtoull ; P8LE-LABEL: spltCnstConvdtoull -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -4653,9 +4653,9 @@ entry: ; P9LE-LABEL: fromDiffConstsConvdtoull ; P8BE-LABEL: fromDiffConstsConvdtoull ; P8LE-LABEL: fromDiffConstsConvdtoull -; P9BE: lxvx +; P9BE: lxv ; P9BE: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE: blr ; P8BE: lxvd2x ; P8BE: blr @@ -4674,10 +4674,10 @@ entry: ; P9LE-LABEL: fromDiffMemConsAConvdtoull ; P8BE-LABEL: fromDiffMemConsAConvdtoull ; P8LE-LABEL: fromDiffMemConsAConvdtoull -; P9BE: lxvx +; P9BE: lxv ; P9BE-NEXT: xvcvdpuxds v2 ; P9BE-NEXT: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE-NEXT: xvcvdpuxds v2 ; P9LE-NEXT: blr ; P8BE: lxvd2x @@ -4705,11 +4705,11 @@ entry: ; P9LE-LABEL: fromDiffMemConsDConvdtoull ; P8BE-LABEL: fromDiffMemConsDConvdtoull ; P8LE-LABEL: fromDiffMemConsDConvdtoull -; P9BE: lxvx +; P9BE: lxv ; P9BE-NEXT: xxswapd ; P9BE-NEXT: xvcvdpuxds v2 ; P9BE-NEXT: blr -; P9LE: lxvx +; P9LE: lxv ; P9LE-NEXT: xxswapd ; P9LE-NEXT: xvcvdpuxds v2 ; P9LE-NEXT: blr @@ -4780,12 +4780,12 @@ entry: ; P8BE-LABEL: fromDiffMemVarDConvdtoull ; P8LE-LABEL: fromDiffMemVarDConvdtoull ; P9BE: sldi -; P9BE: lxvx +; P9BE: lxv ; P9BE-NEXT: xxswapd ; P9BE-NEXT: xvcvdpuxds v2 ; P9BE-NEXT: blr ; P9LE: sldi -; P9LE: lxvx +; P9LE: lxv ; P9LE-NEXT: xxswapd ; P9LE-NEXT: xvcvdpuxds v2 ; P9LE-NEXT: blr diff --git a/test/CodeGen/PowerPC/livephysregs.mir b/test/CodeGen/PowerPC/livephysregs.mir new file mode 100644 index 000000000000..6b6268778e99 --- /dev/null +++ b/test/CodeGen/PowerPC/livephysregs.mir @@ -0,0 +1,52 @@ +# RUN: llc -o - %s -mtriple=powerpc64le--linux-gnu -run-pass=branch-folder | FileCheck %s +# The branch-folder should merge bb.1 and bb.5 below and therefore recalculate +# the liveins list of the merged block. This test is checking whether this +# recalculated list if okay and contains all the non-saved and saved CSRs. +# CHECK-LABEL: name: func +# CHECK: bb.3: +# CHECK-NEXT: liveins: %x30, %x29, %x3, %x6 +# CHECK: %x4 = RLDICR killed %x6, 16, 47 +# CHECK: %x3 = OR8 killed %x4, killed %x3 +# CHECK: BLR8 implicit %lr8, implicit %rm, implicit %x3 +--- +name: func +tracksRegLiveness: true +fixedStack: + - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' } + - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' } + - { id: 2, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false } +body: | + bb.0: + liveins: %x3, %x5, %x29, %x30 + + %x6 = RLWINM8 %x3, 16, 16, 31 + %x3 = RLDICL killed %x3, 0, 48 + BC undef %cr5lt, %bb.3 + + bb.1: + liveins: %x3, %x6, %x29, %x30 + + %x4 = RLDICR killed %x6, 16, 47 + %x3 = OR8 killed %x4, killed %x3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 + + bb.3: + liveins: %x3, %x5, %x6, %x29, %x30 + + dead %x5 = ADD8 %x5, %x6 + BC undef %cr5lt, %bb.1 + + bb.6: + liveins: %x3, %x6, %x29, %x30 + STD killed %x29, -24, %x1 :: (store 8 into %fixed-stack.1) + STD killed %x30, -16, %x1 :: (store 8 into %fixed-stack.0, align 16) + NOP implicit-def dead %x29 + NOP implicit-def dead %x30 + + %x30 = LD -16, %x1 :: (load 8 from %fixed-stack.0, align 16) + %x29 = LD -24, %x1 :: (load 8 from %fixed-stack.1) + + %x4 = RLDICR killed %x6, 16, 47 + %x3 = OR8 killed %x4, killed %x3 + BLR8 implicit %lr8, implicit %rm, implicit %x3 +... diff --git a/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll b/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll index 329f5bb59cb1..de930af75b2d 100644 --- a/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll +++ b/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll @@ -21,7 +21,7 @@ entry: ret <16 x i8> %strided.vec ; CHECK-LABEL: @test2 -; CHECK: vsldoi 2, 2, 2, 12 +; CHECK: xxsldwi 34, 34, 34, 3 ; CHECK: blr } diff --git a/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll b/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll index e3326595d132..fe34bcb85637 100644 --- a/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll +++ b/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll @@ -6,7 +6,7 @@ define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { entry: ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 12 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -45,7 +45,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 12 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 0 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3> ret <4 x float> %vecins @@ -54,7 +54,7 @@ entry: define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { entry: ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 8 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -93,7 +93,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 8 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 4 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3> ret <4 x float> %vecins @@ -102,7 +102,7 @@ entry: define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { entry: ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 4 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -141,7 +141,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 4 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 8 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3> ret <4 x float> %vecins @@ -150,7 +150,7 @@ entry: define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) { entry: ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 0 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -189,7 +189,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 0 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 12 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ret <4 x float> %vecins @@ -198,7 +198,7 @@ entry: define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { entry: ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 12 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -237,7 +237,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 12 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 0 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3> ret <4 x i32> %vecins @@ -246,7 +246,7 @@ entry: define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { entry: ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 8 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -285,7 +285,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 8 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 4 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3> ret <4 x i32> %vecins @@ -294,7 +294,7 @@ entry: define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { entry: ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 4 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -333,7 +333,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 4 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 8 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3> ret <4 x i32> %vecins @@ -342,7 +342,7 @@ entry: define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) { entry: ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 0 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -381,7 +381,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 0 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 12 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ret <4 x i32> %vecins @@ -546,7 +546,7 @@ entry: define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { entry: ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 12 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -585,7 +585,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 12 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 0 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7> ret <4 x float> %vecins @@ -594,7 +594,7 @@ entry: define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { entry: ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 8 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -633,7 +633,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 8 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 4 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7> ret <4 x float> %vecins @@ -642,7 +642,7 @@ entry: define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { entry: ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 4 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -681,7 +681,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 4 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 8 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7> ret <4 x float> %vecins @@ -690,7 +690,7 @@ entry: define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { entry: ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 0 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -729,7 +729,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 0 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 12 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3> ret <4 x float> %vecins @@ -738,7 +738,7 @@ entry: define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { entry: ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 12 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -777,7 +777,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 12 ; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 0 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7> ret <4 x i32> %vecins @@ -786,7 +786,7 @@ entry: define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { entry: ; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 8 ; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -825,7 +825,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 8 ; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 4 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7> ret <4 x i32> %vecins @@ -834,7 +834,7 @@ entry: define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { entry: ; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 4 ; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -873,7 +873,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 4 ; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 8 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7> ret <4 x i32> %vecins @@ -882,7 +882,7 @@ entry: define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) { entry: ; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ -; CHECK: xxsldwi 0, 35, 35, 2 +; CHECK: xxswapd 0, 35 ; CHECK: xxinsertw 34, 0, 0 ; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_ ; CHECK-BE: xxsldwi 0, 35, 35, 3 @@ -921,7 +921,7 @@ entry: ; CHECK: xxsldwi 0, 35, 35, 3 ; CHECK: xxinsertw 34, 0, 0 ; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_ -; CHECK-BE: xxsldwi 0, 35, 35, 2 +; CHECK-BE: xxswapd 0, 35 ; CHECK-BE: xxinsertw 34, 0, 12 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3> ret <4 x i32> %vecins @@ -972,10 +972,10 @@ define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) { entry: ; CHECK-LABEL: insertVarF ; CHECK: stxsspx 1, -; CHECK: lxvx +; CHECK: lxv ; CHECK-BE-LABEL: insertVarF ; CHECK-BE: stxsspx 1, -; CHECK-BE: lxvx +; CHECK-BE: lxv %vecins = insertelement <4 x float> %a, float %f, i32 %el ret <4 x float> %vecins } @@ -983,10 +983,10 @@ define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) { entry: ; CHECK-LABEL: insertVarI ; CHECK: stwx -; CHECK: lxvx +; CHECK: lxv ; CHECK-BE-LABEL: insertVarI ; CHECK-BE: stwx -; CHECK-BE: lxvx +; CHECK-BE: lxv %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el ret <4 x i32> %vecins } diff --git a/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/test/CodeGen/PowerPC/ppc64-i128-abi.ll index 4a8fd90db3eb..90dd1d84fc23 100644 --- a/test/CodeGen/PowerPC/ppc64-i128-abi.ll +++ b/test/CodeGen/PowerPC/ppc64-i128-abi.ll @@ -63,7 +63,7 @@ define <1 x i128> @v1i128_increment_by_one(<1 x i128> %a) nounwind { ; FIXME: li [[R1:r[0-9]+]], 1 ; FIXME: li [[R2:r[0-9]+]], 0 ; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]] -; CHECK-P9: lxvx [[V1:v[0-9]+]] +; CHECK-P9: lxv [[V1:v[0-9]+]] ; CHECK-P9: vadduqm v2, v2, [[V1]] ; CHECK-P9: blr @@ -207,7 +207,7 @@ define <1 x i128> @call_v1i128_increment_by_one() nounwind { ; CHECK-LE: blr ; CHECK-P9-LABEL: @call_v1i128_increment_by_one -; CHECK-P9: lxvx +; CHECK-P9: lxv ; CHECK-P9: bl v1i128_increment_by_one ; CHECK-P9: blr @@ -237,8 +237,8 @@ define <1 x i128> @call_v1i128_increment_by_val() nounwind { ; CHECK-LE: blr ; CHECK-P9-LABEL: @call_v1i128_increment_by_val -; CHECK-P9-DAG: lxvx v2 -; CHECK-P9-DAG: lxvx v3 +; CHECK-P9-DAG: lxv v2 +; CHECK-P9-DAG: lxv v3 ; CHECK-P9: bl v1i128_increment_by_val ; CHECK-P9: blr diff --git a/test/CodeGen/PowerPC/pr25157-peephole.ll b/test/CodeGen/PowerPC/pr25157-peephole.ll index 7f959add00f6..aacd64e401f5 100644 --- a/test/CodeGen/PowerPC/pr25157-peephole.ll +++ b/test/CodeGen/PowerPC/pr25157-peephole.ll @@ -65,5 +65,5 @@ L.LB38_2452: ; CHECK-P9-LABEL: @aercalc_ ; CHECK-P9: lfs ; CHECK-P9: xxspltd -; CHECK-P9: stxvx +; CHECK-P9: stxv ; CHECK-P9-NOT: xxswapd diff --git a/test/CodeGen/PowerPC/pr27078.ll b/test/CodeGen/PowerPC/pr27078.ll index b100e3a5ba53..d97008ee5578 100644 --- a/test/CodeGen/PowerPC/pr27078.ll +++ b/test/CodeGen/PowerPC/pr27078.ll @@ -9,11 +9,11 @@ define <4 x float> @bar(float* %p, float* %q) { %6 = shufflevector <12 x float> %5, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> ret <4 x float> %6 -; CHECK: vsldoi +; CHECK: xxsldwi ; CHECK-NEXT: vmrghw ; CHECK-NEXT: vmrglw -; CHECK-NEXT: vsldoi -; CHECK-NEXT: vsldoi -; CHECK-NEXT: vsldoi +; CHECK-NEXT: xxsldwi +; CHECK-NEXT: xxsldwi +; CHECK-NEXT: xxsldwi ; CHECK-NEXT: blr } diff --git a/test/CodeGen/PowerPC/swaps-le-6.ll b/test/CodeGen/PowerPC/swaps-le-6.ll index d573441f2cc9..e7640cab6aef 100644 --- a/test/CodeGen/PowerPC/swaps-le-6.ll +++ b/test/CodeGen/PowerPC/swaps-le-6.ll @@ -33,11 +33,11 @@ entry: ; CHECK: stxvd2x [[REG5]] ; CHECK-P9-LABEL: @bar0 -; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]] +; CHECK-P9-DAG: lxv [[REG1:[0-9]+]] ; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3) ; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0 ; CHECK-P9: xxpermdi [[REG5:[0-9]+]], [[REG1]], [[REG4]], 1 -; CHECK-P9: stxvx [[REG5]] +; CHECK-P9: stxv [[REG5]] define void @bar1() { entry: @@ -56,9 +56,9 @@ entry: ; CHECK: stxvd2x [[REG5]] ; CHECK-P9-LABEL: @bar1 -; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]] +; CHECK-P9-DAG: lxv [[REG1:[0-9]+]] ; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3) ; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0 ; CHECK-P9: xxmrgld [[REG5:[0-9]+]], [[REG4]], [[REG1]] -; CHECK-P9: stxvx [[REG5]] +; CHECK-P9: stxv [[REG5]] diff --git a/test/CodeGen/PowerPC/vec_sldwi.ll b/test/CodeGen/PowerPC/vec_sldwi.ll new file mode 100644 index 000000000000..01537d1f5927 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_sldwi.ll @@ -0,0 +1,307 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-LE +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-BE + +; Possible LE ShuffleVector masks (Case 1): +; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3) +; ShuffleVector((vector int)a, vector(int)b, 7, 0, 1, 2) +; ShuffleVector((vector int)a, vector(int)b, 6, 7, 0, 1) +; ShuffleVector((vector int)a, vector(int)b, 5, 6, 7, 0) +; which targets at: +; xxsldwi a, b, 0 +; xxsldwi a, b, 1 +; xxsldwi a, b, 2 +; xxsldwi a, b, 3 +; Possible LE Swap ShuffleVector masks (Case 2): +; ShuffleVector((vector int)a, vector(int)b, 4, 5, 6, 7) +; ShuffleVector((vector int)a, vector(int)b, 3, 4, 5, 6) +; ShuffleVector((vector int)a, vector(int)b, 2, 3, 4, 5) +; ShuffleVector((vector int)a, vector(int)b, 1, 2, 3, 4) +; which targets at: +; xxsldwi b, a, 0 +; xxsldwi b, a, 1 +; xxsldwi b, a, 2 +; xxsldwi b, a, 3 +; Possible LE ShuffleVector masks when a == b, b is undef (Case 3): +; ShuffleVector((vector int)a, vector(int)a, 0, 1, 2, 3) +; ShuffleVector((vector int)a, vector(int)a, 3, 0, 1, 2) +; ShuffleVector((vector int)a, vector(int)a, 2, 3, 0, 1) +; ShuffleVector((vector int)a, vector(int)a, 1, 2, 3, 0) +; which targets at: +; xxsldwi a, a, 0 +; xxsldwi a, a, 1 +; xxsldwi a, a, 2 +; xxsldwi a, a, 3 + +; Possible BE ShuffleVector masks (Case 4): +; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3) +; ShuffleVector((vector int)a, vector(int)b, 1, 2, 3, 4) +; ShuffleVector((vector int)a, vector(int)b, 2, 3, 4, 5) +; ShuffleVector((vector int)a, vector(int)b, 3, 4, 5, 6) +; which targets at: +; xxsldwi b, a, 0 +; xxsldwi b, a, 1 +; xxsldwi a, a, 2 +; xxsldwi a, a, 3 +; Possible BE Swap ShuffleVector masks (Case 5): +; ShuffleVector((vector int)a, vector(int)b, 4, 5, 6, 7) +; ShuffleVector((vector int)a, vector(int)b, 5, 6, 7, 0) +; ShuffleVector((vector int)a, vector(int)b, 6, 7, 0, 1) +; ShuffleVector((vector int)a, vector(int)b, 7, 0, 1, 2) +; which targets at: +; xxsldwi b, a, 0 +; xxsldwi b, a, 1 +; xxsldwi b, a, 2 +; xxsldwi b, a, 3 +; Possible BE ShuffleVector masks when a == b, b is undef (Case 6): +; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3) +; ShuffleVector((vector int)a, vector(int)a, 1, 2, 3, 0) +; ShuffleVector((vector int)a, vector(int)a, 2, 3, 0, 1) +; ShuffleVector((vector int)a, vector(int)a, 3, 0, 1, 2) +; which targets at: +; xxsldwi a, a, 0 +; xxsldwi a, a, 1 +; xxsldwi a, a, 2 +; xxsldwi a, a, 3 + +define <4 x i32> @check_le_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_0 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 7, i32 0, i32 1, i32 2> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_1 +; CHECK-LE: xxsldwi 34, 34, 35, 1 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 6, i32 7, i32 0, i32 1> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_2 +; CHECK-LE: xxsldwi 34, 34, 35, 2 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 5, i32 6, i32 7, i32 0> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_3 +; CHECK-LE: xxsldwi 34, 34, 35, 3 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_swap_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_0 +; CHECK-LE; vmr 2, 3 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_swap_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 3, i32 4, i32 5, i32 6> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_1 +; CHECK-LE: xxsldwi 34, 35, 34, 1 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_swap_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 2, i32 3, i32 4, i32 5> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_2 +; CHECK-LE: xxsldwi 34, 35, 34, 2 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_swap_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_3 +; CHECK-LE: xxsldwi 34, 35, 34, 3 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_vec_sldwi_va_undef_0(<4 x i32> %VA) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_0 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_vec_sldwi_va_undef_1(<4 x i32> %VA) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_le_vec_sldwi_va_undef_1 +; CHECK-LE: xxsldwi 34, 34, 34, 1 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_vec_sldwi_va_undef_2(<4 x i32> %VA) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_2 +; CHECK-LE: xxswapd 34, 34 +; CHECK-LE: blr +} + +define <4 x i32> @check_le_vec_sldwi_va_undef_3(<4 x i32> %VA) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_3 +; CHECK-LE: xxsldwi 34, 34, 34, 3 +; CHECK-LE: blr +} + +define <4 x i32> @check_be_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_0 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_1 +; CHECK-BE: xxsldwi 34, 34, 35, 1 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 2, i32 3, i32 4, i32 5> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_2 +; CHECK-BE: xxsldwi 34, 34, 35, 2 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 3, i32 4, i32 5, i32 6> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_3 +; CHECK-BE: xxsldwi 34, 34, 35, 3 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_swap_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_0 +; CHECK-LE; vmr 2, 3 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_swap_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 5, i32 6, i32 7, i32 0> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_1 +; CHECK-BE: xxsldwi 34, 35, 34, 1 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_swap_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 6, i32 7, i32 0, i32 1> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_2 +; CHECK-BE: xxsldwi 34, 35, 34, 2 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_swap_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 7, i32 0, i32 1, i32 2> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_3 +; CHECK-BE: xxsldwi 34, 35, 34, 3 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_vec_sldwi_va_undef_0(<4 x i32> %VA) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x i32> %0 +; CHECK-LE-LABEL: @check_be_vec_sldwi_va_undef_0 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_vec_sldwi_va_undef_1(<4 x i32> %VA) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_1 +; CHECK-BE: xxsldwi 34, 34, 34, 1 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_vec_sldwi_va_undef_2(<4 x i32> %VA) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_2 +; CHECK-BE: xxswapd 34, 34 +; CHECK-BE: blr +} + +define <4 x i32> @check_be_vec_sldwi_va_undef_3(<4 x i32> %VA) { +entry: + %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2> + ret <4 x i32> %0 +; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_3 +; CHECK-BE: xxsldwi 34, 34, 34, 3 +; CHECK-BE: blr +} + +; More test cases to test different types of vector inputs +define <16 x i8> @test_le_vec_sldwi_v16i8_v16i8(<16 x i8> %VA, <16 x i8> %VB) { + entry: + %0 = shufflevector <16 x i8> %VA, <16 x i8> %VB,<16 x i32> <i32 28, i32 29, i32 30, i32 31,i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> + ret <16 x i8> %0 +; CHECK-LE-LABEL: @test_le_vec_sldwi_v16i8_v16i8 +; CHECK-LE: xxsldwi 34, 34, 35, 1 +; CHECK-LE: blr +} + +define <8 x i16> @test_le_vec_sldwi_v8i16_v8i16(<8 x i16> %VA, <8 x i16> %VB) { + entry: + %0 = shufflevector <8 x i16> %VA, <8 x i16> %VB,<8 x i32> <i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5> + ret <8 x i16> %0 +; CHECK-LE-LABEL: @test_le_vec_sldwi_v8i16_v8i16 +; CHECK-LE: xxsldwi 34, 34, 35, 1 +; CHECK-LE: blr +} + +; Note here xxpermdi 34, 34, 35, 2 <=> xxsldwi 34, 34, 35, 2 +define <2 x i64> @test_be_vec_sldwi_v2i64_v2i64(<2 x i64> %VA, <2 x i64> %VB) { + entry: + %0 = shufflevector <2 x i64> %VA, <2 x i64> %VB,<2 x i32> <i32 3, i32 0> + ret <2 x i64> %0 +; CHECK-LE-LABEL: @test_be_vec_sldwi_v2i64_v2i64 +; CHECK-LE: xxpermdi 34, 34, 35, 2 +; CHECK-LE: blr +} diff --git a/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll b/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll index acedc2606331..0f0426526cc1 100644 --- a/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll +++ b/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll @@ -26,82 +26,82 @@ entry: ; CHECK-LABEL: test1 ; CHECK-P9-LABEL: test1 ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %0 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vsi to i8*)) ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv store <4 x i32> %0, <4 x i32>* @res_vsi, align 16 ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %1 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vui to i8*)) ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv store <4 x i32> %1, <4 x i32>* @res_vui, align 16 ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x float>* @vf to i8*)) %3 = bitcast <4 x i32> %2 to <4 x float> ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv store <4 x float> %3, <4 x float>* @res_vf, align 16 ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %4 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vsll to i8*)) %5 = bitcast <2 x double> %4 to <2 x i64> ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv store <2 x i64> %5, <2 x i64>* @res_vsll, align 16 ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %6 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vull to i8*)) %7 = bitcast <2 x double> %6 to <2 x i64> ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv store <2 x i64> %7, <2 x i64>* @res_vull, align 16 ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %8 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x double>* @vd to i8*)) ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv store <2 x double> %8, <2 x double>* @res_vd, align 16 ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %9 = load <4 x i32>, <4 x i32>* @vsi, align 16 ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %9, i8* bitcast (<4 x i32>* @res_vsi to i8*)) ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %10 = load <4 x i32>, <4 x i32>* @vui, align 16 ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %10, i8* bitcast (<4 x i32>* @res_vui to i8*)) ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %11 = load <4 x float>, <4 x float>* @vf, align 16 %12 = bitcast <4 x float> %11 to <4 x i32> ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %12, i8* bitcast (<4 x float>* @res_vf to i8*)) ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %13 = load <2 x i64>, <2 x i64>* @vsll, align 16 %14 = bitcast <2 x i64> %13 to <2 x double> ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv call void @llvm.ppc.vsx.stxvd2x(<2 x double> %14, i8* bitcast (<2 x i64>* @res_vsll to i8*)) ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %15 = load <2 x i64>, <2 x i64>* @vull, align 16 %16 = bitcast <2 x i64> %15 to <2 x double> ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv call void @llvm.ppc.vsx.stxvd2x(<2 x double> %16, i8* bitcast (<2 x i64>* @res_vull to i8*)) ; CHECK: lxvd2x -; CHECK-P9-DAG: lxvx +; CHECK-P9-DAG: lxv %17 = load <2 x double>, <2 x double>* @vd, align 16 ; CHECK: stxvd2x -; CHECK-P9-DAG: stxvx +; CHECK-P9-DAG: stxv call void @llvm.ppc.vsx.stxvd2x(<2 x double> %17, i8* bitcast (<2 x double>* @res_vd to i8*)) ret void } diff --git a/test/CodeGen/PowerPC/vsx-ldst.ll b/test/CodeGen/PowerPC/vsx-ldst.ll index d8dd635aab5f..0bbc633363a7 100644 --- a/test/CodeGen/PowerPC/vsx-ldst.ll +++ b/test/CodeGen/PowerPC/vsx-ldst.ll @@ -21,8 +21,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t -; RUN: grep lxvx < %t | count 6 -; RUN: grep stxvx < %t | count 6 +; RUN: grep lxv < %t | count 6 +; RUN: grep stxv < %t | count 6 @vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16 diff --git a/test/CodeGen/PowerPC/vsx-p9.ll b/test/CodeGen/PowerPC/vsx-p9.ll index ba359501ccc5..0c29b6adad77 100644 --- a/test/CodeGen/PowerPC/vsx-p9.ll +++ b/test/CodeGen/PowerPC/vsx-p9.ll @@ -36,109 +36,109 @@ entry: %1 = load <16 x i8>, <16 x i8>* @ucb, align 16 %add.i = add <16 x i8> %1, %0 tail call void (...) @sink(<16 x i8> %add.i) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vaddubm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %2 = load <16 x i8>, <16 x i8>* @sca, align 16 %3 = load <16 x i8>, <16 x i8>* @scb, align 16 %add.i22 = add <16 x i8> %3, %2 tail call void (...) @sink(<16 x i8> %add.i22) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vaddubm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %4 = load <8 x i16>, <8 x i16>* @usa, align 16 %5 = load <8 x i16>, <8 x i16>* @usb, align 16 %add.i21 = add <8 x i16> %5, %4 tail call void (...) @sink(<8 x i16> %add.i21) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vadduhm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %6 = load <8 x i16>, <8 x i16>* @ssa, align 16 %7 = load <8 x i16>, <8 x i16>* @ssb, align 16 %add.i20 = add <8 x i16> %7, %6 tail call void (...) @sink(<8 x i16> %add.i20) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vadduhm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %8 = load <4 x i32>, <4 x i32>* @uia, align 16 %9 = load <4 x i32>, <4 x i32>* @uib, align 16 %add.i19 = add <4 x i32> %9, %8 tail call void (...) @sink(<4 x i32> %add.i19) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vadduwm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %10 = load <4 x i32>, <4 x i32>* @sia, align 16 %11 = load <4 x i32>, <4 x i32>* @sib, align 16 %add.i18 = add <4 x i32> %11, %10 tail call void (...) @sink(<4 x i32> %add.i18) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vadduwm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %12 = load <2 x i64>, <2 x i64>* @ulla, align 16 %13 = load <2 x i64>, <2 x i64>* @ullb, align 16 %add.i17 = add <2 x i64> %13, %12 tail call void (...) @sink(<2 x i64> %add.i17) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vaddudm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %14 = load <2 x i64>, <2 x i64>* @slla, align 16 %15 = load <2 x i64>, <2 x i64>* @sllb, align 16 %add.i16 = add <2 x i64> %15, %14 tail call void (...) @sink(<2 x i64> %add.i16) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vaddudm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %16 = load <1 x i128>, <1 x i128>* @uxa, align 16 %17 = load <1 x i128>, <1 x i128>* @uxb, align 16 %add.i15 = add <1 x i128> %17, %16 tail call void (...) @sink(<1 x i128> %add.i15) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vadduqm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %18 = load <1 x i128>, <1 x i128>* @sxa, align 16 %19 = load <1 x i128>, <1 x i128>* @sxb, align 16 %add.i14 = add <1 x i128> %19, %18 tail call void (...) @sink(<1 x i128> %add.i14) -; CHECK: lxvx 34, 0, 3 -; CHECK: lxvx 35, 0, 4 +; CHECK: lxv 34, 0(3) +; CHECK: lxv 35, 0(4) ; CHECK: vadduqm 2, 3, 2 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %20 = load <4 x float>, <4 x float>* @vfa, align 16 %21 = load <4 x float>, <4 x float>* @vfb, align 16 %add.i13 = fadd <4 x float> %20, %21 tail call void (...) @sink(<4 x float> %add.i13) -; CHECK: lxvx 0, 0, 3 -; CHECK: lxvx 1, 0, 4 +; CHECK: lxv 0, 0(3) +; CHECK: lxv 1, 0(4) ; CHECK: xvaddsp 34, 0, 1 -; CHECK: stxvx 34, +; CHECK: stxv 34, ; CHECK: bl sink %22 = load <2 x double>, <2 x double>* @vda, align 16 %23 = load <2 x double>, <2 x double>* @vdb, align 16 %add.i12 = fadd <2 x double> %22, %23 tail call void (...) @sink(<2 x double> %add.i12) -; CHECK: lxvx 0, 0, 3 -; CHECK: lxvx 1, 0, 4 +; CHECK: lxv 0, 0(3) +; CHECK: lxv 1, 0(4) ; CHECK: xvadddp 0, 0, 1 -; CHECK: stxvx 0, +; CHECK: stxv 0, ; CHECK: bl sink ret void } diff --git a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll index 09bf6830416f..98fe3a813cb7 100644 --- a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll +++ b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll @@ -23,7 +23,7 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) { ; CHECK-P9-LABEL: testi0 ; CHECK-P9: lfd [[REG1:[0-9]+]], 0(4) -; CHECK-P9: lxvx [[REG2:[0-9]+]], 0, 3 +; CHECK-P9: lxv [[REG2:[0-9]+]], 0(3) ; CHECK-P9: xxspltd [[REG3:[0-9]+]], [[REG1]], 0 ; CHECK-P9: xxpermdi 34, [[REG2]], [[REG3]], 1 } @@ -43,7 +43,7 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) { ; CHECK-P9-LABEL: testi1 ; CHECK-P9: lfd [[REG1:[0-9]+]], 0(4) -; CHECK-P9: lxvx [[REG2:[0-9]+]], 0, 3 +; CHECK-P9: lxv [[REG2:[0-9]+]], 0(3) ; CHECK-P9: xxspltd [[REG3:[0-9]+]], [[REG1]], 0 ; CHECK-P9: xxmrgld 34, [[REG3]], [[REG2]] } diff --git a/test/CodeGen/PowerPC/vsx_shuffle_le.ll b/test/CodeGen/PowerPC/vsx_shuffle_le.ll index 3bf24adfdd91..cfe201999282 100644 --- a/test/CodeGen/PowerPC/vsx_shuffle_le.ll +++ b/test/CodeGen/PowerPC/vsx_shuffle_le.ll @@ -19,7 +19,7 @@ define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxspltd 34, 0, 0 ; CHECK-P9-LABEL: test00 -; CHECK-P9: lxvx 0, 0, 3 +; CHECK-P9: lxv 0, 0(3) ; CHECK-P9: xxspltd 34, 0, 1 } @@ -34,7 +34,7 @@ define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxswapd 34, 0 ; CHECK-P9-LABEL: test01 -; CHECK-P9: lxvx 34, 0, 3 +; CHECK-P9: lxv 34, 0(3) } define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) { @@ -51,8 +51,8 @@ define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxmrgld 34, 1, 0 ; CHECK-P9-LABEL: @test02 -; CHECK-P9: lxvx 0, 0, 3 -; CHECK-P9: lxvx 1, 0, 4 +; CHECK-P9: lxv 0, 0(3) +; CHECK-P9: lxv 1, 0(4) ; CHECK-P9: xxmrgld 34, 1, 0 } @@ -70,8 +70,8 @@ define <2 x double> @test03(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxpermdi 34, 1, 0, 1 ; CHECK-P9-LABEL: @test03 -; CHECK-P9: lxvx 0, 0, 3 -; CHECK-P9: lxvx 1, 0, 4 +; CHECK-P9: lxv 0, 0(3) +; CHECK-P9: lxv 1, 0(4) ; CHECK-P9: xxpermdi 34, 1, 0, 1 } @@ -85,7 +85,7 @@ define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: lxvd2x 34, 0, 3 ; CHECK-P9-LABEL: @test10 -; CHECK-P9: lxvx 0, 0, 3 +; CHECK-P9: lxv 0, 0(3) ; CHECK-P9: xxswapd 34, 0 } @@ -100,7 +100,7 @@ define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxspltd 34, 0, 1 ; CHECK-P9-LABEL: @test11 -; CHECK-P9: lxvx 0, 0, 3 +; CHECK-P9: lxv 0, 0(3) ; CHECK-P9: xxspltd 34, 0, 0 } @@ -118,8 +118,8 @@ define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxpermdi 34, 1, 0, 2 ; CHECK-P9-LABEL: @test12 -; CHECK-P9: lxvx 0, 0, 3 -; CHECK-P9: lxvx 1, 0, 4 +; CHECK-P9: lxv 0, 0(3) +; CHECK-P9: lxv 1, 0(4) ; CHECK-P9: xxpermdi 34, 1, 0, 2 } @@ -137,8 +137,8 @@ define <2 x double> @test13(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxmrghd 34, 1, 0 ; CHECK-P9-LABEL: @test13 -; CHECK-P9: lxvx 0, 0, 3 -; CHECK-P9: lxvx 1, 0, 4 +; CHECK-P9: lxv 0, 0(3) +; CHECK-P9: lxv 1, 0(4) ; CHECK-P9: xxmrghd 34, 1, 0 } @@ -156,8 +156,8 @@ define <2 x double> @test20(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxmrgld 34, 0, 1 ; CHECK-P9-LABEL: @test20 -; CHECK-P9: lxvx 0, 0, 3 -; CHECK-P9: lxvx 1, 0, 4 +; CHECK-P9: lxv 0, 0(3) +; CHECK-P9: lxv 1, 0(4) ; CHECK-P9: xxmrgld 34, 0, 1 } @@ -175,8 +175,8 @@ define <2 x double> @test21(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxpermdi 34, 0, 1, 1 ; CHECK-P9-LABEL: @test21 -; CHECK-P9: lxvx 0, 0, 3 -; CHECK-P9: lxvx 1, 0, 4 +; CHECK-P9: lxv 0, 0(3) +; CHECK-P9: lxv 1, 0(4) ; CHECK-P9: xxpermdi 34, 0, 1, 1 } @@ -191,7 +191,7 @@ define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxspltd 34, 0, 0 ; CHECK-P9-LABEL: @test22 -; CHECK-P9: lxvx 0, 0, 4 +; CHECK-P9: lxv 0, 0(4) ; CHECK-P9: xxspltd 34, 0, 1 } @@ -206,7 +206,7 @@ define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxswapd 34, 0 ; CHECK-P9-LABEL: @test23 -; CHECK-P9: lxvx 34, 0, 4 +; CHECK-P9: lxv 34, 0(4) } define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) { @@ -223,8 +223,8 @@ define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxpermdi 34, 0, 1, 2 ; CHECK-P9-LABEL: @test30 -; CHECK-P9: lxvx 0, 0, 3 -; CHECK-P9: lxvx 1, 0, 4 +; CHECK-P9: lxv 0, 0(3) +; CHECK-P9: lxv 1, 0(4) ; CHECK-P9: xxpermdi 34, 0, 1, 2 } @@ -242,8 +242,8 @@ define <2 x double> @test31(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxmrghd 34, 0, 1 ; CHECK-P9-LABEL: @test31 -; CHECK-P9: lxvx 0, 0, 3 -; CHECK-P9: lxvx 1, 0, 4 +; CHECK-P9: lxv 0, 0(3) +; CHECK-P9: lxv 1, 0(4) ; CHECK-P9: xxmrghd 34, 0, 1 } @@ -257,7 +257,7 @@ define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: lxvd2x 34, 0, 4 ; CHECK-P9-LABEL: @test32 -; CHECK-P9: lxvx 0, 0, 4 +; CHECK-P9: lxv 0, 0(4) ; CHECK-P9: xxswapd 34, 0 } @@ -272,6 +272,6 @@ define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) { ; CHECK: xxspltd 34, 0, 1 ; CHECK-P9-LABEL: @test33 -; CHECK-P9: lxvx 0, 0, 4 +; CHECK-P9: lxv 0, 0(4) ; CHECK-P9: xxspltd 34, 0, 0 } diff --git a/test/CodeGen/Thumb/machine-cse-physreg.mir b/test/CodeGen/Thumb/machine-cse-physreg.mir new file mode 100644 index 000000000000..5206e89cf779 --- /dev/null +++ b/test/CodeGen/Thumb/machine-cse-physreg.mir @@ -0,0 +1,35 @@ +# RUN: llc -mtriple thumbv5e -run-pass=machine-cse -o - %s | FileCheck %s + +# This is a contrived example made to expose a bug in +# MachineCSE, see PR32538. + +# MachineCSE must not remove this def of %cpsr: +# CHECK-LABEL: bb.1: +# CHECK: , %cpsr = tLSLri + +... +--- +name: spam +registers: + - { id: 0, class: tgpr } + - { id: 1, class: tgpr } + - { id: 2, class: tgpr } + - { id: 3, class: tgpr } +liveins: + - { reg: '%r0', virtual-reg: '%0' } +body: | + bb.0: + liveins: %r0 + %0 = COPY %r0 + %1, %cpsr = tLSLri %0, 2, 14, _ + tCMPi8 %0, 5, 14, _, implicit-def %cpsr + tBcc %bb.8, 8, %cpsr + + bb.1: + %2, %cpsr = tLSLri %0, 2, 14, _ + + bb.8: + liveins: %cpsr + %3 = COPY %cpsr + tSTRi killed %3, %0, 0, 14, _ +... diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll index 172a00a7c86f..89cb71a52c04 100644 --- a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll +++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn -stats 2>&1 | grep "9 machine-licm" +; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn -stats 2>&1 | grep "9 machinelicm" ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn | FileCheck %s ; rdar://6627786 ; rdar://7792037 diff --git a/test/CodeGen/X86/GlobalISel/memop-vec.ll b/test/CodeGen/X86/GlobalISel/memop-vec.ll index f1ffc15f4d03..870e812bbb69 100644 --- a/test/CodeGen/X86/GlobalISel/memop-vec.ll +++ b/test/CodeGen/X86/GlobalISel/memop-vec.ll @@ -1,39 +1,116 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SKX -; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -regbankselect-greedy -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SKX +; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=SKX +; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -regbankselect-greedy -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=SKX define <4 x i32> @test_load_v4i32_noalign(<4 x i32> * %p1) { -; ALL-LABEL: test_load_v4i32_noalign: -; ALL: # BB#0: -; ALL-NEXT: vmovups (%rdi), %xmm0 -; ALL-NEXT: retq +; SKX-LABEL: test_load_v4i32_noalign: +; SKX: # BB#0: +; SKX-NEXT: vmovups (%rdi), %xmm0 +; SKX-NEXT: retq %r = load <4 x i32>, <4 x i32>* %p1, align 1 ret <4 x i32> %r } define <4 x i32> @test_load_v4i32_align(<4 x i32> * %p1) { -; ALL-LABEL: test_load_v4i32_align: -; ALL: # BB#0: -; ALL-NEXT: vmovaps (%rdi), %xmm0 -; ALL-NEXT: retq +; SKX-LABEL: test_load_v4i32_align: +; SKX: # BB#0: +; SKX-NEXT: vmovaps (%rdi), %xmm0 +; SKX-NEXT: retq %r = load <4 x i32>, <4 x i32>* %p1, align 16 ret <4 x i32> %r } +define <8 x i32> @test_load_v8i32_noalign(<8 x i32> * %p1) { +; SKX-LABEL: test_load_v8i32_noalign: +; SKX: # BB#0: +; SKX-NEXT: vmovups (%rdi), %ymm0 +; SKX-NEXT: retq + %r = load <8 x i32>, <8 x i32>* %p1, align 1 + ret <8 x i32> %r +} + +define <8 x i32> @test_load_v8i32_align(<8 x i32> * %p1) { +; SKX-LABEL: test_load_v8i32_align: +; SKX: # BB#0: +; SKX-NEXT: vmovaps (%rdi), %ymm0 +; SKX-NEXT: retq + %r = load <8 x i32>, <8 x i32>* %p1, align 32 + ret <8 x i32> %r +} + +define <16 x i32> @test_load_v16i32_noalign(<16 x i32> * %p1) { +; SKX-LABEL: test_load_v16i32_noalign: +; SKX: # BB#0: +; SKX-NEXT: vmovups (%rdi), %zmm0 +; SKX-NEXT: retq + %r = load <16 x i32>, <16 x i32>* %p1, align 1 + ret <16 x i32> %r +} + +define <16 x i32> @test_load_v16i32_align(<16 x i32> * %p1) { +; SKX-LABEL: test_load_v16i32_align: +; SKX: # BB#0: +; SKX-NEXT: vmovups (%rdi), %zmm0 +; SKX-NEXT: retq + %r = load <16 x i32>, <16 x i32>* %p1, align 32 + ret <16 x i32> %r +} + define void @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) { -; ALL-LABEL: test_store_v4i32_noalign: -; ALL: # BB#0: -; ALL-NEXT: vmovups %xmm0, (%rdi) -; ALL-NEXT: retq +; SKX-LABEL: test_store_v4i32_noalign: +; SKX: # BB#0: +; SKX-NEXT: vmovups %xmm0, (%rdi) +; SKX-NEXT: retq store <4 x i32> %val, <4 x i32>* %p1, align 1 ret void } define void @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) { -; ALL-LABEL: test_store_v4i32_align: -; ALL: # BB#0: -; ALL-NEXT: vmovaps %xmm0, (%rdi) -; ALL-NEXT: retq +; SKX-LABEL: test_store_v4i32_align: +; SKX: # BB#0: +; SKX-NEXT: vmovaps %xmm0, (%rdi) +; SKX-NEXT: retq store <4 x i32> %val, <4 x i32>* %p1, align 16 ret void } + +define void @test_store_v8i32_noalign(<8 x i32> %val, <8 x i32>* %p1) { +; SKX-LABEL: test_store_v8i32_noalign: +; SKX: # BB#0: +; SKX-NEXT: vmovups %ymm0, (%rdi) +; SKX-NEXT: vzeroupper +; SKX-NEXT: retq + store <8 x i32> %val, <8 x i32>* %p1, align 1 + ret void +} + +define void @test_store_v8i32_align(<8 x i32> %val, <8 x i32>* %p1) { +; SKX-LABEL: test_store_v8i32_align: +; SKX: # BB#0: +; SKX-NEXT: vmovaps %ymm0, (%rdi) +; SKX-NEXT: vzeroupper +; SKX-NEXT: retq + store <8 x i32> %val, <8 x i32>* %p1, align 32 + ret void +} + +define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) { +; SKX-LABEL: test_store_v16i32_noalign: +; SKX: # BB#0: +; SKX-NEXT: vmovups %zmm0, (%rdi) +; SKX-NEXT: vzeroupper +; SKX-NEXT: retq + store <16 x i32> %val, <16 x i32>* %p1, align 1 + ret void +} + +define void @test_store_v16i32_align(<16 x i32> %val, <16 x i32>* %p1) { +; SKX-LABEL: test_store_v16i32_align: +; SKX: # BB#0: +; SKX-NEXT: vmovaps %zmm0, (%rdi) +; SKX-NEXT: vzeroupper +; SKX-NEXT: retq + store <16 x i32> %val, <16 x i32>* %p1, align 64 + ret void +} + diff --git a/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir b/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir index f925c836f3d1..cc03f3a57f0b 100644 --- a/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir +++ b/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir @@ -14,7 +14,16 @@ ret void } -... + define <8 x i32> @test_load_v8i32_noalign(<8 x i32>* %p1) { + %r = load <8 x i32>, <8 x i32>* %p1, align 1 + ret <8 x i32> %r + } + + define void @test_store_v8i32_noalign(<8 x i32> %val, <8 x i32>* %p1) { + store <8 x i32> %val, <8 x i32>* %p1, align 1 + ret void + } + --- name: test_mul_vec256 alignment: 4 @@ -84,3 +93,47 @@ body: | RET 0 ... +--- +name: test_load_v8i32_noalign +# CHECK-LABEL: name: test_load_v8i32_noalign +alignment: 4 +legalized: true +regBankSelected: false +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK-NEXT: - { id: 1, class: vecr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: %rdi + + %0(p0) = COPY %rdi + %1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1, align 1) + %ymm0 = COPY %1(<8 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_store_v8i32_noalign +# CHECK-LABEL: name: test_store_v8i32_noalign +alignment: 4 +legalized: true +regBankSelected: false +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: vecr } +# CHECK-NEXT: - { id: 1, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: %rdi, %ymm0 + + %0(<8 x s32>) = COPY %ymm0 + %1(p0) = COPY %rdi + G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1, align 1) + RET 0 + +... diff --git a/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir b/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir index e0c12ff44a2f..278413ad38ef 100644 --- a/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir +++ b/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir @@ -15,22 +15,29 @@ ret void } + define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) { + %r = load <16 x i32>, <16 x i32>* %p1, align 1 + ret <16 x i32> %r + } + + define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) { + store <16 x i32> %val, <16 x i32>* %p1, align 1 + ret void + } + ... --- name: test_mul_vec512 +# CHECK-LABEL: name: test_mul_vec512 alignment: 4 legalized: true regBankSelected: false -selected: false -tracksRegLiveness: true -# CHECK-LABEL: name: test_mul_vec512 -# CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: vecr } +# CHECK-NEXT: - { id: 1, class: vecr } registers: - { id: 0, class: _ } - { id: 1, class: _ } - - { id: 2, class: _ } body: | bb.1 (%ir-block.0): @@ -41,19 +48,16 @@ body: | ... --- name: test_add_vec512 +# CHECK-LABEL: name: test_add_vec512 alignment: 4 legalized: true regBankSelected: false -selected: false -tracksRegLiveness: true -# CHECK-LABEL: name: test_add_vec512 -# CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: vecr } +# CHECK-NEXT: - { id: 1, class: vecr } registers: - { id: 0, class: _ } - { id: 1, class: _ } - - { id: 2, class: _ } body: | bb.1 (%ir-block.0): @@ -64,24 +68,65 @@ body: | ... --- name: test_sub_vec512 +# CHECK-LABEL: name: test_sub_vec512 alignment: 4 legalized: true regBankSelected: false -selected: false -tracksRegLiveness: true -# CHECK-LABEL: name: test_sub_vec512 -# CHECK: registers: -# CHECK: - { id: 0, class: vecr } -# CHECK: - { id: 1, class: vecr } +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: vecr } +# CHECK-NEXT: - { id: 1, class: vecr } registers: - { id: 0, class: _ } - { id: 1, class: _ } - - { id: 2, class: _ } body: | bb.1 (%ir-block.0): %0(<16 x s32>) = IMPLICIT_DEF %1(<16 x s32>) = G_SUB %0, %0 RET 0 +... +--- + +name: test_load_v16i32_noalign +# CHECK-LABEL: name: test_load_v16i32_noalign +alignment: 4 +legalized: true +regBankSelected: false +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK-NEXT: - { id: 1, class: vecr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: %rdi + + %0(p0) = COPY %rdi + %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1) + %zmm0 = COPY %1(<16 x s32>) + RET 0, implicit %zmm0 + +... +--- +name: test_store_v16i32_noalign +# CHECK-LABEL: name: test_store_v16i32_noalign +alignment: 4 +legalized: true +regBankSelected: false +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: vecr } +# CHECK-NEXT: - { id: 1, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.1 (%ir-block.0): + liveins: %rdi, %zmm0 + + %0(<16 x s32>) = COPY %zmm0 + %1(p0) = COPY %rdi + G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1) + RET 0 ... diff --git a/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir b/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir new file mode 100644 index 000000000000..539520c0b8f5 --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir @@ -0,0 +1,96 @@ +# RUN: llc -mtriple=i586-linux-gnu -mcpu=haswell -mattr=-slow-incdec -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK +# +# This is necessary to test that attribute-based rule predicates work and that +# they properly reset between functions. + +--- | + define i32 @const_i32_1() { + ret i32 1 + } + + define i32 @const_i32_1_optsize() #0 { + ret i32 1 + } + + define i32 @const_i32_1b() { + ret i32 1 + } + + define i32 @const_i32_1_optsizeb() #0 { + ret i32 1 + } + + attributes #0 = { optsize } +... +--- +name: const_i32_1 +legalized: true +regBankSelected: true +selected: false +# CHECK-LABEL: name: const_i32_1 +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gr32 } +registers: + - { id: 0, class: gpr } +# CHECK: body: +# CHECK: %0 = MOV32ri 1 +body: | + bb.1 (%ir-block.0): + %0(s32) = G_CONSTANT i32 1 + %eax = COPY %0(s32) + RET 0, implicit %eax +... +--- +name: const_i32_1_optsize +legalized: true +regBankSelected: true +selected: false +# CHECK-LABEL: name: const_i32_1_optsize +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gr32 } +registers: + - { id: 0, class: gpr } +# CHECK: body: +# CHECK: %0 = MOV32r1 +body: | + bb.1 (%ir-block.0): + %0(s32) = G_CONSTANT i32 1 + %eax = COPY %0(s32) + RET 0, implicit %eax +... +--- +name: const_i32_1b +legalized: true +regBankSelected: true +selected: false +# CHECK-LABEL: name: const_i32_1b +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gr32 } +registers: + - { id: 0, class: gpr } +# CHECK: body: +# CHECK: %0 = MOV32ri 1 +body: | + bb.1 (%ir-block.0): + %0(s32) = G_CONSTANT i32 1 + %eax = COPY %0(s32) + RET 0, implicit %eax +... +--- +name: const_i32_1_optsizeb +legalized: true +regBankSelected: true +selected: false +# CHECK-LABEL: name: const_i32_1_optsizeb +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gr32 } +registers: + - { id: 0, class: gpr } +# CHECK: body: +# CHECK: %0 = MOV32r1 +body: | + bb.1 (%ir-block.0): + %0(s32) = G_CONSTANT i32 1 + %eax = COPY %0(s32) + RET 0, implicit %eax +... diff --git a/test/CodeGen/X86/GlobalISel/select-memop-v256.mir b/test/CodeGen/X86/GlobalISel/select-memop-v256.mir new file mode 100644 index 000000000000..b9a7e4a8cc4a --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/select-memop-v256.mir @@ -0,0 +1,188 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL + + +--- | + define <8 x i32> @test_load_v8i32_noalign(<8 x i32>* %p1) { + %r = load <8 x i32>, <8 x i32>* %p1, align 1 + ret <8 x i32> %r + } + + define <8 x i32> @test_load_v8i32_align(<8 x i32>* %p1) { + %r = load <8 x i32>, <8 x i32>* %p1, align 32 + ret <8 x i32> %r + } + + define void @test_store_v8i32_noalign(<8 x i32> %val, <8 x i32>* %p1) { + store <8 x i32> %val, <8 x i32>* %p1, align 1 + ret void + } + + define void @test_store_v8i32_align(<8 x i32> %val, <8 x i32>* %p1) { + store <8 x i32> %val, <8 x i32>* %p1, align 32 + ret void + } + + +... +--- +name: test_load_v8i32_noalign +# ALL-LABEL: name: test_load_v8i32_noalign +alignment: 4 +legalized: true +regBankSelected: true +# NO_AVX512F: registers: +# NO_AVX512F-NEXT: - { id: 0, class: gr64 } +# NO_AVX512F-NEXT: - { id: 1, class: vr256 } +# +# AVX512ALL: registers: +# AVX512ALL-NEXT: - { id: 0, class: gr64 } +# AVX512ALL-NEXT: - { id: 1, class: vr256x } +registers: + - { id: 0, class: gpr } + - { id: 1, class: vecr } +# NO_AVX512F: %0 = COPY %rdi +# NO_AVX512F-NEXT: %1 = VMOVUPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1) +# NO_AVX512F-NEXT: %ymm0 = COPY %1 +# NO_AVX512F-NEXT: RET 0, implicit %ymm0 +# +# AVX512F: %0 = COPY %rdi +# AVX512F-NEXT: %1 = VMOVUPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1) +# AVX512F-NEXT: %ymm0 = COPY %1 +# AVX512F-NEXT: RET 0, implicit %ymm0 +# +# AVX512VL: %0 = COPY %rdi +# AVX512VL-NEXT: %1 = VMOVUPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1) +# AVX512VL-NEXT: %ymm0 = COPY %1 +# AVX512VL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %rdi + + %0(p0) = COPY %rdi + %1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1, align 1) + %ymm0 = COPY %1(<8 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_load_v8i32_align +# ALL-LABEL: name: test_load_v8i32_align +alignment: 4 +legalized: true +regBankSelected: true +# NO_AVX512F: registers: +# NO_AVX512F-NEXT: - { id: 0, class: gr64 } +# NO_AVX512F-NEXT: - { id: 1, class: vr256 } +# +# AVX512ALL: registers: +# AVX512ALL-NEXT: - { id: 0, class: gr64 } +# AVX512ALL-NEXT: - { id: 1, class: vr256x } +registers: + - { id: 0, class: gpr } + - { id: 1, class: vecr } +# NO_AVX512F: %0 = COPY %rdi +# NO_AVX512F-NEXT: %1 = VMOVAPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1) +# NO_AVX512F-NEXT: %ymm0 = COPY %1 +# NO_AVX512F-NEXT: RET 0, implicit %ymm0 +# +# AVX512F: %0 = COPY %rdi +# AVX512F-NEXT: %1 = VMOVAPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1) +# AVX512F-NEXT: %ymm0 = COPY %1 +# AVX512F-NEXT: RET 0, implicit %ymm0 +# +# AVX512VL: %0 = COPY %rdi +# AVX512VL-NEXT: %1 = VMOVAPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1) +# AVX512VL-NEXT: %ymm0 = COPY %1 +# AVX512VL-NEXT: RET 0, implicit %ymm0 +body: | + bb.1 (%ir-block.0): + liveins: %rdi + + %0(p0) = COPY %rdi + %1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1) + %ymm0 = COPY %1(<8 x s32>) + RET 0, implicit %ymm0 + +... +--- +name: test_store_v8i32_noalign +# ALL-LABEL: name: test_store_v8i32_noalign +alignment: 4 +legalized: true +regBankSelected: true +# NO_AVX512F: registers: +# NO_AVX512F-NEXT: - { id: 0, class: vr256 } +# NO_AVX512F-NEXT: - { id: 1, class: gr64 } +# +# AVX512ALL: registers: +# AVX512ALL-NEXT: - { id: 0, class: vr256x } +# AVX512ALL-NEXT: - { id: 1, class: gr64 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: gpr } +# NO_AVX512F: %0 = COPY %ymm0 +# NO_AVX512F-NEXT: %1 = COPY %rdi +# NO_AVX512F-NEXT: VMOVUPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1) +# NO_AVX512F-NEXT: RET 0 +# +# AVX512F: %0 = COPY %ymm0 +# AVX512F-NEXT: %1 = COPY %rdi +# AVX512F-NEXT: VMOVUPSZ256mr_NOVLX %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1) +# AVX512F-NEXT: RET 0 +# +# AVX512VL: %0 = COPY %ymm0 +# AVX512VL-NEXT: %1 = COPY %rdi +# AVX512VL-NEXT: VMOVUPSZ256mr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1) +# AVX512VL-NEXT: RET 0 +body: | + bb.1 (%ir-block.0): + liveins: %rdi, %ymm0 + + %0(<8 x s32>) = COPY %ymm0 + %1(p0) = COPY %rdi + G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1, align 1) + RET 0 + +... +--- +name: test_store_v8i32_align +# ALL-LABEL: name: test_store_v8i32_align +alignment: 4 +legalized: true +regBankSelected: true +# NO_AVX512F: registers: +# NO_AVX512F-NEXT: - { id: 0, class: vr256 } +# NO_AVX512F-NEXT: - { id: 1, class: gr64 } +# +# AVX512ALL: registers: +# AVX512ALL-NEXT: - { id: 0, class: vr256x } +# AVX512ALL-NEXT: - { id: 1, class: gr64 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: gpr } +# NO_AVX512F: %0 = COPY %ymm0 +# NO_AVX512F-NEXT: %1 = COPY %rdi +# NO_AVX512F-NEXT: VMOVAPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1) +# NO_AVX512F-NEXT: RET 0 +# +# AVX512F: %0 = COPY %ymm0 +# AVX512F-NEXT: %1 = COPY %rdi +# AVX512F-NEXT: VMOVAPSZ256mr_NOVLX %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1) +# AVX512F-NEXT: RET 0 +# +# AVX512VL: %0 = COPY %ymm0 +# AVX512VL-NEXT: %1 = COPY %rdi +# AVX512VL-NEXT: VMOVAPSZ256mr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1) +# AVX512VL-NEXT: RET 0 +body: | + bb.1 (%ir-block.0): + liveins: %rdi, %ymm0 + + %0(<8 x s32>) = COPY %ymm0 + %1(p0) = COPY %rdi + G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1) + RET 0 + +... diff --git a/test/CodeGen/X86/GlobalISel/select-memop-v512.mir b/test/CodeGen/X86/GlobalISel/select-memop-v512.mir new file mode 100644 index 000000000000..87978a684d4c --- /dev/null +++ b/test/CodeGen/X86/GlobalISel/select-memop-v512.mir @@ -0,0 +1,127 @@ +# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F +--- | + define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) { + %r = load <16 x i32>, <16 x i32>* %p1, align 1 + ret <16 x i32> %r + } + + define <16 x i32> @test_load_v16i32_align(<16 x i32>* %p1) { + %r = load <16 x i32>, <16 x i32>* %p1, align 32 + ret <16 x i32> %r + } + + define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) { + store <16 x i32> %val, <16 x i32>* %p1, align 1 + ret void + } + + define void @test_store_v16i32_align(<16 x i32> %val, <16 x i32>* %p1) { + store <16 x i32> %val, <16 x i32>* %p1, align 32 + ret void + } + +... +--- +name: test_load_v16i32_noalign +# AVX512F-LABEL: name: test_load_v16i32_noalign +alignment: 4 +legalized: true +regBankSelected: true +# AVX512F: registers: +# AVX512F-NEXT: - { id: 0, class: gr64 } +# AVX512F-NEXT: - { id: 1, class: vr512 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: vecr } +# AVX512F: %0 = COPY %rdi +# AVX512F-NEXT: %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 1) +# AVX512F-NEXT: %zmm0 = COPY %1 +# AVX512F-NEXT: RET 0, implicit %zmm0 +body: | + bb.1 (%ir-block.0): + liveins: %rdi + + %0(p0) = COPY %rdi + %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1) + %zmm0 = COPY %1(<16 x s32>) + RET 0, implicit %zmm0 + +... +--- +name: test_load_v16i32_align +# AVX512F-LABEL: name: test_load_v16i32_align +alignment: 4 +legalized: true +regBankSelected: true +# AVX512F: registers: +# AVX512F-NEXT: - { id: 0, class: gr64 } +# AVX512F-NEXT: - { id: 1, class: vr512 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: vecr } +# AVX512F: %0 = COPY %rdi +# AVX512F-NEXT: %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 32) +# AVX512F-NEXT: %zmm0 = COPY %1 +# AVX512F-NEXT: RET 0, implicit %zmm0 +body: | + bb.1 (%ir-block.0): + liveins: %rdi + + %0(p0) = COPY %rdi + %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32) + %zmm0 = COPY %1(<16 x s32>) + RET 0, implicit %zmm0 + +... +--- +name: test_store_v16i32_noalign +# AVX512F-LABEL: name: test_store_v16i32_noalign +alignment: 4 +legalized: true +regBankSelected: true +# AVX512F: registers: +# AVX512F-NEXT: - { id: 0, class: vr512 } +# AVX512F-NEXT: - { id: 1, class: gr64 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: gpr } +# AVX512F: %0 = COPY %zmm0 +# AVX512F-NEXT: %1 = COPY %rdi +# AVX512F-NEXT: VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 1) +# AVX512F-NEXT: RET 0 +body: | + bb.1 (%ir-block.0): + liveins: %rdi, %zmm0 + + %0(<16 x s32>) = COPY %zmm0 + %1(p0) = COPY %rdi + G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1) + RET 0 + +... +--- +name: test_store_v16i32_align +# AVX512F-LABEL: name: test_store_v16i32_align +alignment: 4 +legalized: true +regBankSelected: true +# AVX512F: registers: +# AVX512F-NEXT: - { id: 0, class: vr512 } +# AVX512F-NEXT: - { id: 1, class: gr64 } +registers: + - { id: 0, class: vecr } + - { id: 1, class: gpr } +# AVX512F: %0 = COPY %zmm0 +# AVX512F-NEXT: %1 = COPY %rdi +# AVX512F-NEXT: VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 32) +# AVX512F-NEXT: RET 0 +body: | + bb.1 (%ir-block.0): + liveins: %rdi, %zmm0 + + %0(<16 x s32>) = COPY %zmm0 + %1(p0) = COPY %rdi + G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 32) + RET 0 + +... diff --git a/test/CodeGen/X86/avx-vzeroupper.ll b/test/CodeGen/X86/avx-vzeroupper.ll index cf514d7aeb31..016ddb9c5e78 100644 --- a/test/CodeGen/X86/avx-vzeroupper.ll +++ b/test/CodeGen/X86/avx-vzeroupper.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s -; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck %s -; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-apple-darwin -mattr=+avx,+fast-partial-ymm-or-zmm-write | FileCheck --check-prefix=FAST-YMM-ZMM %s -; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-apple-darwin -mcpu=btver2 | FileCheck --check-prefix=BTVER2 %s - -; FAST-YMM-ZMM-NOT: vzeroupper -; BTVER2-NOT: vzeroupper +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX +; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX512 +; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,+fast-partial-ymm-or-zmm-write | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=FAST-YMM-ZMM +; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=BTVER2 declare i32 @foo() declare <4 x float> @do_sse(<4 x float>) @@ -15,43 +13,86 @@ declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind ;; Basic checking - don't emit any vzeroupper instruction -; CHECK: _test00 -define <4 x float> @test00(<4 x float> %a, <4 x float> %b) nounwind uwtable ssp { -entry: - ; CHECK-NOT: vzeroupper +define <4 x float> @test00(<4 x float> %a, <4 x float> %b) nounwind { +; ALL-LABEL: test00: +; ALL: # BB#0: +; ALL-NEXT: pushq %rax +; ALL-NEXT: vaddps %xmm1, %xmm0, %xmm0 +; ALL-NEXT: callq do_sse +; ALL-NEXT: popq %rax +; ALL-NEXT: retq %add.i = fadd <4 x float> %a, %b %call3 = call <4 x float> @do_sse(<4 x float> %add.i) nounwind - ; CHECK: ret ret <4 x float> %call3 } ;; Check parameter 256-bit parameter passing -; CHECK: _test01 -define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounwind uwtable ssp { -entry: +define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounwind { +; VZ-LABEL: test01: +; VZ: # BB#0: +; VZ-NEXT: subq $56, %rsp +; VZ-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill +; VZ-NEXT: vmovaps {{.*}}(%rip), %xmm0 +; VZ-NEXT: vzeroupper +; VZ-NEXT: callq do_sse +; VZ-NEXT: vmovaps %xmm0, {{.*}}(%rip) +; VZ-NEXT: callq do_sse +; VZ-NEXT: vmovaps %xmm0, {{.*}}(%rip) +; VZ-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload +; VZ-NEXT: addq $56, %rsp +; VZ-NEXT: retq +; +; FAST-YMM-ZMM-LABEL: test01: +; FAST-YMM-ZMM: # BB#0: +; FAST-YMM-ZMM-NEXT: subq $56, %rsp +; FAST-YMM-ZMM-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill +; FAST-YMM-ZMM-NEXT: vmovaps {{.*}}(%rip), %xmm0 +; FAST-YMM-ZMM-NEXT: callq do_sse +; FAST-YMM-ZMM-NEXT: vmovaps %xmm0, {{.*}}(%rip) +; FAST-YMM-ZMM-NEXT: callq do_sse +; FAST-YMM-ZMM-NEXT: vmovaps %xmm0, {{.*}}(%rip) +; FAST-YMM-ZMM-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload +; FAST-YMM-ZMM-NEXT: addq $56, %rsp +; FAST-YMM-ZMM-NEXT: retq +; +; BTVER2-LABEL: test01: +; BTVER2: # BB#0: +; BTVER2-NEXT: subq $56, %rsp +; BTVER2-NEXT: vmovaps {{.*}}(%rip), %xmm0 +; BTVER2-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill +; BTVER2-NEXT: callq do_sse +; BTVER2-NEXT: vmovaps %xmm0, {{.*}}(%rip) +; BTVER2-NEXT: callq do_sse +; BTVER2-NEXT: vmovaps %xmm0, {{.*}}(%rip) +; BTVER2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload +; BTVER2-NEXT: addq $56, %rsp +; BTVER2-NEXT: retq %tmp = load <4 x float>, <4 x float>* @x, align 16 - ; CHECK: vzeroupper - ; CHECK-NEXT: callq _do_sse %call = tail call <4 x float> @do_sse(<4 x float> %tmp) nounwind store <4 x float> %call, <4 x float>* @x, align 16 - ; CHECK-NOT: vzeroupper - ; CHECK: callq _do_sse %call2 = tail call <4 x float> @do_sse(<4 x float> %call) nounwind store <4 x float> %call2, <4 x float>* @x, align 16 - ; CHECK: ret ret <8 x float> %c } ;; Check that vzeroupper is emitted for tail calls. -; CHECK: _test02 -define <4 x float> @test02(<8 x float> %a, <8 x float> %b) nounwind uwtable ssp { -entry: +define <4 x float> @test02(<8 x float> %a, <8 x float> %b) nounwind { +; VZ-LABEL: test02: +; VZ: # BB#0: +; VZ-NEXT: vaddps %ymm1, %ymm0, %ymm0 +; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; VZ-NEXT: vzeroupper +; VZ-NEXT: jmp do_sse # TAILCALL +; +; NO-VZ-LABEL: test02: +; NO-VZ: # BB#0: +; NO-VZ-NEXT: vaddps %ymm1, %ymm0, %ymm0 +; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; NO-VZ-NEXT: jmp do_sse # TAILCALL %add.i = fadd <8 x float> %a, %b %add.low = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %add.i, i8 0) - ; CHECK: vzeroupper - ; CHECK: jmp _do_sse %call3 = tail call <4 x float> @do_sse(<4 x float> %add.low) nounwind ret <4 x float> %call3 } @@ -59,30 +100,113 @@ entry: ;; Test the pass convergence and also that vzeroupper is only issued when necessary, ;; for this function it should be only once -; CHECK: _test03 -define <4 x float> @test03(<4 x float> %a, <4 x float> %b) nounwind uwtable ssp { +define <4 x float> @test03(<4 x float> %a, <4 x float> %b) nounwind { +; VZ-LABEL: test03: +; VZ: # BB#0: # %entry +; VZ-NEXT: pushq %rbx +; VZ-NEXT: subq $16, %rsp +; VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0 +; VZ-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill +; VZ-NEXT: .p2align 4, 0x90 +; VZ-NEXT: .LBB3_1: # %while.cond +; VZ-NEXT: # =>This Inner Loop Header: Depth=1 +; VZ-NEXT: callq foo +; VZ-NEXT: testl %eax, %eax +; VZ-NEXT: jne .LBB3_1 +; VZ-NEXT: # BB#2: # %for.body.preheader +; VZ-NEXT: movl $4, %ebx +; VZ-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload +; VZ-NEXT: .p2align 4, 0x90 +; VZ-NEXT: .LBB3_3: # %for.body +; VZ-NEXT: # =>This Inner Loop Header: Depth=1 +; VZ-NEXT: callq do_sse +; VZ-NEXT: callq do_sse +; VZ-NEXT: vmovaps {{.*}}(%rip), %ymm0 +; VZ-NEXT: vextractf128 $1, %ymm0, %xmm0 +; VZ-NEXT: vzeroupper +; VZ-NEXT: callq do_sse +; VZ-NEXT: decl %ebx +; VZ-NEXT: jne .LBB3_3 +; VZ-NEXT: # BB#4: # %for.end +; VZ-NEXT: addq $16, %rsp +; VZ-NEXT: popq %rbx +; VZ-NEXT: retq +; +; FAST-YMM-ZMM-LABEL: test03: +; FAST-YMM-ZMM: # BB#0: # %entry +; FAST-YMM-ZMM-NEXT: pushq %rbx +; FAST-YMM-ZMM-NEXT: subq $16, %rsp +; FAST-YMM-ZMM-NEXT: vaddps %xmm1, %xmm0, %xmm0 +; FAST-YMM-ZMM-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill +; FAST-YMM-ZMM-NEXT: .p2align 4, 0x90 +; FAST-YMM-ZMM-NEXT: .LBB3_1: # %while.cond +; FAST-YMM-ZMM-NEXT: # =>This Inner Loop Header: Depth=1 +; FAST-YMM-ZMM-NEXT: callq foo +; FAST-YMM-ZMM-NEXT: testl %eax, %eax +; FAST-YMM-ZMM-NEXT: jne .LBB3_1 +; FAST-YMM-ZMM-NEXT: # BB#2: # %for.body.preheader +; FAST-YMM-ZMM-NEXT: movl $4, %ebx +; FAST-YMM-ZMM-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload +; FAST-YMM-ZMM-NEXT: .p2align 4, 0x90 +; FAST-YMM-ZMM-NEXT: .LBB3_3: # %for.body +; FAST-YMM-ZMM-NEXT: # =>This Inner Loop Header: Depth=1 +; FAST-YMM-ZMM-NEXT: callq do_sse +; FAST-YMM-ZMM-NEXT: callq do_sse +; FAST-YMM-ZMM-NEXT: vmovaps {{.*}}(%rip), %ymm0 +; FAST-YMM-ZMM-NEXT: vextractf128 $1, %ymm0, %xmm0 +; FAST-YMM-ZMM-NEXT: callq do_sse +; FAST-YMM-ZMM-NEXT: decl %ebx +; FAST-YMM-ZMM-NEXT: jne .LBB3_3 +; FAST-YMM-ZMM-NEXT: # BB#4: # %for.end +; FAST-YMM-ZMM-NEXT: addq $16, %rsp +; FAST-YMM-ZMM-NEXT: popq %rbx +; FAST-YMM-ZMM-NEXT: retq +; +; BTVER2-LABEL: test03: +; BTVER2: # BB#0: # %entry +; BTVER2-NEXT: pushq %rbx +; BTVER2-NEXT: subq $16, %rsp +; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 +; BTVER2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill +; BTVER2-NEXT: .p2align 4, 0x90 +; BTVER2-NEXT: .LBB3_1: # %while.cond +; BTVER2-NEXT: # =>This Inner Loop Header: Depth=1 +; BTVER2-NEXT: callq foo +; BTVER2-NEXT: testl %eax, %eax +; BTVER2-NEXT: jne .LBB3_1 +; BTVER2-NEXT: # BB#2: # %for.body.preheader +; BTVER2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload +; BTVER2-NEXT: movl $4, %ebx +; BTVER2-NEXT: .p2align 4, 0x90 +; BTVER2-NEXT: .LBB3_3: # %for.body +; BTVER2-NEXT: # =>This Inner Loop Header: Depth=1 +; BTVER2-NEXT: callq do_sse +; BTVER2-NEXT: callq do_sse +; BTVER2-NEXT: vmovaps {{.*}}(%rip), %ymm0 +; BTVER2-NEXT: vextractf128 $1, %ymm0, %xmm0 +; BTVER2-NEXT: callq do_sse +; BTVER2-NEXT: decl %ebx +; BTVER2-NEXT: jne .LBB3_3 +; BTVER2-NEXT: # BB#4: # %for.end +; BTVER2-NEXT: addq $16, %rsp +; BTVER2-NEXT: popq %rbx +; BTVER2-NEXT: retq entry: %add.i = fadd <4 x float> %a, %b br label %while.cond -while.cond: +while.cond: %call = tail call i32 @foo() %tobool = icmp eq i32 %call, 0 br i1 %tobool, label %for.body, label %while.cond for.body: - ; CHECK: LBB - ; CHECK-NOT: vzeroupper %i.018 = phi i32 [ 0, %while.cond ], [ %1, %for.body ] %c.017 = phi <4 x float> [ %add.i, %while.cond ], [ %call14, %for.body ] - ; CHECK: callq _do_sse %call5 = tail call <4 x float> @do_sse(<4 x float> %c.017) nounwind - ; CHECK-NEXT: callq _do_sse %call7 = tail call <4 x float> @do_sse(<4 x float> %call5) nounwind %tmp11 = load <8 x float>, <8 x float>* @g, align 32 %0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %tmp11, i8 1) nounwind - ; CHECK: vzeroupper - ; CHECK-NEXT: callq _do_sse %call14 = tail call <4 x float> @do_sse(<4 x float> %0) nounwind %1 = add nsw i32 %i.018, 1 %exitcond = icmp eq i32 %1, 4 @@ -94,15 +218,30 @@ for.end: ;; Check that we also perform vzeroupper when we return from a function. -; CHECK: _test04 -define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind uwtable ssp { -entry: +define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind { +; VZ-LABEL: test04: +; VZ: # BB#0: +; VZ-NEXT: pushq %rax +; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; VZ-NEXT: callq do_avx +; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; VZ-NEXT: popq %rax +; VZ-NEXT: vzeroupper +; VZ-NEXT: retq +; +; NO-VZ-LABEL: test04: +; NO-VZ: # BB#0: +; NO-VZ-NEXT: pushq %rax +; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; NO-VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; NO-VZ-NEXT: callq do_avx +; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; NO-VZ-NEXT: popq %rax +; NO-VZ-NEXT: retq %shuf = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> - ; CHECK-NOT: vzeroupper - ; CHECK: call %call = call <8 x float> @do_avx(<8 x float> %shuf) nounwind %shuf2 = shufflevector <8 x float> %call, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> - ; CHECK: vzeroupper - ; CHECK: ret ret <4 x float> %shuf2 } + diff --git a/test/CodeGen/X86/avx512bw-intrinsics.ll b/test/CodeGen/X86/avx512bw-intrinsics.ll index 3337f42eb142..51f9a382ccbf 100644 --- a/test/CodeGen/X86/avx512bw-intrinsics.ll +++ b/test/CodeGen/X86/avx512bw-intrinsics.ll @@ -2216,9 +2216,9 @@ define i32@test_int_x86_avx512_kunpck_wd(i32 %x0, i32 %x1) { ; ; AVX512F-32-LABEL: test_int_x86_avx512_kunpck_wd: ; AVX512F-32: # BB#0: -; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k0 -; AVX512F-32-NEXT: kmovd {{[0-9]+}}(%esp), %k1 -; AVX512F-32-NEXT: kunpckwd %k1, %k0, %k0 +; AVX512F-32-NEXT: kmovw {{[0-9]+}}(%esp), %k0 +; AVX512F-32-NEXT: kmovw {{[0-9]+}}(%esp), %k1 +; AVX512F-32-NEXT: kunpckwd %k0, %k1, %k0 ; AVX512F-32-NEXT: kmovd %k0, %eax ; AVX512F-32-NEXT: retl %res = call i32 @llvm.x86.avx512.kunpck.wd(i32 %x0, i32 %x1) diff --git a/test/CodeGen/X86/avx512vpopcntdq-intrinsics.ll b/test/CodeGen/X86/avx512vpopcntdq-intrinsics.ll new file mode 100644 index 000000000000..019c5282f63b --- /dev/null +++ b/test/CodeGen/X86/avx512vpopcntdq-intrinsics.ll @@ -0,0 +1,88 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vpopcntdq --show-mc-encoding | FileCheck %s --check-prefix=X86_64 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vpopcntdq --show-mc-encoding | FileCheck %s --check-prefix=X86 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; The following tests check that patterns that includes ;; +;; ctpop intrinsic + select are translated to the vpopcntd/q ;; +;; instruction in a correct way. ;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +define <16 x i32> @test_mask_vpopcnt_d(<16 x i32> %a, i16 %mask, <16 x i32> %b) { +; X86_64-LABEL: test_mask_vpopcnt_d: +; X86_64: # BB#0: +; X86_64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf] +; X86_64-NEXT: vpopcntd %zmm1, %zmm0 {%k1} # encoding: [0x62,0xf2,0x7d,0x49,0x55,0xc1] +; X86_64-NEXT: retq # encoding: [0xc3] +; +; X86-LABEL: test_mask_vpopcnt_d: +; X86: # BB#0: +; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04] +; X86-NEXT: vpopcntd %zmm1, %zmm0 {%k1} # encoding: [0x62,0xf2,0x7d,0x49,0x55,0xc1] +; X86-NEXT: retl # encoding: [0xc3] + %1 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %b) + %2 = bitcast i16 %mask to <16 x i1> + %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %a + ret <16 x i32> %3 +} + +define <16 x i32> @test_maskz_vpopcnt_d(i16 %mask, <16 x i32> %a) { +; X86_64-LABEL: test_maskz_vpopcnt_d: +; X86_64: # BB#0: +; X86_64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf] +; X86_64-NEXT: vpopcntd %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7d,0xc9,0x55,0xc0] +; X86_64-NEXT: retq # encoding: [0xc3] +; +; X86-LABEL: test_maskz_vpopcnt_d: +; X86: # BB#0: +; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04] +; X86-NEXT: vpopcntd %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7d,0xc9,0x55,0xc0] +; X86-NEXT: retl # encoding: [0xc3] + %1 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %a) + %2 = bitcast i16 %mask to <16 x i1> + %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> zeroinitializer + ret <16 x i32> %3 +} + +define <8 x i64> @test_mask_vpopcnt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) { +; X86_64-LABEL: test_mask_vpopcnt_q: +; X86_64: # BB#0: +; X86_64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf] +; X86_64-NEXT: vpopcntq %zmm0, %zmm1 {%k1} # encoding: [0x62,0xf2,0xfd,0x49,0x55,0xc8] +; X86_64-NEXT: vmovdqa64 %zmm1, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc1] +; X86_64-NEXT: retq # encoding: [0xc3] +; +; X86-LABEL: test_mask_vpopcnt_q: +; X86: # BB#0: +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04] +; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8] +; X86-NEXT: vpopcntq %zmm0, %zmm1 {%k1} # encoding: [0x62,0xf2,0xfd,0x49,0x55,0xc8] +; X86-NEXT: vmovdqa64 %zmm1, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc1] +; X86-NEXT: retl # encoding: [0xc3] + %1 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %a) + %2 = bitcast i8 %mask to <8 x i1> + %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> %b + ret <8 x i64> %3 +} + +define <8 x i64> @test_maskz_vpopcnt_q(<8 x i64> %a, i8 %mask) { +; X86_64-LABEL: test_maskz_vpopcnt_q: +; X86_64: # BB#0: +; X86_64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf] +; X86_64-NEXT: vpopcntq %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0xc9,0x55,0xc0] +; X86_64-NEXT: retq # encoding: [0xc3] +; +; X86-LABEL: test_maskz_vpopcnt_q: +; X86: # BB#0: +; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04] +; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8] +; X86-NEXT: vpopcntq %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0xc9,0x55,0xc0] +; X86-NEXT: retl # encoding: [0xc3] + %1 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %a) + %2 = bitcast i8 %mask to <8 x i1> + %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> zeroinitializer + ret <8 x i64> %3 +} + +declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) +declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) diff --git a/test/CodeGen/X86/fast-isel-select-cmp.ll b/test/CodeGen/X86/fast-isel-select-cmp.ll index 1af30e9f32fe..4a8e8792f98d 100644 --- a/test/CodeGen/X86/fast-isel-select-cmp.ll +++ b/test/CodeGen/X86/fast-isel-select-cmp.ll @@ -4,9 +4,9 @@ ; different basic blocks. define i32 @select_cmp_cmov_i32(i32 %a, i32 %b) { -; CHECK-LABEL: select_cmp_cmov_i32 +; CHECK-LABEL: select_cmp_cmov_i32: ; CHECK-LABEL: continue -; CHECK-NOT: cmp +; CHECK-NOT: cmp{{[^_]}} %1 = icmp ult i32 %a, %b br i1 %1, label %continue, label %exit @@ -19,9 +19,9 @@ exit: } define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) { -; CHECK-LABEL: select_fcmp_oeq_f32 +; CHECK-LABEL: select_fcmp_oeq_f32: ; CHECK-LABEL: continue -; CHECK-NOT: cmp +; CHECK-NOT: cmp{{[^_]}} %1 = fcmp oeq float %a, %b br i1 %1, label %continue, label %exit @@ -34,7 +34,7 @@ exit: } define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) { -; CHECK-LABEL: select_fcmp_one_f32 +; CHECK-LABEL: select_fcmp_one_f32: ; CHECK-LABEL: continue ; CHECK-NOT: ucomi %1 = fcmp one float %a, %b diff --git a/test/CodeGen/X86/fp-intrinsics.ll b/test/CodeGen/X86/fp-intrinsics.ll index 88aef6bb0659..0f8d730d7535 100644 --- a/test/CodeGen/X86/fp-intrinsics.ll +++ b/test/CodeGen/X86/fp-intrinsics.ll @@ -103,9 +103,156 @@ if.end: ret double %a.0 } +; Verify that sqrt(42.0) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f5 +; CHECK: sqrtsd +define double @f5() { +entry: + %result = call double @llvm.experimental.constrained.sqrt.f64(double 42.0, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that pow(42.1, 3.0) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f6 +; CHECK: pow +define double @f6() { +entry: + %result = call double @llvm.experimental.constrained.pow.f64(double 42.1, + double 3.0, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that powi(42.1, 3) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f7 +; CHECK: powi +define double @f7() { +entry: + %result = call double @llvm.experimental.constrained.powi.f64(double 42.1, + i32 3, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that sin(42.0) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f8 +; CHECK: sin +define double @f8() { +entry: + %result = call double @llvm.experimental.constrained.sin.f64(double 42.0, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that cos(42.0) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f9 +; CHECK: cos +define double @f9() { +entry: + %result = call double @llvm.experimental.constrained.cos.f64(double 42.0, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that exp(42.0) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f10 +; CHECK: exp +define double @f10() { +entry: + %result = call double @llvm.experimental.constrained.exp.f64(double 42.0, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that exp2(42.1) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f11 +; CHECK: exp2 +define double @f11() { +entry: + %result = call double @llvm.experimental.constrained.exp2.f64(double 42.1, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that log(42.0) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f12 +; CHECK: log +define double @f12() { +entry: + %result = call double @llvm.experimental.constrained.log.f64(double 42.0, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that log10(42.0) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f13 +; CHECK: log10 +define double @f13() { +entry: + %result = call double @llvm.experimental.constrained.log10.f64(double 42.0, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that log2(42.0) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f14 +; CHECK: log2 +define double @f14() { +entry: + %result = call double @llvm.experimental.constrained.log2.f64(double 42.0, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that rint(42.1) isn't simplified when the rounding mode is unknown. +; CHECK-LABEL: f15 +; CHECK: rint +define double @f15() { +entry: + %result = call double @llvm.experimental.constrained.rint.f64(double 42.1, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} + +; Verify that nearbyint(42.1) isn't simplified when the rounding mode is +; unknown. +; CHECK-LABEL: f16 +; CHECK: nearbyint +define double @f16() { +entry: + %result = call double @llvm.experimental.constrained.nearbyint.f64( + double 42.1, + metadata !"round.dynamic", + metadata !"fpexcept.strict") + ret double %result +} @llvm.fp.env = thread_local global i8 zeroinitializer, section "llvm.metadata" declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata) declare double @llvm.experimental.constrained.fmul.f64(double, double, metadata, metadata) declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata) declare double @llvm.experimental.constrained.fsub.f64(double, double, metadata, metadata) +declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.pow.f64(double, double, metadata, metadata) +declare double @llvm.experimental.constrained.powi.f64(double, i32, metadata, metadata) +declare double @llvm.experimental.constrained.sin.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.cos.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.exp.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.exp2.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.log.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.log10.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.log2.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.rint.f64(double, metadata, metadata) +declare double @llvm.experimental.constrained.nearbyint.f64(double, metadata, metadata) diff --git a/test/CodeGen/X86/hoist-invariant-load.ll b/test/CodeGen/X86/hoist-invariant-load.ll index 5ade5b470b54..e7929c9cecdc 100644 --- a/test/CodeGen/X86/hoist-invariant-load.ll +++ b/test/CodeGen/X86/hoist-invariant-load.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -mcpu=haswell < %s -stats -O2 2>&1 | grep "4 machine-licm.*hoisted" +; RUN: llc -mcpu=haswell < %s -stats -O2 2>&1 | grep "4 machinelicm.*hoisted" ; For test: ; 2 invariant loads, 1 for OBJC_SELECTOR_REFERENCES_ ; and 1 for objc_msgSend from the GOT diff --git a/test/CodeGen/X86/misched-copy.ll b/test/CodeGen/X86/misched-copy.ll index 3e3729285d27..7abd157f147a 100644 --- a/test/CodeGen/X86/misched-copy.ll +++ b/test/CodeGen/X86/misched-copy.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -verify-machineinstrs -march=x86 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -march=x86 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s ; ; Test scheduling of copy instructions. ; diff --git a/test/CodeGen/X86/or-branch.ll b/test/CodeGen/X86/or-branch.ll index 4899a0fc7e88..71d7746642e9 100644 --- a/test/CodeGen/X86/or-branch.ll +++ b/test/CodeGen/X86/or-branch.ll @@ -1,16 +1,34 @@ -; RUN: llc < %s -mtriple=i386-unknown-unknown -jump-is-expensive=0 | FileCheck %s --check-prefix=JUMP2 --check-prefix=CHECK -; RUN: llc < %s -mtriple=i386-unknown-unknown -jump-is-expensive=1 | FileCheck %s --check-prefix=JUMP1 --check-prefix=CHECK +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i386-unknown-unknown -jump-is-expensive=0 | FileCheck %s --check-prefix=JUMP2 +; RUN: llc < %s -mtriple=i386-unknown-unknown -jump-is-expensive=1 | FileCheck %s --check-prefix=JUMP1 define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind { ; JUMP2-LABEL: foo: -; JUMP2-DAG: jl -; JUMP2-DAG: je +; JUMP2: # BB#0: # %entry +; JUMP2-NEXT: cmpl $5, {{[0-9]+}}(%esp) +; JUMP2-NEXT: jl .LBB0_3 +; JUMP2-NEXT: # BB#1: # %entry +; JUMP2-NEXT: movl {{[0-9]+}}(%esp), %eax +; JUMP2-NEXT: testl %eax, %eax +; JUMP2-NEXT: je .LBB0_3 +; JUMP2-NEXT: # BB#2: # %UnifiedReturnBlock +; JUMP2-NEXT: retl +; JUMP2-NEXT: .LBB0_3: # %cond_true +; JUMP2-NEXT: jmp bar # TAILCALL ; ; JUMP1-LABEL: foo: -; JUMP1-DAG: sete -; JUMP1-DAG: setl -; JUMP1: orb -; JUMP1: jne +; JUMP1: # BB#0: # %entry +; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp) +; JUMP1-NEXT: sete %al +; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp) +; JUMP1-NEXT: setl %cl +; JUMP1-NEXT: orb %al, %cl +; JUMP1-NEXT: cmpb $1, %cl +; JUMP1-NEXT: jne .LBB0_1 +; JUMP1-NEXT: # BB#2: # %cond_true +; JUMP1-NEXT: jmp bar # TAILCALL +; JUMP1-NEXT: .LBB0_1: # %UnifiedReturnBlock +; JUMP1-NEXT: retl entry: %tmp1 = icmp eq i32 %X, 0 %tmp3 = icmp slt i32 %Y, 5 @@ -29,11 +47,33 @@ UnifiedReturnBlock: ; regardless of whether they are expensive or not. define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind { -; CHECK-LABEL: unpredictable: -; CHECK-DAG: sete -; CHECK-DAG: setl -; CHECK: orb -; CHECK: jne +; JUMP2-LABEL: unpredictable: +; JUMP2: # BB#0: # %entry +; JUMP2-NEXT: cmpl $0, {{[0-9]+}}(%esp) +; JUMP2-NEXT: sete %al +; JUMP2-NEXT: cmpl $5, {{[0-9]+}}(%esp) +; JUMP2-NEXT: setl %cl +; JUMP2-NEXT: orb %al, %cl +; JUMP2-NEXT: cmpb $1, %cl +; JUMP2-NEXT: jne .LBB1_1 +; JUMP2-NEXT: # BB#2: # %cond_true +; JUMP2-NEXT: jmp bar # TAILCALL +; JUMP2-NEXT: .LBB1_1: # %UnifiedReturnBlock +; JUMP2-NEXT: retl +; +; JUMP1-LABEL: unpredictable: +; JUMP1: # BB#0: # %entry +; JUMP1-NEXT: cmpl $0, {{[0-9]+}}(%esp) +; JUMP1-NEXT: sete %al +; JUMP1-NEXT: cmpl $5, {{[0-9]+}}(%esp) +; JUMP1-NEXT: setl %cl +; JUMP1-NEXT: orb %al, %cl +; JUMP1-NEXT: cmpb $1, %cl +; JUMP1-NEXT: jne .LBB1_1 +; JUMP1-NEXT: # BB#2: # %cond_true +; JUMP1-NEXT: jmp bar # TAILCALL +; JUMP1-NEXT: .LBB1_1: # %UnifiedReturnBlock +; JUMP1-NEXT: retl entry: %tmp1 = icmp eq i32 %X, 0 %tmp3 = icmp slt i32 %Y, 5 diff --git a/test/CodeGen/X86/pr27681.mir b/test/CodeGen/X86/pr27681.mir index 002761bc1e68..956df172b253 100644 --- a/test/CodeGen/X86/pr27681.mir +++ b/test/CodeGen/X86/pr27681.mir @@ -57,7 +57,7 @@ body: | %cl = SETNEr implicit %eflags ; Verify that removal of the %bl antidependence does not use %ch ; as a replacement register. - ; CHECK: %cl = AND8rr %cl, killed %b + ; CHECK: %cl = AND8rr killed %cl, killed %b %cl = AND8rr killed %cl, killed %bl, implicit-def dead %eflags CMP32ri8 %ebp, -1, implicit-def %eflags %edx = MOV32ri 0 diff --git a/test/CodeGen/X86/sandybridge-loads.ll b/test/CodeGen/X86/sandybridge-loads.ll index 2e31154068fc..8570fe7fe7ba 100644 --- a/test/CodeGen/X86/sandybridge-loads.ll +++ b/test/CodeGen/X86/sandybridge-loads.ll @@ -1,13 +1,20 @@ -; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s - -;CHECK-LABEL: wideloads: -;CHECK: vmovaps -;CHECK: vinsertf128 -;CHECK: vmovaps -;CHECK-NOT: vinsertf128 -;CHECK: ret +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp { +; CHECK-LABEL: wideloads: +; CHECK: # BB#0: +; CHECK-NEXT: vmovaps (%rdi), %xmm0 +; CHECK-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 +; CHECK-NEXT: vmovaps (%rsi), %ymm1 +; CHECK-NEXT: vcmpltps %ymm0, %ymm1, %ymm1 +; CHECK-NEXT: vmovaps (%rdx), %ymm2 +; CHECK-NEXT: vcmpltps %ymm0, %ymm2, %ymm0 +; CHECK-NEXT: vandps %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 +; CHECK-NEXT: vmovaps %ymm0, (%rax) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq %v0 = load <8 x float>, <8 x float>* %a, align 16 ; <---- unaligned! %v1 = load <8 x float>, <8 x float>* %b, align 32 ; <---- aligned! %m0 = fcmp olt <8 x float> %v1, %v0 @@ -19,17 +26,16 @@ define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwi ret void } -; CHECK: widestores -; loads: -; CHECK: vmovaps -; CHECK: vmovaps -; stores: -; CHECK: vmovaps -; CHECK: vextractf128 -; CHECK: vmovaps -;CHECK: ret - define void @widestores(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp { +; CHECK-LABEL: widestores: +; CHECK: # BB#0: +; CHECK-NEXT: vmovaps (%rdi), %ymm0 +; CHECK-NEXT: vmovaps (%rsi), %ymm1 +; CHECK-NEXT: vmovaps %ymm0, (%rsi) +; CHECK-NEXT: vextractf128 $1, %ymm1, 16(%rdi) +; CHECK-NEXT: vmovaps %xmm1, (%rdi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq %v0 = load <8 x float>, <8 x float>* %a, align 32 %v1 = load <8 x float>, <8 x float>* %b, align 32 store <8 x float> %v0, <8 x float>* %b, align 32 ; <--- aligned diff --git a/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll b/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll index 383ab21bd404..19305d0dad62 100644 --- a/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll @@ -354,9 +354,8 @@ declare i32 @llvm.x86.sse42.pcmpistriz128(<16 x i8>, <16 x i8>, i8) nounwind rea define i32 @test_mm_crc32_u8(i32 %a0, i8 %a1) { ; X32-LABEL: test_mm_crc32_u8: ; X32: # BB#0: -; X32-NEXT: movb {{[0-9]+}}(%esp), %cl ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: crc32b %cl, %eax +; X32-NEXT: crc32b {{[0-9]+}}(%esp), %eax ; X32-NEXT: retl ; ; X64-LABEL: test_mm_crc32_u8: @@ -372,9 +371,8 @@ declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind readnone define i32 @test_mm_crc32_u16(i32 %a0, i16 %a1) { ; X32-LABEL: test_mm_crc32_u16: ; X32: # BB#0: -; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-NEXT: crc32w %cx, %eax +; X32-NEXT: crc32w {{[0-9]+}}(%esp), %eax ; X32-NEXT: retl ; ; X64-LABEL: test_mm_crc32_u16: diff --git a/test/CodeGen/X86/stack-folding-fp-avx1.ll b/test/CodeGen/X86/stack-folding-fp-avx1.ll index 72542f499087..a00d47bb13e9 100644 --- a/test/CodeGen/X86/stack-folding-fp-avx1.ll +++ b/test/CodeGen/X86/stack-folding-fp-avx1.ll @@ -1651,26 +1651,9 @@ define <8 x float> @stack_fold_sqrtps_ymm(<8 x float> %a0) { } declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone -define double @stack_fold_sqrtsd(double %a0) { - ;CHECK-LABEL: stack_fold_sqrtsd - ;CHECK: vsqrtsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload - %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"() - %2 = call double @llvm.sqrt.f64(double %a0) - ret double %2 -} -declare double @llvm.sqrt.f64(double) nounwind readnone - +; TODO stack_fold_sqrtsd ; TODO stack_fold_sqrtsd_int - -define float @stack_fold_sqrtss(float %a0) { - ;CHECK-LABEL: stack_fold_sqrtss - ;CHECK: vsqrtss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload - %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"() - %2 = call float @llvm.sqrt.f32(float %a0) - ret float %2 -} -declare float @llvm.sqrt.f32(float) nounwind readnone - +; TODO stack_fold_sqrtss ; TODO stack_fold_sqrtss_int define <2 x double> @stack_fold_subpd(<2 x double> %a0, <2 x double> %a1) { diff --git a/test/CodeGen/X86/twoaddr-coalesce-2.ll b/test/CodeGen/X86/twoaddr-coalesce-2.ll index cbcde0655597..9da071f7ede6 100644 --- a/test/CodeGen/X86/twoaddr-coalesce-2.ll +++ b/test/CodeGen/X86/twoaddr-coalesce-2.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -stats 2>&1 | \ -; RUN: grep "twoaddrinstr" | grep "Number of instructions aggressively commuted" +; RUN: grep "twoaddressinstruction" | grep "Number of instructions aggressively commuted" ; rdar://6480363 target triple = "i386-apple-darwin9.6" diff --git a/test/CodeGen/X86/vector-narrow-binop.ll b/test/CodeGen/X86/vector-narrow-binop.ll index f737ea2b7fba..4d183f3172b3 100644 --- a/test/CodeGen/X86/vector-narrow-binop.ll +++ b/test/CodeGen/X86/vector-narrow-binop.ll @@ -22,17 +22,17 @@ define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d ; ; AVX1-LABEL: PR32790: ; AVX1: # BB#0: -; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5 -; AVX1-NEXT: vpaddd %xmm4, %xmm5, %xmm4 +; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm4 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 -; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 -; AVX1-NEXT: vpsubd %xmm2, %xmm1, %xmm1 -; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm1 +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm1 +; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm1 +; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: PR32790: @@ -60,46 +60,17 @@ define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d define <4 x i32> @do_not_use_256bit_op(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { ; SSE-LABEL: do_not_use_256bit_op: ; SSE: # BB#0: -; SSE-NEXT: pand %xmm3, %xmm1 ; SSE-NEXT: pand %xmm2, %xmm0 +; SSE-NEXT: pand %xmm3, %xmm1 ; SSE-NEXT: psubd %xmm1, %xmm0 ; SSE-NEXT: retq ; -; AVX1-LABEL: do_not_use_256bit_op: -; AVX1: # BB#0: -; AVX1-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 -; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1 -; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: do_not_use_256bit_op: -; AVX2: # BB#0: -; AVX2-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> -; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 -; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm1 -; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 -; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -; -; AVX512-LABEL: do_not_use_256bit_op: -; AVX512: # BB#0: -; AVX512-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> -; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 -; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm1 -; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpsubd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vzeroupper -; AVX512-NEXT: retq +; AVX-LABEL: do_not_use_256bit_op: +; AVX: # BB#0: +; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX-NEXT: vpand %xmm3, %xmm1, %xmm1 +; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq %concat1 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %concat2 = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %and = and <8 x i32> %concat1, %concat2 diff --git a/test/CodeGen/X86/vector-popcnt-128.ll b/test/CodeGen/X86/vector-popcnt-128.ll index 27909c6bb4a0..adda108bdc77 100644 --- a/test/CodeGen/X86/vector-popcnt-128.ll +++ b/test/CodeGen/X86/vector-popcnt-128.ll @@ -5,6 +5,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vpopcntdq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512VPOPCNTDQ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind { ; SSE2-LABEL: testv2i64: @@ -81,19 +82,41 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind { ; SSE41-NEXT: psadbw %xmm3, %xmm0 ; SSE41-NEXT: retq ; -; AVX-LABEL: testv2i64: -; AVX: # BB#0: -; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2 -; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX-NEXT: vpshufb %xmm2, %xmm3, %xmm2 -; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 -; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpshufb %xmm0, %xmm3, %xmm0 -; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 -; AVX-NEXT: retq +; AVX1-LABEL: testv2i64: +; AVX1: # BB#0: +; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX1-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: testv2i64: +; AVX2: # BB#0: +; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX2-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX2-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv2i64: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: vzeroupper +; AVX512VPOPCNTDQ-NEXT: retq %out = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %in) ret <2 x i64> %out } @@ -193,23 +216,49 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind { ; SSE41-NEXT: packuswb %xmm3, %xmm0 ; SSE41-NEXT: retq ; -; AVX-LABEL: testv4i32: -; AVX: # BB#0: -; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2 -; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX-NEXT: vpshufb %xmm2, %xmm3, %xmm2 -; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 -; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpshufb %xmm0, %xmm3, %xmm0 -; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0 -; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] -; AVX-NEXT: vpsadbw %xmm1, %xmm2, %xmm2 -; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero -; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 -; AVX-NEXT: retq +; AVX1-LABEL: testv4i32: +; AVX1: # BB#0: +; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX1-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; AVX1-NEXT: vpsadbw %xmm1, %xmm2, %xmm2 +; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero +; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: testv4i32: +; AVX2: # BB#0: +; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX2-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX2-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; AVX2-NEXT: vpsadbw %xmm1, %xmm2, %xmm2 +; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero +; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv4i32: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: vzeroupper +; AVX512VPOPCNTDQ-NEXT: retq %out = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %in) ret <4 x i32> %out } diff --git a/test/CodeGen/X86/vector-popcnt-256.ll b/test/CodeGen/X86/vector-popcnt-256.ll index 7a675619d720..accbad35e9d7 100644 --- a/test/CodeGen/X86/vector-popcnt-256.ll +++ b/test/CodeGen/X86/vector-popcnt-256.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vpopcntdq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512VPOPCNTDQ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX1-LABEL: testv4i64: @@ -39,6 +40,13 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv4i64: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: retq %out = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %in) ret <4 x i64> %out } @@ -92,6 +100,13 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv8i32: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: retq %out = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> %in) ret <8 x i32> %out } @@ -137,6 +152,21 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { ; AVX2-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX2-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv16i16: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm0, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm0, %ymm1, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %in) ret <16 x i16> %out } @@ -173,6 +203,18 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; AVX2-NEXT: vpshufb %ymm0, %ymm3, %ymm0 ; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv32i8: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <32 x i8> @llvm.ctpop.v32i8(<32 x i8> %in) ret <32 x i8> %out } diff --git a/test/CodeGen/X86/vector-popcnt-512.ll b/test/CodeGen/X86/vector-popcnt-512.ll index cf4f21e62b61..aa50206e7a5e 100644 --- a/test/CodeGen/X86/vector-popcnt-512.ll +++ b/test/CodeGen/X86/vector-popcnt-512.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512F ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512vpopcntdq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512VPOPCNTDQ define <8 x i64> @testv8i64(<8 x i64> %in) nounwind { ; AVX512F-LABEL: testv8i64: @@ -39,6 +40,11 @@ define <8 x i64> @testv8i64(<8 x i64> %in) nounwind { ; AVX512BW-NEXT: vpxord %zmm1, %zmm1, %zmm1 ; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv8i64: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %in) ret <8 x i64> %out } @@ -92,6 +98,11 @@ define <16 x i32> @testv16i32(<16 x i32> %in) nounwind { ; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv16i32: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %in) ret <16 x i32> %out } @@ -135,6 +146,30 @@ define <32 x i16> @testv32i16(<32 x i16> %in) nounwind { ; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0 ; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv32i16: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm0, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm0, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm0, %ymm3, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm1, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %in) ret <32 x i16> %out } @@ -169,6 +204,24 @@ define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { ; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv64i8: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm0, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm4, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm3, %ymm4, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm1, %ymm4, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm3, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %in) ret <64 x i8> %out } diff --git a/test/CodeGen/X86/vector-shuffle-512-v16.ll b/test/CodeGen/X86/vector-shuffle-512-v16.ll index fa3471c2fe40..2e65bd8c75c7 100644 --- a/test/CodeGen/X86/vector-shuffle-512-v16.ll +++ b/test/CodeGen/X86/vector-shuffle-512-v16.ll @@ -282,8 +282,7 @@ define <16 x i32> @shuffle_v16i32_0_1_2_19_u_u_u_u_u_u_u_u_u_u_u_u(<16 x i32> %a define <8 x float> @shuffle_v16f32_extract_256(float* %RET, float* %a) { ; ALL-LABEL: shuffle_v16f32_extract_256: ; ALL: # BB#0: -; ALL-NEXT: vmovups (%rsi), %zmm0 -; ALL-NEXT: vextractf32x8 $1, %zmm0, %ymm0 +; ALL-NEXT: vmovups 32(%rsi), %ymm0 ; ALL-NEXT: retq %ptr_a = bitcast float* %a to <16 x float>* %v_a = load <16 x float>, <16 x float>* %ptr_a, align 4 diff --git a/test/CodeGen/X86/vector-shuffle-avx512.ll b/test/CodeGen/X86/vector-shuffle-avx512.ll index 5aab21749d14..706edd27a3f1 100644 --- a/test/CodeGen/X86/vector-shuffle-avx512.ll +++ b/test/CodeGen/X86/vector-shuffle-avx512.ll @@ -511,11 +511,10 @@ define <8 x float> @expand14(<4 x float> %a) { ; ; KNL64-LABEL: expand14: ; KNL64: # BB#0: +; KNL64-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,3,0,0] +; KNL64-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1] ; KNL64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3] ; KNL64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3] -; KNL64-NEXT: vmovaps {{.*#+}} ymm1 = <0,2,4,0,u,u,u,u> -; KNL64-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,3,0,0] -; KNL64-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1] ; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3],ymm0[4],ymm1[5,6,7] ; KNL64-NEXT: retq ; @@ -529,11 +528,10 @@ define <8 x float> @expand14(<4 x float> %a) { ; ; KNL32-LABEL: expand14: ; KNL32: # BB#0: +; KNL32-NEXT: vpermilps {{.*#+}} xmm1 = mem[3,3,0,0] +; KNL32-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1] ; KNL32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3] ; KNL32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3] -; KNL32-NEXT: vmovaps {{.*#+}} ymm1 = <0,2,4,0,u,u,u,u> -; KNL32-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,3,0,0] -; KNL32-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1] ; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3],ymm0[4],ymm1[5,6,7] ; KNL32-NEXT: retl %addV = fadd <4 x float> <float 0.0,float 1.0,float 2.0,float 0.0> , <float 0.0,float 1.0,float 2.0,float 0.0> @@ -545,39 +543,35 @@ define <8 x float> @expand14(<4 x float> %a) { define <8 x float> @expand15(<4 x float> %a) { ; SKX64-LABEL: expand15: ; SKX64: # BB#0: -; SKX64-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,1,1,3] -; SKX64-NEXT: vmovaps {{.*#+}} ymm0 = <0,2,4,0,u,u,u,u> -; SKX64-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[0,1,0,0] +; SKX64-NEXT: vpermilps {{.*#+}} xmm1 = mem[0,1,0,0] +; SKX64-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[0,1,1,3] ; SKX64-NEXT: vmovaps {{.*#+}} ymm0 = [0,1,8,3,10,3,2,3] -; SKX64-NEXT: vpermi2ps %ymm1, %ymm2, %ymm0 +; SKX64-NEXT: vpermi2ps %ymm2, %ymm1, %ymm0 ; SKX64-NEXT: retq ; ; KNL64-LABEL: expand15: ; KNL64: # BB#0: +; KNL64-NEXT: vpermilps {{.*#+}} xmm1 = mem[0,1,0,0] +; KNL64-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1] ; KNL64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3] ; KNL64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3] -; KNL64-NEXT: vmovaps {{.*#+}} ymm1 = <0,2,4,0,u,u,u,u> -; KNL64-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,1,0,0] -; KNL64-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1] ; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3],ymm0[4],ymm1[5,6,7] ; KNL64-NEXT: retq ; ; SKX32-LABEL: expand15: ; SKX32: # BB#0: -; SKX32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[0,1,1,3] -; SKX32-NEXT: vmovaps {{.*#+}} ymm0 = <0,2,4,0,u,u,u,u> -; SKX32-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[0,1,0,0] +; SKX32-NEXT: vpermilps {{.*#+}} xmm1 = mem[0,1,0,0] +; SKX32-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[0,1,1,3] ; SKX32-NEXT: vmovaps {{.*#+}} ymm0 = [0,1,8,3,10,3,2,3] -; SKX32-NEXT: vpermi2ps %ymm1, %ymm2, %ymm0 +; SKX32-NEXT: vpermi2ps %ymm2, %ymm1, %ymm0 ; SKX32-NEXT: retl ; ; KNL32-LABEL: expand15: ; KNL32: # BB#0: +; KNL32-NEXT: vpermilps {{.*#+}} xmm1 = mem[0,1,0,0] +; KNL32-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1] ; KNL32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,3] ; KNL32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,3] -; KNL32-NEXT: vmovaps {{.*#+}} ymm1 = <0,2,4,0,u,u,u,u> -; KNL32-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,1,0,0] -; KNL32-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,1,1,1] ; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3],ymm0[4],ymm1[5,6,7] ; KNL32-NEXT: retl %addV = fadd <4 x float> <float 0.0,float 1.0,float 2.0,float 0.0> , <float 0.0,float 1.0,float 2.0,float 0.0> diff --git a/test/CodeGen/X86/vector-sqrt.ll b/test/CodeGen/X86/vector-sqrt.ll index c5ac4466b5fa..13088b7fa5f2 100644 --- a/test/CodeGen/X86/vector-sqrt.ll +++ b/test/CodeGen/X86/vector-sqrt.ll @@ -5,8 +5,10 @@ define <2 x double> @sqrtd2(double* nocapture readonly %v) local_unnamed_addr #0 { ; CHECK-LABEL: sqrtd2: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: vsqrtsd (%rdi), %xmm0, %xmm0 -; CHECK-NEXT: vsqrtsd 8(%rdi), %xmm1, %xmm1 +; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero +; CHECK-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 ; CHECK-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; CHECK-NEXT: retq entry: @@ -27,10 +29,14 @@ declare double @sqrt(double) local_unnamed_addr #1 define <4 x float> @sqrtf4(float* nocapture readonly %v) local_unnamed_addr #0 { ; CHECK-LABEL: sqrtf4: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: vsqrtss (%rdi), %xmm0, %xmm0 -; CHECK-NEXT: vsqrtss 4(%rdi), %xmm1, %xmm1 -; CHECK-NEXT: vsqrtss 8(%rdi), %xmm2, %xmm2 -; CHECK-NEXT: vsqrtss 12(%rdi), %xmm3, %xmm3 +; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 +; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero +; CHECK-NEXT: vsqrtss %xmm2, %xmm2, %xmm2 +; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero +; CHECK-NEXT: vsqrtss %xmm3, %xmm3, %xmm3 ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] diff --git a/test/CodeGen/X86/vector-trunc-math.ll b/test/CodeGen/X86/vector-trunc-math.ll index a5fac9ac6a41..d4fbb72bbe6d 100644 --- a/test/CodeGen/X86/vector-trunc-math.ll +++ b/test/CodeGen/X86/vector-trunc-math.ll @@ -3030,10 +3030,10 @@ define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_and_v8i32_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pand %xmm2, %xmm0 ; SSE-NEXT: pand %xmm3, %xmm1 ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 +; SSE-NEXT: pand %xmm2, %xmm0 ; SSE-NEXT: pslld $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0 @@ -3786,10 +3786,10 @@ define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_xor_v8i32_v8i16: ; SSE: # BB#0: -; SSE-NEXT: pxor %xmm2, %xmm0 ; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 +; SSE-NEXT: pxor %xmm2, %xmm0 ; SSE-NEXT: pslld $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0 @@ -4542,10 +4542,10 @@ define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: trunc_or_v8i32_v8i16: ; SSE: # BB#0: -; SSE-NEXT: por %xmm2, %xmm0 ; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: pslld $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1 +; SSE-NEXT: por %xmm2, %xmm0 ; SSE-NEXT: pslld $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0 diff --git a/test/CodeGen/X86/vector-tzcnt-128.ll b/test/CodeGen/X86/vector-tzcnt-128.ll index 22d0065b264f..a22a60756264 100644 --- a/test/CodeGen/X86/vector-tzcnt-128.ll +++ b/test/CodeGen/X86/vector-tzcnt-128.ll @@ -7,6 +7,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512CDVL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,-avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512CD +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vpopcntdq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VPOPCNTDQ ; ; Just one 32-bit run to make sure we do reasonable things for i64 tzcnt. ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=X32-SSE --check-prefix=X32-SSE41 @@ -117,6 +118,17 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind { ; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv2i64: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubq %xmm0, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubq {{.*}}(%rip), %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: vzeroupper +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: testv2i64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -284,6 +296,17 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind { ; AVX512CD-NEXT: vzeroupper ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv2i64u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubq %xmm0, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubq {{.*}}(%rip), %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: vzeroupper +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: testv2i64u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -501,6 +524,18 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind { ; AVX512CD-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv4i32: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %xmm0, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: vzeroupper +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: testv4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -700,6 +735,18 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind { ; AVX512CD-NEXT: vzeroupper ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv4i32u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %xmm0, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: vzeroupper +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: testv4i32u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -843,6 +890,25 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind { ; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv8i16: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubw %xmm0, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %xmm0, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %xmm0, %xmm1, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: testv8i16: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -984,6 +1050,25 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind { ; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv8i16u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubw %xmm0, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %xmm0, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %xmm0, %xmm1, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: testv8i16u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -1106,6 +1191,22 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind { ; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv16i8: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubb %xmm0, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubb {{.*}}(%rip), %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: testv16i8: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -1224,6 +1325,22 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind { ; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv16i8u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubb %xmm0, %xmm1, %xmm1 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubb {{.*}}(%rip), %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %xmm2, %xmm3, %xmm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %xmm0, %xmm3, %xmm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %xmm2, %xmm0, %xmm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: testv16i8u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: pxor %xmm1, %xmm1 @@ -1258,6 +1375,12 @@ define <2 x i64> @foldv2i64() nounwind { ; AVX-NEXT: vmovq %rax, %xmm0 ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: foldv2i64: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: movl $8, %eax +; AVX512VPOPCNTDQ-NEXT: vmovq %rax, %xmm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: foldv2i64: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movl $8, %eax @@ -1280,6 +1403,12 @@ define <2 x i64> @foldv2i64u() nounwind { ; AVX-NEXT: vmovq %rax, %xmm0 ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: foldv2i64u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: movl $8, %eax +; AVX512VPOPCNTDQ-NEXT: vmovq %rax, %xmm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: foldv2i64u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movl $8, %eax @@ -1300,6 +1429,11 @@ define <4 x i32> @foldv4i32() nounwind { ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0] ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: foldv4i32: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0] +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: foldv4i32: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,32,0] @@ -1319,6 +1453,11 @@ define <4 x i32> @foldv4i32u() nounwind { ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0] ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: foldv4i32u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,32,0] +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: foldv4i32u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,32,0] @@ -1338,6 +1477,11 @@ define <8 x i16> @foldv8i16() nounwind { ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: foldv8i16: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: foldv8i16: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] @@ -1357,6 +1501,11 @@ define <8 x i16> @foldv8i16u() nounwind { ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: foldv8i16u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: foldv8i16u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,16,0,16,0,3,3] @@ -1376,6 +1525,11 @@ define <16 x i8> @foldv16i8() nounwind { ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: foldv16i8: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: foldv16i8: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] @@ -1395,6 +1549,11 @@ define <16 x i8> @foldv16i8u() nounwind { ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] ; AVX-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: foldv16i8u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-SSE-LABEL: foldv16i8u: ; X32-SSE: # BB#0: ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,8,0,8,0,3,3,1,1,0,1,2,3,4,5] diff --git a/test/CodeGen/X86/vector-tzcnt-256.ll b/test/CodeGen/X86/vector-tzcnt-256.ll index a0b277ddd732..101ae95550e7 100644 --- a/test/CodeGen/X86/vector-tzcnt-256.ll +++ b/test/CodeGen/X86/vector-tzcnt-256.ll @@ -3,6 +3,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512CDVL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,-avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512CD +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vpopcntdq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512VPOPCNTDQ ; ; Just one 32-bit run to make sure we do reasonable things for i64 tzcnt. ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=X32-AVX --check-prefix=X32-AVX2 @@ -12,11 +13,8 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX1: # BB#0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm1 -; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm3 -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 -; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm3 +; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1] ; AVX1-NEXT: vpsubq %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] @@ -28,6 +26,8 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 ; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1 ; AVX1-NEXT: vpsadbw %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm5 +; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0 ; AVX1-NEXT: vpsubq %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm3 ; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3 @@ -92,6 +92,17 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX512CD-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv4i64: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubq %ymm0, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpbroadcastq {{.*}}(%rip), %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubq %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-AVX-LABEL: testv4i64: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 @@ -117,11 +128,8 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { ; AVX1: # BB#0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm1 -; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm3 -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 -; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm3 +; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1] ; AVX1-NEXT: vpsubq %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] @@ -133,6 +141,8 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { ; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 ; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1 ; AVX1-NEXT: vpsadbw %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm5 +; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0 ; AVX1-NEXT: vpsubq %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm3 ; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3 @@ -182,6 +192,17 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { ; AVX512CD-NEXT: vpsubq %ymm0, %ymm1, %ymm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv4i64u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubq %ymm0, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpbroadcastq {{.*}}(%rip), %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubq %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-AVX-LABEL: testv4i64u: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 @@ -205,28 +226,27 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; AVX1-LABEL: testv8i32: ; AVX1: # BB#0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX1-NEXT: vpsubd %xmm2, %xmm1, %xmm2 -; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm3 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 -; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm3 +; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1] -; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm5 +; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm5 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 -; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2 -; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2 -; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 -; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2 -; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX1-NEXT: vpsadbw %xmm1, %xmm5, %xmm5 -; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero -; AVX1-NEXT: vpsadbw %xmm1, %xmm2, %xmm2 -; AVX1-NEXT: vpackuswb %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1 +; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 +; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm1[2],xmm2[2],xmm1[3],xmm2[3] +; AVX1-NEXT: vpsadbw %xmm2, %xmm5, %xmm5 +; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero +; AVX1-NEXT: vpsadbw %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpackuswb %xmm5, %xmm1, %xmm1 +; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm5 +; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0 ; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm3 ; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3 @@ -234,12 +254,12 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] -; AVX1-NEXT: vpsadbw %xmm1, %xmm3, %xmm3 +; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm0[2],xmm2[2],xmm0[3],xmm2[3] +; AVX1-NEXT: vpsadbw %xmm2, %xmm3, %xmm3 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero -; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: testv8i32: @@ -307,6 +327,17 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; AVX512CD-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv8i32: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %ymm0, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-AVX-LABEL: testv8i32: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 @@ -335,28 +366,27 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { ; AVX1-LABEL: testv8i32u: ; AVX1: # BB#0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX1-NEXT: vpsubd %xmm2, %xmm1, %xmm2 -; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm3 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 -; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm3 +; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1] -; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm5 +; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm5 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 -; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2 -; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2 -; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 -; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2 -; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX1-NEXT: vpsadbw %xmm1, %xmm5, %xmm5 -; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero -; AVX1-NEXT: vpsadbw %xmm1, %xmm2, %xmm2 -; AVX1-NEXT: vpackuswb %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1 +; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 +; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm5 = xmm1[2],xmm2[2],xmm1[3],xmm2[3] +; AVX1-NEXT: vpsadbw %xmm2, %xmm5, %xmm5 +; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero +; AVX1-NEXT: vpsadbw %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpackuswb %xmm5, %xmm1, %xmm1 +; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm5 +; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0 ; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm3 ; AVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3 @@ -364,12 +394,12 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] -; AVX1-NEXT: vpsadbw %xmm1, %xmm3, %xmm3 +; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm0[2],xmm2[2],xmm0[3],xmm2[3] +; AVX1-NEXT: vpsadbw %xmm2, %xmm3, %xmm3 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero -; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsadbw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: testv8i32u: @@ -414,6 +444,17 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { ; AVX512CD-NEXT: vpsubd %ymm0, %ymm1, %ymm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv8i32u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %ymm0, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpbroadcastd {{.*}}(%rip), %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-AVX-LABEL: testv8i32u: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 @@ -442,32 +483,31 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { ; AVX1-LABEL: testv16i16: ; AVX1: # BB#0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vpsubw %xmm1, %xmm2, %xmm1 -; AVX1-NEXT: vpsubw %xmm0, %xmm2, %xmm2 -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 -; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1] -; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm2 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4 +; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpsubw %xmm0, %xmm1, %xmm2 +; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1] +; AVX1-NEXT: vpsubw %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm5 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 ; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2 -; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2 -; AVX1-NEXT: vpaddb %xmm4, %xmm2, %xmm2 -; AVX1-NEXT: vpsllw $8, %xmm2, %xmm4 -; AVX1-NEXT: vpaddb %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 +; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $8, %xmm2, %xmm5 +; AVX1-NEXT: vpaddb %xmm2, %xmm5, %xmm2 ; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm1 -; AVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1 +; AVX1-NEXT: vpsubw %xmm0, %xmm1, %xmm1 +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsubw %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm1 +; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0 -; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0 +; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1 ; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0 @@ -532,6 +572,25 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { ; AVX512CD-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv16i16: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm0, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm0, %ymm1, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-AVX-LABEL: testv16i16: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 @@ -557,32 +616,31 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind { ; AVX1-LABEL: testv16i16u: ; AVX1: # BB#0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vpsubw %xmm1, %xmm2, %xmm1 -; AVX1-NEXT: vpsubw %xmm0, %xmm2, %xmm2 -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 -; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1] -; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm2 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4 +; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vpsubw %xmm0, %xmm1, %xmm2 +; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1] +; AVX1-NEXT: vpsubw %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm5 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 ; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2 -; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2 -; AVX1-NEXT: vpaddb %xmm4, %xmm2, %xmm2 -; AVX1-NEXT: vpsllw $8, %xmm2, %xmm4 -; AVX1-NEXT: vpaddb %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 +; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpsllw $8, %xmm2, %xmm5 +; AVX1-NEXT: vpaddb %xmm2, %xmm5, %xmm2 ; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm1 -; AVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1 +; AVX1-NEXT: vpsubw %xmm0, %xmm1, %xmm1 +; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsubw %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm1 +; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0 -; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0 +; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $8, %xmm0, %xmm1 ; AVX1-NEXT: vpaddb %xmm0, %xmm1, %xmm0 @@ -647,6 +705,25 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind { ; AVX512CD-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv16i16u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm0, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm0, %ymm1, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-AVX-LABEL: testv16i16u: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 @@ -674,27 +751,26 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; AVX1: # BB#0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1 -; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2 -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 -; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] -; AVX1-NEXT: vpsubb %xmm2, %xmm1, %xmm1 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm4 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4 -; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm3 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1 -; AVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1 -; AVX1-NEXT: vpaddb %xmm4, %xmm1, %xmm1 -; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0 -; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm2 -; AVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] +; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm5 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 +; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1 +; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 +; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1 +; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2 +; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0 -; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0 +; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: retq @@ -747,6 +823,22 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv32i8: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsubb {{.*}}(%rip), %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-AVX-LABEL: testv32i8: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 @@ -771,27 +863,26 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; AVX1: # BB#0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1 -; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2 -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 -; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] -; AVX1-NEXT: vpsubb %xmm2, %xmm1, %xmm1 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm4 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; AVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4 -; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm3 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1 -; AVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1 -; AVX1-NEXT: vpaddb %xmm4, %xmm1, %xmm1 -; AVX1-NEXT: vpsubb %xmm2, %xmm0, %xmm0 -; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm2 -; AVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] +; AVX1-NEXT: vpsubb %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm5 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 +; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1 +; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1 +; AVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 +; AVX1-NEXT: vpaddb %xmm5, %xmm1, %xmm1 +; AVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2 +; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm2 +; AVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm0 -; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0 +; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: retq @@ -844,6 +935,22 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; AVX512CD-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX512CD-NEXT: retq ; +; AVX512VPOPCNTDQ-LABEL: testv32i8u: +; AVX512VPOPCNTDQ: # BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm1, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsubb {{.*}}(%rip), %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm3, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm3, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: retq +; ; X32-AVX-LABEL: testv32i8u: ; X32-AVX: # BB#0: ; X32-AVX-NEXT: vpxor %ymm1, %ymm1, %ymm1 diff --git a/test/CodeGen/X86/vector-tzcnt-512.ll b/test/CodeGen/X86/vector-tzcnt-512.ll index 2d1715949a5e..abbe964e983c 100644 --- a/test/CodeGen/X86/vector-tzcnt-512.ll +++ b/test/CodeGen/X86/vector-tzcnt-512.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd,-avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512CD ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512CDBW ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=-avx512cd,+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512vpopcntdq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VPOPCNTDQ define <8 x i64> @testv8i64(<8 x i64> %in) nounwind { ; AVX512CD-LABEL: testv8i64: @@ -64,6 +65,15 @@ define <8 x i64> @testv8i64(<8 x i64> %in) nounwind { ; AVX512BW-NEXT: vpaddb %zmm3, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv8i64: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxord %zmm1, %zmm1, %zmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubq %zmm0, %zmm1, %zmm1 +; AVX512VPOPCNTDQ-NEXT: vpandq %zmm1, %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubq {{.*}}(%rip){1to8}, %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %in, i1 0) ret <8 x i64> %out } @@ -105,6 +115,15 @@ define <8 x i64> @testv8i64u(<8 x i64> %in) nounwind { ; AVX512BW-NEXT: vpaddb %zmm3, %zmm0, %zmm0 ; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv8i64u: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxord %zmm1, %zmm1, %zmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubq %zmm0, %zmm1, %zmm1 +; AVX512VPOPCNTDQ-NEXT: vpandq %zmm1, %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubq {{.*}}(%rip){1to8}, %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %in, i1 -1) ret <8 x i64> %out } @@ -186,6 +205,15 @@ define <16 x i32> @testv16i32(<16 x i32> %in) nounwind { ; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv16i32: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxord %zmm1, %zmm1, %zmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %zmm0, %zmm1, %zmm1 +; AVX512VPOPCNTDQ-NEXT: vpandd %zmm1, %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubd {{.*}}(%rip){1to16}, %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %in, i1 0) ret <16 x i32> %out } @@ -231,6 +259,15 @@ define <16 x i32> @testv16i32u(<16 x i32> %in) nounwind { ; AVX512BW-NEXT: vpsadbw %zmm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv16i32u: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxord %zmm1, %zmm1, %zmm1 +; AVX512VPOPCNTDQ-NEXT: vpsubd %zmm0, %zmm1, %zmm1 +; AVX512VPOPCNTDQ-NEXT: vpandd %zmm1, %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: vpsubd {{.*}}(%rip){1to16}, %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %in, i1 -1) ret <16 x i32> %out } @@ -305,6 +342,38 @@ define <32 x i16> @testv32i16(<32 x i16> %in) nounwind { ; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0 ; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv32i16: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm2, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm5, %ymm6, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm6, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm5, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm0, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm0, %ymm5, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm1, %ymm2, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm3, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm1, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm6, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm1, %ymm6, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm1, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 0) ret <32 x i16> %out } @@ -379,6 +448,38 @@ define <32 x i16> @testv32i16u(<32 x i16> %in) nounwind { ; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0 ; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv32i16u: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm0, %ymm2, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm5, %ymm6, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm6, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm5, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm0, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm0, %ymm5, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm1, %ymm2, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubw %ymm3, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm1, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm6, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm1, %ymm6, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsllw $8, %ymm1, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm1, %ymm2, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $8, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 -1) ret <32 x i16> %out } @@ -441,6 +542,32 @@ define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { ; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv64i8: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm2, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm5, %ymm6, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm6, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm5, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm1, %ymm2, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm3, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm1, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm6, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm1, %ymm6, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 0) ret <64 x i8> %out } @@ -503,6 +630,32 @@ define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind { ; AVX512BW-NEXT: vpshufb %zmm0, %zmm3, %zmm0 ; AVX512BW-NEXT: vpaddb %zmm2, %zmm0, %zmm0 ; AVX512BW-NEXT: retq +; +; AVX512VPOPCNTDQ-LABEL: testv64i8u: +; AVX512VPOPCNTDQ: ## BB#0: +; AVX512VPOPCNTDQ-NEXT: vpxor %ymm2, %ymm2, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm0, %ymm2, %ymm3 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm3 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm3, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vmovdqa {{.*#+}} ymm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm5, %ymm6, %ymm5 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm0, %ymm6, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm5, %ymm0, %ymm0 +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm1, %ymm2, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpsubb %ymm3, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm1, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm2, %ymm6, %ymm2 +; AVX512VPOPCNTDQ-NEXT: vpsrlw $4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpand %ymm4, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpshufb %ymm1, %ymm6, %ymm1 +; AVX512VPOPCNTDQ-NEXT: vpaddb %ymm2, %ymm1, %ymm1 +; AVX512VPOPCNTDQ-NEXT: retq %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 -1) ret <64 x i8> %out } diff --git a/test/CodeGen/X86/wide-integer-cmp.ll b/test/CodeGen/X86/wide-integer-cmp.ll index fbaf500e8333..b5c7f86567a1 100644 --- a/test/CodeGen/X86/wide-integer-cmp.ll +++ b/test/CodeGen/X86/wide-integer-cmp.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=i686-linux-gnu %s -o - | FileCheck %s - define i32 @branch_eq(i64 %a, i64 %b) { ; CHECK-LABEL: branch_eq: ; CHECK: # BB#0: # %entry diff --git a/test/CodeGen/X86/widened-broadcast.ll b/test/CodeGen/X86/widened-broadcast.ll index 6b2e4de5cdaa..42c4c23c6349 100644 --- a/test/CodeGen/X86/widened-broadcast.ll +++ b/test/CodeGen/X86/widened-broadcast.ll @@ -151,8 +151,7 @@ define <8 x i32> @load_splat_8i32_8i32_01010101(<8 x i32>* %ptr) nounwind uwtabl ; ; AVX1-LABEL: load_splat_8i32_8i32_01010101: ; AVX1: # BB#0: # %entry -; AVX1-NEXT: vmovapd (%rdi), %ymm0 -; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] +; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: retq ; @@ -288,8 +287,7 @@ define <16 x i16> @load_splat_16i16_16i16_0101010101010101(<16 x i16>* %ptr) nou ; ; AVX1-LABEL: load_splat_16i16_16i16_0101010101010101: ; AVX1: # BB#0: # %entry -; AVX1-NEXT: vmovaps (%rdi), %ymm0 -; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0] +; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = mem[0,0,0,0] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: retq ; @@ -315,22 +313,10 @@ define <16 x i16> @load_splat_16i16_16i16_0123012301230123(<16 x i16>* %ptr) nou ; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: retq ; -; AVX1-LABEL: load_splat_16i16_16i16_0123012301230123: -; AVX1: # BB#0: # %entry -; AVX1-NEXT: vbroadcastsd (%rdi), %ymm0 -; AVX1-NEXT: retq -; -; AVX2-LABEL: load_splat_16i16_16i16_0123012301230123: -; AVX2: # BB#0: # %entry -; AVX2-NEXT: vmovaps (%rdi), %ymm0 -; AVX2-NEXT: vbroadcastsd %xmm0, %ymm0 -; AVX2-NEXT: retq -; -; AVX512-LABEL: load_splat_16i16_16i16_0123012301230123: -; AVX512: # BB#0: # %entry -; AVX512-NEXT: vmovaps (%rdi), %ymm0 -; AVX512-NEXT: vbroadcastsd %xmm0, %ymm0 -; AVX512-NEXT: retq +; AVX-LABEL: load_splat_16i16_16i16_0123012301230123: +; AVX: # BB#0: # %entry +; AVX-NEXT: vbroadcastsd (%rdi), %ymm0 +; AVX-NEXT: retq entry: %ld = load <16 x i16>, <16 x i16>* %ptr %ret = shufflevector <16 x i16> %ld, <16 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3,i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> @@ -513,8 +499,7 @@ define <32 x i8> @load_splat_32i8_32i8_01010101010101010101010101010101(<32 x i8 ; ; AVX1-LABEL: load_splat_32i8_32i8_01010101010101010101010101010101: ; AVX1: # BB#0: # %entry -; AVX1-NEXT: vmovdqa (%rdi), %ymm0 -; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] +; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = mem[0,0,0,0,4,5,6,7] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: retq @@ -587,26 +572,10 @@ define <4 x float> @load_splat_4f32_8f32_0000(<8 x float>* %ptr) nounwind uwtabl ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0] ; SSE-NEXT: retq ; -; AVX1-LABEL: load_splat_4f32_8f32_0000: -; AVX1: # BB#0: # %entry -; AVX1-NEXT: vmovaps (%rdi), %ymm0 -; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0] -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: load_splat_4f32_8f32_0000: -; AVX2: # BB#0: # %entry -; AVX2-NEXT: vmovaps (%rdi), %ymm0 -; AVX2-NEXT: vbroadcastss %xmm0, %xmm0 -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -; -; AVX512-LABEL: load_splat_4f32_8f32_0000: -; AVX512: # BB#0: # %entry -; AVX512-NEXT: vmovaps (%rdi), %ymm0 -; AVX512-NEXT: vbroadcastss %xmm0, %xmm0 -; AVX512-NEXT: vzeroupper -; AVX512-NEXT: retq +; AVX-LABEL: load_splat_4f32_8f32_0000: +; AVX: # BB#0: # %entry +; AVX-NEXT: vbroadcastss (%rdi), %xmm0 +; AVX-NEXT: retq entry: %ld = load <8 x float>, <8 x float>* %ptr %ret = shufflevector <8 x float> %ld, <8 x float> undef, <4 x i32> zeroinitializer @@ -627,22 +596,10 @@ define <8 x float> @load_splat_8f32_16f32_89898989(<16 x float>* %ptr) nounwind ; SSE42-NEXT: movapd %xmm0, %xmm1 ; SSE42-NEXT: retq ; -; AVX1-LABEL: load_splat_8f32_16f32_89898989: -; AVX1: # BB#0: # %entry -; AVX1-NEXT: vbroadcastsd 32(%rdi), %ymm0 -; AVX1-NEXT: retq -; -; AVX2-LABEL: load_splat_8f32_16f32_89898989: -; AVX2: # BB#0: # %entry -; AVX2-NEXT: vbroadcastsd 32(%rdi), %ymm0 -; AVX2-NEXT: retq -; -; AVX512-LABEL: load_splat_8f32_16f32_89898989: -; AVX512: # BB#0: # %entry -; AVX512-NEXT: vmovapd (%rdi), %zmm0 -; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm0 -; AVX512-NEXT: vbroadcastsd %xmm0, %ymm0 -; AVX512-NEXT: retq +; AVX-LABEL: load_splat_8f32_16f32_89898989: +; AVX: # BB#0: # %entry +; AVX-NEXT: vbroadcastsd 32(%rdi), %ymm0 +; AVX-NEXT: retq entry: %ld = load <16 x float>, <16 x float>* %ptr %ret = shufflevector <16 x float> %ld, <16 x float> undef, <8 x i32> <i32 8, i32 9, i32 8, i32 9, i32 8, i32 9, i32 8, i32 9> diff --git a/test/CodeGen/X86/x86-interleaved-access.ll b/test/CodeGen/X86/x86-interleaved-access.ll index 6fbec91e77a3..f4d0503f4a79 100644 --- a/test/CodeGen/X86/x86-interleaved-access.ll +++ b/test/CodeGen/X86/x86-interleaved-access.ll @@ -57,10 +57,8 @@ define <4 x double> @load_factorf64_1(<16 x double>* %ptr) { ; AVX1: # BB#0: ; AVX1-NEXT: vmovups (%rdi), %ymm0 ; AVX1-NEXT: vmovups 32(%rdi), %ymm1 -; AVX1-NEXT: vmovups 64(%rdi), %ymm2 -; AVX1-NEXT: vmovups 96(%rdi), %ymm3 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 -; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 +; AVX1-NEXT: vinsertf128 $1, 64(%rdi), %ymm0, %ymm0 +; AVX1-NEXT: vinsertf128 $1, 96(%rdi), %ymm1, %ymm1 ; AVX1-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] ; AVX1-NEXT: vmulpd %ymm0, %ymm0, %ymm0 ; AVX1-NEXT: retq @@ -69,10 +67,8 @@ define <4 x double> @load_factorf64_1(<16 x double>* %ptr) { ; AVX2: # BB#0: ; AVX2-NEXT: vmovupd (%rdi), %ymm0 ; AVX2-NEXT: vmovupd 32(%rdi), %ymm1 -; AVX2-NEXT: vmovupd 64(%rdi), %ymm2 -; AVX2-NEXT: vmovupd 96(%rdi), %ymm3 -; AVX2-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 -; AVX2-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 +; AVX2-NEXT: vinsertf128 $1, 64(%rdi), %ymm0, %ymm0 +; AVX2-NEXT: vinsertf128 $1, 96(%rdi), %ymm1, %ymm1 ; AVX2-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] ; AVX2-NEXT: vmulpd %ymm0, %ymm0, %ymm0 ; AVX2-NEXT: retq diff --git a/test/CodeGen/X86/x87.ll b/test/CodeGen/X86/x87.ll index 683d7b05cf8c..9bc654861b69 100644 --- a/test/CodeGen/X86/x87.ll +++ b/test/CodeGen/X86/x87.ll @@ -1,13 +1,16 @@ ; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X87 ; RUN: llc < %s -march=x86-64 -mattr=-sse | FileCheck %s -check-prefix=X87 -; RUN: llc < %s -march=x86 -mattr=-x87 | FileCheck %s -check-prefix=NOX87 --implicit-check-not "{{ }}f{{.*}}" -; RUN: llc < %s -march=x86-64 -mattr=-x87,-sse | FileCheck %s -check-prefix=NOX87 --implicit-check-not "{{ }}f{{.*}}" -; RUN: llc < %s -march=x86 -mattr=-x87,+sse | FileCheck %s -check-prefix=NOX87 --implicit-check-not "{{ }}f{{.*}}" -; RUN: llc < %s -march=x86-64 -mattr=-x87,-sse2 | FileCheck %s -check-prefix=NOX87 --implicit-check-not "{{ }}f{{.*}}" +; RUN: llc < %s -march=x86 -mattr=-x87 | FileCheck %s -check-prefix=NOX87 +; RUN: llc < %s -march=x86-64 -mattr=-x87,-sse | FileCheck %s -check-prefix=NOX87 +; RUN: llc < %s -march=x86 -mattr=-x87,+sse | FileCheck %s -check-prefix=NOX87 +; RUN: llc < %s -march=x86-64 -mattr=-x87,-sse2 | FileCheck %s -check-prefix=NOX87 define void @test(i32 %i, i64 %l, float* %pf, double* %pd, fp128* %pld) nounwind readnone { ; X87-LABEL: test: ; NOX87-LABEL: test: + +; NOX87-NOT: {{ }}f{{.*}} + ; X87: fild ; NOX87: __floatunsisf %tmp = uitofp i32 %i to float diff --git a/test/CodeGen/XCore/epilogue_prologue.ll b/test/CodeGen/XCore/epilogue_prologue.ll index aed49f4b67ba..d214c40dd9b9 100644 --- a/test/CodeGen/XCore/epilogue_prologue.ll +++ b/test/CodeGen/XCore/epilogue_prologue.ll @@ -6,7 +6,7 @@ ; When using FP, for large or small frames, we may need one scratch register. ; FP + small frame: spill FP+SR = entsp 2 -; CHECKFP-LABEL: f1 +; CHECKFP-LABEL: f1: ; CHECKFP: entsp 2 ; CHECKFP-NEXT: stw r10, sp[1] ; CHECKFP-NEXT: ldaw r10, sp[0] @@ -15,7 +15,7 @@ ; CHECKFP-NEXT: retsp 2 ; ; !FP + small frame: no spills = no stack adjustment needed -; CHECK-LABEL: f1 +; CHECK-LABEL: f1: ; CHECK: stw lr, sp[0] ; CHECK: ldw lr, sp[0] ; CHECK-NEXT: retsp 0 @@ -27,7 +27,7 @@ entry: ; FP + small frame: spill FP+SR+R0+LR = entsp 3 + extsp 1 -; CHECKFP-LABEL:f3 +; CHECKFP-LABEL: f3: ; CHECKFP: entsp 3 ; CHECKFP-NEXT: stw r10, sp[1] ; CHECKFP-NEXT: ldaw r10, sp[0] @@ -43,7 +43,7 @@ entry: ; CHECKFP-NEXT: retsp 3 ; ; !FP + small frame: spill R0+LR = entsp 2 -; CHECK-LABEL: f3 +; CHECK-LABEL: f3: ; CHECK: entsp 2 ; CHECK-NEXT: stw [[REG:r[4-9]+]], sp[1] ; CHECK-NEXT: mov [[REG]], r0 @@ -60,7 +60,7 @@ entry: ; FP + large frame: spill FP+SR = entsp 2 + 100000 -; CHECKFP-LABEL: f4 +; CHECKFP-LABEL: f4: ; CHECKFP: entsp 65535 ; CHECKFP-NEXT: .Lcfi{{[0-9]+}} ; CHECKFP-NEXT: .cfi_def_cfa_offset 262140 @@ -81,7 +81,7 @@ entry: ; CHECKFP-NEXT: retsp 34467 ; ; !FP + large frame: spill SR+SR = entsp 2 + 100000 -; CHECK-LABEL: f4 +; CHECK-LABEL: f4: ; CHECK: entsp 65535 ; CHECK-NEXT: .Lcfi{{[0-9]+}} ; CHECK-NEXT: .cfi_def_cfa_offset 262140 @@ -107,7 +107,7 @@ entry: ; CHECKFP-NEXT: .LCPI[[CNST1:[0-9_]+]]: ; CHECKFP-NEXT: .long 200001 ; CHECKFP-NEXT: .text -; CHECKFP-LABEL: f6 +; CHECKFP-LABEL: f6: ; CHECKFP: entsp 65535 ; CHECKFP-NEXT: .Lcfi{{[0-9]+}} ; CHECKFP-NEXT: .cfi_def_cfa_offset 262140 @@ -160,7 +160,7 @@ entry: ; CHECK-NEXT: .LCPI[[CNST1:[0-9_]+]]: ; CHECK-NEXT: .long 200002 ; CHECK-NEXT: .text -; CHECK-LABEL: f6 +; CHECK-LABEL: f6: ; CHECK: entsp 65535 ; CHECK-NEXT: .Lcfi{{[0-9]+}} ; CHECK-NEXT: .cfi_def_cfa_offset 262140 @@ -207,7 +207,7 @@ entry: } ; FP + large frame: spill FP+SR+LR = entsp 2 + 256 + extsp 1 -; CHECKFP-LABEL:f8 +; CHECKFP-LABEL: f8: ; CHECKFP: entsp 258 ; CHECKFP-NEXT: stw r10, sp[1] ; CHECKFP-NEXT: ldaw r10, sp[0] @@ -221,7 +221,7 @@ entry: ; CHECKFP-NEXT: retsp 258 ; ; !FP + large frame: spill SR+SR+LR = entsp 3 + 256 -; CHECK-LABEL:f8 +; CHECK-LABEL: f8: ; CHECK: entsp 257 ; CHECK-NEXT: ldaw r0, sp[254] ; CHECK-NEXT: bl f5 @@ -235,7 +235,7 @@ entry: } ; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1 -; CHECKFP-LABEL:f9 +; CHECKFP-LABEL: f9: ; CHECKFP: entsp 32770 ; CHECKFP-NEXT: stw r10, sp[1] ; CHECKFP-NEXT: ldaw r10, sp[0] @@ -249,7 +249,7 @@ entry: ; CHECKFP-NEXT: retsp 32770 ; ; !FP + large frame: spill SR+SR+LR = entsp 3 + 32768 -; CHECK-LABEL:f9 +; CHECK-LABEL: f9: ; CHECK: entsp 32771 ; CHECK-NEXT: ldaw r0, sp[32768] ; CHECK-NEXT: bl f5 |