diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2015-01-18 16:17:27 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-01-18 16:17:27 +0000 |
| commit | 67c32a98315f785a9ec9d531c1f571a0196c7463 (patch) | |
| tree | 4abb9cbeecc7901726dd0b4a37369596c852e9ef /test/MC/ARM | |
| parent | 9f61947910e6ab40de38e6b4034751ef1513200f (diff) | |
Diffstat (limited to 'test/MC/ARM')
50 files changed, 2606 insertions, 484 deletions
diff --git a/test/MC/ARM/arm-elf-relocation-diagnostics.s b/test/MC/ARM/arm-elf-relocation-diagnostics.s new file mode 100644 index 000000000000..5fe903f71619 --- /dev/null +++ b/test/MC/ARM/arm-elf-relocation-diagnostics.s @@ -0,0 +1,27 @@ +@ RUN: not llvm-mc -triple armv7-eabi -filetype obj -o - %s 2>&1 \ +@ RUN: | FileCheck %s +@ RUN: not llvm-mc -triple thumbv7-eabi -filetype obj -o - %s 2>&1 \ +@ RUN: | FileCheck %s + + .byte target(sbrel) +@ CHECK: error: relocated expression must be 32-bit +@ CHECK: .byte target(sbrel) +@ CHECK: ^ + +@ TODO: enable these negative test cases +@ .hword target(sbrel) +@ @ CHECK-SBREL-HWORD: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-HWORD: .hword target(sbrel) +@ @ CHECK-SBREL-HWORD: ^ +@ +@ .short target(sbrel) +@ @ CHECK-SBREL-SHORT: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-SHORT: .short target(sbrel) +@ @ CHECK-SBREL-SHORT: ^ +@ +@ .quad target(sbrel) +@ @ CHECK-SBREL-SHORT: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-SHORT: .quad target(sbrel) +@ @ CHECK-SBREL-SHORT: ^ + + diff --git a/test/MC/ARM/arm-elf-relocations.s b/test/MC/ARM/arm-elf-relocations.s new file mode 100644 index 000000000000..4059591d95b1 --- /dev/null +++ b/test/MC/ARM/arm-elf-relocations.s @@ -0,0 +1,37 @@ +@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s | llvm-readobj -r - \ +@ RUN: | FileCheck %s +@ RUN: llvm-mc -triple thumbv7-eabi -filetype obj -o - %s | llvm-readobj -r - \ +@ RUN: | FileCheck %s + + .syntax unified + + .section .text.r_arm_abs8 + + .byte abs8_0 -128 + .byte abs8_1 +255 + +@ CHECK: Section {{.*}} .rel.text.r_arm_abs8 { +@ CHECK: 0x0 R_ARM_ABS8 abs8_0 0x0 +@ CHECK: 0x1 R_ARM_ABS8 abs8_1 0x0 +@ CHECK: } + + .section .text.r_arm_abs16 + + .short abs16_0 -32768 + .short abs16_1 +65535 + +@ CHECK: Section {{.*}} .rel.text.r_arm_abs16 { +@ CHECK: 0x0 R_ARM_ABS16 abs16_0 0x0 +@ CHECK: 0x2 R_ARM_ABS16 abs16_1 0x0 +@ CHECK: } + + .section .text.r_arm_sbrel32 + + .word target(sbrel) + .word target(SBREL) + +@ CHECK: Section {{.*}} .rel.text.r_arm_sbrel32 { +@ CHECK: 0x0 R_ARM_SBREL32 target 0x0 +@ CHECK: 0x4 R_ARM_SBREL32 target 0x0 +@ CHECK: } + diff --git a/test/MC/ARM/arm-load-store-multiple-deprecated.s b/test/MC/ARM/arm-load-store-multiple-deprecated.s new file mode 100644 index 000000000000..9354822bc417 --- /dev/null +++ b/test/MC/ARM/arm-load-store-multiple-deprecated.s @@ -0,0 +1,222 @@ +@ RUN: llvm-mc -triple armv6t2-linux-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck %s + +@ RUN: not llvm-mc -triple armv7-linux-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck %s -check-prefix CHECK -check-prefix CHECK-V7 + + .syntax unified + .arm + + .global stm + .type stm,%function +stm: + stm sp!, {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm sp!, {r0, pc} +@ CHECK: ^ + stm r0!, {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm r0!, {r0, sp} +@ CHECK: ^ + stm r1!, {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm r1!, {r0, sp, pc} +@ CHECK: ^ + stm r2!, {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm r2!, {sp, pc} +@ CHECK: ^ + stm sp!, {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm sp!, {pc} +@ CHECK: ^ + stm r0!, {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stm r0!, {sp} +@ CHECK: ^ + + .global stmda + .type stmda,%function +stmda: + stmda sp!, {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda sp!, {r0, pc} +@ CHECK: ^ + stmda r0!, {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda r0!, {r0, sp} +@ CHECK: ^ + stmda r1!, {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda r1!, {r0, sp, pc} +@ CHECK: ^ + stmda r2!, {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda r2!, {sp, pc} +@ CHECK: ^ + stmda sp!, {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda sp!, {pc} +@ CHECK: ^ + stmda r0!, {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmda r0!, {sp} +@ CHECK: ^ + + .global stmdb + .type stmdb,%function +stmdb: + stmdb sp!, {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb sp!, {r0, pc} +@ CHECK: ^ + stmdb r0!, {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb r0!, {r0, sp} +@ CHECK: ^ + stmdb r1!, {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb r1!, {r0, sp, pc} +@ CHECK: ^ + stmdb r2!, {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb r2!, {sp, pc} +@ CHECK: ^ + stmdb sp!, {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb sp!, {pc} +@ CHECK: ^ + stmdb r0!, {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmdb r0!, {sp} +@ CHECK: ^ + + .global stmib + .type stmib,%function +stmib: + stmib sp!, {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib sp!, {r0, pc} +@ CHECK: ^ + stmib r0!, {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib r0!, {r0, sp} +@ CHECK: ^ + stmib r1!, {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib r1!, {r0, sp, pc} +@ CHECK: ^ + stmib r2!, {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib r2!, {sp, pc} +@ CHECK: ^ + stmib sp!, {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib sp!, {pc} +@ CHECK: ^ + stmib r0!, {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: stmib r0!, {sp} +@ CHECK: ^ + + + .global push + .type push,%function +push: + push {r0, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {r0, pc} +@ CHECK: ^ + push {r0, sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {r0, sp} +@ CHECK: ^ + push {r0, sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {r0, sp, pc} +@ CHECK: ^ + push {sp, pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {sp, pc} +@ CHECK: ^ + push {pc} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {pc} +@ CHECK: ^ + push {sp} +@ CHECK: warning: use of SP or PC in the list is deprecated +@ CHECK: push {sp} +@ CHECK: ^ + + .global ldm + .type ldm,%function +ldm: + ldm r0!, {r1, sp} +@ CHECK: warning: use of SP in the list is deprecated + ldm r0!, {sp} +@ CHECK: warning: use of SP in the list is deprecated + ldm r0!, {r1, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + ldm r0!, {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global ldmda + .type ldmda,%function +ldmda: + ldmda r0!, {r1, sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmda r0!, {sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmda r0!, {r1, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + ldmda r0!, {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global ldmdb + .type ldmdb,%function +ldmdb: + ldmdb r0!, {r1, sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmdb r0!, {sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmdb r0!, {r1, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + ldmdb r0!, {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global ldmib + .type ldmib,%function +ldmib: + ldmib r0!, {r1, sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmib r0!, {sp} +@ CHECK: warning: use of SP in the list is deprecated + ldmib r0!, {r1, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + ldmib r0!, {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global pop + .type pop,%function +pop: + pop {r0, sp} +@ CHECK: warning: use of SP in the list is deprecated +@ CHECK-V7: error: writeback register not allowed in register list + pop {sp} +@ CHECK: warning: use of SP in the list is deprecated +@ CHECK-V7: error: writeback register not allowed in register list + pop {r0, lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + pop {lr, pc} +@ CHECK: warning: use of LR and PC simultaneously in the list is deprecated + + .global valid + .type valid,%function +valid: + stmdaeq r0, {r0} +@ CHECK: stmdaeq r0, {r0} + ldmdaeq r0, {r0} +@ CHECK: ldmdaeq r0, {r0} + pop {r0, pc} +@ CHECK: pop {r0, pc} + diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index a4b6bda880c5..a4c100ee68f9 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -1,6 +1,6 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s \ @ RUN: | FileCheck %s -check-prefix=ALL -@ RUN: llvm-mc -mcpu=cortex-a9-mp -triple armv7-unknown-nacl -show-encoding %s \ +@ RUN: llvm-mc -mcpu=cortex-a9 -triple armv7-unknown-nacl -show-encoding %s \ @ RUN: | FileCheck %s -check-prefix=NACL @ RUN: llvm-mc -mcpu=cortex-a8 -mattr=+nacl-trap -triple armv7 -show-encoding %s \ @ RUN: | FileCheck %s -check-prefix=NACL diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index e5e96170a775..616674e56350 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -16,6 +16,15 @@ _func: @ ADC (immediate) @------------------------------------------------------------------------------ adc r1, r2, #0xf + adc r1, r2, $0xf + adc r1, r2, 0xf + adc r7, r8, #(0xff << 16) + adc r7, r8, #-2147483638 + adc r7, r8, #42, #2 + adc r7, r8, #40, #2 + adc r7, r8, $40, $2 + adc r7, r8, 40, 2 + adc r7, r8, (2 * 20), (1 << 1) adc r1, r2, #0xf0 adc r1, r2, #0xf00 adc r1, r2, #0xf000 @@ -25,20 +34,30 @@ _func: adc r1, r2, #0xf0000000 adc r1, r2, #0xf000000f adcs r1, r2, #0xf00 + adcs r7, r8, #40, #2 adcseq r1, r2, #0xf00 adceq r1, r2, #0xf00 @ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2] +@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2] +@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2] +@ CHECK: adc r7, r8, #16711680 @ encoding: [0xff,0x78,0xa8,0xe2] +@ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2] +@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2] @ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2] @ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2] @ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2] @ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2] @ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2] @ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2] -@ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2] -@ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2] - +@ CHECK: adc r1, r2, #-268435456 @ encoding: [0x0f,0x12,0xa2,0xe2] +@ CHECK: adc r1, r2, #-268435441 @ encoding: [0xff,0x12,0xa2,0xe2] @ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2] +@ CHECK: adcs r7, r8, #40, #2 @ encoding: [0x28,0x71,0xb8,0xe2] @ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02] @ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02] @@ -162,6 +181,16 @@ Lforward: @ ADD @------------------------------------------------------------------------------ add r4, r5, #0xf000 + add r4, r5, $0xf000 + add r4, r5, 0xf000 + add r4, r5, -0xf000 + add r7, r8, #(0xff << 16) + add r7, r8, #-2147483638 + add r7, r8, #42, #2 + add r7, r8, #40, #2 + add r7, r8, $40, $2 + add r7, r8, 40, 2 + add r7, r8, (2 * 20), (1 << 1) add r4, r5, r6 add r4, r5, r6, lsl #5 add r4, r5, r6, lsr #5 @@ -177,6 +206,16 @@ Lforward: @ destination register is optional add r5, #0xf000 + add r5, $0xf000 + add r5, 0xf000 + add r5, -0xf000 + add r7, #(0xff << 16) + add r7, #-2147483638 + add r7, #42, #2 + add r7, #40, #2 + add r7, $40, $2 + add r7, 40, 2 + add r7, (2 * 20), (1 << 1) add r4, r5 add r4, r5, lsl #5 add r4, r5, lsr #5 @@ -189,11 +228,25 @@ Lforward: add r6, r7, ror r9 add r4, r5, rrx - add r0, #-4 - add r4, r5, #-21 + add r0, #-4 + add r4, r5, #-21 add r0, pc, #0xc0000000 + addseq r0,pc,#0xc0000000 + + + add r0, pc, #(Lback - .) @ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] +@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] +@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] +@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: add r7, r8, #16711680 @ encoding: [0xff,0x78,0x88,0xe2] +@ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2] +@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2] @ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0] @ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0] @ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0] @@ -208,6 +261,16 @@ Lforward: @ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0] @ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2] +@ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2] +@ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2] +@ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: add r7, r7, #16711680 @ encoding: [0xff,0x78,0x87,0xe2] +@ CHECK: add r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe2] +@ CHECK: add r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe2] @ CHECK: add r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe0] @ CHECK: add r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe0] @ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0] @@ -222,7 +285,12 @@ Lforward: @ CHECK: sub r0, r0, #4 @ encoding: [0x04,0x00,0x40,0xe2] @ CHECK: sub r4, r5, #21 @ encoding: [0x15,0x40,0x45,0xe2] -@ CHECK: adr r0, #-1073741824 @ encoding: [0x03,0x01,0x8f,0xe2] +@ CHECK: adr r0, #-1073741824 @ encoding: [0x03,0x01,0x8f,0xe2] +@ CHECK: addseq r0, pc, #-1073741824 @ encoding: [0x03,0x01,0x9f,0x02] +@ CHECK: Ltmp0: +@ CHECK-NEXT: Ltmp1: +@ CHECK-NEXT: adr r0, (Ltmp1+8)+(Lback-Ltmp0) @ encoding: [A,A,0x0f'A',0xe2'A'] +@ CHECK-NEXT: @ fixup A - offset: 0, value: (Ltmp1+8)+(Lback-Ltmp0), kind: fixup_arm_adr_pcrel_12 @ Test right shift by 32, which is encoded as 0 add r3, r1, r2, lsr #32 @@ -231,9 +299,44 @@ Lforward: @ CHECK: add r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe0] @------------------------------------------------------------------------------ +@ ADDS +@------------------------------------------------------------------------------ + adds r7, r8, #16711680 + adds r7, r8, $16711680 + adds r7, r8, 16711680 + adds r7, r8, #(0xff << 16) + adds r7, r8, #-2147483638 + adds r7, r8, #42, #2 + adds r7, r8, #40, #2 + adds r7, r8, $40, $2 + adds r7, r8, 40, 2 + adds r7, r8, (2 * 20), (1 << 1) + +@ CHECK: adds r7, r8, #16711680 @ encoding: [0xff,0x78,0x98,0xe2] +@ CHECK: adds r7, r8, #16711680 @ encoding: [0xff,0x78,0x98,0xe2] +@ CHECK: adds r7, r8, #16711680 @ encoding: [0xff,0x78,0x98,0xe2] +@ CHECK: adds r7, r8, #16711680 @ encoding: [0xff,0x78,0x98,0xe2] +@ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2] +@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2] + +@------------------------------------------------------------------------------ @ AND @------------------------------------------------------------------------------ and r10, r1, #0xf + and r10, r1, $0xf + and r10, r1, 0xf + and r10, r1, -0xf + and r7, r8, #(0xff << 16) + and r7, r8, #-2147483638 + and r7, r8, #42, #2 + and r7, r8, #40, #2 + and r7, r8, $40, $2 + and r7, r8, 40, 2 + and r7, r8, (2 * 20), (1 << 1) and r10, r1, r6 and r10, r1, r6, lsl #10 and r10, r1, r6, lsr #10 @@ -249,6 +352,16 @@ Lforward: @ destination register is optional and r1, #0xf + and r1, $0xf + and r1, 0xf + and r1, -0xf + and r7, #(0xff << 16) + and r7, #-2147483638 + and r7, #42, #2 + and r7, #40, #2 + and r7, $40, $2 + and r7, 40, 2 + and r7, (2 * 20), (1 << 1) and r10, r1 and r10, r1, lsl #10 and r10, r1, lsr #10 @@ -262,6 +375,16 @@ Lforward: and r10, r1, rrx @ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2] +@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2] +@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2] +@ CHECK: bic r10, r1, #14 @ encoding: [0x0e,0xa0,0xc1,0xe3] +@ CHECK: and r7, r8, #16711680 @ encoding: [0xff,0x78,0x08,0xe2] +@ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2] +@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2] @ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0] @ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0] @ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0] @@ -276,6 +399,16 @@ Lforward: @ CHECK: bic r2, r3, #-2147483648 @ encoding: [0x02,0x21,0xc3,0xe3] @ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] +@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] +@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2] +@ CHECK: bic r1, r1, #14 @ encoding: [0x0e,0x10,0xc1,0xe3] +@ CHECK: and r7, r7, #16711680 @ encoding: [0xff,0x78,0x07,0xe2] +@ CHECK: and r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #40, #2 @ encoding: [0x28,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #40, #2 @ encoding: [0x28,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #40, #2 @ encoding: [0x28,0x71,0x07,0xe2] +@ CHECK: and r7, r7, #40, #2 @ encoding: [0x28,0x71,0x07,0xe2] @ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0] @ CHECK: and r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0x0a,0xe0] @ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0] @@ -348,6 +481,16 @@ Lforward: @ BIC @------------------------------------------------------------------------------ bic r10, r1, #0xf + bic r10, r1, $0xf + bic r10, r1, 0xf + bic r10, r1, -0xf + bic r7, r8, #(0xff << 16) + bic r7, r8, #-2147483638 + bic r7, r8, #42, #2 + bic r7, r8, #40, #2 + bic r7, r8, $40, $2 + bic r7, r8, 40, 2 + bic r7, r8, (2 * 20), (1 << 1) bic r10, r1, r6 bic r10, r1, r6, lsl #10 bic r10, r1, r6, lsr #10 @@ -362,6 +505,16 @@ Lforward: @ destination register is optional bic r1, #0xf + bic r1, $0xf + bic r1, 0xf + bic r1, -0xf + bic r7, #(0xff << 16) + bic r7, #-2147483638 + bic r7, #42, #2 + bic r7, #40, #2 + bic r7, $40, $2 + bic r7, 40, 2 + bic r7, (2 * 20), (1 << 1) bic r10, r1 bic r10, r1, lsl #10 bic r10, r1, lsr #10 @@ -375,6 +528,15 @@ Lforward: bic r10, r1, rrx @ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] +@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] +@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] +@ CHECK: and r10, r1, #14 @ encoding: [0x0e,0xa0,0x01,0xe2] +@ CHECK: bic r7, r8, #16711680 @ encoding: [0xff,0x78,0xc8,0xe3] +@ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3] +@ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3] +@ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3] +@ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3] +@ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3] @ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1] @ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1] @ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1] @@ -389,6 +551,16 @@ Lforward: @ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] +@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] +@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3] +@ CHECK: and r1, r1, #14 @ encoding: [0x0e,0x10,0x01,0xe2] +@ CHECK: bic r7, r7, #16711680 @ encoding: [0xff,0x78,0xc7,0xe3] +@ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3] +@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3] @ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1] @ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1] @ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1] @@ -505,6 +677,16 @@ Lforward: @ CMN @------------------------------------------------------------------------------ cmn r1, #0xf + cmn r1, $0xf + cmn r1, 0xf + cmn r1, -0xf + cmn r7, #(0xff << 16) + cmn r7, #-2147483638 + cmn r7, #42, #2 + cmn r7, #40, #2 + cmn r7, $40, $2 + cmn r7, 40, 2 + cmn r7, (20 * 2), (1 << 1) cmn r1, r6 cmn r1, r6, lsl #10 cmn r1, r6, lsr #10 @@ -518,6 +700,16 @@ Lforward: cmn r1, r6, rrx @ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmn r7, #16711680 @ encoding: [0xff,0x08,0x77,0xe3] +@ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3] +@ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3] +@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3] +@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3] +@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3] +@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3] @ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1] @ CHECK: cmn r1, r6, lsl #10 @ encoding: [0x06,0x05,0x71,0xe1] @ CHECK: cmn r1, r6, lsr #10 @ encoding: [0x26,0x05,0x71,0xe1] @@ -534,6 +726,16 @@ Lforward: @ CMP @------------------------------------------------------------------------------ cmp r1, #0xf + cmp r1, $0xf + cmp r1, 0xf + cmp r1, -0xf + cmp r7, #(0xff << 16) + cmp r7, #-2147483638 + cmp r7, #42, #2 + cmp r7, #40, #2 + cmp r7, $40, $2 + cmp r7, 40, 2 + cmp r7, (2 * 20), (1 << 1) cmp r1, r6 cmp r1, r6, lsl #10 cmp r1, r6, lsr #10 @@ -549,6 +751,16 @@ Lforward: cmp lr, #0 @ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] +@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] +@ CHECK: cmp r7, #16711680 @ encoding: [0xff,0x08,0x57,0xe3] +@ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3] +@ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3] +@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3] +@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3] +@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3] +@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3] @ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1] @ CHECK: cmp r1, r6, lsl #10 @ encoding: [0x06,0x05,0x51,0xe1] @ CHECK: cmp r1, r6, lsr #10 @ encoding: [0x26,0x05,0x51,0xe1] @@ -734,6 +946,15 @@ Lforward: @ EOR @------------------------------------------------------------------------------ eor r4, r5, #0xf000 + eor r4, r5, $0xf000 + eor r4, r5, 0xf000 + eor r7, r8, #(0xff << 16) + eor r7, r8, #-2147483638 + eor r7, r8, #42, #2 + eor r7, r8, #40, #2 + eor r7, r8, $40, $2 + eor r7, r8, 40, 2 + eor r7, r8, (20 * 2), (1 << 1) eor r4, r5, r6 eor r4, r5, r6, lsl #5 eor r4, r5, r6, lsr #5 @@ -748,6 +969,15 @@ Lforward: @ destination register is optional eor r5, #0xf000 + eor r5, $0xf000 + eor r5, 0xf000 + eor r7, #(0xff << 16) + eor r7, #-2147483638 + eor r7, #42, #2 + eor r7, #40, #2 + eor r7, $40, $2 + eor r7, 40, 2 + eor r7, (20 * 2), (1 << 1) eor r4, r5 eor r4, r5, lsl #5 eor r4, r5, lsr #5 @@ -761,6 +991,15 @@ Lforward: eor r4, r5, rrx @ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2] +@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2] +@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2] +@ CHECK: eor r7, r8, #16711680 @ encoding: [0xff,0x78,0x28,0xe2] +@ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2] +@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2] @ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0] @ CHECK: eor r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x25,0xe0] @ CHECK: eor r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x25,0xe0] @@ -775,6 +1014,15 @@ Lforward: @ CHECK: eor r5, r5, #61440 @ encoding: [0x0f,0x5a,0x25,0xe2] +@ CHECK: eor r5, r5, #61440 @ encoding: [0x0f,0x5a,0x25,0xe2] +@ CHECK: eor r5, r5, #61440 @ encoding: [0x0f,0x5a,0x25,0xe2] +@ CHECK: eor r7, r7, #16711680 @ encoding: [0xff,0x78,0x27,0xe2] +@ CHECK: eor r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #40, #2 @ encoding: [0x28,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #40, #2 @ encoding: [0x28,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #40, #2 @ encoding: [0x28,0x71,0x27,0xe2] +@ CHECK: eor r7, r7, #40, #2 @ encoding: [0x28,0x71,0x27,0xe2] @ CHECK: eor r4, r4, r5 @ encoding: [0x05,0x40,0x24,0xe0] @ CHECK: eor r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x24,0xe0] @ CHECK: eor r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x24,0xe0] @@ -1028,8 +1276,23 @@ Lforward: @ MOV (immediate) @------------------------------------------------------------------------------ mov r3, #7 + mov r3, $7 + mov r3, 7 + mov r3, -7 mov r4, #0xff0 mov r5, #0xff0000 + mov r7, #42, #0 + mov r7, #42, #10 + mov r7, #(0xff << 16) + mov r7, #-2147483638 + mov r7, #42, #2 + mov pc, #42, #2 + mov r7, #0, #2 + mov r7, #40, #2 + mov r7, $40, $2 + mov r7, 40, 2 + mov r7, (2 * 20), (1 << 1) + mov r7, #42, #30 mov r6, #0xffff movw r9, #0xffff movs r3, #7 @@ -1037,8 +1300,23 @@ Lforward: movseq r5, #0xff0000 @ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] +@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] +@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] +@ CHECK: mvn r3, #6 @ encoding: [0x06,0x30,0xe0,0xe3] @ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3] @ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3] +@ CHECK: mov r7, #42 @ encoding: [0x2a,0x70,0xa0,0xe3] +@ CHECK: mov r7, #176160768 @ encoding: [0x2a,0x75,0xa0,0xe3] +@ CHECK: mov r7, #16711680 @ encoding: [0xff,0x78,0xa0,0xe3] +@ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3] +@ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3] +@ CHECK: mov pc, #2147483658 @ encoding: [0x2a,0xf1,0xa0,0xe3] +@ CHECK: mov r7, #0, #2 @ encoding: [0x00,0x71,0xa0,0xe3] +@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3] +@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3] +@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3] +@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3] +@ CHECK: mov r7, #42, #30 @ encoding: [0x2a,0x7f,0xa0,0xe3] @ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3] @ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3] @ CHECK: movs r3, #7 @ encoding: [0x07,0x30,0xb0,0xe3] @@ -1132,6 +1410,8 @@ Lforward: @------------------------------------------------------------------------------ msr apsr, #5 + msr apsr, $5 + msr apsr, 5 msr apsr_g, #5 msr apsr_nzcvq, #5 msr APSR_nzcvq, #5 @@ -1145,8 +1425,17 @@ Lforward: msr spsr_fc, #5 msr SPSR_fsxc, #5 msr cpsr_fsxc, #5 + msr apsr_nzcvqg, #(0xff << 16) + msr APSR_nzcvq, #42, #2 + msr apsr_nzcvqg, #2147483658 + msr SPSR_fsxc, #40, #2 + msr SPSR_fsxc, $40, $2 + msr SPSR_fsxc, 40, 2 + msr SPSR_fsxc, (2 * 20), (1 << 1) @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3] @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] @@ -1160,6 +1449,13 @@ Lforward: @ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3] @ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3] @ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3] +@ CHECK: msr APSR_nzcvqg, #16711680 @ encoding: [0xff,0xf8,0x2c,0xe3] +@ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3] +@ CHECK: msr APSR_nzcvqg, #2147483658 @ encoding: [0x2a,0xf1,0x2c,0xe3] +@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3] +@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3] +@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3] +@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3] msr apsr, r0 msr apsr_g, r0 @@ -1210,15 +1506,35 @@ Lforward: @ MVN (immediate) @------------------------------------------------------------------------------ mvn r3, #7 + mvn r3, $7 + mvn r3, 7 + mvn r3, -7 mvn r4, #0xff0 mvn r5, #0xff0000 + mvn r7, #(0xff << 16) + mvn r7, #-2147483638 + mvn r7, #42, #2 + mvn r7, #40, #2 + mvn r7, $40, $2 + mvn r7, 40, 2 + mvn r7, (2 * 20), (1 << 1) mvns r3, #7 mvneq r4, #0xff0 mvnseq r5, #0xff0000 @ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3] +@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3] +@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3] +@ CHECK: mov r3, #6 @ encoding: [0x06,0x30,0xa0,0xe3] @ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3] @ CHECK: mvn r5, #16711680 @ encoding: [0xff,0x58,0xe0,0xe3] +@ CHECK: mvn r7, #16711680 @ encoding: [0xff,0x78,0xe0,0xe3] +@ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3] +@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3] @ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3] @ CHECK: mvneq r4, #4080 @ encoding: [0xff,0x4e,0xe0,0x03] @ CHECK: mvnseq r5, #16711680 @ encoding: [0xff,0x58,0xf0,0x03] @@ -1285,6 +1601,15 @@ Lforward: @ ORR @------------------------------------------------------------------------------ orr r4, r5, #0xf000 + orr r4, r5, $0xf000 + orr r4, r5, 0xf000 + orr r7, r8, #(0xff << 16) + orr r7, r8, #-2147483638 + orr r7, r8, #42, #2 + orr r7, r8, #40, #2 + orr r7, r8, $40, $2 + orr r7, r8, 40, 2 + orr r7, r8, (2 * 20), (1 << 1) orr r4, r5, r6 orr r4, r5, r6, lsl #5 orr r4, r5, r6, lsr #5 @@ -1299,6 +1624,17 @@ Lforward: @ destination register is optional orr r5, #0xf000 + orr r5, $0xf000 + orr r5, 0xf000 + + orr r7, #(0xff << 16) + orr r7, #-2147483638 + orr r7, #42, #2 + orr r7, #40, #2 + orr r7, $40, $2 + orr r7, 40, 2 + orr r7, (2 * 20), (1 << 1) + orr r4, r5 orr r4, r5, lsl #5 orr r4, r5, lsr #5 @@ -1312,6 +1648,15 @@ Lforward: orr r4, r5, rrx @ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3] +@ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3] +@ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3] +@ CHECK: orr r7, r8, #16711680 @ encoding: [0xff,0x78,0x88,0xe3] +@ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3] +@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3] @ CHECK: orr r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe1] @ CHECK: orr r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe1] @ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1] @@ -1325,6 +1670,15 @@ Lforward: @ CHECK: orr r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe1] @ CHECK: orr r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe3] +@ CHECK: orr r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe3] +@ CHECK: orr r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe3] +@ CHECK: orr r7, r7, #16711680 @ encoding: [0xff,0x78,0x87,0xe3] +@ CHECK: orr r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe3] +@ CHECK: orr r7, r7, #40, #2 @ encoding: [0x28,0x71,0x87,0xe3] @ CHECK: orr r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe1] @ CHECK: orr r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe1] @ CHECK: orr r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe1] @@ -1570,6 +1924,15 @@ Lforward: @ RSB @------------------------------------------------------------------------------ rsb r4, r5, #0xf000 + rsb r4, r5, $0xf000 + rsb r4, r5, 0xf000 + rsb r7, r8, #(0xff << 16) + rsb r7, r8, #-2147483638 + rsb r7, r8, #42, #2 + rsb r7, r8, #40, #2 + rsb r7, r8, $40, $2 + rsb r7, r8, 40, 2 + rsb r7, r8, (2 * 20), (1 << 1) rsb r4, r5, r6 rsb r4, r5, r6, lsl #5 rsblo r4, r5, r6, lsr #5 @@ -1584,6 +1947,15 @@ Lforward: @ destination register is optional rsb r5, #0xf000 + rsb r5, $0xf000 + rsb r5, 0xf000 + rsb r7, #(0xff << 16) + rsb r7, #-2147483638 + rsb r7, #42, #2 + rsb r7, #40, #2 + rsb r7, $40, $2 + rsb r7, 40, 2 + rsb r7, (2 * 20), (1 << 1) rsb r4, r5 rsb r4, r5, lsl #5 rsb r4, r5, lsr #5 @@ -1597,6 +1969,15 @@ Lforward: rsb r4, r5, rrx @ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2] +@ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2] +@ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2] +@ CHECK: rsb r7, r8, #16711680 @ encoding: [0xff,0x78,0x68,0xe2] +@ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2] +@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2] @ CHECK: rsb r4, r5, r6 @ encoding: [0x06,0x40,0x65,0xe0] @ CHECK: rsb r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x65,0xe0] @ CHECK: rsblo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0x30] @@ -1610,6 +1991,15 @@ Lforward: @ CHECK: rsb r4, r5, r6, rrx @ encoding: [0x66,0x40,0x65,0xe0] @ CHECK: rsb r5, r5, #61440 @ encoding: [0x0f,0x5a,0x65,0xe2] +@ CHECK: rsb r5, r5, #61440 @ encoding: [0x0f,0x5a,0x65,0xe2] +@ CHECK: rsb r5, r5, #61440 @ encoding: [0x0f,0x5a,0x65,0xe2] +@ CHECK: rsb r7, r7, #16711680 @ encoding: [0xff,0x78,0x67,0xe2] +@ CHECK: rsb r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #40, #2 @ encoding: [0x28,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #40, #2 @ encoding: [0x28,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #40, #2 @ encoding: [0x28,0x71,0x67,0xe2] +@ CHECK: rsb r7, r7, #40, #2 @ encoding: [0x28,0x71,0x67,0xe2] @ CHECK: rsb r4, r4, r5 @ encoding: [0x05,0x40,0x64,0xe0] @ CHECK: rsb r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x64,0xe0] @ CHECK: rsb r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x64,0xe0] @@ -1623,9 +2013,43 @@ Lforward: @ CHECK: rsb r4, r4, r5, rrx @ encoding: [0x65,0x40,0x64,0xe0] @------------------------------------------------------------------------------ +@ RSBS +@------------------------------------------------------------------------------ + rsbs r7, #16711680 + rsbs r7, $16711680 + rsbs r7, 16711680 + rsbs r7, #(0xff << 16) + rsbs r7, r8, #-2147483638 + rsbs r7, r8, #42, #2 + rsbs r7, r8, #40, #2 + rsbs r7, r8, $40, $2 + rsbs r7, r8, 40, 2 + rsbs r7, r8, (2 * 20), (1 << 1) + +@ CHECK: rsbs r7, r7, #16711680 @ encoding: [0xff,0x78,0x77,0xe2] +@ CHECK: rsbs r7, r7, #16711680 @ encoding: [0xff,0x78,0x77,0xe2] +@ CHECK: rsbs r7, r7, #16711680 @ encoding: [0xff,0x78,0x77,0xe2] +@ CHECK: rsbs r7, r7, #16711680 @ encoding: [0xff,0x78,0x77,0xe2] +@ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2] +@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2] + +@------------------------------------------------------------------------------ @ RSC @------------------------------------------------------------------------------ rsc r4, r5, #0xf000 + rsc r4, r5, $0xf000 + rsc r4, r5, 0xf000 + rsc r7, r8, #(0xff << 16) + rsc r7, r8, #-2147483638 + rsc r7, r8, #42, #2 + rsc r7, r8, #40, #2 + rsc r7, r8, $40, $2 + rsc r7, r8, 40, 2 + rsc r7, r8, (2 * 20), (1 << 1) rsc r4, r5, r6 rsc r4, r5, r6, lsl #5 rsclo r4, r5, r6, lsr #5 @@ -1640,6 +2064,15 @@ Lforward: @ destination register is optional rsc r5, #0xf000 + rsc r5, $0xf000 + rsc r5, 0xf000 + rsc r7, #(0xff << 16) + rsc r7, #-2147483638 + rsc r7, #42, #2 + rsc r7, #40, #2 + rsc r7, $40, $2 + rsc r7, 40, 2 + rsc r7, (2 * 20), (1 << 1) rsc r4, r5 rsc r4, r5, lsl #5 rsc r4, r5, lsr #5 @@ -1652,6 +2085,15 @@ Lforward: rsc r6, r7, ror r9 @ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2] +@ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2] +@ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2] +@ CHECK: rsc r7, r8, #16711680 @ encoding: [0xff,0x78,0xe8,0xe2] +@ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2] +@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2] @ CHECK: rsc r4, r5, r6 @ encoding: [0x06,0x40,0xe5,0xe0] @ CHECK: rsc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xe5,0xe0] @ CHECK: rsclo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0x30] @@ -1665,6 +2107,15 @@ Lforward: @ CHECK: rscs r1, r8, #4064 @ encoding: [0xfe,0x1e,0xf8,0xe2] @ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2] +@ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2] +@ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2] +@ CHECK: rsc r7, r7, #16711680 @ encoding: [0xff,0x78,0xe7,0xe2] +@ CHECK: rsc r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xe7,0xe2] +@ CHECK: rsc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xe7,0xe2] @ CHECK: rsc r4, r4, r5 @ encoding: [0x05,0x40,0xe4,0xe0] @ CHECK: rsc r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0xe4,0xe0] @ CHECK: rsc r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xe4,0xe0] @@ -1728,6 +2179,15 @@ Lforward: @ SBC @------------------------------------------------------------------------------ sbc r4, r5, #0xf000 + sbc r4, r5, $0xf000 + sbc r4, r5, 0xf000 + sbc r7, r8, #(0xff << 16) + sbc r7, r8, #-2147483638 + sbc r7, r8, #42, #2 + sbc r7, r8, #40, #2 + sbc r7, r8, $40, $2 + sbc r7, r8, 40, 2 + sbc r7, r8, (20 * 2), (1 << 1) sbc r4, r5, r6 sbc r4, r5, r6, lsl #5 sbc r4, r5, r6, lsr #5 @@ -1741,6 +2201,15 @@ Lforward: @ destination register is optional sbc r5, #0xf000 + sbc r5, $0xf000 + sbc r5, 0xf000 + sbc r7, #(0xff << 16) + sbc r7, #-2147483638 + sbc r7, #42, #2 + sbc r7, #40, #2 + sbc r7, $40, $2 + sbc r7, 40, 2 + sbc r7, (20 * 2), (1 << 1) sbc r4, r5 sbc r4, r5, lsl #5 sbc r4, r5, lsr #5 @@ -1753,6 +2222,15 @@ Lforward: sbc r6, r7, ror r9 @ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2] +@ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2] +@ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2] +@ CHECK: sbc r7, r8, #16711680 @ encoding: [0xff,0x78,0xc8,0xe2] +@ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2] +@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2] @ CHECK: sbc r4, r5, r6 @ encoding: [0x06,0x40,0xc5,0xe0] @ CHECK: sbc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xc5,0xe0] @ CHECK: sbc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xc5,0xe0] @@ -1765,6 +2243,15 @@ Lforward: @ CHECK: sbc r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xc7,0xe0] @ CHECK: sbc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xc5,0xe2] +@ CHECK: sbc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xc5,0xe2] +@ CHECK: sbc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xc5,0xe2] +@ CHECK: sbc r7, r7, #16711680 @ encoding: [0xff,0x78,0xc7,0xe2] +@ CHECK: sbc r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe2] +@ CHECK: sbc r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe2] @ CHECK: sbc r4, r4, r5 @ encoding: [0x05,0x40,0xc4,0xe0] @ CHECK: sbc r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0xc4,0xe0] @ CHECK: sbc r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xc4,0xe0] @@ -2383,6 +2870,15 @@ Lforward: @ SUB @------------------------------------------------------------------------------ sub r4, r5, #0xf000 + sub r4, r5, $0xf000 + sub r4, r5, 0xf000 + sub r7, r8, #(0xff << 16) + sub r7, r8, #-2147483638 + sub r7, r8, #42, #2 + sub r7, r8, #40, #2 + sub r7, r8, $40, $2 + sub r7, r8, 40, 2 + sub r7, r8, (20 * 2), (1 << 1) sub r4, r5, r6 sub r4, r5, r6, lsl #5 sub r4, r5, r6, lsr #5 @@ -2396,6 +2892,15 @@ Lforward: @ destination register is optional sub r5, #0xf000 + sub r5, $0xf000 + sub r5, 0xf000 + sub r7, #(0xff << 16) + sub r7, #-2147483638 + sub r7, #42, #2 + sub r7, #40, #2 + sub r7, $40, $2 + sub r7, 40, 2 + sub r7, (20 * 2), (1 << 1) sub r4, r5 sub r4, r5, lsl #5 sub r4, r5, lsr #5 @@ -2408,6 +2913,15 @@ Lforward: sub r6, r7, ror r9 @ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: sub r7, r8, #16711680 @ encoding: [0xff,0x78,0x48,0xe2] +@ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2] +@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2] @ CHECK: sub r4, r5, r6 @ encoding: [0x06,0x40,0x45,0xe0] @ CHECK: sub r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x45,0xe0] @ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0] @@ -2421,6 +2935,15 @@ Lforward: @ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: sub r7, r7, #16711680 @ encoding: [0xff,0x78,0x47,0xe2] +@ CHECK: sub r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x47,0xe2] +@ CHECK: sub r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0x47,0xe2] +@ CHECK: sub r7, r7, #40, #2 @ encoding: [0x28,0x71,0x47,0xe2] +@ CHECK: sub r7, r7, #40, #2 @ encoding: [0x28,0x71,0x47,0xe2 +@ CHECK: sub r7, r7, #40, #2 @ encoding: [0x28,0x71,0x47,0xe2] +@ CHECK: sub r7, r7, #40, #2 @ encoding: [0x28,0x71,0x47,0xe2] @ CHECK: sub r4, r4, r5 @ encoding: [0x05,0x40,0x44,0xe0] @ CHECK: sub r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x44,0xe0] @ CHECK: sub r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x44,0xe0] @@ -2439,6 +2962,31 @@ Lforward: @ CHECK: sub r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x41,0xe0] @------------------------------------------------------------------------------ +@ SUBS +@------------------------------------------------------------------------------ + subs r7, r8, #16711680 + subs r7, r8, $16711680 + subs r7, r8, 16711680 + subs r7, r8, #(0xff << 16) + subs r7, r8, #-2147483638 + subs r7, r8, #42, #2 + subs r7, r8, #40, #2 + subs r7, r8, $40, $2 + subs r7, r8, 40, 2 + subs r7, r8, (20 * 2), (1 << 1) + +@ CHECK: subs r7, r8, #16711680 @ encoding: [0xff,0x78,0x58,0xe2] +@ CHECK: subs r7, r8, #16711680 @ encoding: [0xff,0x78,0x58,0xe2] +@ CHECK: subs r7, r8, #16711680 @ encoding: [0xff,0x78,0x58,0xe2] +@ CHECK: subs r7, r8, #16711680 @ encoding: [0xff,0x78,0x58,0xe2] +@ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2] +@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2] + +@------------------------------------------------------------------------------ @ SVC @------------------------------------------------------------------------------ svc #16 @@ -2560,6 +3108,15 @@ Lforward: @ TEQ @------------------------------------------------------------------------------ teq r5, #0xf000 + teq r5, $0xf000 + teq r5, 0xf000 + teq r7, #(0xff << 16) + teq r7, #-2147483638 + teq r7, #42, #2 + teq r7, #40, #2 + teq r7, $40, $2 + teq r7, 40, 2 + teq r7, (20 * 2), (1 << 1) teq r4, r5 teq r4, r5, lsl #5 teq r4, r5, lsr #5 @@ -2572,6 +3129,15 @@ Lforward: teq r6, r7, ror r9 @ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r7, #16711680 @ encoding: [0xff,0x08,0x37,0xe3] +@ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3] +@ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3] +@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3] +@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3] +@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3] +@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3] @ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1] @ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1] @ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1] @@ -2588,6 +3154,15 @@ Lforward: @ TST @------------------------------------------------------------------------------ tst r5, #0xf000 + tst r5, $0xf000 + tst r5, 0xf000 + tst r7, #(0xff << 16) + tst r7, #-2147483638 + tst r7, #42, #2 + tst r7, #40, #2 + tst r7, $40, $2 + tst r7, 40, 2 + tst r7, (20 * 2), (1 << 1) tst r4, r5 tst r4, r5, lsl #5 tst r4, r5, lsr #5 @@ -2600,6 +3175,15 @@ Lforward: tst r6, r7, ror r9 @ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3] +@ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3] +@ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3] +@ CHECK: tst r7, #16711680 @ encoding: [0xff,0x08,0x17,0xe3] +@ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3] +@ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3] +@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3] +@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3] +@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3] +@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3] @ CHECK: tst r4, r5 @ encoding: [0x05,0x00,0x14,0xe1] @ CHECK: tst r4, r5, lsl #5 @ encoding: [0x85,0x02,0x14,0xe1] @ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1] diff --git a/test/MC/ARM/coff-debugging-secrel.ll b/test/MC/ARM/coff-debugging-secrel.ll index f37b19e6a70c..7323fc6828bb 100644 --- a/test/MC/ARM/coff-debugging-secrel.ll +++ b/test/MC/ARM/coff-debugging-secrel.ll @@ -16,17 +16,17 @@ entry: !llvm.dbg.cu = !{!7} !llvm.module.flags = !{!9, !10} -!0 = metadata !{i32 1, i32 0, metadata !1, null} -!1 = metadata !{i32 786478, metadata !2, metadata !3, metadata !"function", metadata !"function", metadata !"", i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @function, null, null, metadata !6, i32 1} ; [ DW_TAG_subprogram ], [line 1], [def], [function] -!2 = metadata !{metadata !"/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", metadata !"/Users/compnerd/work/llvm"} -!3 = metadata !{i32 786473, metadata !2} ; [ DW_TAG_file_type] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] -!4 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ], [line 0, size 0, align 0, offset 0] [from ] -!5 = metadata !{null} -!6 = metadata !{} -!7 = metadata !{i32 786449, metadata !2, i32 12, metadata !"clang version 3.5.0", i1 false, metadata !"", i32 0, metadata !6, metadata !6, metadata !8, metadata !6, metadata !6, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] [DW_LANG_C99] -!8 = metadata !{metadata !1} -!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!0 = !MDLocation(line: 1, scope: !1) +!1 = !{!"0x2e\00function\00function\00\001\000\001\000\006\000\000\001", !2, !3, !4, null, void ()* @function, null, null, !6} ; [ DW_TAG_subprogram ], [line 1], [def], [function] +!2 = !{!"/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", !"/Users/compnerd/work/llvm"} +!3 = !{!"0x29", !2} ; [ DW_TAG_file_type] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] +!4 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ], [line 0, size 0, align 0, offset 0] [from ] +!5 = !{null} +!6 = !{} +!7 = !{!"0x11\0012\00clang version 3.5.0\000\00\000\00\001", !2, !6, !6, !8, !6, !6} ; [ DW_TAG_compile_unit ] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] [DW_LANG_C99] +!8 = !{!1} +!9 = !{i32 2, !"Dwarf Version", i32 4} +!10 = !{i32 1, !"Debug Info Version", i32 2} ; CHECK-ITANIUM: Relocations [ ; CHECK-ITANIUM: Section {{.*}} .debug_info { @@ -42,8 +42,10 @@ entry: ; CHECK-MSVC: Relocations [ ; CHECK-MSVC: Section {{.*}} .debug$S { -; CHECK-MSVC: 0xC IMAGE_REL_ARM_SECREL function -; CHECK-MSVC: 0x10 IMAGE_REL_ARM_SECTION function +; CHECK-MSVC: 0x2C IMAGE_REL_ARM_SECREL function +; CHECK-MSVC: 0x30 IMAGE_REL_ARM_SECTION function +; CHECK-MSVC: 0x48 IMAGE_REL_ARM_SECREL function +; CHECK-MSVC: 0x4C IMAGE_REL_ARM_SECTION function ; CHECK-MSVC: } ; CHECK-MSVC: ] diff --git a/test/MC/ARM/coff-file.s b/test/MC/ARM/coff-file.s index f0dd29a29256..d3f26f4c8f7c 100644 --- a/test/MC/ARM/coff-file.s +++ b/test/MC/ARM/coff-file.s @@ -21,7 +21,7 @@ // CHECK-SCN: Symbols [ // CHECK-SCN: Symbol { // CHECK-SCN: Name: .file -// CHECK-SCN: Section: (65534) +// CHECK-SCN: Section: IMAGE_SYM_DEBUG (-2) // CHECK-SCN: StorageClass: File // CHECK-SCN: AuxFileRecord { // CHECK-SCN: FileName: null-padded.asm @@ -29,7 +29,7 @@ // CHECK-SCN: } // CHECK-SCN: Symbol { // CHECK-SCN: Name: .file -// CHECK-SCN: Section: (65534) +// CHECK-SCN: Section: IMAGE_SYM_DEBUG (-2) // CHECK-SCN: StorageClass: File // CHECK-SCN: AuxFileRecord { // CHECK-SCN: FileName: eighteen-chars.asm @@ -37,7 +37,7 @@ // CHECK-SCN: } // CHECK-SCN: Symbol { // CHECK-SCN: Name: .file -// CHECK-SCN: Section: (65534) +// CHECK-SCN: Section: IMAGE_SYM_DEBUG (-2) // CHECK-SCN: StorageClass: File // CHECK-SCN: AuxFileRecord { // CHECK-SCN: FileName: multiple-auxiliary-entries.asm diff --git a/test/MC/ARM/coproc-diag.s b/test/MC/ARM/coproc-diag.s new file mode 100644 index 000000000000..c96f2db6b6e1 --- /dev/null +++ b/test/MC/ARM/coproc-diag.s @@ -0,0 +1,10 @@ +# Special test to make sure we don't error on VFP co-proc access +@ RUN: llvm-mc -triple=armv5 < %s | FileCheck %s +@ RUN: llvm-mc -triple=armv6 < %s | FileCheck %s + + @ p10 and p11 are reserved for NEON, but accessible on v5/v6 + ldc p10, cr0, [r0], {0x20} + ldc2 p11, cr0, [r0], {0x21} + ldcl p11, cr0, [r0], {0x20} + +@ CHECK-NOT: error: invalid operand for instruction diff --git a/test/MC/ARM/cps.s b/test/MC/ARM/cps.s new file mode 100644 index 000000000000..a848b22d9876 --- /dev/null +++ b/test/MC/ARM/cps.s @@ -0,0 +1,17 @@ +@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF + + cpsie f + cpsie i, #3 + cps #0 + +@ CHECK: cpsie f @ encoding: [0x61,0xb6] +@ CHECK: cpsie i, #3 @ encoding: [0xaf,0xf3,0x43,0x85] +@ CHECK: cps #0 @ encoding: [0xaf,0xf3,0x00,0x81] + +@ UNDEF-DAG: cpsie f @ encoding: [0x61,0xb6] +@ UNDEF-DAG: error: instruction requires: +@ UNDEF-DAG: error: instruction 'cps' requires effect for M-class diff --git a/test/MC/ARM/cpu-test.s b/test/MC/ARM/cpu-test.s new file mode 100644 index 000000000000..766e454d080a --- /dev/null +++ b/test/MC/ARM/cpu-test.s @@ -0,0 +1,13 @@ +// RUN: not llvm-mc -o - -triple arm-gnueabi-freebsd11.0 < %s > %t 2> %t2 +// RUN: FileCheck %s < %t +// RUN: FileCheck %s --check-prefix=CHECK-ERROR < %t2 + +// CHECK: .cpu cortex-a8 +.cpu cortex-a8 +// CHECK: dsb sy +dsb +.cpu arm9 +// CHECK-ERROR: error: instruction requires: data-barriers +dsb +// CHECK-ERROR: error: Unknown CPU name +.cpu foobar diff --git a/test/MC/ARM/d16.s b/test/MC/ARM/d16.s new file mode 100644 index 000000000000..aa549a3d7ca1 --- /dev/null +++ b/test/MC/ARM/d16.s @@ -0,0 +1,24 @@ +@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32 +@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,+d16 2>&1 | FileCheck %s --check-prefix=D16 + +@ D32-NOT: error: + +@ D16: invalid operand for instruction +@ D16-NEXT: vadd.f64 d1, d2, d16 +vadd.f64 d1, d2, d16 + +@ D16: invalid operand for instruction +@ D16-NEXT: vadd.f64 d1, d17, d6 +vadd.f64 d1, d17, d6 + +@ D16: invalid operand for instruction +@ D16-NEXT: vadd.f64 d19, d7, d6 +vadd.f64 d19, d7, d6 + +@ D16: invalid operand for instruction +@ D16-NEXT: vcvt.f64.f32 d22, s4 +vcvt.f64.f32 d22, s4 + +@ D16: invalid operand for instruction +@ D16-NEXT: vcvt.f32.f64 s26, d30 +vcvt.f32.f64 s26, d30 diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 88c5fb5b688a..6f66dc3b4d0a 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -491,3 +491,213 @@ foo2: @ CHECK-ERRORS: ^ @ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 @ CHECK-ERRORS: ^ + + str r0, [r0, #4]! + str r0, [r0, r1]! + str r0, [r0], #4 + str r0, [r0], r1 + strh r0, [r0, #2]! + strh r0, [r0, r1]! + strh r0, [r0], #2 + strh r0, [r0], r1 + strb r0, [r0, #1]! + strb r0, [r0, r1]! + strb r0, [r0], #1 + strb r0, [r0], r1 +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0, #4]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0], #4 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strh r0, [r0, #2]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strh r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strh r0, [r0], #2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strh r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strb r0, [r0, #1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strb r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strb r0, [r0], #1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strb r0, [r0], r1 +@ CHECK-ERRORS: ^ + + ldr r0, [r0, #4]! + ldr r0, [r0, r1]! + ldr r0, [r0], #4 + ldr r0, [r0], r1 + ldrh r0, [r0, #2]! + ldrh r0, [r0, r1]! + ldrh r0, [r0], #2 + ldrh r0, [r0], r1 + ldrsh r0, [r0, #2]! + ldrsh r0, [r0, r1]! + ldrsh r0, [r0], #2 + ldrsh r0, [r0], r1 + ldrb r0, [r0, #1]! + ldrb r0, [r0, r1]! + ldrb r0, [r0], #1 + ldrb r0, [r0], r1 + ldrsb r0, [r0, #1]! + ldrsb r0, [r0, r1]! + ldrsb r0, [r0], #1 + ldrsb r0, [r0], r1 +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldr r0, [r0, #4]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldr r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldr r0, [r0], #4 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldr r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrh r0, [r0, #2]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrh r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrh r0, [r0], #2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrh r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsh r0, [r0, #2]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsh r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsh r0, [r0], #2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsh r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrb r0, [r0, #1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrb r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrb r0, [r0], #1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrb r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsb r0, [r0, #1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsb r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsb r0, [r0], #1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsb r0, [r0], r1 +@ CHECK-ERRORS: ^ + + @ Out of range modified immediate values + mov r5, #-256, #6 + mov r6, #42, #7 + mvn r5, #256, #6 + mvn r6, #42, #298 + cmp r5, #65535, #6 + cmp r6, #42, #31 + cmn r5, #-1, #6 + cmn r6, #42, #32 + msr APSR_nzcvq, #-128, #2 + msr apsr_nzcvqg, #0, #1 + adc r7, r8, #-256, #2 + adc r7, r8, #128, #1 + sbc r7, r8, #-256, #2 + sbc r7, r8, #128, #1 + add r7, r8, #-2149, #0 + add r7, r8, #100, #1 + sub r7, r8, #-2149, #0 + sub r7, r8, #100, #1 + and r7, r8, #-2149, #0 + and r7, r8, #100, #1 + orr r7, r8, #-2149, #0 + orr r7, r8, #100, #1 + eor r7, r8, #-2149, #0 + eor r7, r8, #100, #1 + bic r7, r8, #-2149, #0 + bic r7, r8, #100, #1 + rsb r7, r8, #-2149, #0 + rsb r7, r8, #100, #1 + adds r7, r8, #-2149, #0 + adds r7, r8, #100, #1 + subs r7, r8, #-2149, #0 + subs r7, r8, #100, #1 + rsbs r7, r8, #-2149, #0 + rsbs r7, r8, #100, #1 + rsc r7, r8, #-2149, #0 + rsc r7, r8, #100, #1 + TST r7, #-2149, #0 + TST r7, #100, #1 + TEQ r7, #-2149, #0 + TEQ r7, #100, #1 +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] +@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255] +@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30] diff --git a/test/MC/ARM/directive-arch-iwmmxt.s b/test/MC/ARM/directive-arch-iwmmxt.s index db25ec683fe5..c54846dbcc20 100644 --- a/test/MC/ARM/directive-arch-iwmmxt.s +++ b/test/MC/ARM/directive-arch-iwmmxt.s @@ -16,7 +16,7 @@ @ CHECK-ATTR: FileAttributes { @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_name -@ CHECK-ATTR: Value: IWMMXT +@ CHECK-ATTR: Value: iwmmxt @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_arch diff --git a/test/MC/ARM/directive-arch-iwmmxt2.s b/test/MC/ARM/directive-arch-iwmmxt2.s index de94f97b449e..a4e59b5ba277 100644 --- a/test/MC/ARM/directive-arch-iwmmxt2.s +++ b/test/MC/ARM/directive-arch-iwmmxt2.s @@ -16,7 +16,7 @@ @ CHECK-ATTR: FileAttributes { @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_name -@ CHECK-ATTR: Value: IWMMXT2 +@ CHECK-ATTR: Value: iwmmxt2 @ CHECK-ATTR: } @ CHECK-ATTR: Attribute { @ CHECK-ATTR: TagName: CPU_arch diff --git a/test/MC/ARM/directive-arch_extension-crc.s b/test/MC/ARM/directive-arch_extension-crc.s index 9e4dedabca48..1359b1f649ac 100644 --- a/test/MC/ARM/directive-arch_extension-crc.s +++ b/test/MC/ARM/directive-arch_extension-crc.s @@ -37,21 +37,21 @@ crc: nocrc: crc32b r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32h r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32w r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32cb r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32ch r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32cw r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc diff --git a/test/MC/ARM/directive-arch_extension-fp.s b/test/MC/ARM/directive-arch_extension-fp.s index 0327dd74337e..f2b4dc2c4122 100644 --- a/test/MC/ARM/directive-arch_extension-fp.s +++ b/test/MC/ARM/directive-arch_extension-fp.s @@ -1,11 +1,11 @@ @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V8 +@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V8 +@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK .syntax unified @@ -153,192 +153,131 @@ fp: .type nofp,%function nofp: vmrs r0, mvfr2 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselgt.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselge.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vseleq.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselvs.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vmaxnm.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselgt.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselge.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vseleq.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselvs.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vmaxnm.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtb.f64.f16 d0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtb.f16.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtt.f64.f16 d0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtt.f16.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 diff --git a/test/MC/ARM/directive-arch_extension-idiv.s b/test/MC/ARM/directive-arch_extension-idiv.s index c63bbfbb4cab..88614ea55db5 100644 --- a/test/MC/ARM/directive-arch_extension-idiv.s +++ b/test/MC/ARM/directive-arch_extension-idiv.s @@ -43,11 +43,11 @@ noidiv: udiv r0, r1, r2 @ CHECK-ARMv6: error: instruction requires: divide in ARM @ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode -@ CHECK-ARMv7: error: instruction requires: divide in ARM arm-mode +@ CHECK-ARMv7: error: instruction requires: divide in ARM @ CHECK-THUMBv7: error: instruction requires: divide in THUMB sdiv r0, r1, r2 @ CHECK-ARMv6: error: instruction requires: divide in ARM @ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode -@ CHECK-ARMv7: error: instruction requires: divide in ARM arm-mode +@ CHECK-ARMv7: error: instruction requires: divide in ARM @ CHECK-THUMBv7: error: instruction requires: divide in THUMB diff --git a/test/MC/ARM/directive-arch_extension-mode-switch.s b/test/MC/ARM/directive-arch_extension-mode-switch.s new file mode 100644 index 000000000000..7e4159f2e8f4 --- /dev/null +++ b/test/MC/ARM/directive-arch_extension-mode-switch.s @@ -0,0 +1,17 @@ +@ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null %s 2>&1 | FileCheck %s + +@ Ensure that a mode switch does not revert the architectural features that were +@ alternated explicitly. + + .syntax unified + + .arch_extension noidiv + + .arm + udiv r0, r0, r1 +@ CHECK: instruction requires: divide in ARM + + .thumb + udiv r0, r0, r1 +@ CHECK: instruction requires: divide in THUMB + diff --git a/test/MC/ARM/directive-arch_extension-simd.s b/test/MC/ARM/directive-arch_extension-simd.s index c9dbf21541c1..14359c645229 100644 --- a/test/MC/ARM/directive-arch_extension-simd.s +++ b/test/MC/ARM/directive-arch_extension-simd.s @@ -1,11 +1,11 @@ @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V8 +@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V8 +@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK .syntax unified @@ -125,151 +125,103 @@ simd: .type nosimd,%function nosimd: vmaxnm.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vmaxnm.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 diff --git a/test/MC/ARM/directive-arch_extension-toggle.s b/test/MC/ARM/directive-arch_extension-toggle.s new file mode 100644 index 000000000000..c3fb901cad47 --- /dev/null +++ b/test/MC/ARM/directive-arch_extension-toggle.s @@ -0,0 +1,8 @@ +@ RUN: llvm-mc -triple armv7-eabi -mattr hwdiv -filetype asm -o /dev/null %s + + .syntax unified + .thumb + + udiv r0, r1, r2 + .arch_extension idiv + udiv r0, r1, r2 diff --git a/test/MC/ARM/directive-cpu.s b/test/MC/ARM/directive-cpu.s index 952dd93f370c..d81a03e5e299 100644 --- a/test/MC/ARM/directive-cpu.s +++ b/test/MC/ARM/directive-cpu.s @@ -20,7 +20,6 @@ @ CHECK: 10000000 .cpu cortex-a8 -@ CHECK: 05 -@ CHECK: 434F52 5445582D 413800 +@ CHECK: 05636F72 7465782D 613800 @ CHECK: ) diff --git a/test/MC/ARM/directive-eabi_attribute-2.s b/test/MC/ARM/directive-eabi_attribute-2.s deleted file mode 100644 index 8f00ac807802..000000000000 --- a/test/MC/ARM/directive-eabi_attribute-2.s +++ /dev/null @@ -1,98 +0,0 @@ -@ RUN: llvm-mc -triple armv7-elf -filetype asm -o - %s | FileCheck %s - - .syntax unified - .thumb - - .eabi_attribute Tag_CPU_raw_name, "Cortex-A9" -@ CHECK: .eabi_attribute 4, "Cortex-A9" - .eabi_attribute Tag_CPU_name, "cortex-a9" -@ CHECK: .cpu cortex-a9 - .eabi_attribute Tag_CPU_arch, 10 -@ CHECK: .eabi_attribute 6, 10 - .eabi_attribute Tag_CPU_arch_profile, 'A' -@ CHECK: .eabi_attribute 7, 65 - .eabi_attribute Tag_ARM_ISA_use, 0 -@ CHECK: .eabi_attribute 8, 0 - .eabi_attribute Tag_THUMB_ISA_use, 2 -@ CHECK: .eabi_attribute 9, 2 - .eabi_attribute Tag_FP_arch, 3 -@ CHECK: .eabi_attribute 10, 3 - .eabi_attribute Tag_WMMX_arch, 0 -@ CHECK: .eabi_attribute 11, 0 - .eabi_attribute Tag_Advanced_SIMD_arch, 1 -@ CHECK: .eabi_attribute 12, 1 - .eabi_attribute Tag_PCS_config, 2 -@ CHECK: .eabi_attribute 13, 2 - .eabi_attribute Tag_ABI_PCS_R9_use, 0 -@ CHECK: .eabi_attribute 14, 0 - .eabi_attribute Tag_ABI_PCS_RW_data, 0 -@ CHECK: .eabi_attribute 15, 0 - .eabi_attribute Tag_ABI_PCS_RO_data, 0 -@ CHECK: .eabi_attribute 16, 0 - .eabi_attribute Tag_ABI_PCS_GOT_use, 0 -@ CHECK: .eabi_attribute 17, 0 - .eabi_attribute Tag_ABI_PCS_wchar_t, 4 -@ CHECK: .eabi_attribute 18, 4 - .eabi_attribute Tag_ABI_FP_rounding, 1 -@ CHECK: .eabi_attribute 19, 1 - .eabi_attribute Tag_ABI_FP_denormal, 2 -@ CHECK: .eabi_attribute 20, 2 - .eabi_attribute Tag_ABI_FP_exceptions, 1 -@ CHECK: .eabi_attribute 21, 1 - .eabi_attribute Tag_ABI_FP_user_exceptions, 1 -@ CHECK: .eabi_attribute 22, 1 - .eabi_attribute Tag_ABI_FP_number_model, 3 -@ CHECK: .eabi_attribute 23, 3 - .eabi_attribute Tag_ABI_align_needed, 1 -@ CHECK: .eabi_attribute 24, 1 - .eabi_attribute Tag_ABI_align_preserved, 2 -@ CHECK: .eabi_attribute 25, 2 - .eabi_attribute Tag_ABI_enum_size, 3 -@ CHECK: .eabi_attribute 26, 3 - .eabi_attribute Tag_ABI_HardFP_use, 0 -@ CHECK: .eabi_attribute 27, 0 - .eabi_attribute Tag_ABI_VFP_args, 1 -@ CHECK: .eabi_attribute 28, 1 - .eabi_attribute Tag_ABI_WMMX_args, 0 -@ CHECK: .eabi_attribute 29, 0 - .eabi_attribute Tag_ABI_FP_optimization_goals, 1 -@ CHECK: .eabi_attribute 31, 1 - .eabi_attribute Tag_compatibility, 1 -@ CHECK: .eabi_attribute 32, 1 - .eabi_attribute Tag_compatibility, 1, "aeabi" -@ CHECK: .eabi_attribute 32, 1, "aeabi" - .eabi_attribute Tag_CPU_unaligned_access, 0 -@ CHECK: .eabi_attribute 34, 0 - .eabi_attribute Tag_FP_HP_extension, 0 -@ CHECK: .eabi_attribute 36, 0 - .eabi_attribute Tag_ABI_FP_16bit_format, 0 -@ CHECK: .eabi_attribute 38, 0 - .eabi_attribute Tag_MPextension_use, 0 -@ CHECK: .eabi_attribute 42, 0 - .eabi_attribute Tag_DIV_use, 0 -@ CHECK: .eabi_attribute 44, 0 - .eabi_attribute Tag_nodefaults, 0 -@ CHECK: .eabi_attribute 64, 0 - .eabi_attribute Tag_also_compatible_with, "gnu" -@ CHECK: .eabi_attribute 65, "gnu" - .eabi_attribute Tag_T2EE_use, 0 -@ CHECK: .eabi_attribute 66, 0 - .eabi_attribute Tag_conformance, "2.09" -@ CHECK: .eabi_attribute 67, "2.09" - .eabi_attribute Tag_Virtualization_use, 0 -@ CHECK: .eabi_attribute 68, 0 - -@ ===--- Compatibility Checks ---=== - - .eabi_attribute Tag_ABI_align8_needed, 1 -@ CHECK: .eabi_attribute 24, 1 - .eabi_attribute Tag_ABI_align8_preserved, 2 -@ CHECK: .eabi_attribute 25, 2 - -@ ===--- GNU AS Compatibility Checks ---=== - - .eabi_attribute 2 * 2 + 1, "cortex-a9" -@ CHECK: .cpu cortex-a9 - .eabi_attribute 2 * 2 + 2, 5 * 2 -@ CHECK: .eabi_attribute 6, 10 - diff --git a/test/MC/ARM/directive-eabi_attribute-diagnostics.s b/test/MC/ARM/directive-eabi_attribute-diagnostics.s index d1ae352b25f4..2b0375e57613 100644 --- a/test/MC/ARM/directive-eabi_attribute-diagnostics.s +++ b/test/MC/ARM/directive-eabi_attribute-diagnostics.s @@ -29,6 +29,11 @@ @ CHECK: .eabi_attribute 0 @ CHECK: ^ + .eabi_attribute Tag_compatibility, 1 +@ CHECK: error: comma expected +@ CHECK: .eabi_attribute Tag_compatibility, 1 +@ CHECK: ^ + .eabi_attribute Tag_MPextension_use_old, 0 @ CHECK: error: attribute name not recognised: Tag_MPextension_use_old @ CHECK: .eabi_attribute Tag_MPextension_use_old, 0 diff --git a/test/MC/ARM/directive-eabi_attribute-overwrite.s b/test/MC/ARM/directive-eabi_attribute-overwrite.s index 6fdded3d8312..e2c509972754 100644 --- a/test/MC/ARM/directive-eabi_attribute-overwrite.s +++ b/test/MC/ARM/directive-eabi_attribute-overwrite.s @@ -3,13 +3,11 @@ .syntax unified .thumb - - .eabi_attribute Tag_compatibility, 1 .eabi_attribute Tag_compatibility, 1, "aeabi" @ CHECK-ATTR: FileAttributes { @ CHECK-ATTR: Attribute { -@ CHECK-ATTR: Value: 1, AEABI +@ CHECK-ATTR: Value: 1, aeabi @ CHECK-ATTR: TagName: compatibility @ CHECK-ATTR: Description: AEABI Conformant @ CHECK-ATTR: } diff --git a/test/MC/ARM/directive-eabi_attribute.s b/test/MC/ARM/directive-eabi_attribute.s index c060b809c843..74a51ab7279a 100644 --- a/test/MC/ARM/directive-eabi_attribute.s +++ b/test/MC/ARM/directive-eabi_attribute.s @@ -1,56 +1,248 @@ +@ RUN: llvm-mc -triple armv7-elf -filetype asm -o - %s | FileCheck %s @ RUN: llvm-mc < %s -triple armv7-unknown-linux-gnueabi -filetype=obj -o - \ -@ RUN: | llvm-readobj -s -sd | FileCheck %s - -@ CHECK: Name: .ARM.attribute -@ CHECK: SectionData ( - -@ <format-version> -@ CHECK: 41 - -@ <section-length> -@ CHECK: 250000 00 - -@ <vendor-name> "aeabi\0" -@ CHECK: 616561 626900 - -@ <file-tag> -@ CHECK: 01 - -@ <size> -@ CHECK: 1B000000 - -@ <attribute>* - - .eabi_attribute 6, 10 -@ CHECK: 060A - - .eabi_attribute 7, 65 -@ CHECK: 0741 - - .eabi_attribute 8, 1 -@ CHECK: 0801 - - .eabi_attribute 9, 2 -@ CHECK: 0902 - - .eabi_attribute 10, 3 -@ CHECK: 0A03 - - .eabi_attribute 12, 1 -@ CHECK: 0C01 - - .eabi_attribute 20, 1 -@ CHECK: 1401 - - .eabi_attribute 21, 1 -@ CHECK: 1501 - - .eabi_attribute 23, 3 -@ CHECK: 1703 - - .eabi_attribute 24, 1 -@ CHECK: 1801 - - .eabi_attribute 25, 1 -@ CHECK: 1901 -@ CHECK: ) +@ RUN: | llvm-readobj -arm-attributes | FileCheck %s --check-prefix=CHECK-OBJ + + .syntax unified + .thumb + + .eabi_attribute Tag_conformance, "2.09" +@ CHECK: .eabi_attribute 67, "2.09" +@ Tag_conformance should be be emitted first in a file-scope +@ sub-subsection of the first public subsection of the attributes +@ section. 2.3.7.4 of ABI Addenda. +@ CHECK-OBJ: Tag: 67 +@ CHECK-OBJ-NEXT: TagName: conformance +@ CHECK-OBJ-NEXT: Value: 2.09 + .eabi_attribute Tag_CPU_raw_name, "Cortex-A9" +@ CHECK: .eabi_attribute 4, "Cortex-A9" +@ CHECK-OBJ: Tag: 4 +@ CHECK-OBJ-NEXT: TagName: CPU_raw_name +@ CHECK-OBJ-NEXT: Value: Cortex-A9 + .eabi_attribute Tag_CPU_name, "cortex-a9" +@ CHECK: .cpu cortex-a9 +@ CHECK-OBJ: Tag: 5 +@ CHECK-OBJ-NEXT: TagName: CPU_name +@ CHECK-OBJ-NEXT: Value: cortex-a9 + .eabi_attribute Tag_CPU_arch, 10 +@ CHECK: .eabi_attribute 6, 10 +@ CHECK-OBJ: Tag: 6 +@ CHECK-OBJ-NEXT: Value: 10 +@ CHECK-OBJ-NEXT: TagName: CPU_arch +@ CHECK-OBJ-NEXT: Description: ARM v7 + .eabi_attribute Tag_CPU_arch_profile, 'A' +@ CHECK: .eabi_attribute 7, 65 +@ CHECK-OBJ: Tag: 7 +@ CHECK-OBJ-NEXT: Value: 65 +@ CHECK-OBJ-NEXT: TagName: CPU_arch_profile +@ CHECK-OBJ-NEXT: Description: Application + .eabi_attribute Tag_ARM_ISA_use, 0 +@ CHECK: .eabi_attribute 8, 0 +@ CHECK-OBJ: Tag: 8 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ARM_ISA_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_THUMB_ISA_use, 2 +@ CHECK: .eabi_attribute 9, 2 +@ CHECK-OBJ: Tag: 9 +@ CHECK-OBJ-NEXT: Value: 2 +@ CHECK-OBJ-NEXT: TagName: THUMB_ISA_use +@ CHECK-OBJ-NEXT: Description: Thumb-2 + .eabi_attribute Tag_FP_arch, 3 +@ CHECK: .eabi_attribute 10, 3 +@ CHECK-OBJ: Tag: 10 +@ CHECK-OBJ-NEXT: Value: 3 +@ CHECK-OBJ-NEXT: TagName: FP_arch +@ CHECK-OBJ-NEXT: Description: VFPv3 + .eabi_attribute Tag_WMMX_arch, 0 +@ CHECK: .eabi_attribute 11, 0 +@ CHECK-OBJ: Tag: 11 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: WMMX_arch +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_Advanced_SIMD_arch, 1 +@ CHECK: .eabi_attribute 12, 1 +@ CHECK-OBJ: Tag: 12 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: Advanced_SIMD_arch +@ CHECK-OBJ-NEXT: Description: NEONv1 + .eabi_attribute Tag_PCS_config, 2 +@ CHECK: .eabi_attribute 13, 2 +@ CHECK-OBJ: Tag: 13 +@ CHECK-OBJ-NEXT: Value: 2 +@ CHECK-OBJ-NEXT: TagName: PCS_config +@ CHECK-OBJ-NEXT: Description: Linux Application + .eabi_attribute Tag_ABI_PCS_R9_use, 0 +@ CHECK: .eabi_attribute 14, 0 +@ CHECK-OBJ: Tag: 14 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_R9_use +@ CHECK-OBJ-NEXT: Description: v6 + .eabi_attribute Tag_ABI_PCS_RW_data, 0 +@ CHECK: .eabi_attribute 15, 0 +@ CHECK-OBJ: Tag: 15 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_RW_data +@ CHECK-OBJ-NEXT: Description: Absolute + .eabi_attribute Tag_ABI_PCS_RO_data, 0 +@ CHECK: .eabi_attribute 16, 0 +@ CHECK-OBJ: Tag: 16 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_RO_data +@ CHECK-OBJ-NEXT: Description: Absolute + .eabi_attribute Tag_ABI_PCS_GOT_use, 0 +@ CHECK: .eabi_attribute 17, 0 +@ CHECK-OBJ: Tag: 17 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_GOT_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_ABI_PCS_wchar_t, 4 +@ CHECK: .eabi_attribute 18, 4 +@ CHECK-OBJ: Tag: 18 +@ CHECK-OBJ-NEXT: Value: 4 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_wchar_t +@ CHECK-OBJ-NEXT: Description: 4-byte + .eabi_attribute Tag_ABI_FP_rounding, 1 +@ CHECK: .eabi_attribute 19, 1 +@ CHECK-OBJ: Tag: 19 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_rounding +@ CHECK-OBJ-NEXT: Description: Runtime + .eabi_attribute Tag_ABI_FP_denormal, 2 +@ CHECK: .eabi_attribute 20, 2 +@ CHECK-OBJ: Tag: 20 +@ CHECK-OBJ-NEXT: Value: 2 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_denormal +@ CHECK-OBJ-NEXT: Description: Sign Only + .eabi_attribute Tag_ABI_FP_exceptions, 1 +@ CHECK: .eabi_attribute 21, 1 +@ CHECK-OBJ: Tag: 21 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_exceptions +@ CHECK-OBJ-NEXT: Description: IEEE-754 + .eabi_attribute Tag_ABI_FP_user_exceptions, 1 +@ CHECK: .eabi_attribute 22, 1 +@ CHECK-OBJ: Tag: 22 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_user_exceptions +@ CHECK-OBJ-NEXT: Description: IEEE-754 + .eabi_attribute Tag_ABI_FP_number_model, 3 +@ CHECK: .eabi_attribute 23, 3 +@ CHECK-OBJ: Tag: 23 +@ CHECK-OBJ-NEXT: Value: 3 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_number_model +@ CHECK-OBJ-NEXT: Description: IEEE-754 + .eabi_attribute Tag_ABI_align_needed, 1 +@ CHECK: .eabi_attribute 24, 1 +@ CHECK-OBJ: Tag: 24 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_align_needed +@ CHECK-OBJ-NEXT: Description: 8-byte alignment + .eabi_attribute Tag_ABI_align_preserved, 2 +@ CHECK: .eabi_attribute 25, 2 +@ CHECK-OBJ: Tag: 25 +@ CHECK-OBJ-NEXT: Value: 2 +@ CHECK-OBJ-NEXT: TagName: ABI_align_preserved +@ CHECK-OBJ-NEXT: Description: 8-byte data and code alignment + .eabi_attribute Tag_ABI_enum_size, 3 +@ CHECK: .eabi_attribute 26, 3 +@ CHECK-OBJ: Tag: 26 +@ CHECK-OBJ-NEXT: Value: 3 +@ CHECK-OBJ-NEXT: TagName: ABI_enum_size +@ CHECK-OBJ-NEXT: Description: External Int32 + .eabi_attribute Tag_ABI_HardFP_use, 0 +@ CHECK: .eabi_attribute 27, 0 +@ CHECK-OBJ: Tag: 27 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_HardFP_use +@ CHECK-OBJ-NEXT: Description: Tag_FP_arch + .eabi_attribute Tag_ABI_VFP_args, 1 +@ CHECK: .eabi_attribute 28, 1 +@ CHECK-OBJ: Tag: 28 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_VFP_args +@ CHECK-OBJ-NEXT: Description: AAPCS VFP + .eabi_attribute Tag_ABI_WMMX_args, 0 +@ CHECK: .eabi_attribute 29, 0 +@ CHECK-OBJ: Tag: 29 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_WMMX_args +@ CHECK-OBJ-NEXT: Description: AAPCS + .eabi_attribute Tag_ABI_FP_optimization_goals, 1 +@ CHECK: .eabi_attribute 31, 1 +@ CHECK-OBJ: Tag: 31 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_optimization_goals +@ CHECK-OBJ-NEXT: Description: Speed + .eabi_attribute Tag_compatibility, 1, "aeabi" +@ CHECK: .eabi_attribute 32, 1, "aeabi" +@ CHECK-OBJ: Tag: 32 +@ CHECK-OBJ-NEXT: Value: 1, aeabi +@ CHECK-OBJ-NEXT: TagName: compatibility +@ CHECK-OBJ-NEXT: Description: AEABI Conformant + .eabi_attribute Tag_CPU_unaligned_access, 0 +@ CHECK: .eabi_attribute 34, 0 +@ CHECK-OBJ: Tag: 34 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: CPU_unaligned_access +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_FP_HP_extension, 0 +@ CHECK: .eabi_attribute 36, 0 +@ CHECK-OBJ: Tag: 36 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: FP_HP_extension +@ CHECK-OBJ-NEXT: Description: If Available + .eabi_attribute Tag_ABI_FP_16bit_format, 0 +@ CHECK: .eabi_attribute 38, 0 +@ CHECK-OBJ: Tag: 38 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_16bit_format +@ CHECK-OBJ-NEXT: Description: Not Permitte + .eabi_attribute Tag_MPextension_use, 0 +@ CHECK: .eabi_attribute 42, 0 +@ CHECK-OBJ: Tag: 42 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: MPextension_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_DIV_use, 0 +@ CHECK: .eabi_attribute 44, 0 +@ CHECK-OBJ: Tag: 44 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: DIV_use +@ CHECK-OBJ-NEXT: Description: If Available + .eabi_attribute Tag_nodefaults, 0 +@ CHECK: .eabi_attribute 64, 0 +@ CHECK-OBJ: Tag: 64 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: nodefaults +@ CHECK-OBJ-NEXT: Description: Unspecified Tags UNDEFINED + .eabi_attribute Tag_also_compatible_with, "gnu" +@ CHECK: .eabi_attribute 65, "gnu" +@ CHECK-OBJ: Tag: 65 +@ CHECK-OBJ-NEXT: TagName: also_compatible_with +@ CHECK-OBJ-NEXT: Value: gnu + .eabi_attribute Tag_T2EE_use, 0 +@ CHECK: .eabi_attribute 66, 0 +@ CHECK-OBJ: Tag: 66 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: T2EE_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_Virtualization_use, 0 +@ CHECK: .eabi_attribute 68, 0 +@ CHECK-OBJ: Tag: 68 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: Virtualization_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + +@ ===--- Compatibility Checks ---=== + + .eabi_attribute Tag_ABI_align8_needed, 1 +@ CHECK: .eabi_attribute 24, 1 + .eabi_attribute Tag_ABI_align8_preserved, 2 +@ CHECK: .eabi_attribute 25, 2 + +@ ===--- GNU AS Compatibility Checks ---=== + + .eabi_attribute 2 * 2 + 1, "cortex-a9" +@ CHECK: .cpu cortex-a9 + .eabi_attribute 2 * 2 + 2, 5 * 2 +@ CHECK: .eabi_attribute 6, 10 diff --git a/test/MC/ARM/directive-fpu-instrs.s b/test/MC/ARM/directive-fpu-instrs.s new file mode 100644 index 000000000000..ec97a77aef66 --- /dev/null +++ b/test/MC/ARM/directive-fpu-instrs.s @@ -0,0 +1,16 @@ +// RUN: llvm-mc -triple armv7-unknown-linux-gnueabi -mattr=+vfp3,-neon %s + +.fpu neon +VAND d3, d5, d5 +vldr d21, [r7, #296] + +@ .thumb should not disable the prior .fpu neon +.thumb + +vmov q4, q11 @ v4si +str r6, [r7, #264] +mov r6, r5 +vldr d21, [r7, #296] +add r9, r7, #216 + +fstmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15} diff --git a/test/MC/ARM/directive-thumb_func.s b/test/MC/ARM/directive-thumb_func.s new file mode 100644 index 000000000000..f82e0d1b60a1 --- /dev/null +++ b/test/MC/ARM/directive-thumb_func.s @@ -0,0 +1,22 @@ +@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null %s 2>&1 \ +@ RUN: | FileCheck %s -check-prefix CHECK-EABI + +@ NOTE: this test ensures that both forms are accepted for MachO +@ RUN: llvm-mc -triple armv7-darwin -filetype asm -o /dev/null %s + + .syntax unified + + .thumb_func +no_suffix: + bx lr + + .thumb_func suffix +suffix: + bx lr + +// CHECK-EABI: error: unexpected token in directive +// CHECK-EABI: .thumb_func suffix +// CHECK-EABI: ^ + +// CHECK-EABI-NOT: error: invalid instruction + diff --git a/test/MC/ARM/directive-unsupported.s b/test/MC/ARM/directive-unsupported.s new file mode 100644 index 000000000000..0b1f9bac61a1 --- /dev/null +++ b/test/MC/ARM/directive-unsupported.s @@ -0,0 +1,68 @@ +@ RUN: not llvm-mc -triple thumbv7-windows -filetype asm -o /dev/null %s 2>&1 \ +@ RUN: | FileCheck %s + +@ RUN: not llvm-mc -triple armv7-darwin -filetype asm -o /dev/null %s 2>&1 \ +@ RUN: | FileCheck %s + + .syntax unified + + .arch armv7 + +// CHECK: error: unknown directive +// CHECK: .arch armv7 +// CHECK: ^ + + .cpu cortex-a7 + +// CHECK: error: unknown directive +// CHECK: .cpu cortex-a7 +// CHECK: ^ + + .fpu neon + +// CHECK: error: unknown directive +// CHECK: .fpu neon +// CHECK: ^ + + .eabi_attribute 0, 0 + +// CHECK: error: unknown directive +// CHECK: .eabi_attribute 0, 0 +// CHECK: ^ + + .inst 0xdefe + +// CHECK: error: unknown directive +// CHECK: .inst 0xdefe +// CHECK: ^ + + .inst.n 0xdefe + +// CHECK: error: unknown directive +// CHECK: .inst.n 0xdefe +// CHECK: ^ + + .inst.w 0xdefe + +// CHECK: error: unknown directive +// CHECK: .inst.w 0xdefe +// CHECK: ^ + + .object_arch armv7 + +// CHECK: error: unknown directive +// CHECK: .object_arch armv7 +// CHECK: ^ + + .tlsdescseq undefined + +// CHECK: error: unknown directive +// CHECK: .tlsdescseq undefined +// CHECK: ^ + + .fnstart + +// CHECK: error: unknown directive +// CHECK: .fnstart +// CHECK: ^ + diff --git a/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s b/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s new file mode 100644 index 000000000000..5bf8fbd57fa5 --- /dev/null +++ b/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s @@ -0,0 +1,66 @@ +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp -dwarf-version 2 2>&1 | FileCheck -check-prefix MESSAGES %s +// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s +// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s + + .section .text, "ax" +a: + mov r0, r0 + + .section foo, "ax" +b: + mov r1, r1 + +// MESSAGES: warning: DWARF2 only supports one section per compilation unit + +// DWARF: .debug_abbrev contents: +// DWARF: Abbrev table for offset: 0x00000000 +// DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes +// DWARF: DW_AT_stmt_list DW_FORM_data4 +// DWARF: DW_AT_low_pc DW_FORM_addr +// DWARF: DW_AT_high_pc DW_FORM_addr +// DWARF: DW_AT_name DW_FORM_string +// DWARF: DW_AT_comp_dir DW_FORM_string +// DWARF: DW_AT_producer DW_FORM_string +// DWARF: DW_AT_language DW_FORM_data2 + +// DWARF: .debug_info contents: +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] +// CHECK-NOT-DWARF: DW_TAG_ +// DWARF: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) +// DWARF: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000004) + +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * +// DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a") + + +// DWARF: .debug_aranges contents: +// DWARF-NEXT: Address Range Header: length = 0x00000024, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x04, seg_size = 0x00 +// DWARF-NEXT: [0x00000000 - 0x00000004) +// DWARF-NEXT: [0x00000000 - 0x00000004) + +// DWARF: .debug_line contents: +// DWARF: 0x0000000000000000 7 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 7 0 1 0 0 is_stmt end_sequence +// DWARF: 0x0000000000000000 11 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 11 0 1 0 0 is_stmt end_sequence + + +// DWARF: .debug_ranges contents: +// DWARF-NOT: {{0-9a-f}} +// DWARF: .debug_pubnames contents: + + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_info]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_abbrev +// RELOC-NEXT: 0000000c R_ARM_ABS32 .debug_line +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 foo + +// RELOC-NOT: RELOCATION RECORDS FOR [.rel.debug_ranges]: + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_aranges]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_info +// RELOC-NEXT: 00000010 R_ARM_ABS32 .text +// RELOC-NEXT: 00000018 R_ARM_ABS32 foo diff --git a/test/MC/ARM/dwarf-asm-multiple-sections.s b/test/MC/ARM/dwarf-asm-multiple-sections.s index ed1b89eff3cd..0eb8bab81620 100644 --- a/test/MC/ARM/dwarf-asm-multiple-sections.s +++ b/test/MC/ARM/dwarf-asm-multiple-sections.s @@ -1,7 +1,7 @@ // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp // RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s // RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s -// RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 2 2>&1 | FileCheck -check-prefix VERSION %s +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 2 2>&1 | FileCheck -check-prefix VERSION %s // RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 1 2>&1 | FileCheck -check-prefix DWARF1 %s // RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 5 2>&1 | FileCheck -check-prefix DWARF5 %s .section .text, "ax" @@ -25,7 +25,7 @@ b: // DWARF: .debug_info contents: // DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] // CHECK-NOT-DWARF: DW_TAG_ -// DWARF: DW_AT_ranges [DW_FORM_data4] (0x00000000) +// DWARF: DW_AT_ranges [DW_FORM_data4] (0x00000000 // DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * // DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a") @@ -73,7 +73,7 @@ b: // RELOC-NEXT: 00000018 R_ARM_ABS32 foo -// VERSION: {{.*}} error: DWARF2 only supports one section per compilation unit +// VERSION: {{.*}} warning: DWARF2 only supports one section per compilation unit // DWARF1: Dwarf version 1 is not supported. // DWARF5: Dwarf version 5 is not supported. diff --git a/test/MC/ARM/ldr-pseudo-parse-errors.s b/test/MC/ARM/ldr-pseudo-parse-errors.s index 2e6114d6fe08..2516239f5ee0 100644 --- a/test/MC/ARM/ldr-pseudo-parse-errors.s +++ b/test/MC/ARM/ldr-pseudo-parse-errors.s @@ -4,7 +4,7 @@ .text bar: mov r0, =0x101 -@ CHECK: error: unexpected token in operand +@ CHECK: error: unknown token in expression @ CHECK: mov r0, =0x101 @ CHECK: ^ diff --git a/test/MC/ARM/move-banked-regs.s b/test/MC/ARM/move-banked-regs.s new file mode 100644 index 000000000000..b3b91f5915e2 --- /dev/null +++ b/test/MC/ARM/move-banked-regs.s @@ -0,0 +1,220 @@ +@ RUN: llvm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM +@ RUN: llvm-mc -triple thumbv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-THUMB + + mrs r2, r8_usr + mrs r3, r9_usr + mrs r5, r10_usr + mrs r7, r11_usr + mrs r11, r12_usr + mrs r1, sp_usr + mrs r2, lr_usr +@ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x00,0xe1] +@ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x01,0xe1] +@ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x02,0xe1] +@ CHECK-ARM: mrs r7, r11_usr @ encoding: [0x00,0x72,0x03,0xe1] +@ CHECK-ARM: mrs r11, r12_usr @ encoding: [0x00,0xb2,0x04,0xe1] +@ CHECK-ARM: mrs r1, sp_usr @ encoding: [0x00,0x12,0x05,0xe1] +@ CHECK-ARM: mrs r2, lr_usr @ encoding: [0x00,0x22,0x06,0xe1] +@ CHECK-THUMB: mrs r2, r8_usr @ encoding: [0xe0,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, r9_usr @ encoding: [0xe1,0xf3,0x20,0x83] +@ CHECK-THUMB: mrs r5, r10_usr @ encoding: [0xe2,0xf3,0x20,0x85] +@ CHECK-THUMB: mrs r7, r11_usr @ encoding: [0xe3,0xf3,0x20,0x87] +@ CHECK-THUMB: mrs r11, r12_usr @ encoding: [0xe4,0xf3,0x20,0x8b] +@ CHECK-THUMB: mrs r1, sp_usr @ encoding: [0xe5,0xf3,0x20,0x81] +@ CHECK-THUMB: mrs r2, lr_usr @ encoding: [0xe6,0xf3,0x20,0x82] + + mrs r2, r8_fiq + mrs r3, r9_fiq + mrs r5, r10_fiq + mrs r7, r11_fiq + mrs r11, r12_fiq + mrs r1, sp_fiq + mrs r2, lr_fiq + mrs r3, spsr_fiq +@ CHECK-ARM: mrs r2, r8_fiq @ encoding: [0x00,0x22,0x08,0xe1] +@ CHECK-ARM: mrs r3, r9_fiq @ encoding: [0x00,0x32,0x09,0xe1] +@ CHECK-ARM: mrs r5, r10_fiq @ encoding: [0x00,0x52,0x0a,0xe1] +@ CHECK-ARM: mrs r7, r11_fiq @ encoding: [0x00,0x72,0x0b,0xe1] +@ CHECK-ARM: mrs r11, r12_fiq @ encoding: [0x00,0xb2,0x0c,0xe1] +@ CHECK-ARM: mrs r1, sp_fiq @ encoding: [0x00,0x12,0x0d,0xe1] +@ CHECK-ARM: mrs r2, lr_fiq @ encoding: [0x00,0x22,0x0e,0xe1] +@ CHECK-ARM: mrs r3, SPSR_fiq @ encoding: [0x00,0x32,0x4e,0xe1] +@ CHECK-THUMB: mrs r2, r8_fiq @ encoding: [0xe8,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, r9_fiq @ encoding: [0xe9,0xf3,0x20,0x83] +@ CHECK-THUMB: mrs r5, r10_fiq @ encoding: [0xea,0xf3,0x20,0x85] +@ CHECK-THUMB: mrs r7, r11_fiq @ encoding: [0xeb,0xf3,0x20,0x87] +@ CHECK-THUMB: mrs r11, r12_fiq @ encoding: [0xec,0xf3,0x20,0x8b] +@ CHECK-THUMB: mrs r1, sp_fiq @ encoding: [0xed,0xf3,0x20,0x81] +@ CHECK-THUMB: mrs r2, lr_fiq @ encoding: [0xee,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, SPSR_fiq @ encoding: [0xfe,0xf3,0x20,0x83] + + mrs r4, lr_irq + mrs r9, sp_irq + mrs r1, spsr_irq +@ CHECK-ARM: mrs r4, lr_irq @ encoding: [0x00,0x43,0x00,0xe1] +@ CHECK-ARM: mrs r9, sp_irq @ encoding: [0x00,0x93,0x01,0xe1] +@ CHECK-ARM: mrs r1, SPSR_irq @ encoding: [0x00,0x13,0x40,0xe1] +@ CHECK-THUMB: mrs r4, lr_irq @ encoding: [0xe0,0xf3,0x30,0x84] +@ CHECK-THUMB: mrs r9, sp_irq @ encoding: [0xe1,0xf3,0x30,0x89] +@ CHECK-THUMB: mrs r1, SPSR_irq @ encoding: [0xf0,0xf3,0x30,0x81] + + mrs r1, lr_svc + mrs r3, sp_svc + mrs r5, spsr_svc +@ CHECK-ARM: mrs r1, lr_svc @ encoding: [0x00,0x13,0x02,0xe1] +@ CHECK-ARM: mrs r3, sp_svc @ encoding: [0x00,0x33,0x03,0xe1] +@ CHECK-ARM: mrs r5, SPSR_svc @ encoding: [0x00,0x53,0x42,0xe1] +@ CHECK-THUMB: mrs r1, lr_svc @ encoding: [0xe2,0xf3,0x30,0x81] +@ CHECK-THUMB: mrs r3, sp_svc @ encoding: [0xe3,0xf3,0x30,0x83] +@ CHECK-THUMB: mrs r5, SPSR_svc @ encoding: [0xf2,0xf3,0x30,0x85] + + mrs r5, lr_abt + mrs r7, sp_abt + mrs r9, spsr_abt +@ CHECK-ARM: mrs r5, lr_abt @ encoding: [0x00,0x53,0x04,0xe1] +@ CHECK-ARM: mrs r7, sp_abt @ encoding: [0x00,0x73,0x05,0xe1] +@ CHECK-ARM: mrs r9, SPSR_abt @ encoding: [0x00,0x93,0x44,0xe1] +@ CHECK-THUMB: mrs r5, lr_abt @ encoding: [0xe4,0xf3,0x30,0x85] +@ CHECK-THUMB: mrs r7, sp_abt @ encoding: [0xe5,0xf3,0x30,0x87] +@ CHECK-THUMB: mrs r9, SPSR_abt @ encoding: [0xf4,0xf3,0x30,0x89] + + mrs r9, lr_und + mrs r11, sp_und + mrs r12, spsr_und +@ CHECK-ARM: mrs r9, lr_und @ encoding: [0x00,0x93,0x06,0xe1] +@ CHECK-ARM: mrs r11, sp_und @ encoding: [0x00,0xb3,0x07,0xe1] +@ CHECK-ARM: mrs r12, SPSR_und @ encoding: [0x00,0xc3,0x46,0xe1] +@ CHECK-THUMB: mrs r9, lr_und @ encoding: [0xe6,0xf3,0x30,0x89] +@ CHECK-THUMB: mrs r11, sp_und @ encoding: [0xe7,0xf3,0x30,0x8b] +@ CHECK-THUMB: mrs r12, SPSR_und @ encoding: [0xf6,0xf3,0x30,0x8c] + + + mrs r2, lr_mon + mrs r4, sp_mon + mrs r6, spsr_mon +@ CHECK-ARM: mrs r2, lr_mon @ encoding: [0x00,0x23,0x0c,0xe1] +@ CHECK-ARM: mrs r4, sp_mon @ encoding: [0x00,0x43,0x0d,0xe1] +@ CHECK-ARM: mrs r6, SPSR_mon @ encoding: [0x00,0x63,0x4c,0xe1] +@ CHECK-THUMB: mrs r2, lr_mon @ encoding: [0xec,0xf3,0x30,0x82] +@ CHECK-THUMB: mrs r4, sp_mon @ encoding: [0xed,0xf3,0x30,0x84] +@ CHECK-THUMB: mrs r6, SPSR_mon @ encoding: [0xfc,0xf3,0x30,0x86] + + + mrs r6, elr_hyp + mrs r8, sp_hyp + mrs r10, spsr_hyp +@ CHECK-ARM: mrs r6, elr_hyp @ encoding: [0x00,0x63,0x0e,0xe1] +@ CHECK-ARM: mrs r8, sp_hyp @ encoding: [0x00,0x83,0x0f,0xe1] +@ CHECK-ARM: mrs r10, SPSR_hyp @ encoding: [0x00,0xa3,0x4e,0xe1] +@ CHECK-THUMB: mrs r6, elr_hyp @ encoding: [0xee,0xf3,0x30,0x86] +@ CHECK-THUMB: mrs r8, sp_hyp @ encoding: [0xef,0xf3,0x30,0x88] +@ CHECK-THUMB: mrs r10, SPSR_hyp @ encoding: [0xfe,0xf3,0x30,0x8a] + + + msr r8_usr, r2 + msr r9_usr, r3 + msr r10_usr, r5 + msr r11_usr, r7 + msr r12_usr, r11 + msr sp_usr, r1 + msr lr_usr, r2 +@ CHECK-ARM: msr r8_usr, r2 @ encoding: [0x02,0xf2,0x20,0xe1] +@ CHECK-ARM: msr r9_usr, r3 @ encoding: [0x03,0xf2,0x21,0xe1] +@ CHECK-ARM: msr r10_usr, r5 @ encoding: [0x05,0xf2,0x22,0xe1] +@ CHECK-ARM: msr r11_usr, r7 @ encoding: [0x07,0xf2,0x23,0xe1] +@ CHECK-ARM: msr r12_usr, r11 @ encoding: [0x0b,0xf2,0x24,0xe1] +@ CHECK-ARM: msr sp_usr, r1 @ encoding: [0x01,0xf2,0x25,0xe1] +@ CHECK-ARM: msr lr_usr, r2 @ encoding: [0x02,0xf2,0x26,0xe1] +@ CHECK-THUMB: msr r8_usr, r2 @ encoding: [0x82,0xf3,0x20,0x80] +@ CHECK-THUMB: msr r9_usr, r3 @ encoding: [0x83,0xf3,0x20,0x81] +@ CHECK-THUMB: msr r10_usr, r5 @ encoding: [0x85,0xf3,0x20,0x82] +@ CHECK-THUMB: msr r11_usr, r7 @ encoding: [0x87,0xf3,0x20,0x83] +@ CHECK-THUMB: msr r12_usr, r11 @ encoding: [0x8b,0xf3,0x20,0x84] +@ CHECK-THUMB: msr sp_usr, r1 @ encoding: [0x81,0xf3,0x20,0x85] +@ CHECK-THUMB: msr lr_usr, r2 @ encoding: [0x82,0xf3,0x20,0x86] + + msr r8_fiq, r2 + msr r9_fiq, r3 + msr r10_fiq, r5 + msr r11_fiq, r7 + msr r12_fiq, r11 + msr sp_fiq, r1 + msr lr_fiq, r2 + msr spsr_fiq, r3 +@ CHECK-ARM: msr r8_fiq, r2 @ encoding: [0x02,0xf2,0x28,0xe1] +@ CHECK-ARM: msr r9_fiq, r3 @ encoding: [0x03,0xf2,0x29,0xe1] +@ CHECK-ARM: msr r10_fiq, r5 @ encoding: [0x05,0xf2,0x2a,0xe1] +@ CHECK-ARM: msr r11_fiq, r7 @ encoding: [0x07,0xf2,0x2b,0xe1] +@ CHECK-ARM: msr r12_fiq, r11 @ encoding: [0x0b,0xf2,0x2c,0xe1] +@ CHECK-ARM: msr sp_fiq, r1 @ encoding: [0x01,0xf2,0x2d,0xe1] +@ CHECK-ARM: msr lr_fiq, r2 @ encoding: [0x02,0xf2,0x2e,0xe1] +@ CHECK-ARM: msr SPSR_fiq, r3 @ encoding: [0x03,0xf2,0x6e,0xe1] +@ CHECK-THUMB: msr r8_fiq, r2 @ encoding: [0x82,0xf3,0x20,0x88] +@ CHECK-THUMB: msr r9_fiq, r3 @ encoding: [0x83,0xf3,0x20,0x89] +@ CHECK-THUMB: msr r10_fiq, r5 @ encoding: [0x85,0xf3,0x20,0x8a] +@ CHECK-THUMB: msr r11_fiq, r7 @ encoding: [0x87,0xf3,0x20,0x8b] +@ CHECK-THUMB: msr r12_fiq, r11 @ encoding: [0x8b,0xf3,0x20,0x8c] +@ CHECK-THUMB: msr sp_fiq, r1 @ encoding: [0x81,0xf3,0x20,0x8d] +@ CHECK-THUMB: msr lr_fiq, r2 @ encoding: [0x82,0xf3,0x20,0x8e] +@ CHECK-THUMB: msr SPSR_fiq, r3 @ encoding: [0x93,0xf3,0x20,0x8e] + + msr lr_irq, r4 + msr sp_irq, r9 + msr spsr_irq, r11 +@ CHECK-ARM: msr lr_irq, r4 @ encoding: [0x04,0xf3,0x20,0xe1] +@ CHECK-ARM: msr sp_irq, r9 @ encoding: [0x09,0xf3,0x21,0xe1] +@ CHECK-ARM: msr SPSR_irq, r11 @ encoding: [0x0b,0xf3,0x60,0xe1] +@ CHECK-THUMB: msr lr_irq, r4 @ encoding: [0x84,0xf3,0x30,0x80] +@ CHECK-THUMB: msr sp_irq, r9 @ encoding: [0x89,0xf3,0x30,0x81] +@ CHECK-THUMB: msr SPSR_irq, r11 @ encoding: [0x9b,0xf3,0x30,0x80] + + msr lr_svc, r1 + msr sp_svc, r3 + msr spsr_svc, r5 +@ CHECK-ARM: msr lr_svc, r1 @ encoding: [0x01,0xf3,0x22,0xe1] +@ CHECK-ARM: msr sp_svc, r3 @ encoding: [0x03,0xf3,0x23,0xe1] +@ CHECK-ARM: msr SPSR_svc, r5 @ encoding: [0x05,0xf3,0x62,0xe1] +@ CHECK-THUMB: msr lr_svc, r1 @ encoding: [0x81,0xf3,0x30,0x82] +@ CHECK-THUMB: msr sp_svc, r3 @ encoding: [0x83,0xf3,0x30,0x83] +@ CHECK-THUMB: msr SPSR_svc, r5 @ encoding: [0x95,0xf3,0x30,0x82] + + msr lr_abt, r5 + msr sp_abt, r7 + msr spsr_abt, r9 +@ CHECK-ARM: msr lr_abt, r5 @ encoding: [0x05,0xf3,0x24,0xe1] +@ CHECK-ARM: msr sp_abt, r7 @ encoding: [0x07,0xf3,0x25,0xe1] +@ CHECK-ARM: msr SPSR_abt, r9 @ encoding: [0x09,0xf3,0x64,0xe1] +@ CHECK-THUMB: msr lr_abt, r5 @ encoding: [0x85,0xf3,0x30,0x84] +@ CHECK-THUMB: msr sp_abt, r7 @ encoding: [0x87,0xf3,0x30,0x85] +@ CHECK-THUMB: msr SPSR_abt, r9 @ encoding: [0x99,0xf3,0x30,0x84] + + msr lr_und, r9 + msr sp_und, r11 + msr spsr_und, r12 +@ CHECK-ARM: msr lr_und, r9 @ encoding: [0x09,0xf3,0x26,0xe1] +@ CHECK-ARM: msr sp_und, r11 @ encoding: [0x0b,0xf3,0x27,0xe1] +@ CHECK-ARM: msr SPSR_und, r12 @ encoding: [0x0c,0xf3,0x66,0xe1] +@ CHECK-THUMB: msr lr_und, r9 @ encoding: [0x89,0xf3,0x30,0x86] +@ CHECK-THUMB: msr sp_und, r11 @ encoding: [0x8b,0xf3,0x30,0x87] +@ CHECK-THUMB: msr SPSR_und, r12 @ encoding: [0x9c,0xf3,0x30,0x86] + + + msr lr_mon, r2 + msr sp_mon, r4 + msr spsr_mon, r6 +@ CHECK-ARM: msr lr_mon, r2 @ encoding: [0x02,0xf3,0x2c,0xe1] +@ CHECK-ARM: msr sp_mon, r4 @ encoding: [0x04,0xf3,0x2d,0xe1] +@ CHECK-ARM: msr SPSR_mon, r6 @ encoding: [0x06,0xf3,0x6c,0xe1] +@ CHECK-THUMB: msr lr_mon, r2 @ encoding: [0x82,0xf3,0x30,0x8c] +@ CHECK-THUMB: msr sp_mon, r4 @ encoding: [0x84,0xf3,0x30,0x8d] +@ CHECK-THUMB: msr SPSR_mon, r6 @ encoding: [0x96,0xf3,0x30,0x8c] + + msr elr_hyp, r6 + msr sp_hyp, r8 + msr spsr_hyp, r10 +@ CHECK-ARM: msr elr_hyp, r6 @ encoding: [0x06,0xf3,0x2e,0xe1] +@ CHECK-ARM: msr sp_hyp, r8 @ encoding: [0x08,0xf3,0x2f,0xe1] +@ CHECK-ARM: msr SPSR_hyp, r10 @ encoding: [0x0a,0xf3,0x6e,0xe1] +@ CHECK-THUMB: msr elr_hyp, r6 @ encoding: [0x86,0xf3,0x30,0x8e] +@ CHECK-THUMB: msr sp_hyp, r8 @ encoding: [0x88,0xf3,0x30,0x8f] +@ CHECK-THUMB: msr SPSR_hyp, r10 @ encoding: [0x9a,0xf3,0x30,0x8e] diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s index 8c7228835c9b..d142dbabec9e 100644 --- a/test/MC/ARM/neon-bitwise-encoding.s +++ b/test/MC/ARM/neon-bitwise-encoding.s @@ -29,18 +29,63 @@ vbic d16, d17, d16 vbic q8, q8, q9 + vbic q10, q11 + vbic d9, d1 + vbic.i16 d16, #0xFF00 + vbic.i16 q8, #0xFF00 + vbic.i16 d16, #0x00FF + vbic.i16 q8, #0x00FF vbic.i32 d16, #0xFF000000 - vbic.i32 q8, #0xFF000000 - vbic q10, q11 - vbic d9, d1 + vbic.i32 q8, #0xFF000000 + vbic.i32 d16, #0x00FF0000 + vbic.i32 q8, #0x00FF0000 + vbic.i32 d16, #0x0000FF00 + vbic.i32 q8, #0x0000FF00 + vbic.i32 d16, #0x000000FF + vbic.i32 q8, #0x000000FF @ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] -@ CHECK: vbic.i32 d16, #0xff000000 @ encoding: [0x3f,0x07,0xc7,0xf3] -@ CHECK: vbic.i32 q8, #0xff000000 @ encoding: [0x7f,0x07,0xc7,0xf3] @ CHECK: vbic q10, q10, q11 @ encoding: [0xf6,0x41,0x54,0xf2] @ CHECK: vbic d9, d9, d1 @ encoding: [0x11,0x91,0x19,0xf2] - +@ CHECK: vbic.i16 d16, #0xff00 @ encoding: [0x3f,0x0b,0xc7,0xf3] +@ CHECK: vbic.i16 q8, #0xff00 @ encoding: [0x7f,0x0b,0xc7,0xf3] +@ CHECK: vbic.i16 d16, #0xff @ encoding: [0x3f,0x09,0xc7,0xf3] +@ CHECK: vbic.i16 q8, #0xff @ encoding: [0x7f,0x09,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff000000 @ encoding: [0x3f,0x07,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff000000 @ encoding: [0x7f,0x07,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff0000 @ encoding: [0x3f,0x05,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff0000 @ encoding: [0x7f,0x05,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff00 @ encoding: [0x3f,0x03,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff00 @ encoding: [0x7f,0x03,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff @ encoding: [0x3f,0x01,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff @ encoding: [0x7f,0x01,0xc7,0xf3] + + vand.i16 d10, #0xff03 + vand.i16 q10, #0xff03 + vand.i16 d10, #0x03ff + vand.i16 q10, #0x03ff + vand.i32 d10, #0x03ffffff + vand.i32 q10, #0x03ffffff + vand.i32 d10, #0xff03ffff + vand.i32 q10, #0xff03ffff + vand.i32 d10, #0xffff03ff + vand.i32 q10, #0xffff03ff + vand.i32 d10, #0xffffff03 + vand.i32 q10, #0xffffff03 + +@ CHECK: vbic.i16 d10, #0xfc @ encoding: [0x3c,0xa9,0x87,0xf3] +@ CHECK: vbic.i16 q10, #0xfc @ encoding: [0x7c,0x49,0xc7,0xf3] +@ CHECK: vbic.i16 d10, #0xfc00 @ encoding: [0x3c,0xab,0x87,0xf3] +@ CHECK: vbic.i16 q10, #0xfc00 @ encoding: [0x7c,0x4b,0xc7,0xf3] +@ CHECK: vbic.i32 d10, #0xfc000000 @ encoding: [0x3c,0xa7,0x87,0xf3] +@ CHECK: vbic.i32 q10, #0xfc000000 @ encoding: [0x7c,0x47,0xc7,0xf3] +@ CHECK: vbic.i32 d10, #0xfc0000 @ encoding: [0x3c,0xa5,0x87,0xf3] +@ CHECK: vbic.i32 q10, #0xfc0000 @ encoding: [0x7c,0x45,0xc7,0xf3] +@ CHECK: vbic.i32 d10, #0xfc00 @ encoding: [0x3c,0xa3,0x87,0xf3] +@ CHECK: vbic.i32 q10, #0xfc00 @ encoding: [0x7c,0x43,0xc7,0xf3] +@ CHECK: vbic.i32 d10, #0xfc @ encoding: [0x3c,0xa1,0x87,0xf3] +@ CHECK: vbic.i32 q10, #0xfc @ encoding: [0x7c,0x41,0xc7,0xf3] vorn d16, d17, d16 vorn q8, q8, q9 diff --git a/test/MC/ARM/neon-mov-vfp.s b/test/MC/ARM/neon-mov-vfp.s new file mode 100644 index 000000000000..6ee6bfda436c --- /dev/null +++ b/test/MC/ARM/neon-mov-vfp.s @@ -0,0 +1,32 @@ +@ RUN: not llvm-mc -mcpu=cortex-a8 -triple armv7-unknown-unknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK +@ RUN: not llvm-mc -mcpu=cortex-a8 -triple thumbv7-unknown-unknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-unknown-unknown -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK + +@ The 32-bit variants of the NEON scalar move instructions are also available +@ to any core with VFPv2 + +@ CHECK-DAG: vmov.32 d13[0], r6 @ encoding: +@ CHECK-DAG: vmov.32 d17[1], r9 @ encoding: +vmov.32 d13[0], r6 +vmov.32 d17[1], r9 + +@ VFP-DAG: error: instruction requires: NEON +@ VFP-DAG: error: instruction requires: NEON +@ NEON-DAG: vmov.8 d22[5], r2 @ encoding: +@ NEON-DAG: vmov.16 d3[2], r4 @ encoding: +vmov.8 d22[5], r2 +vmov.16 d3[2], r4 + +@ CHECK-DAG: vmov.32 r6, d13[0] @ encoding: +@ CHECK-DAG: vmov.32 r9, d17[1] @ encoding: +vmov.32 r6, d13[0] +vmov.32 r9, d17[1] + +@ VFP-DAG: error: instruction requires: NEON +@ VFP-DAG: error: instruction requires: NEON +@ NEON-DAG: vmov.s8 r2, d22[5] @ encoding: +@ NEON-DAG: vmov.u16 r4, d3[2] @ encoding: +vmov.s8 r2, d22[5] +vmov.u16 r4, d3[2] + diff --git a/test/MC/ARM/symbol-variants.s b/test/MC/ARM/symbol-variants.s index a10fe5029e0a..af1bc07b5e1a 100644 --- a/test/MC/ARM/symbol-variants.s +++ b/test/MC/ARM/symbol-variants.s @@ -19,8 +19,8 @@ @ plt bl f04(PLT) bl f05(plt) -@ARM: 10 R_ARM_PLT32 f04 -@ARM: 14 R_ARM_PLT32 f05 +@ARM: 10 R_ARM_CALL f04 +@ARM: 14 R_ARM_CALL f05 @THUMB: 10 R_ARM_THM_CALL f04 @THUMB: 14 R_ARM_THM_CALL f05 diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s index 19d17c2deef6..bd26d06865ca 100644 --- a/test/MC/ARM/thumb-diagnostics.s +++ b/test/MC/ARM/thumb-diagnostics.s @@ -1,9 +1,11 @@ -@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s -@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s -@ RUN: not llvm-mc -triple=thumbv8 < %s 2> %t -@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s +@ RUN: not llvm-mc -triple=thumbv6-apple-darwin -o /dev/null < %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK-ERRORS %s +@ RUN: not llvm-mc -triple=thumbv5-apple-darwin -o /dev/null < %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V5 %s +@ RUN: not llvm-mc -triple=thumbv7m -o /dev/null < %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V7M %s +@ RUN: not llvm-mc -triple=thumbv8 -o /dev/null < %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK-ERRORS-V8 %s @ Check for various assembly diagnostic messages on invalid input. @@ -59,6 +61,13 @@ error: invalid operand for instruction ldm r2!, {r2, r3, r4} ldm r2!, {r2, r3, r4, r10} ldmdb r2!, {r2, r3, r4} + ldm r0, {r2, sp} + ldmia r0, {r2-r3, sp} + ldmia r0!, {r2-r3, sp} + ldmfd r2, {r1, r3-r6, sp} + ldmfd r2!, {r1, r3-r6, sp} + ldmdb r1, {r2, r3, sp} + ldmdb r1!, {r2, r3, sp} @ CHECK-ERRORS: error: registers must be in range r0-r7 @ CHECK-ERRORS: ldm r2!, {r5, r8} @ CHECK-ERRORS: ^ @@ -74,6 +83,27 @@ error: invalid operand for instruction @ CHECK-ERRORS-V8: error: writeback register not allowed in register list @ CHECK-ERRORS-V8: ldmdb r2!, {r2, r3, r4} @ CHECK-ERRORS-V8: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: ldm r0, {r2, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: ldmia r0, {r2-r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: ldmia r0!, {r2-r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: ldmfd r2, {r1, r3-r6, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: ldmfd r2!, {r1, r3-r6, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: ldmdb r1, {r2, r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: ldmdb r1!, {r2, r3, sp} +@ CHECK-ERRORS-V7M: ^ @ Invalid writeback and register lists for PUSH/POP pop {r1, r2, r10} @@ -91,6 +121,10 @@ error: invalid operand for instruction stm r1!, {r2, r9} stm r2!, {r2, r9} stmdb r2!, {r0, r2} + stm r1!, {r2, sp} + stmia r4!, {r0-r3, sp} + stmdb r1, {r2, r3, sp} + stmdb r1!, {r2, r3, sp} @ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: stm r1, {r2, r6} @ CHECK-ERRORS: ^ @@ -103,6 +137,18 @@ error: invalid operand for instruction @ CHECK-ERRORS-V8: error: writeback register not allowed in register list @ CHECK-ERRORS-V8: stmdb r2!, {r0, r2} @ CHECK-ERRORS-V8: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: stm r1!, {r2, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: stmia r4!, {r0-r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: stmdb r1, {r2, r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP may not be in the register list +@ CHECK-ERRORS-V7M: stmdb r1!, {r2, r3, sp} +@ CHECK-ERRORS-V7M: ^ @ Out of range immediates for LSL instruction. lsls r4, r5, #-1 @@ -160,7 +206,7 @@ error: invalid operand for instruction @ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add sp, sp, #512 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add r2, sp, #1024 @ CHECK-ERRORS: ^ @@ -218,3 +264,14 @@ error: invalid operand for instruction ldr r4, [pc, #-12] @ CHECK-ERRORS: error: instruction requires: thumb2 +@------------------------------------------------------------------------------ +@ STC2{L}/LDC2{L} - requires thumb2 +@------------------------------------------------------------------------------ + stc2 p0, c8, [r1, #4] + stc2l p6, c2, [r7, #4] + ldc2 p0, c8, [r1, #4] + ldc2l p6, c2, [r7, #4] +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction diff --git a/test/MC/ARM/thumb-load-store-multiple.s b/test/MC/ARM/thumb-load-store-multiple.s new file mode 100644 index 000000000000..6958450df078 --- /dev/null +++ b/test/MC/ARM/thumb-load-store-multiple.s @@ -0,0 +1,100 @@ +@ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck %s +@ RUN: not llvm-mc -triple thumbv7a-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7A %s +@ RUN: not llvm-mc -triple thumbv7m-eabi -filetype asm -o - %s 2>&1 \ +@ RUN: | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s + + .syntax unified + .thumb + + .global ldm + .type ldm,%function +ldm: + ldm r0!, {r1, sp} +@ CHECK: error: SP may not be in the register list +@ CHECK: ldm r0!, {r1, sp} +@ CHECK: ^ + ldm r0!, {lr, pc} +@ CHECK: error: PC and LR may not be in the register list simultaneously +@ CHECK: ldm r0!, {lr, pc} +@ CHECK: ^ + itt eq + ldmeq r0!, {r1, pc} + ldmeq r0!, {r2, lr} +@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block +@ CHECK: ldmeq r0!, {r1, pc} +@ CHECK: ^ + + .global ldmdb + .type ldmdb,%function +ldmdb: + ldmdb r0!, {r1, sp} +@ CHECK: error: SP may not be in the register list + ldmdb r0!, {lr, pc} +@ error: PC and LR may not be in the register list simultaneously + itt eq + ldmeq r0!, {r1, pc} + ldmeq r0!, {r2, lr} +@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block +@ CHECK: ldmeq r0!, {r1, pc} +@ CHECK: ^ + + .global stm + .type stm,%function +stm: + stm r0!, {r1, sp} +@ CHECK: error: SP may not be in the register list + stm r0!, {r2, pc} +@ CHECK: error: PC may not be in the register list + stm r0!, {sp, pc} +@ CHECK: error: SP and PC may not be in the register list + + .global stmdb + .type stmdb,%function +stmdb: + stmdb r0!, {r1, sp} +@ CHECK: error: SP may not be in the register list + stmdb r0!, {r2, pc} +@ CHECK: error: PC may not be in the register list + stmdb r0!, {sp, pc} +@ CHECK: error: SP and PC may not be in the register list + + .global push + .type push,%function +push: + push {sp} +@ CHECK: error: SP may not be in the register list + push {pc} +@ CHECK: error: PC may not be in the register list + push {sp, pc} +@ CHECK: error: SP and PC may not be in the register list + + .global pop + .type pop,%function +pop: + pop {sp} +@ CHECK-V7M: error: SP may not be in the register list + pop {lr, pc} +@ CHECK: error: PC and LR may not be in the register list simultaneously +@ CHECK: pop {lr, pc} +@ CHECK: ^ + itt eq + popeq {r1, pc} + popeq {r2, lr} +@ CHECK: error: instruction must be outside of IT block or the last instruction in an IT block +@ CHECK: popeq {r1, pc} +@ CHECK: ^ + + .global valid + .type valid,%function +valid: + pop {sp} +@ CHECK-V7A: ldr sp, [sp], #4 + pop {sp, pc} +@ CHECK-V7A: pop.w {sp, pc} + push.w {r0} +@ CHECK: str r0, [sp, #-4] + pop.w {r0} +@ CHECK: ldr r0, [sp], #4 + diff --git a/test/MC/ARM/thumb-not-mclass.s b/test/MC/ARM/thumb-not-mclass.s new file mode 100644 index 000000000000..fec545e64b06 --- /dev/null +++ b/test/MC/ARM/thumb-not-mclass.s @@ -0,0 +1,26 @@ +@ RUN: not llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s 2> %t +@ RUN: FileCheck < %t %s +@ RUN: not llvm-mc -triple=thumbv6m -show-encoding < %s 2> %t +@ RUN: FileCheck < %t %s + .syntax unified + .globl _func + +@ Check that the assembler rejects thumb instructions that are not valid +@ on mclass. + +@------------------------------------------------------------------------------ +@ BLX (immediate) +@------------------------------------------------------------------------------ + blx _baz + +@ CHECK: error: instruction requires: !armv*m + +@------------------------------------------------------------------------------ +@ SETEND +@------------------------------------------------------------------------------ + + setend be + setend le + +@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid operand for instruction diff --git a/test/MC/ARM/thumb2-bxj.s b/test/MC/ARM/thumb2-bxj.s new file mode 100644 index 000000000000..e60d1a447cba --- /dev/null +++ b/test/MC/ARM/thumb2-bxj.s @@ -0,0 +1,10 @@ +@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF +@ RUN: not llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF + + bxj r2 + +@ CHECK: bxj r2 @ encoding: [0xc2,0xf3,0x00,0x8f] +@ UNDEF: error: instruction requires: arm-mode diff --git a/test/MC/ARM/thumb2-exception-return-mclass.s b/test/MC/ARM/thumb2-exception-return-mclass.s new file mode 100644 index 000000000000..21669b0dc657 --- /dev/null +++ b/test/MC/ARM/thumb2-exception-return-mclass.s @@ -0,0 +1,15 @@ +# RUN: not llvm-mc -triple thumbv7m -assemble < %s 2>&1 | FileCheck %s + + .text + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: srsdb sp, #7 + srsdb sp, #7 + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: rfeia r6 + rfeia r6 + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: subs pc, lr, #42 + subs pc, lr, #42 diff --git a/test/MC/ARM/thumb2-ldrb-ldrh.s b/test/MC/ARM/thumb2-ldrb-ldrh.s new file mode 100644 index 000000000000..8c97987fc68d --- /dev/null +++ b/test/MC/ARM/thumb2-ldrb-ldrh.s @@ -0,0 +1,51 @@ +@ RUN: not llvm-mc -triple thumbv7a-none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK +@ RUN: not llvm-mc -triple thumbv7m-none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK + +@ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for +@ preload hints). +@ We don't check the actual error messages here as they are currently not very +@ helpful, see http://llvm.org/bugs/show_bug.cgi?id=21066. + +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: + ldrb pc, [r0, #10] + ldrb.w pc, [r1, #10] + ldrb pc, [r2, #-5] + ldrb pc, [pc, #7] + ldrb.w pc, [pc, #7] + +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: + ldrsb pc, [r3, #10] + ldrsb.w pc, [r4, #10] + ldrsb pc, [r5, #-5] + ldrsb pc, [pc, #7] + ldrsb.w pc, [pc, #7] + +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: + ldrh pc, [r6, #10] + ldrh.w pc, [r7, #10] + ldrh pc, [r8, #-5] + ldrh pc, [pc, #7] + ldrh.w pc, [pc, #7] + +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: + ldrsh pc, [r9, #10] + ldrsh.w pc, [r10, #10] + ldrsh pc, [r11, #-5] + ldrsh pc, [pc, #7] + ldrsh.w pc, [pc, #7] diff --git a/test/MC/ARM/thumb2-ldrexd-strexd.s b/test/MC/ARM/thumb2-ldrexd-strexd.s new file mode 100644 index 000000000000..3ffb0cb6eaf1 --- /dev/null +++ b/test/MC/ARM/thumb2-ldrexd-strexd.s @@ -0,0 +1,14 @@ +@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF + + ldrexd r0, r1, [r2] + strexd r3, r4, r5, [r6] + +@ CHECK: ldrexd r0, r1, [r2] @ encoding: [0xd2,0xe8,0x7f,0x01] +@ CHECK: strexd r3, r4, r5, [r6] @ encoding: [0xc6,0xe8,0x73,0x45] + +@ UNDEF: error: instruction requires: !armv*m +@ UNDEF: error: instruction requires: !armv*m diff --git a/test/MC/ARM/thumb2-mclass.s b/test/MC/ARM/thumb2-mclass.s index d9c96dfcdd34..331ecc147629 100644 --- a/test/MC/ARM/thumb2-mclass.s +++ b/test/MC/ARM/thumb2-mclass.s @@ -1,7 +1,7 @@ -@ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s -@ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V6M %s +@ RUN: llvm-mc -triple=thumbv7m -show-encoding < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s + .syntax unified - .globl _func @ Check that the assembler can handle the documented syntax from the ARM ARM. @ These tests test instruction encodings specific to v6m & v7m (FeatureMClass). @@ -40,20 +40,12 @@ msr apsr, r0 msr apsr_nzcvq, r0 - msr apsr_g, r0 - msr apsr_nzcvqg, r0 msr iapsr, r0 msr iapsr_nzcvq, r0 - msr iapsr_g, r0 - msr iapsr_nzcvqg, r0 msr eapsr, r0 msr eapsr_nzcvq, r0 - msr eapsr_g, r0 - msr eapsr_nzcvqg, r0 msr xpsr, r0 msr xpsr_nzcvq, r0 - msr xpsr_g, r0 - msr xpsr_nzcvqg, r0 msr ipsr, r0 msr epsr, r0 msr iepsr, r0 @@ -62,22 +54,22 @@ msr primask, r0 msr control, r0 -@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] -@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] -@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84] -@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c] -@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] -@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] -@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84] -@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c] -@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] -@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] -@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84] -@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c] -@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] -@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] -@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84] -@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c] +@ CHECK-V6M: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK-V6M: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK-V6M: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK-V6M: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK-V6M: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK-V6M: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK-V6M: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK-V6M: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK-V7M: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK-V7M: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK-V7M: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK-V7M: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK-V7M: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK-V7M: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK-V7M: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK-V7M: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88] @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88] @ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88] @ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88] diff --git a/test/MC/ARM/thumb_rewrites.s b/test/MC/ARM/thumb_rewrites.s new file mode 100644 index 000000000000..c9d625e60de7 --- /dev/null +++ b/test/MC/ARM/thumb_rewrites.s @@ -0,0 +1,52 @@ +@ RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s + + adds r0, r0, #8 +@ CHECK: adds r0, #8 @ encoding: [0x08,0x30] + + adds r0, r0, r0 +@ CHECK: adds r0, r0, r0 @ encoding: [0x00,0x18] + + add r0, r0, r8 +@ CHECK: add r0, r8 @ encoding: [0x40,0x44] + + add sp, sp, r0 +@ CHECK: add sp, r0 @ encoding: [0x85,0x44] + + add r0, r0, r1 +@ CHECK: add r0, r1 @ encoding: [0x08,0x44] + + add r2, r2, r3 +@ CHECK: add r2, r3 @ encoding: [0x1a,0x44] + + subs r0, r0, r0 +@ CHECK: subs r0, r0, r0 @ encoding: [0x00,0x1a] + + ands r0, r0, r1 +@ CHECK: ands r0, r1 @ encoding: [0x08,0x40] + + eors r0, r0, r1 +@ CHECK: eors r0, r1 @ encoding: [0x48,0x40] + + lsls r0, r0, r1 +@ CHECK: lsls r0, r1 @ encoding: [0x88,0x40] + + lsrs r0, r0, r1 +@ CHECK: lsrs r0, r1 @ encoding: [0xc8,0x40] + + asrs r0, r0, r1 +@ CHECK: asrs r0, r1 @ encoding: [0x08,0x41] + + adcs r0, r0, r1 +@ CHECK: adcs r0, r1 @ encoding: [0x48,0x41] + + sbcs r0, r0, r1 +@ CHECK: sbcs r0, r1 @ encoding: [0x88,0x41] + + rors r0, r0, r1 +@ CHECK: rors r0, r1 @ encoding: [0xc8,0x41] + + orrs r0, r0, r1 +@ CHECK: orrs r0, r1 @ encoding: [0x08,0x43] + + bics r0, r0, r1 +@ CHECK: bics r0, r1 @ encoding: [0x88,0x43] diff --git a/test/MC/ARM/thumbv7em.s b/test/MC/ARM/thumbv7em.s new file mode 100644 index 000000000000..53ebff2f4835 --- /dev/null +++ b/test/MC/ARM/thumbv7em.s @@ -0,0 +1,53 @@ +@ RUN: llvm-mc -triple=thumbv7em -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7m -show-encoding 2>&1 < %s | FileCheck --check-prefix=CHECK-V7M %s + + .syntax unified + +@ Check that the assembler can handle the documented syntax from the ARM ARM. +@ These tests test instruction encodings specific to ARMv7E-M. + +@------------------------------------------------------------------------------ +@ MSR +@------------------------------------------------------------------------------ + + msr apsr_g, r0 + msr apsr_nzcvqg, r0 + msr iapsr_g, r0 + msr iapsr_nzcvqg, r0 + msr eapsr_g, r0 + msr eapsr_nzcvqg, r0 + msr xpsr_g, r0 + msr xpsr_nzcvqg, r0 + +@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84] +@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c] +@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84] +@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c] +@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84] +@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c] +@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84] +@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c] +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr apsr_g, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr apsr_nzcvqg, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr iapsr_g, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr iapsr_nzcvqg, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr eapsr_g, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr eapsr_nzcvqg, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr xpsr_g, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr xpsr_nzcvqg, r0 +@ CHECK-V7M-NEXT: ^ diff --git a/test/MC/ARM/v8_IT_manual.s b/test/MC/ARM/v8_IT_manual.s index 4b63aa82dd68..160e98ce8b4f 100644 --- a/test/MC/ARM/v8_IT_manual.s +++ b/test/MC/ARM/v8_IT_manual.s @@ -554,11 +554,11 @@ pushge {r1, r3, r7} @ PUSH, encoding T2 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -pushge {r1, r13, r7} +pushge {r1, r3, r7} @ PUSH, encoding T3 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -pushge {r13} +pushge {r3} @ REV, encoding T1 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block @@ -614,9 +614,10 @@ stmge r1!, {r2, r3} @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge stmge r1, {r2, r3} +@ STM, encoding T3 (32-bit) @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block it ge -stmge r1!, {r2, r13} +stmge r1!, {r2, r3} @ LDM, encoding T1 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block diff --git a/test/MC/ARM/vfp4.s b/test/MC/ARM/vfp4.s index 8b1b0e0c538b..1563b5aef71e 100644 --- a/test/MC/ARM/vfp4.s +++ b/test/MC/ARM/vfp4.s @@ -6,7 +6,7 @@ @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee] @ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b] -@ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17 vfma.f64 d16, d18, d17 @@ -17,7 +17,7 @@ vfma.f32 s2, s4, s0 @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2] @ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c] -@ THUMB_V7EM-ERRORS: error: instruction requires: NEON +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17 vfma.f32 d16, d18, d17 @@ -29,7 +29,7 @@ vfma.f32 q2, q4, q0 @ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee] @ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b] -@ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17 vfnma.f64 d16, d18, d17 @@ -40,7 +40,7 @@ vfnma.f32 s2, s4, s0 @ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee] @ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b] -@ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17 vfms.f64 d16, d18, d17 @@ -51,7 +51,7 @@ vfms.f32 s2, s4, s0 @ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2] @ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c] -@ THUMB_V7EM-ERRORS: error: instruction requires: NEON +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17 vfms.f32 d16, d18, d17 @@ -63,7 +63,7 @@ vfms.f32 q2, q4, q0 @ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee] @ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b] -@ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17 vfnms.f64 d16, d18, d17 diff --git a/test/MC/ARM/virtexts-arm.s b/test/MC/ARM/virtexts-arm.s new file mode 100644 index 000000000000..a67a8fea5c6f --- /dev/null +++ b/test/MC/ARM/virtexts-arm.s @@ -0,0 +1,42 @@ +# RUN: llvm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM + + hvc #1 + hvc #7 + hvc #257 + hvc #65535 +# CHECK-ARM: [0x71,0x00,0x40,0xe1] +# CHECK-ARM: [0x77,0x00,0x40,0xe1] +# CHECK-ARM: [0x71,0x10,0x40,0xe1] +# CHECK-ARM: [0x7f,0xff,0x4f,0xe1] + + eret + ereteq + eretne + ereths + eretlo + eretmi + eretpl + eretvs + eretvc + erethi + eretls + eretge + eretlt + eretgt + eretle +# CHECK-ARM: [0x6e,0x00,0x60,0xe1] +# CHECK-ARM: [0x6e,0x00,0x60,0x01] +# CHECK-ARM: [0x6e,0x00,0x60,0x11] +# CHECK-ARM: [0x6e,0x00,0x60,0x21] +# CHECK-ARM: [0x6e,0x00,0x60,0x31] +# CHECK-ARM: [0x6e,0x00,0x60,0x41] +# CHECK-ARM: [0x6e,0x00,0x60,0x51] +# CHECK-ARM: [0x6e,0x00,0x60,0x61] +# CHECK-ARM: [0x6e,0x00,0x60,0x71] +# CHECK-ARM: [0x6e,0x00,0x60,0x81] +# CHECK-ARM: [0x6e,0x00,0x60,0x91] +# CHECK-ARM: [0x6e,0x00,0x60,0xa1] +# CHECK-ARM: [0x6e,0x00,0x60,0xb1] +# CHECK-ARM: [0x6e,0x00,0x60,0xc1] +# CHECK-ARM: [0x6e,0x00,0x60,0xd1] + diff --git a/test/MC/ARM/virtexts-thumb.s b/test/MC/ARM/virtexts-thumb.s new file mode 100644 index 000000000000..d911e1dfb1d7 --- /dev/null +++ b/test/MC/ARM/virtexts-thumb.s @@ -0,0 +1,59 @@ +# RUN: llvm-mc -triple thumbv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-THUMB + + hvc #1 + hvc #7 + hvc #257 + hvc #65535 +# CHECK-THUMB: [0xe0,0xf7,0x01,0x80] +# CHECK-THUMB: [0xe0,0xf7,0x07,0x80] +# CHECK-THUMB: [0xe0,0xf7,0x01,0x81] +# CHECK-THUMB: [0xef,0xf7,0xff,0x8f] + + hvc.w #1 + hvc.w #7 + hvc.w #257 + hvc.w #65535 +# CHECK-THUMB: [0xe0,0xf7,0x01,0x80] +# CHECK-THUMB: [0xe0,0xf7,0x07,0x80] +# CHECK-THUMB: [0xe0,0xf7,0x01,0x81] +# CHECK-THUMB: [0xef,0xf7,0xff,0x8f] + + eret + it eq; ereteq + it ne; eretne + it hs; ereths + it lo; eretlo + it mi; eretmi + it pl; eretpl + it vs; eretvs + it vc; eretvc + it hi; erethi + it ls; eretls + it ge; eretge + it lt; eretlt + it gt; eretgt + it le; eretle +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] + +# SUBS PC, LR, #0 should have the same encoding as ERET. +# The conditional forms can't be tested becuse the ARM assembler parser doesn't +# accept SUBS<cond> PC, LR, #<imm>, only the unconditonal form is allowed. This +# is due to the way that the custom parser handles optional operands; see the +# FIXME in ARM/AsmParser/ARMAsmParser.cpp. + + subs pc, lr, #0 +# CHECK-THUMB: [0xde,0xf3,0x00,0x8f] diff --git a/test/MC/ARM/vorr-vbic-illegal-cases.s b/test/MC/ARM/vorr-vbic-illegal-cases.s index 16ab6b5bc74b..673098ad5a07 100644 --- a/test/MC/ARM/vorr-vbic-illegal-cases.s +++ b/test/MC/ARM/vorr-vbic-illegal-cases.s @@ -1,6 +1,13 @@ @ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s .text + vorr.i32 d2, #0xffffffff + vorr.i32 q2, #0xffffffff + vorr.i32 d2, #0xabababab + vorr.i32 q2, #0xabababab + vorr.i16 q2, #0xabab + vorr.i16 q2, #0xabab + @ CHECK: error: invalid operand for instruction @ CHECK: vorr.i32 d2, #0xffffffff @ CHECK: error: invalid operand for instruction @@ -14,6 +21,13 @@ @ CHECK: error: invalid operand for instruction @ CHECK: vorr.i16 q2, #0xabab + vbic.i32 d2, #0xffffffff + vbic.i32 q2, #0xffffffff + vbic.i32 d2, #0xabababab + vbic.i32 q2, #0xabababab + vbic.i16 d2, #0xabab + vbic.i16 q2, #0xabab + @ CHECK: error: invalid operand for instruction @ CHECK: vbic.i32 d2, #0xffffffff @ CHECK: error: invalid operand for instruction @@ -27,16 +41,25 @@ @ CHECK: error: invalid operand for instruction @ CHECK: vbic.i16 q2, #0xabab - vorr.i32 d2, #0xffffffff - vorr.i32 q2, #0xffffffff - vorr.i32 d2, #0xabababab - vorr.i32 q2, #0xabababab - vorr.i16 q2, #0xabab - vorr.i16 q2, #0xabab + vbic.i32 d2, #0x03ffffff + vbic.i32 q2, #0x03ffff + vbic.i32 d2, #0x03ff + vbic.i32 d2, #0xff00ff + vbic.i16 d2, #0x03ff + vbic.i16 q2, #0xf0f0 + vbic.i16 q2, #0xf0f0f0 - vbic.i32 d2, #0xffffffff - vbic.i32 q2, #0xffffffff - vbic.i32 d2, #0xabababab - vbic.i32 q2, #0xabababab - vbic.i16 d2, #0xabab - vbic.i16 q2, #0xabab +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 d2, #0x03ffffff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 q2, #0x03ffff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 d2, #0x03ff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 d2, #0xff00ff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i16 d2, #0x03ff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i16 q2, #0xf0f0 +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i16 q2, #0xf0f0f0 |