diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2014-11-24 09:08:18 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2014-11-24 09:08:18 +0000 |
| commit | 5ca98fd98791947eba83a1ed3f2c8191ef7afa6c (patch) | |
| tree | f5944309621cee4fe0976be6f9ac619b7ebfc4c2 /test/Transforms | |
| parent | 68bcb7db193e4bc81430063148253d30a791023e (diff) | |
Notes
Diffstat (limited to 'test/Transforms')
395 files changed, 17849 insertions, 887 deletions
diff --git a/test/Transforms/AddDiscriminators/basic.ll b/test/Transforms/AddDiscriminators/basic.ll new file mode 100644 index 000000000000..b12cbee6adb5 --- /dev/null +++ b/test/Transforms/AddDiscriminators/basic.ll @@ -0,0 +1,59 @@ +; RUN: opt < %s -add-discriminators -S | FileCheck %s + +; Basic DWARF discriminator test. All the instructions in block +; 'if.then' should have a different discriminator value than +; the conditional branch at the end of block 'entry'. +; +; Original code: +; +; void foo(int i) { +; int x; +; if (i < 10) x = i; +; } + +define void @foo(i32 %i) #0 { +entry: + %i.addr = alloca i32, align 4 + %x = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %0 = load i32* %i.addr, align 4, !dbg !10 + %cmp = icmp slt i32 %0, 10, !dbg !10 + br i1 %cmp, label %if.then, label %if.end, !dbg !10 + +if.then: ; preds = %entry + %1 = load i32* %i.addr, align 4, !dbg !10 +; CHECK: %1 = load i32* %i.addr, align 4, !dbg !12 + + store i32 %1, i32* %x, align 4, !dbg !10 +; CHECK: store i32 %1, i32* %x, align 4, !dbg !12 + + br label %if.end, !dbg !10 +; CHECK: br label %if.end, !dbg !12 + +if.end: ; preds = %if.then, %entry + ret void, !dbg !12 +} + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [basic.c] [DW_LANG_C99] +!1 = metadata !{metadata !"basic.c", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32)* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [basic.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!8 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!9 = metadata !{metadata !"clang version 3.5 "} +!10 = metadata !{i32 3, i32 0, metadata !11, null} +!11 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [basic.c] +!12 = metadata !{i32 4, i32 0, metadata !4, null} + +; CHECK: !12 = metadata !{i32 3, i32 0, metadata !13, null} +; CHECK: !13 = metadata !{i32 786443, metadata !1, metadata !11, i32 3, i32 0, i32 1, i32 0} ; [ DW_TAG_lexical_block ] [./basic.c] +; CHECK: !14 = metadata !{i32 4, i32 0, metadata !4, null} diff --git a/test/Transforms/AddDiscriminators/first-only.ll b/test/Transforms/AddDiscriminators/first-only.ll new file mode 100644 index 000000000000..f3b0357e5766 --- /dev/null +++ b/test/Transforms/AddDiscriminators/first-only.ll @@ -0,0 +1,82 @@ +; RUN: opt < %s -add-discriminators -S | FileCheck %s + +; Test that the only instructions that receive a new discriminator in +; the block 'if.then' are those that share the same line number as +; the branch in 'entry'. +; +; Original code: +; +; void foo(int i) { +; int x, y; +; if (i < 10) { x = i; +; y = -i; +; } +; } + +define void @foo(i32 %i) #0 { +entry: + %i.addr = alloca i32, align 4 + %x = alloca i32, align 4 + %y = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %0 = load i32* %i.addr, align 4, !dbg !10 + %cmp = icmp slt i32 %0, 10, !dbg !10 + br i1 %cmp, label %if.then, label %if.end, !dbg !10 + +if.then: ; preds = %entry + %1 = load i32* %i.addr, align 4, !dbg !12 + store i32 %1, i32* %x, align 4, !dbg !12 + + %2 = load i32* %i.addr, align 4, !dbg !14 +; CHECK: %2 = load i32* %i.addr, align 4, !dbg !15 + + %sub = sub nsw i32 0, %2, !dbg !14 +; CHECK: %sub = sub nsw i32 0, %2, !dbg !15 + + store i32 %sub, i32* %y, align 4, !dbg !14 +; CHECK: store i32 %sub, i32* %y, align 4, !dbg !15 + + br label %if.end, !dbg !15 +; CHECK: br label %if.end, !dbg !16 + +if.end: ; preds = %if.then, %entry + ret void, !dbg !16 +; CHECK: ret void, !dbg !17 +} + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5 (trunk 199750) (llvm/trunk 199751)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [first-only.c] [DW_LANG_C99] +!1 = metadata !{metadata !"first-only.c", metadata !"."} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32)* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [first-only.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!8 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!9 = metadata !{metadata !"clang version 3.5 (trunk 199750) (llvm/trunk 199751)"} +!10 = metadata !{i32 3, i32 0, metadata !11, null} + +!11 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [first-only.c] +; CHECK: !11 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 0, i32 0} + +!12 = metadata !{i32 3, i32 0, metadata !13, null} + +!13 = metadata !{i32 786443, metadata !1, metadata !11, i32 3, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [first-only.c] +; CHECK: !13 = metadata !{i32 786443, metadata !1, metadata !14, i32 3, i32 0, i32 1, i32 0} ; [ DW_TAG_lexical_block ] [./first-only.c] + +!14 = metadata !{i32 4, i32 0, metadata !13, null} +; CHECK: !14 = metadata !{i32 786443, metadata !1, metadata !11, i32 3, i32 0, i32 1} + +!15 = metadata !{i32 5, i32 0, metadata !13, null} +; CHECK: !15 = metadata !{i32 4, i32 0, metadata !14, null} + +!16 = metadata !{i32 6, i32 0, metadata !4, null} +; CHECK: !16 = metadata !{i32 5, i32 0, metadata !14, null} +; CHECK: !17 = metadata !{i32 6, i32 0, metadata !4, null} + diff --git a/test/Transforms/AddDiscriminators/multiple.ll b/test/Transforms/AddDiscriminators/multiple.ll new file mode 100644 index 000000000000..0241a0c1a0b1 --- /dev/null +++ b/test/Transforms/AddDiscriminators/multiple.ll @@ -0,0 +1,71 @@ +; RUN: opt < %s -add-discriminators -S | FileCheck %s + +; Discriminator support for multiple CFG paths on the same line. +; +; void foo(int i) { +; int x; +; if (i < 10) x = i; else x = -i; +; } +; +; The two stores inside the if-then-else line must have different discriminator +; values. + +define void @foo(i32 %i) #0 { +entry: + %i.addr = alloca i32, align 4 + %x = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %0 = load i32* %i.addr, align 4, !dbg !10 + %cmp = icmp slt i32 %0, 10, !dbg !10 + br i1 %cmp, label %if.then, label %if.else, !dbg !10 + +if.then: ; preds = %entry + %1 = load i32* %i.addr, align 4, !dbg !10 +; CHECK: %1 = load i32* %i.addr, align 4, !dbg !12 + + store i32 %1, i32* %x, align 4, !dbg !10 +; CHECK: store i32 %1, i32* %x, align 4, !dbg !12 + + br label %if.end, !dbg !10 +; CHECK: br label %if.end, !dbg !12 + +if.else: ; preds = %entry + %2 = load i32* %i.addr, align 4, !dbg !10 +; CHECK: %2 = load i32* %i.addr, align 4, !dbg !14 + + %sub = sub nsw i32 0, %2, !dbg !10 +; CHECK: %sub = sub nsw i32 0, %2, !dbg !14 + + store i32 %sub, i32* %x, align 4, !dbg !10 +; CHECK: store i32 %sub, i32* %x, align 4, !dbg !14 + + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void, !dbg !12 +} + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5 (trunk 199750) (llvm/trunk 199751)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [multiple.c] [DW_LANG_C99] +!1 = metadata !{metadata !"multiple.c", metadata !"."} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32)* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [multiple.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!8 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!9 = metadata !{metadata !"clang version 3.5 (trunk 199750) (llvm/trunk 199751)"} +!10 = metadata !{i32 3, i32 0, metadata !11, null} +!11 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [multiple.c] +!12 = metadata !{i32 4, i32 0, metadata !4, null} + +; CHECK: !12 = metadata !{i32 3, i32 0, metadata !13, null} +; CHECK: !13 = metadata !{i32 786443, metadata !1, metadata !11, i32 3, i32 0, i32 1, i32 0} ; [ DW_TAG_lexical_block ] [./multiple.c] +; CHECK: !14 = metadata !{i32 3, i32 0, metadata !15, null} +; CHECK: !15 = metadata !{i32 786443, metadata !1, metadata !11, i32 3, i32 0, i32 2, i32 1} ; [ DW_TAG_lexical_block ] [./multiple.c] diff --git a/test/Transforms/AddDiscriminators/no-discriminators.ll b/test/Transforms/AddDiscriminators/no-discriminators.ll new file mode 100644 index 000000000000..f7b45e295551 --- /dev/null +++ b/test/Transforms/AddDiscriminators/no-discriminators.ll @@ -0,0 +1,71 @@ +; RUN: opt < %s -add-discriminators -S | FileCheck %s + +; We should not generate discriminators for DWARF versions prior to 4. +; +; Original code: +; +; int foo(long i) { +; if (i < 5) return 2; else return 90; +; } +; +; None of the !dbg nodes associated with the if() statement should be +; altered. If they are, it means that the discriminators pass added a +; new lexical scope. + +define i32 @foo(i64 %i) #0 { +entry: + %retval = alloca i32, align 4 + %i.addr = alloca i64, align 8 + store i64 %i, i64* %i.addr, align 8 + call void @llvm.dbg.declare(metadata !{i64* %i.addr}, metadata !13), !dbg !14 + %0 = load i64* %i.addr, align 8, !dbg !15 +; CHECK: %0 = load i64* %i.addr, align 8, !dbg !15 + %cmp = icmp slt i64 %0, 5, !dbg !15 +; CHECK: %cmp = icmp slt i64 %0, 5, !dbg !15 + br i1 %cmp, label %if.then, label %if.else, !dbg !15 +; CHECK: br i1 %cmp, label %if.then, label %if.else, !dbg !15 + +if.then: ; preds = %entry + store i32 2, i32* %retval, !dbg !15 + br label %return, !dbg !15 + +if.else: ; preds = %entry + store i32 90, i32* %retval, !dbg !15 + br label %return, !dbg !15 + +return: ; preds = %if.else, %if.then + %1 = load i32* %retval, !dbg !17 + ret i32 %1, !dbg !17 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata) #1 + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!10, !11} +!llvm.ident = !{!12} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5.0 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [./no-discriminators] [DW_LANG_C99] +!1 = metadata !{metadata !"no-discriminators", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i64)* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [./no-discriminators] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{metadata !8, metadata !9} +!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = metadata !{i32 786468, null, null, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed] +!10 = metadata !{i32 2, metadata !"Dwarf Version", i32 2} +; CHECK: !10 = metadata !{i32 2, metadata !"Dwarf Version", i32 2} +!11 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!12 = metadata !{metadata !"clang version 3.5.0 "} +!13 = metadata !{i32 786689, metadata !4, metadata !"i", metadata !5, i32 16777217, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [i] [line 1] +!14 = metadata !{i32 1, i32 0, metadata !4, null} +!15 = metadata !{i32 2, i32 0, metadata !16, null} +; CHECK: !15 = metadata !{i32 2, i32 0, metadata !16, null} +!16 = metadata !{i32 786443, metadata !1, metadata !4, i32 2, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [./no-discriminators] +; CHECK: !16 = metadata !{i32 786443, metadata !1, metadata !4, i32 2, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [./no-discriminators] +!17 = metadata !{i32 3, i32 0, metadata !4, null} diff --git a/test/Transforms/ArgumentPromotion/basictest.ll b/test/Transforms/ArgumentPromotion/basictest.ll index d3d21fcabee1..8f78b98437bc 100644 --- a/test/Transforms/ArgumentPromotion/basictest.ll +++ b/test/Transforms/ArgumentPromotion/basictest.ll @@ -1,23 +1,29 @@ -; RUN: opt < %s -basicaa -argpromotion -mem2reg -S | not grep alloca +; RUN: opt < %s -basicaa -argpromotion -mem2reg -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" + define internal i32 @test(i32* %X, i32* %Y) { - %A = load i32* %X ; <i32> [#uses=1] - %B = load i32* %Y ; <i32> [#uses=1] - %C = add i32 %A, %B ; <i32> [#uses=1] - ret i32 %C +; CHECK-LABEL: define internal i32 @test(i32 %X.val, i32 %Y.val) + %A = load i32* %X + %B = load i32* %Y + %C = add i32 %A, %B + ret i32 %C } define internal i32 @caller(i32* %B) { - %A = alloca i32 ; <i32*> [#uses=2] - store i32 1, i32* %A - %C = call i32 @test( i32* %A, i32* %B ) ; <i32> [#uses=1] - ret i32 %C +; CHECK-LABEL: define internal i32 @caller(i32 %B.val1) + %A = alloca i32 + store i32 1, i32* %A + %C = call i32 @test(i32* %A, i32* %B) +; CHECK: call i32 @test(i32 1, i32 %B.val1) + ret i32 %C } define i32 @callercaller() { - %B = alloca i32 ; <i32*> [#uses=2] - store i32 2, i32* %B - %X = call i32 @caller( i32* %B ) ; <i32> [#uses=1] - ret i32 %X +; CHECK-LABEL: define i32 @callercaller() + %B = alloca i32 + store i32 2, i32* %B + %X = call i32 @caller(i32* %B) +; CHECK: call i32 @caller(i32 2) + ret i32 %X } diff --git a/test/Transforms/ArgumentPromotion/byval-2.ll b/test/Transforms/ArgumentPromotion/byval-2.ll index 368c6896cf82..b412f5ef0856 100644 --- a/test/Transforms/ArgumentPromotion/byval-2.ll +++ b/test/Transforms/ArgumentPromotion/byval-2.ll @@ -1,26 +1,31 @@ -; RUN: opt < %s -argpromotion -S | grep -F "i32* byval" | count 2 -; Argpromote + scalarrepl should change this to passing the two integers by value. +; RUN: opt < %s -argpromotion -S | FileCheck %s - %struct.ss = type { i32, i64 } +; Arg promotion eliminates the struct argument. +; FIXME: Should it eliminate the i32* argument? + +%struct.ss = type { i32, i64 } define internal void @f(%struct.ss* byval %b, i32* byval %X) nounwind { +; CHECK-LABEL: define internal void @f(i32 %b.0, i64 %b.1, i32* byval %X) entry: - %tmp = getelementptr %struct.ss* %b, i32 0, i32 0 - %tmp1 = load i32* %tmp, align 4 - %tmp2 = add i32 %tmp1, 1 - store i32 %tmp2, i32* %tmp, align 4 + %tmp = getelementptr %struct.ss* %b, i32 0, i32 0 + %tmp1 = load i32* %tmp, align 4 + %tmp2 = add i32 %tmp1, 1 + store i32 %tmp2, i32* %tmp, align 4 - store i32 0, i32* %X - ret void + store i32 0, i32* %X + ret void } define i32 @test(i32* %X) { +; CHECK-LABEL: define i32 @test entry: - %S = alloca %struct.ss ; <%struct.ss*> [#uses=4] - %tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 1, i32* %tmp1, align 8 - %tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1 ; <i64*> [#uses=1] - store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S, i32* byval %X) - ret i32 0 + %S = alloca %struct.ss + %tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0 + store i32 1, i32* %tmp1, align 8 + %tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1 + store i64 2, i64* %tmp4, align 4 + call void @f( %struct.ss* byval %S, i32* byval %X) +; CHECK: call void @f(i32 %{{.*}}, i64 %{{.*}}, i32* byval %{{.*}}) + ret i32 0 } diff --git a/test/Transforms/ArgumentPromotion/byval.ll b/test/Transforms/ArgumentPromotion/byval.ll index 44b26fc2f30c..27305e92068d 100644 --- a/test/Transforms/ArgumentPromotion/byval.ll +++ b/test/Transforms/ArgumentPromotion/byval.ll @@ -1,25 +1,28 @@ -; RUN: opt < %s -argpromotion -scalarrepl -S | not grep load +; RUN: opt < %s -argpromotion -S | FileCheck %s + target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" -; Argpromote + scalarrepl should change this to passing the two integers by value. - %struct.ss = type { i32, i64 } +%struct.ss = type { i32, i64 } define internal void @f(%struct.ss* byval %b) nounwind { +; CHECK-LABEL: define internal void @f(i32 %b.0, i64 %b.1) entry: - %tmp = getelementptr %struct.ss* %b, i32 0, i32 0 ; <i32*> [#uses=2] - %tmp1 = load i32* %tmp, align 4 ; <i32> [#uses=1] - %tmp2 = add i32 %tmp1, 1 ; <i32> [#uses=1] - store i32 %tmp2, i32* %tmp, align 4 - ret void + %tmp = getelementptr %struct.ss* %b, i32 0, i32 0 ; <i32*> [#uses=2] + %tmp1 = load i32* %tmp, align 4 ; <i32> [#uses=1] + %tmp2 = add i32 %tmp1, 1 ; <i32> [#uses=1] + store i32 %tmp2, i32* %tmp, align 4 + ret void } define i32 @main() nounwind { +; CHECK-LABEL: define i32 @main entry: - %S = alloca %struct.ss ; <%struct.ss*> [#uses=4] - %tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 1, i32* %tmp1, align 8 - %tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1 ; <i64*> [#uses=1] - store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S ) nounwind - ret i32 0 + %S = alloca %struct.ss ; <%struct.ss*> [#uses=4] + %tmp1 = getelementptr %struct.ss* %S, i32 0, i32 0 ; <i32*> [#uses=1] + store i32 1, i32* %tmp1, align 8 + %tmp4 = getelementptr %struct.ss* %S, i32 0, i32 1 ; <i64*> [#uses=1] + store i64 2, i64* %tmp4, align 4 + call void @f( %struct.ss* byval %S ) nounwind +; CHECK: call void @f(i32 %{{.*}}, i64 %{{.*}}) + ret i32 0 } diff --git a/test/Transforms/ArgumentPromotion/dbg.ll b/test/Transforms/ArgumentPromotion/dbg.ll new file mode 100644 index 000000000000..70503afb5870 --- /dev/null +++ b/test/Transforms/ArgumentPromotion/dbg.ll @@ -0,0 +1,22 @@ +; RUN: opt < %s -argpromotion -S | FileCheck %s +; CHECK: call void @test(), !dbg [[DBG_LOC:![0-9]]] +; CHECK: [[TEST_FN:.*]] = {{.*}} void ()* @test +; CHECK: [[DBG_LOC]] = metadata !{i32 8, i32 0, metadata [[TEST_FN]], null} + +define internal void @test(i32* %X) { + ret void +} + +define void @caller() { + call void @test(i32* null), !dbg !1 + ret void +} + +!llvm.module.flags = !{!0} +!llvm.dbg.cu = !{!3} + +!0 = metadata !{i32 2, metadata !"Debug Info Version", i32 1} +!1 = metadata !{i32 8, i32 0, metadata !2, null} +!2 = metadata !{i32 786478, null, null, metadata !"test", metadata !"test", metadata !"", i32 3, null, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*)* @test, null, null, null, i32 3} +!3 = metadata !{i32 786449, null, i32 4, metadata !"clang version 3.5.0 ", i1 false, metadata !"", i32 0, null, null, metadata !4, null, null, metadata !"", i32 2} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/pr20038/reduce/<stdin>] [DW_LANG_C_plus_plus] +!4 = metadata !{metadata !2} diff --git a/test/Transforms/ArgumentPromotion/inalloca.ll b/test/Transforms/ArgumentPromotion/inalloca.ll new file mode 100644 index 000000000000..089a78f6b319 --- /dev/null +++ b/test/Transforms/ArgumentPromotion/inalloca.ll @@ -0,0 +1,49 @@ +; RUN: opt %s -argpromotion -scalarrepl -S | FileCheck %s + +target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" + +%struct.ss = type { i32, i32 } + +; Argpromote + scalarrepl should change this to passing the two integers by value. +define internal i32 @f(%struct.ss* inalloca %s) { +entry: + %f0 = getelementptr %struct.ss* %s, i32 0, i32 0 + %f1 = getelementptr %struct.ss* %s, i32 0, i32 1 + %a = load i32* %f0, align 4 + %b = load i32* %f1, align 4 + %r = add i32 %a, %b + ret i32 %r +} +; CHECK-LABEL: define internal i32 @f +; CHECK-NOT: load +; CHECK: ret + +define i32 @main() { +entry: + %S = alloca inalloca %struct.ss + %f0 = getelementptr %struct.ss* %S, i32 0, i32 0 + %f1 = getelementptr %struct.ss* %S, i32 0, i32 1 + store i32 1, i32* %f0, align 4 + store i32 2, i32* %f1, align 4 + %r = call i32 @f(%struct.ss* inalloca %S) + ret i32 %r +} +; CHECK-LABEL: define i32 @main +; CHECK-NOT: load +; CHECK: ret + +; Argpromote can't promote %a because of the icmp use. +define internal i1 @g(%struct.ss* %a, %struct.ss* inalloca %b) nounwind { +; CHECK: define internal i1 @g(%struct.ss* %a, %struct.ss* inalloca %b) +entry: + %c = icmp eq %struct.ss* %a, %b + ret i1 %c +} + +define i32 @test() { +entry: + %S = alloca inalloca %struct.ss + %c = call i1 @g(%struct.ss* %S, %struct.ss* inalloca %S) +; CHECK: call i1 @g(%struct.ss* %S, %struct.ss* inalloca %S) + ret i32 0 +} diff --git a/test/Transforms/ArgumentPromotion/tail.ll b/test/Transforms/ArgumentPromotion/tail.ll new file mode 100644 index 000000000000..43b8996ca18a --- /dev/null +++ b/test/Transforms/ArgumentPromotion/tail.ll @@ -0,0 +1,20 @@ +; RUN: opt %s -argpromotion -S -o - | FileCheck %s +; PR14710 + +%pair = type { i32, i32 } + +declare i8* @foo(%pair*) + +define internal void @bar(%pair* byval %Data) { +; CHECK: define internal void @bar(i32 %Data.0, i32 %Data.1) +; CHECK: %Data = alloca %pair +; CHECK-NOT: tail +; CHECK: call i8* @foo(%pair* %Data) + tail call i8* @foo(%pair* %Data) + ret void +} + +define void @zed(%pair* byval %Data) { + call void @bar(%pair* byval %Data) + ret void +} diff --git a/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll b/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll new file mode 100644 index 000000000000..6a93016fc26e --- /dev/null +++ b/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v7.ll @@ -0,0 +1,364 @@ +; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -atomic-ll-sc %s | FileCheck %s + +define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) { +; CHECK-LABEL: @test_atomic_xchg_i8 +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 +; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK-NOT: fence +; CHECK: ret i8 [[OLDVAL]] + %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic + ret i8 %res +} + +define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) { +; CHECK-LABEL: @test_atomic_add_i16 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 +; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend +; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence seq_cst +; CHECK: ret i16 [[OLDVAL]] + %res = atomicrmw add i16* %ptr, i16 %addend seq_cst + ret i16 %res +} + +define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) { +; CHECK-LABEL: @test_atomic_sub_i32 +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr) +; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence acquire +; CHECK: ret i32 [[OLDVAL]] + %res = atomicrmw sub i32* %ptr, i32 %subend acquire + ret i32 %res +} + +define i8 @test_atomic_and_i8(i8* %ptr, i8 %andend) { +; CHECK-LABEL: @test_atomic_and_i8 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 +; CHECK: [[NEWVAL:%.*]] = and i8 [[OLDVAL]], %andend +; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK-NOT: fence +; CHECK: ret i8 [[OLDVAL]] + %res = atomicrmw and i8* %ptr, i8 %andend release + ret i8 %res +} + +define i16 @test_atomic_nand_i16(i16* %ptr, i16 %nandend) { +; CHECK-LABEL: @test_atomic_nand_i16 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 +; CHECK: [[NEWVAL_TMP:%.*]] = and i16 [[OLDVAL]], %nandend +; CHECK: [[NEWVAL:%.*]] = xor i16 [[NEWVAL_TMP]], -1 +; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence seq_cst +; CHECK: ret i16 [[OLDVAL]] + %res = atomicrmw nand i16* %ptr, i16 %nandend seq_cst + ret i16 %res +} + +define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) { +; CHECK-LABEL: @test_atomic_or_i64 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* +; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]]) +; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 +; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 +; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 +; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64 +; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32 +; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]] +; CHECK: [[NEWVAL:%.*]] = or i64 [[OLDVAL]], %orend +; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32 +; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32 +; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 +; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence seq_cst +; CHECK: ret i64 [[OLDVAL]] + %res = atomicrmw or i64* %ptr, i64 %orend seq_cst + ret i64 %res +} + +define i8 @test_atomic_xor_i8(i8* %ptr, i8 %xorend) { +; CHECK-LABEL: @test_atomic_xor_i8 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 +; CHECK: [[NEWVAL:%.*]] = xor i8 [[OLDVAL]], %xorend +; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence seq_cst +; CHECK: ret i8 [[OLDVAL]] + %res = atomicrmw xor i8* %ptr, i8 %xorend seq_cst + ret i8 %res +} + +define i8 @test_atomic_max_i8(i8* %ptr, i8 %maxend) { +; CHECK-LABEL: @test_atomic_max_i8 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 +; CHECK: [[WANT_OLD:%.*]] = icmp sgt i8 [[OLDVAL]], %maxend +; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %maxend +; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence seq_cst +; CHECK: ret i8 [[OLDVAL]] + %res = atomicrmw max i8* %ptr, i8 %maxend seq_cst + ret i8 %res +} + +define i8 @test_atomic_min_i8(i8* %ptr, i8 %minend) { +; CHECK-LABEL: @test_atomic_min_i8 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 +; CHECK: [[WANT_OLD:%.*]] = icmp sle i8 [[OLDVAL]], %minend +; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %minend +; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence seq_cst +; CHECK: ret i8 [[OLDVAL]] + %res = atomicrmw min i8* %ptr, i8 %minend seq_cst + ret i8 %res +} + +define i8 @test_atomic_umax_i8(i8* %ptr, i8 %umaxend) { +; CHECK-LABEL: @test_atomic_umax_i8 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 +; CHECK: [[WANT_OLD:%.*]] = icmp ugt i8 [[OLDVAL]], %umaxend +; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %umaxend +; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence seq_cst +; CHECK: ret i8 [[OLDVAL]] + %res = atomicrmw umax i8* %ptr, i8 %umaxend seq_cst + ret i8 %res +} + +define i8 @test_atomic_umin_i8(i8* %ptr, i8 %uminend) { +; CHECK-LABEL: @test_atomic_umin_i8 +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 +; CHECK: [[WANT_OLD:%.*]] = icmp ule i8 [[OLDVAL]], %uminend +; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %uminend +; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK: fence seq_cst +; CHECK: ret i8 [[OLDVAL]] + %res = atomicrmw umin i8* %ptr, i8 %uminend seq_cst + ret i8 %res +} + +define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) { +; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] + +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8 +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK: fence seq_cst +; CHECK: br label %[[DONE:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK: fence seq_cst +; CHECK: br label %[[DONE]] + +; CHECK: [[DONE]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i8 [[OLDVAL]] + + %pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst + %old = extractvalue { i8, i1 } %pairold, 0 + ret i8 %old +} + +define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) { +; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic +; CHECK: fence release +; CHECK: br label %[[LOOP:.*]] + +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) +; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK: fence seq_cst +; CHECK: br label %[[DONE:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK-NOT: fence +; CHECK: br label %[[DONE]] + +; CHECK: [[DONE]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i16 [[OLDVAL]] + + %pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic + %old = extractvalue { i16, i1 } %pairold, 0 + ret i16 %old +} + +define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) { +; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] + +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr) +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr) +; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK: fence acquire +; CHECK: br label %[[DONE:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK: fence acquire +; CHECK: br label %[[DONE]] + +; CHECK: [[DONE]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i32 [[OLDVAL]] + + %pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire + %old = extractvalue { i32, i1 } %pairold, 0 + ret i32 %old +} + +define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) { +; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] + +; CHECK: [[LOOP]]: +; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* +; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]]) +; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 +; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 +; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 +; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64 +; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32 +; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]] +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32 +; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32 +; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 +; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) +; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK-NOT: fence +; CHECK: br label %[[DONE:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK-NOT: fence +; CHECK: br label %[[DONE]] + +; CHECK: [[DONE]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i64 [[OLDVAL]] + + %pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic + %old = extractvalue { i64, i1 } %pairold, 0 + ret i64 %old +}
\ No newline at end of file diff --git a/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll b/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll new file mode 100644 index 000000000000..8092c1010ff5 --- /dev/null +++ b/test/Transforms/AtomicExpandLoadLinked/ARM/atomic-expansion-v8.ll @@ -0,0 +1,226 @@ +; RUN: opt -S -o - -mtriple=armv8-linux-gnueabihf -atomic-ll-sc %s | FileCheck %s + +define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) { +; CHECK-LABEL: @test_atomic_xchg_i8 +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 +; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK-NOT: fence +; CHECK: ret i8 [[OLDVAL]] + %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic + ret i8 %res +} + +define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) { +; CHECK-LABEL: @test_atomic_add_i16 +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 +; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend +; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK-NOT: fence +; CHECK: ret i16 [[OLDVAL]] + %res = atomicrmw add i16* %ptr, i16 %addend seq_cst + ret i16 %res +} + +define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) { +; CHECK-LABEL: @test_atomic_sub_i32 +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* %ptr) +; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* %ptr) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK-NOT: fence +; CHECK: ret i32 [[OLDVAL]] + %res = atomicrmw sub i32* %ptr, i32 %subend acquire + ret i32 %res +} + +define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) { +; CHECK-LABEL: @test_atomic_or_i64 +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* +; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldaexd(i8* [[PTR8]]) +; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 +; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 +; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 +; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64 +; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32 +; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]] +; CHECK: [[NEWVAL:%.*]] = or i64 [[OLDVAL]], %orend +; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32 +; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32 +; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 +; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) +; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] +; CHECK: [[END]]: +; CHECK-NOT: fence +; CHECK: ret i64 [[OLDVAL]] + %res = atomicrmw or i64* %ptr, i64 %orend seq_cst + ret i64 %res +} + +define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) { +; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] + +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i8(i8* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8 +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i8(i32 [[NEWVAL32]], i8* %ptr) +; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK-NOT: fence_cst +; CHECK: br label %[[DONE:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK-NOT: fence_cst +; CHECK: br label %[[DONE]] + +; CHECK: [[DONE]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i8 [[OLDVAL]] + + %pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst + %old = extractvalue { i8, i1 } %pairold, 0 + ret i8 %old +} + +define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) { +; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] + +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* %ptr) +; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* %ptr) +; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK-NOT: fence +; CHECK: br label %[[DONE:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK-NOT: fence +; CHECK: br label %[[DONE]] + +; CHECK: [[DONE]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i16 [[OLDVAL]] + + %pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic + %old = extractvalue { i16, i1 } %pairold, 0 + ret i16 %old +} + +define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) { +; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] + +; CHECK: [[LOOP]]: +; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* %ptr) +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr) +; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK-NOT: fence_cst +; CHECK: br label %[[DONE:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK-NOT: fence_cst +; CHECK: br label %[[DONE]] + +; CHECK: [[DONE]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i32 [[OLDVAL]] + + %pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire + %old = extractvalue { i32, i1 } %pairold, 0 + ret i32 %old +} + +define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) { +; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic +; CHECK-NOT: fence +; CHECK: br label %[[LOOP:.*]] + +; CHECK: [[LOOP]]: +; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* +; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]]) +; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 +; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 +; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 +; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64 +; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32 +; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]] +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32 +; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32 +; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 +; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) +; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK-NOT: fence_cst +; CHECK: br label %[[DONE:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK-NOT: fence_cst +; CHECK: br label %[[DONE]] + +; CHECK: [[DONE]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i64 [[OLDVAL]] + + %pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic + %old = extractvalue { i64, i1 } %pairold, 0 + ret i64 %old +}
\ No newline at end of file diff --git a/test/Transforms/AtomicExpandLoadLinked/ARM/cmpxchg-weak.ll b/test/Transforms/AtomicExpandLoadLinked/ARM/cmpxchg-weak.ll new file mode 100644 index 000000000000..07a4a7f26e62 --- /dev/null +++ b/test/Transforms/AtomicExpandLoadLinked/ARM/cmpxchg-weak.ll @@ -0,0 +1,97 @@ +; RUN: opt -atomic-ll-sc -S -mtriple=thumbv7s-apple-ios7.0 %s | FileCheck %s + +define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) { +; CHECK-LABEL: @test_cmpxchg_seq_cst +; CHECK: fence release +; CHECK: br label %[[START:.*]] + +; CHECK: [[START]]: +; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) +; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 +; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK: fence seq_cst +; CHECK: br label %[[END:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK: fence seq_cst +; CHECK: br label %[[END]] + +; CHECK: [[END]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i32 [[LOADED]] + + %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst seq_cst + %oldval = extractvalue { i32, i1 } %pair, 0 + ret i32 %oldval +} + +define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) { +; CHECK-LABEL: @test_cmpxchg_weak_fail +; CHECK: fence release +; CHECK: br label %[[START:.*]] + +; CHECK: [[START]]: +; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) +; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 +; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK: fence seq_cst +; CHECK: br label %[[END:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK-NOT: fence +; CHECK: br label %[[END]] + +; CHECK: [[END]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i1 [[SUCCESS]] + + %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic + %oldval = extractvalue { i32, i1 } %pair, 1 + ret i1 %oldval +} + +define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) { +; CHECK-LABEL: @test_cmpxchg_monotonic +; CHECK-NOT: fence +; CHECK: br label %[[START:.*]] + +; CHECK: [[START]]: +; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) +; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired +; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[TRY_STORE]]: +; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) +; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 +; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] + +; CHECK: [[SUCCESS_BB]]: +; CHECK-NOT: fence +; CHECK: br label %[[END:.*]] + +; CHECK: [[FAILURE_BB]]: +; CHECK-NOT: fence +; CHECK: br label %[[END]] + +; CHECK: [[END]]: +; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] +; CHECK: ret i32 [[LOADED]] + + %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new monotonic monotonic + %oldval = extractvalue { i32, i1 } %pair, 0 + ret i32 %oldval +} diff --git a/test/Transforms/AtomicExpandLoadLinked/ARM/lit.local.cfg b/test/Transforms/AtomicExpandLoadLinked/ARM/lit.local.cfg new file mode 100644 index 000000000000..98c6700c209d --- /dev/null +++ b/test/Transforms/AtomicExpandLoadLinked/ARM/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'ARM' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/BBVectorize/lit.local.cfg b/test/Transforms/BBVectorize/lit.local.cfg index ba763cf03ffc..e71f3cc4c41e 100644 --- a/test/Transforms/BBVectorize/lit.local.cfg +++ b/test/Transforms/BBVectorize/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/BBVectorize/simple-int.ll b/test/Transforms/BBVectorize/simple-int.ll index e33ac612edc2..e0c1efa5b974 100644 --- a/test/Transforms/BBVectorize/simple-int.ll +++ b/test/Transforms/BBVectorize/simple-int.ll @@ -5,6 +5,18 @@ declare double @llvm.fma.f64(double, double, double) declare double @llvm.fmuladd.f64(double, double, double) declare double @llvm.cos.f64(double) declare double @llvm.powi.f64(double, i32) +declare double @llvm.round.f64(double) +declare double @llvm.copysign.f64(double, double) +declare double @llvm.ceil.f64(double) +declare double @llvm.nearbyint.f64(double) +declare double @llvm.rint.f64(double) +declare double @llvm.trunc.f64(double) +declare double @llvm.floor.f64(double) +declare double @llvm.fabs.f64(double) +declare i64 @llvm.bswap.i64(i64) +declare i64 @llvm.ctpop.i64(i64) +declare i64 @llvm.ctlz.i64(i64, i1) +declare i64 @llvm.cttz.i64(i64, i1) ; Basic depth-3 chain with fma define double @test1(double %A1, double %A2, double %B1, double %B2, double %C1, double %C2) { @@ -124,10 +136,371 @@ define double @test4(double %A1, double %A2, double %B1, double %B2, i32 %P) { ; CHECK: ret double %R } +; Basic depth-3 chain with round +define double @testround(double %A1, double %A2, double %B1, double %B2) { + %X1 = fsub double %A1, %B1 + %X2 = fsub double %A2, %B2 + %Y1 = call double @llvm.round.f64(double %X1) + %Y2 = call double @llvm.round.f64(double %X2) + %Z1 = fadd double %Y1, %B1 + %Z2 = fadd double %Y2, %B2 + %R = fmul double %Z1, %Z2 + ret double %R +; CHECK: @testround +; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1 +; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x double> @llvm.round.v2f64(<2 x double> %X1) +; CHECK: %Z1 = fadd <2 x double> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1 +; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2 +; CHECK: ret double %R + +} + +; Basic depth-3 chain with copysign +define double @testcopysign(double %A1, double %A2, double %B1, double %B2) { + %X1 = fsub double %A1, %B1 + %X2 = fsub double %A2, %B2 + %Y1 = call double @llvm.copysign.f64(double %X1, double %A1) + %Y2 = call double @llvm.copysign.f64(double %X2, double %A1) + %Z1 = fadd double %Y1, %B1 + %Z2 = fadd double %Y2, %B2 + %R = fmul double %Z1, %Z2 + ret double %R +; CHECK: @testcopysign +; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1 +; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1.v.i1.2 = insertelement <2 x double> %X1.v.i0.1, double %A1, i32 1 +; CHECK: %Y1 = call <2 x double> @llvm.copysign.v2f64(<2 x double> %X1, <2 x double> %Y1.v.i1.2) +; CHECK: %Z1 = fadd <2 x double> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1 +; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2 +; CHECK: ret double %R + +} + +; Basic depth-3 chain with ceil +define double @testceil(double %A1, double %A2, double %B1, double %B2) { + %X1 = fsub double %A1, %B1 + %X2 = fsub double %A2, %B2 + %Y1 = call double @llvm.ceil.f64(double %X1) + %Y2 = call double @llvm.ceil.f64(double %X2) + %Z1 = fadd double %Y1, %B1 + %Z2 = fadd double %Y2, %B2 + %R = fmul double %Z1, %Z2 + ret double %R +; CHECK: @testceil +; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1 +; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %X1) +; CHECK: %Z1 = fadd <2 x double> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1 +; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2 +; CHECK: ret double %R + +} + +; Basic depth-3 chain with nearbyint +define double @testnearbyint(double %A1, double %A2, double %B1, double %B2) { + %X1 = fsub double %A1, %B1 + %X2 = fsub double %A2, %B2 + %Y1 = call double @llvm.nearbyint.f64(double %X1) + %Y2 = call double @llvm.nearbyint.f64(double %X2) + %Z1 = fadd double %Y1, %B1 + %Z2 = fadd double %Y2, %B2 + %R = fmul double %Z1, %Z2 + ret double %R +; CHECK: @testnearbyint +; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1 +; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %X1) +; CHECK: %Z1 = fadd <2 x double> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1 +; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2 +; CHECK: ret double %R + +} + +; Basic depth-3 chain with rint +define double @testrint(double %A1, double %A2, double %B1, double %B2) { + %X1 = fsub double %A1, %B1 + %X2 = fsub double %A2, %B2 + %Y1 = call double @llvm.rint.f64(double %X1) + %Y2 = call double @llvm.rint.f64(double %X2) + %Z1 = fadd double %Y1, %B1 + %Z2 = fadd double %Y2, %B2 + %R = fmul double %Z1, %Z2 + ret double %R +; CHECK: @testrint +; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1 +; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x double> @llvm.rint.v2f64(<2 x double> %X1) +; CHECK: %Z1 = fadd <2 x double> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1 +; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2 +; CHECK: ret double %R + +} + +; Basic depth-3 chain with trunc +define double @testtrunc(double %A1, double %A2, double %B1, double %B2) { + %X1 = fsub double %A1, %B1 + %X2 = fsub double %A2, %B2 + %Y1 = call double @llvm.trunc.f64(double %X1) + %Y2 = call double @llvm.trunc.f64(double %X2) + %Z1 = fadd double %Y1, %B1 + %Z2 = fadd double %Y2, %B2 + %R = fmul double %Z1, %Z2 + ret double %R +; CHECK: @testtrunc +; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1 +; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x double> @llvm.trunc.v2f64(<2 x double> %X1) +; CHECK: %Z1 = fadd <2 x double> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1 +; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2 +; CHECK: ret double %R + +} + +; Basic depth-3 chain with floor +define double @testfloor(double %A1, double %A2, double %B1, double %B2) { + %X1 = fsub double %A1, %B1 + %X2 = fsub double %A2, %B2 + %Y1 = call double @llvm.floor.f64(double %X1) + %Y2 = call double @llvm.floor.f64(double %X2) + %Z1 = fadd double %Y1, %B1 + %Z2 = fadd double %Y2, %B2 + %R = fmul double %Z1, %Z2 + ret double %R +; CHECK: @testfloor +; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1 +; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x double> @llvm.floor.v2f64(<2 x double> %X1) +; CHECK: %Z1 = fadd <2 x double> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1 +; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2 +; CHECK: ret double %R + +} + +; Basic depth-3 chain with fabs +define double @testfabs(double %A1, double %A2, double %B1, double %B2) { + %X1 = fsub double %A1, %B1 + %X2 = fsub double %A2, %B2 + %Y1 = call double @llvm.fabs.f64(double %X1) + %Y2 = call double @llvm.fabs.f64(double %X2) + %Z1 = fadd double %Y1, %B1 + %Z2 = fadd double %Y2, %B2 + %R = fmul double %Z1, %Z2 + ret double %R +; CHECK: @testfabs +; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1 +; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x double> @llvm.fabs.v2f64(<2 x double> %X1) +; CHECK: %Z1 = fadd <2 x double> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1 +; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2 +; CHECK: ret double %R + +} + +; Basic depth-3 chain with bswap +define i64 @testbswap(i64 %A1, i64 %A2, i64 %B1, i64 %B2) { + %X1 = sub i64 %A1, %B1 + %X2 = sub i64 %A2, %B2 + %Y1 = call i64 @llvm.bswap.i64(i64 %X1) + %Y2 = call i64 @llvm.bswap.i64(i64 %X2) + %Z1 = add i64 %Y1, %B1 + %Z2 = add i64 %Y2, %B2 + %R = mul i64 %Z1, %Z2 + ret i64 %R + +; CHECK: @testbswap +; CHECK: %X1.v.i1.1 = insertelement <2 x i64> undef, i64 %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x i64> %X1.v.i1.1, i64 %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x i64> undef, i64 %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x i64> %X1.v.i0.1, i64 %A2, i32 1 +; CHECK: %X1 = sub <2 x i64> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %X1) +; CHECK: %Z1 = add <2 x i64> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x i64> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x i64> %Z1, i32 1 +; CHECK: %R = mul i64 %Z1.v.r1, %Z1.v.r2 +; CHECK: ret i64 %R + +} + +; Basic depth-3 chain with ctpop +define i64 @testctpop(i64 %A1, i64 %A2, i64 %B1, i64 %B2) { + %X1 = sub i64 %A1, %B1 + %X2 = sub i64 %A2, %B2 + %Y1 = call i64 @llvm.ctpop.i64(i64 %X1) + %Y2 = call i64 @llvm.ctpop.i64(i64 %X2) + %Z1 = add i64 %Y1, %B1 + %Z2 = add i64 %Y2, %B2 + %R = mul i64 %Z1, %Z2 + ret i64 %R + +; CHECK: @testctpop +; CHECK: %X1.v.i1.1 = insertelement <2 x i64> undef, i64 %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x i64> %X1.v.i1.1, i64 %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x i64> undef, i64 %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x i64> %X1.v.i0.1, i64 %A2, i32 1 +; CHECK: %X1 = sub <2 x i64> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %X1) +; CHECK: %Z1 = add <2 x i64> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x i64> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x i64> %Z1, i32 1 +; CHECK: %R = mul i64 %Z1.v.r1, %Z1.v.r2 +; CHECK: ret i64 %R + +} + +; Basic depth-3 chain with ctlz +define i64 @testctlz(i64 %A1, i64 %A2, i64 %B1, i64 %B2) { + %X1 = sub i64 %A1, %B1 + %X2 = sub i64 %A2, %B2 + %Y1 = call i64 @llvm.ctlz.i64(i64 %X1, i1 true) + %Y2 = call i64 @llvm.ctlz.i64(i64 %X2, i1 true) + %Z1 = add i64 %Y1, %B1 + %Z2 = add i64 %Y2, %B2 + %R = mul i64 %Z1, %Z2 + ret i64 %R + +; CHECK: @testctlz +; CHECK: %X1.v.i1.1 = insertelement <2 x i64> undef, i64 %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x i64> %X1.v.i1.1, i64 %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x i64> undef, i64 %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x i64> %X1.v.i0.1, i64 %A2, i32 1 +; CHECK: %X1 = sub <2 x i64> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %X1, i1 true) +; CHECK: %Z1 = add <2 x i64> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x i64> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x i64> %Z1, i32 1 +; CHECK: %R = mul i64 %Z1.v.r1, %Z1.v.r2 +; CHECK: ret i64 %R + +} + +; Basic depth-3 chain with ctlz +define i64 @testctlzneg(i64 %A1, i64 %A2, i64 %B1, i64 %B2) { + %X1 = sub i64 %A1, %B1 + %X2 = sub i64 %A2, %B2 + %Y1 = call i64 @llvm.ctlz.i64(i64 %X1, i1 true) + %Y2 = call i64 @llvm.ctlz.i64(i64 %X2, i1 false) + %Z1 = add i64 %Y1, %B1 + %Z2 = add i64 %Y2, %B2 + %R = mul i64 %Z1, %Z2 + ret i64 %R + +; CHECK: @testctlzneg +; CHECK: %X1 = sub i64 %A1, %B1 +; CHECK: %X2 = sub i64 %A2, %B2 +; CHECK: %Y1 = call i64 @llvm.ctlz.i64(i64 %X1, i1 true) +; CHECK: %Y2 = call i64 @llvm.ctlz.i64(i64 %X2, i1 false) +; CHECK: %Z1 = add i64 %Y1, %B1 +; CHECK: %Z2 = add i64 %Y2, %B2 +; CHECK: %R = mul i64 %Z1, %Z2 +; CHECK: ret i64 %R +} + +; Basic depth-3 chain with cttz +define i64 @testcttz(i64 %A1, i64 %A2, i64 %B1, i64 %B2) { + %X1 = sub i64 %A1, %B1 + %X2 = sub i64 %A2, %B2 + %Y1 = call i64 @llvm.cttz.i64(i64 %X1, i1 true) + %Y2 = call i64 @llvm.cttz.i64(i64 %X2, i1 true) + %Z1 = add i64 %Y1, %B1 + %Z2 = add i64 %Y2, %B2 + %R = mul i64 %Z1, %Z2 + ret i64 %R + +; CHECK: @testcttz +; CHECK: %X1.v.i1.1 = insertelement <2 x i64> undef, i64 %B1, i32 0 +; CHECK: %X1.v.i1.2 = insertelement <2 x i64> %X1.v.i1.1, i64 %B2, i32 1 +; CHECK: %X1.v.i0.1 = insertelement <2 x i64> undef, i64 %A1, i32 0 +; CHECK: %X1.v.i0.2 = insertelement <2 x i64> %X1.v.i0.1, i64 %A2, i32 1 +; CHECK: %X1 = sub <2 x i64> %X1.v.i0.2, %X1.v.i1.2 +; CHECK: %Y1 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %X1, i1 true) +; CHECK: %Z1 = add <2 x i64> %Y1, %X1.v.i1.2 +; CHECK: %Z1.v.r1 = extractelement <2 x i64> %Z1, i32 0 +; CHECK: %Z1.v.r2 = extractelement <2 x i64> %Z1, i32 1 +; CHECK: %R = mul i64 %Z1.v.r1, %Z1.v.r2 +; CHECK: ret i64 %R + +} + +; Basic depth-3 chain with cttz +define i64 @testcttzneg(i64 %A1, i64 %A2, i64 %B1, i64 %B2) { + %X1 = sub i64 %A1, %B1 + %X2 = sub i64 %A2, %B2 + %Y1 = call i64 @llvm.cttz.i64(i64 %X1, i1 true) + %Y2 = call i64 @llvm.cttz.i64(i64 %X2, i1 false) + %Z1 = add i64 %Y1, %B1 + %Z2 = add i64 %Y2, %B2 + %R = mul i64 %Z1, %Z2 + ret i64 %R + +; CHECK: @testcttzneg +; CHECK: %X1 = sub i64 %A1, %B1 +; CHECK: %X2 = sub i64 %A2, %B2 +; CHECK: %Y1 = call i64 @llvm.cttz.i64(i64 %X1, i1 true) +; CHECK: %Y2 = call i64 @llvm.cttz.i64(i64 %X2, i1 false) +; CHECK: %Z1 = add i64 %Y1, %B1 +; CHECK: %Z2 = add i64 %Y2, %B2 +; CHECK: %R = mul i64 %Z1, %Z2 +; CHECK: ret i64 %R +} + + + ; CHECK: declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) #0 ; CHECK: declare <2 x double> @llvm.fmuladd.v2f64(<2 x double>, <2 x double>, <2 x double>) #0 -; CHECK: declare <2 x double> @llvm.cos.v2f64(<2 x double>) #1 -; CHECK: declare <2 x double> @llvm.powi.v2f64(<2 x double>, i32) #1 - +; CHECK: declare <2 x double> @llvm.cos.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.powi.v2f64(<2 x double>, i32) #0 +; CHECK: declare <2 x double> @llvm.round.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) #0 +; CHECK: declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.rint.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.trunc.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.floor.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.fabs.v2f64(<2 x double>) #0 +; CHECK: declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) #0 +; CHECK: declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) #0 +; CHECK: declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) #0 +; CHECK: declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1) #0 ; CHECK: attributes #0 = { nounwind readnone } -; CHECK: attributes #1 = { nounwind readonly } diff --git a/test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll b/test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll index 9d82819f9db4..598ea0e354e1 100644 --- a/test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll +++ b/test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -std-compile-opts -o - | llc -o - | grep bork_directive | wc -l | grep 2 +; RUN: opt < %s -std-compile-opts -o - | llc -no-integrated-as -o - | grep bork_directive | wc -l | grep 2 ;; We don't want branch folding to fold asm directives. diff --git a/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll b/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll new file mode 100644 index 000000000000..430b99299d82 --- /dev/null +++ b/test/Transforms/CodeGenPrepare/X86/extend-sink-hoist.ll @@ -0,0 +1,64 @@ +; RUN: opt -codegenprepare -disable-cgp-branch-opts -S < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; The first cast should be sunk into block2, in order that the +; instruction selector can form an efficient +; i64 * i64 -> i128 multiplication. +define i128 @sink(i64* %mem1, i64* %mem2) { +; CHECK-LABEL: block1: +; CHECK-NEXT: load +block1: + %l1 = load i64* %mem1 + %s1 = sext i64 %l1 to i128 + br label %block2 + +; CHECK-LABEL: block2: +; CHECK-NEXT: sext +; CHECK-NEXT: load +; CHECK-NEXT: sext +block2: + %l2 = load i64* %mem2 + %s2 = sext i64 %l2 to i128 + %res = mul i128 %s1, %s2 + ret i128 %res +} + +; The first cast should be hoisted into block1, in order that the +; instruction selector can form an extend-load. +define i64 @hoist(i32* %mem1, i32* %mem2) { +; CHECK-LABEL: block1: +; CHECK-NEXT: load +; CHECK-NEXT: sext +block1: + %l1 = load i32* %mem1 + br label %block2 + +; CHECK-LABEL: block2: +; CHECK-NEXT: load +; CHECK-NEXT: sext +block2: + %s1 = sext i32 %l1 to i64 + %l2 = load i32* %mem2 + %s2 = sext i32 %l2 to i64 + %res = mul i64 %s1, %s2 + ret i64 %res +} + +; Make sure the cast sink logic and OptimizeExtUses don't end up in an infinite +; loop. +define i128 @use_ext_source() { +block1: + %v1 = or i64 undef, undef + %v2 = zext i64 %v1 to i128 + br i1 undef, label %block2, label %block3 + +block2: + %v3 = add i64 %v1, 1 + %v4 = zext i64 %v3 to i128 + br label %block3 + +block3: + %res = phi i128 [ %v2, %block1 ], [ %v4, %block2 ] + ret i128 %res +} diff --git a/test/Transforms/CodeGenPrepare/X86/lit.local.cfg b/test/Transforms/CodeGenPrepare/X86/lit.local.cfg new file mode 100644 index 000000000000..e71f3cc4c41e --- /dev/null +++ b/test/Transforms/CodeGenPrepare/X86/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'X86' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll b/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll new file mode 100644 index 000000000000..a985c36707a9 --- /dev/null +++ b/test/Transforms/CodeGenPrepare/X86/sink-addrspacecast.ll @@ -0,0 +1,37 @@ +; RUN: opt -S -codegenprepare < %s | FileCheck %s + +target datalayout = +"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +; CHECK-LABEL: @load_cast_gep +; CHECK: add i64 %sunkaddr, 40 +define void @load_cast_gep(i1 %cond, i64* %base) { +entry: + %addr = getelementptr inbounds i64* %base, i64 5 + %casted = addrspacecast i64* %addr to i32 addrspace(1)* + br i1 %cond, label %if.then, label %fallthrough + +if.then: + %v = load i32 addrspace(1)* %casted, align 4 + br label %fallthrough + +fallthrough: + ret void +} + +; CHECK-LABEL: @store_gep_cast +; CHECK: add i64 %sunkaddr, 20 +define void @store_gep_cast(i1 %cond, i64* %base) { +entry: + %casted = addrspacecast i64* %base to i32 addrspace(1)* + %addr = getelementptr inbounds i32 addrspace(1)* %casted, i64 5 + br i1 %cond, label %if.then, label %fallthrough + +if.then: + store i32 0, i32 addrspace(1)* %addr, align 4 + br label %fallthrough + +fallthrough: + ret void +} diff --git a/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll b/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll new file mode 100644 index 000000000000..e945b03c33ae --- /dev/null +++ b/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll @@ -0,0 +1,105 @@ +; RUN: opt -S -codegenprepare -mcpu=core-avx2 %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AVX2 +; RUN: opt -S -codegenprepare -mcpu=corei7 %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SSE2 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-darwin10.9.0" + +define <16 x i8> @test_8bit(<16 x i8> %lhs, <16 x i8> %tmp, i1 %tst) { +; CHECK-LABEL: @test_8bit +; CHECK: if_true: +; CHECK-NOT: shufflevector + +; CHECK: if_false: +; CHECK-NOT: shufflevector +; CHECK: shl <16 x i8> %lhs, %mask + %mask = shufflevector <16 x i8> %tmp, <16 x i8> undef, <16 x i32> zeroinitializer + br i1 %tst, label %if_true, label %if_false + +if_true: + ret <16 x i8> %mask + +if_false: + %res = shl <16 x i8> %lhs, %mask + ret <16 x i8> %res +} + +define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) { +; CHECK-LABEL: @test_16bit +; CHECK: if_true: +; CHECK-NOT: shufflevector + +; CHECK: if_false: +; CHECK: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector +; CHECK: shl <8 x i16> %lhs, [[SPLAT]] + %mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer + br i1 %tst, label %if_true, label %if_false + +if_true: + ret <8 x i16> %mask + +if_false: + %res = shl <8 x i16> %lhs, %mask + ret <8 x i16> %res +} + +define <4 x i32> @test_notsplat(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) { +; CHECK-LABEL: @test_notsplat +; CHECK: if_true: +; CHECK-NOT: shufflevector + +; CHECK: if_false: +; CHECK-NOT: shufflevector +; CHECK: shl <4 x i32> %lhs, %mask + %mask = shufflevector <4 x i32> %tmp, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0> + br i1 %tst, label %if_true, label %if_false + +if_true: + ret <4 x i32> %mask + +if_false: + %res = shl <4 x i32> %lhs, %mask + ret <4 x i32> %res +} + +define <4 x i32> @test_32bit(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) { +; CHECK-AVX2-LABEL: @test_32bit +; CHECK-AVX2: if_false: +; CHECK-AVX2-NOT: shufflevector +; CHECK-AVX2: ashr <4 x i32> %lhs, %mask + +; CHECK-SSE2-LABEL: @test_32bit +; CHECK-SSE2: if_false: +; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector +; CHECK-SSE2: ashr <4 x i32> %lhs, [[SPLAT]] + %mask = shufflevector <4 x i32> %tmp, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0> + br i1 %tst, label %if_true, label %if_false + +if_true: + ret <4 x i32> %mask + +if_false: + %res = ashr <4 x i32> %lhs, %mask + ret <4 x i32> %res +} + +define <2 x i64> @test_64bit(<2 x i64> %lhs, <2 x i64> %tmp, i1 %tst) { +; CHECK-AVX2-LABEL: @test_64bit +; CHECK-AVX2: if_false: +; CHECK-AVX2-NOT: shufflevector +; CHECK-AVX2: lshr <2 x i64> %lhs, %mask + +; CHECK-SSE2-LABEL: @test_64bit +; CHECK-SSE2: if_false: +; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector +; CHECK-SSE2: lshr <2 x i64> %lhs, [[SPLAT]] + + %mask = shufflevector <2 x i64> %tmp, <2 x i64> undef, <2 x i32> zeroinitializer + br i1 %tst, label %if_true, label %if_false + +if_true: + ret <2 x i64> %mask + +if_false: + %res = lshr <2 x i64> %lhs, %mask + ret <2 x i64> %res +} diff --git a/test/Transforms/ConstProp/loads.ll b/test/Transforms/ConstProp/loads.ll index d05db47dcaaa..5a23dad87f3a 100644 --- a/test/Transforms/ConstProp/loads.ll +++ b/test/Transforms/ConstProp/loads.ll @@ -36,6 +36,19 @@ define i16 @test2() { ; BE: ret i16 -8531 } +define i16 @test2_addrspacecast() { + %r = load i16 addrspace(1)* addrspacecast(i32* getelementptr ({{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16 addrspace(1)*) + ret i16 %r + +; 0xBEEF +; LE-LABEL: @test2_addrspacecast( +; LE: ret i16 -16657 + +; 0xDEAD +; BE-LABEL: @test2_addrspacecast( +; BE: ret i16 -8531 +} + ; Load of second 16 bits of 32-bit value. define i16 @test3() { %r = load i16* getelementptr(i16* bitcast(i32* getelementptr ({{i32,i8},i32}* @g1, i32 0, i32 0, i32 0) to i16*), i32 1) @@ -219,3 +232,37 @@ entry: ; BE-LABEL: @test15( ; BE: ret i64 2 } + +@gv7 = constant [4 x i8*] [i8* null, i8* inttoptr (i64 -14 to i8*), i8* null, i8* null] +define i64 @test16.1() { + %v = load i64* bitcast ([4 x i8*]* @gv7 to i64*), align 8 + ret i64 %v + +; LE-LABEL: @test16.1( +; LE: ret i64 0 + +; BE-LABEL: @test16.1( +; BE: ret i64 0 +} + +define i64 @test16.2() { + %v = load i64* bitcast (i8** getelementptr inbounds ([4 x i8*]* @gv7, i64 0, i64 1) to i64*), align 8 + ret i64 %v + +; LE-LABEL: @test16.2( +; LE: ret i64 -14 + +; BE-LABEL: @test16.2( +; BE: ret i64 -14 +} + +define i64 @test16.3() { + %v = load i64* bitcast (i8** getelementptr inbounds ([4 x i8*]* @gv7, i64 0, i64 2) to i64*), align 8 + ret i64 %v + +; LE-LABEL: @test16.3( +; LE: ret i64 0 + +; BE-LABEL: @test16.3( +; BE: ret i64 0 +} diff --git a/test/Transforms/ConstantHoisting/AArch64/const-addr.ll b/test/Transforms/ConstantHoisting/AArch64/const-addr.ll new file mode 100644 index 000000000000..89d596055c44 --- /dev/null +++ b/test/Transforms/ConstantHoisting/AArch64/const-addr.ll @@ -0,0 +1,23 @@ +; RUN: opt -mtriple=arm64-darwin-unknown -S -consthoist < %s | FileCheck %s + +%T = type { i32, i32, i32, i32 } + +define i32 @test1() nounwind { +; CHECK-LABEL: test1 +; CHECK: %const = bitcast i64 68141056 to i64 +; CHECK: %1 = inttoptr i64 %const to %T* +; CHECK: %o1 = getelementptr %T* %1, i32 0, i32 1 +; CHECK: %o2 = getelementptr %T* %1, i32 0, i32 2 +; CHECK: %o3 = getelementptr %T* %1, i32 0, i32 3 + %at = inttoptr i64 68141056 to %T* + %o1 = getelementptr %T* %at, i32 0, i32 1 + %t1 = load i32* %o1 + %o2 = getelementptr %T* %at, i32 0, i32 2 + %t2 = load i32* %o2 + %a1 = add i32 %t1, %t2 + %o3 = getelementptr %T* %at, i32 0, i32 3 + %t3 = load i32* %o3 + %a2 = add i32 %a1, %t3 + ret i32 %a2 +} + diff --git a/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll b/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll new file mode 100644 index 000000000000..575be791d9b1 --- /dev/null +++ b/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll @@ -0,0 +1,27 @@ +; RUN: opt -mtriple=arm64-darwin-unknown -S -consthoist < %s | FileCheck %s + +define i128 @test1(i128 %a) nounwind { +; CHECK-LABEL: test1 +; CHECK: %const = bitcast i128 12297829382473034410122878 to i128 + %1 = add i128 %a, 12297829382473034410122878 + %2 = add i128 %1, 12297829382473034410122878 + ret i128 %2 +} + +; Check that we don't hoist large, but cheap constants +define i512 @test2(i512 %a) nounwind { +; CHECK-LABEL: test2 +; CHECK-NOT: %const = bitcast i512 7 to i512 + %1 = and i512 %a, 7 + %2 = or i512 %1, 7 + ret i512 %2 +} + +; Check that we don't hoist the shift value of a shift instruction. +define i512 @test3(i512 %a) nounwind { +; CHECK-LABEL: test3 +; CHECK-NOT: %const = bitcast i512 504 to i512 + %1 = shl i512 %a, 504 + %2 = ashr i512 %1, 504 + ret i512 %2 +} diff --git a/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg b/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg new file mode 100644 index 000000000000..7184443994b6 --- /dev/null +++ b/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'AArch64' in config.root.targets: + config.unsupported = True diff --git a/test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll b/test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll new file mode 100644 index 000000000000..b4337eeda653 --- /dev/null +++ b/test/Transforms/ConstantHoisting/PowerPC/const-base-addr.ll @@ -0,0 +1,23 @@ +; RUN: opt -S -consthoist < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%T = type { i32, i32, i32, i32 } + +; Test if even cheap base addresses are hoisted. +define i32 @test1() nounwind { +; CHECK-LABEL: @test1 +; CHECK: %const = bitcast i32 12345678 to i32 +; CHECK: %1 = inttoptr i32 %const to %T* +; CHECK: %addr1 = getelementptr %T* %1, i32 0, i32 1 + %addr1 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 1 + %tmp1 = load i32* %addr1 + %addr2 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 2 + %tmp2 = load i32* %addr2 + %addr3 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 3 + %tmp3 = load i32* %addr3 + %tmp4 = add i32 %tmp1, %tmp2 + %tmp5 = add i32 %tmp3, %tmp4 + ret i32 %tmp5 +} + diff --git a/test/Transforms/ConstantHoisting/PowerPC/lit.local.cfg b/test/Transforms/ConstantHoisting/PowerPC/lit.local.cfg new file mode 100644 index 000000000000..5d33887ff0a4 --- /dev/null +++ b/test/Transforms/ConstantHoisting/PowerPC/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'PowerPC' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/ConstantHoisting/PowerPC/masks.ll b/test/Transforms/ConstantHoisting/PowerPC/masks.ll new file mode 100644 index 000000000000..d55318201136 --- /dev/null +++ b/test/Transforms/ConstantHoisting/PowerPC/masks.ll @@ -0,0 +1,66 @@ +; RUN: opt -S -consthoist < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Here the masks are all contiguous, and should not be hoisted. +define i32 @test1() nounwind { +entry: +; CHECK-LABEL: @test1 +; CHECK-NOT: bitcast i32 65535 to i32 +; CHECK: and i32 undef, 65535 + %conv121 = and i32 undef, 65535 + br i1 undef, label %if.then152, label %if.end167 + +if.then152: +; CHECK: and i32 undef, 65535 + %conv153 = and i32 undef, 65535 + br i1 undef, label %if.end167, label %end2 + +if.end167: +; CHECK: and i32 {{.*}}, 32768 + %shl161 = shl nuw nsw i32 %conv121, 15 + %0 = load i8* undef, align 1 + %conv169 = zext i8 %0 to i32 + %shl170 = shl nuw nsw i32 %conv169, 7 + %shl161.masked = and i32 %shl161, 32768 + %conv174 = or i32 %shl170, %shl161.masked + %cmp178 = icmp ugt i32 %conv174, 32767 + br i1 %cmp178, label %end1, label %end2 + +end1: + unreachable + +end2: + unreachable +} + +; Here the masks are not contiguous, and should be hoisted. +define i32 @test2() nounwind { +entry: +; CHECK-LABEL: @test2 +; CHECK: bitcast i32 65531 to i32 + %conv121 = and i32 undef, 65531 + br i1 undef, label %if.then152, label %if.end167 + +if.then152: + %conv153 = and i32 undef, 65531 + br i1 undef, label %if.end167, label %end2 + +if.end167: +; CHECK: add i32 {{.*}}, -32758 + %shl161 = shl nuw nsw i32 %conv121, 15 + %0 = load i8* undef, align 1 + %conv169 = zext i8 %0 to i32 + %shl170 = shl nuw nsw i32 %conv169, 7 + %shl161.masked = and i32 %shl161, 32773 + %conv174 = or i32 %shl170, %shl161.masked + %cmp178 = icmp ugt i32 %conv174, 32767 + br i1 %cmp178, label %end1, label %end2 + +end1: + unreachable + +end2: + unreachable +} + diff --git a/test/Transforms/ConstantHoisting/X86/cast-inst.ll b/test/Transforms/ConstantHoisting/X86/cast-inst.ll new file mode 100644 index 000000000000..f490f4a37236 --- /dev/null +++ b/test/Transforms/ConstantHoisting/X86/cast-inst.ll @@ -0,0 +1,29 @@ +; RUN: opt -S -consthoist < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +; Check if the materialization of the constant and the cast instruction are +; inserted in the correct order. +define i32 @cast_inst_test() { +; CHECK-LABEL: @cast_inst_test +; CHECK: %const = bitcast i64 4646526064 to i64 +; CHECK: %1 = inttoptr i64 %const to i32* +; CHECK: %v0 = load i32* %1, align 16 +; CHECK: %const_mat = add i64 %const, 16 +; CHECK-NEXT: %2 = inttoptr i64 %const_mat to i32* +; CHECK-NEXT: %v1 = load i32* %2, align 16 +; CHECK: %const_mat1 = add i64 %const, 32 +; CHECK-NEXT: %3 = inttoptr i64 %const_mat1 to i32* +; CHECK-NEXT: %v2 = load i32* %3, align 16 + %a0 = inttoptr i64 4646526064 to i32* + %v0 = load i32* %a0, align 16 + %a1 = inttoptr i64 4646526080 to i32* + %v1 = load i32* %a1, align 16 + %a2 = inttoptr i64 4646526096 to i32* + %v2 = load i32* %a2, align 16 + %r0 = add i32 %v0, %v1 + %r1 = add i32 %r0, %v2 + ret i32 %r1 +} + diff --git a/test/Transforms/ConstantHoisting/X86/const-base-addr.ll b/test/Transforms/ConstantHoisting/X86/const-base-addr.ll new file mode 100644 index 000000000000..01e6cdfd2a5b --- /dev/null +++ b/test/Transforms/ConstantHoisting/X86/const-base-addr.ll @@ -0,0 +1,24 @@ +; RUN: opt -S -consthoist < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +%T = type { i32, i32, i32, i32 } + +; Test if even cheap base addresses are hoisted. +define i32 @test1() nounwind { +; CHECK-LABEL: @test1 +; CHECK: %const = bitcast i32 12345678 to i32 +; CHECK: %1 = inttoptr i32 %const to %T* +; CHECK: %addr1 = getelementptr %T* %1, i32 0, i32 1 + %addr1 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 1 + %tmp1 = load i32* %addr1 + %addr2 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 2 + %tmp2 = load i32* %addr2 + %addr3 = getelementptr %T* inttoptr (i32 12345678 to %T*), i32 0, i32 3 + %tmp3 = load i32* %addr3 + %tmp4 = add i32 %tmp1, %tmp2 + %tmp5 = add i32 %tmp3, %tmp4 + ret i32 %tmp5 +} + diff --git a/test/Transforms/ConstantHoisting/X86/delete-dead-cast-inst.ll b/test/Transforms/ConstantHoisting/X86/delete-dead-cast-inst.ll new file mode 100644 index 000000000000..d35238692078 --- /dev/null +++ b/test/Transforms/ConstantHoisting/X86/delete-dead-cast-inst.ll @@ -0,0 +1,22 @@ +; RUN: opt -S -consthoist < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +%T = type { i32, i32, i32, i32 } + +define i32 @test1() nounwind { +; CHECK-LABEL: @test1 +; CHECK: %const = bitcast i32 12345678 to i32 +; CHECK-NOT: %base = inttoptr i32 12345678 to %T* +; CHECK-NEXT: %1 = inttoptr i32 %const to %T* +; CHECK-NEXT: %addr1 = getelementptr %T* %1, i32 0, i32 1 +; CHECK-NEXT: %addr2 = getelementptr %T* %1, i32 0, i32 2 +; CHECK-NEXT: %addr3 = getelementptr %T* %1, i32 0, i32 3 + %base = inttoptr i32 12345678 to %T* + %addr1 = getelementptr %T* %base, i32 0, i32 1 + %addr2 = getelementptr %T* %base, i32 0, i32 2 + %addr3 = getelementptr %T* %base, i32 0, i32 3 + ret i32 12345678 +} + diff --git a/test/Transforms/ConstantHoisting/X86/large-immediate.ll b/test/Transforms/ConstantHoisting/X86/large-immediate.ll new file mode 100644 index 000000000000..b8c04f38b12f --- /dev/null +++ b/test/Transforms/ConstantHoisting/X86/large-immediate.ll @@ -0,0 +1,36 @@ +; RUN: opt -mtriple=x86_64-darwin-unknown -S -consthoist < %s | FileCheck %s + +define i128 @test1(i128 %a) nounwind { +; CHECK-LABEL: test1 +; CHECK: %const = bitcast i128 12297829382473034410122878 to i128 + %1 = add i128 %a, 12297829382473034410122878 + %2 = add i128 %1, 12297829382473034410122878 + ret i128 %2 +} + +; Check that we don't hoist the shift value of a shift instruction. +define i512 @test2(i512 %a) nounwind { +; CHECK-LABEL: test2 +; CHECK-NOT: %const = bitcast i512 504 to i512 + %1 = shl i512 %a, 504 + %2 = ashr i512 %1, 504 + ret i512 %2 +} + +; Check that we don't hoist constants with a type larger than i128. +define i196 @test3(i196 %a) nounwind { +; CHECK-LABEL: test3 +; CHECK-NOT: %const = bitcast i196 2 to i196 + %1 = mul i196 %a, 2 + %2 = mul i196 %1, 2 + ret i196 %2 +} + +; Check that we don't hoist immediates with small values. +define i96 @test4(i96 %a) nounwind { +; CHECK-LABEL: test4 +; CHECK-NOT: %const = bitcast i96 2 to i96 + %1 = mul i96 %a, 2 + %2 = add i96 %1, 2 + ret i96 %2 +} diff --git a/test/Transforms/ConstantHoisting/X86/lit.local.cfg b/test/Transforms/ConstantHoisting/X86/lit.local.cfg new file mode 100644 index 000000000000..e71f3cc4c41e --- /dev/null +++ b/test/Transforms/ConstantHoisting/X86/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'X86' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/ConstantHoisting/X86/phi.ll b/test/Transforms/ConstantHoisting/X86/phi.ll new file mode 100644 index 000000000000..086df1404703 --- /dev/null +++ b/test/Transforms/ConstantHoisting/X86/phi.ll @@ -0,0 +1,116 @@ +; RUN: opt -S -consthoist < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +; PR18626 +define i8* @test1(i1 %cmp, i64* %tmp) { +entry: + call void @foo(i8* inttoptr (i64 68719476735 to i8*)) + br i1 %cmp, label %if.end, label %return + +if.end: ; preds = %bb1 + call void @foo(i8* inttoptr (i64 68719476736 to i8*)) + br label %return + +return: + %retval.0 = phi i8* [ null, %entry ], [ inttoptr (i64 68719476736 to i8*), %if.end ] + store i64 1172321806, i64* %tmp + ret i8* %retval.0 + +; CHECK-LABEL: @test1 +; CHECK: if.end: +; CHECK: %2 = inttoptr i64 %const to i8* +; CHECK-NEXT: br +; CHECK: return: +; CHECK-NEXT: %retval.0 = phi i8* [ null, %entry ], [ %2, %if.end ] +} + +define void @test2(i1 %cmp, i64** %tmp) { +entry: + call void @foo(i8* inttoptr (i64 68719476736 to i8*)) + br i1 %cmp, label %if.end, label %return + +if.end: ; preds = %bb1 + call void @foo(i8* inttoptr (i64 68719476736 to i8*)) + br label %return + +return: + store i64* inttoptr (i64 68719476735 to i64*), i64** %tmp + ret void + +; CHECK-LABEL: @test2 +; CHECK: return: +; CHECK-NEXT: %const_mat = add i64 %const, -1 +; CHECK-NEXT: inttoptr i64 %const_mat to i64* +} + +declare void @foo(i8*) + +; PR18768 +define i32 @test3(i1 %c) { +entry: + br i1 %c, label %if.then, label %if.end3 + +if.then: ; preds = %entry + br label %if.end3 + +if.end3: ; preds = %if.then, %entry + %d.0 = phi i32* [ inttoptr (i64 985162435264511 to i32*), %entry ], [ null, %if.then ] + %cmp4 = icmp eq i32* %d.0, inttoptr (i64 985162435264511 to i32*) + %cmp6 = icmp eq i32* %d.0, inttoptr (i64 985162418487296 to i32*) + %or = or i1 %cmp4, %cmp6 + br i1 %or, label %if.then8, label %if.end9 + +if.then8: ; preds = %if.end3 + ret i32 1 + +if.end9: ; preds = %if.then8, %if.end3 + ret i32 undef +} + +; <rdar://problem/16394449> +define i64 @switch_test1(i64 %a) { +; CHECK-LABEL: @switch_test1 +; CHECK: %0 = phi i64 [ %const, %case2 ], [ %const_mat, %Entry ], [ %const_mat, %Entry ] +Entry: + %sel = add i64 %a, 4519019440 + switch i64 %sel, label %fail [ + i64 462, label %continuation + i64 449, label %case2 + i64 443, label %continuation + ] + +case2: + br label %continuation + +continuation: + %0 = phi i64 [ 4519019440, %case2 ], [ 4519019460, %Entry ], [ 4519019460, %Entry ] + ret i64 0; + +fail: + ret i64 -1; +} + +define i64 @switch_test2(i64 %a) { +; CHECK-LABEL: @switch_test2 +; CHECK: %2 = phi i64* [ %1, %case2 ], [ %0, %Entry ], [ %0, %Entry ] +Entry: + %sel = add i64 %a, 4519019440 + switch i64 %sel, label %fail [ + i64 462, label %continuation + i64 449, label %case2 + i64 443, label %continuation + ] + +case2: + br label %continuation + +continuation: + %0 = phi i64* [ inttoptr(i64 4519019440 to i64*), %case2 ], [ inttoptr(i64 4519019460 to i64*), %Entry ], [ inttoptr(i64 4519019460 to i64*), %Entry ] + ret i64 0; + +fail: + ret i64 -1; +} + diff --git a/test/Transforms/ConstantHoisting/X86/stackmap.ll b/test/Transforms/ConstantHoisting/X86/stackmap.ll new file mode 100644 index 000000000000..9df44177820e --- /dev/null +++ b/test/Transforms/ConstantHoisting/X86/stackmap.ll @@ -0,0 +1,17 @@ +; RUN: opt -S -consthoist < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +; Test if the 3rd argument of a stackmap is hoisted. +define i128 @test1(i128 %a) { +; CHECK-LABEL: @test1 +; CHECK: %const = bitcast i128 134646182756734033220 to i128 +; CHECK: tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 24, i128 %const) +entry: + %0 = add i128 %a, 134646182756734033220 + tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 24, i128 134646182756734033220) + ret i128 %0 +} + +declare void @llvm.experimental.stackmap(i64, i32, ...) diff --git a/test/Transforms/ConstantMerge/linker-private.ll b/test/Transforms/ConstantMerge/linker-private.ll deleted file mode 100644 index eba7880e8af7..000000000000 --- a/test/Transforms/ConstantMerge/linker-private.ll +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: opt < %s -constmerge -S | FileCheck %s -; <rdar://problem/10564621> - -%0 = type opaque -%struct.NSConstantString = type { i32*, i32, i8*, i32 } - -; CHECK: @.str3 = linker_private unnamed_addr constant [1 x i8] zeroinitializer, align 1 - -@isLogVisible = global i8 0, align 1 -@__CFConstantStringClassReference = external global [0 x i32] -@.str3 = linker_private unnamed_addr constant [1 x i8] zeroinitializer, align 1 -@_unnamed_cfstring_4 = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([1 x i8]* @.str3, i32 0, i32 0), i32 0 }, section "__DATA,__cfstring" -@null.array = weak_odr constant [1 x i8] zeroinitializer, align 1 - -define linkonce_odr void @bar() nounwind ssp align 2 { -entry: - %stack = alloca i8*, align 4 - %call = call %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* (i8*, i8*, %0*)*)(i8* null, i8* null, %0* bitcast (%struct.NSConstantString* @_unnamed_cfstring_4 to %0*)) - store i8* getelementptr inbounds ([1 x i8]* @null.array, i32 0, i32 0), i8** %stack, align 4 - ret void -} - -declare i8* @objc_msgSend(i8*, i8*, ...) nonlazybind diff --git a/test/Transforms/DeadArgElim/deadexternal.ll b/test/Transforms/DeadArgElim/deadexternal.ll index acbcf75ee495..665d7dbf4937 100644 --- a/test/Transforms/DeadArgElim/deadexternal.ll +++ b/test/Transforms/DeadArgElim/deadexternal.ll @@ -32,7 +32,7 @@ entry: %i = alloca i32, align 4 store volatile i32 10, i32* %i, align 4 ; CHECK: %tmp = load volatile i32* %i, align 4 -; CHECK-next: call void @f(i32 undef) +; CHECK-NEXT: call void @f(i32 undef) %tmp = load volatile i32* %i, align 4 call void @f(i32 %tmp) ret void diff --git a/test/Transforms/DeadArgElim/keepalive.ll b/test/Transforms/DeadArgElim/keepalive.ll index 82e01f225843..16569db4d38f 100644 --- a/test/Transforms/DeadArgElim/keepalive.ll +++ b/test/Transforms/DeadArgElim/keepalive.ll @@ -28,4 +28,20 @@ define void @caller() { ret void } +; We can't remove 'this' here, as that would put argmem in ecx instead of +; memory. +define internal x86_thiscallcc i32 @unused_this(i32* %this, i32* inalloca %argmem) { + %v = load i32* %argmem + ret i32 %v +} +; CHECK-LABEL: define internal x86_thiscallcc i32 @unused_this(i32* %this, i32* inalloca %argmem) + +define i32 @caller2() { + %t = alloca i32 + %m = alloca inalloca i32 + store i32 42, i32* %m + %v = call x86_thiscallcc i32 @unused_this(i32* %t, i32* inalloca %m) + ret i32 %v +} + ; CHECK: attributes #0 = { nounwind } diff --git a/test/Transforms/DeadStoreElimination/PartialStore.ll b/test/Transforms/DeadStoreElimination/PartialStore.ll index 4799ef3383bc..80c2bfae846e 100644 --- a/test/Transforms/DeadStoreElimination/PartialStore.ll +++ b/test/Transforms/DeadStoreElimination/PartialStore.ll @@ -45,9 +45,9 @@ define void @test4(i8* %P) { store i8 19, i8* %P ;; dead %A = getelementptr i8* %P, i32 3 - + store i8 42, i8* %A ;; dead - + %Q = bitcast i8* %P to double* store double 0.0, double* %Q ret void @@ -61,7 +61,7 @@ define void @test5(i32 %i) nounwind ssp { %C = getelementptr i8* %B, i32 %i store i8 10, i8* %C ;; Dead store to variable index. store i32 20, i32* %A - + call void @test5a(i32* %A) ret void ; CHECK-LABEL: @test5( @@ -69,3 +69,19 @@ define void @test5(i32 %i) nounwind ssp { ; CHECK-NEXT: store i32 20 ; CHECK-NEXT: call void @test5a } + +declare void @test5a_as1(i32*) +define void @test5_addrspacecast(i32 %i) nounwind ssp { + %A = alloca i32 + %B = addrspacecast i32* %A to i8 addrspace(1)* + %C = getelementptr i8 addrspace(1)* %B, i32 %i + store i8 10, i8 addrspace(1)* %C ;; Dead store to variable index. + store i32 20, i32* %A + + call void @test5a(i32* %A) + ret void +; CHECK-LABEL: @test5_addrspacecast( +; CHECK-NEXT: alloca +; CHECK-NEXT: store i32 20 +; CHECK-NEXT: call void @test5a +} diff --git a/test/Transforms/DeadStoreElimination/cs-cs-aliasing.ll b/test/Transforms/DeadStoreElimination/cs-cs-aliasing.ll new file mode 100644 index 000000000000..8953f9ce0834 --- /dev/null +++ b/test/Transforms/DeadStoreElimination/cs-cs-aliasing.ll @@ -0,0 +1,74 @@ +; RUN: opt -basicaa -dse -S < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +%class.basic_string = type { %"class.__gnu_cxx::__versa_string" } +%"class.__gnu_cxx::__versa_string" = type { %"class.__gnu_cxx::__sso_string_base" } +%"class.__gnu_cxx::__sso_string_base" = type { %"struct.__gnu_cxx::__vstring_utility<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider", i64, %union.anon } +%"struct.__gnu_cxx::__vstring_utility<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider" = type { i8* } +%union.anon = type { i64, [8 x i8] } + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #0 + +; Function Attrs: noinline nounwind readonly uwtable +declare zeroext i1 @callee_takes_string(%class.basic_string* nonnull) #1 align 2 + +; Function Attrs: nounwind uwtable +define weak_odr zeroext i1 @test() #2 align 2 { + +; CHECK-LABEL: @test + +bb: + %tmp = alloca %class.basic_string, align 8 + %tmp1 = alloca %class.basic_string, align 8 + %tmp3 = getelementptr inbounds %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 2 + %tmp4 = bitcast %union.anon* %tmp3 to i8* + %tmp5 = getelementptr inbounds %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 0, i32 0 + %tmp6 = getelementptr inbounds %class.basic_string* %tmp, i64 0, i32 0, i32 0, i32 1 + %tmp7 = getelementptr inbounds i8* %tmp4, i64 1 + %tmp8 = bitcast %class.basic_string* %tmp to i8* + %tmp9 = bitcast i64 0 to i64 + %tmp10 = getelementptr inbounds %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 2 + %tmp11 = bitcast %union.anon* %tmp10 to i8* + %tmp12 = getelementptr inbounds %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 0, i32 0 + %tmp13 = getelementptr inbounds %class.basic_string* %tmp1, i64 0, i32 0, i32 0, i32 1 + %tmp14 = getelementptr inbounds i8* %tmp11, i64 1 + %tmp15 = bitcast %class.basic_string* %tmp1 to i8* + br label %_ZN12basic_stringIcSt11char_traitsIcESaIcEEC2EPKcRKS2_.exit + +_ZN12basic_stringIcSt11char_traitsIcESaIcEEC2EPKcRKS2_.exit: ; preds = %bb + store i8* %tmp4, i8** %tmp5, align 8 + store i8 62, i8* %tmp4, align 8 + store i64 1, i64* %tmp6, align 8 + store i8 0, i8* %tmp7, align 1 + %tmp16 = call zeroext i1 @callee_takes_string(%class.basic_string* nonnull %tmp) + br label %_ZN9__gnu_cxx17__sso_string_baseIcSt11char_traitsIcESaIcEED2Ev.exit3 + +_ZN9__gnu_cxx17__sso_string_baseIcSt11char_traitsIcESaIcEED2Ev.exit3: ; preds = %_ZN12basic_stringIcSt11char_traitsIcESaIcEEC2EPKcRKS2_.exit + +; CHECK: _ZN9__gnu_cxx17__sso_string_baseIcSt11char_traitsIcESaIcEED2Ev.exit3: + +; The following can be read through the call %tmp17: + store i8* %tmp11, i8** %tmp12, align 8 + store i8 125, i8* %tmp11, align 8 + store i64 1, i64* %tmp13, align 8 + store i8 0, i8* %tmp14, align 1 + +; CHECK: store i8* %tmp11, i8** %tmp12, align 8 +; CHECK: store i8 125, i8* %tmp11, align 8 +; CHECK: store i64 1, i64* %tmp13, align 8 +; CHECK: store i8 0, i8* %tmp14, align 1 + + %tmp17 = call zeroext i1 @callee_takes_string(%class.basic_string* nonnull %tmp1) + call void @llvm.memset.p0i8.i64(i8* %tmp11, i8 -51, i64 16, i32 8, i1 false) #0 + call void @llvm.memset.p0i8.i64(i8* %tmp15, i8 -51, i64 32, i32 8, i1 false) #0 + call void @llvm.memset.p0i8.i64(i8* %tmp4, i8 -51, i64 16, i32 8, i1 false) #0 + call void @llvm.memset.p0i8.i64(i8* %tmp8, i8 -51, i64 32, i32 8, i1 false) #0 + ret i1 %tmp17 +} + +attributes #0 = { nounwind } +attributes #1 = { noinline nounwind readonly uwtable } +attributes #2 = { nounwind uwtable } + diff --git a/test/Transforms/DeadStoreElimination/simple.ll b/test/Transforms/DeadStoreElimination/simple.ll index ec98466d33b9..1e813852b04c 100644 --- a/test/Transforms/DeadStoreElimination/simple.ll +++ b/test/Transforms/DeadStoreElimination/simple.ll @@ -105,6 +105,15 @@ define void @test9(%struct.x* byval %a) nounwind { ; CHECK-NEXT: ret void } +; Test for inalloca handling. +define void @test9_2(%struct.x* inalloca %a) nounwind { + %tmp2 = getelementptr %struct.x* %a, i32 0, i32 0 + store i32 1, i32* %tmp2, align 4 + ret void +; CHECK-LABEL: @test9_2( +; CHECK-NEXT: ret void +} + ; va_arg has fuzzy dependence, the store shouldn't be zapped. define double @test10(i8* %X) { %X_addr = alloca i8* @@ -163,6 +172,23 @@ define i32* @test13() { ; CHECK-NEXT: call void } +define i32 addrspace(1)* @test13_addrspacecast() { + %p = tail call i8* @malloc(i32 4) + %p.bc = bitcast i8* %p to i32* + %P = addrspacecast i32* %p.bc to i32 addrspace(1)* + %DEAD = load i32 addrspace(1)* %P + %DEAD2 = add i32 %DEAD, 1 + store i32 %DEAD2, i32 addrspace(1)* %P + call void @test13f( ) + store i32 0, i32 addrspace(1)* %P + ret i32 addrspace(1)* %P +; CHECK: @test13_addrspacecast() +; CHECK-NEXT: malloc +; CHECK-NEXT: bitcast +; CHECK-NEXT: addrspacecast +; CHECK-NEXT: call void +} + declare noalias i8* @malloc(i32) declare noalias i8* @calloc(i32, i32) diff --git a/test/Transforms/FunctionAttrs/nocapture.ll b/test/Transforms/FunctionAttrs/nocapture.ll index 110bd03dac73..d3842c8415ca 100644 --- a/test/Transforms/FunctionAttrs/nocapture.ll +++ b/test/Transforms/FunctionAttrs/nocapture.ll @@ -68,7 +68,7 @@ define i1* @lookup_bit(i32* %q, i32 %bitno) readnone nounwind { ret i1* %lookup } -; CHECK: define i1 @c7(i32* readnone %q, i32 %bitno) +; CHECK: define i1 @c7(i32* readonly %q, i32 %bitno) define i1 @c7(i32* %q, i32 %bitno) { %ptr = call i1* @lookup_bit(i32* %q, i32 %bitno) %val = load i1* %ptr @@ -91,6 +91,21 @@ l: ret i32 %val } +; CHECK: define i32 @nc1_addrspace(i32* %q, i32 addrspace(1)* nocapture %p, i1 %b) +define i32 @nc1_addrspace(i32* %q, i32 addrspace(1)* %p, i1 %b) { +e: + br label %l +l: + %x = phi i32 addrspace(1)* [ %p, %e ] + %y = phi i32* [ %q, %e ] + %tmp = addrspacecast i32 addrspace(1)* %x to i32* ; <i32*> [#uses=2] + %tmp2 = select i1 %b, i32* %tmp, i32* %y + %val = load i32* %tmp2 ; <i32> [#uses=1] + store i32 0, i32* %tmp + store i32* %y, i32** @g + ret i32 %val +} + ; CHECK: define void @nc2(i32* nocapture %p, i32* %q) define void @nc2(i32* %p, i32* %q) { %1 = call i32 @nc1(i32* %q, i32* %p, i1 0) ; <i32> [#uses=0] diff --git a/test/Transforms/FunctionAttrs/readattrs.ll b/test/Transforms/FunctionAttrs/readattrs.ll index 0842f566d124..b4e904cf9b04 100644 --- a/test/Transforms/FunctionAttrs/readattrs.ll +++ b/test/Transforms/FunctionAttrs/readattrs.ll @@ -45,3 +45,23 @@ define void @test6_2(i8** %p, i8* %q) { call void @test6_1() ret void } + +; CHECK: define void @test7_1(i32* inalloca nocapture %a) +; inalloca parameters are always considered written +define void @test7_1(i32* inalloca %a) { + ret void +} + +; CHECK: define i32* @test8_1(i32* readnone %p) +define i32* @test8_1(i32* %p) { +entry: + ret i32* %p +} + +; CHECK: define void @test8_2(i32* %p) +define void @test8_2(i32* %p) { +entry: + %call = call i32* @test8_1(i32* %p) + store i32 10, i32* %call, align 4 + ret void +} diff --git a/test/Transforms/GCOVProfiling/global-ctor.ll b/test/Transforms/GCOVProfiling/global-ctor.ll new file mode 100644 index 000000000000..722a0962ec57 --- /dev/null +++ b/test/Transforms/GCOVProfiling/global-ctor.ll @@ -0,0 +1,58 @@ +; RUN: echo '!16 = metadata !{metadata !"%T/global-ctor.ll", metadata !0}' > %t1 +; RUN: cat %s %t1 > %t2 +; RUN: opt -insert-gcov-profiling -disable-output < %t2 +; RUN: not grep '_GLOBAL__sub_I_global-ctor' %T/global-ctor.gcno +; RUN: rm %T/global-ctor.gcno + +; REQUIRES: shell + +@x = global i32 0, align 4 +@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @_GLOBAL__sub_I_global-ctor.ll, i8* null }] + +; Function Attrs: nounwind +define internal void @__cxx_global_var_init() #0 section ".text.startup" { +entry: + br label %0 + +; <label>:0 ; preds = %entry + %call = call i32 @_Z1fv(), !dbg !13 + store i32 %call, i32* @x, align 4, !dbg !13 + ret void, !dbg !13 +} + +declare i32 @_Z1fv() #1 + +; Function Attrs: nounwind +define internal void @_GLOBAL__sub_I_global-ctor.ll() #0 section ".text.startup" { +entry: + br label %0 + +; <label>:0 ; preds = %entry + call void @__cxx_global_var_init(), !dbg !14 + ret void, !dbg !14 +} + +attributes #0 = { nounwind } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!10, !11} +!llvm.gcov = !{!16} +!llvm.ident = !{!12} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5.0 (trunk 210217)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 2} ; [ DW_TAG_compile_unit ] [/home/nlewycky/<stdin>] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !"<stdin>", metadata !"/home/nlewycky"} +!2 = metadata !{} +!3 = metadata !{metadata !4, metadata !8} +!4 = metadata !{i32 786478, metadata !5, metadata !6, metadata !"__cxx_global_var_init", metadata !"__cxx_global_var_init", metadata !"", i32 2, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @__cxx_global_var_init, null, null, metadata !2, i32 2} ; [ DW_TAG_subprogram ] [line 2] [local] [def] [__cxx_global_var_init] +!5 = metadata !{metadata !"global-ctor.ll", metadata !"/home/nlewycky"} +!6 = metadata !{i32 786473, metadata !5} ; [ DW_TAG_file_type ] [/home/nlewycky/global-ctor.ll] +!7 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = metadata !{i32 786478, metadata !1, metadata !9, metadata !"", metadata !"", metadata !"_GLOBAL__sub_I_global-ctor.ll", i32 0, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 64, i1 false, void ()* @_GLOBAL__sub_I_global-ctor.ll, null, null, metadata !2, i32 0} ; [ DW_TAG_subprogram ] [line 0] [local] [def] +!9 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/home/nlewycky/<stdin>] +!10 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!11 = metadata !{i32 2, metadata !"Debug Info Version", i32 1} +!12 = metadata !{metadata !"clang version 3.5.0 (trunk 210217)"} +!13 = metadata !{i32 2, i32 0, metadata !4, null} +!14 = metadata !{i32 0, i32 0, metadata !15, null} +!15 = metadata !{i32 786443, metadata !5, metadata !8} ; [ DW_TAG_lexical_block ] [/home/nlewycky/global-ctor.ll] diff --git a/test/Transforms/GCOVProfiling/linezero.ll b/test/Transforms/GCOVProfiling/linezero.ll new file mode 100644 index 000000000000..e2f832498428 --- /dev/null +++ b/test/Transforms/GCOVProfiling/linezero.ll @@ -0,0 +1,143 @@ +; RUN: sed -e 's@PATTERN@\%T@g' < %s > %t1 +; RUN: opt -insert-gcov-profiling -disable-output < %t1 +; RUN: rm %T/linezero.gcno %t1 +; REQUIRES: shell + +; This is a crash test. + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +%struct.vector = type { i8 } + +; Function Attrs: nounwind +define i32 @_Z4testv() #0 { +entry: + %retval = alloca i32, align 4 + %__range = alloca %struct.vector*, align 8 + %ref.tmp = alloca %struct.vector, align 1 + %undef.agg.tmp = alloca %struct.vector, align 1 + %__begin = alloca i8*, align 8 + %__end = alloca i8*, align 8 + %spec = alloca i8, align 1 + call void @llvm.dbg.declare(metadata !{%struct.vector** %__range}, metadata !27), !dbg !30 + br label %0 + +; <label>:0 ; preds = %entry + call void @_Z13TagFieldSpecsv(), !dbg !31 + store %struct.vector* %ref.tmp, %struct.vector** %__range, align 8, !dbg !31 + call void @llvm.dbg.declare(metadata !{i8** %__begin}, metadata !32), !dbg !30 + %1 = load %struct.vector** %__range, align 8, !dbg !31 + %call = call i8* @_ZN6vector5beginEv(%struct.vector* %1), !dbg !31 + store i8* %call, i8** %__begin, align 8, !dbg !31 + call void @llvm.dbg.declare(metadata !{i8** %__end}, metadata !33), !dbg !30 + %2 = load %struct.vector** %__range, align 8, !dbg !31 + %call1 = call i8* @_ZN6vector3endEv(%struct.vector* %2), !dbg !31 + store i8* %call1, i8** %__end, align 8, !dbg !31 + br label %for.cond, !dbg !31 + +for.cond: ; preds = %for.inc, %0 + %3 = load i8** %__begin, align 8, !dbg !34 + %4 = load i8** %__end, align 8, !dbg !34 + %cmp = icmp ne i8* %3, %4, !dbg !34 + br i1 %cmp, label %for.body, label %for.end, !dbg !34 + +for.body: ; preds = %for.cond + call void @llvm.dbg.declare(metadata !{i8* %spec}, metadata !37), !dbg !31 + %5 = load i8** %__begin, align 8, !dbg !38 + %6 = load i8* %5, align 1, !dbg !38 + store i8 %6, i8* %spec, align 1, !dbg !38 + br label %for.inc, !dbg !38 + +for.inc: ; preds = %for.body + %7 = load i8** %__begin, align 8, !dbg !40 + %incdec.ptr = getelementptr inbounds i8* %7, i32 1, !dbg !40 + store i8* %incdec.ptr, i8** %__begin, align 8, !dbg !40 + br label %for.cond, !dbg !40 + +for.end: ; preds = %for.cond + call void @llvm.trap(), !dbg !42 + unreachable, !dbg !42 + +return: ; No predecessors! + %8 = load i32* %retval, !dbg !44 + ret i32 %8, !dbg !44 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata) #1 + +declare void @_Z13TagFieldSpecsv() #2 + +declare i8* @_ZN6vector5beginEv(%struct.vector*) #2 + +declare i8* @_ZN6vector3endEv(%struct.vector*) #2 + +; Function Attrs: noreturn nounwind +declare void @llvm.trap() #3 + +; Function Attrs: nounwind +define void @_Z2f1v() #0 { +entry: + br label %0 + +; <label>:0 ; preds = %entry + ret void, !dbg !45 +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } +attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { noreturn nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!23, !24} +!llvm.gcov = !{!25} +!llvm.ident = !{!26} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5.0 (trunk 209871)", i1 false, metadata !"", i32 0, metadata !2, metadata !3, metadata !14, metadata !2, metadata !2, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [<stdin>] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !"<stdin>", metadata !"PATTERN"} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786451, metadata !5, null, metadata !"vector", i32 21, i64 8, i64 8, i32 0, i32 0, null, metadata !6, i32 0, null, null, metadata !"_ZTS6vector"} ; [ DW_TAG_structure_type ] [vector] [line 21, size 8, align 8, offset 0] [def] [from ] +!5 = metadata !{metadata !"linezero.cc", metadata !"PATTERN"} +!6 = metadata !{metadata !7, metadata !13} +!7 = metadata !{i32 786478, metadata !5, metadata !"_ZTS6vector", metadata !"begin", metadata !"begin", metadata !"_ZN6vector5beginEv", i32 25, metadata !8, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, null, i32 25} ; [ DW_TAG_subprogram ] [line 25] [begin] +!8 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !9, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!9 = metadata !{metadata !10, metadata !12} +!10 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char] +!11 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char] +!12 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !"_ZTS6vector"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS6vector] +!13 = metadata !{i32 786478, metadata !5, metadata !"_ZTS6vector", metadata !"end", metadata !"end", metadata !"_ZN6vector3endEv", i32 26, metadata !8, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, null, i32 26} ; [ DW_TAG_subprogram ] [line 26] [end] +!14 = metadata !{metadata !15, metadata !20} +!15 = metadata !{i32 786478, metadata !5, metadata !16, metadata !"test", metadata !"test", metadata !"_Z4testv", i32 50, metadata !17, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z4testv, null, null, metadata !2, i32 50} ; [ DW_TAG_subprogram ] [line 50] [def] [test] +!16 = metadata !{i32 786473, metadata !5} ; [ DW_TAG_file_type ] [./linezero.cc] +!17 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !18, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!18 = metadata !{metadata !19} +!19 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!20 = metadata !{i32 786478, metadata !5, metadata !16, metadata !"f1", metadata !"f1", metadata !"_Z2f1v", i32 54, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z2f1v, null, null, metadata !2, i32 54} ; [ DW_TAG_subprogram ] [line 54] [def] [f1] +!21 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!22 = metadata !{null} +!23 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!24 = metadata !{i32 2, metadata !"Debug Info Version", i32 1} +!25 = metadata !{metadata !"PATTERN/linezero.o", metadata !0} +!26 = metadata !{metadata !"clang version 3.5.0 (trunk 209871)"} +!27 = metadata !{i32 786688, metadata !28, metadata !"__range", null, i32 0, metadata !29, i32 64, i32 0} ; [ DW_TAG_auto_variable ] [__range] [line 0] +!28 = metadata !{i32 786443, metadata !5, metadata !15, i32 51, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [./linezero.cc] +!29 = metadata !{i32 786498, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !"_ZTS6vector"} ; [ DW_TAG_rvalue_reference_type ] [line 0, size 0, align 0, offset 0] [from _ZTS6vector] +!30 = metadata !{i32 0, i32 0, metadata !28, null} +!31 = metadata !{i32 51, i32 0, metadata !28, null} +!32 = metadata !{i32 786688, metadata !28, metadata !"__begin", null, i32 0, metadata !10, i32 64, i32 0} ; [ DW_TAG_auto_variable ] [__begin] [line 0] +!33 = metadata !{i32 786688, metadata !28, metadata !"__end", null, i32 0, metadata !10, i32 64, i32 0} ; [ DW_TAG_auto_variable ] [__end] [line 0] +!34 = metadata !{i32 51, i32 0, metadata !35, null} +!35 = metadata !{i32 786443, metadata !5, metadata !36, i32 51, i32 0, i32 5, i32 5} ; [ DW_TAG_lexical_block ] [./linezero.cc] +!36 = metadata !{i32 786443, metadata !5, metadata !28, i32 51, i32 0, i32 1, i32 1} ; [ DW_TAG_lexical_block ] [./linezero.cc] +!37 = metadata !{i32 786688, metadata !28, metadata !"spec", metadata !16, i32 51, metadata !11, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [spec] [line 51] +!38 = metadata !{i32 51, i32 0, metadata !39, null} +!39 = metadata !{i32 786443, metadata !5, metadata !28, i32 51, i32 0, i32 2, i32 2} ; [ DW_TAG_lexical_block ] [./linezero.cc] +!40 = metadata !{i32 51, i32 0, metadata !41, null} +!41 = metadata !{i32 786443, metadata !5, metadata !28, i32 51, i32 0, i32 4, i32 4} ; [ DW_TAG_lexical_block ] [./linezero.cc] +!42 = metadata !{i32 51, i32 0, metadata !43, null} +!43 = metadata !{i32 786443, metadata !5, metadata !28, i32 51, i32 0, i32 3, i32 3} ; [ DW_TAG_lexical_block ] [./linezero.cc] +!44 = metadata !{i32 52, i32 0, metadata !15, null} +!45 = metadata !{i32 54, i32 0, metadata !20, null} diff --git a/test/Transforms/GCOVProfiling/version.ll b/test/Transforms/GCOVProfiling/version.ll index 2f1bd70f6df9..04f3f992b836 100644 --- a/test/Transforms/GCOVProfiling/version.ll +++ b/test/Transforms/GCOVProfiling/version.ll @@ -1,11 +1,11 @@ ; RUN: echo '!9 = metadata !{metadata !"%T/version.ll", metadata !0}' > %t1 ; RUN: cat %s %t1 > %t2 ; RUN: opt -insert-gcov-profiling -disable-output < %t2 -; RUN: head -c12 %T/version.gcno | grep '^oncg\*204MVLL$' +; RUN: head -c8 %T/version.gcno | grep '^oncg\*204' ; RUN: rm %T/version.gcno ; RUN: not opt -insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t2 ; RUN: opt -insert-gcov-profiling -default-gcov-version=407* -disable-output < %t2 -; RUN: head -c12 %T/version.gcno | grep '^oncg\*704MVLL$' +; RUN: head -c8 %T/version.gcno | grep '^oncg\*704' ; RUN: rm %T/version.gcno define void @test() { diff --git a/test/Transforms/GVN/2009-03-10-PREOnVoid.ll b/test/Transforms/GVN/2009-03-10-PREOnVoid.ll index 89d6a5f982b8..fd31fce59a84 100644 --- a/test/Transforms/GVN/2009-03-10-PREOnVoid.ll +++ b/test/Transforms/GVN/2009-03-10-PREOnVoid.ll @@ -53,30 +53,58 @@ bb11: ; preds = %bb7, %bb5 unreachable } -declare i32 @pthread_once(i32*, void ()*) +define i32 @pthread_once(i32*, void ()*) { + ret i32 0 +} -declare i8* @pthread_getspecific(i32) +define i8* @pthread_getspecific(i32) { + ret i8* null +} -declare i32 @pthread_setspecific(i32, i8*) +define i32 @pthread_setspecific(i32, i8*) { + ret i32 0 +} -declare i32 @pthread_create(i32*, %struct.pthread_attr_t*, i8* (i8*)*, i8*) +define i32 @pthread_create(i32*, %struct.pthread_attr_t*, i8* (i8*)*, i8*) { + ret i32 0 +} -declare i32 @pthread_cancel(i32) +define i32 @pthread_cancel(i32) { + ret i32 0 +} -declare i32 @pthread_mutex_lock(%struct.pthread_mutex_t*) +define i32 @pthread_mutex_lock(%struct.pthread_mutex_t*) { + ret i32 0 +} -declare i32 @pthread_mutex_trylock(%struct.pthread_mutex_t*) +define i32 @pthread_mutex_trylock(%struct.pthread_mutex_t*) { + ret i32 0 +} -declare i32 @pthread_mutex_unlock(%struct.pthread_mutex_t*) +define i32 @pthread_mutex_unlock(%struct.pthread_mutex_t*) { + ret i32 0 +} -declare i32 @pthread_mutex_init(%struct.pthread_mutex_t*, %struct.__sched_param*) +define i32 @pthread_mutex_init(%struct.pthread_mutex_t*, %struct.__sched_param*) { + ret i32 0 +} -declare i32 @pthread_key_create(i32*, void (i8*)*) +define i32 @pthread_key_create(i32*, void (i8*)*) { + ret i32 0 +} -declare i32 @pthread_key_delete(i32) +define i32 @pthread_key_delete(i32) { + ret i32 0 +} -declare i32 @pthread_mutexattr_init(%struct.__sched_param*) +define i32 @pthread_mutexattr_init(%struct.__sched_param*) { + ret i32 0 +} -declare i32 @pthread_mutexattr_settype(%struct.__sched_param*, i32) +define i32 @pthread_mutexattr_settype(%struct.__sched_param*, i32) { + ret i32 0 +} -declare i32 @pthread_mutexattr_destroy(%struct.__sched_param*) +define i32 @pthread_mutexattr_destroy(%struct.__sched_param*) { + ret i32 0 +} diff --git a/test/Transforms/GVN/calloc-load-removal.ll b/test/Transforms/GVN/calloc-load-removal.ll new file mode 100644 index 000000000000..2dde5b7b4146 --- /dev/null +++ b/test/Transforms/GVN/calloc-load-removal.ll @@ -0,0 +1,25 @@ +; RUN: opt -S -basicaa -gvn < %s | FileCheck %s +; RUN: opt -S -basicaa -gvn -disable-simplify-libcalls < %s | FileCheck %s -check-prefix=CHECK_NO_LIBCALLS +; Check that loads from calloc are recognized as being zero. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +; Function Attrs: nounwind uwtable +define i32 @test1() { + %1 = tail call noalias i8* @calloc(i64 1, i64 4) + %2 = bitcast i8* %1 to i32* + ; This load is trivially constant zero + %3 = load i32* %2, align 4 + ret i32 %3 + +; CHECK-LABEL: @test1( +; CHECK-NOT: %3 = load i32* %2, align 4 +; CHECK: ret i32 0 + +; CHECK_NO_LIBCALLS-LABEL: @test1( +; CHECK_NO_LIBCALLS: load +; CHECK_NO_LIBCALLS: ret i32 % + +} + +declare noalias i8* @calloc(i64, i64) diff --git a/test/Transforms/GVN/invariant-load.ll b/test/Transforms/GVN/invariant-load.ll new file mode 100644 index 000000000000..80e2226b5fae --- /dev/null +++ b/test/Transforms/GVN/invariant-load.ll @@ -0,0 +1,31 @@ +; Test if the !invariant.load metadata is maintained by GVN. +; RUN: opt -basicaa -gvn -S < %s | FileCheck %s + +define i32 @test1(i32* nocapture %p, i8* nocapture %q) { +; CHECK-LABEL: test1 +; CHECK: %x = load i32* %p, align 4, !invariant.load !0 +; CHECK-NOT: %y = load +entry: + %x = load i32* %p, align 4, !invariant.load !0 + %conv = trunc i32 %x to i8 + store i8 %conv, i8* %q, align 1 + %y = load i32* %p, align 4, !invariant.load !0 + %add = add i32 %y, 1 + ret i32 %add +} + +define i32 @test2(i32* nocapture %p, i8* nocapture %q) { +; CHECK-LABEL: test2 +; CHECK-NOT: !invariant.load +; CHECK-NOT: %y = load +entry: + %x = load i32* %p, align 4 + %conv = trunc i32 %x to i8 + store i8 %conv, i8* %q, align 1 + %y = load i32* %p, align 4, !invariant.load !0 + %add = add i32 %y, 1 + ret i32 %add +} + +!0 = metadata !{ } + diff --git a/test/Transforms/GVN/load-pre-nonlocal.ll b/test/Transforms/GVN/load-pre-nonlocal.ll new file mode 100644 index 000000000000..7bac1b78e6a2 --- /dev/null +++ b/test/Transforms/GVN/load-pre-nonlocal.ll @@ -0,0 +1,87 @@ +; RUN: opt -S -o - -basicaa -domtree -gvn %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +%struct.S1 = type { i32, i32 } + +@a2 = common global i32* null, align 8 +@a = common global i32* null, align 8 +@s1 = common global %struct.S1 zeroinitializer, align 8 + +; Check that GVN doesn't determine %2 is partially redundant. + +; CHECK-LABEL: define i32 @volatile_load +; CHECK: for.body: +; CHECK: %2 = load i32* +; CHECK: %3 = load volatile i32* +; CHECK: for.cond.for.end_crit_edge: + +define i32 @volatile_load(i32 %n) { +entry: + %cmp6 = icmp sgt i32 %n, 0 + br i1 %cmp6, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: + %0 = load i32** @a2, align 8, !tbaa !1 + %1 = load i32** @a, align 8, !tbaa !1 + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ] + %s.09 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ] + %p.08 = phi i32* [ %0, %for.body.lr.ph ], [ %incdec.ptr, %for.body ] + %2 = load i32* %p.08, align 4, !tbaa !5 + %arrayidx = getelementptr inbounds i32* %1, i64 %indvars.iv + store i32 %2, i32* %arrayidx, align 4, !tbaa !5 + %3 = load volatile i32* %p.08, align 4, !tbaa !5 + %add = add nsw i32 %3, %s.09 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %incdec.ptr = getelementptr inbounds i32* %p.08, i64 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp ne i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge + +for.cond.for.end_crit_edge: + %add.lcssa = phi i32 [ %add, %for.body ] + br label %for.end + +for.end: + %s.0.lcssa = phi i32 [ %add.lcssa, %for.cond.for.end_crit_edge ], [ 0, %entry ] + ret i32 %s.0.lcssa +} + +; %1 is partially redundant if %0 can be widened to a 64-bit load. + +; CHECK-LABEL: define i32 @overaligned_load +; CHECK: if.end: +; CHECK-NOT: %1 = load i32* + +define i32 @overaligned_load(i32 %a, i32* nocapture %b) { +entry: + %cmp = icmp sgt i32 %a, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: + %0 = load i32* getelementptr inbounds (%struct.S1* @s1, i64 0, i32 0), align 8, !tbaa !5 + br label %if.end + +if.else: + %arrayidx = getelementptr inbounds i32* %b, i64 2 + store i32 10, i32* %arrayidx, align 4, !tbaa !5 + br label %if.end + +if.end: + %i.0 = phi i32 [ %0, %if.then ], [ 0, %if.else ] + %p.0 = phi i32* [ getelementptr inbounds (%struct.S1* @s1, i64 0, i32 0), %if.then ], [ %b, %if.else ] + %add.ptr = getelementptr inbounds i32* %p.0, i64 1 + %1 = load i32* %add.ptr, align 4, !tbaa !5 + %add1 = add nsw i32 %1, %i.0 + ret i32 %add1 +} + +!1 = metadata !{metadata !2, metadata !2, i64 0} +!2 = metadata !{metadata !"any pointer", metadata !3, i64 0} +!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} +!4 = metadata !{metadata !"Simple C/C++ TBAA"} +!5 = metadata !{metadata !6, metadata !6, i64 0} +!6 = metadata !{metadata !"int", metadata !3, i64 0} diff --git a/test/Transforms/GVN/rle.ll b/test/Transforms/GVN/rle.ll index 8d289b06997c..6aac93e75a78 100644 --- a/test/Transforms/GVN/rle.ll +++ b/test/Transforms/GVN/rle.ll @@ -318,6 +318,19 @@ define i8 @coerce_offset0(i32 %V, i32* %P) { ; CHECK: ret i8 } +define i8 @coerce_offset0_addrspacecast(i32 %V, i32* %P) { + store i32 %V, i32* %P + + %P2 = addrspacecast i32* %P to i8 addrspace(1)* + %P3 = getelementptr i8 addrspace(1)* %P2, i32 2 + + %A = load i8 addrspace(1)* %P3 + ret i8 %A +; CHECK-LABEL: @coerce_offset0_addrspacecast( +; CHECK-NOT: load +; CHECK: ret i8 +} + ;; non-local i32/float -> i8 load forwarding. define i8 @coerce_offset_nonlocal0(i32* %P, i1 %cond) { %P2 = bitcast i32* %P to float* diff --git a/test/Transforms/GVN/unreachable_block_infinite_loop.ll b/test/Transforms/GVN/unreachable_block_infinite_loop.ll index fe335ced5c37..fca5a28b38dd 100644 --- a/test/Transforms/GVN/unreachable_block_infinite_loop.ll +++ b/test/Transforms/GVN/unreachable_block_infinite_loop.ll @@ -1,4 +1,4 @@ -; RUN: opt -memdep -gvn -disable-output +; RUN: opt -memdep -gvn -disable-output < %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0" diff --git a/test/Transforms/GlobalDCE/2009-01-05-DeadAliases.ll b/test/Transforms/GlobalDCE/2009-01-05-DeadAliases.ll index 6658cee12239..0bdced5114d3 100644 --- a/test/Transforms/GlobalDCE/2009-01-05-DeadAliases.ll +++ b/test/Transforms/GlobalDCE/2009-01-05-DeadAliases.ll @@ -1,8 +1,18 @@ -; RUN: opt < %s -globaldce -S | not grep @D -; RUN: opt < %s -globaldce -S | grep @L | count 3 +; RUN: opt < %s -globaldce -S > %t +; RUN: FileCheck %s < %t +; RUN: FileCheck --check-prefix=DEAD %s < %t @A = global i32 0 +; CHECK: @A = global i32 0 + @D = alias internal i32* @A +; DEAD-NOT: @D + @L1 = alias i32* @A +; CHECK: @L1 = alias i32* @A + @L2 = alias internal i32* @L1 +; CHECK: @L2 = alias internal i32* @L1 + @L3 = alias i32* @L2 +; CHECK: @L3 = alias i32* @L2 diff --git a/test/Transforms/GlobalDCE/global_ctors.ll b/test/Transforms/GlobalDCE/global_ctors.ll new file mode 100644 index 000000000000..91bb9ab7f6bc --- /dev/null +++ b/test/Transforms/GlobalDCE/global_ctors.ll @@ -0,0 +1,14 @@ +; RUN: opt -S -globaldce < %s | FileCheck %s + +; CHECK: @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_notremovable }] +; CHECK-NOT: @_GLOBAL__I_a + +declare void @_notremovable() + +@llvm.global_ctors = appending global [2 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }, { i32, void ()* } { i32 65535, void ()* @_notremovable }] + +; Function Attrs: nounwind readnone +define internal void @_GLOBAL__I_a() #1 section "__TEXT,__StaticInit,regular,pure_instructions" { +entry: + ret void +} diff --git a/test/Transforms/GlobalDCE/global_ctors_integration.ll b/test/Transforms/GlobalDCE/global_ctors_integration.ll new file mode 100644 index 000000000000..5e6cc79f103c --- /dev/null +++ b/test/Transforms/GlobalDCE/global_ctors_integration.ll @@ -0,0 +1,45 @@ +; RUN: opt -S -O2 < %s | FileCheck %s + +; This test checks that -O2 is able to delete constructors that become empty +; only after some optimization passes have run, even if the pass structure +; changes. +; CHECK-NOT: @_GLOBAL__I_a + +%class.Foo = type { i32 } + +@foo = global %class.Foo zeroinitializer, align 4 +@_ZN3Bar18LINKER_INITIALIZEDE = external constant i32 +@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }] + +define internal void @__cxx_global_var_init() section "__TEXT,__StaticInit,regular,pure_instructions" { + %1 = load i32* @_ZN3Bar18LINKER_INITIALIZEDE, align 4 + call void @_ZN3FooC1E17LinkerInitialized(%class.Foo* @foo, i32 %1) + ret void +} + +; Function Attrs: ssp uwtable +define linkonce_odr void @_ZN3FooC1E17LinkerInitialized(%class.Foo* %this, i32) unnamed_addr #0 align 2 { + %2 = alloca %class.Foo*, align 8 + %3 = alloca i32, align 4 + store %class.Foo* %this, %class.Foo** %2, align 8 + store i32 %0, i32* %3, align 4 + %4 = load %class.Foo** %2 + %5 = load i32* %3, align 4 + call void @_ZN3FooC2E17LinkerInitialized(%class.Foo* %4, i32 %5) + ret void +} + +; Function Attrs: nounwind ssp uwtable +define linkonce_odr void @_ZN3FooC2E17LinkerInitialized(%class.Foo* %this, i32) unnamed_addr #1 align 2 { + %2 = alloca %class.Foo*, align 8 + %3 = alloca i32, align 4 + store %class.Foo* %this, %class.Foo** %2, align 8 + store i32 %0, i32* %3, align 4 + %4 = load %class.Foo** %2 + ret void +} + +define internal void @_GLOBAL__I_a() section "__TEXT,__StaticInit,regular,pure_instructions" { + call void @__cxx_global_var_init() + ret void +} diff --git a/test/Transforms/GlobalOpt/2009-02-15-BitcastAlias.ll b/test/Transforms/GlobalOpt/2009-02-15-BitcastAlias.ll index a1b69efe1a76..d6a565ad10a8 100644 --- a/test/Transforms/GlobalOpt/2009-02-15-BitcastAlias.ll +++ b/test/Transforms/GlobalOpt/2009-02-15-BitcastAlias.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -globalopt -@g = external global i32 +@g = global i32 0 @a = alias bitcast (i32* @g to i8*) diff --git a/test/Transforms/GlobalOpt/2009-03-06-Anonymous.ll b/test/Transforms/GlobalOpt/2009-03-06-Anonymous.ll index 62f75e123be7..930a96e2182f 100644 --- a/test/Transforms/GlobalOpt/2009-03-06-Anonymous.ll +++ b/test/Transforms/GlobalOpt/2009-03-06-Anonymous.ll @@ -1,11 +1,23 @@ -; RUN: opt < %s -globalopt -S | grep internal | count 2 +; RUN: opt < %s -globalopt -S | FileCheck %s global i32 0 -define i32* @1() { +; CHECK-DAG: @0 = internal global i32 0 + +private global i32 0 +; CHECK-DAG: @1 = private global i32 0 + +define i32* @2() { ret i32* @0 } +; CHECK-DAG: define internal fastcc i32* @2() + define i32* @f() { entry: - call i32* @1() + call i32* @2() ret i32* %0 } + +define i32* @g() { +entry: + ret i32* @1 +} diff --git a/test/Transforms/GlobalOpt/alias-resolve.ll b/test/Transforms/GlobalOpt/alias-resolve.ll index 32f4bf8ebe25..9d70c708aad8 100644 --- a/test/Transforms/GlobalOpt/alias-resolve.ll +++ b/test/Transforms/GlobalOpt/alias-resolve.ll @@ -1,31 +1,39 @@ -; We use a temporary file so that the test fails when opt crashes. - -; RUN: opt < %s -globalopt -S > %t -; RUN: FileCheck %s < %t +; RUN: opt < %s -globalopt -S | FileCheck %s @foo1 = alias void ()* @foo2 -; CHECK: @foo1 = alias void ()* @foo2 +; CHECK: @foo1 = alias void ()* @bar2 -@foo2 = alias weak void()* @bar1 -; CHECK: @foo2 = alias weak void ()* @bar2 +@foo2 = alias void()* @bar1 +; CHECK: @foo2 = alias void ()* @bar2 @bar1 = alias void ()* @bar2 ; CHECK: @bar1 = alias void ()* @bar2 -declare void @bar2() -; CHECK: declare void @bar2() +@weak1 = alias weak void ()* @bar2 +; CHECK: @weak1 = alias weak void ()* @bar2 + +@bar4 = private unnamed_addr constant [2 x i8*] zeroinitializer +@foo4 = unnamed_addr alias linkonce_odr getelementptr inbounds ([2 x i8*]* @bar4, i32 0, i32 1) +; CHECK: @foo4 = unnamed_addr alias linkonce_odr getelementptr inbounds ([2 x i8*]* @bar4, i32 0, i32 1) + +define void @bar2() { + ret void +} +; CHECK: define void @bar2() define void @baz() { entry: call void @foo1() -; CHECK: call void @foo2() +; CHECK: call void @bar2() call void @foo2() -; CHECK: call void @foo2() +; CHECK: call void @bar2() call void @bar1() ; CHECK: call void @bar2() + call void @weak1() +; CHECK: call void @weak1() ret void } diff --git a/test/Transforms/GlobalOpt/alias-used-address-space.ll b/test/Transforms/GlobalOpt/alias-used-address-space.ll new file mode 100644 index 000000000000..633cd344a796 --- /dev/null +++ b/test/Transforms/GlobalOpt/alias-used-address-space.ll @@ -0,0 +1,26 @@ +; RUN: opt -S -globalopt < %s | FileCheck %s + +target datalayout = "p:32:32:32-p1:16:16:16" + +@c = addrspace(1) global i8 42 + +@i = internal addrspace(1) global i8 42 + +; CHECK: @ia = internal addrspace(1) global i8 42 +@ia = alias internal i8 addrspace(1)* @i + +@llvm.used = appending global [1 x i8*] [i8* addrspacecast (i8 addrspace(1)* @ca to i8*)], section "llvm.metadata" +; CHECK-DAG: @llvm.used = appending global [1 x i8*] [i8* addrspacecast (i8 addrspace(1)* @ca to i8*)], section "llvm.metadata" + +@llvm.compiler.used = appending global [2 x i8*] [i8* addrspacecast(i8 addrspace(1)* @ia to i8*), i8* addrspacecast (i8 addrspace(1)* @i to i8*)], section "llvm.metadata" +; CHECK-DAG: @llvm.compiler.used = appending global [1 x i8*] [i8* addrspacecast (i8 addrspace(1)* @ia to i8*)], section "llvm.metadata" + +@sameAsUsed = global [1 x i8*] [i8* addrspacecast(i8 addrspace(1)* @ca to i8*)] +; CHECK-DAG: @sameAsUsed = global [1 x i8*] [i8* addrspacecast (i8 addrspace(1)* @c to i8*)] + +@ca = alias internal i8 addrspace(1)* @c +; CHECK: @ca = alias internal i8 addrspace(1)* @c + +define i8 addrspace(1)* @h() { + ret i8 addrspace(1)* @ca +} diff --git a/test/Transforms/GlobalOpt/alias-used-section.ll b/test/Transforms/GlobalOpt/alias-used-section.ll new file mode 100644 index 000000000000..121793724d72 --- /dev/null +++ b/test/Transforms/GlobalOpt/alias-used-section.ll @@ -0,0 +1,8 @@ +; RUN: opt -S -globalopt < %s | FileCheck %s + +@_Z17in_custom_section = internal global i8 42, section "CUSTOM" +@in_custom_section = dllexport alias internal i8* @_Z17in_custom_section + +; CHECK: @in_custom_section = internal dllexport global i8 42, section "CUSTOM" + +@llvm.used = appending global [1 x i8*] [i8* @in_custom_section], section "llvm.metadata" diff --git a/test/Transforms/GlobalOpt/atexit.ll b/test/Transforms/GlobalOpt/atexit.ll index dbcd0d7b00bd..55c2dab1c1d7 100644 --- a/test/Transforms/GlobalOpt/atexit.ll +++ b/test/Transforms/GlobalOpt/atexit.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -globalopt -S | FileCheck %s ; CHECK: ModuleID -define internal hidden i32 @__cxa_atexit(void (i8*)* nocapture %func, i8* nocapture %arg, i8* nocapture %dso_handle) nounwind readnone optsize noimplicitfloat { +define internal i32 @__cxa_atexit(void (i8*)* nocapture %func, i8* nocapture %arg, i8* nocapture %dso_handle) nounwind readnone optsize noimplicitfloat { unreachable } diff --git a/test/Transforms/GlobalOpt/constantfold-initializers.ll b/test/Transforms/GlobalOpt/constantfold-initializers.ll index ce6e2c46d627..4a25d661edcf 100644 --- a/test/Transforms/GlobalOpt/constantfold-initializers.ll +++ b/test/Transforms/GlobalOpt/constantfold-initializers.ll @@ -50,7 +50,41 @@ entry: ret void } +; PR19955 + +@dllimportptr = global i32* null, align 4 +; CHECK: @dllimportptr = global i32* null, align 4 +@dllimportvar = external dllimport global i32 +define internal void @test3() { +entry: + store i32* @dllimportvar, i32** @dllimportptr, align 4 + ret void +} + +@dllexportptr = global i32* null, align 4 +; CHECK: @dllexportptr = global i32* @dllexportvar, align 4 +@dllexportvar = dllexport global i32 0, align 4 +; CHECK: @dllexportvar = dllexport global i32 20, align 4 +define internal void @test4() { +entry: + store i32 20, i32* @dllexportvar, align 4 + store i32* @dllexportvar, i32** @dllexportptr, align 4 + ret void +} + +@threadlocalptr = global i32* null, align 4 +; CHECK: @threadlocalptr = global i32* null, align 4 +@threadlocalvar = external thread_local global i32 +define internal void @test5() { +entry: + store i32* @threadlocalvar, i32** @threadlocalptr, align 4 + ret void +} + @llvm.global_ctors = appending constant - [2 x { i32, void ()* }] + [5 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @test1 }, - { i32, void ()* } { i32 65535, void ()* @test2 }] + { i32, void ()* } { i32 65535, void ()* @test2 }, + { i32, void ()* } { i32 65535, void ()* @test3 }, + { i32, void ()* } { i32 65535, void ()* @test4 }, + { i32, void ()* } { i32 65535, void ()* @test5 }] diff --git a/test/Transforms/GlobalOpt/ctor-list-opt.ll b/test/Transforms/GlobalOpt/ctor-list-opt.ll index 542c786762ea..450bdb830284 100644 --- a/test/Transforms/GlobalOpt/ctor-list-opt.ll +++ b/test/Transforms/GlobalOpt/ctor-list-opt.ll @@ -1,5 +1,20 @@ -; RUN: opt < %s -globalopt -S | not grep CTOR -@llvm.global_ctors = appending global [11 x { i32, void ()* }] [ { i32, void ()* } { i32 65535, void ()* @CTOR1 }, { i32, void ()* } { i32 65535, void ()* @CTOR1 }, { i32, void ()* } { i32 65535, void ()* @CTOR2 }, { i32, void ()* } { i32 65535, void ()* @CTOR3 }, { i32, void ()* } { i32 65535, void ()* @CTOR4 }, { i32, void ()* } { i32 65535, void ()* @CTOR5 }, { i32, void ()* } { i32 65535, void ()* @CTOR6 }, { i32, void ()* } { i32 65535, void ()* @CTOR7 }, { i32, void ()* } { i32 65535, void ()* @CTOR8 }, { i32, void ()* } { i32 65535, void ()* @CTOR9 }, { i32, void ()* } { i32 2147483647, void ()* null } ] ; <[10 x { i32, void ()* }]*> [#uses=0] +; RUN: opt < %s -globalopt -S | FileCheck %s +; CHECK-NOT: CTOR +%ini = type { i32, void()*, i8* } +@llvm.global_ctors = appending global [11 x %ini] [ + %ini { i32 65535, void ()* @CTOR1, i8* null }, + %ini { i32 65535, void ()* @CTOR1, i8* null }, + %ini { i32 65535, void ()* @CTOR2, i8* null }, + %ini { i32 65535, void ()* @CTOR3, i8* null }, + %ini { i32 65535, void ()* @CTOR4, i8* null }, + %ini { i32 65535, void ()* @CTOR5, i8* null }, + %ini { i32 65535, void ()* @CTOR6, i8* null }, + %ini { i32 65535, void ()* @CTOR7, i8* null }, + %ini { i32 65535, void ()* @CTOR8, i8* null }, + %ini { i32 65535, void ()* @CTOR9, i8* null }, + %ini { i32 2147483647, void ()* null, i8* null } +] + @G = global i32 0 ; <i32*> [#uses=1] @G2 = global i32 0 ; <i32*> [#uses=1] @G3 = global i32 -123 ; <i32*> [#uses=2] diff --git a/test/Transforms/GlobalOpt/fastcc.ll b/test/Transforms/GlobalOpt/fastcc.ll new file mode 100644 index 000000000000..76122b203d79 --- /dev/null +++ b/test/Transforms/GlobalOpt/fastcc.ll @@ -0,0 +1,46 @@ +; RUN: opt < %s -globalopt -S | FileCheck %s + +define internal i32 @f(i32* %m) { +; CHECK-LABEL: define internal fastcc i32 @f + %v = load i32* %m + ret i32 %v +} + +define internal x86_thiscallcc i32 @g(i32* %m) { +; CHECK-LABEL: define internal fastcc i32 @g + %v = load i32* %m + ret i32 %v +} + +; Leave this one alone, because the user went out of their way to request this +; convention. +define internal coldcc i32 @h(i32* %m) { +; CHECK-LABEL: define internal coldcc i32 @h + %v = load i32* %m + ret i32 %v +} + +define internal i32 @j(i32* %m) { +; CHECK-LABEL: define internal i32 @j + %v = load i32* %m + ret i32 %v +} + +define void @call_things() { + %m = alloca i32 + call i32 @f(i32* %m) + call x86_thiscallcc i32 @g(i32* %m) + call coldcc i32 @h(i32* %m) + call i32 @j(i32* %m) + ret void +} + +@llvm.used = appending global [1 x i8*] [ + i8* bitcast (i32(i32*)* @j to i8*) +], section "llvm.metadata" + +; CHECK-LABEL: define void @call_things() +; CHECK: call fastcc i32 @f +; CHECK: call fastcc i32 @g +; CHECK: call coldcc i32 @h +; CHECK: call i32 @j diff --git a/test/Transforms/GlobalOpt/memset.ll b/test/Transforms/GlobalOpt/memset.ll index 3bb5ce92d082..85320b7f2461 100644 --- a/test/Transforms/GlobalOpt/memset.ll +++ b/test/Transforms/GlobalOpt/memset.ll @@ -1,6 +1,8 @@ -; both globals are write only, delete them. +; RUN: opt -S -globalopt < %s | FileCheck %s -; RUN: opt < %s -globalopt -S | not grep internal +; CHECK-NOT: internal + +; Both globals are write only, delete them. @G0 = internal global [58 x i8] c"asdlfkajsdlfkajsd;lfkajds;lfkjasd;flkajsd;lkfja;sdlkfjasd\00" ; <[58 x i8]*> [#uses=1] @G1 = internal global [4 x i32] [ i32 1, i32 2, i32 3, i32 4 ] ; <[4 x i32]*> [#uses=1] @@ -13,6 +15,17 @@ define void @foo() { ret void } -declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind +@G0_as1 = internal addrspace(1) global [58 x i8] c"asdlfkajsdlfkajsd;lfkajds;lfkjasd;flkajsd;lkfja;sdlkfjasd\00" ; <[58 x i8]*> [#uses=1] +@G1_as1 = internal addrspace(1) global [4 x i32] [ i32 1, i32 2, i32 3, i32 4 ] ; <[4 x i32]*> [#uses=1] + +define void @foo_as1() { + %Blah = alloca [58 x i8] + %tmp3 = bitcast [58 x i8]* %Blah to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* addrspacecast ([4 x i32] addrspace(1)* @G1_as1 to i8*), i8* %tmp3, i32 16, i32 1, i1 false) + call void @llvm.memset.p1i8.i32(i8 addrspace(1)* getelementptr inbounds ([58 x i8] addrspace(1)* @G0_as1, i32 0, i32 0), i8 17, i32 58, i32 1, i1 false) + ret void +} +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind +declare void @llvm.memset.p1i8.i32(i8 addrspace(1)* nocapture, i8, i32, i32, i1) nounwind
\ No newline at end of file diff --git a/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll b/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll index bd174a8be3ff..4ea0b88fd0de 100644 --- a/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll +++ b/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as <%s | opt -ipsccp | llvm-dis | FileCheck %s +; RUN: opt < %s -ipsccp -S | FileCheck %s ; Don't constant-propagate byval pointers, since they are not pointers! ; PR5038 %struct.MYstr = type { i8, i32 } diff --git a/test/Transforms/IndVarSimplify/2014-06-21-congruent-constant.ll b/test/Transforms/IndVarSimplify/2014-06-21-congruent-constant.ll new file mode 100644 index 000000000000..2c738de32e0a --- /dev/null +++ b/test/Transforms/IndVarSimplify/2014-06-21-congruent-constant.ll @@ -0,0 +1,57 @@ +; RUN: opt -S -loop-unswitch -instcombine -indvars < %s | FileCheck %s + +; This used to crash in SCEVExpander when there were congruent phis with and +; undef incoming value from the loop header. The -loop-unswitch -instcombine is +; necessary to create just this pattern, which is essentially a nop and gets +; folded away aggressively if spelled out in IR directly. +; PR 20093 + +@c = external global i32**, align 8 + +define void @test1() { +entry: + br i1 undef, label %for.end12, label %for.cond.preheader + +for.cond.preheader: ; preds = %entry + %0 = load i32*** @c, align 8 + %1 = load i32** %0, align 8 + %2 = load i32* %1, align 4 + br label %for.body + +for.body: ; preds = %for.cond.backedge, %for.body9.us, %for.cond.preheader + %3 = phi i32* [ %1, %for.cond.preheader ], [ %3, %for.cond.backedge ], [ %6, %for.body9.us ] + %4 = phi i32 [ %2, %for.cond.preheader ], [ undef, %for.cond.backedge ], [ %7, %for.body9.us ] + %i.024 = phi i32 [ 0, %for.cond.preheader ], [ %inc, %for.cond.backedge ], [ 0, %for.body9.us ] + %tobool1 = icmp eq i32 %4, 0 + br i1 %tobool1, label %if.end, label %for.cond.backedge + +if.end: ; preds = %for.body + %5 = load i32* %3, align 4 + %tobool4 = icmp eq i32 %5, 0 + br i1 %tobool4, label %for.cond3, label %for.body9.preheader + +for.body9.preheader: ; preds = %if.end + %tobool8 = icmp eq i32 %i.024, 1 + br i1 %tobool8, label %for.body9.us, label %for.body9 + +for.body9.us: ; preds = %for.body9.preheader + %6 = load i32** undef, align 8 + %7 = load i32* %6, align 4 + br label %for.body + +for.cond3: ; preds = %for.cond3, %if.end + br label %for.cond3 + +for.body9: ; preds = %for.body9, %for.body9.preheader + br label %for.body9 + +for.cond.backedge: ; preds = %for.body + %inc = add nsw i32 %i.024, 1 + br i1 false, label %for.body, label %for.end12 + +for.end12: ; preds = %for.cond.backedge, %entry + ret void + +; CHECK-LABEL: @test1 +; CHECK-NOT: phi +} diff --git a/test/Transforms/IndVarSimplify/iv-widen.ll b/test/Transforms/IndVarSimplify/iv-widen.ll new file mode 100644 index 000000000000..c899e2f0a580 --- /dev/null +++ b/test/Transforms/IndVarSimplify/iv-widen.ll @@ -0,0 +1,40 @@ +; RUN: opt < %s -indvars -S | FileCheck %s + +target triple = "x86_64-apple-darwin" + +; CHECK-LABEL: @sloop +; CHECK-LABEL: B18: +; Only one phi now. +; CHECK: phi +; CHECK-NOT: phi +; One trunc for the gep. +; CHECK: trunc i64 %indvars.iv to i32 +; One trunc for the dummy() call. +; CHECK-LABEL: exit24: +; CHECK: trunc i64 {{.*}}lcssa.wide to i32 +define void @sloop(i32* %a) { +Prologue: + br i1 undef, label %B18, label %B6 + +B18: ; preds = %B24, %Prologue + %.02 = phi i32 [ 0, %Prologue ], [ %tmp33, %B24 ] + %tmp23 = zext i32 %.02 to i64 + %tmp33 = add i32 %.02, 1 + %o = getelementptr i32* %a, i32 %.02 + %v = load i32* %o + %t = icmp eq i32 %v, 0 + br i1 %t, label %exit24, label %B24 + +B24: ; preds = %B18 + %t2 = icmp eq i32 %tmp33, 20 + br i1 %t2, label %B6, label %B18 + +B6: ; preds = %Prologue + ret void + +exit24: ; preds = %B18 + call void @dummy(i32 %.02) + unreachable +} + +declare void @dummy(i32) diff --git a/test/Transforms/IndVarSimplify/lcssa-preservation.ll b/test/Transforms/IndVarSimplify/lcssa-preservation.ll new file mode 100644 index 000000000000..f69c96ce0210 --- /dev/null +++ b/test/Transforms/IndVarSimplify/lcssa-preservation.ll @@ -0,0 +1,51 @@ +; RUN: opt < %s -indvars -S | FileCheck %s +; +; Make sure IndVars preserves LCSSA form, especially across loop nests. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @PR18642(i32 %x) { +; CHECK-LABEL: @PR18642( +entry: + br label %outer.header +; CHECK: br label %outer.header + +outer.header: +; CHECK: outer.header: + %outer.iv = phi i32 [ 0, %entry ], [ %x, %outer.latch ] + br label %inner.header +; CHECK: %[[SCEV_EXPANDED:.*]] = add i32 +; CHECK: br label %inner.header + +inner.header: +; CHECK: inner.header: + %inner.iv = phi i32 [ undef, %outer.header ], [ %inc, %inner.latch ] + %cmp1 = icmp slt i32 %inner.iv, %outer.iv + br i1 %cmp1, label %inner.latch, label %outer.latch +; CHECK: br i1 {{.*}}, label %inner.latch, label %outer.latch + +inner.latch: +; CHECK: inner.latch: + %inc = add nsw i32 %inner.iv, 1 + %cmp2 = icmp slt i32 %inner.iv, %outer.iv + br i1 %cmp2, label %inner.header, label %exit +; CHECK: br i1 {{.*}}, label %inner.header, label %[[EXIT_FROM_INNER:.*]] + +outer.latch: +; CHECK: outer.latch: + br i1 undef, label %outer.header, label %exit +; CHECK: br i1 {{.*}}, label %outer.header, label %[[EXIT_FROM_OUTER:.*]] + +; CHECK: [[EXIT_FROM_INNER]]: +; CHECK-NEXT: %[[LCSSA:.*]] = phi i32 [ %[[SCEV_EXPANDED]], %inner.latch ] +; CHECK-NEXT: br label %exit + +; CHECK: [[EXIT_FROM_OUTER]]: +; CHECK-NEXT: br label %exit + +exit: +; CHECK: exit: + %exit.phi = phi i32 [ %inc, %inner.latch ], [ undef, %outer.latch ] +; CHECK-NEXT: phi i32 [ %[[LCSSA]], %[[EXIT_FROM_INNER]] ], [ undef, %[[EXIT_FROM_OUTER]] ] + ret void +} diff --git a/test/Transforms/IndVarSimplify/lftr-extend-const.ll b/test/Transforms/IndVarSimplify/lftr-extend-const.ll index 2fac4a797e29..4736f857bcce 100644 --- a/test/Transforms/IndVarSimplify/lftr-extend-const.ll +++ b/test/Transforms/IndVarSimplify/lftr-extend-const.ll @@ -1,6 +1,6 @@ ;RUN: opt -S %s -indvars | FileCheck %s -; CHECK-LABEL-LABEL: @foo( +; CHECK-LABEL: @foo( ; CHECK-NOT: %lftr.wideiv = trunc i32 %indvars.iv.next to i16 ; CHECK: %exitcond = icmp ne i32 %indvars.iv.next, 512 define void @foo() #0 { @@ -20,7 +20,7 @@ for.end: ; preds = %for.body } ; Check that post-incrementing the backedge taken count does not overflow. -; CHECK-LABEL-LABEL: @postinc( +; CHECK-LABEL: @postinc( ; CHECK: icmp eq i32 %indvars.iv.next, 256 define i32 @postinc() #0 { entry: diff --git a/test/Transforms/IndVarSimplify/lftr-reuse.ll b/test/Transforms/IndVarSimplify/lftr-reuse.ll index fe3df5cfa88c..1fdcdd1ec3a4 100644 --- a/test/Transforms/IndVarSimplify/lftr-reuse.ll +++ b/test/Transforms/IndVarSimplify/lftr-reuse.ll @@ -38,17 +38,16 @@ for.end: ret void } -; It would be nice if SCEV and any loop analysis could assume that -; preheaders exist. Unfortunately it is not always the case. This test -; checks that SCEVExpander can handle an outer loop that has not yet -; been simplified. As a result, the inner loop's exit test will not be -; rewritten. +; This test checks that SCEVExpander can handle an outer loop that has been +; simplified, and as a result the inner loop's exit test will be rewritten. define void @expandOuterRecurrence(i32 %arg) nounwind { entry: %sub1 = sub nsw i32 %arg, 1 %cmp1 = icmp slt i32 0, %sub1 br i1 %cmp1, label %outer, label %exit +; CHECK: outer: +; CHECK: icmp slt outer: %i = phi i32 [ 0, %entry ], [ %i.inc, %outer.inc ] %sub2 = sub nsw i32 %arg, %i @@ -60,7 +59,6 @@ inner.ph: br label %inner ; CHECK: inner: -; CHECK: icmp slt ; CHECK: br i1 inner: %j = phi i32 [ 0, %inner.ph ], [ %j.inc, %inner ] diff --git a/test/Transforms/IndVarSimplify/overflowcheck.ll b/test/Transforms/IndVarSimplify/overflowcheck.ll new file mode 100644 index 000000000000..2603f363ab60 --- /dev/null +++ b/test/Transforms/IndVarSimplify/overflowcheck.ll @@ -0,0 +1,56 @@ +; RUN: opt < %s -indvars -liv-reduce -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx" + +; CHECK-LABEL: @addwithoverflow +; CHECK-LABEL: loop1: +; CHECK-NOT: zext +; CHECK: add nsw +; CHECK: @llvm.sadd.with.overflow +; CHECK-LABEL: loop2: +; CHECK-NOT: extractvalue +; CHECK: add nuw nsw +; CHECK: @llvm.sadd.with.overflow +; CHECK-LABEL: loop3: +; CHECK-NOT: extractvalue +; CHECK: ret +define i64 @addwithoverflow(i32 %n, i64* %a) { +entry: + br label %loop0 + +loop0: + %i = phi i32 [ 0, %entry ], [ %i1val, %loop3 ] + %s = phi i32 [ 0, %entry ], [ %addsval, %loop3 ] + %bc = icmp ult i32 %i, %n + br i1 %bc, label %loop1, label %exit + +loop1: + %zxt = zext i32 %i to i64 + %ofs = shl nuw nsw i64 %zxt, 3 + %gep = getelementptr i64* %a, i64 %zxt + %v = load i64* %gep, align 8 + %truncv = trunc i64 %v to i32 + %adds = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %s, i32 %truncv) + %ovflows = extractvalue { i32, i1 } %adds, 1 + br i1 %ovflows, label %exit, label %loop2 + +loop2: + %addsval = extractvalue { i32, i1 } %adds, 0 + %i1 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %i, i32 1) + %i1check = extractvalue { i32, i1 } %i1, 1 + br i1 %i1check, label %exit, label %loop3 + +loop3: + %i1val = extractvalue { i32, i1 } %i1, 0 + %test = icmp slt i32 %i1val, %n + br i1 %test, label %return, label %loop0 + +return: + %ret = zext i32 %addsval to i64 + ret i64 %ret + +exit: + unreachable +} + +declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) diff --git a/test/Transforms/IndVarSimplify/pr18223.ll b/test/Transforms/IndVarSimplify/pr18223.ll new file mode 100644 index 000000000000..738f75c0fe03 --- /dev/null +++ b/test/Transforms/IndVarSimplify/pr18223.ll @@ -0,0 +1,30 @@ +; RUN: opt -indvars -S < %s | FileCheck %s + +; indvars should transform the phi node pair from the for-loop +; CHECK-LABEL: @main( +; CHECK: ret = phi i32 [ 0, %entry ], [ 0, {{.*}} ] + +@c = common global i32 0, align 4 + +define i32 @main() #0 { +entry: + %0 = load i32* @c, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %for.body, label %exit + +for.body: + %inc2 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %sub = add i32 %inc2, -1 + %cmp1 = icmp uge i32 %sub, %inc2 + %conv = zext i1 %cmp1 to i32 + br label %for.inc + +for.inc: + %inc = add nsw i32 %inc2, 1 + %cmp = icmp slt i32 %inc, 5 + br i1 %cmp, label %for.body, label %exit + +exit: + %ret = phi i32 [ 0, %entry ], [ %conv, %for.inc ] + ret i32 %ret +} diff --git a/test/Transforms/IndVarSimplify/tripcount_compute.ll b/test/Transforms/IndVarSimplify/tripcount_compute.ll index 626a29b20b7e..966d152cda69 100644 --- a/test/Transforms/IndVarSimplify/tripcount_compute.ll +++ b/test/Transforms/IndVarSimplify/tripcount_compute.ll @@ -160,3 +160,34 @@ loop9: ; preds = %loop2, %loopexit loopexit9: ; preds = %loop2 ret i32 %l.next } + +; PR18449. Check that the early exit is reduced to never taken. +; +; CHECK-LABEL: @twoexit +; CHECK-LABEL: loop: +; CHECK: phi +; CHECK: br i1 false +; CHECK: br +; CHECK: ret +define void @twoexit() { +"function top level": + br label %loop + +loop: ; preds = %body, %"function top level" + %0 = phi i64 [ 0, %"function top level" ], [ %2, %body ] + %1 = icmp ugt i64 %0, 2 + br i1 %1, label %fail, label %body + +fail: ; preds = %loop + tail call void @bounds_fail() + unreachable + +body: ; preds = %loop + %2 = add i64 %0, 1 + %3 = icmp slt i64 %2, 3 + br i1 %3, label %loop, label %out + +out: ; preds = %body + ret void +} +declare void @bounds_fail() diff --git a/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll b/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll deleted file mode 100644 index b37b9f2ffa28..000000000000 --- a/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: opt < %s -tailcallelim -inline -instcombine -dse -S | FileCheck %s -; PR7272 - -; When inlining through a byval call site, the inliner creates allocas which may -; be used by inlined calls, so any inlined calls need to have their 'tail' flags -; cleared. If not then you can get nastiness like with this testcase, where the -; (inlined) call to 'ext' in 'foo' was being passed an uninitialized value. - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" -target triple = "i386-pc-linux-gnu" - -declare void @ext(i32*) - -define void @bar(i32* byval %x) { - call void @ext(i32* %x) - ret void -} - -define void @foo(i32* %x) { -; CHECK-LABEL: define void @foo( -; CHECK: store i32 %1, i32* %x - call void @bar(i32* byval %x) - ret void -} diff --git a/test/Transforms/Inline/always-inline.ll b/test/Transforms/Inline/always-inline.ll index a8703b898777..5ad1bde3e2d2 100644 --- a/test/Transforms/Inline/always-inline.ll +++ b/test/Transforms/Inline/always-inline.ll @@ -122,3 +122,14 @@ entry: ret void } +define i32 @inner7() { + ret i32 1 +} +define i32 @outer7() { +; CHECK-LABEL: @outer7( +; CHECK-NOT: call +; CHECK: ret + + %r = call i32 @inner7() alwaysinline + ret i32 %r +} diff --git a/test/Transforms/Inline/blockaddress.ll b/test/Transforms/Inline/blockaddress.ll index 4206312d7743..8eb307250330 100644 --- a/test/Transforms/Inline/blockaddress.ll +++ b/test/Transforms/Inline/blockaddress.ll @@ -1,8 +1,9 @@ ; RUN: opt -inline -S < %s | FileCheck %s ; PR10162 -; Make sure the blockaddress is mapped correctly when doit is inlined -; CHECK: store i8* blockaddress(@f, %here.i), i8** @ptr1, align 8 +; Make sure doit is not inlined since the blockaddress is taken +; which could be unsafe +; CHECK: store i8* blockaddress(@doit, %here), i8** %pptr, align 8 @i = global i32 1, align 4 @ptr1 = common global i8* null, align 8 diff --git a/test/Transforms/Inline/byval-tail-call.ll b/test/Transforms/Inline/byval-tail-call.ll new file mode 100644 index 000000000000..3a8906aa210f --- /dev/null +++ b/test/Transforms/Inline/byval-tail-call.ll @@ -0,0 +1,38 @@ +; RUN: opt < %s -tailcallelim -inline -instcombine -dse -S | FileCheck %s +; PR7272 + +; Calls that capture byval parameters cannot be marked as tail calls. Other +; tails that don't capture byval parameters can still be tail calls. + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-pc-linux-gnu" + +declare void @ext(i32*) + +define void @bar(i32* byval %x) { + call void @ext(i32* %x) + ret void +} + +define void @foo(i32* %x) { +; CHECK-LABEL: define void @foo( +; CHECK: llvm.lifetime.start +; CHECK: store i32 %2, i32* %x + call void @bar(i32* byval %x) + ret void +} + +define internal void @qux(i32* byval %x) { + call void @ext(i32* %x) + tail call void @ext(i32* null) + ret void +} +define void @frob(i32* %x) { +; CHECK-LABEL: define void @frob( +; CHECK: alloca i32 +; CHECK: {{^ *}}call void @ext( +; CHECK: tail call void @ext(i32* null) +; CHECK: ret void + tail call void @qux(i32* byval %x) + ret void +} diff --git a/test/Transforms/Inline/byval_lifetime.ll b/test/Transforms/Inline/byval_lifetime.ll new file mode 100644 index 000000000000..e8dff2aa711d --- /dev/null +++ b/test/Transforms/Inline/byval_lifetime.ll @@ -0,0 +1,26 @@ +; RUN: opt -S -inline < %s | FileCheck %s +; END. + +; By inlining foo, an alloca is created in main to hold the byval argument, so +; a lifetime marker should be generated as well by default. + +%struct.foo = type { i32, [16 x i32] } + +@gFoo = global %struct.foo zeroinitializer, align 8 + +define i32 @foo(%struct.foo* byval align 8 %f, i32 %a) { +entry: + %a1 = getelementptr inbounds %struct.foo* %f, i32 0, i32 1 + %arrayidx = getelementptr inbounds [16 x i32]* %a1, i32 0, i32 %a + %tmp2 = load i32* %arrayidx, align 1 + ret i32 %tmp2 +} + +define i32 @main(i32 %argc, i8** %argv) { +; CHECK-LABEL: @main +; CHECK: llvm.lifetime.start +; CHECK: memcpy +entry: + %call = call i32 @foo(%struct.foo* byval align 8 @gFoo, i32 %argc) + ret i32 %call +} diff --git a/test/Transforms/Inline/debug-invoke.ll b/test/Transforms/Inline/debug-invoke.ll new file mode 100644 index 000000000000..41d60742fd29 --- /dev/null +++ b/test/Transforms/Inline/debug-invoke.ll @@ -0,0 +1,37 @@ +; RUN: opt < %s -always-inline -S | FileCheck %s + +; Test that the debug location is preserved when rewriting an inlined call as an invoke + +; CHECK: invoke void @test() +; CHECK-NEXT: to label {{.*}} unwind label {{.*}}, !dbg [[INL_LOC:!.*]] +; CHECK: [[EMPTY:.*]] = metadata !{} +; CHECK: [[INL_LOC]] = metadata !{i32 1, i32 0, metadata [[EMPTY]], metadata [[INL_AT:.*]]} +; CHECK: [[INL_AT]] = metadata !{i32 2, i32 0, metadata [[EMPTY]], null} + +declare void @test() +declare i32 @__gxx_personality_v0(...) + +attributes #0 = { alwaysinline } +define void @inl() #0 { + call void @test(), !dbg !3 + ret void +} + +define void @caller() { + invoke void @inl() + to label %cont unwind label %lpad, !dbg !4 + +cont: + ret void + +lpad: + landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + ret void +} + +!llvm.module.flags = !{!1} +!1 = metadata !{i32 2, metadata !"Debug Info Version", i32 1} +!2 = metadata !{} +!3 = metadata !{i32 1, i32 0, metadata !2, null} +!4 = metadata !{i32 2, i32 0, metadata !2, null} diff --git a/test/Transforms/Inline/ignore-debug-info.ll b/test/Transforms/Inline/ignore-debug-info.ll new file mode 100644 index 000000000000..543a89be0214 --- /dev/null +++ b/test/Transforms/Inline/ignore-debug-info.ll @@ -0,0 +1,55 @@ +; RUN: opt < %s -S -inline -inline-threshold=2 | FileCheck %s +; RUN: opt < %s -S -strip-debug -inline -inline-threshold=2 | FileCheck %s +; +; The purpose of this test is to check that debug info doesn't influence +; inlining decisions. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.value(metadata, i64, metadata) #1 + +define <4 x float> @inner_vectors(<4 x float> %a, <4 x float> %b) { +entry: + call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}) + %mul = fmul <4 x float> %a, <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00> + call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}) + %mul1 = fmul <4 x float> %b, <float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00> + call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}) + %add = fadd <4 x float> %mul, %mul1 + ret <4 x float> %add +} + +define float @outer_vectors(<4 x float> %a, <4 x float> %b) { +; CHECK-LABEL: @outer_vectors( +; CHECK-NOT: call <4 x float> @inner_vectors( +; CHECK: ret float + +entry: + call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}) + call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}) + %call = call <4 x float> @inner_vectors(<4 x float> %a, <4 x float> %b) + call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}) + %vecext = extractelement <4 x float> %call, i32 0 + %vecext1 = extractelement <4 x float> %call, i32 1 + %add = fadd float %vecext, %vecext1 + %vecext2 = extractelement <4 x float> %call, i32 2 + %add3 = fadd float %add, %vecext2 + %vecext4 = extractelement <4 x float> %call, i32 3 + %add5 = fadd float %add3, %vecext4 + ret float %add5 +} + +attributes #0 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4} +!llvm.ident = !{!5} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !{}, metadata !2, metadata !2, metadata !""} +!1 = metadata !{metadata !"", metadata !""} +!2 = metadata !{i32 0} +!3 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!4 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!5 = metadata !{metadata !""} diff --git a/test/Transforms/Inline/inline-cold.ll b/test/Transforms/Inline/inline-cold.ll new file mode 100644 index 000000000000..57433771961e --- /dev/null +++ b/test/Transforms/Inline/inline-cold.ll @@ -0,0 +1,200 @@ +; RUN: opt < %s -inline -S -inlinecold-threshold=75 | FileCheck %s +; Test that functions with attribute Cold are not inlined while the +; same function without attribute Cold will be inlined. + +; RUN: opt < %s -inline -S -inline-threshold=600 | FileCheck %s -check-prefix=OVERRIDE +; The command line argument for inline-threshold should override +; the default cold threshold, so a cold function with size bigger +; than the default cold threshold (225) will be inlined. + +; RUN: opt < %s -inline -S | FileCheck %s -check-prefix=DEFAULT +; The same cold function will not be inlined with the default behavior. + +@a = global i32 4 + +; This function should be larger than the cold threshold (75), but smaller +; than the regular threshold. +; Function Attrs: nounwind readnone uwtable +define i32 @simpleFunction(i32 %a) #0 { +entry: + %a1 = load volatile i32* @a + %x1 = add i32 %a1, %a1 + %a2 = load volatile i32* @a + %x2 = add i32 %x1, %a2 + %a3 = load volatile i32* @a + %x3 = add i32 %x2, %a3 + %a4 = load volatile i32* @a + %x4 = add i32 %x3, %a4 + %a5 = load volatile i32* @a + %x5 = add i32 %x4, %a5 + %a6 = load volatile i32* @a + %x6 = add i32 %x5, %a6 + %a7 = load volatile i32* @a + %x7 = add i32 %x6, %a6 + %a8 = load volatile i32* @a + %x8 = add i32 %x7, %a8 + %a9 = load volatile i32* @a + %x9 = add i32 %x8, %a9 + %a10 = load volatile i32* @a + %x10 = add i32 %x9, %a10 + %a11 = load volatile i32* @a + %x11 = add i32 %x10, %a11 + %a12 = load volatile i32* @a + %x12 = add i32 %x11, %a12 + %add = add i32 %x12, %a + ret i32 %add +} + +; Function Attrs: nounwind cold readnone uwtable +define i32 @ColdFunction(i32 %a) #1 { +; CHECK-LABEL: @ColdFunction +; CHECK: ret +; OVERRIDE-LABEL: @ColdFunction +; OVERRIDE: ret +; DEFAULT-LABEL: @ColdFunction +; DEFAULT: ret +entry: + %a1 = load volatile i32* @a + %x1 = add i32 %a1, %a1 + %a2 = load volatile i32* @a + %x2 = add i32 %x1, %a2 + %a3 = load volatile i32* @a + %x3 = add i32 %x2, %a3 + %a4 = load volatile i32* @a + %x4 = add i32 %x3, %a4 + %a5 = load volatile i32* @a + %x5 = add i32 %x4, %a5 + %a6 = load volatile i32* @a + %x6 = add i32 %x5, %a6 + %a7 = load volatile i32* @a + %x7 = add i32 %x6, %a6 + %a8 = load volatile i32* @a + %x8 = add i32 %x7, %a8 + %a9 = load volatile i32* @a + %x9 = add i32 %x8, %a9 + %a10 = load volatile i32* @a + %x10 = add i32 %x9, %a10 + %a11 = load volatile i32* @a + %x11 = add i32 %x10, %a11 + %a12 = load volatile i32* @a + %x12 = add i32 %x11, %a12 + %add = add i32 %x12, %a + ret i32 %add +} + +; This function should be larger than the default cold threshold (225). +define i32 @ColdFunction2(i32 %a) #1 { +; CHECK-LABEL: @ColdFunction2 +; CHECK: ret +; OVERRIDE-LABEL: @ColdFunction2 +; OVERRIDE: ret +; DEFAULT-LABEL: @ColdFunction2 +; DEFAULT: ret +entry: + %a1 = load volatile i32* @a + %x1 = add i32 %a1, %a1 + %a2 = load volatile i32* @a + %x2 = add i32 %x1, %a2 + %a3 = load volatile i32* @a + %x3 = add i32 %x2, %a3 + %a4 = load volatile i32* @a + %x4 = add i32 %x3, %a4 + %a5 = load volatile i32* @a + %x5 = add i32 %x4, %a5 + %a6 = load volatile i32* @a + %x6 = add i32 %x5, %a6 + %a7 = load volatile i32* @a + %x7 = add i32 %x6, %a7 + %a8 = load volatile i32* @a + %x8 = add i32 %x7, %a8 + %a9 = load volatile i32* @a + %x9 = add i32 %x8, %a9 + %a10 = load volatile i32* @a + %x10 = add i32 %x9, %a10 + %a11 = load volatile i32* @a + %x11 = add i32 %x10, %a11 + %a12 = load volatile i32* @a + %x12 = add i32 %x11, %a12 + + %a21 = load volatile i32* @a + %x21 = add i32 %x12, %a21 + %a22 = load volatile i32* @a + %x22 = add i32 %x21, %a22 + %a23 = load volatile i32* @a + %x23 = add i32 %x22, %a23 + %a24 = load volatile i32* @a + %x24 = add i32 %x23, %a24 + %a25 = load volatile i32* @a + %x25 = add i32 %x24, %a25 + %a26 = load volatile i32* @a + %x26 = add i32 %x25, %a26 + %a27 = load volatile i32* @a + %x27 = add i32 %x26, %a27 + %a28 = load volatile i32* @a + %x28 = add i32 %x27, %a28 + %a29 = load volatile i32* @a + %x29 = add i32 %x28, %a29 + %a30 = load volatile i32* @a + %x30 = add i32 %x29, %a30 + %a31 = load volatile i32* @a + %x31 = add i32 %x30, %a31 + %a32 = load volatile i32* @a + %x32 = add i32 %x31, %a32 + + %a41 = load volatile i32* @a + %x41 = add i32 %x32, %a41 + %a42 = load volatile i32* @a + %x42 = add i32 %x41, %a42 + %a43 = load volatile i32* @a + %x43 = add i32 %x42, %a43 + %a44 = load volatile i32* @a + %x44 = add i32 %x43, %a44 + %a45 = load volatile i32* @a + %x45 = add i32 %x44, %a45 + %a46 = load volatile i32* @a + %x46 = add i32 %x45, %a46 + %a47 = load volatile i32* @a + %x47 = add i32 %x46, %a47 + %a48 = load volatile i32* @a + %x48 = add i32 %x47, %a48 + %a49 = load volatile i32* @a + %x49 = add i32 %x48, %a49 + %a50 = load volatile i32* @a + %x50 = add i32 %x49, %a50 + %a51 = load volatile i32* @a + %x51 = add i32 %x50, %a51 + %a52 = load volatile i32* @a + %x52 = add i32 %x51, %a52 + + %add = add i32 %x52, %a + ret i32 %add +} + +; Function Attrs: nounwind readnone uwtable +define i32 @bar(i32 %a) #0 { +; CHECK-LABEL: @bar +; CHECK: call i32 @ColdFunction(i32 5) +; CHECK-NOT: call i32 @simpleFunction(i32 6) +; CHECK: call i32 @ColdFunction2(i32 5) +; CHECK: ret +; OVERRIDE-LABEL: @bar +; OVERRIDE-NOT: call i32 @ColdFunction(i32 5) +; OVERRIDE-NOT: call i32 @simpleFunction(i32 6) +; OVERRIDE-NOT: call i32 @ColdFunction2(i32 5) +; OVERRIDE: ret +; DEFAULT-LABEL: @bar +; DEFAULT-NOT: call i32 @ColdFunction(i32 5) +; DEFAULT-NOT: call i32 @simpleFunction(i32 6) +; DEFAULT: call i32 @ColdFunction2(i32 5) +; DEFAULT: ret +entry: + %0 = tail call i32 @ColdFunction(i32 5) + %1 = tail call i32 @simpleFunction(i32 6) + %2 = tail call i32 @ColdFunction2(i32 5) + %3 = add i32 %0, %1 + %add = add i32 %2, %3 + ret i32 %add +} + +attributes #0 = { nounwind readnone uwtable } +attributes #1 = { nounwind cold readnone uwtable } diff --git a/test/Transforms/Inline/inline-tail.ll b/test/Transforms/Inline/inline-tail.ll index 8bb059d01a0c..b40328e0a272 100644 --- a/test/Transforms/Inline/inline-tail.ll +++ b/test/Transforms/Inline/inline-tail.ll @@ -1,15 +1,182 @@ -; RUN: opt < %s -inline -S | not grep tail +; RUN: opt < %s -inline -S | FileCheck %s -declare void @bar(i32*) +; We have to apply the less restrictive TailCallKind of the call site being +; inlined and any call sites cloned into the caller. -define internal void @foo(i32* %P) { - tail call void @bar( i32* %P ) - ret void +; No tail marker after inlining, since test_capture_c captures an alloca. +; CHECK: define void @test_capture_a( +; CHECK-NOT: tail +; CHECK: call void @test_capture_c( + +declare void @test_capture_c(i32*) +define internal void @test_capture_b(i32* %P) { + tail call void @test_capture_c(i32* %P) + ret void +} +define void @test_capture_a() { + %A = alloca i32 ; captured by test_capture_b + call void @test_capture_b(i32* %A) + ret void +} + +; No musttail marker after inlining, since the prototypes don't match. +; CHECK: define void @test_proto_mismatch_a( +; CHECK-NOT: musttail +; CHECK: call void @test_proto_mismatch_c( + +declare void @test_proto_mismatch_c(i32*) +define internal void @test_proto_mismatch_b(i32* %p) { + musttail call void @test_proto_mismatch_c(i32* %p) + ret void +} +define void @test_proto_mismatch_a() { + call void @test_proto_mismatch_b(i32* null) + ret void +} + +; After inlining through a musttail call site, we need to keep musttail markers +; to prevent unbounded stack growth. +; CHECK: define void @test_musttail_basic_a( +; CHECK: musttail call void @test_musttail_basic_c( + +declare void @test_musttail_basic_c(i32* %p) +define internal void @test_musttail_basic_b(i32* %p) { + musttail call void @test_musttail_basic_c(i32* %p) + ret void +} +define void @test_musttail_basic_a(i32* %p) { + musttail call void @test_musttail_basic_b(i32* %p) + ret void +} + +; Don't insert lifetime end markers here, the lifetime is trivially over due +; the return. +; CHECK: define void @test_byval_a( +; CHECK: musttail call void @test_byval_c( +; CHECK-NEXT: ret void + +declare void @test_byval_c(i32* byval %p) +define internal void @test_byval_b(i32* byval %p) { + musttail call void @test_byval_c(i32* byval %p) + ret void +} +define void @test_byval_a(i32* byval %p) { + musttail call void @test_byval_b(i32* byval %p) + ret void } -define void @caller() { - %A = alloca i32 ; <i32*> [#uses=1] - call void @foo( i32* %A ) - ret void +; Don't insert a stack restore, we're about to return. +; CHECK: define void @test_dynalloca_a( +; CHECK: call i8* @llvm.stacksave( +; CHECK: alloca i8, i32 %n +; CHECK: musttail call void @test_dynalloca_c( +; CHECK-NEXT: ret void + +declare void @escape(i8* %buf) +declare void @test_dynalloca_c(i32* byval %p, i32 %n) +define internal void @test_dynalloca_b(i32* byval %p, i32 %n) alwaysinline { + %buf = alloca i8, i32 %n ; dynamic alloca + call void @escape(i8* %buf) ; escape it + musttail call void @test_dynalloca_c(i32* byval %p, i32 %n) + ret void +} +define void @test_dynalloca_a(i32* byval %p, i32 %n) { + musttail call void @test_dynalloca_b(i32* byval %p, i32 %n) + ret void } +; We can't merge the returns. +; CHECK: define void @test_multiret_a( +; CHECK: musttail call void @test_multiret_c( +; CHECK-NEXT: ret void +; CHECK: musttail call void @test_multiret_d( +; CHECK-NEXT: ret void + +declare void @test_multiret_c(i1 zeroext %b) +declare void @test_multiret_d(i1 zeroext %b) +define internal void @test_multiret_b(i1 zeroext %b) { + br i1 %b, label %c, label %d +c: + musttail call void @test_multiret_c(i1 zeroext %b) + ret void +d: + musttail call void @test_multiret_d(i1 zeroext %b) + ret void +} +define void @test_multiret_a(i1 zeroext %b) { + musttail call void @test_multiret_b(i1 zeroext %b) + ret void +} + +; We have to avoid bitcast chains. +; CHECK: define i32* @test_retptr_a( +; CHECK: musttail call i8* @test_retptr_c( +; CHECK-NEXT: bitcast i8* {{.*}} to i32* +; CHECK-NEXT: ret i32* + +declare i8* @test_retptr_c() +define internal i16* @test_retptr_b() { + %rv = musttail call i8* @test_retptr_c() + %v = bitcast i8* %rv to i16* + ret i16* %v +} +define i32* @test_retptr_a() { + %rv = musttail call i16* @test_retptr_b() + %v = bitcast i16* %rv to i32* + ret i32* %v +} + +; Combine the last two cases: multiple returns with pointer bitcasts. +; CHECK: define i32* @test_multiptrret_a( +; CHECK: musttail call i8* @test_multiptrret_c( +; CHECK-NEXT: bitcast i8* {{.*}} to i32* +; CHECK-NEXT: ret i32* +; CHECK: musttail call i8* @test_multiptrret_d( +; CHECK-NEXT: bitcast i8* {{.*}} to i32* +; CHECK-NEXT: ret i32* + +declare i8* @test_multiptrret_c(i1 zeroext %b) +declare i8* @test_multiptrret_d(i1 zeroext %b) +define internal i16* @test_multiptrret_b(i1 zeroext %b) { + br i1 %b, label %c, label %d +c: + %c_rv = musttail call i8* @test_multiptrret_c(i1 zeroext %b) + %c_v = bitcast i8* %c_rv to i16* + ret i16* %c_v +d: + %d_rv = musttail call i8* @test_multiptrret_d(i1 zeroext %b) + %d_v = bitcast i8* %d_rv to i16* + ret i16* %d_v +} +define i32* @test_multiptrret_a(i1 zeroext %b) { + %rv = musttail call i16* @test_multiptrret_b(i1 zeroext %b) + %v = bitcast i16* %rv to i32* + ret i32* %v +} + +; Inline a musttail call site which contains a normal return and a musttail call. +; CHECK: define i32 @test_mixedret_a( +; CHECK: br i1 %b +; CHECK: musttail call i32 @test_mixedret_c( +; CHECK-NEXT: ret i32 +; CHECK: call i32 @test_mixedret_d(i1 zeroext %b) +; CHECK: add i32 1, +; CHECK-NOT: br +; CHECK: ret i32 + +declare i32 @test_mixedret_c(i1 zeroext %b) +declare i32 @test_mixedret_d(i1 zeroext %b) +define internal i32 @test_mixedret_b(i1 zeroext %b) { + br i1 %b, label %c, label %d +c: + %c_rv = musttail call i32 @test_mixedret_c(i1 zeroext %b) + ret i32 %c_rv +d: + %d_rv = call i32 @test_mixedret_d(i1 zeroext %b) + %d_rv1 = add i32 1, %d_rv + ret i32 %d_rv1 +} +define i32 @test_mixedret_a(i1 zeroext %b) { + %rv = musttail call i32 @test_mixedret_b(i1 zeroext %b) + ret i32 %rv +} diff --git a/test/Transforms/Inline/inline-vla.ll b/test/Transforms/Inline/inline-vla.ll new file mode 100644 index 000000000000..dc9deaafe743 --- /dev/null +++ b/test/Transforms/Inline/inline-vla.ll @@ -0,0 +1,38 @@ +; RUN: opt -S -inline %s -o - | FileCheck %s + +; Check that memcpy2 is completely inlined away. +; CHECK-NOT: memcpy2 + +@.str = private unnamed_addr constant [2 x i8] c"a\00", align 1 +@.str1 = private unnamed_addr constant [3 x i8] c"ab\00", align 1 + +; Function Attrs: nounwind ssp uwtable +define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 { +entry: + %data = alloca [2 x i8], align 1 + %arraydecay = getelementptr inbounds [2 x i8]* %data, i64 0, i64 0 + call fastcc void @memcpy2(i8* %arraydecay, i8* getelementptr inbounds ([2 x i8]* @.str, i64 0, i64 0), i64 1) + call fastcc void @memcpy2(i8* %arraydecay, i8* getelementptr inbounds ([3 x i8]* @.str1, i64 0, i64 0), i64 2) + ret i32 0 +} + +; Function Attrs: inlinehint nounwind ssp uwtable +define internal fastcc void @memcpy2(i8* nocapture %dst, i8* nocapture readonly %src, i64 %size) #1 { +entry: + %vla = alloca i64, i64 %size, align 16 + %0 = bitcast i64* %vla to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %src, i64 %size, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %0, i64 %size, i32 1, i1 false) + ret void +} + +; Function Attrs: nounwind +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2 + +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { inlinehint nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind } + +!llvm.ident = !{!0} + +!0 = metadata !{metadata !"clang version 3.5.0 (trunk 205695) (llvm/trunk 205706)"} diff --git a/test/Transforms/Inline/inline_invoke.ll b/test/Transforms/Inline/inline_invoke.ll index c3941388f937..c53bb5aa17be 100644 --- a/test/Transforms/Inline/inline_invoke.ll +++ b/test/Transforms/Inline/inline_invoke.ll @@ -96,7 +96,6 @@ eh.resume: ; CHECK: landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 ; CHECK-NEXT: cleanup ; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) -; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) ; CHECK-NEXT: invoke void @_ZN1AD1Ev(%struct.A* [[A]]) ; CHECK-NEXT: to label %[[LBL:[^\s]+]] unwind ; CHECK: [[LBL]]: @@ -167,7 +166,6 @@ eh.resume: ; CHECK-NEXT: [[LPADVAL1:%.*]] = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 ; CHECK-NEXT: cleanup ; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) -; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) ; CHECK-NEXT: invoke void @_ZN1AD1Ev(%struct.A* [[A1]]) ; CHECK-NEXT: to label %[[RESUME1:[^\s]+]] unwind ; CHECK: [[RESUME1]]: @@ -187,7 +185,6 @@ eh.resume: ; CHECK-NEXT: [[LPADVAL2:%.*]] = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 ; CHECK-NEXT: cleanup ; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) -; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) ; CHECK-NEXT: invoke void @_ZN1AD1Ev(%struct.A* [[A2]]) ; CHECK-NEXT: to label %[[RESUME2:[^\s]+]] unwind ; CHECK: [[RESUME2]]: @@ -275,7 +272,6 @@ lpad.cont: ; CHECK: landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 ; CHECK-NEXT: cleanup ; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) -; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) ; CHECK-NEXT: invoke void @_ZN1AD1Ev( ; CHECK-NEXT: to label %[[L:[^\s]+]] unwind ; CHECK: [[L]]: @@ -322,7 +318,6 @@ terminate: ; CHECK: landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0 ; CHECK-NEXT: cleanup ; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) -; CHECK-NEXT: catch i8* bitcast (i8** @_ZTIi to i8*) ; CHECK-NEXT: invoke void @_ZN1AD1Ev( ; CHECK-NEXT: to label %[[L:[^\s]+]] unwind ; CHECK: [[L]]: diff --git a/test/Transforms/Inline/inline_returns_twice.ll b/test/Transforms/Inline/inline_returns_twice.ll index 678ee82f4b84..36042640cc00 100644 --- a/test/Transforms/Inline/inline_returns_twice.ll +++ b/test/Transforms/Inline/inline_returns_twice.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -inline -S | FileCheck %s ; Check that functions with "returns_twice" calls are only inlined, -; if they are themselve marked as such. +; if they are themselves marked as such. declare i32 @a() returns_twice diff --git a/test/Transforms/Inline/invoke-cleanup.ll b/test/Transforms/Inline/invoke-cleanup.ll new file mode 100644 index 000000000000..457ae2addeb3 --- /dev/null +++ b/test/Transforms/Inline/invoke-cleanup.ll @@ -0,0 +1,39 @@ +; RUN: opt %s -inline -S | FileCheck %s + +declare void @external_func() + +@exception_type1 = external global i8 +@exception_type2 = external global i8 + + +define internal void @inner() { + invoke void @external_func() + to label %cont unwind label %lpad +cont: + ret void +lpad: + %lp = landingpad i32 personality i8* null + catch i8* @exception_type1 + resume i32 %lp +} + +; Test that the "cleanup" clause is kept when inlining @inner() into +; this call site (PR17872), otherwise C++ destructors will not be +; called when they should be. + +define void @outer() { + invoke void @inner() + to label %cont unwind label %lpad +cont: + ret void +lpad: + %lp = landingpad i32 personality i8* null + cleanup + catch i8* @exception_type2 + resume i32 %lp +} +; CHECK: define void @outer +; CHECK: landingpad +; CHECK-NEXT: cleanup +; CHECK-NEXT: catch i8* @exception_type1 +; CHECK-NEXT: catch i8* @exception_type2 diff --git a/test/Transforms/Inline/invoke-combine-clauses.ll b/test/Transforms/Inline/invoke-combine-clauses.ll new file mode 100644 index 000000000000..5f06039b9edc --- /dev/null +++ b/test/Transforms/Inline/invoke-combine-clauses.ll @@ -0,0 +1,117 @@ +; RUN: opt %s -inline -S | FileCheck %s + +declare void @external_func() +declare void @abort() + +@exception_inner = external global i8 +@exception_outer = external global i8 +@condition = external global i1 + + +; Check for a bug in which multiple "resume" instructions in the +; inlined function caused "catch i8* @exception_outer" to appear +; multiple times in the resulting landingpad. + +define internal void @inner_multiple_resume() { + invoke void @external_func() + to label %cont unwind label %lpad +cont: + ret void +lpad: + %lp = landingpad i32 personality i8* null + catch i8* @exception_inner + %cond = load i1* @condition + br i1 %cond, label %resume1, label %resume2 +resume1: + resume i32 1 +resume2: + resume i32 2 +} + +define void @outer_multiple_resume() { + invoke void @inner_multiple_resume() + to label %cont unwind label %lpad +cont: + ret void +lpad: + %lp = landingpad i32 personality i8* null + catch i8* @exception_outer + resume i32 %lp +} +; CHECK: define void @outer_multiple_resume() +; CHECK: %lp.i = landingpad +; CHECK-NEXT: catch i8* @exception_inner +; CHECK-NEXT: catch i8* @exception_outer +; Check that there isn't another "catch" clause: +; CHECK-NEXT: load + + +; Check for a bug in which having a "resume" and a "call" in the +; inlined function caused "catch i8* @exception_outer" to appear +; multiple times in the resulting landingpad. + +define internal void @inner_resume_and_call() { + call void @external_func() + invoke void @external_func() + to label %cont unwind label %lpad +cont: + ret void +lpad: + %lp = landingpad i32 personality i8* null + catch i8* @exception_inner + resume i32 %lp +} + +define void @outer_resume_and_call() { + invoke void @inner_resume_and_call() + to label %cont unwind label %lpad +cont: + ret void +lpad: + %lp = landingpad i32 personality i8* null + catch i8* @exception_outer + resume i32 %lp +} +; CHECK: define void @outer_resume_and_call() +; CHECK: %lp.i = landingpad +; CHECK-NEXT: catch i8* @exception_inner +; CHECK-NEXT: catch i8* @exception_outer +; Check that there isn't another "catch" clause: +; CHECK-NEXT: br + + +; Check what happens if the inlined function contains an "invoke" but +; no "resume". In this case, the inlined landingpad does not need to +; include the "catch i8* @exception_outer" clause from the outer +; function (since the outer function's landingpad will not be +; reachable), but it's OK to include this clause. + +define internal void @inner_no_resume_or_call() { + invoke void @external_func() + to label %cont unwind label %lpad +cont: + ret void +lpad: + %lp = landingpad i32 personality i8* null + catch i8* @exception_inner + ; A landingpad might have no "resume" if a C++ destructor aborts. + call void @abort() noreturn nounwind + unreachable +} + +define void @outer_no_resume_or_call() { + invoke void @inner_no_resume_or_call() + to label %cont unwind label %lpad +cont: + ret void +lpad: + %lp = landingpad i32 personality i8* null + catch i8* @exception_outer + resume i32 %lp +} +; CHECK: define void @outer_no_resume_or_call() +; CHECK: %lp.i = landingpad +; CHECK-NEXT: catch i8* @exception_inner +; CHECK-NEXT: catch i8* @exception_outer +; Check that there isn't another "catch" clause: +; CHECK-NEXT: call void @abort() diff --git a/test/Transforms/Inline/null-function.ll b/test/Transforms/Inline/null-function.ll new file mode 100644 index 000000000000..2aecfa85cd8f --- /dev/null +++ b/test/Transforms/Inline/null-function.ll @@ -0,0 +1,9 @@ +; RUN: opt -print-before=always-inline -always-inline < %s -o /dev/null 2>&1 | FileCheck %s + +define i32 @main() #0 { +entry: + ret i32 0 +} + +; CHECK: *** IR Dump Before Inliner for always_inline functions *** +; CHECK: Printing <null> Function diff --git a/test/Transforms/Inline/optimization-remarks.ll b/test/Transforms/Inline/optimization-remarks.ll new file mode 100644 index 000000000000..9108f3ab14d6 --- /dev/null +++ b/test/Transforms/Inline/optimization-remarks.ll @@ -0,0 +1,60 @@ +; RUN: opt < %s -inline -pass-remarks=inline -pass-remarks-missed=inline -pass-remarks-analysis=inline -S 2>&1 | FileCheck %s + +; CHECK: foo should always be inlined (cost=always) +; CHECK: foo inlined into bar +; CHECK: foz should never be inlined (cost=never) +; CHECK: foz will not be inlined into bar + +; Function Attrs: alwaysinline nounwind uwtable +define i32 @foo(i32 %x, i32 %y) #0 { +entry: + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + store i32 %y, i32* %y.addr, align 4 + %0 = load i32* %x.addr, align 4 + %1 = load i32* %y.addr, align 4 + %add = add nsw i32 %0, %1 + ret i32 %add +} + +; Function Attrs: noinline nounwind uwtable +define float @foz(i32 %x, i32 %y) #1 { +entry: + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + store i32 %y, i32* %y.addr, align 4 + %0 = load i32* %x.addr, align 4 + %1 = load i32* %y.addr, align 4 + %mul = mul nsw i32 %0, %1 + %conv = sitofp i32 %mul to float + ret float %conv +} + +; Function Attrs: nounwind uwtable +define i32 @bar(i32 %j) #2 { +entry: + %j.addr = alloca i32, align 4 + store i32 %j, i32* %j.addr, align 4 + %0 = load i32* %j.addr, align 4 + %1 = load i32* %j.addr, align 4 + %sub = sub nsw i32 %1, 2 + %call = call i32 @foo(i32 %0, i32 %sub) + %conv = sitofp i32 %call to float + %2 = load i32* %j.addr, align 4 + %sub1 = sub nsw i32 %2, 2 + %3 = load i32* %j.addr, align 4 + %call2 = call float @foz(i32 %sub1, i32 %3) + %mul = fmul float %conv, %call2 + %conv3 = fptosi float %mul to i32 + ret i32 %conv3 +} + +attributes #0 = { alwaysinline nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { noinline nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.ident = !{!0} + +!0 = metadata !{metadata !"clang version 3.5.0 "} diff --git a/test/Transforms/Inline/ptr-diff.ll b/test/Transforms/Inline/ptr-diff.ll index af42bc7cedeb..46c3bcd4dc53 100644 --- a/test/Transforms/Inline/ptr-diff.ll +++ b/test/Transforms/Inline/ptr-diff.ll @@ -31,7 +31,7 @@ else: define i32 @outer2(i32* %ptr) { ; Test that an inbounds GEP disables this -- it isn't safe in general as -; wrapping changes the behavior of lessthan and greaterthan comparisions. +; wrapping changes the behavior of lessthan and greaterthan comparisons. ; CHECK-LABEL: @outer2( ; CHECK: call i32 @inner2 ; CHECK: ret i32 diff --git a/test/Transforms/Inline/switch.ll b/test/Transforms/Inline/switch.ll new file mode 100644 index 000000000000..c5dab53e8b64 --- /dev/null +++ b/test/Transforms/Inline/switch.ll @@ -0,0 +1,60 @@ +; RUN: opt < %s -inline -inline-threshold=20 -S | FileCheck %s + +define i32 @callee(i32 %a) { + switch i32 %a, label %sw.default [ + i32 0, label %sw.bb0 + i32 1, label %sw.bb1 + i32 2, label %sw.bb2 + i32 3, label %sw.bb3 + i32 4, label %sw.bb4 + i32 5, label %sw.bb5 + i32 6, label %sw.bb6 + i32 7, label %sw.bb7 + i32 8, label %sw.bb8 + i32 9, label %sw.bb9 + ] + +sw.default: + br label %return + +sw.bb0: + br label %return + +sw.bb1: + br label %return + +sw.bb2: + br label %return + +sw.bb3: + br label %return + +sw.bb4: + br label %return + +sw.bb5: + br label %return + +sw.bb6: + br label %return + +sw.bb7: + br label %return + +sw.bb8: + br label %return + +sw.bb9: + br label %return + +return: + ret i32 42 +} + +define i32 @caller(i32 %a) { +; CHECK-LABEL: @caller( +; CHECK: call i32 @callee( + + %result = call i32 @callee(i32 %a) + ret i32 %result +} diff --git a/test/Transforms/InstCombine/2007-09-10-AliasConstFold.ll b/test/Transforms/InstCombine/2007-09-10-AliasConstFold.ll index c27fe0ab6a6d..7f9bd9e40dcb 100644 --- a/test/Transforms/InstCombine/2007-09-10-AliasConstFold.ll +++ b/test/Transforms/InstCombine/2007-09-10-AliasConstFold.ll @@ -3,7 +3,9 @@ @__gthrw_pthread_cancel = alias weak i32 (i32)* @pthread_cancel ; <i32 (i32)*> [#uses=1] @__gthread_active_ptr.5335 = internal constant i8* bitcast (i32 (i32)* @__gthrw_pthread_cancel to i8*) ; <i8**> [#uses=1] -declare extern_weak i32 @pthread_cancel(i32) +define weak i32 @pthread_cancel(i32) { + ret i32 0 +} define i1 @__gthread_active_p() { entry: diff --git a/test/Transforms/InstCombine/2007-09-17-AliasConstFold2.ll b/test/Transforms/InstCombine/2007-09-17-AliasConstFold2.ll index 23ee12ba754f..c7cef752dcc9 100644 --- a/test/Transforms/InstCombine/2007-09-17-AliasConstFold2.ll +++ b/test/Transforms/InstCombine/2007-09-17-AliasConstFold2.ll @@ -3,7 +3,9 @@ @A = alias weak void ()* @B ; <void ()*> [#uses=1] -declare extern_weak void @B() +define weak void @B() { + ret void +} define i32 @active() { entry: diff --git a/test/Transforms/InstCombine/2010-03-03-ExtElim.ll b/test/Transforms/InstCombine/2010-03-03-ExtElim.ll index b1384ec00209..e0def997d974 100644 --- a/test/Transforms/InstCombine/2010-03-03-ExtElim.ll +++ b/test/Transforms/InstCombine/2010-03-03-ExtElim.ll @@ -22,11 +22,11 @@ define i1 @PR6486() nounwind { define i1 @PR16462_1() nounwind { ; CHECK-LABEL: @PR16462_1( ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 65535) -; CHECK: ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 65535) +; CHECK: ret i1 false } define i1 @PR16462_2() nounwind { ; CHECK-LABEL: @PR16462_2( ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 42) -; CHECK: ret i1 icmp sgt (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16), i16 42) +; CHECK: ret i1 false } diff --git a/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll b/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll index 2dedd44e2be1..39408a2d394c 100644 --- a/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll +++ b/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll @@ -1,6 +1,3 @@ -target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" -target triple = "thumbv7-apple-ios0" - ; RUN: opt -S -instcombine < %s | FileCheck %s define <4 x i32> @mulByZero(<4 x i16> %x) nounwind readnone ssp { @@ -67,6 +64,72 @@ entry: declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +; ARM64 variants - <rdar://problem/12349617> + +define <4 x i32> @mulByZeroARM64(<4 x i16> %x) nounwind readnone ssp { +entry: + %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind + ret <4 x i32> %a +; CHECK: entry: +; CHECK-NEXT: ret <4 x i32> zeroinitializer +} + +define <4 x i32> @mulByOneARM64(<4 x i16> %x) nounwind readnone ssp { +entry: + %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind + ret <4 x i32> %a +; CHECK: entry: +; CHECK-NEXT: %a = sext <4 x i16> %x to <4 x i32> +; CHECK-NEXT: ret <4 x i32> %a +} + +define <4 x i32> @constantMulARM64() nounwind readnone ssp { +entry: + %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind + ret <4 x i32> %a +; CHECK: entry: +; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6> +} + +define <4 x i32> @constantMulSARM64() nounwind readnone ssp { +entry: + %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind + ret <4 x i32> %b +; CHECK: entry: +; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> +} + +define <4 x i32> @constantMulUARM64() nounwind readnone ssp { +entry: + %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind + ret <4 x i32> %b +; CHECK: entry: +; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> +} + +define <4 x i32> @complex1ARM64(<4 x i16> %x) nounwind readnone ssp { +entry: + %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind + %b = add <4 x i32> zeroinitializer, %a + ret <4 x i32> %b +; CHECK: entry: +; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]] +; CHECK-NEXT: ret <4 x i32> %a +} + +define <4 x i32> @complex2ARM64(<4 x i32> %x) nounwind readnone ssp { +entry: + %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind + %b = add <4 x i32> %x, %a + ret <4 x i32> %b +; CHECK: entry: +; CHECK-NEXT: %b = add <4 x i32> %x, <i32 6, i32 6, i32 6, i32 6> +; CHECK-NEXT: ret <4 x i32> %b +} + +declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone + ; CHECK: attributes #0 = { nounwind readnone ssp } ; CHECK: attributes #1 = { nounwind readnone } ; CHECK: attributes [[NUW]] = { nounwind } diff --git a/test/Transforms/InstCombine/2012-07-30-addrsp-bitcast.ll b/test/Transforms/InstCombine/2012-07-30-addrsp-bitcast.ll index 4d185bf7e06e..ac9c555020d0 100644 --- a/test/Transforms/InstCombine/2012-07-30-addrsp-bitcast.ll +++ b/test/Transforms/InstCombine/2012-07-30-addrsp-bitcast.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -instcombine -S | FileCheck %s ; CHECK: addrspacecast -@base = internal addrspace(3) unnamed_addr global [16 x i32] zeroinitializer, align 16 +@base = internal unnamed_addr addrspace(3) global [16 x i32] zeroinitializer, align 16 declare void @foo(i32*) define void @test() nounwind { diff --git a/test/Transforms/InstCombine/AddOverFlow.ll b/test/Transforms/InstCombine/AddOverFlow.ll new file mode 100644 index 000000000000..8f3d429c8d60 --- /dev/null +++ b/test/Transforms/InstCombine/AddOverFlow.ll @@ -0,0 +1,118 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + +; CHECK-LABEL: @oppositesign +; CHECK: add nsw i16 %a, %b +define i16 @oppositesign(i16 %x, i16 %y) { +; %a is negative, %b is positive + %a = or i16 %x, 32768 + %b = and i16 %y, 32767 + %c = add i16 %a, %b + ret i16 %c +} + +define i16 @zero_sign_bit(i16 %a) { +; CHECK-LABEL: @zero_sign_bit( +; CHECK-NEXT: and +; CHECK-NEXT: add nuw +; CHECK-NEXT: ret + %1 = and i16 %a, 32767 + %2 = add i16 %1, 512 + ret i16 %2 +} + +define i16 @zero_sign_bit2(i16 %a, i16 %b) { +; CHECK-LABEL: @zero_sign_bit2( +; CHECK-NEXT: and +; CHECK-NEXT: and +; CHECK-NEXT: add nuw +; CHECK-NEXT: ret + %1 = and i16 %a, 32767 + %2 = and i16 %b, 32767 + %3 = add i16 %1, %2 + ret i16 %3 +} + +declare i16 @bounded(i16 %input); +declare i32 @__gxx_personality_v0(...); +!0 = metadata !{i16 0, i16 32768} ; [0, 32767] +!1 = metadata !{i16 0, i16 32769} ; [0, 32768] + +define i16 @add_bounded_values(i16 %a, i16 %b) { +; CHECK-LABEL: @add_bounded_values( +entry: + %c = call i16 @bounded(i16 %a), !range !0 + %d = invoke i16 @bounded(i16 %b) to label %cont unwind label %lpad, !range !0 +cont: +; %c and %d are in [0, 32767]. Therefore, %c + %d doesn't unsigned overflow. + %e = add i16 %c, %d +; CHECK: add nuw i16 %c, %d + ret i16 %e +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + filter [0 x i8*] zeroinitializer + ret i16 42 +} + +define i16 @add_bounded_values_2(i16 %a, i16 %b) { +; CHECK-LABEL: @add_bounded_values_2( +entry: + %c = call i16 @bounded(i16 %a), !range !1 + %d = invoke i16 @bounded(i16 %b) to label %cont unwind label %lpad, !range !1 +cont: +; Similar to add_bounded_values, but %c and %d are in [0, 32768]. Therefore, +; %c + %d may unsigned overflow and we cannot add NUW. + %e = add i16 %c, %d +; CHECK: add i16 %c, %d + ret i16 %e +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + filter [0 x i8*] zeroinitializer + ret i16 42 +} + +; CHECK-LABEL: @ripple_nsw1 +; CHECK: add nsw i16 %a, %b +define i16 @ripple_nsw1(i16 %x, i16 %y) { +; %a has at most one bit set + %a = and i16 %y, 1 + +; %b has a 0 bit other than the sign bit + %b = and i16 %x, 49151 + + %c = add i16 %a, %b + ret i16 %c +} + +; Like the previous test, but flip %a and %b +; CHECK-LABEL: @ripple_nsw2 +; CHECK: add nsw i16 %b, %a +define i16 @ripple_nsw2(i16 %x, i16 %y) { + %a = and i16 %y, 1 + %b = and i16 %x, 49151 + %c = add i16 %b, %a + ret i16 %c +} + +; CHECK-LABEL: @ripple_no_nsw1 +; CHECK: add i32 %a, %x +define i32 @ripple_no_nsw1(i32 %x, i32 %y) { +; We know nothing about %x + %a = and i32 %y, 1 + %b = add i32 %a, %x + ret i32 %b +} + +; CHECK-LABEL: @ripple_no_nsw2 +; CHECK: add nuw i16 %a, %b +define i16 @ripple_no_nsw2(i16 %x, i16 %y) { +; %a has at most one bit set + %a = and i16 %y, 1 + +; %b has a 0 bit, but it is the sign bit + %b = and i16 %x, 32767 + + %c = add i16 %a, %b + ret i16 %c +} diff --git a/test/Transforms/InstCombine/OverlappingInsertvalues.ll b/test/Transforms/InstCombine/OverlappingInsertvalues.ll new file mode 100644 index 000000000000..9248aecdf575 --- /dev/null +++ b/test/Transforms/InstCombine/OverlappingInsertvalues.ll @@ -0,0 +1,36 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + +; Check that we can find and remove redundant insertvalues +; CHECK-LABEL: foo_simple +; CHECK-NOT: i8* %x, 0 +define { i8*, i64, i32 } @foo_simple(i8* %x, i8* %y) nounwind { +entry: + %0 = insertvalue { i8*, i64, i32 } undef, i8* %x, 0 + %1 = insertvalue { i8*, i64, i32 } %0, i8* %y, 0 + ret { i8*, i64, i32 } %1 +} +; Check that we can find and remove redundant nodes in insertvalues chain +; CHECK-LABEL: foo_ovwrt_chain +; CHECK-NOT: i64 %y, 1 +; CHECK-NOT: i32 555, 2 +define { i8*, i64, i32 } @foo_ovwrt_chain(i8* %x, i64 %y, i64 %z) nounwind { +entry: + %0 = insertvalue { i8*, i64, i32 } undef, i8* %x, 0 + %1 = insertvalue { i8*, i64, i32 } %0, i64 %y, 1 + %2 = insertvalue { i8*, i64, i32 } %1, i32 555, 2 + %3 = insertvalue { i8*, i64, i32 } %2, i64 %z, 1 + %4 = insertvalue { i8*, i64, i32 } %3, i32 777, 2 + ret { i8*, i64, i32 } %4 +} +; Check that we propagate insertvalues only if they are use as the first +; operand (as initial value of aggregate) +; CHECK-LABEL: foo_use_as_second_operand +; CHECK: i16 %x, 0 +; CHECK: %0, 1 +define { i8, {i16, i32} } @foo_use_as_second_operand(i16 %x) nounwind { +entry: + %0 = insertvalue { i16, i32 } undef, i16 %x, 0 + %1 = insertvalue { i8, {i16, i32} } undef, { i16, i32 } %0, 1 + ret { i8, {i16, i32} } %1 +} diff --git a/test/Transforms/InstCombine/abs_abs.ll b/test/Transforms/InstCombine/abs_abs.ll new file mode 100644 index 000000000000..de10fd180a79 --- /dev/null +++ b/test/Transforms/InstCombine/abs_abs.ll @@ -0,0 +1,961 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define i32 @abs_abs_x01(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, -1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x01( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x02(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, -1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x02( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x03(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, -1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x03( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x04(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, -1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x04( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x05(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x05( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x06(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x06( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x07(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x07( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x08(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x08( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x09(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x09( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x10(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x10( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x11(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x11( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x12(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x12( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x13(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x13( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x14(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x14( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x15(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x15( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_abs_x16(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_abs_x16( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x01(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, -1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x01( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x02(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, -1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x02( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x03(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, -1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x03( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x04(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, -1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x04( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x05(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x05( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x06(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x06( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x07(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x07( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x08(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x08( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x09(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x09( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x10(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x10( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x11(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x11( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x12(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x12( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x13(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x13( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x14(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x14( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x15(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x15( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_nabs_x16(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_nabs_x16( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x01(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, -1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x01( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x02(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, -1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x02( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x03(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, -1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x03( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x04(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, -1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x04( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x05(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x05( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x06(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x06( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x07(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x07( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x08(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x08( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x09(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x09( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x10(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x10( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x11(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x11( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x12(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x12( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x13(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x13( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x14(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x14( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x15(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x15( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @abs_nabs_x16(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @abs_nabs_x16( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x01(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, -1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x01( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x02(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, -1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x02( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x03(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, -1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x03( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x04(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, -1 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x04( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x05(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x05( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x06(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp sgt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x06( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x07(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x07( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x08(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp sgt i32 %cond, 0 + %sub9 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x08( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x09(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x09( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x10(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x10( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x11(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x11( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x12(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 0 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x12( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x13(i32 %x) { + %cmp = icmp sgt i32 %x, -1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x13( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x14(i32 %x) { + %cmp = icmp sgt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %x, i32 %sub + %cmp1 = icmp slt i32 %cond, 1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x14( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x15(i32 %x) { + %cmp = icmp slt i32 %x, 0 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x15( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +} + +define i32 @nabs_abs_x16(i32 %x) { + %cmp = icmp slt i32 %x, 1 + %sub = sub nsw i32 0, %x + %cond = select i1 %cmp, i32 %sub, i32 %x + %cmp1 = icmp slt i32 %cond, 1 + %sub16 = sub nsw i32 0, %cond + %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 + ret i32 %cond18 +; CHECK-LABEL: @nabs_abs_x16( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1 +; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]] +; CHECK-NEXT: ret i32 [[SEL]] +}
\ No newline at end of file diff --git a/test/Transforms/InstCombine/add-shrink.ll b/test/Transforms/InstCombine/add-shrink.ll index 3edb392ed184..67a990fcb105 100644 --- a/test/Transforms/InstCombine/add-shrink.ll +++ b/test/Transforms/InstCombine/add-shrink.ll @@ -1,9 +1,11 @@ -; RUN: opt < %s -instcombine -S | grep "add nsw i32" -; RUN: opt < %s -instcombine -S | grep sext | count 1 - -; Should only have one sext and the add should be i32 instead of i64. +; RUN: opt < %s -instcombine -S | FileCheck %s +; CHECK-LABEL: define i64 @test define i64 @test1(i32 %A) { +; CHECK: %[[ADD:.*]] = add nsw i32 %B, %C +; CHECK: %F = sext i32 %[[ADD]] to i64 +; CHECK: ret i64 %F + %B = ashr i32 %A, 7 ; <i32> [#uses=1] %C = ashr i32 %A, 9 ; <i32> [#uses=1] %D = sext i32 %B to i64 ; <i64> [#uses=1] diff --git a/test/Transforms/InstCombine/add-sitofp.ll b/test/Transforms/InstCombine/add-sitofp.ll index 40edf7114a06..3b5485e00528 100644 --- a/test/Transforms/InstCombine/add-sitofp.ll +++ b/test/Transforms/InstCombine/add-sitofp.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -instcombine -S | grep "add nsw i32" +; RUN: opt < %s -instcombine -S | grep "add nuw nsw i32" define double @x(i32 %a, i32 %b) nounwind { %m = lshr i32 %a, 24 diff --git a/test/Transforms/InstCombine/add2.ll b/test/Transforms/InstCombine/add2.ll index 0964bc00d1cb..d7eac4b0fd21 100644 --- a/test/Transforms/InstCombine/add2.ll +++ b/test/Transforms/InstCombine/add2.ll @@ -41,3 +41,275 @@ define i32 @test4(i32 %A) { ; CHECK-NEXT: ret i32 %B } +define <2 x i1> @test5(<2 x i1> %A, <2 x i1> %B) { + %add = add <2 x i1> %A, %B + ret <2 x i1> %add +; CHECK-LABEL: @test5( +; CHECK-NEXT: %add = xor <2 x i1> %A, %B +; CHECK-NEXT: ret <2 x i1> %add +} + +define <2 x i64> @test6(<2 x i64> %A) { + %shl = shl <2 x i64> %A, <i64 2, i64 3> + %add = add <2 x i64> %shl, %A + ret <2 x i64> %add +; CHECK-LABEL: @test6( +; CHECK-NEXT: %add = mul <2 x i64> %A, <i64 5, i64 9> +; CHECK-NEXT: ret <2 x i64> %add +} + +define <2 x i64> @test7(<2 x i64> %A) { + %shl = shl <2 x i64> %A, <i64 2, i64 3> + %mul = mul <2 x i64> %A, <i64 3, i64 4> + %add = add <2 x i64> %shl, %mul + ret <2 x i64> %add +; CHECK-LABEL: @test7( +; CHECK-NEXT: %add = mul <2 x i64> %A, <i64 7, i64 12> +; CHECK-NEXT: ret <2 x i64> %add +} + +define <2 x i64> @test8(<2 x i64> %A) { + %xor = xor <2 x i64> %A, <i64 -1, i64 -1> + %add = add <2 x i64> %xor, <i64 2, i64 3> + ret <2 x i64> %add +; CHECK-LABEL: @test8( +; CHECK-NEXT: %add = sub <2 x i64> <i64 1, i64 2>, %A +; CHECK-NEXT: ret <2 x i64> %add +} + +define i16 @test9(i16 %a) { + %b = mul i16 %a, 2 + %c = mul i16 %a, 32767 + %d = add i16 %b, %c + ret i16 %d +; CHECK-LABEL: @test9( +; CHECK-NEXT: %d = mul i16 %a, -32767 +; CHECK-NEXT: ret i16 %d +} + +; y + (~((x >> 3) & 0x55555555) + 1) -> y - ((x >> 3) & 0x55555555) +define i32 @test10(i32 %x, i32 %y) { + %shr = ashr i32 %x, 3 + %shr.not = or i32 %shr, -1431655766 + %neg = xor i32 %shr.not, 1431655765 + %add = add i32 %y, 1 + %add1 = add i32 %add, %neg + ret i32 %add1 +; CHECK-LABEL: @test10( +; CHECK-NEXT: [[SHR:%[a-z0-9]+]] = ashr i32 %x, 3 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHR]], 1431655765 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +; y + (~(x & 0x55555555) + 1) -> y - (x & 0x55555555) +define i32 @test11(i32 %x, i32 %y) { + %x.not = or i32 %x, -1431655766 + %neg = xor i32 %x.not, 1431655765 + %add = add i32 %y, 1 + %add1 = add i32 %add, %neg + ret i32 %add1 +; CHECK-LABEL: @test11( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 1431655765 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +; (y + 1) + ~(x & 0x55555555) -> y - (x & 0x55555555) +define i32 @test12(i32 %x, i32 %y) { + %add = add nsw i32 %y, 1 + %x.not = or i32 %x, -1431655766 + %neg = xor i32 %x.not, 1431655765 + %add1 = add nsw i32 %add, %neg + ret i32 %add1 +; CHECK-LABEL: @test12( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 1431655765 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +; y + (~(x & 0x55555556) + 1) -> y - (x & 0x55555556) +define i32 @test13(i32 %x, i32 %y) { + %x.not = or i32 %x, -1431655767 + %neg = xor i32 %x.not, 1431655766 + %add = add i32 %y, 1 + %add1 = add i32 %add, %neg + ret i32 %add1 +; CHECK-LABEL: @test13( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 1431655766 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +; (y + 1) + ~(x & 0x55555556) -> y - (x & 0x55555556) +define i32 @test14(i32 %x, i32 %y) { + %add = add nsw i32 %y, 1 + %x.not = or i32 %x, -1431655767 + %neg = xor i32 %x.not, 1431655766 + %add1 = add nsw i32 %add, %neg + ret i32 %add1 +; CHECK-LABEL: @test14( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 1431655766 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +; y + (~(x | 0x55555556) + 1) -> y - (x | 0x55555556) +define i32 @test15(i32 %x, i32 %y) { + %x.not = and i32 %x, -1431655767 + %neg = xor i32 %x.not, -1431655767 + %add = add i32 %y, 1 + %add1 = add i32 %add, %neg + ret i32 %add1 +; CHECK-LABEL: @test15( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = or i32 %x, 1431655766 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +; (y + 1) + ~(x | 0x55555556) -> y - (x | 0x555555556) +define i32 @test16(i32 %x, i32 %y) { + %add = add nsw i32 %y, 1 + %x.not = and i32 %x, -1431655767 + %neg = xor i32 %x.not, -1431655767 + %add1 = add nsw i32 %add, %neg + ret i32 %add1 +; CHECK-LABEL: @test16( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = or i32 %x, 1431655766 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +; y + (~(x | 0x55555555) + 1) -> y - (x | 0x55555555) +define i32 @test17(i32 %x, i32 %y) { + %x.not = and i32 %x, -1431655766 + %add2 = xor i32 %x.not, -1431655765 + %add1 = add nsw i32 %add2, %y + ret i32 %add1 +; CHECK-LABEL: @test17( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = or i32 %x, 1431655765 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +; (y + 1) + ~(x | 0x55555555) -> y - (x | 0x55555555) +define i32 @test18(i32 %x, i32 %y) { + %add = add nsw i32 %y, 1 + %x.not = and i32 %x, -1431655766 + %neg = xor i32 %x.not, -1431655766 + %add1 = add nsw i32 %add, %neg + ret i32 %add1 +; CHECK-LABEL: @test18( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = or i32 %x, 1431655765 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]] +; CHECK-NEXT: ret i32 [[SUB]] +} + +define i16 @add_nsw_mul_nsw(i16 %x) { + %add1 = add nsw i16 %x, %x + %add2 = add nsw i16 %add1, %x + ret i16 %add2 +; CHECK-LABEL: @add_nsw_mul_nsw( +; CHECK-NEXT: %add2 = mul nsw i16 %x, 3 +; CHECK-NEXT: ret i16 %add2 +} + +define i16 @mul_add_to_mul_1(i16 %x) { + %mul1 = mul nsw i16 %x, 8 + %add2 = add nsw i16 %x, %mul1 + ret i16 %add2 +; CHECK-LABEL: @mul_add_to_mul_1( +; CHECK-NEXT: %add2 = mul nsw i16 %x, 9 +; CHECK-NEXT: ret i16 %add2 +} + +define i16 @mul_add_to_mul_2(i16 %x) { + %mul1 = mul nsw i16 %x, 8 + %add2 = add nsw i16 %mul1, %x + ret i16 %add2 +; CHECK-LABEL: @mul_add_to_mul_2( +; CHECK-NEXT: %add2 = mul nsw i16 %x, 9 +; CHECK-NEXT: ret i16 %add2 +} + +define i16 @mul_add_to_mul_3(i16 %a) { + %mul1 = mul i16 %a, 2 + %mul2 = mul i16 %a, 3 + %add = add nsw i16 %mul1, %mul2 + ret i16 %add +; CHECK-LABEL: @mul_add_to_mul_3( +; CHECK-NEXT: %add = mul i16 %a, 5 +; CHECK-NEXT: ret i16 %add +} + +define i16 @mul_add_to_mul_4(i16 %a) { + %mul1 = mul nsw i16 %a, 2 + %mul2 = mul nsw i16 %a, 7 + %add = add nsw i16 %mul1, %mul2 + ret i16 %add +; CHECK-LABEL: @mul_add_to_mul_4( +; CHECK-NEXT: %add = mul nsw i16 %a, 9 +; CHECK-NEXT: ret i16 %add +} + +define i16 @mul_add_to_mul_5(i16 %a) { + %mul1 = mul nsw i16 %a, 3 + %mul2 = mul nsw i16 %a, 7 + %add = add nsw i16 %mul1, %mul2 + ret i16 %add +; CHECK-LABEL: @mul_add_to_mul_5( +; CHECK-NEXT: %add = mul nsw i16 %a, 10 +; CHECK-NEXT: ret i16 %add +} + +define i32 @mul_add_to_mul_6(i32 %x, i32 %y) { + %mul1 = mul nsw i32 %x, %y + %mul2 = mul nsw i32 %mul1, 5 + %add = add nsw i32 %mul1, %mul2 + ret i32 %add +; CHECK-LABEL: @mul_add_to_mul_6( +; CHECK-NEXT: %mul1 = mul nsw i32 %x, %y +; CHECK-NEXT: %add = mul nsw i32 %mul1, 6 +; CHECK-NEXT: ret i32 %add +} + +; This test and the next test verify that when a range metadata is attached to +; llvm.cttz, ValueTracking correctly intersects the range specified by the +; metadata and the range implied by the intrinsic. +; +; In this test, the range specified by the metadata is more strict. Therefore, +; ValueTracking uses that range. +define i16 @add_cttz(i16 %a) { +; CHECK-LABEL: @add_cttz( + ; llvm.cttz.i16(..., /*is_zero_undefined=*/true) implies the value returned + ; is in [0, 16). The range metadata indicates the value returned is in [0, 8). + ; Intersecting these ranges, we know the value returned is in [0, 8). + ; Therefore, InstCombine will transform + ; add %cttz, 1111 1111 1111 1000 ; decimal -8 + ; to + ; or %cttz, 1111 1111 1111 1000 + %cttz = call i16 @llvm.cttz.i16(i16 %a, i1 true), !range !0 + %b = add i16 %cttz, -8 +; CHECK: or i16 %cttz, -8 + ret i16 %b +} +declare i16 @llvm.cttz.i16(i16, i1) +!0 = metadata !{i16 0, i16 8} + +; Similar to @add_cttz, but in this test, the range implied by the +; intrinsic is more strict. Therefore, ValueTracking uses that range. +define i16 @add_cttz_2(i16 %a) { +; CHECK-LABEL: @add_cttz_2( + ; llvm.cttz.i16(..., /*is_zero_undefined=*/true) implies the value returned + ; is in [0, 16). The range metadata indicates the value returned is in + ; [0, 32). Intersecting these ranges, we know the value returned is in + ; [0, 16). Therefore, InstCombine will transform + ; add %cttz, 1111 1111 1111 0000 ; decimal -16 + ; to + ; or %cttz, 1111 1111 1111 0000 + %cttz = call i16 @llvm.cttz.i16(i16 %a, i1 true), !range !1 + %b = add i16 %cttz, -16 +; CHECK: or i16 %cttz, -16 + ret i16 %b +} +!1 = metadata !{i16 0, i16 32} diff --git a/test/Transforms/InstCombine/add4.ll b/test/Transforms/InstCombine/add4.ll index 208c7f03200e..f9b7e3b5a079 100644 --- a/test/Transforms/InstCombine/add4.ll +++ b/test/Transforms/InstCombine/add4.ll @@ -77,3 +77,26 @@ define float @test7(float %A, float %B, i32 %C) { ; CHECK: uitofp } +define <4 x float> @test8(<4 x float> %A, <4 x float> %B, <4 x i1> %C) { + ;; B*(uitofp i1 C) + A*(1 - uitofp i1 C) -> select C, A, B + %cf = uitofp <4 x i1> %C to <4 x float> + %mc = fsub fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %cf + %p1 = fmul fast <4 x float> %A, %mc + %p2 = fmul fast <4 x float> %B, %cf + %s1 = fadd fast <4 x float> %p2, %p1 + ret <4 x float> %s1 +; CHECK-LABEL: @test8( +; CHECK: select <4 x i1> %C, <4 x float> %B, <4 x float> %A +} + +define <4 x float> @test9(<4 x float> %A, <4 x float> %B, <4 x i1> %C) { + ;; A*(1 - uitofp i1 C) + B*(uitofp i1 C) -> select C, A, B + %cf = uitofp <4 x i1> %C to <4 x float> + %mc = fsub fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %cf + %p1 = fmul fast <4 x float> %A, %mc + %p2 = fmul fast <4 x float> %B, %cf + %s1 = fadd fast <4 x float> %p1, %p2 + ret <4 x float> %s1 +; CHECK-LABEL: @test9 +; CHECK: select <4 x i1> %C, <4 x float> %B, <4 x float> %A +} diff --git a/test/Transforms/InstCombine/addrspacecast.ll b/test/Transforms/InstCombine/addrspacecast.ll index d908b556e195..c1684361f99f 100644 --- a/test/Transforms/InstCombine/addrspacecast.ll +++ b/test/Transforms/InstCombine/addrspacecast.ll @@ -28,13 +28,91 @@ define <4 x i32*> @combine_redundant_addrspacecast_vector(<4 x i32 addrspace(1)* define float* @combine_redundant_addrspacecast_types(i32 addrspace(1)* %x) nounwind { ; CHECK-LABEL: @combine_redundant_addrspacecast_types( -; CHECK: addrspacecast i32 addrspace(1)* %x to float* +; CHECK-NEXT: bitcast i32 addrspace(1)* %x to float addrspace(1)* +; CHECK-NEXT: addrspacecast float addrspace(1)* %1 to float* ; CHECK-NEXT: ret %y = addrspacecast i32 addrspace(1)* %x to i32 addrspace(3)* %z = addrspacecast i32 addrspace(3)* %y to float* ret float* %z } +define <4 x float*> @combine_redundant_addrspacecast_types_vector(<4 x i32 addrspace(1)*> %x) nounwind { +; CHECK-LABEL: @combine_redundant_addrspacecast_types_vector( +; CHECK-NEXT: bitcast <4 x i32 addrspace(1)*> %x to <4 x float addrspace(1)*> +; CHECK-NEXT: addrspacecast <4 x float addrspace(1)*> %1 to <4 x float*> +; CHECK-NEXT: ret + %y = addrspacecast <4 x i32 addrspace(1)*> %x to <4 x i32 addrspace(3)*> + %z = addrspacecast <4 x i32 addrspace(3)*> %y to <4 x float*> + ret <4 x float*> %z +} + +define float addrspace(2)* @combine_addrspacecast_bitcast_1(i32 addrspace(1)* %x) nounwind { +; CHECK-LABEL: @combine_addrspacecast_bitcast_1( +; CHECK-NEXT: bitcast i32 addrspace(1)* %x to float addrspace(1)* +; CHECK-NEXT: addrspacecast float addrspace(1)* %1 to float addrspace(2)* +; CHECK-NEXT: ret + %y = addrspacecast i32 addrspace(1)* %x to i32 addrspace(2)* + %z = bitcast i32 addrspace(2)* %y to float addrspace(2)* + ret float addrspace(2)* %z +} + +define i32 addrspace(2)* @combine_addrspacecast_bitcast_2(i32 addrspace(1)* %x) nounwind { +; CHECK-LABEL: @combine_addrspacecast_bitcast_2( +; CHECK: addrspacecast i32 addrspace(1)* %x to i32 addrspace(2)* +; CHECK-NEXT: ret + %y = addrspacecast i32 addrspace(1)* %x to float addrspace(2)* + %z = bitcast float addrspace(2)* %y to i32 addrspace(2)* + ret i32 addrspace(2)* %z +} + +define i32 addrspace(2)* @combine_bitcast_addrspacecast_1(i32 addrspace(1)* %x) nounwind { +; CHECK-LABEL: @combine_bitcast_addrspacecast_1( +; CHECK: addrspacecast i32 addrspace(1)* %x to i32 addrspace(2)* +; CHECK-NEXT: ret + %y = bitcast i32 addrspace(1)* %x to i8 addrspace(1)* + %z = addrspacecast i8 addrspace(1)* %y to i32 addrspace(2)* + ret i32 addrspace(2)* %z +} + +define float addrspace(2)* @combine_bitcast_addrspacecast_2(i32 addrspace(1)* %x) nounwind { +; CHECK-LABEL: @combine_bitcast_addrspacecast_2( +; CHECK: bitcast i32 addrspace(1)* %x to float addrspace(1)* +; CHECK: addrspacecast float addrspace(1)* %1 to float addrspace(2)* +; CHECK-NEXT: ret + %y = bitcast i32 addrspace(1)* %x to i8 addrspace(1)* + %z = addrspacecast i8 addrspace(1)* %y to float addrspace(2)* + ret float addrspace(2)* %z +} + +define float addrspace(2)* @combine_addrspacecast_types(i32 addrspace(1)* %x) nounwind { +; CHECK-LABEL: @combine_addrspacecast_types( +; CHECK-NEXT: bitcast i32 addrspace(1)* %x to float addrspace(1)* +; CHECK-NEXT: addrspacecast float addrspace(1)* %1 to float addrspace(2)* +; CHECK-NEXT: ret + %y = addrspacecast i32 addrspace(1)* %x to float addrspace(2)* + ret float addrspace(2)* %y +} + +define <4 x float addrspace(2)*> @combine_addrspacecast_types_vector(<4 x i32 addrspace(1)*> %x) nounwind { +; CHECK-LABEL: @combine_addrspacecast_types_vector( +; CHECK-NEXT: bitcast <4 x i32 addrspace(1)*> %x to <4 x float addrspace(1)*> +; CHECK-NEXT: addrspacecast <4 x float addrspace(1)*> %1 to <4 x float addrspace(2)*> +; CHECK-NEXT: ret + %y = addrspacecast <4 x i32 addrspace(1)*> %x to <4 x float addrspace(2)*> + ret <4 x float addrspace(2)*> %y +} + +define i32 @canonicalize_addrspacecast([16 x i32] addrspace(1)* %arr) { +; CHECK-LABEL: @canonicalize_addrspacecast( +; CHECK-NEXT: getelementptr inbounds [16 x i32] addrspace(1)* %arr, i32 0, i32 0 +; CHECK-NEXT: addrspacecast i32 addrspace(1)* %{{[a-zA-Z0-9]+}} to i32* +; CHECK-NEXT: load i32* +; CHECK-NEXT: ret i32 + %p = addrspacecast [16 x i32] addrspace(1)* %arr to i32* + %v = load i32* %p + ret i32 %v +} + @const_array = addrspace(2) constant [60 x i8] [i8 2, i8 9, i8 4, i8 22, i8 2, i8 9, i8 4, i8 22, i8 2, i8 9, i8 4, i8 22, i8 2, i8 9, i8 4, i8 22, i8 2, i8 9, i8 4, i8 22, i8 2, i8 9, i8 4, i8 22, i8 2, i8 9, i8 4, i8 22, i8 2, i8 9, i8 4, i8 22, i8 2, i8 9, i8 4, i8 22, diff --git a/test/Transforms/InstCombine/align-2d-gep.ll b/test/Transforms/InstCombine/align-2d-gep.ll index 5bca46d5a21d..f6a877684ce4 100644 --- a/test/Transforms/InstCombine/align-2d-gep.ll +++ b/test/Transforms/InstCombine/align-2d-gep.ll @@ -31,7 +31,7 @@ bb1: store <2 x double><double 0.0, double 0.0>, <2 x double>* %r, align 8 %indvar.next = add i64 %j, 2 - %exitcond = icmp eq i64 %indvar.next, 557 + %exitcond = icmp eq i64 %indvar.next, 556 br i1 %exitcond, label %bb11, label %bb1 bb11: diff --git a/test/Transforms/InstCombine/alloca.ll b/test/Transforms/InstCombine/alloca.ll index ae1cfa1ed2fc..6d0c131c51ed 100644 --- a/test/Transforms/InstCombine/alloca.ll +++ b/test/Transforms/InstCombine/alloca.ll @@ -129,3 +129,24 @@ define void @test8() { call void (...)* @use(i32* %x) ret void } + +; PR19569 +%struct_type = type { i32, i32 } +declare void @test9_aux(<{ %struct_type }>* inalloca) +declare i8* @llvm.stacksave() +declare void @llvm.stackrestore(i8*) + +define void @test9(%struct_type* %a) { +; CHECK-LABEL: @test9( +entry: + %inalloca.save = call i8* @llvm.stacksave() + %argmem = alloca inalloca <{ %struct_type }> +; CHECK: alloca inalloca i64, align 8 + %0 = getelementptr inbounds <{ %struct_type }>* %argmem, i32 0, i32 0 + %1 = bitcast %struct_type* %0 to i8* + %2 = bitcast %struct_type* %a to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* %2, i32 8, i32 4, i1 false) + call void @test9_aux(<{ %struct_type }>* inalloca %argmem) + call void @llvm.stackrestore(i8* %inalloca.save) + ret void +} diff --git a/test/Transforms/InstCombine/ashr-nop.ll b/test/Transforms/InstCombine/ashr-nop.ll deleted file mode 100644 index 870ede38cd88..000000000000 --- a/test/Transforms/InstCombine/ashr-nop.ll +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: opt < %s -instcombine -S | not grep ashr - -define i32 @foo(i32 %x) { - %o = and i32 %x, 1 - %n = add i32 %o, -1 - %t = ashr i32 %n, 17 - ret i32 %t -} diff --git a/test/Transforms/InstCombine/bitcast-store.ll b/test/Transforms/InstCombine/bitcast-store.ll index e4a61e98e4f5..e46b5c82d9ff 100644 --- a/test/Transforms/InstCombine/bitcast-store.ll +++ b/test/Transforms/InstCombine/bitcast-store.ll @@ -3,14 +3,14 @@ ; Instcombine should preserve metadata and alignment while ; folding a bitcast into a store. -; CHECK: store i32 (...)** bitcast (i8** getelementptr inbounds ([5 x i8*]* @G, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 16, !tag !0 - target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" %struct.A = type { i32 (...)** } @G = external constant [5 x i8*] +; CHECK-LABEL: @foo +; CHECK: store i32 (...)** bitcast (i8** getelementptr inbounds ([5 x i8*]* @G, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 16, !tag !0 define void @foo(%struct.A* %a) nounwind { entry: %0 = bitcast %struct.A* %a to i8*** @@ -18,4 +18,18 @@ entry: ret void } +; Check instcombine doesn't try and fold the following bitcast into the store. +; This transformation would not be safe since we would need to use addrspacecast +; and addrspacecast is not guaranteed to be a no-op cast. + +; CHECK-LABEL: @bar +; CHECK: %cast = bitcast i8** %b to i8 addrspace(1)** +; CHECK: store i8 addrspace(1)* %a, i8 addrspace(1)** %cast +define void @bar(i8 addrspace(1)* %a, i8** %b) nounwind { +entry: + %cast = bitcast i8** %b to i8 addrspace(1)** + store i8 addrspace(1)* %a, i8 addrspace(1)** %cast + ret void +} + !0 = metadata !{metadata !"hello"} diff --git a/test/Transforms/InstCombine/blend_x86.ll b/test/Transforms/InstCombine/blend_x86.ll new file mode 100644 index 000000000000..778d44ba342c --- /dev/null +++ b/test/Transforms/InstCombine/blend_x86.ll @@ -0,0 +1,55 @@ +; RUN: opt < %s -instcombine -mtriple=x86_64-apple-macosx -mcpu=core-avx2 -S | FileCheck %s + +define <2 x double> @constant_blendvpd(<2 x double> %xy, <2 x double> %ab) { +; CHECK-LABEL: @constant_blendvpd +; CHECK: select <2 x i1> <i1 true, i1 false>, <2 x double> %ab, <2 x double> %xy + %1 = tail call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %xy, <2 x double> %ab, <2 x double> <double 0xFFFFFFFFE0000000, double 0.000000e+00>) + ret <2 x double> %1 +} + +define <4 x float> @constant_blendvps(<4 x float> %xyzw, <4 x float> %abcd) { +; CHECK-LABEL: @constant_blendvps +; CHECK: select <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %abcd, <4 x float> %xyzw + %1 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %xyzw, <4 x float> %abcd, <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0xFFFFFFFFE0000000>) + ret <4 x float> %1 +} + +define <16 x i8> @constant_pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd) { +; CHECK-LABEL: @constant_pblendvb +; CHECK: select <16 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <16 x i8> %abcd, <16 x i8> %xyzw + %1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd, <16 x i8> <i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0>) + ret <16 x i8> %1 +} + +define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) { +; CHECK-LABEL: @constant_blendvpd_avx +; CHECK: select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %ab, <4 x double> %xy + %1 = tail call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %xy, <4 x double> %ab, <4 x double> <double 0xFFFFFFFFE0000000, double 0.000000e+00, double 0xFFFFFFFFE0000000, double 0.000000e+00>) + ret <4 x double> %1 +} + +define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) { +; CHECK-LABEL: @constant_blendvps_avx +; CHECK: select <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x float> %abcd, <8 x float> %xyzw + %1 = tail call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %xyzw, <8 x float> %abcd, <8 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0xFFFFFFFFE0000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0xFFFFFFFFE0000000>) + ret <8 x float> %1 +} + +define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) { +; CHECK-LABEL: @constant_pblendvb_avx2 +; CHECK: select <32 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <32 x i8> %abcd, <32 x i8> %xyzw + %1 = tail call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %xyzw, <32 x i8> %abcd, + <32 x i8> <i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, + i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, + i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, + i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0>) + ret <32 x i8> %1 +} + +declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>) +declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) +declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>) + +declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>) +declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) +declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) diff --git a/test/Transforms/InstCombine/call-cast-target-inalloca.ll b/test/Transforms/InstCombine/call-cast-target-inalloca.ll new file mode 100644 index 000000000000..90289e2468f8 --- /dev/null +++ b/test/Transforms/InstCombine/call-cast-target-inalloca.ll @@ -0,0 +1,22 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +target datalayout = "e-p:32:32" +target triple = "i686-pc-linux-gnu" + +declare void @takes_i32(i32) +declare void @takes_i32_inalloca(i32* inalloca) + +define void @f() { +; CHECK-LABEL: define void @f() + %args = alloca inalloca i32 + call void bitcast (void (i32)* @takes_i32 to void (i32*)*)(i32* inalloca %args) +; CHECK: call void bitcast + ret void +} + +define void @g() { +; CHECK-LABEL: define void @g() + call void bitcast (void (i32*)* @takes_i32_inalloca to void (i32)*)(i32 0) +; CHECK: call void bitcast + ret void +} diff --git a/test/Transforms/InstCombine/call-cast-target.ll b/test/Transforms/InstCombine/call-cast-target.ll index 315c51683fd2..1af3317a398b 100644 --- a/test/Transforms/InstCombine/call-cast-target.ll +++ b/test/Transforms/InstCombine/call-cast-target.ll @@ -13,3 +13,15 @@ entry: declare i8* @ctime(i32*) +define internal { i8 } @foo(i32*) { +entry: + ret { i8 } { i8 0 } +} + +define void @test_struct_ret() { +; CHECK-LABEL: @test_struct_ret +; CHECK-NOT: bitcast +entry: + %0 = call { i8 } bitcast ({ i8 } (i32*)* @foo to { i8 } (i16*)*)(i16* null) + ret void +} diff --git a/test/Transforms/InstCombine/cast-call-combine.ll b/test/Transforms/InstCombine/cast-call-combine.ll new file mode 100644 index 000000000000..be70a8763ea8 --- /dev/null +++ b/test/Transforms/InstCombine/cast-call-combine.ll @@ -0,0 +1,23 @@ +; RUN: opt < %s -always-inline -instcombine -S | FileCheck %s + +define internal void @foo(i16*) alwaysinline { + ret void +} + +define void @bar() noinline noreturn { + unreachable +} + +define void @test() { + br i1 false, label %then, label %else + +then: + call void @bar() + unreachable + +else: + ; CHECK-NOT: call + call void bitcast (void (i16*)* @foo to void (i8*)*) (i8* null) + ret void +} + diff --git a/test/Transforms/InstCombine/cast-set.ll b/test/Transforms/InstCombine/cast-set.ll index 893440424c4c..47ba920d9286 100644 --- a/test/Transforms/InstCombine/cast-set.ll +++ b/test/Transforms/InstCombine/cast-set.ll @@ -10,6 +10,7 @@ define i1 @test1(i32 %X) { ; Convert to setne int %X, 12 %c = icmp ne i32 %A, 12 ; <i1> [#uses=1] ret i1 %c +; CHECK-LABEL @test1( ; CHECK: %c = icmp ne i32 %X, 12 ; CHECK: ret i1 %c } @@ -20,6 +21,7 @@ define i1 @test2(i32 %X, i32 %Y) { ; Convert to setne int %X, %Y %c = icmp ne i32 %A, %B ; <i1> [#uses=1] ret i1 %c +; CHECK-LABEL @test2( ; CHECK: %c = icmp ne i32 %X, %Y ; CHECK: ret i1 %c } @@ -29,6 +31,7 @@ define i32 @test4(i32 %A) { %C = shl i32 %B, 2 ; <i32> [#uses=1] %D = bitcast i32 %C to i32 ; <i32> [#uses=1] ret i32 %D +; CHECK-LABEL: @test4( ; CHECK: %C = shl i32 %A, 2 ; CHECK: ret i32 %C } @@ -38,6 +41,7 @@ define i16 @test5(i16 %A) { %C = and i32 %B, 15 ; <i32> [#uses=1] %D = trunc i32 %C to i16 ; <i16> [#uses=1] ret i16 %D +; CHECK-LABEL: @test5( ; CHECK: %C = and i16 %A, 15 ; CHECK: ret i16 %C } @@ -46,6 +50,7 @@ define i1 @test6(i1 %A) { %B = zext i1 %A to i32 ; <i32> [#uses=1] %C = icmp ne i32 %B, 0 ; <i1> [#uses=1] ret i1 %C +; CHECK-LABEL: @test6( ; CHECK: ret i1 %A } @@ -53,6 +58,7 @@ define i1 @test6a(i1 %A) { %B = zext i1 %A to i32 ; <i32> [#uses=1] %C = icmp ne i32 %B, -1 ; <i1> [#uses=1] ret i1 %C +; CHECK-LABEL: @test6a( ; CHECK: ret i1 true } @@ -60,6 +66,7 @@ define i1 @test7(i8* %A) { %B = bitcast i8* %A to i32* ; <i32*> [#uses=1] %C = icmp eq i32* %B, null ; <i1> [#uses=1] ret i1 %C +; CHECK-LABEL: @test7( ; CHECK: %C = icmp eq i8* %A, null ; CHECK: ret i1 %C } diff --git a/test/Transforms/InstCombine/cast.ll b/test/Transforms/InstCombine/cast.ll index cac0ec109163..0cbfbb071bb7 100644 --- a/test/Transforms/InstCombine/cast.ll +++ b/test/Transforms/InstCombine/cast.ll @@ -1,6 +1,6 @@ ; Tests to make sure elimination of casts is working correctly ; RUN: opt < %s -instcombine -S | FileCheck %s -target datalayout = "E-p:64:64:64-p1:32:32:32-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128-n8:16:32:64" +target datalayout = "E-p:64:64:64-p1:32:32:32-p2:64:64:64-p3:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128-n8:16:32:64" @inbuf = external global [32832 x i8] ; <[32832 x i8]*> [#uses=1] @@ -370,7 +370,7 @@ define zeroext i64 @test43(i8 zeroext %on_off) nounwind readonly { ret i64 %C ;; Should be (add (zext i8 -> i64), -1) ; CHECK-LABEL: @test43( ; CHECK-NEXT: %A = zext i8 %on_off to i64 -; CHECK-NEXT: %B = add i64 %A, -1 +; CHECK-NEXT: %B = add nsw i64 %A, -1 ; CHECK-NEXT: ret i64 %B } @@ -708,6 +708,34 @@ define %s @test68(%s *%p, i64 %i) { ; CHECK-NEXT: ret %s } +; addrspacecasts should be eliminated. +define %s @test68_addrspacecast(%s* %p, i64 %i) { +; CHECK-LABEL: @test68_addrspacecast( +; CHECK-NEXT: getelementptr %s* +; CHECK-NEXT: load %s* +; CHECK-NEXT: ret %s + %o = mul i64 %i, 12 + %q = addrspacecast %s* %p to i8 addrspace(2)* + %pp = getelementptr inbounds i8 addrspace(2)* %q, i64 %o + %r = addrspacecast i8 addrspace(2)* %pp to %s* + %l = load %s* %r + ret %s %l +} + +define %s @test68_addrspacecast_2(%s* %p, i64 %i) { +; CHECK-LABEL: @test68_addrspacecast_2( +; CHECK-NEXT: getelementptr %s* %p +; CHECK-NEXT: addrspacecast +; CHECK-NEXT: load %s addrspace(1)* +; CHECK-NEXT: ret %s + %o = mul i64 %i, 12 + %q = addrspacecast %s* %p to i8 addrspace(2)* + %pp = getelementptr inbounds i8 addrspace(2)* %q, i64 %o + %r = addrspacecast i8 addrspace(2)* %pp to %s addrspace(1)* + %l = load %s addrspace(1)* %r + ret %s %l +} + define %s @test68_as1(%s addrspace(1)* %p, i32 %i) { ; CHECK-LABEL: @test68_as1( %o = mul i32 %i, 12 @@ -903,6 +931,33 @@ define double @test80([100 x double]* %p, i32 %i) { ; CHECK-NEXT: ret double } +define double @test80_addrspacecast([100 x double] addrspace(1)* %p, i32 %i) { +; CHECK-LABEL: @test80_addrspacecast( +; CHECK-NEXT: getelementptr [100 x double] addrspace(1)* %p +; CHECK-NEXT: load double addrspace(1)* +; CHECK-NEXT: ret double + %tmp = mul nsw i32 %i, 8 + %q = addrspacecast [100 x double] addrspace(1)* %p to i8 addrspace(2)* + %pp = getelementptr i8 addrspace(2)* %q, i32 %tmp + %r = addrspacecast i8 addrspace(2)* %pp to double addrspace(1)* + %l = load double addrspace(1)* %r + ret double %l +} + +define double @test80_addrspacecast_2([100 x double] addrspace(1)* %p, i32 %i) { +; CHECK-LABEL: @test80_addrspacecast_2( +; CHECK-NEXT: getelementptr [100 x double] addrspace(1)* +; CHECK-NEXT: addrspacecast double addrspace(1)* +; CHECK-NEXT: load double addrspace(3)* +; CHECK-NEXT: ret double + %tmp = mul nsw i32 %i, 8 + %q = addrspacecast [100 x double] addrspace(1)* %p to i8 addrspace(2)* + %pp = getelementptr i8 addrspace(2)* %q, i32 %tmp + %r = addrspacecast i8 addrspace(2)* %pp to double addrspace(3)* + %l = load double addrspace(3)* %r + ret double %l +} + define double @test80_as1([100 x double] addrspace(1)* %p, i16 %i) { ; CHECK-LABEL: @test80_as1( %tmp = mul nsw i16 %i, 8 diff --git a/test/Transforms/InstCombine/ceil.ll b/test/Transforms/InstCombine/ceil.ll new file mode 100644 index 000000000000..9f965a3c34b4 --- /dev/null +++ b/test/Transforms/InstCombine/ceil.ll @@ -0,0 +1,56 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +declare float @llvm.ceil.f32(float) #0 +declare double @llvm.ceil.f64(double) #0 +declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #0 + +; CHECK-LABEL: @constant_fold_ceil_f32_01 +; CHECK-NEXT: ret float 1.000000e+00 +define float @constant_fold_ceil_f32_01() #0 { + %x = call float @llvm.ceil.f32(float 1.00) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_ceil_f32_02 +; CHECK-NEXT: ret float 2.000000e+00 +define float @constant_fold_ceil_f32_02() #0 { + %x = call float @llvm.ceil.f32(float 1.25) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_ceil_f32_03 +; CHECK-NEXT: ret float -1.000000e+00 +define float @constant_fold_ceil_f32_03() #0 { + %x = call float @llvm.ceil.f32(float -1.25) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_ceil_v4f32_01 +; CHECK-NEXT: ret <4 x float> <float 1.000000e+00, float 2.000000e+00, float -1.000000e+00, float -1.000000e+00> +define <4 x float> @constant_fold_ceil_v4f32_01() #0 { + %x = call <4 x float> @llvm.ceil.v4f32(<4 x float> <float 1.00, float 1.25, float -1.25, float -1.00>) + ret <4 x float> %x +} + +; CHECK-LABEL: @constant_fold_ceil_f64_01 +; CHECK-NEXT: ret double 1.000000e+00 +define double @constant_fold_ceil_f64_01() #0 { + %x = call double @llvm.ceil.f64(double 1.0) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_ceil_f64_02 +; CHECK-NEXT: ret double 2.000000e+00 +define double @constant_fold_ceil_f64_02() #0 { + %x = call double @llvm.ceil.f64(double 1.3) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_ceil_f64_03 +; CHECK-NEXT: ret double -1.000000e+00 +define double @constant_fold_ceil_f64_03() #0 { + %x = call double @llvm.ceil.f64(double -1.75) #0 + ret double %x +} + +attributes #0 = { nounwind readnone } diff --git a/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll b/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll index 9f21d5419b72..7fac78a40f56 100644 --- a/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll +++ b/test/Transforms/InstCombine/constant-fold-address-space-pointer.ll @@ -230,3 +230,13 @@ define i32 @constant_through_array_as_ptrs() { %b = load i32 addrspace(1)* %a, align 4 ret i32 %b } + +@shared_mem = external addrspace(3) global [0 x i8] + +define float @canonicalize_addrspacecast(i32 %i) { +; CHECK-LABEL: @canonicalize_addrspacecast +; CHECK-NEXT: getelementptr inbounds float* addrspacecast (float addrspace(3)* bitcast ([0 x i8] addrspace(3)* @shared_mem to float addrspace(3)*) to float*), i32 %i + %p = getelementptr inbounds float* addrspacecast ([0 x i8] addrspace(3)* @shared_mem to float*), i32 %i + %v = load float* %p + ret float %v +} diff --git a/test/Transforms/InstCombine/constant-fold-math.ll b/test/Transforms/InstCombine/constant-fold-math.ll new file mode 100644 index 000000000000..14377df37299 --- /dev/null +++ b/test/Transforms/InstCombine/constant-fold-math.ll @@ -0,0 +1,47 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +declare float @llvm.fma.f32(float, float, float) #0 +declare float @llvm.fmuladd.f32(float, float, float) #0 +declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 + +declare double @llvm.fma.f64(double, double, double) #0 +declare double @llvm.fmuladd.f64(double, double, double) #0 + + + +; CHECK-LABEL: @constant_fold_fma_f32 +; CHECK-NEXT: ret float 6.000000e+00 +define float @constant_fold_fma_f32() #0 { + %x = call float @llvm.fma.f32(float 1.0, float 2.0, float 4.0) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_fma_v4f32 +; CHECK-NEXT: ret <4 x float> <float 1.200000e+01, float 1.400000e+01, float 1.600000e+01, float 1.800000e+01> +define <4 x float> @constant_fold_fma_v4f32() #0 { + %x = call <4 x float> @llvm.fma.v4f32(<4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>, <4 x float> <float 10.0, float 10.0, float 10.0, float 10.0>) + ret <4 x float> %x +} + +; CHECK-LABEL: @constant_fold_fmuladd_f32 +; CHECK-NEXT: ret float 6.000000e+00 +define float @constant_fold_fmuladd_f32() #0 { + %x = call float @llvm.fmuladd.f32(float 1.0, float 2.0, float 4.0) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_fma_f64 +; CHECK-NEXT: ret double 6.000000e+00 +define double @constant_fold_fma_f64() #0 { + %x = call double @llvm.fma.f64(double 1.0, double 2.0, double 4.0) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_fmuladd_f64 +; CHECK-NEXT: ret double 6.000000e+00 +define double @constant_fold_fmuladd_f64() #0 { + %x = call double @llvm.fmuladd.f64(double 1.0, double 2.0, double 4.0) #0 + ret double %x +} + +attributes #0 = { nounwind readnone } diff --git a/test/Transforms/InstCombine/copysign.ll b/test/Transforms/InstCombine/copysign.ll new file mode 100644 index 000000000000..556b79999b02 --- /dev/null +++ b/test/Transforms/InstCombine/copysign.ll @@ -0,0 +1,49 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +declare float @llvm.copysign.f32(float, float) #0 +declare double @llvm.copysign.f64(double, double) #0 + +; CHECK-LABEL: @constant_fold_copysign_f32_01 +; CHECK-NEXT: ret float -1.000000e+00 +define float @constant_fold_copysign_f32_01() #0 { + %x = call float @llvm.copysign.f32(float 1.0, float -2.0) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_copysign_f32_02 +; CHECK-NEXT: ret float 2.000000e+00 +define float @constant_fold_copysign_f32_02() #0 { + %x = call float @llvm.copysign.f32(float -2.0, float 1.0) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_copysign_f32_03 +; CHECK-NEXT: ret float -2.000000e+00 +define float @constant_fold_copysign_f32_03() #0 { + %x = call float @llvm.copysign.f32(float -2.0, float -1.0) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_copysign_f64_01 +; CHECK-NEXT: ret double -1.000000e+00 +define double @constant_fold_copysign_f64_01() #0 { + %x = call double @llvm.copysign.f64(double 1.0, double -2.0) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_copysign_f64_02 +; CHECK-NEXT: ret double 1.000000e+00 +define double @constant_fold_copysign_f64_02() #0 { + %x = call double @llvm.copysign.f64(double -1.0, double 2.0) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_copysign_f64_03 +; CHECK-NEXT: ret double -1.000000e+00 +define double @constant_fold_copysign_f64_03() #0 { + %x = call double @llvm.copysign.f64(double -1.0, double -2.0) #0 + ret double %x +} + + +attributes #0 = { nounwind readnone } diff --git a/test/Transforms/InstCombine/descale-zero.ll b/test/Transforms/InstCombine/descale-zero.ll new file mode 100644 index 000000000000..7990fdb3eca3 --- /dev/null +++ b/test/Transforms/InstCombine/descale-zero.ll @@ -0,0 +1,21 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.10.0" + +define internal i8* @descale_zero() { +entry: +; CHECK: load i16** inttoptr (i64 48 to i16**), align 16 +; CHECK-NEXT: bitcast i16* +; CHECK-NEXT: ret i8* + %i16_ptr = load i16** inttoptr (i64 48 to i16**), align 16 + %num = load i64* inttoptr (i64 64 to i64*), align 64 + %num_times_2 = shl i64 %num, 1 + %num_times_2_plus_4 = add i64 %num_times_2, 4 + %i8_ptr = bitcast i16* %i16_ptr to i8* + %i8_ptr_num_times_2_plus_4 = getelementptr i8* %i8_ptr, i64 %num_times_2_plus_4 + %num_times_neg2 = mul i64 %num, -2 + %num_times_neg2_minus_4 = add i64 %num_times_neg2, -4 + %addr = getelementptr i8* %i8_ptr_num_times_2_plus_4, i64 %num_times_neg2_minus_4 + ret i8* %addr +} diff --git a/test/Transforms/InstSimplify/2010-12-20-Distribute.ll b/test/Transforms/InstCombine/distribute.ll index 9ea0a5e10708..e6360f8ba64e 100644 --- a/test/Transforms/InstSimplify/2010-12-20-Distribute.ll +++ b/test/Transforms/InstCombine/distribute.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -instsimplify -S | FileCheck %s +; RUN: opt < %s -instcombine -S | FileCheck %s define i32 @factorize(i32 %x, i32 %y) { ; CHECK-LABEL: @factorize( @@ -28,27 +28,32 @@ define i32 @factorize3(i32 %x, i32 %a, i32 %b) { %r = or i32 %x, %b %z = and i32 %l, %r ret i32 %z -; CHECK: ret i32 %r +; CHECK: %z = or i32 %b, %x +; CHECK: ret i32 %z } define i32 @factorize4(i32 %x, i32 %y) { ; CHECK-LABEL: @factorize4( +; ((Y << 1) * X) - (X * Y) -> (X * (Y * 2 - Y)) -> (X * Y) %sh = shl i32 %y, 1 %ml = mul i32 %sh, %x %mr = mul i32 %x, %y %s = sub i32 %ml, %mr ret i32 %s -; CHECK: ret i32 %mr +; CHECK: %s = mul i32 %y, %x +; CHECK: ret i32 %s } define i32 @factorize5(i32 %x, i32 %y) { ; CHECK-LABEL: @factorize5( +; ((Y * 2) * X) - (X * Y) -> (X * Y) %sh = mul i32 %y, 2 %ml = mul i32 %sh, %x %mr = mul i32 %x, %y %s = sub i32 %ml, %mr ret i32 %s -; CHECK: ret i32 %mr +; CHECK: %s = mul i32 %y, %x +; CHECK: ret i32 %s } define i32 @expand(i32 %x) { @@ -58,5 +63,6 @@ define i32 @expand(i32 %x) { %b = or i32 %a, 2 %c = and i32 %b, 1 ret i32 %c +; CHECK: %a = and i32 %x, 1 ; CHECK: ret i32 %a } diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll index f67fd1c51be3..9c7ba9b03059 100644 --- a/test/Transforms/InstCombine/div.ll +++ b/test/Transforms/InstCombine/div.ll @@ -131,4 +131,47 @@ define i32 @test15(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: ret i32 } +define <2 x i64> @test16(<2 x i64> %x) nounwind { + %shr = lshr <2 x i64> %x, <i64 3, i64 5> + %div = udiv <2 x i64> %shr, <i64 4, i64 6> + ret <2 x i64> %div +; CHECK-LABEL: @test16( +; CHECK-NEXT: udiv <2 x i64> %x, <i64 32, i64 192> +; CHECK-NEXT: ret <2 x i64> +} + +define <2 x i64> @test17(<2 x i64> %x) nounwind { + %neg = sub nsw <2 x i64> zeroinitializer, %x + %div = sdiv <2 x i64> %neg, <i64 3, i64 4> + ret <2 x i64> %div +; CHECK-LABEL: @test17( +; CHECK-NEXT: sdiv <2 x i64> %x, <i64 -3, i64 -4> +; CHECK-NEXT: ret <2 x i64> +} + +define <2 x i64> @test18(<2 x i64> %x) nounwind { + %div = sdiv <2 x i64> %x, <i64 -1, i64 -1> + ret <2 x i64> %div +; CHECK-LABEL: @test18( +; CHECK-NEXT: sub <2 x i64> zeroinitializer, %x +; CHECK-NEXT: ret <2 x i64> +} +define i32 @test19(i32 %x) { + %A = udiv i32 1, %x + ret i32 %A +; CHECK-LABEL: @test19( +; CHECK-NEXT: icmp eq i32 %x, 1 +; CHECK-NEXT: zext i1 %{{.*}} to i32 +; CHECK-NEXT ret i32 +} + +define i32 @test20(i32 %x) { + %A = sdiv i32 1, %x + ret i32 %A +; CHECK-LABEL: @test20( +; CHECK-NEXT: add i32 %x, 1 +; CHECK-NEXT: icmp ult i32 %{{.*}}, 3 +; CHECK-NEXT: select i1 %{{.*}}, i32 %x, i32 {{.*}} +; CHECK-NEXT: ret i32 +} diff --git a/test/Transforms/InstCombine/double-float-shrink-1.ll b/test/Transforms/InstCombine/double-float-shrink-1.ll index 5cacb591e006..d958470f1baa 100644 --- a/test/Transforms/InstCombine/double-float-shrink-1.ll +++ b/test/Transforms/InstCombine/double-float-shrink-1.ll @@ -157,7 +157,10 @@ define float @exp10_test(float %f) nounwind readnone { %call = call double @exp10(double %conv) %conv1 = fptrunc double %call to float ret float %conv1 -; CHECK: call float @exp10f(float %f) +; FIXME: Re-enable this when Linux allows transforming this again, or when we +; can use builtin attributes to test the transform regardless of OS. +; DISABLED-CHECK: call float @exp10f(float %f) +; CHECK: call double @exp10(double %conv) } define double @exp10_test2(float %f) nounwind readnone { diff --git a/test/Transforms/InstCombine/exp2-1.ll b/test/Transforms/InstCombine/exp2-1.ll index 99fb9ecfd2b2..8e6a0e0d93f6 100644 --- a/test/Transforms/InstCombine/exp2-1.ll +++ b/test/Transforms/InstCombine/exp2-1.ll @@ -1,6 +1,7 @@ ; Test that the exp2 library call simplifier works correctly. ; ; RUN: opt < %s -instcombine -S | FileCheck %s +; RUN: opt < %s -instcombine -S -mtriple=i386-pc-win32 | FileCheck %s -check-prefix=CHECK-WIN target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" @@ -74,3 +75,26 @@ define float @test_simplify8(i8 zeroext %x) { ; CHECK: call float @ldexpf ret float %ret } + +declare double @llvm.exp2.f64(double) +declare float @llvm.exp2.f32(float) + +define double @test_simplify9(i8 zeroext %x) { +; CHECK-LABEL: @test_simplify9( +; CHECK-WIN-LABEL: @test_simplify9( + %conv = uitofp i8 %x to double + %ret = call double @llvm.exp2.f64(double %conv) +; CHECK: call double @ldexp +; CHECK-WIN: call double @ldexp + ret double %ret +} + +define float @test_simplify10(i8 zeroext %x) { +; CHECK-LABEL: @test_simplify10( +; CHECK-WIN-LABEL: @test_simplify10( + %conv = uitofp i8 %x to float + %ret = call float @llvm.exp2.f32(float %conv) +; CHECK: call float @ldexpf +; CHECK-WIN-NOT: call float @ldexpf + ret float %ret +} diff --git a/test/Transforms/InstCombine/fast-math.ll b/test/Transforms/InstCombine/fast-math.ll index d8ba2a59ff5e..2ee4b0f2c381 100644 --- a/test/Transforms/InstCombine/fast-math.ll +++ b/test/Transforms/InstCombine/fast-math.ll @@ -140,6 +140,42 @@ define float @fold13(float %x) { ; CHECK: ret } +; -x + y => y - x +define float @fold14(float %x, float %y) { + %neg = fsub fast float -0.0, %x + %add = fadd fast float %neg, %y + ret float %add +; CHECK: fold14 +; CHECK: fsub fast float %y, %x +; CHECK: ret +} + +; x + -y => x - y +define float @fold15(float %x, float %y) { + %neg = fsub fast float -0.0, %y + %add = fadd fast float %x, %neg + ret float %add +; CHECK: fold15 +; CHECK: fsub fast float %x, %y +; CHECK: ret +} + +; (select X+Y, X-Y) => X + (select Y, -Y) +define float @fold16(float %x, float %y) { + %cmp = fcmp ogt float %x, %y + %plus = fadd fast float %x, %y + %minus = fsub fast float %x, %y + %r = select i1 %cmp, float %plus, float %minus + ret float %r +; CHECK: fold16 +; CHECK: fsub fast float +; CHECK: select +; CHECK: fadd fast float +; CHECK: ret +} + + + ; ========================================================================= ; ; Testing-cases about fmul begin @@ -223,6 +259,14 @@ define float @fmul3(float %f1, float %f2) { ; CHECK: fmul fast float %f1, 3.000000e+00 } +define <4 x float> @fmul3_vec(<4 x float> %f1, <4 x float> %f2) { + %t1 = fdiv <4 x float> %f1, <float 2.0e+3, float 3.0e+3, float 2.0e+3, float 1.0e+3> + %t3 = fmul fast <4 x float> %t1, <float 6.0e+3, float 6.0e+3, float 2.0e+3, float 1.0e+3> + ret <4 x float> %t3 +; CHECK-LABEL: @fmul3_vec( +; CHECK: fmul fast <4 x float> %f1, <float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00> +} + ; Rule "X/C1 * C2 => X * (C2/C1) is not applicable if C2/C1 is either a special ; value of a denormal. The 0x3810000000000000 here take value FLT_MIN ; @@ -309,6 +353,15 @@ define float @fdiv2(float %x) { ; CHECK: fmul fast float %x, 0x3FE0B21660000000 } +define <2 x float> @fdiv2_vec(<2 x float> %x) { + %mul = fmul <2 x float> %x, <float 6.0, float 9.0> + %div1 = fdiv fast <2 x float> %mul, <float 2.0, float 3.0> + ret <2 x float> %div1 + +; CHECK-LABEL: @fdiv2_vec( +; CHECK: fmul fast <2 x float> %x, <float 3.000000e+00, float 3.000000e+00> +} + ; "X/C1 / C2 => X * (1/(C2*C1))" is disabled (for now) is C2/C1 is a denormal ; define float @fdiv3(float %x) { diff --git a/test/Transforms/InstCombine/fdiv.ll b/test/Transforms/InstCombine/fdiv.ll index 1edbc5ecd60b..af6a2401a8fc 100644 --- a/test/Transforms/InstCombine/fdiv.ll +++ b/test/Transforms/InstCombine/fdiv.ll @@ -23,3 +23,29 @@ define float @test3(float %x) nounwind readnone ssp { ; CHECK-LABEL: @test3( ; CHECK-NEXT: fdiv float %x, 0x36A0000000000000 } + +define float @test4(float %x) nounwind readnone ssp { + %div = fdiv fast float %x, 8.0 + ret float %div + +; CHECK-LABEL: @test4( +; CHECK-NEXT: fmul fast float %x, 1.250000e-01 +} + +define float @test5(float %x, float %y, float %z) nounwind readnone ssp { + %div1 = fdiv fast float %x, %y + %div2 = fdiv fast float %div1, %z + ret float %div2 +; CHECK-LABEL: @test5( +; CHECK-NEXT: fmul fast +; CHECK-NEXT: fdiv fast +} + +define float @test6(float %x, float %y, float %z) nounwind readnone ssp { + %div1 = fdiv fast float %x, %y + %div2 = fdiv fast float %z, %div1 + ret float %div2 +; CHECK-LABEL: @test6( +; CHECK-NEXT: fmul fast +; CHECK-NEXT: fdiv fast +} diff --git a/test/Transforms/InstCombine/ffs-1.ll b/test/Transforms/InstCombine/ffs-1.ll index 1dec11da0eb0..c8763dc199a9 100644 --- a/test/Transforms/InstCombine/ffs-1.ll +++ b/test/Transforms/InstCombine/ffs-1.ll @@ -103,7 +103,7 @@ define i32 @test_simplify13(i32 %x) { ; CHECK-LABEL: @test_simplify13( %ret = call i32 @ffs(i32 %x) ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 false) -; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add i32 [[CTTZ]], 1 +; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0 ret i32 %ret @@ -114,7 +114,7 @@ define i32 @test_simplify14(i32 %x) { ; CHECK-LINUX-LABEL: @test_simplify14( %ret = call i32 @ffsl(i32 %x) ; CHECK-LINUX-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 false) -; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add i32 [[CTTZ]], 1 +; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1 ; CHECK-LINUX-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0 ; CHECK-LINUX-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0 ret i32 %ret @@ -125,7 +125,7 @@ define i32 @test_simplify15(i64 %x) { ; CHECK-LINUX-LABEL: @test_simplify15( %ret = call i32 @ffsll(i64 %x) ; CHECK-LINUX-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 false) -; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add i64 [[CTTZ]], 1 +; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1 ; CHECK-LINUX-NEXT: [[TRUNC:%[a-z0-9]+]] = trunc i64 [[INC]] to i32 ; CHECK-LINUX-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i64 %x, 0 ; CHECK-LINUX-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[TRUNC]], i32 0 diff --git a/test/Transforms/InstCombine/float-shrink-compare.ll b/test/Transforms/InstCombine/float-shrink-compare.ll index 26f77a7f702b..e50046790da8 100644 --- a/test/Transforms/InstCombine/float-shrink-compare.ll +++ b/test/Transforms/InstCombine/float-shrink-compare.ll @@ -170,6 +170,58 @@ define i32 @test14(float %x, float %y) nounwind uwtable { ; CHECK-NEXT: fcmp oeq float %truncf, %y } +define i32 @test15(float %x, float %y, float %z) nounwind uwtable { + %1 = fpext float %x to double + %2 = fpext float %y to double + %3 = call double @fmin(double %1, double %2) nounwind + %4 = fpext float %z to double + %5 = fcmp oeq double %3, %4 + %6 = zext i1 %5 to i32 + ret i32 %6 +; CHECK-LABEL: @test15( +; CHECK-NEXT: %fminf = call float @fminf(float %x, float %y) +; CHECK-NEXT: fcmp oeq float %fminf, %z +} + +define i32 @test16(float %x, float %y, float %z) nounwind uwtable { + %1 = fpext float %z to double + %2 = fpext float %x to double + %3 = fpext float %y to double + %4 = call double @fmin(double %2, double %3) nounwind + %5 = fcmp oeq double %1, %4 + %6 = zext i1 %5 to i32 + ret i32 %6 +; CHECK-LABEL: @test16( +; CHECK-NEXT: %fminf = call float @fminf(float %x, float %y) +; CHECK-NEXT: fcmp oeq float %fminf, %z +} + +define i32 @test17(float %x, float %y, float %z) nounwind uwtable { + %1 = fpext float %x to double + %2 = fpext float %y to double + %3 = call double @fmax(double %1, double %2) nounwind + %4 = fpext float %z to double + %5 = fcmp oeq double %3, %4 + %6 = zext i1 %5 to i32 + ret i32 %6 +; CHECK-LABEL: @test17( +; CHECK-NEXT: %fmaxf = call float @fmaxf(float %x, float %y) +; CHECK-NEXT: fcmp oeq float %fmaxf, %z +} + +define i32 @test18(float %x, float %y, float %z) nounwind uwtable { + %1 = fpext float %z to double + %2 = fpext float %x to double + %3 = fpext float %y to double + %4 = call double @fmax(double %2, double %3) nounwind + %5 = fcmp oeq double %1, %4 + %6 = zext i1 %5 to i32 + ret i32 %6 +; CHECK-LABEL: @test18( +; CHECK-NEXT: %fmaxf = call float @fmaxf(float %x, float %y) +; CHECK-NEXT: fcmp oeq float %fmaxf, %z +} + declare double @fabs(double) nounwind readnone declare double @ceil(double) nounwind readnone declare double @floor(double) nounwind readnone @@ -177,3 +229,5 @@ declare double @nearbyint(double) nounwind readnone declare double @rint(double) nounwind readnone declare double @round(double) nounwind readnone declare double @trunc(double) nounwind readnone +declare double @fmin(double, double) nounwind readnone +declare double @fmax(double, double) nounwind readnone diff --git a/test/Transforms/InstCombine/fmul.ll b/test/Transforms/InstCombine/fmul.ll index 402ee52e624a..18cbf9da5361 100644 --- a/test/Transforms/InstCombine/fmul.ll +++ b/test/Transforms/InstCombine/fmul.ll @@ -24,10 +24,10 @@ define float @test2(float %x) { define float @test3(float %x, float %y) { %sub1 = fsub float -0.000000e+00, %x %sub2 = fsub float -0.000000e+00, %y - %mul = fmul float %sub1, %sub2 + %mul = fmul fast float %sub1, %sub2 ret float %mul ; CHECK-LABEL: @test3( -; CHECK: fmul float %x, %y +; CHECK: fmul fast float %x, %y } ; (0.0 - X) * (0.0 - Y) => X * Y @@ -93,3 +93,33 @@ for.body: ; preds = %for.cond for.end: ; preds = %for.cond ret void } + +; X * -1.0 => -0.0 - X +define float @test9(float %x) { + %mul = fmul float %x, -1.0 + ret float %mul + +; CHECK-LABEL: @test9( +; CHECK-NOT: fmul +; CHECK: fsub +} + +; PR18532 +define <4 x float> @test10(<4 x float> %x) { + %mul = fmul <4 x float> %x, <float -1.0, float -1.0, float -1.0, float -1.0> + ret <4 x float> %mul + +; CHECK-LABEL: @test10( +; CHECK-NOT: fmul +; CHECK: fsub +} + +define float @test11(float %x, float %y) { + %a = fadd fast float %x, 1.0 + %b = fadd fast float %y, 2.0 + %c = fadd fast float %a, %b + ret float %c +; CHECK-LABEL: @test11( +; CHECK-NOT: fadd float +; CHECK: fadd fast float +} diff --git a/test/Transforms/InstCombine/fpcast.ll b/test/Transforms/InstCombine/fpcast.ll index 05d1b48d5996..9be66fd42c68 100644 --- a/test/Transforms/InstCombine/fpcast.ll +++ b/test/Transforms/InstCombine/fpcast.ll @@ -31,6 +31,15 @@ define half @test4(float %a) { ret half %c } +; CHECK: test4-fast +define half @test4-fast(float %a) { +; CHECK: fptrunc +; CHECK: fsub fast + %b = fsub fast float -0.0, %a + %c = fptrunc float %b to half + ret half %c +} + ; CHECK: test5 define half @test5(float %a, float %b, float %c) { ; CHECK: fcmp ogt diff --git a/test/Transforms/InstCombine/fpextend.ll b/test/Transforms/InstCombine/fpextend.ll index 70e0c62dd70e..8640cd2b6f5c 100644 --- a/test/Transforms/InstCombine/fpextend.ll +++ b/test/Transforms/InstCombine/fpextend.ll @@ -1,3 +1,4 @@ + ; RUN: opt < %s -instcombine -S | not grep fpext @X = external global float @Y = external global float @@ -12,6 +13,18 @@ entry: ret void } +define void @test2() nounwind { +entry: + %tmp = load float* @X, align 4 ; <float> [#uses=1] + %tmp1 = fpext float %tmp to double ; <double> [#uses=1] + %tmp2 = load float* @Y, align 4 ; <float> [#uses=1] + %tmp23 = fpext float %tmp2 to double ; <double> [#uses=1] + %tmp5 = fmul double %tmp1, %tmp23 ; <double> [#uses=1] + %tmp56 = fptrunc double %tmp5 to float ; <float> [#uses=1] + store float %tmp56, float* @X, align 4 + ret void +} + define void @test3() nounwind { entry: %tmp = load float* @X, align 4 ; <float> [#uses=1] @@ -33,4 +46,3 @@ entry: store float %tmp34, float* @X, align 4 ret void } - diff --git a/test/Transforms/InstCombine/fpextend_x86.ll b/test/Transforms/InstCombine/fpextend_x86.ll new file mode 100644 index 000000000000..e012551ebdf4 --- /dev/null +++ b/test/Transforms/InstCombine/fpextend_x86.ll @@ -0,0 +1,57 @@ +; RUN: opt < %s -instcombine -mtriple=x86_64-apple-macosx -S | FileCheck %s +target triple = "x86_64-apple-macosx" + +define double @test1(double %a, double %b) nounwind { + %wa = fpext double %a to x86_fp80 + %wb = fpext double %b to x86_fp80 + %wr = fadd x86_fp80 %wa, %wb + %r = fptrunc x86_fp80 %wr to double + ret double %r +; CHECK: test1 +; CHECK: fadd x86_fp80 +; CHECK: ret +} + +define double @test2(double %a, double %b) nounwind { + %wa = fpext double %a to x86_fp80 + %wb = fpext double %b to x86_fp80 + %wr = fsub x86_fp80 %wa, %wb + %r = fptrunc x86_fp80 %wr to double + ret double %r +; CHECK: test2 +; CHECK: fsub x86_fp80 +; CHECK: ret +} + +define double @test3(double %a, double %b) nounwind { + %wa = fpext double %a to x86_fp80 + %wb = fpext double %b to x86_fp80 + %wr = fmul x86_fp80 %wa, %wb + %r = fptrunc x86_fp80 %wr to double + ret double %r +; CHECK: test3 +; CHECK: fmul x86_fp80 +; CHECK: ret +} + +define double @test4(double %a, half %b) nounwind { + %wa = fpext double %a to x86_fp80 + %wb = fpext half %b to x86_fp80 + %wr = fmul x86_fp80 %wa, %wb + %r = fptrunc x86_fp80 %wr to double + ret double %r +; CHECK: test4 +; CHECK: fmul double +; CHECK: ret +} + +define double @test5(double %a, double %b) nounwind { + %wa = fpext double %a to x86_fp80 + %wb = fpext double %b to x86_fp80 + %wr = fdiv x86_fp80 %wa, %wb + %r = fptrunc x86_fp80 %wr to double + ret double %r +; CHECK: test5 +; CHECK: fdiv x86_fp80 +; CHECK: ret +} diff --git a/test/Transforms/InstCombine/fprintf-1.ll b/test/Transforms/InstCombine/fprintf-1.ll index 3f6a314e3472..6741345839a0 100644 --- a/test/Transforms/InstCombine/fprintf-1.ll +++ b/test/Transforms/InstCombine/fprintf-1.ll @@ -56,18 +56,18 @@ define void @test_simplify4(%FILE* %fp) { ; CHECK-IPRINTF-LABEL: @test_simplify4( %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0 call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, i32 187) -; CHECK-NEXT-IPRINTF: call i32 (%FILE*, i8*, ...)* @fiprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187) +; CHECK-IPRINTF-NEXT: call i32 (%FILE*, i8*, ...)* @fiprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187) ret void -; CHECK-NEXT-IPRINTF: ret void +; CHECK-IPRINTF-NEXT: ret void } define void @test_no_simplify1(%FILE* %fp) { ; CHECK-IPRINTF-LABEL: @test_no_simplify1( %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0 call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, double 1.87) -; CHECK-NEXT-IPRINTF: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00) +; CHECK-IPRINTF-NEXT: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00) ret void -; CHECK-NEXT-IPRINTF: ret void +; CHECK-IPRINTF-NEXT: ret void } define void @test_no_simplify2(%FILE* %fp, double %d) { diff --git a/test/Transforms/InstCombine/gep-addrspace.ll b/test/Transforms/InstCombine/gep-addrspace.ll index 24c355d817e5..29511a3c6677 100644 --- a/test/Transforms/InstCombine/gep-addrspace.ll +++ b/test/Transforms/InstCombine/gep-addrspace.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -instcombine -S +; RUN: opt < %s -instcombine -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-pc-win32" @@ -17,3 +17,18 @@ ST: ret void } +@array = internal addrspace(3) global [256 x float] zeroinitializer, align 4 +@scalar = internal addrspace(3) global float 0.000000e+00, align 4 + +define void @keep_necessary_addrspacecast(i64 %i, float** %out0, float** %out1) { +entry: +; CHECK-LABEL: @keep_necessary_addrspacecast + %0 = getelementptr [256 x float]* addrspacecast ([256 x float] addrspace(3)* @array to [256 x float]*), i64 0, i64 %i +; CHECK: addrspacecast float addrspace(3)* %{{[0-9]+}} to float* + %1 = getelementptr [0 x float]* addrspacecast (float addrspace(3)* @scalar to [0 x float]*), i64 0, i64 %i +; CHECK: addrspacecast float addrspace(3)* %{{[0-9]+}} to float* + store float* %0, float** %out0, align 4 + store float* %1, float** %out1, align 4 + ret void +} + diff --git a/test/Transforms/InstCombine/gepphigep.ll b/test/Transforms/InstCombine/gepphigep.ll new file mode 100644 index 000000000000..9aab609901e2 --- /dev/null +++ b/test/Transforms/InstCombine/gepphigep.ll @@ -0,0 +1,56 @@ +; RUN: opt -instcombine -S < %s | FileCheck %s + +%struct1 = type { %struct2*, i32, i32, i32 } +%struct2 = type { i32, i32 } + +define i32 @test1(%struct1* %dm, i1 %tmp4, i64 %tmp9, i64 %tmp19) { +bb: + %tmp = getelementptr inbounds %struct1* %dm, i64 0, i32 0 + %tmp1 = load %struct2** %tmp, align 8 + br i1 %tmp4, label %bb1, label %bb2 + +bb1: + %tmp10 = getelementptr inbounds %struct2* %tmp1, i64 %tmp9 + %tmp11 = getelementptr inbounds %struct2* %tmp10, i64 0, i32 0 + store i32 0, i32* %tmp11, align 4 + br label %bb3 + +bb2: + %tmp20 = getelementptr inbounds %struct2* %tmp1, i64 %tmp19 + %tmp21 = getelementptr inbounds %struct2* %tmp20, i64 0, i32 0 + store i32 0, i32* %tmp21, align 4 + br label %bb3 + +bb3: + %phi = phi %struct2* [ %tmp10, %bb1 ], [ %tmp20, %bb2 ] + %tmp24 = getelementptr inbounds %struct2* %phi, i64 0, i32 1 + %tmp25 = load i32* %tmp24, align 4 + ret i32 %tmp25 + +; CHECK-LABEL: @test1( +; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp9, i32 0 +; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp19, i32 0 +; CHECK: %[[PHI:[0-9A-Za-z]+]] = phi i64 [ %tmp9, %bb1 ], [ %tmp19, %bb2 ] +; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %[[PHI]], i32 1 + +} + +define i32 @test2(%struct1* %dm, i1 %tmp4, i64 %tmp9, i64 %tmp19) { +bb: + %tmp = getelementptr inbounds %struct1* %dm, i64 0, i32 0 + %tmp1 = load %struct2** %tmp, align 8 + %tmp10 = getelementptr inbounds %struct2* %tmp1, i64 %tmp9 + %tmp11 = getelementptr inbounds %struct2* %tmp10, i64 0, i32 0 + store i32 0, i32* %tmp11, align 4 + %tmp20 = getelementptr inbounds %struct2* %tmp1, i64 %tmp19 + %tmp21 = getelementptr inbounds %struct2* %tmp20, i64 0, i32 0 + store i32 0, i32* %tmp21, align 4 + %tmp24 = getelementptr inbounds %struct2* %tmp10, i64 0, i32 1 + %tmp25 = load i32* %tmp24, align 4 + ret i32 %tmp25 + +; CHECK-LABEL: @test2( +; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp9, i32 0 +; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp19, i32 0 +; CHECK: getelementptr inbounds %struct2* %tmp1, i64 %tmp9, i32 1 +} diff --git a/test/Transforms/InstCombine/getelementptr.ll b/test/Transforms/InstCombine/getelementptr.ll index c29a7dccb8ee..3240c6d2a4d0 100644 --- a/test/Transforms/InstCombine/getelementptr.ll +++ b/test/Transforms/InstCombine/getelementptr.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -instcombine -S | FileCheck %s -target datalayout = "e-p:64:64-p1:16:16-p2:32:32:32" +target datalayout = "e-p:64:64-p1:16:16-p2:32:32:32-p3:64:64:64" %intstruct = type { i32 } %pair = type { i32, i32 } @@ -728,6 +728,20 @@ define i64 @test_gep_bitcast_array_same_size_element([100 x double]* %arr, i64 % ret i64 %x } +; gep should be done in the original address space. +define i64 @test_gep_bitcast_array_same_size_element_addrspacecast([100 x double]* %arr, i64 %N) { +; CHECK-LABEL: @test_gep_bitcast_array_same_size_element_addrspacecast( +; CHECK: getelementptr [100 x double]* %arr, i64 0, i64 %V +; CHECK-NEXT: bitcast double* +; CHECK-NEXT: %t = addrspacecast i64* +; CHECK: load i64 addrspace(3)* %t + %cast = addrspacecast [100 x double]* %arr to i64 addrspace(3)* + %V = mul i64 %N, 8 + %t = getelementptr i64 addrspace(3)* %cast, i64 %V + %x = load i64 addrspace(3)* %t + ret i64 %x +} + ; The element size of the array is different the element size of the pointer define i8 @test_gep_bitcast_array_different_size_element([100 x double]* %arr, i64 %N) { ; CHECK-LABEL: @test_gep_bitcast_array_different_size_element( @@ -789,4 +803,25 @@ define i16 @test41([3 x i32] addrspace(1)* %array) { ; CHECK-NEXT: ret i16 8 } +define i32 addrspace(1)* @ascast_0_gep(i32* %p) nounwind { +; CHECK-LABEL: @ascast_0_gep( +; CHECK-NOT: getelementptr +; CHECK: ret + %gep = getelementptr i32* %p, i32 0 + %x = addrspacecast i32* %gep to i32 addrspace(1)* + ret i32 addrspace(1)* %x +} + +; Do not merge the GEP and the addrspacecast, because it would undo the +; addrspacecast canonicalization. +define i32 addrspace(1)* @ascast_0_0_gep([128 x i32]* %p) nounwind { +; CHECK-LABEL: @ascast_0_0_gep( +; CHECK-NEXT: getelementptr [128 x i32] +; CHECK-NEXT: addrspacecast i32* +; CHECK-NEXT: ret i32 addrspace(1)* + %gep = getelementptr [128 x i32]* %p, i32 0, i32 0 + %x = addrspacecast i32* %gep to i32 addrspace(1)* + ret i32 addrspace(1)* %x +} + ; CHECK: attributes [[NUW]] = { nounwind } diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll index 12a4744cc0fe..26e144f93a57 100644 --- a/test/Transforms/InstCombine/icmp.ll +++ b/test/Transforms/InstCombine/icmp.ll @@ -1,7 +1,6 @@ ; RUN: opt < %s -instcombine -S | FileCheck %s -target datalayout = -"e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target datalayout = "e-p:64:64:64-p1:16:16:16-p2:32:32:32-p3:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" define i32 @test1(i32 %X) { entry: @@ -166,6 +165,14 @@ define i1 @test17(i32 %x) nounwind { ; CHECK-NEXT: %cmp = icmp ne i32 %x, 3 } +define i1 @test17a(i32 %x) nounwind { + %shl = shl i32 1, %x + %and = and i32 %shl, 7 + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +; CHECK-LABEL: @test17a( +; CHECK-NEXT: %cmp = icmp ugt i32 %x, 2 +} define i1 @test18(i32 %x) nounwind { %sh = lshr i32 8, %x @@ -194,6 +201,15 @@ define i1 @test20(i32 %x) nounwind { ; CHECK-NEXT: %cmp = icmp eq i32 %x, 3 } +define i1 @test20a(i32 %x) nounwind { + %shl = shl i32 1, %x + %and = and i32 %shl, 7 + %cmp = icmp ne i32 %and, 0 + ret i1 %cmp +; CHECK-LABEL: @test20a( +; CHECK-NEXT: %cmp = icmp ult i32 %x, 3 +} + define i1 @test21(i8 %x, i8 %y) { ; CHECK-LABEL: @test21( ; CHECK-NOT: or i8 @@ -657,6 +673,49 @@ define i1 @test60_as1(i8 addrspace(1)* %foo, i64 %i, i64 %j) { ; CHECK-NEXT: ret i1 } +; Same as test60, but look through an addrspacecast instead of a +; bitcast. This uses the same sized addrspace. +define i1 @test60_addrspacecast(i8* %foo, i64 %i, i64 %j) { + %bit = addrspacecast i8* %foo to i32 addrspace(3)* + %gep1 = getelementptr inbounds i32 addrspace(3)* %bit, i64 %i + %gep2 = getelementptr inbounds i8* %foo, i64 %j + %cast1 = addrspacecast i32 addrspace(3)* %gep1 to i8* + %cmp = icmp ult i8* %cast1, %gep2 + ret i1 %cmp +; CHECK-LABEL: @test60_addrspacecast( +; CHECK-NEXT: %gep1.idx = shl nuw i64 %i, 2 +; CHECK-NEXT: icmp slt i64 %gep1.idx, %j +; CHECK-NEXT: ret i1 +} + +define i1 @test60_addrspacecast_smaller(i8* %foo, i16 %i, i64 %j) { + %bit = addrspacecast i8* %foo to i32 addrspace(1)* + %gep1 = getelementptr inbounds i32 addrspace(1)* %bit, i16 %i + %gep2 = getelementptr inbounds i8* %foo, i64 %j + %cast1 = addrspacecast i32 addrspace(1)* %gep1 to i8* + %cmp = icmp ult i8* %cast1, %gep2 + ret i1 %cmp +; CHECK-LABEL: @test60_addrspacecast_smaller( +; CHECK-NEXT: %gep1.idx = shl nuw i16 %i, 2 +; CHECK-NEXT: trunc i64 %j to i16 +; CHECK-NEXT: icmp sgt i16 %1, %gep1.idx +; CHECK-NEXT: ret i1 +} + +define i1 @test60_addrspacecast_larger(i8 addrspace(1)* %foo, i32 %i, i16 %j) { + %bit = addrspacecast i8 addrspace(1)* %foo to i32 addrspace(2)* + %gep1 = getelementptr inbounds i32 addrspace(2)* %bit, i32 %i + %gep2 = getelementptr inbounds i8 addrspace(1)* %foo, i16 %j + %cast1 = addrspacecast i32 addrspace(2)* %gep1 to i8 addrspace(1)* + %cmp = icmp ult i8 addrspace(1)* %cast1, %gep2 + ret i1 %cmp +; CHECK-LABEL: @test60_addrspacecast_larger( +; CHECK-NEXT: %gep1.idx = shl nuw i32 %i, 2 +; CHECK-NEXT: trunc i32 %gep1.idx to i16 +; CHECK-NEXT: icmp slt i16 %1, %j +; CHECK-NEXT: ret i1 +} + define i1 @test61(i8* %foo, i64 %i, i64 %j) { %bit = bitcast i8* %foo to i32* %gep1 = getelementptr i32* %bit, i64 %i @@ -1356,3 +1415,12 @@ define i1 @icmp_ashr_ashr_ne(i32 %a, i32 %b) nounwind { %z = icmp ne i32 %x, %y ret i1 %z } + +; CHECK-LABEL: @icmp_neg_cst_slt +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %a, 10 +; CHECK-NEXT: ret i1 [[CMP]] +define i1 @icmp_neg_cst_slt(i32 %a) { + %1 = sub nsw i32 0, %a + %2 = icmp slt i32 %1, -10 + ret i1 %2 +} diff --git a/test/Transforms/InstCombine/insert-extract-shuffle.ll b/test/Transforms/InstCombine/insert-extract-shuffle.ll new file mode 100644 index 000000000000..8929c82def7b --- /dev/null +++ b/test/Transforms/InstCombine/insert-extract-shuffle.ll @@ -0,0 +1,37 @@ +; RUN: opt -S -instcombine %s | FileCheck %s + +define <1 x i8> @test1(<8 x i8> %in) { +; CHECK-LABEL: @test1 +; CHECK: shufflevector <8 x i8> %in, <8 x i8> undef, <1 x i32> <i32 5> + %val = extractelement <8 x i8> %in, i32 5 + %vec = insertelement <1 x i8> undef, i8 %val, i32 0 + ret <1 x i8> %vec +} + +define <4 x i16> @test2(<8 x i16> %in, <8 x i16> %in2) { +; CHECK-LABEL: @test2 +; CHECK: shufflevector <8 x i16> %in2, <8 x i16> %in, <4 x i32> <i32 11, i32 9, i32 0, i32 10> + %elt0 = extractelement <8 x i16> %in, i32 3 + %elt1 = extractelement <8 x i16> %in, i32 1 + %elt2 = extractelement <8 x i16> %in2, i32 0 + %elt3 = extractelement <8 x i16> %in, i32 2 + + %vec.0 = insertelement <4 x i16> undef, i16 %elt0, i32 0 + %vec.1 = insertelement <4 x i16> %vec.0, i16 %elt1, i32 1 + %vec.2 = insertelement <4 x i16> %vec.1, i16 %elt2, i32 2 + %vec.3 = insertelement <4 x i16> %vec.2, i16 %elt3, i32 3 + + ret <4 x i16> %vec.3 +} + +define <2 x i64> @test_vcopyq_lane_p64(<2 x i64> %a, <1 x i64> %b) #0 { +; CHECK-LABEL: @test_vcopyq_lane_p64 +; CHECK: extractelement +; CHECK: insertelement +; CHECK-NOT: shufflevector +entry: + %elt = extractelement <1 x i64> %b, i32 0 + %res = insertelement <2 x i64> %a, i64 %elt, i32 1 + ret <2 x i64> %res +} + diff --git a/test/Transforms/InstCombine/intrinsics.ll b/test/Transforms/InstCombine/intrinsics.ll index 91c44704ce78..9b58d9386f58 100644 --- a/test/Transforms/InstCombine/intrinsics.ll +++ b/test/Transforms/InstCombine/intrinsics.ll @@ -3,6 +3,7 @@ %overflow.result = type {i8, i1} declare %overflow.result @llvm.uadd.with.overflow.i8(i8, i8) +declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) declare %overflow.result @llvm.umul.with.overflow.i8(i8, i8) declare double @llvm.powi.f64(double, i32) nounwind readonly declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone @@ -89,6 +90,18 @@ define i8 @uaddtest7(i8 %A, i8 %B) { ; CHECK-NEXT: ret i8 %z } +; PR20194 +define { i32, i1 } @saddtest1(i8 %a, i8 %b) { + %A = sext i8 %a to i32 + %B = sext i8 %b to i32 + %x = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %A, i32 %B) + ret { i32, i1 } %x +; CHECK-LABEL: @saddtest1 +; CHECK: %x = add nsw i32 %A, %B +; CHECK-NEXT: %1 = insertvalue { i32, i1 } { i32 undef, i1 false }, i32 %x, 0 +; CHECK-NEXT: ret { i32, i1 } %1 +} + define i8 @umultest1(i8 %A, i1* %overflowPtr) { %x = call %overflow.result @llvm.umul.with.overflow.i8(i8 0, i8 %A) diff --git a/test/Transforms/InstCombine/load-addrspace-cast.ll b/test/Transforms/InstCombine/load-addrspace-cast.ll new file mode 100644 index 000000000000..fd6339cc9262 --- /dev/null +++ b/test/Transforms/InstCombine/load-addrspace-cast.ll @@ -0,0 +1,12 @@ +; RUN: opt -instcombine -S < %s | FileCheck %s +target datalayout = "e-p:64:64:64-n8:16:32:64" + +define i32* @pointer_to_addrspace_pointer(i32 addrspace(1)** %x) nounwind { +; CHECK-LABEL: @pointer_to_addrspace_pointer( +; CHECK: load +; CHECK: addrspacecast + %y = bitcast i32 addrspace(1)** %x to i32** + %z = load i32** %y + ret i32* %z +} + diff --git a/test/Transforms/InstCombine/load.ll b/test/Transforms/InstCombine/load.ll index d11e08e10de9..c8ce70a5c03a 100644 --- a/test/Transforms/InstCombine/load.ll +++ b/test/Transforms/InstCombine/load.ll @@ -1,6 +1,7 @@ +; RUN: opt -instcombine -S < %s | FileCheck %s + ; This test makes sure that these instructions are properly eliminated. -; -; RUN: opt < %s -instcombine -S | not grep load + @X = constant i32 42 ; <i32*> [#uses=2] @X2 = constant i32 47 ; <i32*> [#uses=1] @@ -10,47 +11,63 @@ @GLOBAL = internal constant [4 x i32] zeroinitializer +; CHECK-LABEL: @test1( +; CHECK-NOT: load define i32 @test1() { %B = load i32* @X ; <i32> [#uses=1] ret i32 %B } +; CHECK-LABEL: @test2( +; CHECK-NOT: load define float @test2() { %A = getelementptr [2 x { i32, float }]* @Y, i64 0, i64 1, i32 1 ; <float*> [#uses=1] %B = load float* %A ; <float> [#uses=1] ret float %B } +; CHECK-LABEL: @test3( +; CHECK-NOT: load define i32 @test3() { %A = getelementptr [2 x { i32, float }]* @Y, i64 0, i64 0, i32 0 ; <i32*> [#uses=1] %B = load i32* %A ; <i32> [#uses=1] ret i32 %B } +; CHECK-LABEL: @test4( +; CHECK-NOT: load define i32 @test4() { %A = getelementptr [2 x { i32, float }]* @Z, i64 0, i64 1, i32 0 ; <i32*> [#uses=1] %B = load i32* %A ; <i32> [#uses=1] ret i32 %B } +; CHECK-LABEL: @test5( +; CHECK-NOT: load define i32 @test5(i1 %C) { %Y = select i1 %C, i32* @X, i32* @X2 ; <i32*> [#uses=1] %Z = load i32* %Y ; <i32> [#uses=1] ret i32 %Z } +; CHECK-LABEL: @test7( +; CHECK-NOT: load define i32 @test7(i32 %X) { %V = getelementptr i32* null, i32 %X ; <i32*> [#uses=1] %R = load i32* %V ; <i32> [#uses=1] ret i32 %R } +; CHECK-LABEL: @test8( +; CHECK-NOT: load define i32 @test8(i32* %P) { store i32 1, i32* %P %X = load i32* %P ; <i32> [#uses=1] ret i32 %X } +; CHECK-LABEL: @test9( +; CHECK-NOT: load define i32 @test9(i32* %P) { %X = load i32* %P ; <i32> [#uses=1] %Y = load i32* %P ; <i32> [#uses=1] @@ -58,6 +75,8 @@ define i32 @test9(i32* %P) { ret i32 %Z } +; CHECK-LABEL: @test10( +; CHECK-NOT: load define i32 @test10(i1 %C.upgrd.1, i32* %P, i32* %Q) { br i1 %C.upgrd.1, label %T, label %F T: ; preds = %0 @@ -72,6 +91,8 @@ C: ; preds = %F, %T ret i32 %V } +; CHECK-LABEL: @test11( +; CHECK-NOT: load define double @test11(double* %p) { %t0 = getelementptr double* %p, i32 1 store double 2.0, double* %t0 @@ -80,19 +101,20 @@ define double @test11(double* %p) { ret double %x } +; CHECK-LABEL: @test12( +; CHECK-NOT: load define i32 @test12(i32* %P) { - %A = alloca i32 - store i32 123, i32* %A - ; Cast the result of the load not the source - %Q = bitcast i32* %A to i32* - %V = load i32* %Q - ret i32 %V + %A = alloca i32 + store i32 123, i32* %A + ; Cast the result of the load not the source + %Q = bitcast i32* %A to i32* + %V = load i32* %Q + ret i32 %V } +; CHECK-LABEL: @test13( +; CHECK-NOT: load define <16 x i8> @test13(<2 x i64> %x) { -entry: - %tmp = load <16 x i8> * bitcast ([4 x i32]* @GLOBAL to <16 x i8>*) - ret <16 x i8> %tmp + %tmp = load <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*) + ret <16 x i8> %tmp } - - diff --git a/test/Transforms/InstCombine/loadstore-alignment.ll b/test/Transforms/InstCombine/loadstore-alignment.ll index 2263cb20ec5e..e90bdb7cdd99 100644 --- a/test/Transforms/InstCombine/loadstore-alignment.ll +++ b/test/Transforms/InstCombine/loadstore-alignment.ll @@ -1,67 +1,117 @@ -; RUN: opt < %s -instcombine -S | grep ", align 16" | count 14 -target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" +; RUN: opt -instcombine -S < %s | FileCheck %s +target datalayout = "E-p:64:64:64-p1:64:64:64-p2:32:32:32-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" @x = external global <2 x i64>, align 16 @xx = external global [13 x <2 x i64>], align 16 +@x.as2 = external addrspace(2) global <2 x i64>, align 16 + +; CHECK-LABEL: @static_hem( +; CHECK: , align 16 define <2 x i64> @static_hem() { - %t = getelementptr <2 x i64>* @x, i32 7 - %tmp1 = load <2 x i64>* %t, align 1 - ret <2 x i64> %tmp1 + %t = getelementptr <2 x i64>* @x, i32 7 + %tmp1 = load <2 x i64>* %t, align 1 + ret <2 x i64> %tmp1 +} + +; CHECK-LABEL: @static_hem_addrspacecast( +; CHECK: , align 16 +define <2 x i64> @static_hem_addrspacecast() { + %t = getelementptr <2 x i64>* @x, i32 7 + %t.asc = addrspacecast <2 x i64>* %t to <2 x i64> addrspace(1)* + %tmp1 = load <2 x i64> addrspace(1)* %t.asc, align 1 + ret <2 x i64> %tmp1 +} + +; CHECK-LABEL: @static_hem_addrspacecast_smaller_ptr( +; CHECK: , align 16 +define <2 x i64> @static_hem_addrspacecast_smaller_ptr() { + %t = getelementptr <2 x i64>* @x, i32 7 + %t.asc = addrspacecast <2 x i64>* %t to <2 x i64> addrspace(2)* + %tmp1 = load <2 x i64> addrspace(2)* %t.asc, align 1 + ret <2 x i64> %tmp1 +} + +; CHECK-LABEL: @static_hem_addrspacecast_larger_ptr( +; CHECK: , align 16 +define <2 x i64> @static_hem_addrspacecast_larger_ptr() { + %t = getelementptr <2 x i64> addrspace(2)* @x.as2, i32 7 + %t.asc = addrspacecast <2 x i64> addrspace(2)* %t to <2 x i64> addrspace(1)* + %tmp1 = load <2 x i64> addrspace(1)* %t.asc, align 1 + ret <2 x i64> %tmp1 } +; CHECK-LABEL: @hem( +; CHECK: , align 16 define <2 x i64> @hem(i32 %i) { - %t = getelementptr <2 x i64>* @x, i32 %i - %tmp1 = load <2 x i64>* %t, align 1 - ret <2 x i64> %tmp1 + %t = getelementptr <2 x i64>* @x, i32 %i + %tmp1 = load <2 x i64>* %t, align 1 + ret <2 x i64> %tmp1 } +; CHECK-LABEL: @hem_2d( +; CHECK: , align 16 define <2 x i64> @hem_2d(i32 %i, i32 %j) { - %t = getelementptr [13 x <2 x i64>]* @xx, i32 %i, i32 %j - %tmp1 = load <2 x i64>* %t, align 1 - ret <2 x i64> %tmp1 + %t = getelementptr [13 x <2 x i64>]* @xx, i32 %i, i32 %j + %tmp1 = load <2 x i64>* %t, align 1 + ret <2 x i64> %tmp1 } +; CHECK-LABEL: @foo( +; CHECK: , align 16 define <2 x i64> @foo() { - %tmp1 = load <2 x i64>* @x, align 1 - ret <2 x i64> %tmp1 + %tmp1 = load <2 x i64>* @x, align 1 + ret <2 x i64> %tmp1 } +; CHECK-LABEL: @bar( +; CHECK: , align 16 +; CHECK: , align 16 define <2 x i64> @bar() { - %t = alloca <2 x i64> - call void @kip(<2 x i64>* %t) - %tmp1 = load <2 x i64>* %t, align 1 - ret <2 x i64> %tmp1 + %t = alloca <2 x i64> + call void @kip(<2 x i64>* %t) + %tmp1 = load <2 x i64>* %t, align 1 + ret <2 x i64> %tmp1 } +; CHECK-LABEL: @static_hem_store( +; CHECK: , align 16 define void @static_hem_store(<2 x i64> %y) { - %t = getelementptr <2 x i64>* @x, i32 7 - store <2 x i64> %y, <2 x i64>* %t, align 1 - ret void + %t = getelementptr <2 x i64>* @x, i32 7 + store <2 x i64> %y, <2 x i64>* %t, align 1 + ret void } +; CHECK-LABEL: @hem_store( +; CHECK: , align 16 define void @hem_store(i32 %i, <2 x i64> %y) { - %t = getelementptr <2 x i64>* @x, i32 %i - store <2 x i64> %y, <2 x i64>* %t, align 1 - ret void + %t = getelementptr <2 x i64>* @x, i32 %i + store <2 x i64> %y, <2 x i64>* %t, align 1 + ret void } +; CHECK-LABEL: @hem_2d_store( +; CHECK: , align 16 define void @hem_2d_store(i32 %i, i32 %j, <2 x i64> %y) { - %t = getelementptr [13 x <2 x i64>]* @xx, i32 %i, i32 %j - store <2 x i64> %y, <2 x i64>* %t, align 1 - ret void + %t = getelementptr [13 x <2 x i64>]* @xx, i32 %i, i32 %j + store <2 x i64> %y, <2 x i64>* %t, align 1 + ret void } +; CHECK-LABEL: @foo_store( +; CHECK: , align 16 define void @foo_store(<2 x i64> %y) { - store <2 x i64> %y, <2 x i64>* @x, align 1 - ret void + store <2 x i64> %y, <2 x i64>* @x, align 1 + ret void } +; CHECK-LABEL: @bar_store( +; CHECK: , align 16 define void @bar_store(<2 x i64> %y) { - %t = alloca <2 x i64> - call void @kip(<2 x i64>* %t) - store <2 x i64> %y, <2 x i64>* %t, align 1 - ret void + %t = alloca <2 x i64> + call void @kip(<2 x i64>* %t) + store <2 x i64> %y, <2 x i64>* %t, align 1 + ret void } declare void @kip(<2 x i64>* %t) diff --git a/test/Transforms/InstCombine/memcpy-from-global.ll b/test/Transforms/InstCombine/memcpy-from-global.ll index 58793ab431d1..3bc1d36f486d 100644 --- a/test/Transforms/InstCombine/memcpy-from-global.ll +++ b/test/Transforms/InstCombine/memcpy-from-global.ll @@ -7,11 +7,11 @@ entry: %lookupTable = alloca [128 x float], align 16 ; <[128 x float]*> [#uses=5] %lookupTable1 = bitcast [128 x float]* %lookupTable to i8* ; <i8*> [#uses=1] call void @llvm.memcpy.p0i8.p0i8.i64(i8* %lookupTable1, i8* bitcast ([128 x float]* @C.0.1248 to i8*), i64 512, i32 16, i1 false) - + ; CHECK-LABEL: @test1( ; CHECK-NOT: alloca ; CHECK-NOT: call{{.*}}@llvm.memcpy - + %tmp3 = shl i32 %hash, 2 ; <i32> [#uses=1] %tmp5 = and i32 %tmp3, 124 ; <i32> [#uses=4] %tmp753 = getelementptr [128 x float]* %lookupTable, i32 0, i32 %tmp5 ; <float*> [#uses=1] @@ -37,6 +37,9 @@ entry: } declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind +declare void @llvm.memcpy.p1i8.p0i8.i64(i8 addrspace(1)* nocapture, i8* nocapture, i64, i32, i1) nounwind +declare void @llvm.memcpy.p0i8.p1i8.i64(i8* nocapture, i8 addrspace(1)* nocapture, i64, i32, i1) nounwind +declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i32, i1) nounwind %T = type { i8, [123 x i8] } %U = type { i32, i32, i32, i32, i32 } @@ -64,7 +67,31 @@ define void @test2() { ret void } +define void @test2_addrspacecast() { + %A = alloca %T + %B = alloca %T + %a = addrspacecast %T* %A to i8 addrspace(1)* + %b = addrspacecast %T* %B to i8 addrspace(1)* + +; CHECK-LABEL: @test2_addrspacecast( + +; %A alloca is deleted +; This doesn't exactly match what test2 does, because folding the type +; cast into the alloca doesn't work for the addrspacecast yet. +; CHECK-NEXT: alloca [124 x i8] +; CHECK-NEXT: getelementptr +; CHECK-NEXT: addrspacecast + +; use @G instead of %A +; CHECK-NEXT: call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* %{{.*}}, + call void @llvm.memcpy.p1i8.p0i8.i64(i8 addrspace(1)* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* %b, i8 addrspace(1)* %a, i64 124, i32 4, i1 false) + call void @bar_as1(i8 addrspace(1)* %b) + ret void +} + declare void @bar(i8*) +declare void @bar_as1(i8 addrspace(1)*) ;; Should be able to eliminate the alloca. @@ -78,11 +105,22 @@ define void @test3() { ret void } +define void @test3_addrspacecast() { + %A = alloca %T + %a = bitcast %T* %A to i8* + call void @llvm.memcpy.p0i8.p1i8.i64(i8* %a, i8 addrspace(1)* addrspacecast (%T* @G to i8 addrspace(1)*), i64 124, i32 4, i1 false) + call void @bar(i8* %a) readonly +; CHECK-LABEL: @test3_addrspacecast( +; CHECK-NEXT: call void @bar(i8* getelementptr inbounds (%T* @G, i64 0, i32 0)) + ret void +} + + define void @test4() { %A = alloca %T %a = bitcast %T* %A to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false) - call void @baz(i8* byval %a) + call void @baz(i8* byval %a) ; CHECK-LABEL: @test4( ; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T* @G, i64 0, i32 0)) ret void @@ -94,7 +132,7 @@ define void @test5() { %a = bitcast %T* %A to i8* call void @llvm.lifetime.start(i64 -1, i8* %a) call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false) - call void @baz(i8* byval %a) + call void @baz(i8* byval %a) ; CHECK-LABEL: @test5( ; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T* @G, i64 0, i32 0)) ret void @@ -135,6 +173,18 @@ define void @test8() { ret void } + +define void @test8_addrspacecast() { + %A = alloca %U, align 16 + %a = bitcast %U* %A to i8* + call void @llvm.memcpy.p0i8.p1i8.i64(i8* %a, i8 addrspace(1)* addrspacecast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 1) to i8 addrspace(1)*), i64 20, i32 4, i1 false) + call void @bar(i8* %a) readonly +; CHECK-LABEL: @test8_addrspacecast( +; CHECK: llvm.memcpy +; CHECK: bar + ret void +} + define void @test9() { %A = alloca %U, align 4 %a = bitcast %U* %A to i8* @@ -144,3 +194,13 @@ define void @test9() { ; CHECK-NEXT: call void @bar(i8* bitcast (%U* getelementptr inbounds ([2 x %U]* @H, i64 0, i64 1) to i8*)) ret void } + +define void @test9_addrspacecast() { + %A = alloca %U, align 4 + %a = bitcast %U* %A to i8* + call void @llvm.memcpy.p0i8.p1i8.i64(i8* %a, i8 addrspace(1)* addrspacecast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 1) to i8 addrspace(1)*), i64 20, i32 4, i1 false) + call void @bar(i8* %a) readonly +; CHECK-LABEL: @test9_addrspacecast( +; CHECK-NEXT: call void @bar(i8* bitcast (%U* getelementptr inbounds ([2 x %U]* @H, i64 0, i64 1) to i8*)) + ret void +} diff --git a/test/Transforms/InstCombine/mul.ll b/test/Transforms/InstCombine/mul.ll index 94fc1183c55a..d19bedc7a10c 100644 --- a/test/Transforms/InstCombine/mul.ll +++ b/test/Transforms/InstCombine/mul.ll @@ -181,3 +181,19 @@ define i32 @test19(i32 %A, i32 %B) { ret i32 %H ; CHECK: ret i32 0 } + +define <2 x i64> @test20(<2 x i64> %A) { +; CHECK-LABEL: @test20( + %B = add <2 x i64> %A, <i64 12, i64 14> + %C = mul <2 x i64> %B, <i64 3, i64 2> + ret <2 x i64> %C +; CHECK: mul <2 x i64> %A, <i64 3, i64 2> +; CHECK: add <2 x i64> %{{.}}, <i64 36, i64 28> +} + +define <2 x i1> @test21(<2 x i1> %A, <2 x i1> %B) { +; CHECK-LABEL: @test21( + %C = mul <2 x i1> %A, %B + ret <2 x i1> %C +; CHECK: %C = and <2 x i1> %A, %B +} diff --git a/test/Transforms/InstCombine/onehot_merge.ll b/test/Transforms/InstCombine/onehot_merge.ll index 51f955c2c248..496d847b5321 100644 --- a/test/Transforms/InstCombine/onehot_merge.ll +++ b/test/Transforms/InstCombine/onehot_merge.ll @@ -16,7 +16,7 @@ bb: ;CHECK: @foo1_and ;CHECK: shl i32 1, %c1 -;CHECK-NEXT: shl i32 1, %c2 +;CHECK-NEXT: lshr i32 -2147483648, %c2 ;CHECK-NEXT: or i32 ;CHECK-NEXT: and i32 ;CHECK-NEXT: icmp ne i32 %1, %0 @@ -24,7 +24,7 @@ bb: define i1 @foo1_and(i32 %k, i32 %c1, i32 %c2) { bb: %tmp = shl i32 1, %c1 - %tmp4 = shl i32 1, %c2 + %tmp4 = lshr i32 -2147483648, %c2 %tmp1 = and i32 %tmp, %k %tmp2 = icmp eq i32 %tmp1, 0 %tmp5 = and i32 %tmp4, %k diff --git a/test/Transforms/InstCombine/overflow-mul.ll b/test/Transforms/InstCombine/overflow-mul.ll new file mode 100644 index 000000000000..cbb2f5f95003 --- /dev/null +++ b/test/Transforms/InstCombine/overflow-mul.ll @@ -0,0 +1,175 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +; return mul(zext x, zext y) > MAX +define i32 @pr4917_1(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4917_1( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 +; CHECK-NOT: zext i32 + %mul64 = mul i64 %l, %r +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y) + %overflow = icmp ugt i64 %mul64, 4294967295 +; CHECK: extractvalue { i32, i1 } [[MUL]], 1 + %retval = zext i1 %overflow to i32 + ret i32 %retval +} + +; return mul(zext x, zext y) >= MAX+1 +define i32 @pr4917_1a(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4917_1a( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 +; CHECK-NOT: zext i32 + %mul64 = mul i64 %l, %r +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y) + %overflow = icmp uge i64 %mul64, 4294967296 +; CHECK: extractvalue { i32, i1 } [[MUL]], 1 + %retval = zext i1 %overflow to i32 + ret i32 %retval +} + +; mul(zext x, zext y) > MAX +; mul(x, y) is used +define i32 @pr4917_2(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4917_2( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 +; CHECK-NOT: zext i32 + %mul64 = mul i64 %l, %r +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y) + %overflow = icmp ugt i64 %mul64, 4294967295 +; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 + %mul32 = trunc i64 %mul64 to i32 +; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 + %retval = select i1 %overflow, i32 %mul32, i32 111 +; CHECK: select i1 [[OVFL]], i32 [[VAL]] + ret i32 %retval +} + +; return mul(zext x, zext y) > MAX +; mul is used in non-truncate +define i64 @pr4917_3(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4917_3( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 + %mul64 = mul i64 %l, %r +; CHECK-NOT: umul.with.overflow.i32 + %overflow = icmp ugt i64 %mul64, 4294967295 + %retval = select i1 %overflow, i64 %mul64, i64 111 + ret i64 %retval +} + +; return mul(zext x, zext y) <= MAX +define i32 @pr4917_4(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4917_4( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 +; CHECK-NOT: zext i32 + %mul64 = mul i64 %l, %r +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y) + %overflow = icmp ule i64 %mul64, 4294967295 +; CHECK: extractvalue { i32, i1 } [[MUL]], 1 +; CHECK: xor + %retval = zext i1 %overflow to i32 + ret i32 %retval +} + +; return mul(zext x, zext y) < MAX+1 +define i32 @pr4917_4a(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4917_4a( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 +; CHECK-NOT: zext i32 + %mul64 = mul i64 %l, %r +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y) + %overflow = icmp ult i64 %mul64, 4294967296 +; CHECK: extractvalue { i32, i1 } [[MUL]], 1 +; CHECK: xor + %retval = zext i1 %overflow to i32 + ret i32 %retval +} + +; operands of mul are of different size +define i32 @pr4917_5(i32 %x, i8 %y) nounwind { +; CHECK-LABEL: @pr4917_5( +entry: + %l = zext i32 %x to i64 + %r = zext i8 %y to i64 +; CHECK: [[Y:%.*]] = zext i8 %y to i32 + %mul64 = mul i64 %l, %r + %overflow = icmp ugt i64 %mul64, 4294967295 + %mul32 = trunc i64 %mul64 to i32 +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 [[Y]]) +; CHECK-DAG: [[VAL:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 +; CHECK-DAG: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 + %retval = select i1 %overflow, i32 %mul32, i32 111 +; CHECK: select i1 [[OVFL]], i32 [[VAL]] + ret i32 %retval +} + +; mul(zext x, zext y) != zext trunc mul +define i32 @pr4918_1(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4918_1( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 + %mul64 = mul i64 %l, %r +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y) + %part32 = trunc i64 %mul64 to i32 + %part64 = zext i32 %part32 to i64 + %overflow = icmp ne i64 %mul64, %part64 +; CHECK: [[OVFL:%.*]] = extractvalue { i32, i1 } [[MUL:%.*]], 1 + %retval = zext i1 %overflow to i32 + ret i32 %retval +} + +; mul(zext x, zext y) == zext trunc mul +define i32 @pr4918_2(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4918_2( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 + %mul64 = mul i64 %l, %r +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y) + %part32 = trunc i64 %mul64 to i32 + %part64 = zext i32 %part32 to i64 + %overflow = icmp eq i64 %mul64, %part64 +; CHECK: extractvalue { i32, i1 } [[MUL]] + %retval = zext i1 %overflow to i32 +; CHECK: xor + ret i32 %retval +} + +; zext trunc mul != mul(zext x, zext y) +define i32 @pr4918_3(i32 %x, i32 %y) nounwind { +; CHECK-LABEL: @pr4918_3( +entry: + %l = zext i32 %x to i64 + %r = zext i32 %y to i64 + %mul64 = mul i64 %l, %r +; CHECK: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %x, i32 %y) + %part32 = trunc i64 %mul64 to i32 + %part64 = zext i32 %part32 to i64 + %overflow = icmp ne i64 %part64, %mul64 +; CHECK: extractvalue { i32, i1 } [[MUL]], 1 + %retval = zext i1 %overflow to i32 + ret i32 %retval +} + +define <4 x i32> @pr20113(<4 x i16> %a, <4 x i16> %b) { +; CHECK-LABEL: @pr20113 +; CHECK-NOT: mul.with.overflow +; CHECK: ret + %vmovl.i.i726 = zext <4 x i16> %a to <4 x i32> + %vmovl.i.i712 = zext <4 x i16> %b to <4 x i32> + %mul.i703 = mul <4 x i32> %vmovl.i.i712, %vmovl.i.i726 + %tmp = icmp sge <4 x i32> %mul.i703, zeroinitializer + %vcgez.i = sext <4 x i1> %tmp to <4 x i32> + ret <4 x i32> %vcgez.i +} diff --git a/test/Transforms/InstCombine/pow-1.ll b/test/Transforms/InstCombine/pow-1.ll index 9f1d073fe760..fb3b7d796160 100644 --- a/test/Transforms/InstCombine/pow-1.ll +++ b/test/Transforms/InstCombine/pow-1.ll @@ -1,6 +1,11 @@ ; Test that the pow library call simplifier works correctly. ; ; RUN: opt < %s -instcombine -S | FileCheck %s +; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefix=CHECK-EXP10 +; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios7.0 | FileCheck %s --check-prefix=CHECK-EXP10 +; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.8 | FileCheck %s --check-prefix=CHECK-NO-EXP10 +; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios6.0 | FileCheck %s --check-prefix=CHECK-NO-EXP10 +; RUN: opt -instcombine -S < %s -mtriple=x86_64-netbsd | FileCheck %s --check-prefix=CHECK-NO-EXP10 ; rdar://7251832 ; NOTE: The readonly attribute on the pow call should be preserved @@ -155,13 +160,33 @@ declare double @llvm.pow.f64(double %Val, double %Power) define double @test_simplify17(double %x) { ; CHECK-LABEL: @test_simplify17( %retval = call double @llvm.pow.f64(double %x, double 0.5) -; CHECK-NEXT: [[SQRT:%[a-z0-9]+]] = call double @sqrt(double %x) [[NUW_RO]] -; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]]) [[NUW_RO]] +; CHECK-NEXT: [[SQRT:%[a-z0-9]+]] = call double @sqrt(double %x) +; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]]) ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq double %x, 0xFFF0000000000000 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]] ret double %retval ; CHECK-NEXT: ret double [[SELECT]] } +; Check pow(10.0, x) -> __exp10(x) on OS X 10.9+ and iOS 7.0+. + +define float @test_simplify18(float %x) { +; CHECK-LABEL: @test_simplify18( + %retval = call float @powf(float 10.0, float %x) +; CHECK-EXP10: [[EXP10F:%[_a-z0-9]+]] = call float @__exp10f(float %x) [[NUW_RO:#[0-9]+]] + ret float %retval +; CHECK-EXP10: ret float [[EXP10F]] +; CHECK-NO-EXP10: call float @powf +} + +define double @test_simplify19(double %x) { +; CHECK-LABEL: @test_simplify19( + %retval = call double @pow(double 10.0, double %x) +; CHECK-EXP10: [[EXP10:%[_a-z0-9]+]] = call double @__exp10(double %x) [[NUW_RO]] + ret double %retval +; CHECK-EXP10: ret double [[EXP10]] +; CHECK-NO-EXP10: call double @pow +} + ; CHECK: attributes [[NUW_RO]] = { nounwind readonly } diff --git a/test/Transforms/InstCombine/pr19420.ll b/test/Transforms/InstCombine/pr19420.ll new file mode 100644 index 000000000000..23fa0a409745 --- /dev/null +++ b/test/Transforms/InstCombine/pr19420.ll @@ -0,0 +1,67 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL +; CHECK: mul <4 x i32> %in, <i32 0, i32 -32, i32 0, i32 -32> +; CHECK-NEXT: ret +define <4 x i32> @test_FoldShiftByConstant_CreateSHL(<4 x i32> %in) { + %mul.i = mul <4 x i32> %in, <i32 0, i32 -1, i32 0, i32 -1> + %vshl_n = shl <4 x i32> %mul.i, <i32 5, i32 5, i32 5, i32 5> + ret <4 x i32> %vshl_n +} + +; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL2 +; CHECK: mul <8 x i16> %in, <i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32> +; CHECK-NEXT: ret +define <8 x i16> @test_FoldShiftByConstant_CreateSHL2(<8 x i16> %in) { + %mul.i = mul <8 x i16> %in, <i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1> + %vshl_n = shl <8 x i16> %mul.i, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> + ret <8 x i16> %vshl_n +} + +; CHECK-LABEL: @test_FoldShiftByConstant_CreateAnd +; CHECK: mul <16 x i8> %in0, <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33> +; CHECK-NEXT: and <16 x i8> %vsra_n2, <i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32> +; CHECK-NEXT: ret +define <16 x i8> @test_FoldShiftByConstant_CreateAnd(<16 x i8> %in0) { + %vsra_n = ashr <16 x i8> %in0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> + %tmp = add <16 x i8> %in0, %vsra_n + %vshl_n = shl <16 x i8> %tmp, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> + ret <16 x i8> %vshl_n +} + + +define i32 @bar(i32 %x, i32 %y) { + %a = lshr i32 %x, 4 + %b = add i32 %a, %y + %c = shl i32 %b, 4 + ret i32 %c +} + +define <2 x i32> @bar_v2i32(<2 x i32> %x, <2 x i32> %y) { + %a = lshr <2 x i32> %x, <i32 5, i32 5> + %b = add <2 x i32> %a, %y + %c = shl <2 x i32> %b, <i32 5, i32 5> + ret <2 x i32> %c +} + + + + +define i32 @foo(i32 %x, i32 %y) { + %a = lshr i32 %x, 4 + %b = and i32 %a, 8 + %c = add i32 %b, %y + %d = shl i32 %c, 4 + ret i32 %d +} + +define <2 x i32> @foo_v2i32(<2 x i32> %x, <2 x i32> %y) { + %a = lshr <2 x i32> %x, <i32 4, i32 4> + %b = and <2 x i32> %a, <i32 8, i32 8> + %c = add <2 x i32> %b, %y + %d = shl <2 x i32> %c, <i32 4, i32 4> + ret <2 x i32> %d +} + + + diff --git a/test/Transforms/InstCombine/pr20059.ll b/test/Transforms/InstCombine/pr20059.ll new file mode 100644 index 000000000000..0ef315936ff2 --- /dev/null +++ b/test/Transforms/InstCombine/pr20059.ll @@ -0,0 +1,16 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +; In PR20059 ( http://llvm.org/pr20059 ), shufflevector operations are reordered/removed +; for an srem operation. This is not a valid optimization because it may cause a trap +; on div-by-zero. + +; CHECK-LABEL: @do_not_reorder +; CHECK: %splat1 = shufflevector <4 x i32> %p1, <4 x i32> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: %splat2 = shufflevector <4 x i32> %p2, <4 x i32> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: %retval = srem <4 x i32> %splat1, %splat2 +define <4 x i32> @do_not_reorder(<4 x i32> %p1, <4 x i32> %p2) { + %splat1 = shufflevector <4 x i32> %p1, <4 x i32> undef, <4 x i32> zeroinitializer + %splat2 = shufflevector <4 x i32> %p2, <4 x i32> undef, <4 x i32> zeroinitializer + %retval = srem <4 x i32> %splat1, %splat2 + ret <4 x i32> %retval +} diff --git a/test/Transforms/InstCombine/pr20079.ll b/test/Transforms/InstCombine/pr20079.ll new file mode 100644 index 000000000000..ce9c4deb06a0 --- /dev/null +++ b/test/Transforms/InstCombine/pr20079.ll @@ -0,0 +1,9 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s +@b = internal global [1 x i32] zeroinitializer, align 4 +@c = internal global i32 0, align 4 + +; CHECK-LABEL: @fn1 +; CHECK-NEXT: ret i32 0 +define i32 @fn1(i32 %a) { + ret i32 0 +} diff --git a/test/Transforms/InstCombine/printf-1.ll b/test/Transforms/InstCombine/printf-1.ll index c98ddd55df10..483bc7a6b079 100644 --- a/test/Transforms/InstCombine/printf-1.ll +++ b/test/Transforms/InstCombine/printf-1.ll @@ -87,18 +87,18 @@ define void @test_simplify7() { ; CHECK-IPRINTF-LABEL: @test_simplify7( %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0 call i32 (i8*, ...)* @printf(i8* %fmt, i32 187) -; CHECK-NEXT-IPRINTF: call i32 (i8*, ...)* @iprintf(i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187) +; CHECK-IPRINTF-NEXT: call i32 (i8*, ...)* @iprintf(i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187) ret void -; CHECK-NEXT-IPRINTF: ret void +; CHECK-IPRINTF-NEXT: ret void } define void @test_no_simplify1() { ; CHECK-IPRINTF-LABEL: @test_no_simplify1( %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0 call i32 (i8*, ...)* @printf(i8* %fmt, double 1.87) -; CHECK-NEXT-IPRINTF: call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00) +; CHECK-IPRINTF-NEXT: call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00) ret void -; CHECK-NEXT-IPRINTF: ret void +; CHECK-IPRINTF-NEXT: ret void } define void @test_no_simplify2(i8* %fmt, double %d) { diff --git a/test/Transforms/InstCombine/r600-intrinsics.ll b/test/Transforms/InstCombine/r600-intrinsics.ll new file mode 100644 index 000000000000..1db6b0d28bf5 --- /dev/null +++ b/test/Transforms/InstCombine/r600-intrinsics.ll @@ -0,0 +1,47 @@ +; RUN: opt -instcombine -S < %s | FileCheck %s + +declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone +declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone + +; CHECK-LABEL: @test_constant_fold_rcp_f32_1 +; CHECK-NEXT: ret float 1.000000e+00 +define float @test_constant_fold_rcp_f32_1() nounwind { + %val = call float @llvm.AMDGPU.rcp.f32(float 1.0) nounwind readnone + ret float %val +} + +; CHECK-LABEL: @test_constant_fold_rcp_f64_1 +; CHECK-NEXT: ret double 1.000000e+00 +define double @test_constant_fold_rcp_f64_1() nounwind { + %val = call double @llvm.AMDGPU.rcp.f64(double 1.0) nounwind readnone + ret double %val +} + +; CHECK-LABEL: @test_constant_fold_rcp_f32_half +; CHECK-NEXT: ret float 2.000000e+00 +define float @test_constant_fold_rcp_f32_half() nounwind { + %val = call float @llvm.AMDGPU.rcp.f32(float 0.5) nounwind readnone + ret float %val +} + +; CHECK-LABEL: @test_constant_fold_rcp_f64_half +; CHECK-NEXT: ret double 2.000000e+00 +define double @test_constant_fold_rcp_f64_half() nounwind { + %val = call double @llvm.AMDGPU.rcp.f64(double 0.5) nounwind readnone + ret double %val +} + +; CHECK-LABEL: @test_constant_fold_rcp_f32_43 +; CHECK-NEXT: call float @llvm.AMDGPU.rcp.f32(float 4.300000e+01) +define float @test_constant_fold_rcp_f32_43() nounwind { + %val = call float @llvm.AMDGPU.rcp.f32(float 4.300000e+01) nounwind readnone + ret float %val +} + +; CHECK-LABEL: @test_constant_fold_rcp_f64_43 +; CHECK-NEXT: call double @llvm.AMDGPU.rcp.f64(double 4.300000e+01) +define double @test_constant_fold_rcp_f64_43() nounwind { + %val = call double @llvm.AMDGPU.rcp.f64(double 4.300000e+01) nounwind readnone + ret double %val +} + diff --git a/test/Transforms/InstCombine/rem.ll b/test/Transforms/InstCombine/rem.ll index 22fd90bf7a75..0595a67393a6 100644 --- a/test/Transforms/InstCombine/rem.ll +++ b/test/Transforms/InstCombine/rem.ll @@ -127,7 +127,7 @@ define i64 @test14(i64 %x, i32 %y) { ; CHECK-LABEL: @test14( ; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64 -; CHECK-NEXT: [[ADD:%.*]] = add i64 [[ZEXT]], -1 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[ZEXT]], -1 ; CHECK-NEXT: [[AND:%.*]] = and i64 [[ADD]], %x ; CHECK-NEXT: ret i64 [[AND]] %shl = shl i32 1, %y @@ -204,3 +204,12 @@ define i32 @test19(i32 %x, i32 %y) { %E = urem i32 %y, %D ret i32 %E } + +define <2 x i64> @test20(<2 x i64> %X, <2 x i1> %C) { +; CHECK-LABEL: @test20( +; CHECK-NEXT: select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> zeroinitializer +; CHECK-NEXT: ret <2 x i64> + %V = select <2 x i1> %C, <2 x i64> <i64 1, i64 2>, <2 x i64> <i64 8, i64 9> + %R = urem <2 x i64> %V, <i64 2, i64 3> + ret <2 x i64> %R +} diff --git a/test/Transforms/InstCombine/round.ll b/test/Transforms/InstCombine/round.ll new file mode 100644 index 000000000000..ecc62dda36ba --- /dev/null +++ b/test/Transforms/InstCombine/round.ll @@ -0,0 +1,90 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +declare float @llvm.round.f32(float) #0 +declare double @llvm.round.f64(double) #0 + +; CHECK-LABEL: @constant_fold_round_f32_01 +; CHECK-NEXT: ret float 1.000000e+00 +define float @constant_fold_round_f32_01() #0 { + %x = call float @llvm.round.f32(float 1.25) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_round_f32_02 +; CHECK-NEXT: ret float -1.000000e+00 +define float @constant_fold_round_f32_02() #0 { + %x = call float @llvm.round.f32(float -1.25) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_round_f32_03 +; CHECK-NEXT: ret float 2.000000e+00 +define float @constant_fold_round_f32_03() #0 { + %x = call float @llvm.round.f32(float 1.5) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_round_f32_04 +; CHECK-NEXT: ret float -2.000000e+00 +define float @constant_fold_round_f32_04() #0 { + %x = call float @llvm.round.f32(float -1.5) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_round_f32_05 +; CHECK-NEXT: ret float 3.000000e+00 +define float @constant_fold_round_f32_05() #0 { + %x = call float @llvm.round.f32(float 2.75) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_round_f32_06 +; CHECK-NEXT: ret float -3.000000e+00 +define float @constant_fold_round_f32_06() #0 { + %x = call float @llvm.round.f32(float -2.75) #0 + ret float %x +} + +; CHECK-LABEL: @constant_fold_round_f64_01 +; CHECK-NEXT: ret double 1.000000e+00 +define double @constant_fold_round_f64_01() #0 { + %x = call double @llvm.round.f64(double 1.3) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_round_f64_02 +; CHECK-NEXT: ret double -1.000000e+00 +define double @constant_fold_round_f64_02() #0 { + %x = call double @llvm.round.f64(double -1.3) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_round_f64_03 +; CHECK-NEXT: ret double 2.000000e+00 +define double @constant_fold_round_f64_03() #0 { + %x = call double @llvm.round.f64(double 1.5) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_round_f64_04 +; CHECK-NEXT: ret double -2.000000e+00 +define double @constant_fold_round_f64_04() #0 { + %x = call double @llvm.round.f64(double -1.5) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_round_f64_05 +; CHECK-NEXT: ret double 3.000000e+00 +define double @constant_fold_round_f64_05() #0 { + %x = call double @llvm.round.f64(double 2.7) #0 + ret double %x +} + +; CHECK-LABEL: @constant_fold_round_f64_06 +; CHECK-NEXT: ret double -3.000000e+00 +define double @constant_fold_round_f64_06() #0 { + %x = call double @llvm.round.f64(double -2.7) #0 + ret double %x +} + +attributes #0 = { nounwind readnone } diff --git a/test/Transforms/InstCombine/select-2.ll b/test/Transforms/InstCombine/select-2.ll index 5b9deb4515a8..832d958c5f34 100644 --- a/test/Transforms/InstCombine/select-2.ll +++ b/test/Transforms/InstCombine/select-2.ll @@ -19,3 +19,13 @@ define i32 @t2(i32 %c, i32 %x) nounwind { %t3 = select i1 %t1, i32 %t2, i32 %x ret i32 %t3 } + +define float @t3(float %x, float %y) nounwind { + %t1 = fcmp ogt float %x, %y + %t2 = select i1 %t1, float %x, float 1.0 + %t3 = fadd fast float %t2, 1.0 + ret float %t3 +; CHECK-LABEL: @t3( +; CHECK: fadd fast +; CHECK: select +} diff --git a/test/Transforms/InstCombine/select-select.ll b/test/Transforms/InstCombine/select-select.ll new file mode 100644 index 000000000000..65820acf07b8 --- /dev/null +++ b/test/Transforms/InstCombine/select-select.ll @@ -0,0 +1,24 @@ +; RUN: opt -instcombine -S < %s | FileCheck %s + +; CHECK: @foo1 +define float @foo1(float %a) #0 { +; CHECK-NOT: xor + %b = fcmp ogt float %a, 0.000000e+00 + %c = select i1 %b, float %a, float 0.000000e+00 + %d = fcmp olt float %c, 1.000000e+00 + %f = select i1 %d, float %c, float 1.000000e+00 + ret float %f +} + +; CHECK: @foo2 +define float @foo2(float %a) #0 { +; CHECK-NOT: xor + %b = fcmp ogt float %a, 0.000000e+00 + %c = select i1 %b, float %a, float 0.000000e+00 + %d = fcmp olt float %c, 1.000000e+00 + %e = select i1 %b, float %a, float 0.000000e+00 + %f = select i1 %d, float %e, float 1.000000e+00 + ret float %f +} + +attributes #0 = { nounwind readnone ssp uwtable } diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll index 1458bde82124..d625f3b1b33d 100644 --- a/test/Transforms/InstCombine/select.ll +++ b/test/Transforms/InstCombine/select.ll @@ -281,7 +281,7 @@ define i32 @test15i(i32 %X) { ; CHECK-NEXT: %t1 = shl i32 %X, 8 ; CHECK-NEXT: %1 = and i32 %t1, 512 ; CHECK-NEXT: %2 = xor i32 %1, 512 -; CHECK-NEXT: %3 = add i32 %2, 577 +; CHECK-NEXT: %3 = add nuw nsw i32 %2, 577 ; CHECK-NEXT: ret i32 %3 } @@ -294,7 +294,7 @@ define i32 @test15j(i32 %X) { ; CHECK-LABEL: @test15j( ; CHECK-NEXT: %t1 = shl i32 %X, 8 ; CHECK-NEXT: %1 = and i32 %t1, 512 -; CHECK-NEXT: %2 = add i32 %1, 577 +; CHECK-NEXT: %2 = add nuw nsw i32 %1, 577 ; CHECK-NEXT: ret i32 %2 } @@ -521,7 +521,7 @@ define i32 @test35(i32 %x) { ; CHECK-LABEL: @test35( ; CHECK: ashr i32 %x, 31 ; CHECK: and i32 {{.*}}, 40 -; CHECK: add i32 {{.*}}, 60 +; CHECK: add nuw nsw i32 {{.*}}, 60 ; CHECK: ret } @@ -532,7 +532,7 @@ define i32 @test36(i32 %x) { ; CHECK-LABEL: @test36( ; CHECK: ashr i32 %x, 31 ; CHECK: and i32 {{.*}}, -40 -; CHECK: add i32 {{.*}}, 100 +; CHECK: add nsw i32 {{.*}}, 100 ; CHECK: ret } @@ -996,6 +996,111 @@ define <2 x i32> @select_icmp_eq_and_1_0_or_vector_of_2s(i32 %x, <2 x i32> %y) { ret <2 x i32> %select } +; CHECK-LABEL: @select_icmp_and_8_eq_0_or_8( +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %x, 8 +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_and_8_eq_0_or_8(i32 %x) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %x, 8 + %or.x = select i1 %cmp, i32 %or, i32 %x + ret i32 %or.x +} + +; CHECK-LABEL: @select_icmp_and_8_ne_0_xor_8( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, -9 +; CHECK-NEXT: ret i32 [[AND]] +define i32 @select_icmp_and_8_ne_0_xor_8(i32 %x) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %xor = xor i32 %x, 8 + %x.xor = select i1 %cmp, i32 %x, i32 %xor + ret i32 %x.xor +} + +; CHECK-LABEL: @select_icmp_and_8_eq_0_xor_8( +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %x, 8 +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_and_8_eq_0_xor_8(i32 %x) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %xor = xor i32 %x, 8 + %xor.x = select i1 %cmp, i32 %xor, i32 %x + ret i32 %xor.x +} + +; CHECK-LABEL: @select_icmp_and_8_ne_0_and_not_8( +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, -9 +; CHECK-NEXT: ret i32 [[AND]] +define i32 @select_icmp_and_8_ne_0_and_not_8(i32 %x) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %and1 = and i32 %x, -9 + %x.and1 = select i1 %cmp, i32 %x, i32 %and1 + ret i32 %x.and1 +} + +; CHECK-LABEL: @select_icmp_and_8_eq_0_and_not_8( +; CHECK-NEXT: ret i32 %x +define i32 @select_icmp_and_8_eq_0_and_not_8(i32 %x) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %and1 = and i32 %x, -9 + %and1.x = select i1 %cmp, i32 %and1, i32 %x + ret i32 %and1.x +} + +; CHECK-LABEL: @select_icmp_x_and_8_eq_0_y_xor_8( +; CHECK: select i1 %cmp, i64 %y, i64 %xor +define i64 @select_icmp_x_and_8_eq_0_y_xor_8(i32 %x, i64 %y) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %xor = xor i64 %y, 8 + %y.xor = select i1 %cmp, i64 %y, i64 %xor + ret i64 %y.xor +} + +; CHECK-LABEL: @select_icmp_x_and_8_eq_0_y_and_not_8( +; CHECK: select i1 %cmp, i64 %y, i64 %and1 +define i64 @select_icmp_x_and_8_eq_0_y_and_not_8(i32 %x, i64 %y) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %and1 = and i64 %y, -9 + %y.and1 = select i1 %cmp, i64 %y, i64 %and1 + ret i64 %y.and1 +} + +; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_xor_8( +; CHECK: select i1 %cmp, i64 %xor, i64 %y +define i64 @select_icmp_x_and_8_ne_0_y_xor_8(i32 %x, i64 %y) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %xor = xor i64 %y, 8 + %xor.y = select i1 %cmp, i64 %xor, i64 %y + ret i64 %xor.y +} + +; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_and_not_8( +; CHECK: select i1 %cmp, i64 %and1, i64 %y +define i64 @select_icmp_x_and_8_ne_0_y_and_not_8(i32 %x, i64 %y) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %and1 = and i64 %y, -9 + %and1.y = select i1 %cmp, i64 %and1, i64 %y + ret i64 %and1.y +} + +; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_or_8( +; CHECK: xor i64 %1, 8 +; CHECK: or i64 %2, %y +define i64 @select_icmp_x_and_8_ne_0_y_or_8(i32 %x, i64 %y) { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %or = or i64 %y, 8 + %or.y = select i1 %cmp, i64 %or, i64 %y + ret i64 %or.y +} + define i32 @test65(i64 %x) { %1 = and i64 %x, 16 %2 = icmp ne i64 %1, 0 @@ -1031,3 +1136,103 @@ define i32 @test67(i16 %x) { ; CHECK: lshr exact i32 %2, 1 ; CHECK: xor i32 %3, 42 } + +; SMIN(SMIN(X, 11), 92) -> SMIN(X, 11) +define i32 @test68(i32 %x) { +entry: + %cmp = icmp slt i32 11, %x + %cond = select i1 %cmp, i32 11, i32 %x + %cmp3 = icmp slt i32 92, %cond + %retval = select i1 %cmp3, i32 92, i32 %cond + ret i32 %retval +; CHECK-LABEL: @test68( +; CHECK: ret i32 %cond +} + +; MIN(MIN(X, 24), 83) -> MIN(X, 24) +define i32 @test69(i32 %x) { +entry: + %cmp = icmp ult i32 24, %x + %cond = select i1 %cmp, i32 24, i32 %x + %cmp3 = icmp ult i32 83, %cond + %retval = select i1 %cmp3, i32 83, i32 %cond + ret i32 %retval +; CHECK-LABEL: @test69( +; CHECK: ret i32 %cond +} + +; SMAX(SMAX(X, 75), 36) -> SMAX(X, 75) +define i32 @test70(i32 %x) { +entry: + %cmp = icmp slt i32 %x, 75 + %cond = select i1 %cmp, i32 75, i32 %x + %cmp3 = icmp slt i32 %cond, 36 + %retval = select i1 %cmp3, i32 36, i32 %cond + ret i32 %retval +; CHECK-LABEL: @test70( +; CHECK: ret i32 %cond +} + +; MAX(MAX(X, 68), 47) -> MAX(X, 68) +define i32 @test71(i32 %x) { +entry: + %cmp = icmp ult i32 %x, 68 + %cond = select i1 %cmp, i32 68, i32 %x + %cmp3 = icmp ult i32 %cond, 47 + %retval = select i1 %cmp3, i32 47, i32 %cond + ret i32 %retval +; CHECK-LABEL: @test71( +; CHECK: ret i32 %cond +} + +; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11) +define i32 @test72(i32 %x) { + %cmp = icmp sgt i32 %x, 92 + %cond = select i1 %cmp, i32 92, i32 %x + %cmp3 = icmp sgt i32 %cond, 11 + %retval = select i1 %cmp3, i32 11, i32 %cond + ret i32 %retval +; CHECK-LABEL: @test72( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 11 +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 11, i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +; MIN(MIN(X, 83), 24) -> MIN(X, 24) +define i32 @test73(i32 %x) { + %cmp = icmp ugt i32 %x, 83 + %cond = select i1 %cmp, i32 83, i32 %x + %cmp3 = icmp ugt i32 %cond, 24 + %retval = select i1 %cmp3, i32 24, i32 %cond + ret i32 %retval +; CHECK-LABEL: @test73( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %x, 24 +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 24, i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +; SMAX(SMAX(X, 36), 75) -> SMAX(X, 75) +define i32 @test74(i32 %x) { + %cmp = icmp slt i32 %x, 36 + %cond = select i1 %cmp, i32 36, i32 %x + %cmp3 = icmp slt i32 %cond, 75 + %retval = select i1 %cmp3, i32 75, i32 %cond + ret i32 %retval +; CHECK-LABEL: @test74( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 75 +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 75, i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} + +; MAX(MAX(X, 47), 68) -> MAX(X, 68) +define i32 @test75(i32 %x) { + %cmp = icmp ult i32 %x, 47 + %cond = select i1 %cmp, i32 47, i32 %x + %cmp3 = icmp ult i32 %cond, 68 + %retval = select i1 %cmp3, i32 68, i32 %cond + ret i32 %retval +; CHECK-LABEL: @test75( +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %x, 68 +; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 68, i32 %x +; CHECK-NEXT: ret i32 [[SEL]] +} diff --git a/test/Transforms/InstCombine/sext.ll b/test/Transforms/InstCombine/sext.ll index b8dfe2257b18..f04afcc747b8 100644 --- a/test/Transforms/InstCombine/sext.ll +++ b/test/Transforms/InstCombine/sext.ll @@ -145,7 +145,7 @@ define i32 @test13(i32 %x) nounwind { ; CHECK-LABEL: @test13( ; CHECK-NEXT: %and = lshr i32 %x, 3 ; CHECK-NEXT: %1 = and i32 %and, 1 -; CHECK-NEXT: %sext = add i32 %1, -1 +; CHECK-NEXT: %sext = add nsw i32 %1, -1 ; CHECK-NEXT: ret i32 %sext } @@ -157,7 +157,7 @@ define i32 @test14(i16 %x) nounwind { ; CHECK-LABEL: @test14( ; CHECK-NEXT: %and = lshr i16 %x, 4 ; CHECK-NEXT: %1 = and i16 %and, 1 -; CHECK-NEXT: %sext = add i16 %1, -1 +; CHECK-NEXT: %sext = add nsw i16 %1, -1 ; CHECK-NEXT: %ext = sext i16 %sext to i32 ; CHECK-NEXT: ret i32 %ext } diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll index b1082f06ef74..5586bb652783 100644 --- a/test/Transforms/InstCombine/shift.ll +++ b/test/Transforms/InstCombine/shift.ll @@ -36,17 +36,52 @@ define i32 @test4(i8 %A) { define i32 @test5(i32 %A) { ; CHECK-LABEL: @test5( ; CHECK: ret i32 undef - %B = lshr i32 %A, 32 ;; shift all bits out + %B = lshr i32 %A, 32 ;; shift all bits out ret i32 %B } +define <4 x i32> @test5_splat_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5_splat_vector( +; CHECK: ret <4 x i32> undef + %B = lshr <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out + ret <4 x i32> %B +} + +define <4 x i32> @test5_zero_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5_zero_vector( +; CHECK-NEXT: ret <4 x i32> %A + %B = lshr <4 x i32> %A, zeroinitializer + ret <4 x i32> %B +} + +define <4 x i32> @test5_non_splat_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5_non_splat_vector( +; CHECK-NOT: ret <4 x i32> undef + %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> + ret <4 x i32> %B +} + define i32 @test5a(i32 %A) { ; CHECK-LABEL: @test5a( ; CHECK: ret i32 undef - %B = shl i32 %A, 32 ;; shift all bits out + %B = shl i32 %A, 32 ;; shift all bits out ret i32 %B } +define <4 x i32> @test5a_splat_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5a_splat_vector( +; CHECK: ret <4 x i32> undef + %B = shl <4 x i32> %A, <i32 32, i32 32, i32 32, i32 32> ;; shift all bits out + ret <4 x i32> %B +} + +define <4 x i32> @test5a_non_splat_vector(<4 x i32> %A) { +; CHECK-LABEL: @test5a_non_splat_vector( +; CHECK-NOT: ret <4 x i32> undef + %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> + ret <4 x i32> %B +} + define i32 @test5b() { ; CHECK-LABEL: @test5b( ; CHECK: ret i32 -1 @@ -82,7 +117,7 @@ define i32 @test6a(i32 %A) { define i32 @test7(i8 %A) { ; CHECK-LABEL: @test7( ; CHECK-NEXT: ret i32 -1 - %shift.upgrd.3 = zext i8 %A to i32 + %shift.upgrd.3 = zext i8 %A to i32 %B = ashr i32 -1, %shift.upgrd.3 ;; Always equal to -1 ret i32 %B } @@ -232,7 +267,7 @@ define i1 @test16(i32 %X) { ; CHECK-NEXT: and i32 %X, 16 ; CHECK-NEXT: icmp ne i32 ; CHECK-NEXT: ret i1 - %tmp.3 = ashr i32 %X, 4 + %tmp.3 = ashr i32 %X, 4 %tmp.6 = and i32 %tmp.3, 1 %tmp.7 = icmp ne i32 %tmp.6, 0 ret i1 %tmp.7 @@ -344,6 +379,20 @@ define i32 @test25(i32 %tmp.2, i32 %AA) { ret i32 %tmp.6 } +define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) { +; CHECK-LABEL: @test25_vector( +; CHECK: %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17> +; CHECK-NEXT: shl <2 x i32> %tmp.3, <i32 17, i32 17> +; CHECK-NEXT: add <2 x i32> %tmp.51, %AA +; CHECK-NEXT: and <2 x i32> %x2, <i32 -131072, i32 -131072> +; CHECK-NEXT: ret <2 x i32> + %x = lshr <2 x i32> %AA, <i32 17, i32 17> + %tmp.3 = lshr <2 x i32> %tmp.2, <i32 17, i32 17> + %tmp.5 = add <2 x i32> %tmp.3, %x + %tmp.6 = shl <2 x i32> %tmp.5, <i32 17, i32 17> + ret <2 x i32> %tmp.6 +} + ;; handle casts between shifts. define i32 @test26(i32 %A) { ; CHECK-LABEL: @test26( @@ -365,12 +414,12 @@ define i1 @test27(i32 %x) nounwind { %z = trunc i32 %y to i1 ret i1 %z } - + define i8 @test28(i8 %x) { entry: ; CHECK-LABEL: @test28( ; CHECK: icmp slt i8 %x, 0 -; CHECK-NEXT: br i1 +; CHECK-NEXT: br i1 %tmp1 = lshr i8 %x, 7 %cond1 = icmp ne i8 %tmp1, 0 br i1 %cond1, label %bb1, label %bb2 @@ -476,7 +525,7 @@ entry: %ins = or i128 %tmp23, %tmp27 %tmp45 = lshr i128 %ins, 64 ret i128 %tmp45 - + ; CHECK-LABEL: @test36( ; CHECK: %tmp231 = or i128 %B, %A ; CHECK: %ins = and i128 %tmp231, 18446744073709551615 @@ -492,7 +541,7 @@ entry: %tmp45 = lshr i128 %ins, 64 %tmp46 = trunc i128 %tmp45 to i64 ret i64 %tmp46 - + ; CHECK-LABEL: @test37( ; CHECK: %tmp23 = shl nuw nsw i128 %tmp22, 32 ; CHECK: %ins = or i128 %tmp23, %A @@ -780,3 +829,32 @@ bb11: ; preds = %bb8 bb12: ; preds = %bb11, %bb8, %bb ret void } + +define i32 @test64(i32 %a) { +; CHECK-LABEL: @test64( +; CHECK-NEXT: ret i32 undef + %b = ashr i32 %a, 32 ; shift all bits out + ret i32 %b +} + +define <4 x i32> @test64_splat_vector(<4 x i32> %a) { +; CHECK-LABEL: @test64_splat_vector +; CHECK-NEXT: ret <4 x i32> undef + %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out + ret <4 x i32> %b +} + +define <4 x i32> @test64_non_splat_vector(<4 x i32> %a) { +; CHECK-LABEL: @test64_non_splat_vector +; CHECK-NOT: ret <4 x i32> undef + %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out + ret <4 x i32> %b +} + +define <2 x i65> @test_65(<2 x i64> %t) { +; CHECK-LABEL: @test_65 + %a = zext <2 x i64> %t to <2 x i65> + %sext = shl <2 x i65> %a, <i65 33, i65 33> + %b = ashr <2 x i65> %sext, <i65 33, i65 33> + ret <2 x i65> %b +} diff --git a/test/Transforms/InstCombine/sign-test-and-or.ll b/test/Transforms/InstCombine/sign-test-and-or.ll index 95ed9b976ba3..aa23d933b09e 100644 --- a/test/Transforms/InstCombine/sign-test-and-or.ll +++ b/test/Transforms/InstCombine/sign-test-and-or.ll @@ -177,3 +177,41 @@ if.then: if.end: ret void } + +define void @test10(i32 %a) nounwind { + %1 = and i32 %a, 2 + %2 = icmp eq i32 %1, 0 + %3 = icmp ult i32 %a, 4 + %or.cond = and i1 %2, %3 + br i1 %or.cond, label %if.then, label %if.end + +; CHECK-LABEL: @test10( +; CHECK-NEXT: %1 = icmp ult i32 %a, 2 +; CHECK-NEXT: br i1 %1, label %if.then, label %if.end + +if.then: + tail call void @foo() nounwind + ret void + +if.end: + ret void +} + +define void @test11(i32 %a) nounwind { + %1 = and i32 %a, 2 + %2 = icmp ne i32 %1, 0 + %3 = icmp ugt i32 %a, 3 + %or.cond = or i1 %2, %3 + br i1 %or.cond, label %if.then, label %if.end + +; CHECK-LABEL: @test11( +; CHECK-NEXT: %1 = icmp ugt i32 %a, 1 +; CHECK-NEXT: br i1 %1, label %if.then, label %if.end + +if.then: + tail call void @foo() nounwind + ret void + +if.end: + ret void +} diff --git a/test/Transforms/InstCombine/sincospi.ll b/test/Transforms/InstCombine/sincospi.ll index 0d1a6027a00a..739827f1962a 100644 --- a/test/Transforms/InstCombine/sincospi.ll +++ b/test/Transforms/InstCombine/sincospi.ll @@ -1,5 +1,6 @@ ; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefix=CHECK-FLOAT-IN-VEC ; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios7.0 | FileCheck %s +; RUN: opt -instcombine -S < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s ; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.8 | FileCheck %s --check-prefix=CHECK-NO-SINCOS ; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios6.0 | FileCheck %s --check-prefix=CHECK-NO-SINCOS ; RUN: opt -instcombine -S < %s -mtriple=x86_64-none-linux-gnu | FileCheck %s --check-prefix=CHECK-NO-SINCOS @@ -23,12 +24,12 @@ define float @test_instbased_f32() { %res = fadd float %sin, %cos ret float %res ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float* @var32 -; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospi_stretf(float [[VAL]]) +; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]]) ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1 ; CHECK: [[VAL:%[a-z0-9]+]] = load float* @var32 -; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospi_stretf(float [[VAL]]) +; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospif_stret(float [[VAL]]) ; CHECK: extractvalue { float, float } [[SINCOS]], 0 ; CHECK: extractvalue { float, float } [[SINCOS]], 1 @@ -41,11 +42,11 @@ define float @test_constant_f32() { %cos = call float @__cospif(float 1.0) #0 %res = fadd float %sin, %cos ret float %res -; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospi_stretf(float 1.000000e+00) +; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float 1.000000e+00) ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1 -; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospi_stretf(float 1.000000e+00) +; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospif_stret(float 1.000000e+00) ; CHECK: extractvalue { float, float } [[SINCOS]], 0 ; CHECK: extractvalue { float, float } [[SINCOS]], 1 diff --git a/test/Transforms/InstCombine/sprintf-1.ll b/test/Transforms/InstCombine/sprintf-1.ll index 78dd7aa7df47..afa38f35ae83 100644 --- a/test/Transforms/InstCombine/sprintf-1.ll +++ b/test/Transforms/InstCombine/sprintf-1.ll @@ -77,18 +77,18 @@ define void @test_simplify6(i8* %dst) { ; CHECK-IPRINTF-LABEL: @test_simplify6( %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0 call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, i32 187) -; CHECK-NEXT-IPRINTF: call i32 (i8*, i8*, ...)* @siprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187) +; CHECK-IPRINTF-NEXT: call i32 (i8*, i8*, ...)* @siprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187) ret void -; CHECK-NEXT-IPRINTF: ret void +; CHECK-IPRINTF-NEXT: ret void } define void @test_no_simplify1(i8* %dst) { ; CHECK-IPRINTF-LABEL: @test_no_simplify1( %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0 call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, double 1.87) -; CHECK-NEXT-IPRINTF: call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00) +; CHECK-IPRINTF-NEXT: call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00) ret void -; CHECK-NEXT-IPRINTF: ret void +; CHECK-IPRINTF-NEXT: ret void } define void @test_no_simplify2(i8* %dst, i8* %fmt, double %d) { diff --git a/test/Transforms/InstCombine/strchr-1.ll b/test/Transforms/InstCombine/strchr-1.ll index d2c989462156..66b3e2e51c7a 100644 --- a/test/Transforms/InstCombine/strchr-1.ll +++ b/test/Transforms/InstCombine/strchr-1.ll @@ -63,3 +63,16 @@ define void @test_simplify5() { store i8* %dst, i8** @chp ret void } + +; Check transformation strchr(p, 0) -> p + strlen(p) +define void @test_simplify6(i8* %str) { +; CHECK: %strlen = call i32 @strlen(i8* %str) +; CHECK-NOT: call i8* @strchr +; CHECK: %strchr = getelementptr i8* %str, i32 %strlen +; CHECK: store i8* %strchr, i8** @chp, align 4 +; CHECK: ret void + + %dst = call i8* @strchr(i8* %str, i32 0) + store i8* %dst, i8** @chp + ret void +} diff --git a/test/Transforms/InstCombine/strlen-1.ll b/test/Transforms/InstCombine/strlen-1.ll index 4fa5b4fdb62f..4a3caf28a0fe 100644 --- a/test/Transforms/InstCombine/strlen-1.ll +++ b/test/Transforms/InstCombine/strlen-1.ll @@ -5,6 +5,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" @hello = constant [6 x i8] c"hello\00" +@longer = constant [7 x i8] c"longer\00" @null = constant [1 x i8] zeroinitializer @null_hello = constant [7 x i8] c"\00hello\00" @nullstring = constant i8 0 @@ -85,6 +86,17 @@ define i1 @test_simplify8() { ; CHECK-NEXT: ret i1 false } +define i32 @test_simplify9(i1 %x) { +; CHECK-LABEL: @test_simplify9 + %hello = getelementptr [6 x i8]* @hello, i32 0, i32 0 + %longer = getelementptr [7 x i8]* @longer, i32 0, i32 0 + %s = select i1 %x, i8* %hello, i8* %longer + %l = call i32 @strlen(i8* %s) +; CHECK-NEXT: select i1 %x, i32 5, i32 6 + ret i32 %l +; CHECK-NEXT: ret +} + ; Check cases that shouldn't be simplified. define i32 @test_no_simplify1() { diff --git a/test/Transforms/InstCombine/sub.ll b/test/Transforms/InstCombine/sub.ll index 36c523bd7b75..67b7c4996b07 100644 --- a/test/Transforms/InstCombine/sub.ll +++ b/test/Transforms/InstCombine/sub.ll @@ -391,4 +391,76 @@ define i16 @test30_as1(i8 addrspace(1)* %foo, i16 %i, i16 %j) { ret i16 %sub } +define <2 x i64> @test31(<2 x i64> %A) { + %xor = xor <2 x i64> %A, <i64 -1, i64 -1> + %sub = sub <2 x i64> <i64 2, i64 3>, %xor + ret <2 x i64> %sub +; CHECK-LABEL: @test31( +; CHECK-NEXT: %sub = add <2 x i64> %A, <i64 3, i64 4> +; CHECK-NEXT: ret <2 x i64> %sub +} + +define <2 x i64> @test32(<2 x i64> %A) { + %add = add <2 x i64> %A, <i64 -1, i64 -1> + %sub = sub <2 x i64> <i64 2, i64 3>, %add + ret <2 x i64> %sub +; CHECK-LABEL: @test32( +; CHECK-NEXT: %sub = sub <2 x i64> <i64 3, i64 4> +; CHECK-NEXT: ret <2 x i64> %sub +} + +define <2 x i64> @test33(<2 x i1> %A) { + %ext = zext <2 x i1> %A to <2 x i64> + %sub = sub <2 x i64> zeroinitializer, %ext + ret <2 x i64> %sub +; CHECK-LABEL: @test33( +; CHECK-NEXT: %sub = sext <2 x i1> %A to <2 x i64> +; CHECK-NEXT: ret <2 x i64> %sub +} + +define <2 x i64> @test34(<2 x i1> %A) { + %ext = sext <2 x i1> %A to <2 x i64> + %sub = sub <2 x i64> zeroinitializer, %ext + ret <2 x i64> %sub +; CHECK-LABEL: @test34( +; CHECK-NEXT: %sub = zext <2 x i1> %A to <2 x i64> +; CHECK-NEXT: ret <2 x i64> %sub +} +define <2 x i64> @test35(<2 x i64> %A) { + %mul = mul <2 x i64> %A, <i64 3, i64 4> + %sub = sub <2 x i64> %A, %mul + ret <2 x i64> %sub +; CHECK-LABEL: @test35( +; CHECK-NEXT: %sub = mul <2 x i64> %A, <i64 -2, i64 -3> +; CHECK-NEXT: ret <2 x i64> %sub +} + +define <2 x i64> @test36(<2 x i64> %A) { + %shl = shl <2 x i64> %A, <i64 3, i64 4> + %sub = sub <2 x i64> %shl, %A + ret <2 x i64> %sub +; CHECK-LABEL: @test36( +; CHECK-NEXT: %sub = mul <2 x i64> %A, <i64 7, i64 15> +; CHECK-NEXT: ret <2 x i64> %sub +} + +define <2 x i32> @test37(<2 x i32> %A) { + %div = sdiv <2 x i32> %A, <i32 -2147483648, i32 -2147483648> + %sub = sub nsw <2 x i32> zeroinitializer, %div + ret <2 x i32> %sub +; CHECK-LABEL: @test37( +; CHECK-NEXT: [[ICMP:%.*]] = icmp eq <2 x i32> %A, <i32 -2147483648, i32 -2147483648> +; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[ICMP]] to <2 x i32> +; CHECK-NEXT: ret <2 x i32> [[SEXT]] +} + +define i32 @test38(i32 %A) { + %div = sdiv i32 %A, -2147483648 + %sub = sub nsw i32 0, %div + ret i32 %sub +; CHECK-LABEL: @test38( +; CHECK-NEXT: [[ICMP:%.*]] = icmp eq i32 %A, -2147483648 +; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[ICMP]] to i32 +; CHECK-NEXT: ret i32 [[SEXT]] +} diff --git a/test/Transforms/InstCombine/vec_demanded_elts.ll b/test/Transforms/InstCombine/vec_demanded_elts.ll index d12412a92977..41d2b292eeff 100644 --- a/test/Transforms/InstCombine/vec_demanded_elts.ll +++ b/test/Transforms/InstCombine/vec_demanded_elts.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" define i16 @test1(float %f) { entry: @@ -209,4 +210,369 @@ define <4 x float> @test_select(float %f, float %g) { ret <4 x float> %ret } +; We should optimize these two redundant insertqi into one +; CHECK: define <2 x i64> @testInsertTwice(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertTwice(<2 x i64> %v, <2 x i64> %i) { +; CHECK: call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 32) +; CHECK-NOT: insertqi + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 32) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 32) + ret <2 x i64> %2 +} + +; The result of this insert is the second arg, since the top 64 bits of +; the result are undefined, and we copy the bottom 64 bits from the +; second arg +; CHECK: define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) { +; CHECK: ret <2 x i64> %i + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 64, i8 0) + ret <2 x i64> %1 +} + +; Test the several types of ranges and ordering that exist for two insertqi +; CHECK: define <2 x i64> @testInsertContainedRange(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertContainedRange(<2 x i64> %v, <2 x i64> %i) { +; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0) +; CHECK: ret <2 x i64> %[[RES]] + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 16) + ret <2 x i64> %2 +} + +; CHECK: define <2 x i64> @testInsertContainedRange_2(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertContainedRange_2(<2 x i64> %v, <2 x i64> %i) { +; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0) +; CHECK: ret <2 x i64> %[[RES]] + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 16) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0) + ret <2 x i64> %2 +} + +; CHECK: define <2 x i64> @testInsertOverlappingRange(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertOverlappingRange(<2 x i64> %v, <2 x i64> %i) { +; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0) +; CHECK: ret <2 x i64> %[[RES]] + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 16) + ret <2 x i64> %2 +} + +; CHECK: define <2 x i64> @testInsertOverlappingRange_2(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertOverlappingRange_2(<2 x i64> %v, <2 x i64> %i) { +; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0) +; CHECK: ret <2 x i64> %[[RES]] + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 16) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0) + ret <2 x i64> %2 +} + +; CHECK: define <2 x i64> @testInsertAdjacentRange(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertAdjacentRange(<2 x i64> %v, <2 x i64> %i) { +; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0) +; CHECK: ret <2 x i64> %[[RES]] + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 32, i8 0) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32) + ret <2 x i64> %2 +} + +; CHECK: define <2 x i64> @testInsertAdjacentRange_2(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertAdjacentRange_2(<2 x i64> %v, <2 x i64> %i) { +; CHECK: %[[RES:.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 0) +; CHECK: ret <2 x i64> %[[RES]] + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 32) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 32, i8 0) + ret <2 x i64> %2 +} + +; CHECK: define <2 x i64> @testInsertDisjointRange(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertDisjointRange(<2 x i64> %v, <2 x i64> %i) { +; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0) +; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32) + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32) + ret <2 x i64> %2 +} + +; CHECK: define <2 x i64> @testInsertDisjointRange_2(<2 x i64> %v, <2 x i64> %i) +define <2 x i64> @testInsertDisjointRange_2(<2 x i64> %v, <2 x i64> %i) { +; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0) +; CHECK: tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32) + %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 16, i8 0) + %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %i, i8 16, i8 32) + ret <2 x i64> %2 +} + + +; CHECK: declare <2 x i64> @llvm.x86.sse4a.insertqi +declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind + +declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) +define <4 x float> @test_vpermilvar_ps(<4 x float> %v) { +; CHECK-LABEL: @test_vpermilvar_ps( +; CHECK: shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + %a = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %v, <4 x i32> <i32 3, i32 2, i32 1, i32 0>) + ret <4 x float> %a +} + +declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) +define <8 x float> @test_vpermilvar_ps_256(<8 x float> %v) { +; CHECK-LABEL: @test_vpermilvar_ps_256( +; CHECK: shufflevector <8 x float> %v, <8 x float> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> + %a = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %v, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>) + ret <8 x float> %a +} + +declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i32>) +define <2 x double> @test_vpermilvar_pd(<2 x double> %v) { +; CHECK-LABEL: @test_vpermilvar_pd( +; CHECK: shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> <i32 1, i32 0> + %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i32> <i32 2, i32 0>) + ret <2 x double> %a +} + +declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i32>) +define <4 x double> @test_vpermilvar_pd_256(<4 x double> %v) { +; CHECK-LABEL: @test_vpermilvar_pd_256( +; CHECK: shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> + %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> <i32 3, i32 1, i32 2, i32 0>) + ret <4 x double> %a +} + +define <4 x float> @test_vpermilvar_ps_zero(<4 x float> %v) { +; CHECK-LABEL: @test_vpermilvar_ps_zero( +; CHECK: shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer + %a = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %v, <4 x i32> zeroinitializer) + ret <4 x float> %a +} + +define <8 x float> @test_vpermilvar_ps_256_zero(<8 x float> %v) { +; CHECK-LABEL: @test_vpermilvar_ps_256_zero( +; CHECK: shufflevector <8 x float> %v, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4> + %a = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %v, <8 x i32> zeroinitializer) + ret <8 x float> %a +} + +define <2 x double> @test_vpermilvar_pd_zero(<2 x double> %v) { +; CHECK-LABEL: @test_vpermilvar_pd_zero( +; CHECK: shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> zeroinitializer + %a = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %v, <2 x i32> zeroinitializer) + ret <2 x double> %a +} + +define <4 x double> @test_vpermilvar_pd_256_zero(<4 x double> %v) { +; CHECK-LABEL: @test_vpermilvar_pd_256_zero( +; CHECK: shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> + %a = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %v, <4 x i32> zeroinitializer) + ret <4 x double> %a +} + +define <2 x i64> @test_sse2_1() nounwind readnone uwtable { + %S = bitcast i32 1 to i32 + %1 = zext i32 %S to i64 + %2 = insertelement <2 x i64> undef, i64 %1, i32 0 + %3 = insertelement <2 x i64> %2, i64 0, i32 1 + %4 = bitcast <2 x i64> %3 to <8 x i16> + %5 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, <8 x i16> %4) + %6 = bitcast <8 x i16> %5 to <4 x i32> + %7 = bitcast <2 x i64> %3 to <4 x i32> + %8 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %6, <4 x i32> %7) + %9 = bitcast <4 x i32> %8 to <2 x i64> + %10 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %9, <2 x i64> %3) + %11 = bitcast <2 x i64> %10 to <8 x i16> + %12 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %11, i32 %S) + %13 = bitcast <8 x i16> %12 to <4 x i32> + %14 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %13, i32 %S) + %15 = bitcast <4 x i32> %14 to <2 x i64> + %16 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %15, i32 %S) + ret <2 x i64> %16 +; CHECK: test_sse2_1 +; CHECK: ret <2 x i64> <i64 72058418680037440, i64 144117112246370624> +} + +define <4 x i64> @test_avx2_1() nounwind readnone uwtable { + %S = bitcast i32 1 to i32 + %1 = zext i32 %S to i64 + %2 = insertelement <2 x i64> undef, i64 %1, i32 0 + %3 = insertelement <2 x i64> %2, i64 0, i32 1 + %4 = bitcast <2 x i64> %3 to <8 x i16> + %5 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> <i16 1, i16 0, i16 0, i16 0, i16 2, i16 0, i16 0, i16 0, i16 3, i16 0, i16 0, i16 0, i16 4, i16 0, i16 0, i16 0>, <8 x i16> %4) + %6 = bitcast <16 x i16> %5 to <8 x i32> + %7 = bitcast <2 x i64> %3 to <4 x i32> + %8 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %6, <4 x i32> %7) + %9 = bitcast <8 x i32> %8 to <4 x i64> + %10 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %9, <2 x i64> %3) + %11 = bitcast <4 x i64> %10 to <16 x i16> + %12 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %11, i32 %S) + %13 = bitcast <16 x i16> %12 to <8 x i32> + %14 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %13, i32 %S) + %15 = bitcast <8 x i32> %14 to <4 x i64> + %16 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %15, i32 %S) + ret <4 x i64> %16 +; CHECK: test_avx2_1 +; CHECK: ret <4 x i64> <i64 64, i64 128, i64 192, i64 256> +} + +define <2 x i64> @test_sse2_0() nounwind readnone uwtable { + %S = bitcast i32 128 to i32 + %1 = zext i32 %S to i64 + %2 = insertelement <2 x i64> undef, i64 %1, i32 0 + %3 = insertelement <2 x i64> %2, i64 0, i32 1 + %4 = bitcast <2 x i64> %3 to <8 x i16> + %5 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, <8 x i16> %4) + %6 = bitcast <8 x i16> %5 to <4 x i32> + %7 = bitcast <2 x i64> %3 to <4 x i32> + %8 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %6, <4 x i32> %7) + %9 = bitcast <4 x i32> %8 to <2 x i64> + %10 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %9, <2 x i64> %3) + %11 = bitcast <2 x i64> %10 to <8 x i16> + %12 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %11, i32 %S) + %13 = bitcast <8 x i16> %12 to <4 x i32> + %14 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %13, i32 %S) + %15 = bitcast <4 x i32> %14 to <2 x i64> + %16 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %15, i32 %S) + ret <2 x i64> %16 +; CHECK: test_sse2_0 +; CHECK: ret <2 x i64> zeroinitializer +} + +define <4 x i64> @test_avx2_0() nounwind readnone uwtable { + %S = bitcast i32 128 to i32 + %1 = zext i32 %S to i64 + %2 = insertelement <2 x i64> undef, i64 %1, i32 0 + %3 = insertelement <2 x i64> %2, i64 0, i32 1 + %4 = bitcast <2 x i64> %3 to <8 x i16> + %5 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> <i16 1, i16 0, i16 0, i16 0, i16 2, i16 0, i16 0, i16 0, i16 3, i16 0, i16 0, i16 0, i16 4, i16 0, i16 0, i16 0>, <8 x i16> %4) + %6 = bitcast <16 x i16> %5 to <8 x i32> + %7 = bitcast <2 x i64> %3 to <4 x i32> + %8 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %6, <4 x i32> %7) + %9 = bitcast <8 x i32> %8 to <4 x i64> + %10 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %9, <2 x i64> %3) + %11 = bitcast <4 x i64> %10 to <16 x i16> + %12 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %11, i32 %S) + %13 = bitcast <16 x i16> %12 to <8 x i32> + %14 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %13, i32 %S) + %15 = bitcast <8 x i32> %14 to <4 x i64> + %16 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %15, i32 %S) + ret <4 x i64> %16 +; CHECK: test_avx2_0 +; CHECK: ret <4 x i64> zeroinitializer +} +define <2 x i64> @test_sse2_psrl_1() nounwind readnone uwtable { + %S = bitcast i32 1 to i32 + %1 = zext i32 %S to i64 + %2 = insertelement <2 x i64> undef, i64 %1, i32 0 + %3 = insertelement <2 x i64> %2, i64 0, i32 1 + %4 = bitcast <2 x i64> %3 to <8 x i16> + %5 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> <i16 16, i16 32, i16 64, i16 128, i16 256, i16 512, i16 1024, i16 2048>, <8 x i16> %4) + %6 = bitcast <8 x i16> %5 to <4 x i32> + %7 = bitcast <2 x i64> %3 to <4 x i32> + %8 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %6, <4 x i32> %7) + %9 = bitcast <4 x i32> %8 to <2 x i64> + %10 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %9, <2 x i64> %3) + %11 = bitcast <2 x i64> %10 to <8 x i16> + %12 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %11, i32 %S) + %13 = bitcast <8 x i16> %12 to <4 x i32> + %14 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %13, i32 %S) + %15 = bitcast <4 x i32> %14 to <2 x i64> + %16 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %15, i32 %S) + ret <2 x i64> %16 +; CHECK: test_sse2_psrl_1 +; CHECK: ret <2 x i64> <i64 562954248421376, i64 9007267974742020> +} + +define <4 x i64> @test_avx2_psrl_1() nounwind readnone uwtable { + %S = bitcast i32 1 to i32 + %1 = zext i32 %S to i64 + %2 = insertelement <2 x i64> undef, i64 %1, i32 0 + %3 = insertelement <2 x i64> %2, i64 0, i32 1 + %4 = bitcast <2 x i64> %3 to <8 x i16> + %5 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> <i16 1024, i16 0, i16 0, i16 0, i16 2048, i16 0, i16 0, i16 0, i16 4096, i16 0, i16 0, i16 0, i16 8192, i16 0, i16 0, i16 0>, <8 x i16> %4) + %6 = bitcast <16 x i16> %5 to <8 x i32> + %7 = bitcast <2 x i64> %3 to <4 x i32> + %8 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %6, <4 x i32> %7) + %9 = bitcast <8 x i32> %8 to <4 x i64> + %10 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %9, <2 x i64> %3) + %11 = bitcast <4 x i64> %10 to <16 x i16> + %12 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %11, i32 %S) + %13 = bitcast <16 x i16> %12 to <8 x i32> + %14 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %13, i32 %S) + %15 = bitcast <8 x i32> %14 to <4 x i64> + %16 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %15, i32 %S) + ret <4 x i64> %16 +; CHECK: test_avx2_psrl_1 +; CHECK: ret <4 x i64> <i64 16, i64 32, i64 64, i64 128> +} + +define <2 x i64> @test_sse2_psrl_0() nounwind readnone uwtable { + %S = bitcast i32 128 to i32 + %1 = zext i32 %S to i64 + %2 = insertelement <2 x i64> undef, i64 %1, i32 0 + %3 = insertelement <2 x i64> %2, i64 0, i32 1 + %4 = bitcast <2 x i64> %3 to <8 x i16> + %5 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> <i16 32, i16 64, i16 128, i16 256, i16 512, i16 1024, i16 2048, i16 4096>, <8 x i16> %4) + %6 = bitcast <8 x i16> %5 to <4 x i32> + %7 = bitcast <2 x i64> %3 to <4 x i32> + %8 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %6, <4 x i32> %7) + %9 = bitcast <4 x i32> %8 to <2 x i64> + %10 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %9, <2 x i64> %3) + %11 = bitcast <2 x i64> %10 to <8 x i16> + %12 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %11, i32 %S) + %13 = bitcast <8 x i16> %12 to <4 x i32> + %14 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %13, i32 %S) + %15 = bitcast <4 x i32> %14 to <2 x i64> + %16 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %15, i32 %S) + ret <2 x i64> %16 +; CHECK: test_sse2_psrl_0 +; CHECK: ret <2 x i64> zeroinitializer +} + +define <4 x i64> @test_avx2_psrl_0() nounwind readnone uwtable { + %S = bitcast i32 128 to i32 + %1 = zext i32 %S to i64 + %2 = insertelement <2 x i64> undef, i64 %1, i32 0 + %3 = insertelement <2 x i64> %2, i64 0, i32 1 + %4 = bitcast <2 x i64> %3 to <8 x i16> + %5 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> <i16 1024, i16 0, i16 0, i16 0, i16 2048, i16 0, i16 0, i16 0, i16 4096, i16 0, i16 0, i16 0, i16 8192, i16 0, i16 0, i16 0>, <8 x i16> %4) + %6 = bitcast <16 x i16> %5 to <8 x i32> + %7 = bitcast <2 x i64> %3 to <4 x i32> + %8 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %6, <4 x i32> %7) + %9 = bitcast <8 x i32> %8 to <4 x i64> + %10 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %9, <2 x i64> %3) + %11 = bitcast <4 x i64> %10 to <16 x i16> + %12 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %11, i32 %S) + %13 = bitcast <16 x i16> %12 to <8 x i32> + %14 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %13, i32 %S) + %15 = bitcast <8 x i32> %14 to <4 x i64> + %16 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %15, i32 %S) + ret <4 x i64> %16 +; CHECK: test_avx2_psrl_0 +; CHECK: ret <4 x i64> zeroinitializer +} + +declare <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64>, i32) #1 +declare <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32>, i32) #1 +declare <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16>, i32) #1 +declare <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64>, <2 x i64>) #1 +declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) #1 +declare <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16>, <8 x i16>) #1 +declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) #1 +declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) #1 +declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) #1 +declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) #1 +declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) #1 +declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) #1 +declare <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64>, i32) #1 +declare <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32>, i32) #1 +declare <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16>, i32) #1 +declare <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64>, <2 x i64>) #1 +declare <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32>, <4 x i32>) #1 +declare <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16>, <8 x i16>) #1 +declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) #1 +declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) #1 +declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) #1 +declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) #1 +declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) #1 +declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) #1 +attributes #1 = { nounwind readnone } diff --git a/test/Transforms/InstCombine/vec_phi_extract.ll b/test/Transforms/InstCombine/vec_phi_extract.ll index 73ec1f1bb04f..1d778a000fb7 100644 --- a/test/Transforms/InstCombine/vec_phi_extract.ll +++ b/test/Transforms/InstCombine/vec_phi_extract.ll @@ -36,10 +36,10 @@ for.cond: %input_1.addr.1 = phi <3 x i32> [ undef, %entry ], [ %dec43, %for.body ] br i1 undef, label %for.end, label %for.body -; CHECK extractelement +; CHECK: extractelement for.body: %dec43 = add <3 x i32> %input_1.addr.1, <i32 -1, i32 -1, i32 -1> - %sub44 = sub <3 x i32> zeroinitializer, %dec43 + %sub44 = sub <3 x i32> <i32 -1, i32 -1, i32 -1>, %dec43 %div45 = sdiv <3 x i32> %input_2.addr.0, %sub44 br label %for.cond diff --git a/test/Transforms/InstCombine/vec_sext.ll b/test/Transforms/InstCombine/vec_sext.ll index d7ab96b9cfd8..6f0d21476e3e 100644 --- a/test/Transforms/InstCombine/vec_sext.ll +++ b/test/Transforms/InstCombine/vec_sext.ll @@ -13,6 +13,7 @@ entry: %cond = or <4 x i32> %2, %3 ret <4 x i32> %cond +; CHECK-LABEL: @psignd_3 ; CHECK: ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> ; CHECK: sub nsw <4 x i32> zeroinitializer, %a ; CHECK: xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1> @@ -20,3 +21,25 @@ entry: ; CHECK: and <4 x i32> %b.lobit, %sub ; CHECK: or <4 x i32> %1, %2 } + +define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) nounwind ssp { +entry: + %cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1> + %sext = sext <4 x i1> %cmp to <4 x i32> + %sub = sub nsw <4 x i32> zeroinitializer, %a + %0 = icmp slt <4 x i32> %sext, zeroinitializer + %sext3 = sext <4 x i1> %0 to <4 x i32> + %1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1> + %2 = and <4 x i32> %a, %1 + %3 = and <4 x i32> %sext3, %sub + %cond = or <4 x i32> %2, %3 + ret <4 x i32> %cond + +; CHECK-LABEL: @test1 +; CHECK: ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31> +; CHECK: xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1> +; CHECK: sub nsw <4 x i32> zeroinitializer, %a +; CHECK: and <4 x i32> %b.lobit, %a +; CHECK: and <4 x i32> %b.lobit.not, %sub +; CHECK: or <4 x i32> %0, %1 +} diff --git a/test/Transforms/InstCombine/vec_shuffle.ll b/test/Transforms/InstCombine/vec_shuffle.ll index 3ee43dc63a6f..eb4e9d6f8c30 100644 --- a/test/Transforms/InstCombine/vec_shuffle.ll +++ b/test/Transforms/InstCombine/vec_shuffle.ll @@ -228,3 +228,189 @@ define <4 x float> @test15b(<4 x float> %LHS, <4 x float> %RHS) { ret <4 x float> %tmp5 } +define <1 x i32> @test16a(i32 %ele) { +; CHECK-LABEL: @test16a( +; CHECK-NEXT: ret <1 x i32> <i32 2> + %tmp0 = insertelement <2 x i32> <i32 1, i32 undef>, i32 %ele, i32 1 + %tmp1 = shl <2 x i32> %tmp0, <i32 1, i32 1> + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <1 x i32> <i32 0> + ret <1 x i32> %tmp2 +} + +define <4 x i8> @test16b(i8 %ele) { +; CHECK-LABEL: @test16b( +; CHECK-NEXT: ret <4 x i8> <i8 2, i8 2, i8 2, i8 2> + %tmp0 = insertelement <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 undef, i8 1>, i8 %ele, i32 6 + %tmp1 = shl <8 x i8> %tmp0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x i8> %tmp2 +} + +; If composition of two shuffles is identity, shuffles can be removed. +define <4 x i32> @shuffle_17ident(<4 x i32> %v) nounwind uwtable { +; CHECK-LABEL: @shuffle_17ident( +; CHECK-NOT: shufflevector + %shuffle = shufflevector <4 x i32> %v, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %shuffle2 = shufflevector <4 x i32> %shuffle, <4 x i32> zeroinitializer, + <4 x i32> <i32 3, i32 0, i32 1, i32 2> + ret <4 x i32> %shuffle2 +} + +; swizzle can be put after operation +define <4 x i32> @shuffle_17and(<4 x i32> %v1, <4 x i32> %v2) nounwind uwtable { +; CHECK-LABEL: @shuffle_17and( +; CHECK-NOT: shufflevector +; CHECK: and <4 x i32> %v1, %v2 +; CHECK: shufflevector + %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %t2 = shufflevector <4 x i32> %v2, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %r = and <4 x i32> %t1, %t2 + ret <4 x i32> %r +} + +define <4 x i32> @shuffle_17add(<4 x i32> %v1, <4 x i32> %v2) nounwind uwtable { +; CHECK-LABEL: @shuffle_17add( +; CHECK-NOT: shufflevector +; CHECK: add <4 x i32> %v1, %v2 +; CHECK: shufflevector + %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %t2 = shufflevector <4 x i32> %v2, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %r = add <4 x i32> %t1, %t2 + ret <4 x i32> %r +} + +define <4 x i32> @shuffle_17addnsw(<4 x i32> %v1, <4 x i32> %v2) nounwind uwtable { +; CHECK-LABEL: @shuffle_17addnsw( +; CHECK-NOT: shufflevector +; CHECK: add nsw <4 x i32> %v1, %v2 +; CHECK: shufflevector + %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %t2 = shufflevector <4 x i32> %v2, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %r = add nsw <4 x i32> %t1, %t2 + ret <4 x i32> %r +} + +define <4 x i32> @shuffle_17addnuw(<4 x i32> %v1, <4 x i32> %v2) nounwind uwtable { +; CHECK-LABEL: @shuffle_17addnuw( +; CHECK-NOT: shufflevector +; CHECK: add nuw <4 x i32> %v1, %v2 +; CHECK: shufflevector + %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %t2 = shufflevector <4 x i32> %v2, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %r = add nuw <4 x i32> %t1, %t2 + ret <4 x i32> %r +} + +define <4 x float> @shuffle_17fsub(<4 x float> %v1, <4 x float> %v2) nounwind uwtable { +; CHECK-LABEL: @shuffle_17fsub( +; CHECK-NOT: shufflevector +; CHECK: fsub <4 x float> %v1, %v2 +; CHECK: shufflevector + %t1 = shufflevector <4 x float> %v1, <4 x float> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %t2 = shufflevector <4 x float> %v2, <4 x float> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %r = fsub <4 x float> %t1, %t2 + ret <4 x float> %r +} + +define <4 x i32> @shuffle_17addconst(<4 x i32> %v1, <4 x i32> %v2) { +; CHECK-LABEL: @shuffle_17addconst( +; CHECK-NOT: shufflevector +; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = add <4 x i32> %v1, <i32 4, i32 1, i32 2, i32 3> +; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <4 x i32> [[VAR1]], <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> +; CHECK: ret <4 x i32> [[VAR2]] + %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 2, i32 3, i32 0> + %r = add <4 x i32> %t1, <i32 1, i32 2, i32 3, i32 4> + ret <4 x i32> %r +} + +define <4 x i32> @shuffle_17add2(<4 x i32> %v) { +; CHECK-LABEL: @shuffle_17add2( +; CHECK-NOT: shufflevector +; CHECK: [[VAR:%[a-zA-Z0-9.]+]] = shl <4 x i32> %v, <i32 1, i32 1, i32 1, i32 1> +; CHECK: ret <4 x i32> [[VAR]] + %t1 = shufflevector <4 x i32> %v, <4 x i32> zeroinitializer, + <4 x i32> <i32 3, i32 2, i32 1, i32 0> + %t2 = add <4 x i32> %t1, %t1 + %r = shufflevector <4 x i32> %t2, <4 x i32> zeroinitializer, + <4 x i32> <i32 3, i32 2, i32 1, i32 0> + ret <4 x i32> %r +} + +define <4 x i32> @shuffle_17mulsplat(<4 x i32> %v) { +; CHECK-LABEL: @shuffle_17mulsplat( +; CHECK-NOT: shufflevector +; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = mul <4 x i32> %v, %v +; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <4 x i32> [[VAR1]], <4 x i32> undef, <4 x i32> zeroinitializer +; CHECK: ret <4 x i32> [[VAR2]] + %s1 = shufflevector <4 x i32> %v, + <4 x i32> zeroinitializer, + <4 x i32> zeroinitializer + %m1 = mul <4 x i32> %s1, %s1 + %s2 = shufflevector <4 x i32> %m1, + <4 x i32> zeroinitializer, + <4 x i32> <i32 1, i32 1, i32 1, i32 1> + ret <4 x i32> %s2 +} + +; Do not reorder shuffle and binop if LHS of shuffles are of different size +define <2 x i32> @pr19717(<4 x i32> %in0, <2 x i32> %in1) { +; CHECK-LABEL: @pr19717( +; CHECK: shufflevector +; CHECK: shufflevector +; CHECK: mul + %shuffle = shufflevector <4 x i32> %in0, <4 x i32> %in0, <2 x i32> zeroinitializer + %shuffle4 = shufflevector <2 x i32> %in1, <2 x i32> %in1, <2 x i32> zeroinitializer + %mul = mul <2 x i32> %shuffle, %shuffle4 + ret <2 x i32> %mul +} + +define <4 x i16> @pr19717a(<8 x i16> %in0, <8 x i16> %in1) { +; CHECK-LABEL: @pr19717a( +; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = mul <8 x i16> %in0, %in1 +; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <8 x i16> [[VAR1]], <8 x i16> undef, <4 x i32> <i32 5, i32 5, i32 5, i32 5> +; CHECK: ret <4 x i16> [[VAR2]] + %shuffle = shufflevector <8 x i16> %in0, <8 x i16> %in0, <4 x i32> <i32 5, i32 5, i32 5, i32 5> + %shuffle1 = shufflevector <8 x i16> %in1, <8 x i16> %in1, <4 x i32> <i32 5, i32 5, i32 5, i32 5> + %mul = mul <4 x i16> %shuffle, %shuffle1 + ret <4 x i16> %mul +} + +define <8 x i8> @pr19730(<16 x i8> %in0) { +; CHECK-LABEL: @pr19730( +; CHECK: shufflevector + %shuffle = shufflevector <16 x i8> %in0, <16 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> + %shuffle1 = shufflevector <8 x i8> %shuffle, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> + ret <8 x i8> %shuffle1 +} + +define i32 @pr19737(<4 x i32> %in0) { +; CHECK-LABEL: @pr19737( +; CHECK: [[VAR:%[a-zA-Z0-9.]+]] = extractelement <4 x i32> %in0, i32 0 +; CHECK: ret i32 [[VAR]] + %shuffle.i = shufflevector <4 x i32> zeroinitializer, <4 x i32> %in0, <4 x i32> <i32 0, i32 4, i32 2, i32 6> + %neg.i = xor <4 x i32> %shuffle.i, <i32 -1, i32 -1, i32 -1, i32 -1> + %and.i = and <4 x i32> %in0, %neg.i + %rv = extractelement <4 x i32> %and.i, i32 0 + ret i32 %rv +} + +define <4 x i32> @pr20114(<4 x i32> %__mask) { +; CHECK-LABEL: @pr20114 +; CHECK: shufflevector +; CHECK: and + %mask01.i = shufflevector <4 x i32> %__mask, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1> + %masked_new.i.i.i = and <4 x i32> bitcast (<2 x i64> <i64 ptrtoint (<4 x i32> (<4 x i32>)* @pr20114 to i64), i64 ptrtoint (<4 x i32> (<4 x i32>)* @pr20114 to i64)> to <4 x i32>), %mask01.i + ret <4 x i32> %masked_new.i.i.i +} diff --git a/test/Transforms/InstCombine/zext-bool-add-sub.ll b/test/Transforms/InstCombine/zext-bool-add-sub.ll index d7f338b659b4..6fa4d70d6360 100644 --- a/test/Transforms/InstCombine/zext-bool-add-sub.ll +++ b/test/Transforms/InstCombine/zext-bool-add-sub.ll @@ -6,7 +6,7 @@ entry: ; CHECK-LABEL: @a( ; CHECK: [[TMP1:%.*]] = sext i1 %y to i32 ; CHECK: [[TMP2:%.*]] = select i1 %x, i32 2, i32 1 -; CHECK-NEXT: add i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: add nsw i32 [[TMP2]], [[TMP1]] %conv = zext i1 %x to i32 %conv3 = zext i1 %y to i32 %conv3.neg = sub i32 0, %conv3 diff --git a/test/Transforms/InstCombine/zext.ll b/test/Transforms/InstCombine/zext.ll index 10eabf7aed46..b62c626c95c0 100644 --- a/test/Transforms/InstCombine/zext.ll +++ b/test/Transforms/InstCombine/zext.ll @@ -5,7 +5,41 @@ define i64 @test_sext_zext(i16 %A) { %c1 = zext i16 %A to i32 ; <i32> [#uses=1] %c2 = sext i32 %c1 to i64 ; <i64> [#uses=1] ret i64 %c2 + +; CHECK-LABEL: @test_sext_zext ; CHECK-NOT: %c1 ; CHECK: %c2 = zext i16 %A to i64 ; CHECK: ret i64 %c2 } + +define <2 x i64> @test2(<2 x i1> %A) { + %xor = xor <2 x i1> %A, <i1 true, i1 true> + %zext = zext <2 x i1> %xor to <2 x i64> + ret <2 x i64> %zext + +; CHECK-LABEL: @test2 +; CHECK-NEXT: zext <2 x i1> %A to <2 x i64> +; CHECK-NEXT: xor <2 x i64> %1, <i64 1, i64 1> +} + +define <2 x i64> @test3(<2 x i64> %A) { + %trunc = trunc <2 x i64> %A to <2 x i32> + %and = and <2 x i32> %trunc, <i32 23, i32 42> + %zext = zext <2 x i32> %and to <2 x i64> + ret <2 x i64> %zext + +; CHECK-LABEL: @test3 +; CHECK-NEXT: and <2 x i64> %A, <i64 23, i64 42> +} + +define <2 x i64> @test4(<2 x i64> %A) { + %trunc = trunc <2 x i64> %A to <2 x i32> + %and = and <2 x i32> %trunc, <i32 23, i32 42> + %xor = xor <2 x i32> %and, <i32 23, i32 42> + %zext = zext <2 x i32> %xor to <2 x i64> + ret <2 x i64> %zext + +; CHECK-LABEL: @test4 +; CHECK-NEXT: xor <2 x i64> %A, <i64 4294967295, i64 4294967295> +; CHECK-NEXT: and <2 x i64> %1, <i64 23, i64 42> +} diff --git a/test/Transforms/InstMerge/ld_hoist_st_sink.ll b/test/Transforms/InstMerge/ld_hoist_st_sink.ll new file mode 100644 index 000000000000..978160aa002e --- /dev/null +++ b/test/Transforms/InstMerge/ld_hoist_st_sink.ll @@ -0,0 +1,84 @@ +; Tests to make sure that loads and stores in a diamond get merged +; Loads are hoisted into the header. Stores sunks into the footer. +; RUN: opt -basicaa -memdep -mldst-motion -S < %s | FileCheck %s +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +%struct.node = type { i64, %struct.node*, %struct.node*, %struct.node*, i64, %struct.arc*, i64, i64, i64 } +%struct.arc = type { i64, i64, i64 } + +define i64 @foo(%struct.node* nocapture readonly %r) nounwind { +entry: + %node.0.in16 = getelementptr inbounds %struct.node* %r, i64 0, i32 2 + %node.017 = load %struct.node** %node.0.in16, align 8 + %tobool18 = icmp eq %struct.node* %node.017, null + br i1 %tobool18, label %while.end, label %while.body.preheader + +; CHECK-LABEL: while.body.preheader +while.body.preheader: ; preds = %entry +; CHECK: load + br label %while.body + +while.body: ; preds = %while.body.preheader, %if.end + %node.020 = phi %struct.node* [ %node.0, %if.end ], [ %node.017, %while.body.preheader ] + %sum.019 = phi i64 [ %inc, %if.end ], [ 0, %while.body.preheader ] + %orientation = getelementptr inbounds %struct.node* %node.020, i64 0, i32 4 + %0 = load i64* %orientation, align 8 + %cmp = icmp eq i64 %0, 1 + br i1 %cmp, label %if.then, label %if.else +; CHECK: if.then +if.then: ; preds = %while.body + %a = getelementptr inbounds %struct.node* %node.020, i64 0, i32 5 +; CHECK-NOT: load %struct.arc + %1 = load %struct.arc** %a, align 8 + %cost = getelementptr inbounds %struct.arc* %1, i64 0, i32 0 +; CHECK-NOT: load i64* + %2 = load i64* %cost, align 8 + %pred = getelementptr inbounds %struct.node* %node.020, i64 0, i32 1 +; CHECK-NOT: load %struct.node** + %3 = load %struct.node** %pred, align 8 + %p = getelementptr inbounds %struct.node* %3, i64 0, i32 6 +; CHECK-NOT: load i64* + %4 = load i64* %p, align 8 + %add = add nsw i64 %4, %2 + %p1 = getelementptr inbounds %struct.node* %node.020, i64 0, i32 6 +; CHECK-NOT: store i64 + store i64 %add, i64* %p1, align 8 + br label %if.end + +; CHECK: if.else +if.else: ; preds = %while.body + %pred2 = getelementptr inbounds %struct.node* %node.020, i64 0, i32 1 +; CHECK-NOT: load %struct.node** + %5 = load %struct.node** %pred2, align 8 + %p3 = getelementptr inbounds %struct.node* %5, i64 0, i32 6 +; CHECK-NOT: load i64* + %6 = load i64* %p3, align 8 + %a4 = getelementptr inbounds %struct.node* %node.020, i64 0, i32 5 +; CHECK-NOT: load %struct.arc** + %7 = load %struct.arc** %a4, align 8 + %cost5 = getelementptr inbounds %struct.arc* %7, i64 0, i32 0 +; CHECK-NOT: load i64* + %8 = load i64* %cost5, align 8 + %sub = sub nsw i64 %6, %8 + %p6 = getelementptr inbounds %struct.node* %node.020, i64 0, i32 6 +; CHECK-NOT: store i64 + store i64 %sub, i64* %p6, align 8 + br label %if.end + +; CHECK: if.end +if.end: ; preds = %if.else, %if.then +; CHECK: store + %inc = add nsw i64 %sum.019, 1 + %node.0.in = getelementptr inbounds %struct.node* %node.020, i64 0, i32 2 + %node.0 = load %struct.node** %node.0.in, align 8 + %tobool = icmp eq %struct.node* %node.0, null + br i1 %tobool, label %while.end.loopexit, label %while.body + +while.end.loopexit: ; preds = %if.end + %inc.lcssa = phi i64 [ %inc, %if.end ] + br label %while.end + +while.end: ; preds = %while.end.loopexit, %entry + %sum.0.lcssa = phi i64 [ 0, %entry ], [ %inc.lcssa, %while.end.loopexit ] + ret i64 %sum.0.lcssa +} diff --git a/test/Transforms/InstSimplify/apint-or.ll b/test/Transforms/InstSimplify/apint-or.ll new file mode 100644 index 000000000000..5d314db7133d --- /dev/null +++ b/test/Transforms/InstSimplify/apint-or.ll @@ -0,0 +1,37 @@ +; RUN: opt < %s -instsimplify -S | not grep or + +; Test the case where integer BitWidth <= 64 && BitWidth % 2 != 0. +define i39 @test1(i39 %V, i39 %M) { + ;; If we have: ((V + N) & C1) | (V & C2) + ;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0 + ;; replace with V+N. + %C1 = xor i39 274877906943, -1 ;; C2 = 274877906943 + %N = and i39 %M, 274877906944 + %A = add i39 %V, %N + %B = and i39 %A, %C1 + %D = and i39 %V, 274877906943 + %R = or i39 %B, %D + ret i39 %R +; CHECK-LABEL @test1 +; CHECK-NEXT: and {{.*}}, -274877906944 +; CHECK-NEXT: add +; CHECK-NEXT: ret +} + +; Test the case where Integer BitWidth > 64 && BitWidth <= 1024. +define i399 @test2(i399 %V, i399 %M) { + ;; If we have: ((V + N) & C1) | (V & C2) + ;; .. and C2 = ~C1 and C2 is 0+1+ and (N & C2) == 0 + ;; replace with V+N. + %C1 = xor i399 274877906943, -1 ;; C2 = 274877906943 + %N = and i399 %M, 18446742974197923840 + %A = add i399 %V, %N + %B = and i399 %A, %C1 + %D = and i399 %V, 274877906943 + %R = or i399 %B, %D + ret i399 %R +; CHECK-LABEL @test2 +; CHECK-NEXT: and {{.*}}, 18446742974197923840 +; CHECK-NEXT: add +; CHECK-NEXT: ret +} diff --git a/test/Transforms/InstSimplify/ashr-nop.ll b/test/Transforms/InstSimplify/ashr-nop.ll new file mode 100644 index 000000000000..0914d725e40d --- /dev/null +++ b/test/Transforms/InstSimplify/ashr-nop.ll @@ -0,0 +1,10 @@ +; RUN: opt < %s -instsimplify -S | FileCheck %s + +; CHECK-LABEL: @foo +; CHECK-NOT: ashr +define i32 @foo(i32 %x) { + %o = and i32 %x, 1 + %n = add i32 %o, -1 + %t = ashr i32 %n, 17 + ret i32 %t +} diff --git a/test/Transforms/InstSimplify/compare.ll b/test/Transforms/InstSimplify/compare.ll index abb38695e710..94872d35bb97 100644 --- a/test/Transforms/InstSimplify/compare.ll +++ b/test/Transforms/InstSimplify/compare.ll @@ -739,3 +739,233 @@ define i1 @non_inbounds_gep_compare2(i64* %a) { ret i1 %cmp ; CHECK-NEXT: ret i1 true } + +define <4 x i8> @vectorselectfold(<4 x i8> %a, <4 x i8> %b) { + %false = icmp ne <4 x i8> zeroinitializer, zeroinitializer + %sel = select <4 x i1> %false, <4 x i8> %a, <4 x i8> %b + ret <4 x i8> %sel + +; CHECK-LABEL: @vectorselectfold +; CHECK-NEXT: ret <4 x i8> %b +} + +define <4 x i8> @vectorselectfold2(<4 x i8> %a, <4 x i8> %b) { + %true = icmp eq <4 x i8> zeroinitializer, zeroinitializer + %sel = select <4 x i1> %true, <4 x i8> %a, <4 x i8> %b + ret <4 x i8> %sel + +; CHECK-LABEL: @vectorselectfold +; CHECK-NEXT: ret <4 x i8> %a +} + +define i1 @compare_always_true_slt(i16 %a) { + %1 = zext i16 %a to i32 + %2 = sub nsw i32 0, %1 + %3 = icmp slt i32 %2, 1 + ret i1 %3 + +; CHECK-LABEL: @compare_always_true_slt +; CHECK-NEXT: ret i1 true +} + +define i1 @compare_always_true_sle(i16 %a) { + %1 = zext i16 %a to i32 + %2 = sub nsw i32 0, %1 + %3 = icmp sle i32 %2, 0 + ret i1 %3 + +; CHECK-LABEL: @compare_always_true_sle +; CHECK-NEXT: ret i1 true +} + +define i1 @compare_always_false_sgt(i16 %a) { + %1 = zext i16 %a to i32 + %2 = sub nsw i32 0, %1 + %3 = icmp sgt i32 %2, 0 + ret i1 %3 + +; CHECK-LABEL: @compare_always_false_sgt +; CHECK-NEXT: ret i1 false +} + +define i1 @compare_always_false_sge(i16 %a) { + %1 = zext i16 %a to i32 + %2 = sub nsw i32 0, %1 + %3 = icmp sge i32 %2, 1 + ret i1 %3 + +; CHECK-LABEL: @compare_always_false_sge +; CHECK-NEXT: ret i1 false +} + +define i1 @compare_always_false_eq(i16 %a) { + %1 = zext i16 %a to i32 + %2 = sub nsw i32 0, %1 + %3 = icmp eq i32 %2, 1 + ret i1 %3 + +; CHECK-LABEL: @compare_always_false_eq +; CHECK-NEXT: ret i1 false +} + +define i1 @compare_always_false_ne(i16 %a) { + %1 = zext i16 %a to i32 + %2 = sub nsw i32 0, %1 + %3 = icmp ne i32 %2, 1 + ret i1 %3 + +; CHECK-LABEL: @compare_always_false_ne +; CHECK-NEXT: ret i1 true +} + +define i1 @compare_dividend(i32 %a) { + %div = sdiv i32 2, %a + %cmp = icmp eq i32 %div, 3 + ret i1 %cmp + +; CHECK-LABEL: @compare_dividend +; CHECK-NEXT: ret i1 false +} + +define i1 @lshr_ugt_false(i32 %a) { + %shr = lshr i32 1, %a + %cmp = icmp ugt i32 %shr, 1 + ret i1 %cmp +; CHECK-LABEL: @lshr_ugt_false +; CHECK-NEXT: ret i1 false +} + +define i1 @exact_lshr_ugt_false(i32 %a) { + %shr = lshr exact i32 30, %a + %cmp = icmp ult i32 %shr, 15 + ret i1 %cmp +; CHECK-LABEL: @exact_lshr_ugt_false +; CHECK-NEXT: ret i1 false +} + +define i1 @lshr_sgt_false(i32 %a) { + %shr = lshr i32 1, %a + %cmp = icmp sgt i32 %shr, 1 + ret i1 %cmp +; CHECK-LABEL: @lshr_sgt_false +; CHECK-NEXT: ret i1 false +} + +define i1 @ashr_sgt_false(i32 %a) { + %shr = ashr i32 -30, %a + %cmp = icmp sgt i32 %shr, -1 + ret i1 %cmp +; CHECK-LABEL: @ashr_sgt_false +; CHECK-NEXT: ret i1 false +} + +define i1 @exact_ashr_sgt_false(i32 %a) { + %shr = ashr exact i32 -30, %a + %cmp = icmp sgt i32 %shr, -15 + ret i1 %cmp +; CHECK-LABEL: @exact_ashr_sgt_false +; CHECK-NEXT: ret i1 false +} + +define i1 @nonnull_arg(i32* nonnull %i) { + %cmp = icmp eq i32* %i, null + ret i1 %cmp +; CHECK-LABEL: @nonnull_arg +; CHECK: ret i1 false +} + +define i1 @nonnull_deref_arg(i32* dereferenceable(4) %i) { + %cmp = icmp eq i32* %i, null + ret i1 %cmp +; CHECK-LABEL: @nonnull_deref_arg +; CHECK: ret i1 false +} + +define i1 @nonnull_deref_as_arg(i32 addrspace(1)* dereferenceable(4) %i) { + %cmp = icmp eq i32 addrspace(1)* %i, null + ret i1 %cmp +; CHECK-LABEL: @nonnull_deref_as_arg +; CHECK: icmp +; CHECK ret +} + +declare nonnull i32* @returns_nonnull_helper() +define i1 @returns_nonnull() { + %call = call nonnull i32* @returns_nonnull_helper() + %cmp = icmp eq i32* %call, null + ret i1 %cmp +; CHECK-LABEL: @returns_nonnull +; CHECK: ret i1 false +} + +declare dereferenceable(4) i32* @returns_nonnull_deref_helper() +define i1 @returns_nonnull_deref() { + %call = call dereferenceable(4) i32* @returns_nonnull_deref_helper() + %cmp = icmp eq i32* %call, null + ret i1 %cmp +; CHECK-LABEL: @returns_nonnull_deref +; CHECK: ret i1 false +} + +declare dereferenceable(4) i32 addrspace(1)* @returns_nonnull_deref_as_helper() +define i1 @returns_nonnull_as_deref() { + %call = call dereferenceable(4) i32 addrspace(1)* @returns_nonnull_deref_as_helper() + %cmp = icmp eq i32 addrspace(1)* %call, null + ret i1 %cmp +; CHECK-LABEL: @returns_nonnull_as_deref +; CHECK: icmp +; CHECK: ret +} + +; If a bit is known to be zero for A and known to be one for B, +; then A and B cannot be equal. +define i1 @icmp_eq_const(i32 %a) nounwind { + %b = mul nsw i32 %a, -2 + %c = icmp eq i32 %b, 1 + ret i1 %c + +; CHECK-LABEL: @icmp_eq_const +; CHECK-NEXT: ret i1 false +} + +define i1 @icmp_ne_const(i32 %a) nounwind { + %b = mul nsw i32 %a, -2 + %c = icmp ne i32 %b, 1 + ret i1 %c + +; CHECK-LABEL: @icmp_ne_const +; CHECK-NEXT: ret i1 true +} + +define i1 @icmp_sdiv_int_min(i32 %a) { + %div = sdiv i32 -2147483648, %a + %cmp = icmp ne i32 %div, -1073741824 + ret i1 %cmp + +; CHECK-LABEL: @icmp_sdiv_int_min +; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 -2147483648, %a +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[DIV]], -1073741824 +; CHECK-NEXT: ret i1 [[CMP]] +} + +define i1 @icmp_sdiv_pr20288(i64 %a) { + %div = sdiv i64 %a, -8589934592 + %cmp = icmp ne i64 %div, 1073741824 + ret i1 %cmp + +; CHECK-LABEL: @icmp_sdiv_pr20288 +; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 %a, -8589934592 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[DIV]], 1073741824 +; CHECK-NEXT: ret i1 [[CMP]] +} + +define i1 @icmp_sdiv_neg1(i64 %a) { + %div = sdiv i64 %a, -1 + %cmp = icmp ne i64 %div, 1073741824 + ret i1 %cmp + +; CHECK-LABEL: @icmp_sdiv_neg1 +; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 %a, -1 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[DIV]], 1073741824 +; CHECK-NEXT: ret i1 [[CMP]] +} diff --git a/test/Transforms/InstSimplify/dead-code-removal.ll b/test/Transforms/InstSimplify/dead-code-removal.ll new file mode 100644 index 000000000000..e181f3b60d5b --- /dev/null +++ b/test/Transforms/InstSimplify/dead-code-removal.ll @@ -0,0 +1,15 @@ +; RUN: opt -instsimplify -S < %s | FileCheck %s + +define void @foo() nounwind { + br i1 undef, label %1, label %4 + +; <label>:1 ; preds = %1, %0 +; CHECK-NOT: phi +; CHECK-NOT: sub + %2 = phi i32 [ %3, %1 ], [ undef, %0 ] + %3 = sub i32 0, undef + br label %1 + +; <label>:4 ; preds = %0 + ret void +} diff --git a/test/Transforms/InstSimplify/undef.ll b/test/Transforms/InstSimplify/undef.ll index 23cd50f92b40..181c2efa2dc0 100644 --- a/test/Transforms/InstSimplify/undef.ll +++ b/test/Transforms/InstSimplify/undef.ll @@ -153,3 +153,10 @@ define i64 @test18(i64 %a) { %r = call i64 (i64)* undef(i64 %a) ret i64 %r } + +; CHECK-LABEL: @test19 +; CHECK: ret <4 x i8> undef +define <4 x i8> @test19(<4 x i8> %a) { + %b = shl <4 x i8> %a, <i8 8, i8 9, i8 undef, i8 -1> + ret <4 x i8> %b +} diff --git a/test/Transforms/InstSimplify/vector_gep.ll b/test/Transforms/InstSimplify/vector_gep.ll index 5ac1ddef64f8..17814637b3dd 100644 --- a/test/Transforms/InstSimplify/vector_gep.ll +++ b/test/Transforms/InstSimplify/vector_gep.ll @@ -1,4 +1,7 @@ -;RUN: opt -instsimplify -disable-output < %s +; RUN: opt -S -instsimplify < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + declare void @helper(<2 x i8*>) define void @test(<2 x i8*> %a) { %A = getelementptr <2 x i8*> %a, <2 x i32> <i32 0, i32 0> @@ -6,3 +9,47 @@ define void @test(<2 x i8*> %a) { ret void } +define <4 x i8*> @test1(<4 x i8*> %a) { + %gep = getelementptr <4 x i8*> %a, <4 x i32> zeroinitializer + ret <4 x i8*> %gep + +; CHECK-LABEL: @test1 +; CHECK-NEXT: ret <4 x i8*> %a +} + +define <4 x i8*> @test2(<4 x i8*> %a) { + %gep = getelementptr <4 x i8*> %a + ret <4 x i8*> %gep + +; CHECK-LABEL: @test2 +; CHECK-NEXT: ret <4 x i8*> %a +} + +%struct = type { double, float } + +define <4 x float*> @test3() { + %gep = getelementptr <4 x %struct*> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 1, i32 1, i32 1, i32 1> + ret <4 x float*> %gep + +; CHECK-LABEL: @test3 +; CHECK-NEXT: ret <4 x float*> undef +} + +%struct.empty = type { } + +define <4 x %struct.empty*> @test4(<4 x %struct.empty*> %a) { + %gep = getelementptr <4 x %struct.empty*> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1> + ret <4 x %struct.empty*> %gep + +; CHECK-LABEL: @test4 +; CHECK-NEXT: ret <4 x %struct.empty*> %a +} + +define <4 x i8*> @test5() { + %c = inttoptr <4 x i64> <i64 1, i64 2, i64 3, i64 4> to <4 x i8*> + %gep = getelementptr <4 x i8*> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1> + ret <4 x i8*> %gep + +; CHECK-LABEL: @test5 +; CHECK-NEXT: ret <4 x i8*> getelementptr (<4 x i8*> <i8* inttoptr (i64 1 to i8*), i8* inttoptr (i64 2 to i8*), i8* inttoptr (i64 3 to i8*), i8* inttoptr (i64 4 to i8*)>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) +} diff --git a/test/Transforms/Internalize/2009-01-05-InternalizeAliases.ll b/test/Transforms/Internalize/2009-01-05-InternalizeAliases.ll index 47cf3f0373e4..16bfe2a46091 100644 --- a/test/Transforms/Internalize/2009-01-05-InternalizeAliases.ll +++ b/test/Transforms/Internalize/2009-01-05-InternalizeAliases.ll @@ -1,10 +1,17 @@ -; RUN: opt < %s -internalize -internalize-public-api-list main -S | grep internal | count 3 +; RUN: opt < %s -internalize -internalize-public-api-list main -S | FileCheck %s @A = global i32 0 +; CHECK: @A = internal global i32 0 + @B = alias i32* @A -@C = alias i32* @B +; CHECK: @B = alias internal i32* @A + +@C = alias i32* @A +; CHECK: @C = alias internal i32* @A define i32 @main() { %tmp = load i32* @C ret i32 %tmp } + +; CHECK: define i32 @main() { diff --git a/test/Transforms/Internalize/lists.ll b/test/Transforms/Internalize/lists.ll index 83e441a2dfe7..548c8aa267b5 100644 --- a/test/Transforms/Internalize/lists.ll +++ b/test/Transforms/Internalize/lists.ll @@ -1,7 +1,7 @@ ; No arguments means internalize everything ; RUN: opt < %s -internalize -S | FileCheck --check-prefix=ALL %s -; Non existent files should be treated as if they were empty (so internalize +; Non-existent files should be treated as if they were empty (so internalize ; everything) ; RUN: opt < %s -internalize -internalize-public-api-file /nonexistent/file 2> /dev/null -S | FileCheck --check-prefix=ALL %s @@ -48,3 +48,12 @@ define void @foo() { define available_externally void @bar() { ret void } + +; ALL: define dllexport void @export_foo() { +; FOO_AND_J: define dllexport void @export_foo() { +; FOO_AND_BAR: define dllexport void @export_foo() { +; FOO_J_AND_BAR: define dllexport void @export_foo() { +define dllexport void @export_foo() { + ret void +} + diff --git a/test/Transforms/Internalize/local-visibility.ll b/test/Transforms/Internalize/local-visibility.ll new file mode 100644 index 000000000000..c24d4b7f32a0 --- /dev/null +++ b/test/Transforms/Internalize/local-visibility.ll @@ -0,0 +1,25 @@ +; RUN: opt < %s -internalize -S | FileCheck %s +; Internalized symbols should have default visibility. + +; CHECK: @global = global i32 0 +@global = global i32 0 +@llvm.used = appending global [1 x i32*] [i32* @global] + +; CHECK: @hidden.variable = internal global i32 0 +@hidden.variable = hidden global i32 0 +; CHECK: @protected.variable = internal global i32 0 +@protected.variable = protected global i32 0 + +; CHECK: @hidden.alias = alias internal i32* @global +@hidden.alias = hidden alias i32* @global +; CHECK: @protected.alias = alias internal i32* @global +@protected.alias = protected alias i32* @global + +; CHECK: define internal void @hidden.function() { +define hidden void @hidden.function() { + ret void +} +; CHECK: define internal void @protected.function() { +define protected void @protected.function() { + ret void +} diff --git a/test/Transforms/JumpThreading/phi-eq.ll b/test/Transforms/JumpThreading/phi-eq.ll index 40d3c7edd05d..e05d5ee7c974 100644 --- a/test/Transforms/JumpThreading/phi-eq.ll +++ b/test/Transforms/JumpThreading/phi-eq.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -jump-threading | llvm-dis | FileCheck %s +; RUN: opt < %s -jump-threading -S | FileCheck %s ; Test whether two consecutive switches with identical structures assign the ; proper value to the proper variable. This is really testing ; Instruction::isIdenticalToWhenDefined, as previously that function was diff --git a/test/Transforms/JumpThreading/pr15851_hang.ll b/test/Transforms/JumpThreading/pr15851_hang.ll new file mode 100644 index 000000000000..0484bc9f9dc9 --- /dev/null +++ b/test/Transforms/JumpThreading/pr15851_hang.ll @@ -0,0 +1,22 @@ +; RUN: opt -S -jump-threading < %s | FileCheck %s + +; CHECK-LABEL: @f( +; CHECK-LABEL: entry +; CHECK: ret void +; CHECK-NOT: for.cond1 +; CHECK-NOT: for.body + +define void @f() { +entry: + ret void + +for.cond1: + %i.025 = phi i32 [ %inc, %for.body ], [ %inc, %for.body ], [ 1, %for.cond1 ] + %cmp = icmp slt i32 %i.025, 2 + br i1 %cmp, label %for.body, label %for.cond1 + +for.body: + %inc = add nsw i32 %i.025, 0 + %a = icmp ugt i32 %inc, 2 + br i1 %a, label %for.cond1, label %for.cond1 +} diff --git a/test/Transforms/JumpThreading/select.ll b/test/Transforms/JumpThreading/select.ll index 201e604e0c5e..545e86c082f4 100644 --- a/test/Transforms/JumpThreading/select.ll +++ b/test/Transforms/JumpThreading/select.ll @@ -127,7 +127,7 @@ L4: ; CHECK: test_switch_default ; CHECK: entry: ; CHECK: load -; CHECK: switch +; CHECK: icmp ; CHECK: [[THREADED:[A-Za-z.0-9]+]]: ; CHECK: store ; CHECK: br diff --git a/test/Transforms/LICM/extra-copies.ll b/test/Transforms/LICM/extra-copies.ll new file mode 100644 index 000000000000..ef52f9f404c1 --- /dev/null +++ b/test/Transforms/LICM/extra-copies.ll @@ -0,0 +1,29 @@ +; RUN: opt < %s -licm -S | FileCheck %s +; PR19835 +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @f(i32 %x) { +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %storemerge4 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %mul = mul nsw i32 %x, %x + %add2 = add nsw i32 %mul, %x + %mul3 = add nsw i32 %add2, %mul + %inc = add nsw i32 %storemerge4, 1 + %cmp = icmp slt i32 %inc, 100 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body + %a9.0.lcssa = phi i32 [ %mul3, %for.body ] + ret i32 %a9.0.lcssa +} + +; Test that there is exactly one copy of mul nsw i32 %x, %x in the exit block. +; CHECK: define i32 @f(i32 [[X:%.*]]) +; CHECK: for.end: +; CHECK-NOT: mul nsw i32 [[X]], [[X]] +; CHECK: mul nsw i32 [[X]], [[X]] +; CHECK-NOT: mul nsw i32 [[X]], [[X]] diff --git a/test/Transforms/LICM/hoist-bitcast-load.ll b/test/Transforms/LICM/hoist-bitcast-load.ll new file mode 100644 index 000000000000..fa61eaf5b46f --- /dev/null +++ b/test/Transforms/LICM/hoist-bitcast-load.ll @@ -0,0 +1,239 @@ +; RUN: opt -S -basicaa -licm < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Make sure the basic alloca pointer hoisting works: +; CHECK-LABEL: @test1 +; CHECK: load i32* %c, align 4 +; CHECK: for.body: + +; Function Attrs: nounwind uwtable +define void @test1(i32* nocapture %a, i32* nocapture readonly %b, i32 %n) #0 { +entry: + %cmp6 = icmp sgt i32 %n, 0 + %c = alloca i32 + br i1 %cmp6, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %1 = load i32* %c, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +; Make sure the basic alloca pointer hoisting works through a bitcast to a +; pointer to a smaller type: +; CHECK-LABEL: @test2 +; CHECK: load i32* %c, align 4 +; CHECK: for.body: + +; Function Attrs: nounwind uwtable +define void @test2(i32* nocapture %a, i32* nocapture readonly %b, i32 %n) #0 { +entry: + %cmp6 = icmp sgt i32 %n, 0 + %ca = alloca i64 + %c = bitcast i64* %ca to i32* + br i1 %cmp6, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %1 = load i32* %c, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +; Make sure the basic alloca pointer hoisting works through an addrspacecast +; CHECK-LABEL: @test2_addrspacecast +; CHECK: load i32 addrspace(1)* %c, align 4 +; CHECK: for.body: + +; Function Attrs: nounwind uwtable +define void @test2_addrspacecast(i32 addrspace(1)* nocapture %a, i32 addrspace(1)* nocapture readonly %b, i32 %n) #0 { +entry: + %cmp6 = icmp sgt i32 %n, 0 + %ca = alloca i64 + %c = addrspacecast i64* %ca to i32 addrspace(1)* + br i1 %cmp6, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32 addrspace(1)* %a, i64 %indvars.iv + %0 = load i32 addrspace(1)* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %1 = load i32 addrspace(1)* %c, align 4 + %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %b, i64 %indvars.iv + %2 = load i32 addrspace(1)* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32 addrspace(1)* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +; Make sure the basic alloca pointer hoisting works through a bitcast to a +; pointer to a smaller type (where the bitcast also needs to be hoisted): +; CHECK-LABEL: @test3 +; CHECK: load i32* %c, align 4 +; CHECK: for.body: + +; Function Attrs: nounwind uwtable +define void @test3(i32* nocapture %a, i32* nocapture readonly %b, i32 %n) #0 { +entry: + %cmp6 = icmp sgt i32 %n, 0 + %ca = alloca i64 + br i1 %cmp6, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %c = bitcast i64* %ca to i32* + %1 = load i32* %c, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +; Make sure the basic alloca pointer hoisting does not happen through a bitcast +; to a pointer to a larger type: +; CHECK-LABEL: @test4 +; CHECK: for.body: +; CHECK: load i32* %c, align 4 + +; Function Attrs: nounwind uwtable +define void @test4(i32* nocapture %a, i32* nocapture readonly %b, i32 %n) #0 { +entry: + %cmp6 = icmp sgt i32 %n, 0 + %ca = alloca i16 + %c = bitcast i16* %ca to i32* + br i1 %cmp6, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %1 = load i32* %c, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +; Don't crash on bitcasts to unsized types. +; CHECK-LABEL: @test5 +; CHECK: for.body: +; CHECK: load i32* %c, align 4 + +%atype = type opaque + +; Function Attrs: nounwind uwtable +define void @test5(i32* nocapture %a, i32* nocapture readonly %b, i32 %n) #0 { +entry: + %cmp6 = icmp sgt i32 %n, 0 + %ca = alloca i16 + %cab = bitcast i16* %ca to %atype* + %c = bitcast %atype* %cab to i32* + br i1 %cmp6, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %1 = load i32* %c, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +attributes #0 = { nounwind uwtable } + diff --git a/test/Transforms/LICM/hoist-deref-load.ll b/test/Transforms/LICM/hoist-deref-load.ll new file mode 100644 index 000000000000..c230d1dcd43b --- /dev/null +++ b/test/Transforms/LICM/hoist-deref-load.ll @@ -0,0 +1,168 @@ +; RUN: opt -S -basicaa -licm < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; This test represents the following function: +; void test1(int * __restrict__ a, int * __restrict__ b, int &c, int n) { +; for (int i = 0; i < n; ++i) +; if (a[i] > 0) +; a[i] = c*b[i]; +; } +; and we want to hoist the load of %c out of the loop. This can be done only +; because the dereferenceable attribute is on %c. + +; CHECK-LABEL: @test1 +; CHECK: load i32* %c, align 4 +; CHECK: for.body: + +define void @test1(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readonly nonnull dereferenceable(4) %c, i32 %n) #0 { +entry: + %cmp11 = icmp sgt i32 %n, 0 + br i1 %cmp11, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %1 = load i32* %c, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +; This is the same as @test1, but without the dereferenceable attribute on %c. +; Without this attribute, we should not hoist the load of %c. + +; CHECK-LABEL: @test2 +; CHECK: if.then: +; CHECK: load i32* %c, align 4 + +define void @test2(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readonly nonnull %c, i32 %n) #0 { +entry: + %cmp11 = icmp sgt i32 %n, 0 + br i1 %cmp11, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %1 = load i32* %c, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +; This test represents the following function: +; void test3(int * restrict a, int * restrict b, int c[static 3], int n) { +; for (int i = 0; i < n; ++i) +; if (a[i] > 0) +; a[i] = c[2]*b[i]; +; } +; and we want to hoist the load of c[2] out of the loop. This can be done only +; because the dereferenceable attribute is on %c. + +; CHECK-LABEL: @test3 +; CHECK: load i32* %c2, align 4 +; CHECK: for.body: + +define void @test3(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readonly dereferenceable(12) %c, i32 %n) #0 { +entry: + %cmp11 = icmp sgt i32 %n, 0 + br i1 %cmp11, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %c2 = getelementptr inbounds i32* %c, i64 2 + %1 = load i32* %c2, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +; This is the same as @test3, but with a dereferenceable attribute on %c with a +; size too small to cover c[2] (and so we should not hoist it). + +; CHECK-LABEL: @test4 +; CHECK: if.then: +; CHECK: load i32* %c2, align 4 + +define void @test4(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readonly dereferenceable(11) %c, i32 %n) #0 { +entry: + %cmp11 = icmp sgt i32 %n, 0 + br i1 %cmp11, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 0 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %c2 = getelementptr inbounds i32* %c, i64 2 + %1 = load i32* %c2, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i64 %indvars.iv + %2 = load i32* %arrayidx3, align 4 + %mul = mul nsw i32 %2, %1 + store i32 %mul, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc, %entry + ret void +} + +attributes #0 = { nounwind uwtable } + diff --git a/test/Transforms/LICM/lcssa-ssa-promoter.ll b/test/Transforms/LICM/lcssa-ssa-promoter.ll new file mode 100644 index 000000000000..5df3ef12181b --- /dev/null +++ b/test/Transforms/LICM/lcssa-ssa-promoter.ll @@ -0,0 +1,76 @@ +; RUN: opt -S -basicaa -licm < %s | FileCheck %s +; +; Manually validate LCSSA form is preserved even after SSAUpdater is used to +; promote things in the loop bodies. + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@x = common global i32 0, align 4 +@y = common global i32 0, align 4 + +define void @PR18688() { +; CHECK-LABEL: @PR18688( + +entry: + br i1 undef, label %return, label %outer.preheader + +outer.preheader: + br label %outer.header +; CHECK: outer.preheader: +; CHECK: br label %outer.header + +outer.header: + store i32 0, i32* @x, align 4 + br i1 undef, label %outer.latch, label %inner.preheader +; CHECK: outer.header: +; CHECK-NEXT: br i1 undef, label %outer.latch, label %inner.preheader + +inner.preheader: + br label %inner.header +; CHECK: inner.preheader: +; CHECK-NEXT: br label %inner.header + +inner.header: + br i1 undef, label %inner.body.rhs, label %inner.latch +; CHECK: inner.header: +; CHECK-NEXT: %[[PHI0:[^,]+]] = phi i32 [ %{{[^,]+}}, %inner.latch ], [ 0, %inner.preheader ] +; CHECK-NEXT: br i1 undef, label %inner.body.rhs, label %inner.latch + +inner.body.rhs: + store i32 0, i32* @x, align 4 + br label %inner.latch +; CHECK: inner.body.rhs: +; CHECK-NEXT: br label %inner.latch + +inner.latch: + %y_val = load i32* @y, align 4 + %icmp = icmp eq i32 %y_val, 0 + br i1 %icmp, label %inner.exit, label %inner.header +; CHECK: inner.latch: +; CHECK-NEXT: %[[PHI1:[^,]+]] = phi i32 [ 0, %inner.body.rhs ], [ %[[PHI0]], %inner.header ] +; CHECK-NEXT: br i1 %{{[^,]+}}, label %inner.exit, label %inner.header + +inner.exit: + br label %outer.latch +; CHECK: inner.exit: +; CHECK-NEXT: %[[INNER_LCSSA:[^,]+]] = phi i32 [ %[[PHI1]], %inner.latch ] +; CHECK-NEXT: br label %outer.latch + +outer.latch: + br i1 undef, label %outer.exit, label %outer.header +; CHECK: outer.latch: +; CHECK-NEXT: %[[PHI2:[^,]+]] = phi i32 [ %[[INNER_LCSSA]], %inner.exit ], [ 0, %outer.header ] +; CHECK-NEXT: br i1 {{.*}}, label %outer.exit, label %outer.header + +outer.exit: + br label %return +; CHECK: outer.exit: +; CHECK-NEXT: %[[OUTER_LCSSA:[^,]+]] = phi i32 [ %[[PHI2]], %outer.latch ] +; CHECK-NEXT: store i32 %[[OUTER_LCSSA]] +; CHECK-NEXT: br label %return + +return: + ret void +} + diff --git a/test/Transforms/LICM/scalar_promote.ll b/test/Transforms/LICM/scalar_promote.ll index 92ef15581ce0..d7e7c6e9a316 100644 --- a/test/Transforms/LICM/scalar_promote.ll +++ b/test/Transforms/LICM/scalar_promote.ll @@ -24,7 +24,8 @@ Loop: ; preds = %Loop, %0 Out: ret void ; CHECK: Out: -; CHECK-NEXT: store i32 %x2, i32* @X +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %x2 +; CHECK-NEXT: store i32 %[[LCSSAPHI]], i32* @X ; CHECK-NEXT: ret void } @@ -48,7 +49,8 @@ Loop: ; preds = %Loop, %0 Exit: ; preds = %Loop ret void ; CHECK: Exit: -; CHECK-NEXT: store i32 %V, i32* getelementptr inbounds (i32* @X, i64 1) +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %V +; CHECK-NEXT: store i32 %[[LCSSAPHI]], i32* getelementptr inbounds (i32* @X, i64 1) ; CHECK-NEXT: ret void } @@ -142,7 +144,8 @@ Loop: ; preds = %Loop, %0 Out: ret void ; CHECK: Out: -; CHECK-NEXT: store i32 %x2, i32* @X +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %x2 +; CHECK-NEXT: store i32 %[[LCSSAPHI]], i32* @X ; CHECK-NEXT: ret void } @@ -178,7 +181,8 @@ for.end: ; preds = %for.cond.for.end_cr ; CHECK: for.body.lr.ph: ; CHECK-NEXT: %gi.promoted = load i32* %gi, align 4, !tbaa !0 ; CHECK: for.cond.for.end_crit_edge: -; CHECK-NEXT: store i32 %inc, i32* %gi, align 4, !tbaa !0 +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %inc +; CHECK-NEXT: store i32 %[[LCSSAPHI]], i32* %gi, align 4, !tbaa !0 } !0 = metadata !{metadata !4, metadata !4, i64 0} diff --git a/test/Transforms/LICM/sinking.ll b/test/Transforms/LICM/sinking.ll index b503f96e42c0..ccc9186f7a48 100644 --- a/test/Transforms/LICM/sinking.ll +++ b/test/Transforms/LICM/sinking.ll @@ -53,7 +53,7 @@ Exit: ; CHECK-LABEL: @test3( ; CHECK: Exit.loopexit: -; CHECK-NEXT: %X = add i32 0, 1 +; CHECK-NEXT: %X.le = add i32 0, 1 ; CHECK-NEXT: br label %Exit } @@ -76,8 +76,9 @@ Out: ; preds = %Loop ret i32 %tmp.7 ; CHECK-LABEL: @test4( ; CHECK: Out: -; CHECK-NEXT: mul i32 %N, %N_addr.0.pn -; CHECK-NEXT: sub i32 %tmp.6, %N +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn +; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]] +; CHECK-NEXT: sub i32 %tmp.6.le, %N ; CHECK-NEXT: ret i32 } @@ -100,8 +101,8 @@ Out: ; preds = %Loop ret i32 %tmp.6 ; CHECK-LABEL: @test5( ; CHECK: Out: -; CHECK-NEXT: %tmp.6 = load i32* @X -; CHECK-NEXT: ret i32 %tmp.6 +; CHECK-NEXT: %tmp.6.le = load i32* @X +; CHECK-NEXT: ret i32 %tmp.6.le } @@ -124,9 +125,9 @@ Out: ; preds = %Loop ret i32 %sunk2 ; CHECK-LABEL: @test6( ; CHECK: Out: -; CHECK-NEXT: %dead = getelementptr %Ty* @X2, i64 0, i32 0 -; CHECK-NEXT: %sunk2 = load i32* %dead -; CHECK-NEXT: ret i32 %sunk2 +; CHECK-NEXT: %dead.le = getelementptr %Ty* @X2, i64 0, i32 0 +; CHECK-NEXT: %sunk2.le = load i32* %dead.le +; CHECK-NEXT: ret i32 %sunk2.le } @@ -152,12 +153,14 @@ Out2: ; preds = %ContLoop ret i32 %tmp.7 ; CHECK-LABEL: @test7( ; CHECK: Out1: -; CHECK-NEXT: mul i32 %N, %N_addr.0.pn -; CHECK-NEXT: sub i32 %tmp.6, %N +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn +; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]] +; CHECK-NEXT: sub i32 %tmp.6.le, %N ; CHECK-NEXT: ret ; CHECK: Out2: -; CHECK-NEXT: mul i32 %N, %N_addr.0.pn -; CHECK-NEXT: sub i32 %tmp.6 +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn +; CHECK-NEXT: mul i32 %N, %[[LCSSAPHI]] +; CHECK-NEXT: sub i32 %tmp.6.le4, %N ; CHECK-NEXT: ret } @@ -183,8 +186,9 @@ exit2: ; preds = %Cont ; CHECK: exit1: ; CHECK-NEXT: ret i32 0 ; CHECK: exit2: -; CHECK-NEXT: %V = add i32 %X, 1 -; CHECK-NEXT: ret i32 %V +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %X +; CHECK-NEXT: %V.le = add i32 %[[LCSSAPHI]], 1 +; CHECK-NEXT: ret i32 %V.le } @@ -208,7 +212,7 @@ return.i: ; preds = %no_exit.1.i ; CHECK-LABEL: @test9( ; CHECK: loopentry.3.i.preheader.loopexit: -; CHECK-NEXT: %inc.1.i = add i32 0, 1 +; CHECK-NEXT: %inc.1.i.le = add i32 0, 1 ; CHECK-NEXT: br label %loopentry.3.i.preheader } @@ -229,8 +233,9 @@ Out: ; preds = %Loop ; CHECK-LABEL: @test10( ; CHECK: Out: -; CHECK-NEXT: %tmp.6 = sdiv i32 %N, %N_addr.0.pn -; CHECK-NEXT: ret i32 %tmp.6 +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn +; CHECK-NEXT: %tmp.6.le = sdiv i32 %N, %[[LCSSAPHI]] +; CHECK-NEXT: ret i32 %tmp.6.le } ; Should delete, not sink, dead instructions. @@ -246,4 +251,69 @@ Out: ; CHECK-NEXT: ret void } +@c = common global [1 x i32] zeroinitializer, align 4 +; Test a *many* way nested loop with multiple exit blocks both of which exit +; multiple loop nests. This exercises LCSSA corner cases. +define i32 @PR18753(i1* %a, i1* %b, i1* %c, i1* %d) { +entry: + br label %l1.header + +l1.header: + %iv = phi i64 [ %iv.next, %l1.latch ], [ 0, %entry ] + %arrayidx.i = getelementptr inbounds [1 x i32]* @c, i64 0, i64 %iv + br label %l2.header + +l2.header: + %x0 = load i1* %c, align 4 + br i1 %x0, label %l1.latch, label %l3.preheader + +l3.preheader: + br label %l3.header + +l3.header: + %x1 = load i1* %d, align 4 + br i1 %x1, label %l2.latch, label %l4.preheader + +l4.preheader: + br label %l4.header + +l4.header: + %x2 = load i1* %a + br i1 %x2, label %l3.latch, label %l4.body + +l4.body: + call void @f(i32* %arrayidx.i) + %x3 = load i1* %b + %l = trunc i64 %iv to i32 + br i1 %x3, label %l4.latch, label %exit + +l4.latch: + call void @g() + %x4 = load i1* %b, align 4 + br i1 %x4, label %l4.header, label %exit + +l3.latch: + br label %l3.header + +l2.latch: + br label %l2.header + +l1.latch: + %iv.next = add nsw i64 %iv, 1 + br label %l1.header + +exit: + %lcssa = phi i32 [ %l, %l4.latch ], [ %l, %l4.body ] +; CHECK-LABEL: @PR18753( +; CHECK: exit: +; CHECK-NEXT: %[[LCSSAPHI:.*]] = phi i64 [ %iv, %l4.latch ], [ %iv, %l4.body ] +; CHECK-NEXT: %l.le = trunc i64 %[[LCSSAPHI]] to i32 +; CHECK-NEXT: ret i32 %l.le + + ret i32 %lcssa +} + +declare void @f(i32*) + +declare void @g() diff --git a/test/Transforms/LICM/volatile-alias.ll b/test/Transforms/LICM/volatile-alias.ll index 886d7f2f8074..df7f0a931eb8 100644 --- a/test/Transforms/LICM/volatile-alias.ll +++ b/test/Transforms/LICM/volatile-alias.ll @@ -4,7 +4,7 @@ ; out of the loop. ; CHECK: load i32* %p ; CHECK: for.body: -; CHECK; load volatile i32* %q +; CHECK: load volatile i32* %q target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" diff --git a/test/Transforms/LoadCombine/load-combine.ll b/test/Transforms/LoadCombine/load-combine.ll new file mode 100644 index 000000000000..c4d9241764d9 --- /dev/null +++ b/test/Transforms/LoadCombine/load-combine.ll @@ -0,0 +1,190 @@ +; RUN: opt < %s -load-combine -instcombine -S | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Combine read from char* idiom. +define i64 @LoadU64_x64_0(i64* %pData) { + %1 = bitcast i64* %pData to i8* + %2 = load i8* %1, align 1 + %3 = zext i8 %2 to i64 + %4 = shl nuw i64 %3, 56 + %5 = getelementptr inbounds i8* %1, i64 1 + %6 = load i8* %5, align 1 + %7 = zext i8 %6 to i64 + %8 = shl nuw nsw i64 %7, 48 + %9 = or i64 %8, %4 + %10 = getelementptr inbounds i8* %1, i64 2 + %11 = load i8* %10, align 1 + %12 = zext i8 %11 to i64 + %13 = shl nuw nsw i64 %12, 40 + %14 = or i64 %9, %13 + %15 = getelementptr inbounds i8* %1, i64 3 + %16 = load i8* %15, align 1 + %17 = zext i8 %16 to i64 + %18 = shl nuw nsw i64 %17, 32 + %19 = or i64 %14, %18 + %20 = getelementptr inbounds i8* %1, i64 4 + %21 = load i8* %20, align 1 + %22 = zext i8 %21 to i64 + %23 = shl nuw nsw i64 %22, 24 + %24 = or i64 %19, %23 + %25 = getelementptr inbounds i8* %1, i64 5 + %26 = load i8* %25, align 1 + %27 = zext i8 %26 to i64 + %28 = shl nuw nsw i64 %27, 16 + %29 = or i64 %24, %28 + %30 = getelementptr inbounds i8* %1, i64 6 + %31 = load i8* %30, align 1 + %32 = zext i8 %31 to i64 + %33 = shl nuw nsw i64 %32, 8 + %34 = or i64 %29, %33 + %35 = getelementptr inbounds i8* %1, i64 7 + %36 = load i8* %35, align 1 + %37 = zext i8 %36 to i64 + %38 = or i64 %34, %37 + ret i64 %38 +; CHECK-LABEL: @LoadU64_x64_0( +; CHECK: load i64* %{{.*}}, align 1 +; CHECK-NOT: load +} + +; Combine simple adjacent loads. +define i32 @"2xi16_i32"(i16* %x) { + %1 = load i16* %x, align 2 + %2 = getelementptr inbounds i16* %x, i64 1 + %3 = load i16* %2, align 2 + %4 = zext i16 %3 to i32 + %5 = shl nuw i32 %4, 16 + %6 = zext i16 %1 to i32 + %7 = or i32 %5, %6 + ret i32 %7 +; CHECK-LABEL: @"2xi16_i32"( +; CHECK: load i32* %{{.*}}, align 2 +; CHECK-NOT: load +} + +; Don't combine loads across stores. +define i32 @"2xi16_i32_store"(i16* %x, i16* %y) { + %1 = load i16* %x, align 2 + store i16 0, i16* %y, align 2 + %2 = getelementptr inbounds i16* %x, i64 1 + %3 = load i16* %2, align 2 + %4 = zext i16 %3 to i32 + %5 = shl nuw i32 %4, 16 + %6 = zext i16 %1 to i32 + %7 = or i32 %5, %6 + ret i32 %7 +; CHECK-LABEL: @"2xi16_i32_store"( +; CHECK: load i16* %{{.*}}, align 2 +; CHECK: store +; CHECK: load i16* %{{.*}}, align 2 +} + +; Don't combine loads with a gap. +define i32 @"2xi16_i32_gap"(i16* %x) { + %1 = load i16* %x, align 2 + %2 = getelementptr inbounds i16* %x, i64 2 + %3 = load i16* %2, align 2 + %4 = zext i16 %3 to i32 + %5 = shl nuw i32 %4, 16 + %6 = zext i16 %1 to i32 + %7 = or i32 %5, %6 + ret i32 %7 +; CHECK-LABEL: @"2xi16_i32_gap"( +; CHECK: load i16* %{{.*}}, align 2 +; CHECK: load i16* %{{.*}}, align 2 +} + +; Combine out of order loads. +define i32 @"2xi16_i32_order"(i16* %x) { + %1 = getelementptr inbounds i16* %x, i64 1 + %2 = load i16* %1, align 2 + %3 = zext i16 %2 to i32 + %4 = load i16* %x, align 2 + %5 = shl nuw i32 %3, 16 + %6 = zext i16 %4 to i32 + %7 = or i32 %5, %6 + ret i32 %7 +; CHECK-LABEL: @"2xi16_i32_order"( +; CHECK: load i32* %{{.*}}, align 2 +; CHECK-NOT: load +} + +; Overlapping loads. +define i32 @"2xi16_i32_overlap"(i8* %x) { + %1 = bitcast i8* %x to i16* + %2 = load i16* %1, align 2 + %3 = getelementptr inbounds i8* %x, i64 1 + %4 = bitcast i8* %3 to i16* + %5 = load i16* %4, align 2 + %6 = zext i16 %5 to i32 + %7 = shl nuw i32 %6, 16 + %8 = zext i16 %2 to i32 + %9 = or i32 %7, %8 + ret i32 %9 +; CHECK-LABEL: @"2xi16_i32_overlap"( +; CHECK: load i16* %{{.*}}, align 2 +; CHECK: load i16* %{{.*}}, align 2 +} + +; Combine valid alignments. +define i64 @"2xi16_i64_align"(i8* %x) { + %1 = bitcast i8* %x to i32* + %2 = load i32* %1, align 4 + %3 = getelementptr inbounds i8* %x, i64 4 + %4 = bitcast i8* %3 to i16* + %5 = load i16* %4, align 2 + %6 = getelementptr inbounds i8* %x, i64 6 + %7 = bitcast i8* %6 to i16* + %8 = load i16* %7, align 2 + %9 = zext i16 %8 to i64 + %10 = shl nuw i64 %9, 48 + %11 = zext i16 %5 to i64 + %12 = shl nuw nsw i64 %11, 32 + %13 = zext i32 %2 to i64 + %14 = or i64 %12, %13 + %15 = or i64 %14, %10 + ret i64 %15 +; CHECK-LABEL: @"2xi16_i64_align"( +; CHECK: load i64* %{{.*}}, align 4 +} + +; Non power of two. +define i64 @"2xi16_i64_npo2"(i8* %x) { + %1 = load i8* %x, align 1 + %2 = zext i8 %1 to i64 + %3 = getelementptr inbounds i8* %x, i64 1 + %4 = load i8* %3, align 1 + %5 = zext i8 %4 to i64 + %6 = shl nuw nsw i64 %5, 8 + %7 = or i64 %6, %2 + %8 = getelementptr inbounds i8* %x, i64 2 + %9 = load i8* %8, align 1 + %10 = zext i8 %9 to i64 + %11 = shl nuw nsw i64 %10, 16 + %12 = or i64 %11, %7 + %13 = getelementptr inbounds i8* %x, i64 3 + %14 = load i8* %13, align 1 + %15 = zext i8 %14 to i64 + %16 = shl nuw nsw i64 %15, 24 + %17 = or i64 %16, %12 + %18 = getelementptr inbounds i8* %x, i64 4 + %19 = load i8* %18, align 1 + %20 = zext i8 %19 to i64 + %21 = shl nuw nsw i64 %20, 32 + %22 = or i64 %21, %17 + %23 = getelementptr inbounds i8* %x, i64 5 + %24 = load i8* %23, align 1 + %25 = zext i8 %24 to i64 + %26 = shl nuw nsw i64 %25, 40 + %27 = or i64 %26, %22 + %28 = getelementptr inbounds i8* %x, i64 6 + %29 = load i8* %28, align 1 + %30 = zext i8 %29 to i64 + %31 = shl nuw nsw i64 %30, 48 + %32 = or i64 %31, %27 + ret i64 %32 +; CHECK-LABEL: @"2xi16_i64_npo2"( +; CHECK: load i32* %{{.*}}, align 1 +} diff --git a/test/Transforms/LoopIdiom/R600/lit.local.cfg b/test/Transforms/LoopIdiom/R600/lit.local.cfg new file mode 100644 index 000000000000..4086e8d681c3 --- /dev/null +++ b/test/Transforms/LoopIdiom/R600/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'R600' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/LoopIdiom/R600/popcnt.ll b/test/Transforms/LoopIdiom/R600/popcnt.ll new file mode 100644 index 000000000000..e4301bbb06d3 --- /dev/null +++ b/test/Transforms/LoopIdiom/R600/popcnt.ll @@ -0,0 +1,104 @@ +; RUN: opt -loop-idiom -mtriple=r600-- -mcpu=SI -S < %s | FileCheck %s + +; Mostly copied from x86 version. + +;To recognize this pattern: +;int popcount(unsigned long long a) { +; int c = 0; +; while (a) { +; c++; +; a &= a - 1; +; } +; return c; +;} +; + +; CHECK-LABEL: @popcount_i64 +; CHECK: entry +; CHECK: llvm.ctpop.i64 +; CHECK: ret +define i32 @popcount_i64(i64 %a) nounwind uwtable readnone ssp { +entry: + %tobool3 = icmp eq i64 %a, 0 + br i1 %tobool3, label %while.end, label %while.body + +while.body: ; preds = %entry, %while.body + %c.05 = phi i32 [ %inc, %while.body ], [ 0, %entry ] + %a.addr.04 = phi i64 [ %and, %while.body ], [ %a, %entry ] + %inc = add nsw i32 %c.05, 1 + %sub = add i64 %a.addr.04, -1 + %and = and i64 %sub, %a.addr.04 + %tobool = icmp eq i64 %and, 0 + br i1 %tobool, label %while.end, label %while.body + +while.end: ; preds = %while.body, %entry + %c.0.lcssa = phi i32 [ 0, %entry ], [ %inc, %while.body ] + ret i32 %c.0.lcssa +} + +; CHECK-LABEL: @popcount_i32 +; CHECK: entry +; CHECK: llvm.ctpop.i32 +; CHECK: ret +define i32 @popcount_i32(i32 %a) nounwind uwtable readnone ssp { +entry: + %tobool3 = icmp eq i32 %a, 0 + br i1 %tobool3, label %while.end, label %while.body + +while.body: ; preds = %entry, %while.body + %c.05 = phi i32 [ %inc, %while.body ], [ 0, %entry ] + %a.addr.04 = phi i32 [ %and, %while.body ], [ %a, %entry ] + %inc = add nsw i32 %c.05, 1 + %sub = add i32 %a.addr.04, -1 + %and = and i32 %sub, %a.addr.04 + %tobool = icmp eq i32 %and, 0 + br i1 %tobool, label %while.end, label %while.body + +while.end: ; preds = %while.body, %entry + %c.0.lcssa = phi i32 [ 0, %entry ], [ %inc, %while.body ] + ret i32 %c.0.lcssa +} + +; To recognize this pattern: +;int popcount(unsigned long long a, int mydata1, int mydata2) { +; int c = 0; +; while (a) { +; c++; +; a &= a - 1; +; mydata1 *= c; +; mydata2 *= (int)a; +; } +; return c + mydata1 + mydata2; +;} + +; CHECK-LABEL: @popcount2 +; CHECK: entry +; CHECK: llvm.ctpop.i64 +; CHECK: ret +define i32 @popcount2(i64 %a, i32 %mydata1, i32 %mydata2) nounwind uwtable readnone ssp { +entry: + %tobool9 = icmp eq i64 %a, 0 + br i1 %tobool9, label %while.end, label %while.body + +while.body: ; preds = %entry, %while.body + %c.013 = phi i32 [ %inc, %while.body ], [ 0, %entry ] + %mydata2.addr.012 = phi i32 [ %mul1, %while.body ], [ %mydata2, %entry ] + %mydata1.addr.011 = phi i32 [ %mul, %while.body ], [ %mydata1, %entry ] + %a.addr.010 = phi i64 [ %and, %while.body ], [ %a, %entry ] + %inc = add nsw i32 %c.013, 1 + %sub = add i64 %a.addr.010, -1 + %and = and i64 %sub, %a.addr.010 + %mul = mul nsw i32 %inc, %mydata1.addr.011 + %conv = trunc i64 %and to i32 + %mul1 = mul nsw i32 %conv, %mydata2.addr.012 + %tobool = icmp eq i64 %and, 0 + br i1 %tobool, label %while.end, label %while.body + +while.end: ; preds = %while.body, %entry + %c.0.lcssa = phi i32 [ 0, %entry ], [ %inc, %while.body ] + %mydata2.addr.0.lcssa = phi i32 [ %mydata2, %entry ], [ %mul1, %while.body ] + %mydata1.addr.0.lcssa = phi i32 [ %mydata1, %entry ], [ %mul, %while.body ] + %add = add i32 %mydata2.addr.0.lcssa, %mydata1.addr.0.lcssa + %add2 = add i32 %add, %c.0.lcssa + ret i32 %add2 +} diff --git a/test/Transforms/LoopIdiom/X86/lit.local.cfg b/test/Transforms/LoopIdiom/X86/lit.local.cfg index ba763cf03ffc..e71f3cc4c41e 100644 --- a/test/Transforms/LoopIdiom/X86/lit.local.cfg +++ b/test/Transforms/LoopIdiom/X86/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/LoopRotate/PhiSelfRefernce-1.ll b/test/Transforms/LoopRotate/PhiSelfReference-1.ll index a1aa21beeef3..aa1708e8475c 100644 --- a/test/Transforms/LoopRotate/PhiSelfRefernce-1.ll +++ b/test/Transforms/LoopRotate/PhiSelfReference-1.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -loop-rotate -verify-dom-info -verify-loop-info -disable-output -; ModuleID = 'PhiSelfRefernce-1.bc' +; ModuleID = 'PhiSelfReference-1.bc' define void @snrm2(i32 %incx) { entry: diff --git a/test/Transforms/LoopRotate/dbgvalue.ll b/test/Transforms/LoopRotate/dbgvalue.ll index 9461980ac08d..50fc9659a804 100644 --- a/test/Transforms/LoopRotate/dbgvalue.ll +++ b/test/Transforms/LoopRotate/dbgvalue.ll @@ -46,7 +46,11 @@ define void @FindFreeHorzSeg(i64 %startCol, i64 %row, i64* %rowStart) { ; CHECK-LABEL: define void @FindFreeHorzSeg( ; CHECK: %dec = add ; CHECK-NEXT: tail call void @llvm.dbg.value -; CHECK-NEXT: br i1 %tobool, label %for.cond, label %for.end +; CHECK-NEXT: br i1 %tobool, label %for.cond, label %[[LOOP_EXIT:[^,]*]] +; CHECK: [[LOOP_EXIT]]: +; CHECK-NEXT: phi i64 [ %{{[^,]*}}, %{{[^,]*}} ] +; CHECK-NEXT: br label %for.end + entry: br label %for.cond diff --git a/test/Transforms/LoopRotate/preserve-loop-simplify.ll b/test/Transforms/LoopRotate/preserve-loop-simplify.ll new file mode 100644 index 000000000000..53fa02a42a8e --- /dev/null +++ b/test/Transforms/LoopRotate/preserve-loop-simplify.ll @@ -0,0 +1,65 @@ +; RUN: opt -S -loop-rotate < %s -verify-loop-info | FileCheck %s +; +; Verify that LoopRotate preserves LoopSimplify form even in very peculiar loop +; structures. We manually validate the CFG with FileCheck because currently we +; can't cause a failure when LoopSimplify fails to be preserved. + +define void @PR18643() { +; CHECK-LABEL: @PR18643( +entry: + br label %outer.header +; CHECK: br label %outer.header + +outer.header: +; CHECK: outer.header: + br i1 undef, label %inner.header, label %outer.body +; CHECK-NEXT: br i1 {{[^,]*}}, label %[[INNER_PREROTATE_PREHEADER:[^,]*]], label %outer.body + +; CHECK: [[INNER_PREROTATE_PREHEADER]]: +; CHECK-NEXT: br i1 {{[^,]*}}, label %[[INNER_PREROTATE_PREHEADER_SPLIT_RETURN:[^,]*]], label %[[INNER_ROTATED_PREHEADER:[^,]*]] + +; CHECK: [[INNER_ROTATED_PREHEADER]]: +; CHECK-NEXT: br label %inner.body + +inner.header: +; Now the latch! +; CHECK: inner.header: + br i1 undef, label %return, label %inner.body +; CHECK-NEXT: br i1 {{[^,]*}}, label %[[INNER_SPLIT_RETURN:[^,]*]], label %inner.body + +inner.body: +; Now the header! +; CHECK: inner.body: + br i1 undef, label %outer.latch, label %inner.latch +; CHECK-NEXT: br i1 {{[^,]*}}, label %[[INNER_SPLIT_OUTER_LATCH:[^,]*]], label %inner.header + +inner.latch: +; Dead! + br label %inner.header + +outer.body: +; CHECK: outer.body: + br label %outer.latch +; CHECK-NEXT: br label %outer.latch + +; L2 -> L1 exit edge needs a simplified exit block. +; CHECK: [[INNER_SPLIT_OUTER_LATCH]]: +; CHECK-NEXT: br label %outer.latch + +outer.latch: +; CHECK: outer.latch: + br label %outer.header +; CHECK-NEXT: br label %outer.header + +; L1 -> L0 exit edge need sa simplified exit block. +; CHECK: [[INNER_PREROTATE_PREHEADER_SPLIT_RETURN]]: +; CHECK-NEXT: br label %return + +; L2 -> L0 exit edge needs a simplified exit block. +; CHECK: [[INNER_SPLIT_RETURN]]: +; CHECK-NEXT: br label %return + +return: +; CHECK: return: + unreachable +} diff --git a/test/Transforms/LoopSimplify/2007-10-28-InvokeCrash.ll b/test/Transforms/LoopSimplify/2007-10-28-InvokeCrash.ll index e91d141cc6ff..0534a0bf7d06 100644 --- a/test/Transforms/LoopSimplify/2007-10-28-InvokeCrash.ll +++ b/test/Transforms/LoopSimplify/2007-10-28-InvokeCrash.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -loop-simplify -disable-output +; RUN: opt < %s -loop-simplify -disable-output ; PR1752 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-s0:0:64-f80:32:32" target triple = "i686-pc-mingw32" diff --git a/test/Transforms/LoopSimplify/ashr-crash.ll b/test/Transforms/LoopSimplify/ashr-crash.ll new file mode 100644 index 000000000000..c58903d49d55 --- /dev/null +++ b/test/Transforms/LoopSimplify/ashr-crash.ll @@ -0,0 +1,80 @@ +; RUN: opt -basicaa -loop-rotate -licm -instcombine -indvars -loop-unroll -S %s | FileCheck %s +; +; PR18361: ScalarEvolution::getAddRecExpr(): +; Assertion `isLoopInvariant(Operands[i],... +; +; After a series of loop optimizations, SCEV's LoopDispositions grow stale. +; In particular, LoopSimplify hoists %cmp4, resulting in this SCEV for %add: +; {(zext i1 %cmp4 to i32),+,1}<nw><%for.cond1.preheader> +; +; When recomputing the SCEV for %ashr, we truncate the operands to get: +; (zext i1 %cmp4 to i16) +; +; This SCEV was never mapped to a value so never invalidated. It's +; loop disposition is still marked as non-loop-invariant, which is +; inconsistent with the AddRec. + +target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx" + +@d = common global i32 0, align 4 +@a = common global i32 0, align 4 +@c = common global i32 0, align 4 +@b = common global i32 0, align 4 + +; Check that the def-use chain that leads to the bad SCEV is still +; there. +; +; CHECK-LABEL: @foo +; CHECK-LABEL: entry: +; CHECK-LABEL: for.cond1.preheader: +; CHECK-LABEL: for.body3: +; CHECK: %cmp4.le.le +; CHECK: %conv.le.le = zext i1 %cmp4.le.le to i32 +; CHECK: %xor.le.le = xor i32 %conv6.le.le, 1 +define void @foo() { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc7, %entry + %storemerge = phi i32 [ 0, %entry ], [ %inc8, %for.inc7 ] + %f.0 = phi i32 [ undef, %entry ], [ %f.1, %for.inc7 ] + store i32 %storemerge, i32* @d, align 4 + %cmp = icmp slt i32 %storemerge, 1 + br i1 %cmp, label %for.cond1, label %for.end9 + +for.cond1: ; preds = %for.cond, %for.body3 + %storemerge1 = phi i32 [ %inc, %for.body3 ], [ 0, %for.cond ] + %f.1 = phi i32 [ %xor, %for.body3 ], [ %f.0, %for.cond ] + store i32 %storemerge1, i32* @a, align 4 + %cmp2 = icmp slt i32 %storemerge1, 1 + br i1 %cmp2, label %for.body3, label %for.inc7 + +for.body3: ; preds = %for.cond1 + %0 = load i32* @c, align 4 + %cmp4 = icmp sge i32 %storemerge1, %0 + %conv = zext i1 %cmp4 to i32 + %1 = load i32* @d, align 4 + %add = add nsw i32 %conv, %1 + %sext = shl i32 %add, 16 + %conv6 = ashr exact i32 %sext, 16 + %xor = xor i32 %conv6, 1 + %inc = add nsw i32 %storemerge1, 1 + br label %for.cond1 + +for.inc7: ; preds = %for.cond1 + %2 = load i32* @d, align 4 + %inc8 = add nsw i32 %2, 1 + br label %for.cond + +for.end9: ; preds = %for.cond + %cmp10 = icmp sgt i32 %f.0, 0 + br i1 %cmp10, label %if.then, label %if.end + +if.then: ; preds = %for.end9 + store i32 0, i32* @b, align 4 + br label %if.end + +if.end: ; preds = %if.then, %for.end9 + ret void +} diff --git a/test/Transforms/LoopSimplify/notify-scev.ll b/test/Transforms/LoopSimplify/notify-scev.ll new file mode 100644 index 000000000000..ee8e2eec9b3f --- /dev/null +++ b/test/Transforms/LoopSimplify/notify-scev.ll @@ -0,0 +1,110 @@ +; RUN: opt -indvars -S %s | FileCheck %s +; +; PR18384: ValueHandleBase::ValueIsDeleted. +; +; Ensure that LoopSimplify calls ScalarEvolution::forgetLoop before +; deleting a block, regardless of whether any values were hoisted out +; of the block. + +target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-darwin" + +%struct.Params = type { [2 x [4 x [16 x i16]]] } + +; Verify that the loop tail is deleted, and we don't crash! +; +; CHECK-LABEL: @t +; CHECK-LABEL: for.cond127.preheader: +; CHECK-NOT: for.cond127: +; CHECK-LABEL: for.body129: +define void @t() { +entry: + br label %for.body102 + +for.body102: + br i1 undef, label %for.cond127.preheader, label %for.inc203 + +for.cond127.preheader: + br label %for.body129 + +for.cond127: + %cmp128 = icmp slt i32 %inc191, 2 + br i1 %cmp128, label %for.body129, label %for.end192 + +for.body129: + %uv.013 = phi i32 [ 0, %for.cond127.preheader ], [ %inc191, %for.cond127 ] + %idxprom130 = sext i32 %uv.013 to i64 + br i1 undef, label %for.cond135.preheader.lr.ph, label %for.end185 + +for.cond135.preheader.lr.ph: + br i1 undef, label %for.cond135.preheader.lr.ph.split.us, label %for.cond135.preheader.lr.ph.split_crit_edge + +for.cond135.preheader.lr.ph.split_crit_edge: + br label %for.cond135.preheader.lr.ph.split + +for.cond135.preheader.lr.ph.split.us: + br label %for.cond135.preheader.us + +for.cond135.preheader.us: + %block_y.09.us = phi i32 [ 0, %for.cond135.preheader.lr.ph.split.us ], [ %add184.us, %for.cond132.us ] + br i1 true, label %for.cond138.preheader.lr.ph.us, label %for.end178.us + +for.end178.us: + %add184.us = add nsw i32 %block_y.09.us, 4 + br i1 undef, label %for.end185split.us-lcssa.us, label %for.cond132.us + +for.end174.us: + br i1 undef, label %for.cond138.preheader.us, label %for.cond135.for.end178_crit_edge.us + +for.inc172.us: + br i1 undef, label %for.cond142.preheader.us, label %for.end174.us + +for.body145.us: + %arrayidx163.us = getelementptr inbounds %struct.Params* undef, i64 0, i32 0, i64 %idxprom130, i64 %idxprom146.us + br i1 undef, label %for.body145.us, label %for.inc172.us + +for.cond142.preheader.us: + %j.04.us = phi i32 [ %block_y.09.us, %for.cond138.preheader.us ], [ undef, %for.inc172.us ] + %idxprom146.us = sext i32 %j.04.us to i64 + br label %for.body145.us + +for.cond138.preheader.us: + br label %for.cond142.preheader.us + +for.cond132.us: + br i1 undef, label %for.cond135.preheader.us, label %for.cond132.for.end185_crit_edge.us-lcssa.us + +for.cond138.preheader.lr.ph.us: + br label %for.cond138.preheader.us + +for.cond135.for.end178_crit_edge.us: + br label %for.end178.us + +for.end185split.us-lcssa.us: + br label %for.end185split + +for.cond132.for.end185_crit_edge.us-lcssa.us: + br label %for.cond132.for.end185_crit_edge + +for.cond135.preheader.lr.ph.split: + br label %for.end185split + +for.end185split: + br label %for.end185 + +for.cond132.for.end185_crit_edge: + br label %for.end185 + +for.end185: + %inc191 = add nsw i32 %uv.013, 1 + br i1 false, label %for.end192, label %for.cond127 + +for.end192: + br label %for.inc203 + +for.inc203: + br label %for.end205 + +for.end205: + ret void +} diff --git a/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg b/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg new file mode 100644 index 000000000000..675f48e199a0 --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg @@ -0,0 +1,4 @@ +config.suffixes = ['.ll'] + +if not 'AArch64' in config.root.targets: + config.unsupported = True diff --git a/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll b/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll new file mode 100644 index 000000000000..9a175ad8d355 --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll @@ -0,0 +1,33 @@ +; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s +; rdar://10232252 +; Prevent LSR of doing poor choice that cannot be folded in addressing mode + +; Remove the -pre-RA-sched=list-hybrid option after fixing: +; <rdar://problem/12702735> [ARM64][coalescer] need better register +; coalescing for simple unit tests. + +; CHECK: testCase +; CHECK: %while.body{{$}} +; CHECK: ldr [[STREG:x[0-9]+]], [{{x[0-9]+}}], #8 +; CHECK-NEXT: str [[STREG]], [{{x[0-9]+}}], #8 +; CHECK: %while.end +define i32 @testCase() nounwind ssp { +entry: + br label %while.body + +while.body: ; preds = %while.body, %entry + %len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ] + %pDst.05 = phi i64* [ inttoptr (i64 6442450944 to i64*), %entry ], [ %incdec.ptr1, %while.body ] + %pSrc.04 = phi i64* [ inttoptr (i64 4294967296 to i64*), %entry ], [ %incdec.ptr, %while.body ] + %incdec.ptr = getelementptr inbounds i64* %pSrc.04, i64 1 + %tmp = load volatile i64* %pSrc.04, align 8 + %incdec.ptr1 = getelementptr inbounds i64* %pDst.05, i64 1 + store volatile i64 %tmp, i64* %pDst.05, align 8 + %sub = add i64 %len.06, -8 + %cmp = icmp sgt i64 %sub, -1 + br i1 %cmp, label %while.body, label %while.end + +while.end: ; preds = %while.body + tail call void inttoptr (i64 6442450944 to void ()*)() nounwind + ret i32 0 +} diff --git a/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll b/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll new file mode 100644 index 000000000000..10b2c3a403cc --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll @@ -0,0 +1,101 @@ +; RUN: llc < %s -O3 -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid | FileCheck %s +; <rdar://problem/11635990> [arm64] [lsr] Inefficient EA/loop-exit calc in bzero_phys +; +; LSR on loop %while.cond should reassociate non-address mode +; expressions at use %cmp16 to avoid sinking computation into %while.body18. +; +; Remove the -pre-RA-sched=list-hybrid option after fixing: +; <rdar://problem/12702735> [ARM64][coalescer] need better register +; coalescing for simple unit tests. + +; CHECK: @memset +; CHECK: %while.body18{{$}} +; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #8 +; First set the IVREG variable, then use it +; CHECK-NEXT: sub [[IVREG:x[0-9]+]], +; CHECK: [[IVREG]], #8 +; CHECK-NEXT: cmp [[IVREG]], #7 +; CHECK-NEXT: b.hi +define i8* @memset(i8* %dest, i32 %val, i64 %len) nounwind ssp noimplicitfloat { +entry: + %cmp = icmp eq i64 %len, 0 + br i1 %cmp, label %done, label %while.cond.preheader + +while.cond.preheader: ; preds = %entry + %conv = trunc i32 %val to i8 + br label %while.cond + +while.cond: ; preds = %while.body, %while.cond.preheader + %ptr.0 = phi i8* [ %incdec.ptr, %while.body ], [ %dest, %while.cond.preheader ] + %len.addr.0 = phi i64 [ %dec, %while.body ], [ %len, %while.cond.preheader ] + %cond = icmp eq i64 %len.addr.0, 0 + br i1 %cond, label %done, label %land.rhs + +land.rhs: ; preds = %while.cond + %0 = ptrtoint i8* %ptr.0 to i64 + %and = and i64 %0, 7 + %cmp5 = icmp eq i64 %and, 0 + br i1 %cmp5, label %if.end9, label %while.body + +while.body: ; preds = %land.rhs + %incdec.ptr = getelementptr inbounds i8* %ptr.0, i64 1 + store i8 %conv, i8* %ptr.0, align 1, !tbaa !0 + %dec = add i64 %len.addr.0, -1 + br label %while.cond + +if.end9: ; preds = %land.rhs + %conv.mask = and i32 %val, 255 + %1 = zext i32 %conv.mask to i64 + %2 = shl nuw nsw i64 %1, 8 + %ins18 = or i64 %2, %1 + %3 = shl nuw nsw i64 %1, 16 + %ins15 = or i64 %ins18, %3 + %4 = shl nuw nsw i64 %1, 24 + %5 = shl nuw nsw i64 %1, 32 + %mask8 = or i64 %ins15, %4 + %6 = shl nuw nsw i64 %1, 40 + %mask5 = or i64 %mask8, %5 + %7 = shl nuw nsw i64 %1, 48 + %8 = shl nuw i64 %1, 56 + %mask2.masked = or i64 %mask5, %6 + %mask = or i64 %mask2.masked, %7 + %ins = or i64 %mask, %8 + %9 = bitcast i8* %ptr.0 to i64* + %cmp1636 = icmp ugt i64 %len.addr.0, 7 + br i1 %cmp1636, label %while.body18, label %while.body29.lr.ph + +while.body18: ; preds = %if.end9, %while.body18 + %wideptr.038 = phi i64* [ %incdec.ptr19, %while.body18 ], [ %9, %if.end9 ] + %len.addr.137 = phi i64 [ %sub, %while.body18 ], [ %len.addr.0, %if.end9 ] + %incdec.ptr19 = getelementptr inbounds i64* %wideptr.038, i64 1 + store i64 %ins, i64* %wideptr.038, align 8, !tbaa !2 + %sub = add i64 %len.addr.137, -8 + %cmp16 = icmp ugt i64 %sub, 7 + br i1 %cmp16, label %while.body18, label %while.end20 + +while.end20: ; preds = %while.body18 + %cmp21 = icmp eq i64 %sub, 0 + br i1 %cmp21, label %done, label %while.body29.lr.ph + +while.body29.lr.ph: ; preds = %while.end20, %if.end9 + %len.addr.1.lcssa49 = phi i64 [ %sub, %while.end20 ], [ %len.addr.0, %if.end9 ] + %wideptr.0.lcssa48 = phi i64* [ %incdec.ptr19, %while.end20 ], [ %9, %if.end9 ] + %10 = bitcast i64* %wideptr.0.lcssa48 to i8* + br label %while.body29 + +while.body29: ; preds = %while.body29, %while.body29.lr.ph + %len.addr.235 = phi i64 [ %len.addr.1.lcssa49, %while.body29.lr.ph ], [ %dec26, %while.body29 ] + %ptr.134 = phi i8* [ %10, %while.body29.lr.ph ], [ %incdec.ptr31, %while.body29 ] + %dec26 = add i64 %len.addr.235, -1 + %incdec.ptr31 = getelementptr inbounds i8* %ptr.134, i64 1 + store i8 %conv, i8* %ptr.134, align 1, !tbaa !0 + %cmp27 = icmp eq i64 %dec26, 0 + br i1 %cmp27, label %done, label %while.body29 + +done: ; preds = %while.cond, %while.body29, %while.end20, %entry + ret i8* %dest +} + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA"} +!2 = metadata !{metadata !"long long", metadata !0} diff --git a/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll b/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll new file mode 100644 index 000000000000..217896e55c66 --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll @@ -0,0 +1,70 @@ +; RUN: llc -mcpu=cyclone -debug-only=loop-reduce < %s 2>&1 | FileCheck %s +; REQUIRES: asserts + +; LSR used to fail here due to a bug in the ReqRegs test. +; CHECK: The chosen solution requires +; CHECK-NOT: No Satisfactory Solution + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-ios" + +define void @do_integer_add(i64 %iterations, i8* nocapture readonly %cookie) { +entry: + %N = bitcast i8* %cookie to i32* + %0 = load i32* %N, align 4 + %add = add nsw i32 %0, 57 + %cmp56 = icmp eq i64 %iterations, 0 + br i1 %cmp56, label %while.end, label %for.cond.preheader.preheader + +for.cond.preheader.preheader: ; preds = %entry + br label %for.cond.preheader + +while.cond.loopexit: ; preds = %for.body + %add21.lcssa = phi i32 [ %add21, %for.body ] + %dec58 = add i64 %dec58.in, -1 + %cmp = icmp eq i64 %dec58, 0 + br i1 %cmp, label %while.end.loopexit, label %for.cond.preheader + +for.cond.preheader: ; preds = %for.cond.preheader.preheader, %while.cond.loopexit + %dec58.in = phi i64 [ %dec58, %while.cond.loopexit ], [ %iterations, %for.cond.preheader.preheader ] + %a.057 = phi i32 [ %add21.lcssa, %while.cond.loopexit ], [ %add, %for.cond.preheader.preheader ] + br label %for.body + +for.body: ; preds = %for.body, %for.cond.preheader + %a.154 = phi i32 [ %a.057, %for.cond.preheader ], [ %add21, %for.body ] + %i.053 = phi i32 [ 1, %for.cond.preheader ], [ %inc, %for.body ] + %inc = add nsw i32 %i.053, 1 + %add2 = shl i32 %a.154, 1 + %add3 = add nsw i32 %add2, %i.053 + %add4 = shl i32 %add3, 1 + %add5 = add nsw i32 %add4, %i.053 + %add6 = shl i32 %add5, 1 + %add7 = add nsw i32 %add6, %i.053 + %add8 = shl i32 %add7, 1 + %add9 = add nsw i32 %add8, %i.053 + %add10 = shl i32 %add9, 1 + %add11 = add nsw i32 %add10, %i.053 + %add12 = shl i32 %add11, 1 + %add13 = add nsw i32 %add12, %i.053 + %add14 = shl i32 %add13, 1 + %add15 = add nsw i32 %add14, %i.053 + %add16 = shl i32 %add15, 1 + %add17 = add nsw i32 %add16, %i.053 + %add18 = shl i32 %add17, 1 + %add19 = add nsw i32 %add18, %i.053 + %add20 = shl i32 %add19, 1 + %add21 = add nsw i32 %add20, %i.053 + %exitcond = icmp eq i32 %inc, 1001 + br i1 %exitcond, label %while.cond.loopexit, label %for.body + +while.end.loopexit: ; preds = %while.cond.loopexit + %add21.lcssa.lcssa = phi i32 [ %add21.lcssa, %while.cond.loopexit ] + br label %while.end + +while.end: ; preds = %while.end.loopexit, %entry + %a.0.lcssa = phi i32 [ %add, %entry ], [ %add21.lcssa.lcssa, %while.end.loopexit ] + tail call void @use_int(i32 %a.0.lcssa) + ret void +} + +declare void @use_int(i32) diff --git a/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll b/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll index 5d728b528ea5..1d56ddea2446 100644 --- a/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll +++ b/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O3 -march=thumb -mcpu=cortex-a8 | FileCheck %s +; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - -arm-atomic-cfg-tidy=0 | FileCheck %s ; ; LSR should only check for valid address modes when the IV user is a ; memory address. diff --git a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll index ab7f20f0129b..f4edf092641f 100644 --- a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll +++ b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -O3 -march=thumb -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9 +; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A9 +; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 -addr-sink-using-gep=1 %s -o - | FileCheck %s -check-prefix=A9 ; @simple is the most basic chain of address induction variables. Chaining ; saves at least one register and avoids complex addressing and setup diff --git a/test/Transforms/LoopStrengthReduce/ARM/lit.local.cfg b/test/Transforms/LoopStrengthReduce/ARM/lit.local.cfg index 8a3ba96497e7..98c6700c209d 100644 --- a/test/Transforms/LoopStrengthReduce/ARM/lit.local.cfg +++ b/test/Transforms/LoopStrengthReduce/ARM/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'ARM' in targets: +if not 'ARM' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll b/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll index e42b67fd35af..937791dca413 100644 --- a/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll +++ b/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -O3 -march=x86-64 -mcpu=core2 | FileCheck %s -check-prefix=X64 ; RUN: llc < %s -O3 -march=x86 -mcpu=core2 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -O3 -march=x86-64 -mcpu=core2 -addr-sink-using-gep=1 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -O3 -march=x86 -mcpu=core2 -addr-sink-using-gep=1 | FileCheck %s -check-prefix=X32 ; @simple is the most basic chain of address induction variables. Chaining ; saves at least one register and avoids complex addressing and setup diff --git a/test/Transforms/LoopStrengthReduce/X86/lit.local.cfg b/test/Transforms/LoopStrengthReduce/X86/lit.local.cfg index ba763cf03ffc..e71f3cc4c41e 100644 --- a/test/Transforms/LoopStrengthReduce/X86/lit.local.cfg +++ b/test/Transforms/LoopStrengthReduce/X86/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/LoopStrengthReduce/X86/no_superflous_induction_vars.ll b/test/Transforms/LoopStrengthReduce/X86/no_superflous_induction_vars.ll new file mode 100644 index 000000000000..55069947240d --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/X86/no_superflous_induction_vars.ll @@ -0,0 +1,50 @@ +; RUN: opt -S -loop-reduce -mcpu=corei7-avx -mtriple=x86_64-apple-macosx < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +define void @indvar_expansion(i8* nocapture readonly %rowsptr) { +entry: + br label %for.cond + +; SCEVExpander used to create induction variables in the loop %for.cond while +; expanding the recurrence start value of loop strength reduced values from +; %vector.body. + +; CHECK-LABEL: indvar_expansion +; CHECK: for.cond: +; CHECK-NOT: phi i3 +; CHECK: br i1 {{.+}}, label %for.cond + +for.cond: + %indvars.iv44 = phi i64 [ %indvars.iv.next45, %for.cond ], [ 0, %entry ] + %cmp = icmp eq i8 undef, 0 + %indvars.iv.next45 = add nuw nsw i64 %indvars.iv44, 1 + br i1 %cmp, label %for.cond, label %for.cond2 + +for.cond2: + br i1 undef, label %for.cond2, label %for.body14.lr.ph + +for.body14.lr.ph: + %sext = shl i64 %indvars.iv44, 32 + %0 = ashr exact i64 %sext, 32 + %1 = sub i64 undef, %indvars.iv44 + %2 = and i64 %1, 4294967295 + %3 = add i64 %2, 1 + %fold = add i64 %1, 1 + %n.mod.vf = and i64 %fold, 7 + %n.vec = sub i64 %3, %n.mod.vf + %end.idx.rnd.down = add i64 %n.vec, %0 + br label %vector.body + +vector.body: + %index = phi i64 [ %index.next, %vector.body ], [ %0, %for.body14.lr.ph ] + %4 = getelementptr inbounds i8* %rowsptr, i64 %index + %5 = bitcast i8* %4 to <4 x i8>* + %wide.load = load <4 x i8>* %5, align 1 + %index.next = add i64 %index, 8 + %6 = icmp eq i64 %index.next, %end.idx.rnd.down + br i1 %6, label %for.end24, label %vector.body + +for.end24: + ret void +} diff --git a/test/Transforms/LoopStrengthReduce/X86/pr17473.ll b/test/Transforms/LoopStrengthReduce/X86/pr17473.ll index 4204abc7ca22..e7ebaa8ea61b 100644 --- a/test/Transforms/LoopStrengthReduce/X86/pr17473.ll +++ b/test/Transforms/LoopStrengthReduce/X86/pr17473.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -loop-reduce -S | FileCheck %s -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128" +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.9.0" ; LSR shouldn't normalize IV if it can't be denormalized to the original diff --git a/test/Transforms/LoopStrengthReduce/dont_insert_redundant_ops.ll b/test/Transforms/LoopStrengthReduce/dont_insert_redundant_ops.ll index 90051e3542c2..16bb508d2e27 100644 --- a/test/Transforms/LoopStrengthReduce/dont_insert_redundant_ops.ll +++ b/test/Transforms/LoopStrengthReduce/dont_insert_redundant_ops.ll @@ -1,5 +1,9 @@ ; Check that this test makes INDVAR and related stuff dead. -; RUN: opt < %s -loop-reduce -S | grep phi | count 2 +; RUN: opt < %s -loop-reduce -S | FileCheck %s + +; CHECK: phi +; CHECK: phi +; CHECK-NOT: phi declare i1 @pred() diff --git a/test/Transforms/LoopStrengthReduce/lsr-expand-quadratic.ll b/test/Transforms/LoopStrengthReduce/lsr-expand-quadratic.ll index 255cf41a8174..aa688d999e60 100644 --- a/test/Transforms/LoopStrengthReduce/lsr-expand-quadratic.ll +++ b/test/Transforms/LoopStrengthReduce/lsr-expand-quadratic.ll @@ -13,7 +13,7 @@ target triple = "x86_64-apple-macosx" ; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %test2.loop ], [ -16777216, %entry ] ; CHECK: %lsr.iv.next = add nsw i32 %lsr.iv, 16777216 ; -; CHECK=LABEL: for.end: +; CHECK-LABEL: for.end: ; CHECK: %sub.cond.us = sub nsw i32 %inc1115.us, %sub.us ; CHECK: %sext.us = mul i32 %lsr.iv.next, %sub.cond.us ; CHECK: %f = ashr i32 %sext.us, 24 diff --git a/test/Transforms/LoopStrengthReduce/pr18165.ll b/test/Transforms/LoopStrengthReduce/pr18165.ll index 89adef7bd49d..c38d6a625e88 100644 --- a/test/Transforms/LoopStrengthReduce/pr18165.ll +++ b/test/Transforms/LoopStrengthReduce/pr18165.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -loop-reduce -S | FileCheck %s -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128" +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.9.0" ; LSR shouldn't reuse IV if the resultant offset is not valid for the operand type. diff --git a/test/Transforms/LoopUnroll/PowerPC/lit.local.cfg b/test/Transforms/LoopUnroll/PowerPC/lit.local.cfg index 2e463005586f..5d33887ff0a4 100644 --- a/test/Transforms/LoopUnroll/PowerPC/lit.local.cfg +++ b/test/Transforms/LoopUnroll/PowerPC/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'PowerPC' in targets: +if not 'PowerPC' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/LoopUnroll/X86/lit.local.cfg b/test/Transforms/LoopUnroll/X86/lit.local.cfg new file mode 100644 index 000000000000..e71f3cc4c41e --- /dev/null +++ b/test/Transforms/LoopUnroll/X86/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'X86' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/LoopUnroll/X86/partial.ll b/test/Transforms/LoopUnroll/X86/partial.ll new file mode 100644 index 000000000000..a2b04c7d85f8 --- /dev/null +++ b/test/Transforms/LoopUnroll/X86/partial.ll @@ -0,0 +1,127 @@ +; RUN: opt < %s -S -loop-unroll -mcpu=nehalem | FileCheck %s +; RUN: opt < %s -S -loop-unroll -mcpu=core -unroll-runtime=0 | FileCheck -check-prefix=CHECK-NOUNRL %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @foo(i32* noalias nocapture readnone %ip, double %alpha, double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 { +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds double* %b, i64 %index + %1 = bitcast double* %0 to <2 x double>* + %wide.load = load <2 x double>* %1, align 8 + %.sum9 = or i64 %index, 2 + %2 = getelementptr double* %b, i64 %.sum9 + %3 = bitcast double* %2 to <2 x double>* + %wide.load8 = load <2 x double>* %3, align 8 + %4 = fadd <2 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00> + %5 = fadd <2 x double> %wide.load8, <double 1.000000e+00, double 1.000000e+00> + %6 = getelementptr inbounds double* %a, i64 %index + %7 = bitcast double* %6 to <2 x double>* + store <2 x double> %4, <2 x double>* %7, align 8 + %.sum10 = or i64 %index, 2 + %8 = getelementptr double* %a, i64 %.sum10 + %9 = bitcast double* %8 to <2 x double>* + store <2 x double> %5, <2 x double>* %9, align 8 + %index.next = add i64 %index, 4 + %10 = icmp eq i64 %index.next, 1600 + br i1 %10, label %for.end, label %vector.body + +; FIXME: We should probably unroll this loop by a factor of 2, but the cost +; model needs to be fixed to account for instructions likely to be folded +; as part of an addressing mode. +; CHECK-LABEL: @foo +; CHECK-NOUNRL-LABEL: @foo + +for.end: ; preds = %vector.body + ret void +} + +define void @bar(i32* noalias nocapture readnone %ip, double %alpha, double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 { +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %v0 = getelementptr inbounds double* %b, i64 %index + %v1 = bitcast double* %v0 to <2 x double>* + %wide.load = load <2 x double>* %v1, align 8 + %v4 = fadd <2 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00> + %v5 = fmul <2 x double> %v4, <double 8.000000e+00, double 8.000000e+00> + %v6 = getelementptr inbounds double* %a, i64 %index + %v7 = bitcast double* %v6 to <2 x double>* + store <2 x double> %v5, <2 x double>* %v7, align 8 + %index.next = add i64 %index, 2 + %v10 = icmp eq i64 %index.next, 1600 + br i1 %v10, label %for.end, label %vector.body + +; FIXME: We should probably unroll this loop by a factor of 2, but the cost +; model needs to first to fixed to account for instructions likely to be folded +; as part of an addressing mode. + +; CHECK-LABEL: @bar +; CHECK: fadd +; CHECK-NEXT: fmul +; CHECK: fadd +; CHECK-NEXT: fmul + +; CHECK-NOUNRL-LABEL: @bar +; CHECK-NOUNRL: fadd +; CHECK-NOUNRL-NEXT: fmul +; CHECK-NOUNRL-NOT: fadd + +for.end: ; preds = %vector.body + ret void +} + +define zeroext i16 @test1(i16* nocapture readonly %arr, i32 %n) #0 { +entry: + %cmp25 = icmp eq i32 %n, 0 + br i1 %cmp25, label %for.end, label %for.body + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %reduction.026 = phi i16 [ %add14, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i16* %arr, i64 %indvars.iv + %0 = load i16* %arrayidx, align 2 + %add = add i16 %0, %reduction.026 + %sext = mul i64 %indvars.iv, 12884901888 + %idxprom3 = ashr exact i64 %sext, 32 + %arrayidx4 = getelementptr inbounds i16* %arr, i64 %idxprom3 + %1 = load i16* %arrayidx4, align 2 + %add7 = add i16 %add, %1 + %sext28 = mul i64 %indvars.iv, 21474836480 + %idxprom10 = ashr exact i64 %sext28, 32 + %arrayidx11 = getelementptr inbounds i16* %arr, i64 %idxprom10 + %2 = load i16* %arrayidx11, align 2 + %add14 = add i16 %add7, %2 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + %reduction.0.lcssa = phi i16 [ 0, %entry ], [ %add14, %for.body ] + ret i16 %reduction.0.lcssa + +; This loop is too large to be partially unrolled (size=16) + +; CHECK-LABEL: @test1 +; CHECK: br +; CHECK: br +; CHECK: br +; CHECK: br +; CHECK-NOT: br + +; CHECK-NOUNRL-LABEL: @test1 +; CHECK-NOUNRL: br +; CHECK-NOUNRL: br +; CHECK-NOUNRL: br +; CHECK-NOUNRL: br +; CHECK-NOUNRL-NOT: br +} + +attributes #0 = { nounwind uwtable } + diff --git a/test/Transforms/LoopUnroll/loop-remarks.ll b/test/Transforms/LoopUnroll/loop-remarks.ll new file mode 100644 index 000000000000..ff3ac178363a --- /dev/null +++ b/test/Transforms/LoopUnroll/loop-remarks.ll @@ -0,0 +1,25 @@ +; RUN: opt < %s -S -loop-unroll -pass-remarks=loop-unroll -unroll-count=16 2>&1 | FileCheck -check-prefix=COMPLETE-UNROLL %s +; RUN: opt < %s -S -loop-unroll -pass-remarks=loop-unroll -unroll-count=4 2>&1 | FileCheck -check-prefix=PARTIAL-UNROLL %s + +; COMPLETE-UNROLL: remark: {{.*}}: completely unrolled loop with 16 iterations +; PARTIAL-UNROLL: remark: {{.*}}: unrolled loop by a factor of 4 + +define i32 @sum() { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %s.06 = phi i32 [ 0, %entry ], [ %add1, %for.body ] + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %add = add nsw i32 %i.05, 4 + %call = tail call i32 @baz(i32 %add) #2 + %add1 = add nsw i32 %call, %s.06 + %inc = add nsw i32 %i.05, 1 + %exitcond = icmp eq i32 %inc, 16 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i32 %add1 +} + +declare i32 @baz(i32) diff --git a/test/Transforms/LoopUnroll/pr18861.ll b/test/Transforms/LoopUnroll/pr18861.ll new file mode 100644 index 000000000000..62f26106afb2 --- /dev/null +++ b/test/Transforms/LoopUnroll/pr18861.ll @@ -0,0 +1,43 @@ +; RUN: opt < %s -loop-unroll -indvars -disable-output + +@b = external global i32, align 4 + +; Function Attrs: nounwind uwtable +define void @fn1() #0 { +entry: + br label %for.cond1thread-pre-split + +for.cond1thread-pre-split: ; preds = %for.inc8, %entry + %storemerge1 = phi i32 [ 0, %entry ], [ %inc9, %for.inc8 ] + br i1 undef, label %for.inc8, label %for.cond2.preheader.lr.ph + +for.cond2.preheader.lr.ph: ; preds = %for.cond1thread-pre-split + br label %for.cond2.preheader + +for.cond2.preheader: ; preds = %for.inc5, %for.cond2.preheader.lr.ph + br label %for.cond2 + +for.cond2: ; preds = %for.body3, %for.cond2.preheader + %storemerge = phi i32 [ %add, %for.body3 ], [ 0, %for.cond2.preheader ] + %cmp = icmp slt i32 %storemerge, 1 + br i1 %cmp, label %for.body3, label %for.inc5 + +for.body3: ; preds = %for.cond2 + %tobool4 = icmp eq i32 %storemerge, 0 + %add = add nsw i32 %storemerge, 1 + br i1 %tobool4, label %for.cond2, label %if.then + +if.then: ; preds = %for.body3 + store i32 %storemerge1, i32* @b, align 4 + ret void + +for.inc5: ; preds = %for.cond2 + br i1 undef, label %for.cond1.for.inc8_crit_edge, label %for.cond2.preheader + +for.cond1.for.inc8_crit_edge: ; preds = %for.inc5 + br label %for.inc8 + +for.inc8: ; preds = %for.cond1.for.inc8_crit_edge, %for.cond1thread-pre-split + %inc9 = add nsw i32 %storemerge1, 1 + br label %for.cond1thread-pre-split +} diff --git a/test/Transforms/LoopUnroll/runtime-loop.ll b/test/Transforms/LoopUnroll/runtime-loop.ll index d8bbea9f1073..a14087dcdce7 100644 --- a/test/Transforms/LoopUnroll/runtime-loop.ll +++ b/test/Transforms/LoopUnroll/runtime-loop.ll @@ -2,6 +2,12 @@ ; Tests for unrolling loops with run-time trip counts +; CHECK: %xtraiter = and i32 %n +; CHECK: %lcmp.mod = icmp ne i32 %xtraiter, 0 +; CHECK: %lcmp.overflow = icmp eq i32 %n, 0 +; CHECK: %lcmp.or = or i1 %lcmp.overflow, %lcmp.mod +; CHECK: br i1 %lcmp.or, label %unr.cmp + ; CHECK: unr.cmp{{.*}}: ; CHECK: for.body.unr{{.*}}: ; CHECK: for.body: diff --git a/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll b/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll new file mode 100644 index 000000000000..39da7fa70ade --- /dev/null +++ b/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll @@ -0,0 +1,69 @@ +; RUN: opt < %s -loop-unroll -S | FileCheck %s +; +; Verify that the unrolling pass removes existing loop unrolling metadata +; and adds a disable unrolling node after unrolling is complete. + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; #pragma clang loop vectorize(enable) unroll(enable) unroll_count(4) vectorize_width(8) +; +; Unroll metadata should be replaces with unroll(disable). Vectorize +; metadata should be untouched. +; +; CHECK-LABEL: @loop1( +; CHECK: br i1 {{.*}}, label {{.*}}, label {{.*}}, !llvm.loop ![[LOOP_1:.*]] +define void @loop1(i32* nocapture %a) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 64 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !1 + +for.end: ; preds = %for.body + ret void +} +!1 = metadata !{metadata !1, metadata !2, metadata !3, metadata !4, metadata !5} +!2 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} +!3 = metadata !{metadata !"llvm.loop.unroll.enable", i1 true} +!4 = metadata !{metadata !"llvm.loop.unroll.count", i32 4} +!5 = metadata !{metadata !"llvm.loop.vectorize.width", i32 8} + +; #pragma clang loop unroll(disable) +; +; Unroll metadata should not change. +; +; CHECK-LABEL: @loop2( +; CHECK: br i1 {{.*}}, label {{.*}}, label {{.*}}, !llvm.loop ![[LOOP_2:.*]] +define void @loop2(i32* nocapture %a) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 64 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !6 + +for.end: ; preds = %for.body + ret void +} +!6 = metadata !{metadata !6, metadata !7} +!7 = metadata !{metadata !"llvm.loop.unroll.enable", i1 false} + +; CHECK: ![[LOOP_1]] = metadata !{metadata ![[LOOP_1]], metadata ![[VEC_ENABLE:.*]], metadata ![[WIDTH_8:.*]], metadata ![[UNROLL_DISABLE:.*]]} +; CHECK: ![[VEC_ENABLE]] = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} +; CHECK: ![[WIDTH_8]] = metadata !{metadata !"llvm.loop.vectorize.width", i32 8} +; CHECK: ![[UNROLL_DISABLE]] = metadata !{metadata !"llvm.loop.unroll.enable", i1 false} +; CHECK: ![[LOOP_2]] = metadata !{metadata ![[LOOP_2]], metadata ![[UNROLL_DISABLE:.*]]} diff --git a/test/Transforms/LoopUnroll/unroll-pragmas.ll b/test/Transforms/LoopUnroll/unroll-pragmas.ll new file mode 100644 index 000000000000..e1b24e44b5ab --- /dev/null +++ b/test/Transforms/LoopUnroll/unroll-pragmas.ll @@ -0,0 +1,289 @@ +; RUN: opt < %s -loop-unroll -S | FileCheck %s +; RUN: opt < %s -loop-unroll -loop-unroll -S | FileCheck %s +; +; Run loop unrolling twice to verify that loop unrolling metadata is properly +; removed and further unrolling is disabled after the pass is run once. + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; loop4 contains a small loop which should be completely unrolled by +; the default unrolling heuristics. It serves as a control for the +; unroll(disable) pragma test loop4_with_disable. +; +; CHECK-LABEL: @loop4( +; CHECK-NOT: br i1 +define void @loop4(i32* nocapture %a) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 4 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} + +; #pragma clang loop unroll(disable) +; +; CHECK-LABEL: @loop4_with_disable( +; CHECK: store i32 +; CHECK-NOT: store i32 +; CHECK: br i1 +define void @loop4_with_disable(i32* nocapture %a) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 4 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !1 + +for.end: ; preds = %for.body + ret void +} +!1 = metadata !{metadata !1, metadata !2} +!2 = metadata !{metadata !"llvm.loop.unroll.enable", i1 false} + +; loop64 has a high enough count that it should *not* be unrolled by +; the default unrolling heuristic. It serves as the control for the +; unroll(enable) pragma test loop64_with_.* tests below. +; +; CHECK-LABEL: @loop64( +; CHECK: store i32 +; CHECK-NOT: store i32 +; CHECK: br i1 +define void @loop64(i32* nocapture %a) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 64 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} + +; #pragma clang loop unroll(enable) +; Loop should be fully unrolled. +; +; CHECK-LABEL: @loop64_with_enable( +; CHECK-NOT: br i1 +define void @loop64_with_enable(i32* nocapture %a) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 64 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !3 + +for.end: ; preds = %for.body + ret void +} +!3 = metadata !{metadata !3, metadata !4} +!4 = metadata !{metadata !"llvm.loop.unroll.enable", i1 true} + +; #pragma clang loop unroll_count(4) +; Loop should be unrolled 4 times. +; +; CHECK-LABEL: @loop64_with_count4( +; CHECK: store i32 +; CHECK: store i32 +; CHECK: store i32 +; CHECK: store i32 +; CHECK-NOT: store i32 +; CHECK: br i1 +define void @loop64_with_count4(i32* nocapture %a) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 64 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !5 + +for.end: ; preds = %for.body + ret void +} +!5 = metadata !{metadata !5, metadata !6} +!6 = metadata !{metadata !"llvm.loop.unroll.count", i32 4} + + +; #pragma clang loop unroll_count(enable) unroll_count(4) +; Loop should be unrolled 4 times. +; +; CHECK-LABEL: @loop64_with_enable_and_count4( +; CHECK: store i32 +; CHECK: store i32 +; CHECK: store i32 +; CHECK: store i32 +; CHECK-NOT: store i32 +; CHECK: br i1 +define void @loop64_with_enable_and_count4(i32* nocapture %a) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 64 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !7 + +for.end: ; preds = %for.body + ret void +} +!7 = metadata !{metadata !7, metadata !6, metadata !4} + +; #pragma clang loop unroll_count(enable) +; Full unrolling is requested, but loop has a dynamic trip count so +; no unrolling should occur. +; +; CHECK-LABEL: @dynamic_loop_with_enable( +; CHECK: store i32 +; CHECK-NOT: store i32 +; CHECK: br i1 +define void @dynamic_loop_with_enable(i32* nocapture %a, i32 %b) { +entry: + %cmp3 = icmp sgt i32 %b, 0 + br i1 %cmp3, label %for.body, label %for.end, !llvm.loop !8 + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %b + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !8 + +for.end: ; preds = %for.body, %entry + ret void +} +!8 = metadata !{metadata !8, metadata !4} + +; #pragma clang loop unroll_count(4) +; Loop has a dynamic trip count. Unrolling should occur, but no +; conditional branches can be removed. +; +; CHECK-LABEL: @dynamic_loop_with_count4( +; CHECK-NOT: store +; CHECK: br i1 +; CHECK: store +; CHECK: br i1 +; CHECK: store +; CHECK: br i1 +; CHECK: store +; CHECK: br i1 +; CHECK: store +; CHECK: br i1 +; CHECK-NOT: br i1 +define void @dynamic_loop_with_count4(i32* nocapture %a, i32 %b) { +entry: + %cmp3 = icmp sgt i32 %b, 0 + br i1 %cmp3, label %for.body, label %for.end, !llvm.loop !9 + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %b + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !9 + +for.end: ; preds = %for.body, %entry + ret void +} +!9 = metadata !{metadata !9, metadata !6} + +; #pragma clang loop unroll_count(1) +; Loop should not be unrolled +; +; CHECK-LABEL: @unroll_1( +; CHECK: store i32 +; CHECK-NOT: store i32 +; CHECK: br i1 +define void @unroll_1(i32* nocapture %a, i32 %b) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 4 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !10 + +for.end: ; preds = %for.body + ret void +} +!10 = metadata !{metadata !10, metadata !11} +!11 = metadata !{metadata !"llvm.loop.unroll.count", i32 1} + +; #pragma clang loop unroll(enable) +; Loop has very high loop count (1 million) and full unrolling was requested. +; Loop should unrolled up to the pragma threshold, but not completely. +; +; CHECK-LABEL: @unroll_1M( +; CHECK: store i32 +; CHECK: store i32 +; CHECK: br i1 +define void @unroll_1M(i32* nocapture %a, i32 %b) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1000000 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !12 + +for.end: ; preds = %for.body + ret void +} +!12 = metadata !{metadata !12, metadata !4} diff --git a/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll b/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll new file mode 100644 index 000000000000..9962c3d76a66 --- /dev/null +++ b/test/Transforms/LoopVectorize/AArch64/aarch64-unroll.ll @@ -0,0 +1,42 @@ +; RUN: opt < %s -loop-vectorize -mtriple=aarch64-none-linux-gnu -mattr=+neon -S | FileCheck %s +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" + +; Function Attrs: nounwind +define i32* @array_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32* %c, i32 %size) { +;CHECK-LABEL: array_add +;CHECK: load <4 x i32> +;CHECK: load <4 x i32> +;CHECK: load <4 x i32> +;CHECK: load <4 x i32> +;CHECK: add nsw <4 x i32> +;CHECK: add nsw <4 x i32> +;CHECK: store <4 x i32> +;CHECK: store <4 x i32> +;CHECK: ret +entry: + %cmp10 = icmp sgt i32 %size, 0 + br i1 %cmp10, label %for.body.preheader, label %for.end + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %arrayidx2 = getelementptr inbounds i32* %b, i64 %indvars.iv + %1 = load i32* %arrayidx2, align 4 + %add = add nsw i32 %1, %0 + %arrayidx4 = getelementptr inbounds i32* %c, i64 %indvars.iv + store i32 %add, i32* %arrayidx4, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %size + br i1 %exitcond, label %for.end.loopexit, label %for.body + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret i32* %c +} diff --git a/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll b/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll new file mode 100644 index 000000000000..f8eb3ed1f35f --- /dev/null +++ b/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll @@ -0,0 +1,42 @@ +; RUN: opt < %s -loop-vectorize -mtriple=arm64-none-linux-gnu -mattr=+neon -S | FileCheck %s +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" + +; Function Attrs: nounwind +define i32* @array_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32* %c, i32 %size) { +;CHECK-LABEL: array_add +;CHECK: load <4 x i32> +;CHECK: load <4 x i32> +;CHECK: load <4 x i32> +;CHECK: load <4 x i32> +;CHECK: add nsw <4 x i32> +;CHECK: add nsw <4 x i32> +;CHECK: store <4 x i32> +;CHECK: store <4 x i32> +;CHECK: ret +entry: + %cmp10 = icmp sgt i32 %size, 0 + br i1 %cmp10, label %for.body.preheader, label %for.end + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %arrayidx2 = getelementptr inbounds i32* %b, i64 %indvars.iv + %1 = load i32* %arrayidx2, align 4 + %add = add nsw i32 %1, %0 + %arrayidx4 = getelementptr inbounds i32* %c, i64 %indvars.iv + store i32 %add, i32* %arrayidx4, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %size + br i1 %exitcond, label %for.end.loopexit, label %for.body + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret i32* %c +} diff --git a/test/Transforms/LoopVectorize/AArch64/gather-cost.ll b/test/Transforms/LoopVectorize/AArch64/gather-cost.ll new file mode 100644 index 000000000000..bb285382e53c --- /dev/null +++ b/test/Transforms/LoopVectorize/AArch64/gather-cost.ll @@ -0,0 +1,85 @@ +; RUN: opt -loop-vectorize -mtriple=arm64-apple-ios -S -mcpu=cyclone < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128" + +@kernel = global [512 x float] zeroinitializer, align 16 +@kernel2 = global [512 x float] zeroinitializer, align 16 +@kernel3 = global [512 x float] zeroinitializer, align 16 +@kernel4 = global [512 x float] zeroinitializer, align 16 +@src_data = global [1536 x float] zeroinitializer, align 16 +@r_ = global i8 0, align 1 +@g_ = global i8 0, align 1 +@b_ = global i8 0, align 1 + +; We don't want to vectorize most loops containing gathers because they are +; expensive. +; Make sure we don't vectorize it. +; CHECK-NOT: x float> + +define void @_Z4testmm(i64 %size, i64 %offset) { +entry: + %cmp53 = icmp eq i64 %size, 0 + br i1 %cmp53, label %for.end, label %for.body.lr.ph + +for.body.lr.ph: + br label %for.body + +for.body: + %r.057 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add10, %for.body ] + %g.056 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add20, %for.body ] + %v.055 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] + %b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ] + %add = add i64 %v.055, %offset + %mul = mul i64 %add, 3 + %arrayidx = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %mul + %0 = load float* %arrayidx, align 4 + %arrayidx2 = getelementptr inbounds [512 x float]* @kernel, i64 0, i64 %v.055 + %1 = load float* %arrayidx2, align 4 + %mul3 = fmul fast float %0, %1 + %arrayidx4 = getelementptr inbounds [512 x float]* @kernel2, i64 0, i64 %v.055 + %2 = load float* %arrayidx4, align 4 + %mul5 = fmul fast float %mul3, %2 + %arrayidx6 = getelementptr inbounds [512 x float]* @kernel3, i64 0, i64 %v.055 + %3 = load float* %arrayidx6, align 4 + %mul7 = fmul fast float %mul5, %3 + %arrayidx8 = getelementptr inbounds [512 x float]* @kernel4, i64 0, i64 %v.055 + %4 = load float* %arrayidx8, align 4 + %mul9 = fmul fast float %mul7, %4 + %add10 = fadd fast float %r.057, %mul9 + %arrayidx.sum = add i64 %mul, 1 + %arrayidx11 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum + %5 = load float* %arrayidx11, align 4 + %mul13 = fmul fast float %1, %5 + %mul15 = fmul fast float %2, %mul13 + %mul17 = fmul fast float %3, %mul15 + %mul19 = fmul fast float %4, %mul17 + %add20 = fadd fast float %g.056, %mul19 + %arrayidx.sum52 = add i64 %mul, 2 + %arrayidx21 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum52 + %6 = load float* %arrayidx21, align 4 + %mul23 = fmul fast float %1, %6 + %mul25 = fmul fast float %2, %mul23 + %mul27 = fmul fast float %3, %mul25 + %mul29 = fmul fast float %4, %mul27 + %add30 = fadd fast float %b.054, %mul29 + %inc = add i64 %v.055, 1 + %exitcond = icmp ne i64 %inc, %size + br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge + +for.cond.for.end_crit_edge: + %add30.lcssa = phi float [ %add30, %for.body ] + %add20.lcssa = phi float [ %add20, %for.body ] + %add10.lcssa = phi float [ %add10, %for.body ] + %phitmp = fptoui float %add10.lcssa to i8 + %phitmp60 = fptoui float %add20.lcssa to i8 + %phitmp61 = fptoui float %add30.lcssa to i8 + br label %for.end + +for.end: + %r.0.lcssa = phi i8 [ %phitmp, %for.cond.for.end_crit_edge ], [ 0, %entry ] + %g.0.lcssa = phi i8 [ %phitmp60, %for.cond.for.end_crit_edge ], [ 0, %entry ] + %b.0.lcssa = phi i8 [ %phitmp61, %for.cond.for.end_crit_edge ], [ 0, %entry ] + store i8 %r.0.lcssa, i8* @r_, align 1 + store i8 %g.0.lcssa, i8* @g_, align 1 + store i8 %b.0.lcssa, i8* @b_, align 1 + ret void +} diff --git a/test/Transforms/LoopVectorize/AArch64/lit.local.cfg b/test/Transforms/LoopVectorize/AArch64/lit.local.cfg new file mode 100644 index 000000000000..937cffb2c119 --- /dev/null +++ b/test/Transforms/LoopVectorize/AArch64/lit.local.cfg @@ -0,0 +1,5 @@ +config.suffixes = ['.ll'] + +if not 'AArch64' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/LoopVectorize/ARM/arm-unroll.ll b/test/Transforms/LoopVectorize/ARM/arm-unroll.ll index 39363ab2d802..8843fc2d2b1a 100644 --- a/test/Transforms/LoopVectorize/ARM/arm-unroll.ll +++ b/test/Transforms/LoopVectorize/ARM/arm-unroll.ll @@ -1,5 +1,6 @@ ; RUN: opt < %s -loop-vectorize -mtriple=thumbv7-apple-ios3.0.0 -S | FileCheck %s ; RUN: opt < %s -loop-vectorize -mtriple=thumbv7-apple-ios3.0.0 -mcpu=swift -S | FileCheck %s --check-prefix=SWIFT +; RUN: opt < %s -loop-vectorize -force-vector-width=1 -mtriple=thumbv7-apple-ios3.0.0 -mcpu=swift -S | FileCheck %s --check-prefix=SWIFTUNROLL target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios3.0.0" @@ -30,3 +31,41 @@ define i32 @foo(i32* nocapture %A, i32 %n) nounwind readonly ssp { %sum.0.lcssa = phi i32 [ 0, %0 ], [ %4, %.lr.ph ] ret i32 %sum.0.lcssa } + +; Verify the register limit. On arm we don't have 16 allocatable registers. +;SWIFTUNROLL-LABEL: @register_limit( +;SWIFTUNROLL: load i32 +;SWIFTUNROLL-NOT: load i32 +define i32 @register_limit(i32* nocapture %A, i32 %n) { + %1 = icmp sgt i32 %n, 0 + br i1 %1, label %.lr.ph, label %._crit_edge + +.lr.ph: + %i.02 = phi i32 [ %5, %.lr.ph ], [ 0, %0 ] + %sum.01 = phi i32 [ %4, %.lr.ph ], [ 0, %0 ] + %sum.02 = phi i32 [ %6, %.lr.ph ], [ 0, %0 ] + %sum.03 = phi i32 [ %7, %.lr.ph ], [ 0, %0 ] + %sum.04 = phi i32 [ %8, %.lr.ph ], [ 0, %0 ] + %sum.05 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ] + %sum.06 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ] + %2 = getelementptr inbounds i32* %A, i32 %i.02 + %3 = load i32* %2, align 4 + %4 = add nsw i32 %3, %sum.01 + %5 = add nsw i32 %i.02, 1 + %6 = add nsw i32 %3, %sum.02 + %7 = add nsw i32 %3, %sum.03 + %8 = add nsw i32 %3, %sum.04 + %9 = add nsw i32 %3, %sum.05 + %10 = add nsw i32 %3, %sum.05 + %exitcond = icmp eq i32 %5, %n + br i1 %exitcond, label %._crit_edge, label %.lr.ph + +._crit_edge: ; preds = %.lr.ph, %0 + %sum.0.lcssa = phi i32 [ 0, %0 ], [ %4, %.lr.ph ] + %sum.1.lcssa = phi i32 [ 0, %0 ], [ %6, %.lr.ph ] + %sum.2.lcssa = phi i32 [ 0, %0 ], [ %7, %.lr.ph ] + %sum.4.lcssa = phi i32 [ 0, %0 ], [ %8, %.lr.ph ] + %sum.5.lcssa = phi i32 [ 0, %0 ], [ %9, %.lr.ph ] + %sum.6.lcssa = phi i32 [ 0, %0 ], [ %10, %.lr.ph ] + ret i32 %sum.0.lcssa +} diff --git a/test/Transforms/LoopVectorize/ARM/lit.local.cfg b/test/Transforms/LoopVectorize/ARM/lit.local.cfg index 8a3ba96497e7..98c6700c209d 100644 --- a/test/Transforms/LoopVectorize/ARM/lit.local.cfg +++ b/test/Transforms/LoopVectorize/ARM/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'ARM' in targets: +if not 'ARM' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/LoopVectorize/PowerPC/lit.local.cfg b/test/Transforms/LoopVectorize/PowerPC/lit.local.cfg new file mode 100644 index 000000000000..5d33887ff0a4 --- /dev/null +++ b/test/Transforms/LoopVectorize/PowerPC/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'PowerPC' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll b/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll new file mode 100644 index 000000000000..6cd9c4d610b5 --- /dev/null +++ b/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll @@ -0,0 +1,51 @@ +; RUN: opt < %s -mcpu=pwr7 -mattr=+vsx -loop-vectorize -instcombine -S | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.GlobalData = type { [32000 x float], [3 x i32], [4 x i8], [32000 x float], [5 x i32], [12 x i8], [32000 x float], [7 x i32], [4 x i8], [32000 x float], [11 x i32], [4 x i8], [32000 x float], [13 x i32], [12 x i8], [256 x [256 x float]], [17 x i32], [12 x i8], [256 x [256 x float]], [19 x i32], [4 x i8], [256 x [256 x float]], [23 x i32], [4 x i8], [256 x [256 x float]] } + +@global_data = external global %struct.GlobalData, align 16 +@ntimes = external hidden unnamed_addr global i32, align 4 + +define signext i32 @s173() #0 { +entry: + %0 = load i32* @ntimes, align 4 + %cmp21 = icmp sgt i32 %0, 0 + br i1 %cmp21, label %for.cond1.preheader, label %for.end12 + +for.cond1.preheader: ; preds = %for.end, %entry + %nl.022 = phi i32 [ %inc11, %for.end ], [ 0, %entry ] + br label %for.body3 + +for.body3: ; preds = %for.body3, %for.cond1.preheader + %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body3 ] + %arrayidx = getelementptr inbounds %struct.GlobalData* @global_data, i64 0, i32 0, i64 %indvars.iv + %1 = load float* %arrayidx, align 4 + %arrayidx5 = getelementptr inbounds %struct.GlobalData* @global_data, i64 0, i32 3, i64 %indvars.iv + %2 = load float* %arrayidx5, align 4 + %add = fadd float %1, %2 + %3 = add nsw i64 %indvars.iv, 16000 + %arrayidx8 = getelementptr inbounds %struct.GlobalData* @global_data, i64 0, i32 0, i64 %3 + store float %add, float* %arrayidx8, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 16000 + br i1 %exitcond, label %for.end, label %for.body3 + +for.end: ; preds = %for.body3 + %inc11 = add nsw i32 %nl.022, 1 + %4 = load i32* @ntimes, align 4 + %mul = mul nsw i32 %4, 10 + %cmp = icmp slt i32 %inc11, %mul + br i1 %cmp, label %for.cond1.preheader, label %for.end12 + +for.end12: ; preds = %for.end, %entry + ret i32 0 + +; CHECK-LABEL: @s173 +; CHECK: load <4 x float>* +; CHECK: add i64 %index, 16000 +; CHECK: ret i32 0 +} + +attributes #0 = { nounwind } + diff --git a/test/Transforms/LoopVectorize/X86/already-vectorized.ll b/test/Transforms/LoopVectorize/X86/already-vectorized.ll index 885418c0fdd9..9c69ba87f392 100644 --- a/test/Transforms/LoopVectorize/X86/already-vectorized.ll +++ b/test/Transforms/LoopVectorize/X86/already-vectorized.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -debug-only=loop-vectorize -O3 -S 2>&1 | FileCheck %s +; RUN: opt < %s -disable-loop-unrolling -debug-only=loop-vectorize -O3 -S 2>&1 | FileCheck %s ; REQUIRES: asserts ; We want to make sure that we don't even try to vectorize loops again ; The vectorizer used to mark the un-vectorized loop only as already vectorized @@ -40,7 +40,7 @@ for.end: ; preds = %for.body ; Now, we check for the Hint metadata ; CHECK: [[vect]] = metadata !{metadata [[vect]], metadata [[width:![0-9]+]], metadata [[unroll:![0-9]+]]} -; CHECK: [[width]] = metadata !{metadata !"llvm.vectorizer.width", i32 1} -; CHECK: [[unroll]] = metadata !{metadata !"llvm.vectorizer.unroll", i32 1} +; CHECK: [[width]] = metadata !{metadata !"llvm.loop.vectorize.width", i32 1} +; CHECK: [[unroll]] = metadata !{metadata !"llvm.loop.interleave.count", i32 1} ; CHECK: [[scalar]] = metadata !{metadata [[scalar]], metadata [[width]], metadata [[unroll]]} diff --git a/test/Transforms/LoopVectorize/X86/avx512.ll b/test/Transforms/LoopVectorize/X86/avx512.ll new file mode 100644 index 000000000000..a2208668177d --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/avx512.ll @@ -0,0 +1,35 @@ +; RUN: opt -mattr=+avx512f --loop-vectorize -S < %s | llc -mattr=+avx512f | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +; Verify that we generate 512-bit wide vectors for a basic integer memset +; loop. + +; CHECK-LABEL: f: +; CHECK: vmovdqu32 %zmm{{.}}, ( +; CHECK-NOT: %ymm + +define void @f(i32* %a, i32 %n) { +entry: + %cmp4 = icmp sgt i32 %n, 0 + br i1 %cmp4, label %for.body.preheader, label %for.end + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + store i32 %n, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end.loopexit, label %for.body + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret void +} diff --git a/test/Transforms/LoopVectorize/X86/fp32_to_uint32-cost-model.ll b/test/Transforms/LoopVectorize/X86/fp32_to_uint32-cost-model.ll new file mode 100644 index 000000000000..529ed883c3b4 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/fp32_to_uint32-cost-model.ll @@ -0,0 +1,39 @@ +; RUN: opt < %s -mcpu=core-avx2 -loop-vectorize -S | llc -mcpu=core-avx2 | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx" + +@float_array = common global [10000 x float] zeroinitializer, align 16 +@unsigned_array = common global [10000 x i32] zeroinitializer, align 16 + +; If we need to scalarize the fptoui and then use inserts to build up the +; vector again, then there is certainly no value in going 256-bit wide. +; CHECK-NOT: vinserti128 + +define void @convert(i32 %N) { +entry: + %0 = icmp eq i32 %N, 0 + br i1 %0, label %for.end, label %for.body.preheader + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds [10000 x float]* @float_array, i64 0, i64 %indvars.iv + %1 = load float* %arrayidx, align 4 + %conv = fptoui float %1 to i32 + %arrayidx2 = getelementptr inbounds [10000 x i32]* @unsigned_array, i64 0, i64 %indvars.iv + store i32 %conv, i32* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %N + br i1 %exitcond, label %for.end.loopexit, label %for.body + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret void +} + diff --git a/test/Transforms/LoopVectorize/X86/fp64_to_uint32-cost-model.ll b/test/Transforms/LoopVectorize/X86/fp64_to_uint32-cost-model.ll new file mode 100644 index 000000000000..ef3e3bec793a --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/fp64_to_uint32-cost-model.ll @@ -0,0 +1,40 @@ +; RUN: opt < %s -mcpu=core-avx2 -loop-vectorize -S | llc -mcpu=core-avx2 | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx" + +@n = global i32 10000, align 4 +@double_array = common global [10000 x double] zeroinitializer, align 16 +@unsigned_array = common global [10000 x i32] zeroinitializer, align 16 + +; If we need to scalarize the fptoui and then use inserts to build up the +; vector again, then there is certainly no value in going 256-bit wide. +; CHECK-NOT: vpinsrd + +define void @convert() { +entry: + %0 = load i32* @n, align 4 + %cmp4 = icmp eq i32 %0, 0 + br i1 %cmp4, label %for.end, label %for.body.preheader + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds [10000 x double]* @double_array, i64 0, i64 %indvars.iv + %1 = load double* %arrayidx, align 8 + %conv = fptoui double %1 to i32 + %arrayidx2 = getelementptr inbounds [10000 x i32]* @unsigned_array, i64 0, i64 %indvars.iv + store i32 %conv, i32* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %2 = trunc i64 %indvars.iv.next to i32 + %cmp = icmp ult i32 %2, %0 + br i1 %cmp, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret void +} diff --git a/test/Transforms/LoopVectorize/X86/fp_to_sint8-cost-model.ll b/test/Transforms/LoopVectorize/X86/fp_to_sint8-cost-model.ll new file mode 100644 index 000000000000..23e62275ce04 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/fp_to_sint8-cost-model.ll @@ -0,0 +1,25 @@ +; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -S -debug-only=loop-vectorize 2>&1 | FileCheck %s +; REQUIRES: asserts + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + + +; CHECK: cost of 7 for VF 8 For instruction: %conv = fptosi float %tmp to i8 +define void @float_to_sint8_cost(i8* noalias nocapture %a, float* noalias nocapture readonly %b) nounwind { +entry: + br label %for.body +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv + %tmp = load float* %arrayidx, align 4 + %conv = fptosi float %tmp to i8 + %arrayidx2 = getelementptr inbounds i8* %a, i64 %indvars.iv + store i8 %conv, i8* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 256 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret void +} diff --git a/test/Transforms/LoopVectorize/X86/lit.local.cfg b/test/Transforms/LoopVectorize/X86/lit.local.cfg index ba763cf03ffc..e71f3cc4c41e 100644 --- a/test/Transforms/LoopVectorize/X86/lit.local.cfg +++ b/test/Transforms/LoopVectorize/X86/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/LoopVectorize/X86/metadata-enable.ll b/test/Transforms/LoopVectorize/X86/metadata-enable.ll new file mode 100644 index 000000000000..8e0ca417b404 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/metadata-enable.ll @@ -0,0 +1,176 @@ +; RUN: opt < %s -mcpu=corei7 -O1 -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O1 +; RUN: opt < %s -mcpu=corei7 -O2 -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O2 +; RUN: opt < %s -mcpu=corei7 -O3 -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O3 +; RUN: opt < %s -mcpu=corei7 -Os -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=Os +; RUN: opt < %s -mcpu=corei7 -Oz -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=Oz +; RUN: opt < %s -mcpu=corei7 -O1 -vectorize-loops -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O1VEC +; RUN: opt < %s -mcpu=corei7 -Oz -vectorize-loops -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=OzVEC +; RUN: opt < %s -mcpu=corei7 -O1 -loop-vectorize -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O1VEC2 +; RUN: opt < %s -mcpu=corei7 -Oz -loop-vectorize -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=OzVEC2 +; RUN: opt < %s -mcpu=corei7 -O3 -disable-loop-vectorization -S -unroll-allow-partial=0 | FileCheck %s --check-prefix=O3DIS + +; This file tests the llvm.loop.vectorize.enable metadata forcing +; vectorization even when optimization levels are too low, or when +; vectorization is disabled. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; O1-LABEL: @enabled( +; O1: store <4 x i32> +; O1: ret i32 +; O2-LABEL: @enabled( +; O2: store <4 x i32> +; O2: ret i32 +; O3-LABEL: @enabled( +; O3: store <4 x i32> +; O3: ret i32 +; Pragma always wins! +; O3DIS-LABEL: @enabled( +; O3DIS: store <4 x i32> +; O3DIS: ret i32 +; Os-LABEL: @enabled( +; Os: store <4 x i32> +; Os: ret i32 +; Oz-LABEL: @enabled( +; Oz: store <4 x i32> +; Oz: ret i32 +; O1VEC-LABEL: @enabled( +; O1VEC: store <4 x i32> +; O1VEC: ret i32 +; OzVEC-LABEL: @enabled( +; OzVEC: store <4 x i32> +; OzVEC: ret i32 +; O1VEC2-LABEL: @enabled( +; O1VEC2: store <4 x i32> +; O1VEC2: ret i32 +; OzVEC2-LABEL: @enabled( +; OzVEC2: store <4 x i32> +; OzVEC2: ret i32 + +define i32 @enabled(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32 %N) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %N + %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv + store i32 %add, i32* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 32 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !0 + +for.end: ; preds = %for.body + %1 = load i32* %a, align 4 + ret i32 %1 +} + +; O1-LABEL: @nopragma( +; O1-NOT: store <4 x i32> +; O1: ret i32 +; O2-LABEL: @nopragma( +; O2: store <4 x i32> +; O2: ret i32 +; O3-LABEL: @nopragma( +; O3: store <4 x i32> +; O3: ret i32 +; O3DIS-LABEL: @nopragma( +; O3DIS-NOT: store <4 x i32> +; O3DIS: ret i32 +; Os-LABEL: @nopragma( +; Os: store <4 x i32> +; Os: ret i32 +; Oz-LABEL: @nopragma( +; Oz-NOT: store <4 x i32> +; Oz: ret i32 +; O1VEC-LABEL: @nopragma( +; O1VEC: store <4 x i32> +; O1VEC: ret i32 +; OzVEC-LABEL: @nopragma( +; OzVEC: store <4 x i32> +; OzVEC: ret i32 +; O1VEC2-LABEL: @nopragma( +; O1VEC2: store <4 x i32> +; O1VEC2: ret i32 +; OzVEC2-LABEL: @nopragma( +; OzVEC2: store <4 x i32> +; OzVEC2: ret i32 + +define i32 @nopragma(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32 %N) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %N + %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv + store i32 %add, i32* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 32 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + %1 = load i32* %a, align 4 + ret i32 %1 +} + +; O1-LABEL: @disabled( +; O1-NOT: store <4 x i32> +; O1: ret i32 +; O2-LABEL: @disabled( +; O2-NOT: store <4 x i32> +; O2: ret i32 +; O3-LABEL: @disabled( +; O3-NOT: store <4 x i32> +; O3: ret i32 +; O3DIS-LABEL: @disabled( +; O3DIS-NOT: store <4 x i32> +; O3DIS: ret i32 +; Os-LABEL: @disabled( +; Os-NOT: store <4 x i32> +; Os: ret i32 +; Oz-LABEL: @disabled( +; Oz-NOT: store <4 x i32> +; Oz: ret i32 +; O1VEC-LABEL: @disabled( +; O1VEC-NOT: store <4 x i32> +; O1VEC: ret i32 +; OzVEC-LABEL: @disabled( +; OzVEC-NOT: store <4 x i32> +; OzVEC: ret i32 +; O1VEC2-LABEL: @disabled( +; O1VEC2-NOT: store <4 x i32> +; O1VEC2: ret i32 +; OzVEC2-LABEL: @disabled( +; OzVEC2-NOT: store <4 x i32> +; OzVEC2: ret i32 + +define i32 @disabled(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32 %N) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %N + %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv + store i32 %add, i32* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 32 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !2 + +for.end: ; preds = %for.body + %1 = load i32* %a, align 4 + ret i32 %1 +} + +!0 = metadata !{metadata !0, metadata !1} +!1 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 1} +!2 = metadata !{metadata !2, metadata !3} +!3 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 0} diff --git a/test/Transforms/LoopVectorize/X86/small-size.ll b/test/Transforms/LoopVectorize/X86/small-size.ll index 14ac417bb573..bcf16aa5db13 100644 --- a/test/Transforms/LoopVectorize/X86/small-size.ll +++ b/test/Transforms/LoopVectorize/X86/small-size.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s +; RUN: opt < %s -basicaa -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -loop-vectorize-with-block-frequency -dce -instcombine -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" @@ -115,6 +115,31 @@ define void @example3(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture ret void } +; N is unknown, we need a tail. Can't vectorize because the loop is cold. +;CHECK-LABEL: @example4( +;CHECK-NOT: <4 x i32> +;CHECK: ret void +define void @example4(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture %q) { + %1 = icmp eq i32 %n, 0 + br i1 %1, label %._crit_edge, label %.lr.ph, !prof !0 + +.lr.ph: ; preds = %0, %.lr.ph + %.05 = phi i32 [ %2, %.lr.ph ], [ %n, %0 ] + %.014 = phi i32* [ %5, %.lr.ph ], [ %p, %0 ] + %.023 = phi i32* [ %3, %.lr.ph ], [ %q, %0 ] + %2 = add nsw i32 %.05, -1 + %3 = getelementptr inbounds i32* %.023, i64 1 + %4 = load i32* %.023, align 16 + %5 = getelementptr inbounds i32* %.014, i64 1 + store i32 %4, i32* %.014, align 16 + %6 = icmp eq i32 %2, 0 + br i1 %6, label %._crit_edge, label %.lr.ph + +._crit_edge: ; preds = %.lr.ph, %0 + ret void +} + +!0 = metadata !{metadata !"branch_weights", i32 64, i32 4} ; We can't vectorize this one because we need a runtime ptr check. ;CHECK-LABEL: @example23( diff --git a/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll b/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll new file mode 100644 index 000000000000..86c32b2d2ee4 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/uint64_to_fp64-cost-model.ll @@ -0,0 +1,26 @@ +; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -S -debug-only=loop-vectorize 2>&1 | FileCheck %s +; REQUIRES: asserts + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + + +; CHECK: cost of 20 for VF 2 For instruction: %conv = uitofp i64 %tmp to double +; CHECK: cost of 40 for VF 4 For instruction: %conv = uitofp i64 %tmp to double +define void @uint64_to_double_cost(i64* noalias nocapture %a, double* noalias nocapture readonly %b) nounwind { +entry: + br label %for.body +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i64* %a, i64 %indvars.iv + %tmp = load i64* %arrayidx, align 4 + %conv = uitofp i64 %tmp to double + %arrayidx2 = getelementptr inbounds double* %b, i64 %indvars.iv + store double %conv, double* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 256 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret void +} diff --git a/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll b/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll index ea107dc4dc51..d5024bb13210 100644 --- a/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll +++ b/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll @@ -1,13 +1,26 @@ -; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -force-vector-width=4 -force-vector-unroll=0 -dce -S | FileCheck %s +; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -force-vector-width=4 -force-vector-unroll=0 -dce -S \ +; RUN: | FileCheck %s --check-prefix=CHECK-VECTOR +; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -force-vector-width=1 -force-vector-unroll=0 -dce -S \ +; RUN: | FileCheck %s --check-prefix=CHECK-SCALAR target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" -;CHECK-LABEL: @foo( -;CHECK: load <4 x i32> -;CHECK-NOT: load <4 x i32> -;CHECK: store <4 x i32> -;CHECK-NOT: store <4 x i32> -;CHECK: ret + +; We don't unroll this loop because it has a small constant trip count. +; +; CHECK-VECTOR-LABEL: @foo( +; CHECK-VECTOR: load <4 x i32> +; CHECK-VECTOR-NOT: load <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR-NOT: store <4 x i32> +; CHECK-VECTOR: ret +; +; CHECK-SCALAR-LABEL: @foo( +; CHECK-SCALAR: load i32* +; CHECK-SCALAR-NOT: load i32* +; CHECK-SCALAR: store i32 +; CHECK-SCALAR-NOT: store i32 +; CHECK-SCALAR: ret define i32 @foo(i32* nocapture %A) nounwind uwtable ssp { br label %1 @@ -26,10 +39,18 @@ define i32 @foo(i32* nocapture %A) nounwind uwtable ssp { ret i32 undef } -;CHECK-LABEL: @bar( -;CHECK: store <4 x i32> -;CHECK: store <4 x i32> -;CHECK: ret +; But this is a good small loop to unroll as we don't know of a bound on its +; trip count. +; +; CHECK-VECTOR-LABEL: @bar( +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: store <4 x i32> +; CHECK-VECTOR: ret +; +; CHECK-SCALAR-LABEL: @bar( +; CHECK-SCALAR: store i32 +; CHECK-SCALAR: store i32 +; CHECK-SCALAR: ret define i32 @bar(i32* nocapture %A, i32 %n) nounwind uwtable ssp { %1 = icmp sgt i32 %n, 0 br i1 %1, label %.lr.ph, label %._crit_edge @@ -48,3 +69,32 @@ define i32 @bar(i32* nocapture %A, i32 %n) nounwind uwtable ssp { ._crit_edge: ; preds = %.lr.ph, %0 ret i32 undef } + +; Also unroll if we need a runtime check but it was going to be added for +; vectorization anyways. +; CHECK-VECTOR-LABEL: @runtime_chk( +; CHECK-VECTOR: store <4 x float> +; CHECK-VECTOR: store <4 x float> +; +; But not if the unrolling would introduce the runtime check. +; CHECK-SCALAR-LABEL: @runtime_chk( +; CHECK-SCALAR: store float +; CHECK-SCALAR-NOT: store float +define void @runtime_chk(float* %A, float* %B, float %N) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %mul = fmul float %0, %N + %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv + store float %mul, float* %arrayidx2, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 256 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret void +} diff --git a/test/Transforms/LoopVectorize/X86/vect.omp.force.ll b/test/Transforms/LoopVectorize/X86/vect.omp.force.ll new file mode 100644 index 000000000000..074313bde6f5 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/vect.omp.force.ll @@ -0,0 +1,93 @@ +; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -debug-only=loop-vectorize -stats -S 2>&1 | FileCheck %s +; REQUIRES: asserts + +; CHECK: LV: Loop hints: force=enabled +; CHECK: LV: Loop hints: force=? +; No more loops in the module +; CHECK-NOT: LV: Loop hints: force= +; CHECK: 2 loop-vectorize - Number of loops analyzed for vectorization +; CHECK: 1 loop-vectorize - Number of loops vectorized + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; +; The source code for the test: +; +; #include <math.h> +; void foo(float* restrict A, float * restrict B, int size) +; { +; for (int i = 0; i < size; ++i) A[i] = sinf(B[i]); +; } +; + +; +; This loop will be vectorized, although the scalar cost is lower than any of vector costs, but vectorization is explicitly forced in metadata. +; + +define void @vectorized(float* noalias nocapture %A, float* noalias nocapture %B, i32 %size) { +entry: + %cmp6 = icmp sgt i32 %size, 0 + br i1 %cmp6, label %for.body.preheader, label %for.end + +for.body.preheader: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1 + %call = tail call float @llvm.sin.f32(float %0) + %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv + store float %call, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %size + br i1 %exitcond, label %for.end.loopexit, label %for.body, !llvm.loop !1 + +for.end.loopexit: + br label %for.end + +for.end: + ret void +} + +!1 = metadata !{metadata !1, metadata !2} +!2 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} + +; +; This method will not be vectorized, as scalar cost is lower than any of vector costs. +; + +define void @not_vectorized(float* noalias nocapture %A, float* noalias nocapture %B, i32 %size) { +entry: + %cmp6 = icmp sgt i32 %size, 0 + br i1 %cmp6, label %for.body.preheader, label %for.end + +for.body.preheader: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3 + %call = tail call float @llvm.sin.f32(float %0) + %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv + store float %call, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %size + br i1 %exitcond, label %for.end.loopexit, label %for.body, !llvm.loop !3 + +for.end.loopexit: + br label %for.end + +for.end: + ret void +} + +declare float @llvm.sin.f32(float) nounwind readnone + +; Dummy metadata +!3 = metadata !{metadata !3} + diff --git a/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll b/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll new file mode 100644 index 000000000000..97c31a148e3a --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll @@ -0,0 +1,73 @@ +; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -debug-only=loop-vectorize -stats -S -vectorizer-min-trip-count=21 2>&1 | FileCheck %s +; REQUIRES: asserts + +; CHECK: LV: Loop hints: force=enabled +; CHECK: LV: Loop hints: force=? +; No more loops in the module +; CHECK-NOT: LV: Loop hints: force= +; CHECK: 2 loop-vectorize - Number of loops analyzed for vectorization +; CHECK: 1 loop-vectorize - Number of loops vectorized + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; +; The source code for the test: +; +; void foo(float* restrict A, float* restrict B) +; { +; for (int i = 0; i < 20; ++i) A[i] += B[i]; +; } +; + +; +; This loop will be vectorized, although the trip count is below the threshold, but vectorization is explicitly forced in metadata. +; +define void @vectorized(float* noalias nocapture %A, float* noalias nocapture readonly %B) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1 + %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv + %1 = load float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1 + %add = fadd fast float %0, %1 + store float %add, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 20 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !1 + +for.end: + ret void +} + +!1 = metadata !{metadata !1, metadata !2} +!2 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} + +; +; This loop will not be vectorized as the trip count is below the threshold. +; +define void @not_vectorized(float* noalias nocapture %A, float* noalias nocapture readonly %B) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds float* %B, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3 + %arrayidx2 = getelementptr inbounds float* %A, i64 %indvars.iv + %1 = load float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 + %add = fadd fast float %0, %1 + store float %add, float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 20 + br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !3 + +for.end: + ret void +} + +!3 = metadata !{metadata !3} + diff --git a/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll b/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll index 59bb8d0054c5..e57cfefec07c 100644 --- a/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll +++ b/test/Transforms/LoopVectorize/X86/vector_ptr_load_store.ll @@ -1,4 +1,4 @@ -; RUN: opt -loop-vectorize -mcpu=corei7-avx -debug -S < %s 2>&1 | FileCheck %s +; RUN: opt -basicaa -loop-vectorize -mcpu=corei7-avx -debug -S < %s 2>&1 | FileCheck %s ; REQUIRES: asserts target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" diff --git a/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll b/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll new file mode 100644 index 000000000000..93f24cbf4909 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll @@ -0,0 +1,161 @@ +; RUN: opt < %s -loop-vectorize -S -pass-remarks-missed='loop-vectorize' -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s + +; C/C++ code for tests +; void test(int *A, int Length) { +; #pragma clang loop vectorize(enable) interleave(enable) +; for (int i = 0; i < Length; i++) { +; A[i] = i; +; if (A[i] > Length) +; break; +; } +; } + +; void test_disabled(int *A, int Length) { +; #pragma clang loop vectorize(disable) interleave(disable) +; for (int i = 0; i < Length; i++) +; A[i] = i; +; } + +; void test_array_bounds(int *A, int *B, int Length) { +; #pragma clang loop vectorize(enable) +; for (int i = 0; i < Length; i++) +; A[i] = A[B[i]]; +; } + +; File, line, and column should match those specified in the metadata +; CHECK: remark: source.cpp:4:5: loop not vectorized: could not determine number of loop iterations +; CHECK: remark: source.cpp:4:5: loop not vectorized: vectorization was not specified +; CHECK: remark: source.cpp:13:5: loop not vectorized: vector width and interleave count are explicitly set to 1 +; CHECK: remark: source.cpp:19:5: loop not vectorized: cannot identify array bounds +; CHECK: remark: source.cpp:19:5: loop not vectorized: vectorization is explicitly enabled +; CHECK: warning: source.cpp:19:5: loop not vectorized: failed explicitly specified loop vectorization + +; CHECK: _Z4testPii +; CHECK-NOT: x i32> +; CHECK: ret + +; CHECK: _Z13test_disabledPii +; CHECK-NOT: x i32> +; CHECK: ret + +; CHECK: _Z17test_array_boundsPiS_i +; CHECK-NOT: x i32> +; CHECK: ret + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +; Function Attrs: nounwind optsize ssp uwtable +define void @_Z4testPii(i32* nocapture %A, i32 %Length) #0 { +entry: + %cmp10 = icmp sgt i32 %Length, 0, !dbg !12 + br i1 %cmp10, label %for.body, label %for.end, !dbg !12, !llvm.loop !14 + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !16 + %0 = trunc i64 %indvars.iv to i32, !dbg !16 + store i32 %0, i32* %arrayidx, align 4, !dbg !16, !tbaa !18 + %cmp3 = icmp sle i32 %0, %Length, !dbg !22 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !12 + %1 = trunc i64 %indvars.iv.next to i32 + %cmp = icmp slt i32 %1, %Length, !dbg !12 + %or.cond = and i1 %cmp3, %cmp, !dbg !22 + br i1 %or.cond, label %for.body, label %for.end, !dbg !22 + +for.end: ; preds = %for.body, %entry + ret void, !dbg !24 +} + +; Function Attrs: nounwind optsize ssp uwtable +define void @_Z13test_disabledPii(i32* nocapture %A, i32 %Length) #0 { +entry: + %cmp4 = icmp sgt i32 %Length, 0, !dbg !25 + br i1 %cmp4, label %for.body, label %for.end, !dbg !25, !llvm.loop !27 + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !30 + %0 = trunc i64 %indvars.iv to i32, !dbg !30 + store i32 %0, i32* %arrayidx, align 4, !dbg !30, !tbaa !18 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !25 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !25 + %exitcond = icmp eq i32 %lftr.wideiv, %Length, !dbg !25 + br i1 %exitcond, label %for.end, label %for.body, !dbg !25, !llvm.loop !27 + +for.end: ; preds = %for.body, %entry + ret void, !dbg !31 +} + +; Function Attrs: nounwind optsize ssp uwtable +define void @_Z17test_array_boundsPiS_i(i32* nocapture %A, i32* nocapture readonly %B, i32 %Length) #0 { +entry: + %cmp9 = icmp sgt i32 %Length, 0, !dbg !32 + br i1 %cmp9, label %for.body.preheader, label %for.end, !dbg !32, !llvm.loop !34 + +for.body.preheader: ; preds = %entry + br label %for.body, !dbg !35 + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv, !dbg !35 + %0 = load i32* %arrayidx, align 4, !dbg !35, !tbaa !18 + %idxprom1 = sext i32 %0 to i64, !dbg !35 + %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1, !dbg !35 + %1 = load i32* %arrayidx2, align 4, !dbg !35, !tbaa !18 + %arrayidx4 = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !35 + store i32 %1, i32* %arrayidx4, align 4, !dbg !35, !tbaa !18 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !32 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !32 + %exitcond = icmp eq i32 %lftr.wideiv, %Length, !dbg !32 + br i1 %exitcond, label %for.end.loopexit, label %for.body, !dbg !32, !llvm.loop !34 + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret void, !dbg !36 +} + +attributes #0 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!9, !10} +!llvm.ident = !{!11} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5.0", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 2} +!1 = metadata !{metadata !"source.cpp", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4, metadata !7, metadata !8} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"test", metadata !"test", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i32*, i32)* @_Z4testPii, null, null, metadata !2, i32 1} +!5 = metadata !{i32 786473, metadata !1} +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} +!7 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"test_disabled", metadata !"test_disabled", metadata !"", i32 10, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i32*, i32)* @_Z13test_disabledPii, null, null, metadata !2, i32 10} +!8 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"test_array_bounds", metadata !"test_array_bounds", metadata !"", i32 16, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i32*, i32*, i32)* @_Z17test_array_boundsPiS_i, null, null, metadata !2, i32 16} +!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 2} +!10 = metadata !{i32 2, metadata !"Debug Info Version", i32 1} +!11 = metadata !{metadata !"clang version 3.5.0"} +!12 = metadata !{i32 3, i32 8, metadata !13, null} +!13 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 3, i32 0, i32 0} +!14 = metadata !{metadata !14, metadata !15, metadata !15} +!15 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} +!16 = metadata !{i32 4, i32 5, metadata !17, null} +!17 = metadata !{i32 786443, metadata !1, metadata !13, i32 3, i32 36, i32 0, i32 1} +!18 = metadata !{metadata !19, metadata !19, i64 0} +!19 = metadata !{metadata !"int", metadata !20, i64 0} +!20 = metadata !{metadata !"omnipotent char", metadata !21, i64 0} +!21 = metadata !{metadata !"Simple C/C++ TBAA"} +!22 = metadata !{i32 5, i32 9, metadata !23, null} +!23 = metadata !{i32 786443, metadata !1, metadata !17, i32 5, i32 9, i32 0, i32 2} +!24 = metadata !{i32 8, i32 1, metadata !4, null} +!25 = metadata !{i32 12, i32 8, metadata !26, null} +!26 = metadata !{i32 786443, metadata !1, metadata !7, i32 12, i32 3, i32 0, i32 3} +!27 = metadata !{metadata !27, metadata !28, metadata !29} +!28 = metadata !{metadata !"llvm.loop.interleave.count", i32 1} +!29 = metadata !{metadata !"llvm.loop.vectorize.width", i32 1} +!30 = metadata !{i32 13, i32 5, metadata !26, null} +!31 = metadata !{i32 14, i32 1, metadata !7, null} +!32 = metadata !{i32 18, i32 8, metadata !33, null} +!33 = metadata !{i32 786443, metadata !1, metadata !8, i32 18, i32 3, i32 0, i32 4} +!34 = metadata !{metadata !34, metadata !15} +!35 = metadata !{i32 19, i32 5, metadata !33, null} +!36 = metadata !{i32 20, i32 1, metadata !8, null} diff --git a/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll b/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll new file mode 100644 index 000000000000..f6834477ff51 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll @@ -0,0 +1,74 @@ +; RUN: opt < %s -loop-vectorize -mtriple=x86_64-unknown-linux -S -pass-remarks='loop-vectorize' 2>&1 | FileCheck -check-prefix=VECTORIZED %s +; RUN: opt < %s -loop-vectorize -force-vector-width=1 -force-vector-unroll=4 -mtriple=x86_64-unknown-linux -S -pass-remarks='loop-vectorize' 2>&1 | FileCheck -check-prefix=UNROLLED %s +; RUN: opt < %s -loop-vectorize -force-vector-width=1 -force-vector-unroll=1 -mtriple=x86_64-unknown-linux -S -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck -check-prefix=NONE %s + +; This code has all the !dbg annotations needed to track source line information, +; but is missing the llvm.dbg.cu annotation. This prevents code generation from +; emitting debug info in the final output. +; RUN: llc -mtriple x86_64-pc-linux-gnu %s -o - | FileCheck -check-prefix=DEBUG-OUTPUT %s +; DEBUG-OUTPUT-NOT: .loc +; DEBUG-OUTPUT-NOT: {{.*}}.debug_info + +; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization factor: 4, unrolling interleave factor: 1) +; UNROLLED: remark: vectorization-remarks.c:17:8: unrolled with interleaving factor 4 (vectorization not beneficial) +; NONE: remark: vectorization-remarks.c:17:8: loop not vectorized: vector width and interleave count are explicitly set to 1 + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + +define i32 @foo(i32 %n) #0 { +entry: + %diff = alloca i32, align 4 + %cb = alloca [16 x i8], align 16 + %cc = alloca [16 x i8], align 16 + store i32 0, i32* %diff, align 4, !dbg !10, !tbaa !11 + br label %for.body, !dbg !15 + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %add8 = phi i32 [ 0, %entry ], [ %add, %for.body ], !dbg !19 + %arrayidx = getelementptr inbounds [16 x i8]* %cb, i64 0, i64 %indvars.iv, !dbg !19 + %0 = load i8* %arrayidx, align 1, !dbg !19, !tbaa !21 + %conv = sext i8 %0 to i32, !dbg !19 + %arrayidx2 = getelementptr inbounds [16 x i8]* %cc, i64 0, i64 %indvars.iv, !dbg !19 + %1 = load i8* %arrayidx2, align 1, !dbg !19, !tbaa !21 + %conv3 = sext i8 %1 to i32, !dbg !19 + %sub = sub i32 %conv, %conv3, !dbg !19 + %add = add nsw i32 %sub, %add8, !dbg !19 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !15 + %exitcond = icmp eq i64 %indvars.iv.next, 16, !dbg !15 + br i1 %exitcond, label %for.end, label %for.body, !dbg !15 + +for.end: ; preds = %for.body + store i32 %add, i32* %diff, align 4, !dbg !19, !tbaa !11 + call void @ibar(i32* %diff) #2, !dbg !22 + ret i32 0, !dbg !23 +} + +declare void @ibar(i32*) #1 + +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!1 = metadata !{metadata !"vectorization-remarks.c", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 5, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32)* @foo, null, null, metadata !2, i32 6} ; [ DW_TAG_subprogram ] [line 5] [def] [scope 6] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [./vectorization-remarks.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!8 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!9 = metadata !{metadata !"clang version 3.5.0 "} +!10 = metadata !{i32 8, i32 3, metadata !4, null} ; [ DW_TAG_imported_declaration ] +!11 = metadata !{metadata !12, metadata !12, i64 0} +!12 = metadata !{metadata !"int", metadata !13, i64 0} +!13 = metadata !{metadata !"omnipotent char", metadata !14, i64 0} +!14 = metadata !{metadata !"Simple C/C++ TBAA"} +!15 = metadata !{i32 17, i32 8, metadata !16, null} +!16 = metadata !{i32 786443, metadata !1, metadata !17, i32 17, i32 8, i32 2, i32 3} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c] +!17 = metadata !{i32 786443, metadata !1, metadata !18, i32 17, i32 8, i32 1, i32 2} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c] +!18 = metadata !{i32 786443, metadata !1, metadata !4, i32 17, i32 3, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c] +!19 = metadata !{i32 18, i32 5, metadata !20, null} +!20 = metadata !{i32 786443, metadata !1, metadata !18, i32 17, i32 27, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [./vectorization-remarks.c] +!21 = metadata !{metadata !13, metadata !13, i64 0} +!22 = metadata !{i32 20, i32 3, metadata !4, null} +!23 = metadata !{i32 21, i32 3, metadata !4, null} diff --git a/test/Transforms/LoopVectorize/XCore/lit.local.cfg b/test/Transforms/LoopVectorize/XCore/lit.local.cfg index 4d17d4642045..bb48713fe33e 100644 --- a/test/Transforms/LoopVectorize/XCore/lit.local.cfg +++ b/test/Transforms/LoopVectorize/XCore/lit.local.cfg @@ -1,3 +1,2 @@ -targets = set(config.root.targets_to_build.split()) -if not 'XCore' in targets: +if not 'XCore' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/LoopVectorize/calloc.ll b/test/Transforms/LoopVectorize/calloc.ll index 7e7991616459..55c0a605450f 100644 --- a/test/Transforms/LoopVectorize/calloc.ll +++ b/test/Transforms/LoopVectorize/calloc.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s +; RUN: opt < %s -basicaa -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.9.0" diff --git a/test/Transforms/LoopVectorize/control-flow.ll b/test/Transforms/LoopVectorize/control-flow.ll new file mode 100644 index 000000000000..e4ba77fa3daa --- /dev/null +++ b/test/Transforms/LoopVectorize/control-flow.ll @@ -0,0 +1,78 @@ +; RUN: opt < %s -loop-vectorize -force-vector-width=4 -S -pass-remarks-missed='loop-vectorize' -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s + +; C/C++ code for control flow test +; int test(int *A, int Length) { +; for (int i = 0; i < Length; i++) { +; if (A[i] > 10.0) goto end; +; A[i] = 0; +; } +; end: +; return 0; +; } + +; CHECK: remark: source.cpp:5:9: loop not vectorized: loop control flow is not understood by vectorizer +; CHECK: remark: source.cpp:5:9: loop not vectorized: vectorization was not specified + +; CHECK: _Z4testPii +; CHECK-NOT: x i32> +; CHECK: ret + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +; Function Attrs: nounwind optsize ssp uwtable +define i32 @_Z4testPii(i32* nocapture %A, i32 %Length) #0 { +entry: + %cmp8 = icmp sgt i32 %Length, 0, !dbg !10 + br i1 %cmp8, label %for.body.preheader, label %end, !dbg !10 + +for.body.preheader: ; preds = %entry + br label %for.body, !dbg !12 + +for.body: ; preds = %for.body.preheader, %if.else + %indvars.iv = phi i64 [ %indvars.iv.next, %if.else ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !12 + %0 = load i32* %arrayidx, align 4, !dbg !12, !tbaa !15 + %cmp1 = icmp sgt i32 %0, 10, !dbg !12 + br i1 %cmp1, label %end.loopexit, label %if.else, !dbg !12 + +if.else: ; preds = %for.body + store i32 0, i32* %arrayidx, align 4, !dbg !19, !tbaa !15 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !10 + %1 = trunc i64 %indvars.iv.next to i32, !dbg !10 + %cmp = icmp slt i32 %1, %Length, !dbg !10 + br i1 %cmp, label %for.body, label %end.loopexit, !dbg !10 + +end.loopexit: ; preds = %if.else, %for.body + br label %end + +end: ; preds = %end.loopexit, %entry + ret i32 0, !dbg !20 +} + +attributes #0 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5.0", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 2} +!1 = metadata !{metadata !"source.cpp", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"test", metadata !"test", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32*, i32)* @_Z4testPii, null, null, metadata !2, i32 2} +!5 = metadata !{i32 786473, metadata !1} +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} +!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 2} +!8 = metadata !{i32 2, metadata !"Debug Info Version", i32 1} +!9 = metadata !{metadata !"clang version 3.5.0"} +!10 = metadata !{i32 3, i32 8, metadata !11, null} +!11 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 3, i32 0, i32 0} +!12 = metadata !{i32 5, i32 9, metadata !13, null} +!13 = metadata !{i32 786443, metadata !1, metadata !14, i32 5, i32 9, i32 0, i32 2} +!14 = metadata !{i32 786443, metadata !1, metadata !11, i32 4, i32 3, i32 0, i32 1} +!15 = metadata !{metadata !16, metadata !16, i64 0} +!16 = metadata !{metadata !"int", metadata !17, i64 0} +!17 = metadata !{metadata !"omnipotent char", metadata !18, i64 0} +!18 = metadata !{metadata !"Simple C/C++ TBAA"} +!19 = metadata !{i32 8, i32 7, metadata !13, null} +!20 = metadata !{i32 12, i32 3, metadata !4, null} diff --git a/test/Transforms/LoopVectorize/flags.ll b/test/Transforms/LoopVectorize/flags.ll index a4ebb4284881..21d09372d546 100644 --- a/test/Transforms/LoopVectorize/flags.ll +++ b/test/Transforms/LoopVectorize/flags.ll @@ -51,3 +51,29 @@ define i32 @flags2(i32 %n, i32* nocapture %A) nounwind uwtable ssp { ._crit_edge: ; preds = %.lr.ph, %0 ret i32 undef } + +; Make sure we copy fast math flags and use them for the final reduction. +; CHECK-LABEL: fast_math +; CHECK: load <4 x float> +; CHECK: fadd fast <4 x float> +; CHECK: br +; CHECK: fadd fast <4 x float> +; CHECK: fadd fast <4 x float> +define float @fast_math(float* noalias %s) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %q.04 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ] + %arrayidx = getelementptr inbounds float* %s, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %add = fadd fast float %q.04, %0 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 256 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + %add.lcssa = phi float [ %add, %for.body ] + ret float %add.lcssa +} diff --git a/test/Transforms/LoopVectorize/float-reduction.ll b/test/Transforms/LoopVectorize/float-reduction.ll index c45098dd2c3b..0dfbab07279a 100644 --- a/test/Transforms/LoopVectorize/float-reduction.ll +++ b/test/Transforms/LoopVectorize/float-reduction.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" ;CHECK-LABEL: @foo( -;CHECK: fadd <4 x float> +;CHECK: fadd fast <4 x float> ;CHECK: ret define float @foo(float* nocapture %A, i32* nocapture %n) nounwind uwtable readonly ssp { entry: diff --git a/test/Transforms/LoopVectorize/gcc-examples.ll b/test/Transforms/LoopVectorize/gcc-examples.ll index d8959d4c106a..b6cde5d00f5e 100644 --- a/test/Transforms/LoopVectorize/gcc-examples.ll +++ b/test/Transforms/LoopVectorize/gcc-examples.ll @@ -1,5 +1,5 @@ -; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-unroll=1 -dce -instcombine -S | FileCheck %s -; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-unroll=4 -dce -instcombine -S | FileCheck %s -check-prefix=UNROLL +; RUN: opt < %s -basicaa -loop-vectorize -force-vector-width=4 -force-vector-unroll=1 -dce -instcombine -S | FileCheck %s +; RUN: opt < %s -basicaa -loop-vectorize -force-vector-width=4 -force-vector-unroll=4 -dce -instcombine -S | FileCheck %s -check-prefix=UNROLL target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" diff --git a/test/Transforms/LoopVectorize/global_alias.ll b/test/Transforms/LoopVectorize/global_alias.ll index 0118fb47412a..d64d67f6a5b1 100644 --- a/test/Transforms/LoopVectorize/global_alias.ll +++ b/test/Transforms/LoopVectorize/global_alias.ll @@ -387,7 +387,7 @@ for.end: ; preds = %for.cond ; return Foo.A[a]; ; } ; CHECK-LABEL: define i32 @noAlias08( -; CHECK: sub nsw <4 x i32> +; CHECK: sub <4 x i32> ; CHECK: ret define i32 @noAlias08(i32 %a) #0 { @@ -439,7 +439,7 @@ for.end: ; preds = %for.cond ; return Foo.A[a]; ; } ; CHECK-LABEL: define i32 @noAlias09( -; CHECK: sub nsw <4 x i32> +; CHECK: sub <4 x i32> ; CHECK: ret define i32 @noAlias09(i32 %a) #0 { @@ -491,7 +491,7 @@ for.end: ; preds = %for.cond ; return *(PA+a); ; } ; CHECK-LABEL: define i32 @noAlias10( -; CHECK-NOT: sub nsw <4 x i32> +; CHECK-NOT: sub {{.*}} <4 x i32> ; CHECK: ret ; ; TODO: This test vectorizes (with run-time check) on real targets with -O3) @@ -721,7 +721,7 @@ for.end: ; preds = %for.cond ; return Foo.A[a]; ; } ; CHECK-LABEL: define i32 @noAlias14( -; CHECK: sub nsw <4 x i32> +; CHECK: sub <4 x i32> ; CHECK: ret define i32 @noAlias14(i32 %a) #0 { diff --git a/test/Transforms/LoopVectorize/if-conversion.ll b/test/Transforms/LoopVectorize/if-conversion.ll index dbe0243a8110..6e3e8ed27853 100644 --- a/test/Transforms/LoopVectorize/if-conversion.ll +++ b/test/Transforms/LoopVectorize/if-conversion.ll @@ -156,7 +156,7 @@ for.body: br i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 0), i32** @c), label %cond.false, label %cond.end cond.false: - %cond.1 = or i32 %inc3, sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 0), i32** @c) to i32)) + %cond.1 = or i32 %inc3, sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 1), i32** @c) to i32)) br label %cond.end cond.end: diff --git a/test/Transforms/LoopVectorize/if-pred-stores.ll b/test/Transforms/LoopVectorize/if-pred-stores.ll new file mode 100644 index 000000000000..7b0e181c845f --- /dev/null +++ b/test/Transforms/LoopVectorize/if-pred-stores.ll @@ -0,0 +1,126 @@ +; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=1 -force-vector-unroll=2 -loop-vectorize < %s | FileCheck %s --check-prefix=UNROLL +; RUN: opt -S -vectorize-num-stores-pred=1 -force-vector-width=2 -force-vector-unroll=1 -loop-vectorize -enable-cond-stores-vec < %s | FileCheck %s --check-prefix=VEC +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +; Test predication of stores. +define i32 @test(i32* nocapture %f) #0 { +entry: + br label %for.body + +; VEC-LABEL: test +; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100> +; VEC: %[[v9:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20> +; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true> +; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[v10]], i32 0 +; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true +; VEC: br i1 %[[v12]], label %[[cond:.+]], label %[[else:.+]] +; +; VEC: [[cond]]: +; VEC: %[[v13:.+]] = extractelement <2 x i32> %[[v9]], i32 0 +; VEC: %[[v14:.+]] = extractelement <2 x i32*> %{{.*}}, i32 0 +; VEC: store i32 %[[v13]], i32* %[[v14]], align 4 +; VEC: br label %[[else:.+]] +; +; VEC: [[else]]: +; VEC: %[[v15:.+]] = extractelement <2 x i1> %[[v10]], i32 1 +; VEC: %[[v16:.+]] = icmp eq i1 %[[v15]], true +; VEC: br i1 %[[v16]], label %[[cond2:.+]], label %[[else2:.+]] +; +; VEC: [[cond2]]: +; VEC: %[[v17:.+]] = extractelement <2 x i32> %[[v9]], i32 1 +; VEC: %[[v18:.+]] = extractelement <2 x i32*> %{{.+}} i32 1 +; VEC: store i32 %[[v17]], i32* %[[v18]], align 4 +; VEC: br label %[[else2:.+]] +; +; VEC: [[else2]]: + +; UNROLL-LABEL: test +; UNROLL: vector.body: +; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 0 +; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.*}}, 1 +; UNROLL: %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32* %f, i64 %[[IND]] +; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32* %f, i64 %[[IND1]] +; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32* %[[v0]], align 4 +; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32* %[[v1]], align 4 +; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100 +; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100 +; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20 +; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20 +; UNROLL: %[[v8:[a-zA-Z0-9]+]] = icmp eq i1 %[[v4]], true +; UNROLL: br i1 %[[v8]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]] +; +; UNROLL: [[cond]]: +; UNROLL: store i32 %[[v6]], i32* %[[v0]], align 4 +; UNROLL: br label %[[else]] +; +; UNROLL: [[else]]: +; UNROLL: %[[v9:[a-zA-Z0-9]+]] = icmp eq i1 %[[v5]], true +; UNROLL: br i1 %[[v9]], label %[[cond2:[a-zA-Z0-9.]+]], label %[[else2:[a-zA-Z0-9.]+]] +; +; UNROLL: [[cond2]]: +; UNROLL: store i32 %[[v7]], i32* %[[v1]], align 4 +; UNROLL: br label %[[else2]] +; +; UNROLL: [[else2]]: + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ] + %arrayidx = getelementptr inbounds i32* %f, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp1 = icmp sgt i32 %0, 100 + br i1 %cmp1, label %if.then, label %for.inc + +if.then: + %add = add nsw i32 %0, 20 + store i32 %add, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 128 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 0 +} + +; Track basic blocks when unrolling conditional blocks. This code used to assert +; because we did not update the phi nodes with the proper predecessor in the +; vectorized loop body. +; PR18724 + +; UNROLL-LABEL: bug18724 +; UNROLL: store i32 +; UNROLL: store i32 + +define void @bug18724() { +entry: + br label %for.body9 + +for.body9: + br i1 undef, label %for.inc26, label %for.body14 + +for.body14: + %indvars.iv3 = phi i64 [ %indvars.iv.next4, %for.inc23 ], [ undef, %for.body9 ] + %iNewChunks.120 = phi i32 [ %iNewChunks.2, %for.inc23 ], [ undef, %for.body9 ] + %arrayidx16 = getelementptr inbounds [768 x i32]* undef, i64 0, i64 %indvars.iv3 + %tmp = load i32* %arrayidx16, align 4 + br i1 undef, label %if.then18, label %for.inc23 + +if.then18: + store i32 2, i32* %arrayidx16, align 4 + %inc21 = add nsw i32 %iNewChunks.120, 1 + br label %for.inc23 + +for.inc23: + %iNewChunks.2 = phi i32 [ %inc21, %if.then18 ], [ %iNewChunks.120, %for.body14 ] + %indvars.iv.next4 = add nsw i64 %indvars.iv3, 1 + %tmp1 = trunc i64 %indvars.iv3 to i32 + %cmp13 = icmp slt i32 %tmp1, 0 + br i1 %cmp13, label %for.body14, label %for.inc26 + +for.inc26: + %iNewChunks.1.lcssa = phi i32 [ undef, %for.body9 ], [ %iNewChunks.2, %for.inc23 ] + unreachable +} diff --git a/test/Transforms/LoopVectorize/increment.ll b/test/Transforms/LoopVectorize/increment.ll index d35bd58a0281..71bedb7334ac 100644 --- a/test/Transforms/LoopVectorize/increment.ll +++ b/test/Transforms/LoopVectorize/increment.ll @@ -34,7 +34,7 @@ define void @inc(i32 %n) nounwind uwtable noinline ssp { ret void } -; Can't vectorize this loop because the access to A[X] is non linear. +; Can't vectorize this loop because the access to A[X] is non-linear. ; ; for (i = 0; i < n; ++i) { ; A[B[i]]++; diff --git a/test/Transforms/LoopVectorize/induction.ll b/test/Transforms/LoopVectorize/induction.ll index 50c3b6b6e79b..7dabcb2ba04f 100644 --- a/test/Transforms/LoopVectorize/induction.ll +++ b/test/Transforms/LoopVectorize/induction.ll @@ -75,7 +75,7 @@ loopexit: ; PR17532 ; CHECK-LABEL: i8_loop -; CHECK; icmp eq i32 {{.*}}, 256 +; CHECK: icmp eq i32 {{.*}}, 256 define i32 @i8_loop() nounwind readnone ssp uwtable { br label %1 @@ -92,7 +92,7 @@ define i32 @i8_loop() nounwind readnone ssp uwtable { } ; CHECK-LABEL: i16_loop -; CHECK; icmp eq i32 {{.*}}, 65536 +; CHECK: icmp eq i32 {{.*}}, 65536 define i32 @i16_loop() nounwind readnone ssp uwtable { br label %1 @@ -108,3 +108,64 @@ define i32 @i16_loop() nounwind readnone ssp uwtable { ; <label>:5 ; preds = %1 ret i32 %2 } + +; This loop has a backedge taken count of i32_max. We need to check for this +; condition and branch directly to the scalar loop. + +; CHECK-LABEL: max_i32_backedgetaken +; CHECK: %backedge.overflow = icmp eq i32 -1, -1 +; CHECK: br i1 %backedge.overflow, label %scalar.ph, label %overflow.checked + +; CHECK: scalar.ph: +; CHECK: %bc.resume.val = phi i32 [ %resume.val, %middle.block ], [ 0, %0 ] +; CHECK: %bc.merge.rdx = phi i32 [ 1, %0 ], [ %5, %middle.block ] + +define i32 @max_i32_backedgetaken() nounwind readnone ssp uwtable { + + br label %1 + +; <label>:1 ; preds = %1, %0 + %a.0 = phi i32 [ 1, %0 ], [ %2, %1 ] + %b.0 = phi i32 [ 0, %0 ], [ %3, %1 ] + %2 = and i32 %a.0, 4 + %3 = add i32 %b.0, -1 + %4 = icmp eq i32 %3, 0 + br i1 %4, label %5, label %1 + +; <label>:5 ; preds = %1 + ret i32 %2 +} + +; When generating the overflow check we must sure that the induction start value +; is defined before the branch to the scalar preheader. + +; CHECK-LABEL: testoverflowcheck +; CHECK: entry +; CHECK: %[[LOAD:.*]] = load i8 +; CHECK: %[[VAL:.*]] = zext i8 %[[LOAD]] to i32 +; CHECK: br + +; CHECK: scalar.ph +; CHECK: phi i32 [ %{{.*}}, %middle.block ], [ %[[VAL]], %entry ] + +@e = global i8 1, align 1 +@d = common global i32 0, align 4 +@c = common global i32 0, align 4 +define i32 @testoverflowcheck() { +entry: + %.pr.i = load i8* @e, align 1 + %0 = load i32* @d, align 4 + %c.promoted.i = load i32* @c, align 4 + br label %cond.end.i + +cond.end.i: + %inc4.i = phi i8 [ %.pr.i, %entry ], [ %inc.i, %cond.end.i ] + %and3.i = phi i32 [ %c.promoted.i, %entry ], [ %and.i, %cond.end.i ] + %and.i = and i32 %0, %and3.i + %inc.i = add i8 %inc4.i, 1 + %tobool.i = icmp eq i8 %inc.i, 0 + br i1 %tobool.i, label %loopexit, label %cond.end.i + +loopexit: + ret i32 %and.i +} diff --git a/test/Transforms/LoopVectorize/intrinsic.ll b/test/Transforms/LoopVectorize/intrinsic.ll index c3d570c03a77..7dfaf03b0f2d 100644 --- a/test/Transforms/LoopVectorize/intrinsic.ll +++ b/test/Transforms/LoopVectorize/intrinsic.ll @@ -1090,3 +1090,105 @@ for.end: ; preds = %for.body ret void } +declare double @llvm.powi.f64(double %Val, i32 %power) nounwind readnone + +;CHECK-LABEL: @powi_f64( +;CHECK: llvm.powi.v4f64 +;CHECK: ret void +define void @powi_f64(i32 %n, double* noalias %y, double* noalias %x, i32 %P) nounwind uwtable { +entry: + %cmp9 = icmp sgt i32 %n, 0 + br i1 %cmp9, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv + %0 = load double* %arrayidx, align 8 + %call = tail call double @llvm.powi.f64(double %0, i32 %P) nounwind readnone + %arrayidx4 = getelementptr inbounds double* %x, i64 %indvars.iv + store double %call, double* %arrayidx4, align 8 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +;CHECK-LABEL: @powi_f64_neg( +;CHECK-NOT: llvm.powi.v4f64 +;CHECK: ret void +define void @powi_f64_neg(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable { +entry: + %cmp9 = icmp sgt i32 %n, 0 + br i1 %cmp9, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv + %0 = load double* %arrayidx, align 8 + %1 = trunc i64 %indvars.iv to i32 + %call = tail call double @llvm.powi.f64(double %0, i32 %1) nounwind readnone + %arrayidx4 = getelementptr inbounds double* %x, i64 %indvars.iv + store double %call, double* %arrayidx4, align 8 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +declare i64 @llvm.cttz.i64 (i64, i1) nounwind readnone + +;CHECK-LABEL: @cttz_f64( +;CHECK: llvm.cttz.v4i64 +;CHECK: ret void +define void @cttz_f64(i32 %n, i64* noalias %y, i64* noalias %x) nounwind uwtable { +entry: + %cmp9 = icmp sgt i32 %n, 0 + br i1 %cmp9, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i64* %y, i64 %indvars.iv + %0 = load i64* %arrayidx, align 8 + %call = tail call i64 @llvm.cttz.i64(i64 %0, i1 true) nounwind readnone + %arrayidx4 = getelementptr inbounds i64* %x, i64 %indvars.iv + store i64 %call, i64* %arrayidx4, align 8 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +declare i64 @llvm.ctlz.i64 (i64, i1) nounwind readnone + +;CHECK-LABEL: @ctlz_f64( +;CHECK: llvm.ctlz.v4i64 +;CHECK: ret void +define void @ctlz_f64(i32 %n, i64* noalias %y, i64* noalias %x) nounwind uwtable { +entry: + %cmp9 = icmp sgt i32 %n, 0 + br i1 %cmp9, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i64* %y, i64 %indvars.iv + %0 = load i64* %arrayidx, align 8 + %call = tail call i64 @llvm.ctlz.i64(i64 %0, i1 true) nounwind readnone + %arrayidx4 = getelementptr inbounds i64* %x, i64 %indvars.iv + store i64 %call, i64* %arrayidx4, align 8 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/Transforms/LoopVectorize/metadata-unroll.ll b/test/Transforms/LoopVectorize/metadata-unroll.ll index 7f1037200659..848f1f9601b9 100644 --- a/test/Transforms/LoopVectorize/metadata-unroll.ll +++ b/test/Transforms/LoopVectorize/metadata-unroll.ll @@ -38,4 +38,4 @@ define void @inc(i32 %n) nounwind uwtable noinline ssp { } !0 = metadata !{metadata !0, metadata !1} -!1 = metadata !{metadata !"llvm.vectorizer.unroll", i32 2} +!1 = metadata !{metadata !"llvm.loop.interleave.count", i32 2} diff --git a/test/Transforms/LoopVectorize/metadata-width.ll b/test/Transforms/LoopVectorize/metadata-width.ll index 1960c0bad6bc..87de655da6f2 100644 --- a/test/Transforms/LoopVectorize/metadata-width.ll +++ b/test/Transforms/LoopVectorize/metadata-width.ll @@ -28,4 +28,4 @@ for.end: ; preds = %for.body, %entry attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } !0 = metadata !{metadata !0, metadata !1} -!1 = metadata !{metadata !"llvm.vectorizer.width", i32 8} +!1 = metadata !{metadata !"llvm.loop.vectorize.width", i32 8} diff --git a/test/Transforms/LoopVectorize/metadata.ll b/test/Transforms/LoopVectorize/metadata.ll new file mode 100644 index 000000000000..bdcf1c9fb229 --- /dev/null +++ b/test/Transforms/LoopVectorize/metadata.ll @@ -0,0 +1,44 @@ +; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -S | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Function Attrs: nounwind uwtable +define i32 @test1(i32* nocapture %a, float* nocapture readonly %b) #0 { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !tbaa !0 + %conv = fptosi float %0 to i32 + %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv + store i32 %conv, i32* %arrayidx2, align 4, !tbaa !4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1600 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i32 0 +} + +; CHECK-LABEL: @test1 +; CHECK: load <4 x float>* %{{.*}}, align 4, !tbaa ![[TFLT:[0-9]+]] +; CHECK: store <4 x i32> %{{.*}}, <4 x i32>* %{{.*}}, align 4, !tbaa ![[TINT:[0-9]+]] +; CHECK: ret i32 0 + +; CHECK-DAG: ![[TFLT]] = metadata !{metadata ![[TFLT1:[0-9]+]] +; CHECK-DAG: ![[TFLT1]] = metadata !{metadata !"float" + +; CHECK-DAG: ![[TINT]] = metadata !{metadata ![[TINT1:[0-9]+]] +; CHECK-DAG: ![[TINT1]] = metadata !{metadata !"int" + +attributes #0 = { nounwind uwtable } + +!0 = metadata !{metadata !1, metadata !1, i64 0} +!1 = metadata !{metadata !"float", metadata !2, i64 0} +!2 = metadata !{metadata !"omnipotent char", metadata !3, i64 0} +!3 = metadata !{metadata !"Simple C/C++ TBAA"} +!4 = metadata !{metadata !5, metadata !5, i64 0} +!5 = metadata !{metadata !"int", metadata !2, i64 0} + diff --git a/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll b/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll index 5fc5ed55a99d..88a29c50df5a 100644 --- a/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll +++ b/test/Transforms/LoopVectorize/multi-use-reduction-bug.ll @@ -1,6 +1,6 @@ ; RUN: opt -indvars -loop-vectorize -force-vector-width=2 -force-vector-unroll=1 -S < %s | FileCheck %s -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.9.0" ; We must not vectorize this loop. %add55 is not reduction. Its value is used diff --git a/test/Transforms/LoopVectorize/multiple-address-spaces.ll b/test/Transforms/LoopVectorize/multiple-address-spaces.ll index 7d836dedbdbb..d64662838e00 100644 --- a/test/Transforms/LoopVectorize/multiple-address-spaces.ll +++ b/test/Transforms/LoopVectorize/multiple-address-spaces.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s +; RUN: opt < %s -basicaa -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s ; From a simple program with two address spaces: ; char Y[4*10000] __attribute__((address_space(1))); diff --git a/test/Transforms/LoopVectorize/no_array_bounds.ll b/test/Transforms/LoopVectorize/no_array_bounds.ll new file mode 100644 index 000000000000..240b1b5d49dc --- /dev/null +++ b/test/Transforms/LoopVectorize/no_array_bounds.ll @@ -0,0 +1,101 @@ +; RUN: opt < %s -loop-vectorize -S 2>&1 | FileCheck %s + +; Verify warning is generated when vectorization/ interleaving is explicitly specified and fails to occur. +; CHECK: warning: no_array_bounds.cpp:5:5: loop not vectorized: failed explicitly specified loop vectorization +; CHECK: warning: no_array_bounds.cpp:10:5: loop not interleaved: failed explicitly specified loop interleaving + +; #pragma clang loop vectorize(enable) +; for (int i = 0; i < number; i++) { +; A[B[i]]++; +; } + +; #pragma clang loop vectorize(disable) interleave(enable) +; for (int i = 0; i < number; i++) { +; B[A[i]]++; +; } + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +; Function Attrs: nounwind ssp uwtable +define void @_Z4testPiS_i(i32* nocapture %A, i32* nocapture %B, i32 %number) #0 { +entry: + %cmp25 = icmp sgt i32 %number, 0, !dbg !10 + br i1 %cmp25, label %for.body.preheader, label %for.end15, !dbg !10, !llvm.loop !12 + +for.body.preheader: ; preds = %entry + br label %for.body, !dbg !14 + +for.cond5.preheader: ; preds = %for.body + br i1 %cmp25, label %for.body7.preheader, label %for.end15, !dbg !16, !llvm.loop !18 + +for.body7.preheader: ; preds = %for.cond5.preheader + br label %for.body7, !dbg !20 + +for.body: ; preds = %for.body.preheader, %for.body + %indvars.iv27 = phi i64 [ %indvars.iv.next28, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv27, !dbg !14 + %0 = load i32* %arrayidx, align 4, !dbg !14, !tbaa !22 + %idxprom1 = sext i32 %0 to i64, !dbg !14 + %arrayidx2 = getelementptr inbounds i32* %A, i64 %idxprom1, !dbg !14 + %1 = load i32* %arrayidx2, align 4, !dbg !14, !tbaa !22 + %inc = add nsw i32 %1, 1, !dbg !14 + store i32 %inc, i32* %arrayidx2, align 4, !dbg !14, !tbaa !22 + %indvars.iv.next28 = add nuw nsw i64 %indvars.iv27, 1, !dbg !10 + %lftr.wideiv29 = trunc i64 %indvars.iv.next28 to i32, !dbg !10 + %exitcond30 = icmp eq i32 %lftr.wideiv29, %number, !dbg !10 + br i1 %exitcond30, label %for.cond5.preheader, label %for.body, !dbg !10, !llvm.loop !12 + +for.body7: ; preds = %for.body7.preheader, %for.body7 + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body7 ], [ 0, %for.body7.preheader ] + %arrayidx9 = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !20 + %2 = load i32* %arrayidx9, align 4, !dbg !20, !tbaa !22 + %idxprom10 = sext i32 %2 to i64, !dbg !20 + %arrayidx11 = getelementptr inbounds i32* %B, i64 %idxprom10, !dbg !20 + %3 = load i32* %arrayidx11, align 4, !dbg !20, !tbaa !22 + %inc12 = add nsw i32 %3, 1, !dbg !20 + store i32 %inc12, i32* %arrayidx11, align 4, !dbg !20, !tbaa !22 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !16 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !16 + %exitcond = icmp eq i32 %lftr.wideiv, %number, !dbg !16 + br i1 %exitcond, label %for.end15.loopexit, label %for.body7, !dbg !16, !llvm.loop !18 + +for.end15.loopexit: ; preds = %for.body7 + br label %for.end15 + +for.end15: ; preds = %for.end15.loopexit, %entry, %for.cond5.preheader + ret void, !dbg !26 +} + +attributes #0 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5.0", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 2} +!1 = metadata !{metadata !"no_array_bounds.cpp", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"test", metadata !"test", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i32*, i32*, i32)* @_Z4testPiS_i, null, null, metadata !2, i32 2} +!5 = metadata !{i32 786473, metadata !1} +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} +!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 2} +!8 = metadata !{i32 2, metadata !"Debug Info Version", i32 1} +!9 = metadata !{metadata !"clang version 3.5.0"} +!10 = metadata !{i32 4, i32 8, metadata !11, null} +!11 = metadata !{i32 786443, metadata !1, metadata !4, i32 4, i32 3, i32 0, i32 0} +!12 = metadata !{metadata !12, metadata !13} +!13 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} +!14 = metadata !{i32 5, i32 5, metadata !15, null} +!15 = metadata !{i32 786443, metadata !1, metadata !11, i32 4, i32 36, i32 0, i32 1} +!16 = metadata !{i32 9, i32 8, metadata !17, null} +!17 = metadata !{i32 786443, metadata !1, metadata !4, i32 9, i32 3, i32 0, i32 2} +!18 = metadata !{metadata !18, metadata !13, metadata !19} +!19 = metadata !{metadata !"llvm.loop.vectorize.width", i32 1} +!20 = metadata !{i32 10, i32 5, metadata !21, null} +!21 = metadata !{i32 786443, metadata !1, metadata !17, i32 9, i32 36, i32 0, i32 3} +!22 = metadata !{metadata !23, metadata !23, i64 0} +!23 = metadata !{metadata !"int", metadata !24, i64 0} +!24 = metadata !{metadata !"omnipotent char", metadata !25, i64 0} +!25 = metadata !{metadata !"Simple C/C++ TBAA"} +!26 = metadata !{i32 12, i32 1, metadata !4, null} diff --git a/test/Transforms/LoopVectorize/no_switch.ll b/test/Transforms/LoopVectorize/no_switch.ll new file mode 100644 index 000000000000..8f654e41d4c8 --- /dev/null +++ b/test/Transforms/LoopVectorize/no_switch.ll @@ -0,0 +1,86 @@ +; RUN: opt < %s -loop-vectorize -force-vector-width=4 -S -pass-remarks-missed='loop-vectorize' -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s + +; CHECK: remark: source.cpp:4:5: loop not vectorized: loop contains a switch statement +; CHECK: remark: source.cpp:4:5: loop not vectorized: vectorization is explicitly enabled with width 4 +; CHECK: warning: source.cpp:4:5: loop not vectorized: failed explicitly specified loop vectorization + +; CHECK: _Z11test_switchPii +; CHECK-NOT: x i32> +; CHECK: ret + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +; Function Attrs: nounwind optsize ssp uwtable +define void @_Z11test_switchPii(i32* nocapture %A, i32 %Length) #0 { +entry: + %cmp18 = icmp sgt i32 %Length, 0, !dbg !10 + br i1 %cmp18, label %for.body.preheader, label %for.end, !dbg !10, !llvm.loop !12 + +for.body.preheader: ; preds = %entry + br label %for.body, !dbg !14 + +for.body: ; preds = %for.body.preheader, %for.inc + %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv, !dbg !14 + %0 = load i32* %arrayidx, align 4, !dbg !14, !tbaa !16 + switch i32 %0, label %for.inc [ + i32 0, label %sw.bb + i32 1, label %sw.bb3 + ], !dbg !14 + +sw.bb: ; preds = %for.body + %1 = trunc i64 %indvars.iv to i32, !dbg !20 + %mul = shl nsw i32 %1, 1, !dbg !20 + br label %for.inc, !dbg !22 + +sw.bb3: ; preds = %for.body + %2 = trunc i64 %indvars.iv to i32, !dbg !23 + store i32 %2, i32* %arrayidx, align 4, !dbg !23, !tbaa !16 + br label %for.inc, !dbg !23 + +for.inc: ; preds = %sw.bb3, %for.body, %sw.bb + %storemerge = phi i32 [ %mul, %sw.bb ], [ 0, %for.body ], [ 0, %sw.bb3 ] + store i32 %storemerge, i32* %arrayidx, align 4, !dbg !20, !tbaa !16 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1, !dbg !10 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !10 + %exitcond = icmp eq i32 %lftr.wideiv, %Length, !dbg !10 + br i1 %exitcond, label %for.end.loopexit, label %for.body, !dbg !10, !llvm.loop !12 + +for.end.loopexit: ; preds = %for.inc + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret void, !dbg !24 +} + +attributes #0 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5.0", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 2} +!1 = metadata !{metadata !"source.cpp", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"test_switch", metadata !"test_switch", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i32*, i32)* @_Z11test_switchPii, null, null, metadata !2, i32 1} +!5 = metadata !{i32 786473, metadata !1} +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} +!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 2} +!8 = metadata !{i32 2, metadata !"Debug Info Version", i32 1} +!9 = metadata !{metadata !"clang version 3.5.0"} +!10 = metadata !{i32 3, i32 8, metadata !11, null} +!11 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 3, i32 0, i32 0} +!12 = metadata !{metadata !12, metadata !13, metadata !13} +!13 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} +!14 = metadata !{i32 4, i32 5, metadata !15, null} +!15 = metadata !{i32 786443, metadata !1, metadata !11, i32 3, i32 36, i32 0, i32 1} +!16 = metadata !{metadata !17, metadata !17, i64 0} +!17 = metadata !{metadata !"int", metadata !18, i64 0} +!18 = metadata !{metadata !"omnipotent char", metadata !19, i64 0} +!19 = metadata !{metadata !"Simple C/C++ TBAA"} +!20 = metadata !{i32 6, i32 7, metadata !21, null} +!21 = metadata !{i32 786443, metadata !1, metadata !15, i32 4, i32 18, i32 0, i32 2} +!22 = metadata !{i32 7, i32 5, metadata !21, null} +!23 = metadata !{i32 9, i32 7, metadata !21, null} +!24 = metadata !{i32 14, i32 1, metadata !4, null} diff --git a/test/Transforms/LoopVectorize/ptr_loops.ll b/test/Transforms/LoopVectorize/ptr_loops.ll index 15983f068556..1259e21ebf2e 100644 --- a/test/Transforms/LoopVectorize/ptr_loops.ll +++ b/test/Transforms/LoopVectorize/ptr_loops.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S -enable-if-conversion | FileCheck %s +; RUN: opt < %s -basicaa -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S -enable-if-conversion | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" diff --git a/test/Transforms/LoopVectorize/runtime-check-address-space.ll b/test/Transforms/LoopVectorize/runtime-check-address-space.ll index 6c86561a1c7e..5bf7020a475a 100644 --- a/test/Transforms/LoopVectorize/runtime-check-address-space.ll +++ b/test/Transforms/LoopVectorize/runtime-check-address-space.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -march=r600 -mcpu=cayman -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine < %s | FileCheck %s +; RUN: opt -S -march=r600 -mcpu=cayman -basicaa -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine < %s | FileCheck %s ; Check vectorization that would ordinarily require a runtime bounds ; check on the pointers when mixing address spaces. For now we cannot diff --git a/test/Transforms/LoopVectorize/runtime-check-readonly.ll b/test/Transforms/LoopVectorize/runtime-check-readonly.ll index a2b9ad94c837..73b28301b7e7 100644 --- a/test/Transforms/LoopVectorize/runtime-check-readonly.ll +++ b/test/Transforms/LoopVectorize/runtime-check-readonly.ll @@ -5,13 +5,16 @@ target triple = "x86_64-apple-macosx10.8.0" ;CHECK-LABEL: @add_ints( ;CHECK: br +;CHECK: br ;CHECK: getelementptr -;CHECK-NEXT: getelementptr -;CHECK-NEXT: icmp uge -;CHECK-NEXT: icmp uge -;CHECK-NEXT: icmp uge -;CHECK-NEXT: icmp uge -;CHECK-NEXT: and +;CHECK-DAG: getelementptr +;CHECK-DAG: icmp uge +;CHECK-DAG: icmp uge +;CHECK-DAG: icmp uge +;CHECK-DAG: icmp uge +;CHECK-DAG: and +;CHECK-DAG: and +;CHECK: br ;CHECK: ret define void @add_ints(i32* nocapture %A, i32* nocapture %B, i32* nocapture %C) { entry: diff --git a/test/Transforms/LoopVectorize/store-shuffle-bug.ll b/test/Transforms/LoopVectorize/store-shuffle-bug.ll index 0ec8010756d1..26f4d156df61 100644 --- a/test/Transforms/LoopVectorize/store-shuffle-bug.ll +++ b/test/Transforms/LoopVectorize/store-shuffle-bug.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine < %s | FileCheck %s +; RUN: opt -S -basicaa -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" @@ -19,18 +19,13 @@ entry: ; CHECK-LABEL: @t( ; CHECK: vector.body: -; CHECK: load <4 x i32> -; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = shufflevector -; CHECK: load <4 x i32> -; CHECK: [[VAR2:%[a-zA-Z0-9]+]] = shufflevector +; CHECK: [[VAR1:%[a-zA-Z0-9.]+]] = load <4 x i32> +; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = load <4 x i32> ; CHECK: [[VAR3:%[a-zA-Z0-9]+]] = add nsw <4 x i32> [[VAR2]], [[VAR1]] -; CHECK: [[VAR4:%[a-zA-Z0-9]+]] = shufflevector <4 x i32> [[VAR3]] -; CHECK: store <4 x i32> [[VAR4]] -; CHECK: load <4 x i32> -; CHECK: [[VAR5:%[a-zA-Z0-9]+]] = shufflevector -; CHECK-NOT: add nsw <4 x i32> [[VAR4]], [[VAR5]] -; CHECK-NOT: add nsw <4 x i32> [[VAR5]], [[VAR4]] -; CHECK: add nsw <4 x i32> [[VAR3]], [[VAR5]] +; CHECK: store <4 x i32> [[VAR3]] +; CHECK: [[VAR4:%[a-zA-Z0-9.]+]] = load <4 x i32> +; CHECK: add nsw <4 x i32> [[VAR3]], [[VAR4]] +; CHECK-NOT: shufflevector for.body: %indvars.iv = phi i64 [ 93, %entry ], [ %indvars.iv.next, %for.body ] diff --git a/test/Transforms/LoopVectorize/tbaa-nodep.ll b/test/Transforms/LoopVectorize/tbaa-nodep.ll new file mode 100644 index 000000000000..f31b3072bc6c --- /dev/null +++ b/test/Transforms/LoopVectorize/tbaa-nodep.ll @@ -0,0 +1,102 @@ +; RUN: opt < %s -tbaa -basicaa -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -simplifycfg -S | FileCheck %s +; RUN: opt < %s -basicaa -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -simplifycfg -S | FileCheck %s --check-prefix=CHECK-NOTBAA +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Function Attrs: nounwind uwtable +define i32 @test1(i32* nocapture %a, float* nocapture readonly %b) #0 { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !tbaa !0 + %conv = fptosi float %0 to i32 + %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv + store i32 %conv, i32* %arrayidx2, align 4, !tbaa !4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1600 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i32 0 + +; TBAA partitions the accesses in this loop, so it can be vectorized without +; runtime checks. + +; CHECK-LABEL: @test1 +; CHECK: entry: +; CHECK-NEXT: br label %vector.body +; CHECK: vector.body: + +; CHECK: load <4 x float>* %{{.*}}, align 4, !tbaa +; CHECK: store <4 x i32> %{{.*}}, <4 x i32>* %{{.*}}, align 4, !tbaa + +; CHECK: ret i32 0 + +; CHECK-NOTBAA-LABEL: @test1 +; CHECK-NOTBAA: icmp uge i32* + +; CHECK-NOTBAA: load <4 x float>* %{{.*}}, align 4, !tbaa +; CHECK-NOTBAA: store <4 x i32> %{{.*}}, <4 x i32>* %{{.*}}, align 4, !tbaa + +; CHECK-NOTBAA: ret i32 0 +} + +; Function Attrs: nounwind uwtable +define i32 @test2(i32* nocapture readonly %a, float* nocapture readonly %b, float* nocapture %c) #0 { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv + %0 = load float* %arrayidx, align 4, !tbaa !0 + %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv + %1 = load i32* %arrayidx2, align 4, !tbaa !4 + %conv = sitofp i32 %1 to float + %mul = fmul float %0, %conv + %arrayidx4 = getelementptr inbounds float* %c, i64 %indvars.iv + store float %mul, float* %arrayidx4, align 4, !tbaa !0 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1600 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i32 0 + +; This test is like the first, except here there is still one runtime check +; required. Without TBAA, however, two checks are required. + +; CHECK-LABEL: @test2 +; CHECK: icmp uge float* +; CHECK: icmp uge float* +; CHECK-NOT: icmp uge i32* + +; CHECK: load <4 x float>* %{{.*}}, align 4, !tbaa +; CHECK: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 4, !tbaa + +; CHECK: ret i32 0 + +; CHECK-NOTBAA-LABEL: @test2 +; CHECK-NOTBAA: icmp uge float* +; CHECK-NOTBAA: icmp uge float* +; CHECK-NOTBAA-DAG: icmp uge float* +; CHECK-NOTBAA-DAG: icmp uge i32* + +; CHECK-NOTBAA: load <4 x float>* %{{.*}}, align 4, !tbaa +; CHECK-NOTBAA: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 4, !tbaa + +; CHECK-NOTBAA: ret i32 0 +} + +attributes #0 = { nounwind uwtable } + +!0 = metadata !{metadata !1, metadata !1, i64 0} +!1 = metadata !{metadata !"float", metadata !2, i64 0} +!2 = metadata !{metadata !"omnipotent char", metadata !3, i64 0} +!3 = metadata !{metadata !"Simple C/C++ TBAA"} +!4 = metadata !{metadata !5, metadata !5, i64 0} +!5 = metadata !{metadata !"int", metadata !2, i64 0} + diff --git a/test/Transforms/LoopVectorize/unroll_novec.ll b/test/Transforms/LoopVectorize/unroll_novec.ll index 33f128da905d..89f4678526de 100644 --- a/test/Transforms/LoopVectorize/unroll_novec.ll +++ b/test/Transforms/LoopVectorize/unroll_novec.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -loop-vectorize -force-vector-width=1 -force-vector-unroll=2 -dce -instcombine -S | FileCheck %s +; RUN: opt < %s -loop-vectorize -force-vector-width=1 -force-target-num-scalar-regs=16 -force-target-max-scalar-unroll=8 -force-target-instruction-cost=1 -small-loop-cost=40 -dce -instcombine -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" @@ -12,10 +12,20 @@ target triple = "x86_64-apple-macosx10.8.0" ;CHECK-LABEL: @inc( ;CHECK: load i32* ;CHECK: load i32* +;CHECK: load i32* +;CHECK: load i32* +;CHECK-NOT: load i32* +;CHECK: add nsw i32 ;CHECK: add nsw i32 ;CHECK: add nsw i32 +;CHECK: add nsw i32 +;CHECK-NOT: add nsw i32 +;CHECK: store i32 +;CHECK: store i32 ;CHECK: store i32 ;CHECK: store i32 +;CHECK-NOT: store i32 +;CHECK: add i64 %{{.*}}, 4 ;CHECK: ret void define void @inc(i32 %n) nounwind uwtable noinline ssp { %1 = icmp sgt i32 %n, 0 diff --git a/test/Transforms/LoopVectorize/value-ptr-bug.ll b/test/Transforms/LoopVectorize/value-ptr-bug.ll index e8d37285f803..6b06afaf0de2 100644 --- a/test/Transforms/LoopVectorize/value-ptr-bug.ll +++ b/test/Transforms/LoopVectorize/value-ptr-bug.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ; PR16073 -; Because we were caching value pointers accross a function call that could RAUW +; Because we were caching value pointers across a function call that could RAUW ; we would generate an undefined value store below: ; SCEVExpander::expandCodeFor would change a value (the start value of an ; induction) that we cached in the induction variable list. diff --git a/test/Transforms/LoopVectorize/vect.omp.persistence.ll b/test/Transforms/LoopVectorize/vect.omp.persistence.ll new file mode 100644 index 000000000000..f6465677839e --- /dev/null +++ b/test/Transforms/LoopVectorize/vect.omp.persistence.ll @@ -0,0 +1,88 @@ +; RUN: opt < %s -O2 -force-vector-unroll=2 -force-vector-width=4 -debug-only=loop-vectorize -stats -S 2>&1 | FileCheck %s +; REQUIRES: asserts + +; Loop from "rotated" +; CHECK: LV: Loop hints: force=enabled +; Loop from "nonrotated" +; CHECK: LV: Loop hints: force=enabled +; No more loops in the module +; CHECK-NOT: LV: Loop hints: force= +; In total only 1 loop should be rotated. +; CHECK: 1 loop-rotate + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; See http://reviews.llvm.org/D3348 for details. + +; +; Test #1 +; +; Ensure that "llvm.loop.vectorize.enable" metadata was not lost prior to LoopVectorize pass. +; In past LoopRotate was clearing that metadata. +; +; The source C code is: +; void rotated(float *a, int size) +; { +; int t = 0; +; #pragma omp simd +; for (int i = 0; i < size; ++i) { +; a[i] = a[i-5] * a[i+2]; +; ++t; +; } +;} + +define void @rotated(float* nocapture %a, i64 %size) { +entry: + %cmp1 = icmp sgt i64 %size, 0 + br i1 %cmp1, label %for.header, label %for.end + +for.header: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %cmp2 = icmp sgt i64 %indvars.iv, %size + br i1 %cmp2, label %for.end, label %for.body + +for.body: + + %0 = add nsw i64 %indvars.iv, -5 + %arrayidx = getelementptr inbounds float* %a, i64 %0 + %1 = load float* %arrayidx, align 4, !llvm.mem.parallel_loop_access !1 + %2 = add nsw i64 %indvars.iv, 2 + %arrayidx2 = getelementptr inbounds float* %a, i64 %2 + %3 = load float* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !1 + %mul = fmul float %1, %3 + %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv + store float %mul, float* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !1 + + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + br label %for.header, !llvm.loop !1 + +for.end: + ret void +} + +!1 = metadata !{metadata !1, metadata !2} +!2 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} + +; +; Test #2 +; +; Ensure that "llvm.loop.vectorize.enable" metadata was not lost even +; if loop was not rotated (see http://reviews.llvm.org/D3348#comment-4). +; +define i32 @nonrotated(i32 %a) { +entry: + br label %loop_cond +loop_cond: + %indx = phi i32 [ 1, %entry ], [ %inc, %loop_inc ] + %cmp = icmp ne i32 %indx, %a + br i1 %cmp, label %return, label %loop_inc +loop_inc: + %inc = add i32 %indx, 1 + br label %loop_cond, !llvm.loop !3 +return: + ret i32 0 +} + +!3 = metadata !{metadata !3, metadata !4} +!4 = metadata !{metadata !"llvm.loop.vectorize.enable", i1 true} diff --git a/test/Transforms/LoopVectorize/vect.stats.ll b/test/Transforms/LoopVectorize/vect.stats.ll new file mode 100644 index 000000000000..92ec24f726ee --- /dev/null +++ b/test/Transforms/LoopVectorize/vect.stats.ll @@ -0,0 +1,65 @@ +; RUN: opt < %s -loop-vectorize -force-vector-unroll=4 -force-vector-width=4 -debug-only=loop-vectorize -stats -S 2>&1 | FileCheck %s +; REQUIRES: asserts + +; +; We have 2 loops, one of them is vectorizable and the second one is not. +; + +; CHECK: 2 loop-vectorize - Number of loops analyzed for vectorization +; CHECK: 1 loop-vectorize - Number of loops vectorized + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @vectorized(float* nocapture %a, i64 %size) { +entry: + %cmp1 = icmp sgt i64 %size, 0 + br i1 %cmp1, label %for.header, label %for.end + +for.header: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %cmp2 = icmp sgt i64 %indvars.iv, %size + br i1 %cmp2, label %for.end, label %for.body + +for.body: + + %arrayidx = getelementptr inbounds float* %a, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %mul = fmul float %0, %0 + store float %mul, float* %arrayidx, align 4 + + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + br label %for.header + +for.end: + ret void +} + +define void @not_vectorized(float* nocapture %a, i64 %size) { +entry: + %cmp1 = icmp sgt i64 %size, 0 + br i1 %cmp1, label %for.header, label %for.end + +for.header: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %cmp2 = icmp sgt i64 %indvars.iv, %size + br i1 %cmp2, label %for.end, label %for.body + +for.body: + + %0 = add nsw i64 %indvars.iv, -5 + %arrayidx = getelementptr inbounds float* %a, i64 %0 + %1 = load float* %arrayidx, align 4 + %2 = add nsw i64 %indvars.iv, 2 + %arrayidx2 = getelementptr inbounds float* %a, i64 %2 + %3 = load float* %arrayidx2, align 4 + %mul = fmul float %1, %3 + %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv + store float %mul, float* %arrayidx4, align 4 + + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + br label %for.header + +for.end: + ret void +}
\ No newline at end of file diff --git a/test/Transforms/LoopVectorize/vectorize-once.ll b/test/Transforms/LoopVectorize/vectorize-once.ll index 780046930e1b..97654f495018 100644 --- a/test/Transforms/LoopVectorize/vectorize-once.ll +++ b/test/Transforms/LoopVectorize/vectorize-once.ll @@ -69,9 +69,9 @@ _ZSt10accumulateIPiiET0_T_S2_S1_.exit: ; preds = %for.body.i, %entry attributes #0 = { nounwind readonly ssp uwtable "fp-contract-model"="standard" "no-frame-pointer-elim" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="pic" "ssp-buffers-size"="8" } ; CHECK: !0 = metadata !{metadata !0, metadata !1, metadata !2} -; CHECK: !1 = metadata !{metadata !"llvm.vectorizer.width", i32 1} -; CHECK: !2 = metadata !{metadata !"llvm.vectorizer.unroll", i32 1} +; CHECK: !1 = metadata !{metadata !"llvm.loop.vectorize.width", i32 1} +; CHECK: !2 = metadata !{metadata !"llvm.loop.interleave.count", i32 1} ; CHECK: !3 = metadata !{metadata !3, metadata !1, metadata !2} !0 = metadata !{metadata !0, metadata !1} -!1 = metadata !{metadata !"llvm.vectorizer.width", i32 1} +!1 = metadata !{metadata !"llvm.loop.vectorize.width", i32 1} diff --git a/test/Transforms/LoopVectorize/version-mem-access.ll b/test/Transforms/LoopVectorize/version-mem-access.ll new file mode 100644 index 000000000000..51d20e227ddf --- /dev/null +++ b/test/Transforms/LoopVectorize/version-mem-access.ll @@ -0,0 +1,87 @@ +; RUN: opt -basicaa -loop-vectorize -enable-mem-access-versioning -force-vector-width=2 -force-vector-unroll=1 < %s -S | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +; CHECK-LABEL: test +define void @test(i32* noalias %A, i64 %AStride, + i32* noalias %B, i32 %BStride, + i32* noalias %C, i64 %CStride, i32 %N) { +entry: + %cmp13 = icmp eq i32 %N, 0 + br i1 %cmp13, label %for.end, label %for.body.preheader + +; CHECK-DAG: icmp ne i64 %AStride, 1 +; CHECK-DAG: icmp ne i32 %BStride, 1 +; CHECK-DAG: icmp ne i64 %CStride, 1 +; CHECK: or +; CHECK: or +; CHECK: br + +; CHECK: vector.body +; CHECK: load <2 x i32> + +for.body.preheader: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %iv.trunc = trunc i64 %indvars.iv to i32 + %mul = mul i32 %iv.trunc, %BStride + %mul64 = zext i32 %mul to i64 + %arrayidx = getelementptr inbounds i32* %B, i64 %mul64 + %0 = load i32* %arrayidx, align 4 + %mul2 = mul nsw i64 %indvars.iv, %CStride + %arrayidx3 = getelementptr inbounds i32* %C, i64 %mul2 + %1 = load i32* %arrayidx3, align 4 + %mul4 = mul nsw i32 %1, %0 + %mul3 = mul nsw i64 %indvars.iv, %AStride + %arrayidx7 = getelementptr inbounds i32* %A, i64 %mul3 + store i32 %mul4, i32* %arrayidx7, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %N + br i1 %exitcond, label %for.end.loopexit, label %for.body + +for.end.loopexit: + br label %for.end + +for.end: + ret void +} + +; We used to crash on this function because we removed the fptosi cast when +; replacing the symbolic stride '%conv'. +; PR18480 + +; CHECK-LABEL: fn1 +; CHECK: load <2 x double> + +define void @fn1(double* noalias %x, double* noalias %c, double %a) { +entry: + %conv = fptosi double %a to i32 + %cmp8 = icmp sgt i32 %conv, 0 + br i1 %cmp8, label %for.body.preheader, label %for.end + +for.body.preheader: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ] + %0 = trunc i64 %indvars.iv to i32 + %mul = mul nsw i32 %0, %conv + %idxprom = sext i32 %mul to i64 + %arrayidx = getelementptr inbounds double* %x, i64 %idxprom + %1 = load double* %arrayidx, align 8 + %arrayidx3 = getelementptr inbounds double* %c, i64 %indvars.iv + store double %1, double* %arrayidx3, align 8 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %conv + br i1 %exitcond, label %for.end.loopexit, label %for.body + +for.end.loopexit: + br label %for.end + +for.end: + ret void +} diff --git a/test/Transforms/LowerAtomic/atomic-swap.ll b/test/Transforms/LowerAtomic/atomic-swap.ll index 4331677764ba..cb1124136f86 100644 --- a/test/Transforms/LowerAtomic/atomic-swap.ll +++ b/test/Transforms/LowerAtomic/atomic-swap.ll @@ -3,15 +3,20 @@ define i8 @cmpswap() { ; CHECK-LABEL: @cmpswap( %i = alloca i8 - %j = cmpxchg i8* %i, i8 0, i8 42 monotonic -; CHECK: [[INST:%[a-z0-9]+]] = load -; CHECK-NEXT: icmp -; CHECK-NEXT: select -; CHECK-NEXT: store + %pair = cmpxchg i8* %i, i8 0, i8 42 monotonic monotonic + %j = extractvalue { i8, i1 } %pair, 0 +; CHECK: [[OLDVAL:%[a-z0-9]+]] = load i8* [[ADDR:%[a-z0-9]+]] +; CHECK-NEXT: [[SAME:%[a-z0-9]+]] = icmp eq i8 [[OLDVAL]], 0 +; CHECK-NEXT: [[TO_STORE:%[a-z0-9]+]] = select i1 [[SAME]], i8 42, i8 [[OLDVAL]] +; CHECK-NEXT: store i8 [[TO_STORE]], i8* [[ADDR]] +; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = insertvalue { i8, i1 } undef, i8 [[OLDVAL]], 0 +; CHECK-NEXT: [[RES:%[a-z0-9]+]] = insertvalue { i8, i1 } [[TMP]], i1 [[SAME]], 1 +; CHECK-NEXT: [[VAL:%[a-z0-9]+]] = extractvalue { i8, i1 } [[RES]], 0 ret i8 %j -; CHECK: ret i8 [[INST]] +; CHECK: ret i8 [[VAL]] } + define i8 @swap() { ; CHECK-LABEL: @swap( %i = alloca i8 diff --git a/test/Transforms/LowerExpectIntrinsic/basic.ll b/test/Transforms/LowerExpectIntrinsic/basic.ll index 955209af14a6..e184cb05b94a 100644 --- a/test/Transforms/LowerExpectIntrinsic/basic.ll +++ b/test/Transforms/LowerExpectIntrinsic/basic.ll @@ -245,6 +245,35 @@ return: ; preds = %if.end, %if.then declare i32 @llvm.expect.i32(i32, i32) nounwind readnone +; CHECK-LABEL: @test9( +define i32 @test9(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp sgt i32 %tmp, 1 + %expval = call i1 @llvm.expect.i1(i1 %cmp, i1 1) +; CHECK: !prof !0 +; CHECK-NOT: @llvm.expect + br i1 %expval, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +declare i1 @llvm.expect.i1(i1, i1) nounwind readnone + ; CHECK: !0 = metadata !{metadata !"branch_weights", i32 64, i32 4} ; CHECK: !1 = metadata !{metadata !"branch_weights", i32 4, i32 64} ; CHECK: !2 = metadata !{metadata !"branch_weights", i32 4, i32 64, i32 4} diff --git a/test/Transforms/LowerInvoke/2004-02-29-PHICrash.ll b/test/Transforms/LowerInvoke/2004-02-29-PHICrash.ll deleted file mode 100644 index bddb70248ed8..000000000000 --- a/test/Transforms/LowerInvoke/2004-02-29-PHICrash.ll +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: opt < %s -lowerinvoke -enable-correct-eh-support -disable-output - -define void @_ZNKSt11__use_cacheISt16__numpunct_cacheIcEEclERKSt6locale() { -entry: - br i1 false, label %then, label %UnifiedReturnBlock -then: ; preds = %entry - invoke void @_Znwj( ) - to label %UnifiedReturnBlock unwind label %UnifiedReturnBlock -UnifiedReturnBlock: ; preds = %then, %then, %entry - %UnifiedRetVal = phi i32* [ null, %entry ], [ null, %then ], [ null, %then ] ; <i32*> [#uses=0] - ret void -} - -declare void @_Znwj() - diff --git a/test/Transforms/LowerInvoke/2005-08-03-InvokeWithPHI.ll b/test/Transforms/LowerInvoke/2005-08-03-InvokeWithPHI.ll deleted file mode 100644 index 1057ad7057cc..000000000000 --- a/test/Transforms/LowerInvoke/2005-08-03-InvokeWithPHI.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: opt < %s -lowerinvoke -enable-correct-eh-support -disable-output - -declare void @ll_listnext__listiterPtr() - -define void @WorkTask.fn() { -block0: - invoke void @ll_listnext__listiterPtr( ) - to label %block9 unwind label %block8_exception_handling -block8_exception_handling: ; preds = %block0 - ret void -block9: ; preds = %block0 - %w_2690 = phi { i32, i32 }* [ null, %block0 ] ; <{ i32, i32 }*> [#uses=1] - %tmp.129 = getelementptr { i32, i32 }* %w_2690, i32 0, i32 1 ; <i32*> [#uses=1] - %v2769 = load i32* %tmp.129 ; <i32> [#uses=0] - ret void -} - diff --git a/test/Transforms/LowerInvoke/2005-08-03-InvokeWithPHIUse.ll b/test/Transforms/LowerInvoke/2005-08-03-InvokeWithPHIUse.ll deleted file mode 100644 index 940204649c74..000000000000 --- a/test/Transforms/LowerInvoke/2005-08-03-InvokeWithPHIUse.ll +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: opt < %s -lowerinvoke -enable-correct-eh-support -disable-output - -declare fastcc i32 @ll_listnext__listiterPtr() - -define fastcc i32 @WorkTask.fn() { -block0: - %v2679 = invoke fastcc i32 @ll_listnext__listiterPtr( ) - to label %block9 unwind label %block8_exception_handling ; <i32> [#uses=1] -block8_exception_handling: ; preds = %block0 - ret i32 0 -block9: ; preds = %block0 - %i_2689 = phi i32 [ %v2679, %block0 ] ; <i32> [#uses=1] - ret i32 %i_2689 -} - diff --git a/test/Transforms/LowerInvoke/2008-02-14-CritEdgePhiCrash.ll b/test/Transforms/LowerInvoke/2008-02-14-CritEdgePhiCrash.ll deleted file mode 100644 index b46ccfbb79a8..000000000000 --- a/test/Transforms/LowerInvoke/2008-02-14-CritEdgePhiCrash.ll +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: opt < %s -lowerinvoke -enable-correct-eh-support -disable-output -; PR2029 -define i32 @main(i32 %argc, i8** %argv) { -bb470: - invoke i32 @main(i32 0, i8** null) to label %invcont474 unwind label -%lpad902 - -invcont474: ; preds = %bb470 - ret i32 0 - -lpad902: ; preds = %bb470 - %tmp471.lcssa = phi i8* [ null, %bb470 ] ; <i8*> - ret i32 0 -} diff --git a/test/Transforms/LowerInvoke/basictest.ll b/test/Transforms/LowerInvoke/basictest.ll deleted file mode 100644 index f0ca5f425311..000000000000 --- a/test/Transforms/LowerInvoke/basictest.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: opt < %s -lowerinvoke -disable-output -enable-correct-eh-support - - -define i32 @foo() { - invoke i32 @foo( ) - to label %Ok unwind label %Crap ; <i32>:1 [#uses=0] -Ok: ; preds = %0 - invoke i32 @foo( ) - to label %Ok2 unwind label %Crap ; <i32>:2 [#uses=0] -Ok2: ; preds = %Ok - ret i32 2 -Crap: ; preds = %Ok, %0 - ret i32 1 -} - -define i32 @bar(i32 %blah) { - br label %doit -doit: ; preds = %0 - ;; Value live across an unwind edge. - %B2 = add i32 %blah, 1 ; <i32> [#uses=1] - invoke i32 @foo( ) - to label %Ok unwind label %Crap ; <i32>:1 [#uses=0] -Ok: ; preds = %doit - invoke i32 @foo( ) - to label %Ok2 unwind label %Crap ; <i32>:2 [#uses=0] -Ok2: ; preds = %Ok - ret i32 2 -Crap: ; preds = %Ok, %doit - ret i32 %B2 -} diff --git a/test/Transforms/LowerInvoke/lowerinvoke.ll b/test/Transforms/LowerInvoke/lowerinvoke.ll new file mode 100644 index 000000000000..05c19be7a9ac --- /dev/null +++ b/test/Transforms/LowerInvoke/lowerinvoke.ll @@ -0,0 +1,25 @@ +; RUN: opt < %s -lowerinvoke -S | FileCheck %s + +declare i32 @external_func(i64 %arg) + +define i32 @invoke_test(i64 %arg) { +entry: + %result = invoke fastcc i32 @external_func(i64 inreg %arg) + to label %cont unwind label %lpad +cont: + ret i32 %result +lpad: + %phi = phi i32 [ 99, %entry ] + %lp = landingpad { i8*, i32 } personality i8* null cleanup + ret i32 %phi +} + +; The "invoke" should be converted to a "call". +; CHECK-LABEL: define i32 @invoke_test +; CHECK: %result = call fastcc i32 @external_func(i64 inreg %arg) +; CHECK-NEXT: br label %cont + +; Note that this pass does not remove dead landingpad blocks. +; CHECK: lpad: +; CHECK-NOT: phi +; CHECK: landingpad diff --git a/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll b/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll new file mode 100644 index 000000000000..3673c04a8b81 --- /dev/null +++ b/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll @@ -0,0 +1,27 @@ +; RUN: opt < %s -lowerswitch -S | FileCheck %s +; CHECK-NOT: icmp eq i32 %0, 1 + +define i32 @foo(i32 %a) #0 { +entry: + %retval = alloca i32, align 4 + %a.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + %0 = load i32* %a.addr, align 4 + switch i32 %0, label %sw.default [ + i32 0, label %sw.bb + i32 1, label %sw.bb1 + i32 2, label %sw.bb2 + ] + +sw.bb: + ret i32 12 + +sw.bb1: + ret i32 4 + +sw.bb2: + ret i32 2 + +sw.default: + ret i32 9 +} diff --git a/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll b/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll new file mode 100644 index 000000000000..0f737211f598 --- /dev/null +++ b/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll @@ -0,0 +1,41 @@ +; RUN: opt < %s -lowerswitch -S | FileCheck %s +; CHECK-NOT: {{.*}}icmp eq{{.*}} +; +;int foo(int a) { +; +; switch (a) { +; case 0: +; return 10; +; case 1: +; return 3; +; default: +; __builtin_unreachable(); +; } +; +;} + +define i32 @foo(i32 %a) nounwind ssp uwtable { + %1 = alloca i32, align 4 + %2 = alloca i32, align 4 + store i32 %a, i32* %2, align 4 + %3 = load i32* %2, align 4 + switch i32 %3, label %6 [ + i32 0, label %4 + i32 1, label %5 + ] + +; <label>:4 + store i32 10, i32* %1 + br label %7 + +; <label>:5 + store i32 3, i32* %1 + br label %7 + +; <label>:6 + unreachable + +; <label>:7 + %8 = load i32* %1 + ret i32 %8 +} diff --git a/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll b/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll new file mode 100644 index 000000000000..c6cddf636a88 --- /dev/null +++ b/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll @@ -0,0 +1,40 @@ +; RUN: opt < %s -lowerswitch -S | FileCheck %s + +define i32 @test(i32 %arg) #0 { +; CHECK-LABEL: @test +; CHECK: ; <label>:2 +; CHECK-NEXT: %res.0 = phi i32 [ 1, %NodeBlock ], [ 2, %1 ] +; CHECK-NEXT: br label %3 +; CHECK: ; <label>:5 +; CHECK-NEXT: %res.3 = phi i32 [ 0, %NewDefault ], [ %res.2, %4 ] +; CHECK-NEXT: %6 = add nsw i32 %res.3, 1 +; CHECK-NEXT: ret i32 %6 + + switch i32 %arg, label %5 [ + i32 1, label %1 + i32 2, label %2 + i32 3, label %3 + i32 4, label %4 + ] + +; <label>:1 + br label %2 + +; <label>:2 + %res.0 = phi i32 [ 1, %0 ], [ 2, %1 ] + br label %3 + +; <label>:3 + %res.1 = phi i32 [ 0, %0 ], [ %res.0, %2 ] + %phitmp = add nsw i32 %res.1, 2 + br label %4 + +; <label>:4 + %res.2 = phi i32 [ 1, %0 ], [ %phitmp, %3 ] + br label %5 + +; <label>:5 + %res.3 = phi i32 [ 0, %0 ], [ %res.2, %4 ] + %6 = add nsw i32 %res.3, 1 + ret i32 %6 +} diff --git a/test/Transforms/LowerSwitch/feature.ll b/test/Transforms/LowerSwitch/feature.ll index e85f03ee5c78..09d25f0b06d4 100644 --- a/test/Transforms/LowerSwitch/feature.ll +++ b/test/Transforms/LowerSwitch/feature.ll @@ -3,93 +3,57 @@ ; We have switch on input. ; On output we should got binary comparison tree. Check that all is fine. -;CHECK: entry: -;CHECK-NEXT: br label %NodeBlock37 +;CHECK: entry: +;CHECK-NEXT: br label %NodeBlock19 -;CHECK: NodeBlock37: ; preds = %entry -;CHECK-NEXT: %Pivot38 = icmp slt i32 %tmp158, 10 -;CHECK-NEXT: br i1 %Pivot38, label %NodeBlock13, label %NodeBlock35 +;CHECK: NodeBlock19: ; preds = %entry +;CHECK-NEXT: %Pivot20 = icmp slt i32 %tmp158, 10 +;CHECK-NEXT: br i1 %Pivot20, label %NodeBlock5, label %NodeBlock17 -;CHECK: NodeBlock35: ; preds = %NodeBlock37 -;CHECK-NEXT: %Pivot36 = icmp slt i32 %tmp158, 13 -;CHECK-NEXT: br i1 %Pivot36, label %NodeBlock23, label %NodeBlock33 +;CHECK: NodeBlock17: ; preds = %NodeBlock19 +;CHECK-NEXT: %Pivot18 = icmp slt i32 %tmp158, 13 +;CHECK-NEXT: br i1 %Pivot18, label %NodeBlock9, label %NodeBlock15 -;CHECK: NodeBlock33: ; preds = %NodeBlock35 -;CHECK-NEXT: %Pivot34 = icmp slt i32 %tmp158, 14 -;CHECK-NEXT: br i1 %Pivot34, label %LeafBlock25, label %NodeBlock31 +;CHECK: NodeBlock15: ; preds = %NodeBlock17 +;CHECK-NEXT: %Pivot16 = icmp slt i32 %tmp158, 14 +;CHECK-NEXT: br i1 %Pivot16, label %bb330, label %NodeBlock13 -;CHECK: NodeBlock31: ; preds = %NodeBlock33 -;CHECK-NEXT: %Pivot32 = icmp slt i32 %tmp158, 15 -;CHECK-NEXT: br i1 %Pivot32, label %LeafBlock27, label %LeafBlock29 +;CHECK: NodeBlock13: ; preds = %NodeBlock15 +;CHECK-NEXT: %Pivot14 = icmp slt i32 %tmp158, 15 +;CHECK-NEXT: br i1 %Pivot14, label %bb332, label %LeafBlock11 -;CHECK: LeafBlock29: ; preds = %NodeBlock31 -;CHECK-NEXT: %SwitchLeaf30 = icmp eq i32 %tmp158, 15 -;CHECK-NEXT: br i1 %SwitchLeaf30, label %bb334, label %NewDefault +;CHECK: LeafBlock11: ; preds = %NodeBlock13 +;CHECK-NEXT: %SwitchLeaf12 = icmp eq i32 %tmp158, 15 +;CHECK-NEXT: br i1 %SwitchLeaf12, label %bb334, label %NewDefault -;CHECK: LeafBlock27: ; preds = %NodeBlock31 -;CHECK-NEXT: %SwitchLeaf28 = icmp eq i32 %tmp158, 14 -;CHECK-NEXT: br i1 %SwitchLeaf28, label %bb332, label %NewDefault +;CHECK: NodeBlock9: ; preds = %NodeBlock17 +;CHECK-NEXT: %Pivot10 = icmp slt i32 %tmp158, 11 +;CHECK-NEXT: br i1 %Pivot10, label %bb324, label %NodeBlock7 -;CHECK: LeafBlock25: ; preds = %NodeBlock33 -;CHECK-NEXT: %SwitchLeaf26 = icmp eq i32 %tmp158, 13 -;CHECK-NEXT: br i1 %SwitchLeaf26, label %bb330, label %NewDefault +;CHECK: NodeBlock7: ; preds = %NodeBlock9 +;CHECK-NEXT: %Pivot8 = icmp slt i32 %tmp158, 12 +;CHECK-NEXT: br i1 %Pivot8, label %bb326, label %bb328 -;CHECK: NodeBlock23: ; preds = %NodeBlock35 -;CHECK-NEXT: %Pivot24 = icmp slt i32 %tmp158, 11 -;CHECK-NEXT: br i1 %Pivot24, label %LeafBlock15, label %NodeBlock21 +;CHECK: NodeBlock5: ; preds = %NodeBlock19 +;CHECK-NEXT: %Pivot6 = icmp slt i32 %tmp158, 7 +;CHECK-NEXT: br i1 %Pivot6, label %NodeBlock, label %NodeBlock3 -;CHECK: NodeBlock21: ; preds = %NodeBlock23 -;CHECK-NEXT: %Pivot22 = icmp slt i32 %tmp158, 12 -;CHECK-NEXT: br i1 %Pivot22, label %LeafBlock17, label %LeafBlock19 +;CHECK: NodeBlock3: ; preds = %NodeBlock5 +;CHECK-NEXT: %Pivot4 = icmp slt i32 %tmp158, 8 +;CHECK-NEXT: br i1 %Pivot4, label %bb, label %NodeBlock1 -;CHECK: LeafBlock19: ; preds = %NodeBlock21 -;CHECK-NEXT: %SwitchLeaf20 = icmp eq i32 %tmp158, 12 -;CHECK-NEXT: br i1 %SwitchLeaf20, label %bb328, label %NewDefault +;CHECK: NodeBlock1: ; preds = %NodeBlock3 +;CHECK-NEXT: %Pivot2 = icmp slt i32 %tmp158, 9 +;CHECK-NEXT: br i1 %Pivot2, label %bb338, label %bb322 -;CHECK: LeafBlock17: ; preds = %NodeBlock21 -;CHECK-NEXT: %SwitchLeaf18 = icmp eq i32 %tmp158, 11 -;CHECK-NEXT: br i1 %SwitchLeaf18, label %bb326, label %NewDefault +;CHECK: NodeBlock: ; preds = %NodeBlock5 +;CHECK-NEXT: %Pivot = icmp slt i32 %tmp158, 0 +;CHECK-NEXT: br i1 %Pivot, label %LeafBlock, label %bb338 -;CHECK: LeafBlock15: ; preds = %NodeBlock23 -;CHECK-NEXT: %SwitchLeaf16 = icmp eq i32 %tmp158, 10 -;CHECK-NEXT: br i1 %SwitchLeaf16, label %bb324, label %NewDefault - -;CHECK: NodeBlock13: ; preds = %NodeBlock37 -;CHECK-NEXT: %Pivot14 = icmp slt i32 %tmp158, 7 -;CHECK-NEXT: br i1 %Pivot14, label %NodeBlock, label %NodeBlock11 - -;CHECK: NodeBlock11: ; preds = %NodeBlock13 -;CHECK-NEXT: %Pivot12 = icmp slt i32 %tmp158, 8 -;CHECK-NEXT: br i1 %Pivot12, label %LeafBlock3, label %NodeBlock9 - -;CHECK: NodeBlock9: ; preds = %NodeBlock11 -;CHECK-NEXT: %Pivot10 = icmp slt i32 %tmp158, 9 -;CHECK-NEXT: br i1 %Pivot10, label %LeafBlock5, label %LeafBlock7 - -;CHECK: LeafBlock7: ; preds = %NodeBlock9 -;CHECK-NEXT: %SwitchLeaf8 = icmp eq i32 %tmp158, 9 -;CHECK-NEXT: br i1 %SwitchLeaf8, label %bb322, label %NewDefault - -;CHECK: LeafBlock5: ; preds = %NodeBlock9 -;CHECK-NEXT: %SwitchLeaf6 = icmp eq i32 %tmp158, 8 -;CHECK-NEXT: br i1 %SwitchLeaf6, label %bb338, label %NewDefault - -;CHECK: LeafBlock3: ; preds = %NodeBlock11 -;CHECK-NEXT: %SwitchLeaf4 = icmp eq i32 %tmp158, 7 -;CHECK-NEXT: br i1 %SwitchLeaf4, label %bb, label %NewDefault - -;CHECK: NodeBlock: ; preds = %NodeBlock13 -;CHECK-NEXT: %Pivot = icmp slt i32 %tmp158, 0 -;CHECK-NEXT: br i1 %Pivot, label %LeafBlock, label %LeafBlock1 - -;CHECK: LeafBlock1: ; preds = %NodeBlock -;CHECK-NEXT: %SwitchLeaf2 = icmp ule i32 %tmp158, 6 -;CHECK-NEXT: br i1 %SwitchLeaf2, label %bb338, label %NewDefault - -;CHECK: LeafBlock: ; preds = %NodeBlock -;CHECK-NEXT: %tmp158.off = add i32 %tmp158, 6 -;CHECK-NEXT: %SwitchLeaf = icmp ule i32 %tmp158.off, 4 -;CHECK-NEXT: br i1 %SwitchLeaf, label %bb338, label %NewDefault +;CHECK: LeafBlock: ; preds = %NodeBlock +;CHECK-NEXT: %tmp158.off = add i32 %tmp158, 6 +;CHECK-NEXT: %SwitchLeaf = icmp ule i32 %tmp158.off, 4 +;CHECK-NEXT: br i1 %SwitchLeaf, label %bb338, label %NewDefault define i32 @main(i32 %tmp158) { entry: diff --git a/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll b/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll index d124be5f9029..00ac34d93e79 100644 --- a/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll +++ b/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll @@ -6,7 +6,7 @@ target triple = "i386-pc-linux-gnu" %0 = type { x86_fp80, x86_fp80 } -define internal fastcc void @initialize(%0* noalias sret %agg.result) nounwind { +define internal fastcc void @initialize(%0* noalias nocapture sret %agg.result) nounwind { entry: %agg.result.03 = getelementptr %0* %agg.result, i32 0, i32 0 store x86_fp80 0xK00000000000000000000, x86_fp80* %agg.result.03 @@ -15,7 +15,7 @@ entry: ret void } -declare fastcc x86_fp80 @passed_uninitialized(%0*) nounwind +declare fastcc x86_fp80 @passed_uninitialized(%0* nocapture) nounwind define fastcc void @badly_optimized() nounwind { entry: diff --git a/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll b/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll index 597b69dee3d4..6982c8bf2f85 100644 --- a/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll +++ b/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll @@ -4,7 +4,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 %a = type { i32 } %b = type { float } -declare void @g(%a*) +declare void @g(%a* nocapture) define float @f() { entry: diff --git a/test/Transforms/MemCpyOpt/capturing-func.ll b/test/Transforms/MemCpyOpt/capturing-func.ll new file mode 100644 index 000000000000..17614fd181d4 --- /dev/null +++ b/test/Transforms/MemCpyOpt/capturing-func.ll @@ -0,0 +1,22 @@ +; RUN: opt < %s -basicaa -memcpyopt -S | FileCheck %s + +target datalayout = "e" + +declare void @foo(i8*) +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind + +define void @test() { + %ptr1 = alloca i8 + %ptr2 = alloca i8 + call void @foo(i8* %ptr2) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %ptr1, i8* %ptr2, i32 1, i32 1, i1 false) + call void @foo(i8* %ptr1) + ret void + + ; Check that the transformation isn't applied if the called function can + ; capture the pointer argument (i.e. the nocapture attribute isn't present) + ; CHECK-LABEL: @test( + ; CHECK: call void @foo(i8* %ptr2) + ; CHECK-NEXT: call void @llvm.memcpy + ; CHECK-NEXT: call void @foo(i8* %ptr1) +} diff --git a/test/Transforms/MemCpyOpt/form-memset.ll b/test/Transforms/MemCpyOpt/form-memset.ll index 7c7b4fc08809..d980b7fdbd69 100644 --- a/test/Transforms/MemCpyOpt/form-memset.ll +++ b/test/Transforms/MemCpyOpt/form-memset.ll @@ -272,3 +272,15 @@ define void @test9() nounwind { ; CHECK-LABEL: @test9( ; CHECK: call void @llvm.memset.p0i8.i64(i8* bitcast ([16 x i64]* @test9buf to i8*), i8 -1, i64 16, i32 16, i1 false) } + +; PR19092 +define void @test10(i8* nocapture %P) nounwind { + tail call void @llvm.memset.p0i8.i64(i8* %P, i8 0, i64 42, i32 1, i1 false) + tail call void @llvm.memset.p0i8.i64(i8* %P, i8 0, i64 23, i32 1, i1 false) + ret void +; CHECK-LABEL: @test10( +; CHECK-NOT: memset +; CHECK: call void @llvm.memset.p0i8.i64(i8* %P, i8 0, i64 42, i32 1, i1 false) +; CHECK-NOT: memset +; CHECK: ret void +} diff --git a/test/Transforms/MemCpyOpt/loadstore-sret.ll b/test/Transforms/MemCpyOpt/loadstore-sret.ll index 89eabca21bf9..d4a700d03115 100644 --- a/test/Transforms/MemCpyOpt/loadstore-sret.ll +++ b/test/Transforms/MemCpyOpt/loadstore-sret.ll @@ -22,4 +22,4 @@ _ZNSt8auto_ptrIiED1Ev.exit: ret void } -declare void @_Z3barv(%"class.std::auto_ptr"* sret) +declare void @_Z3barv(%"class.std::auto_ptr"* nocapture sret) diff --git a/test/Transforms/MemCpyOpt/memcpy-undef.ll b/test/Transforms/MemCpyOpt/memcpy-undef.ll new file mode 100644 index 000000000000..663b8dcfd3df --- /dev/null +++ b/test/Transforms/MemCpyOpt/memcpy-undef.ll @@ -0,0 +1,46 @@ +; RUN: opt < %s -basicaa -memcpyopt -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +%struct.foo = type { i8, [7 x i8], i32 } + +define i32 @test1(%struct.foo* nocapture %foobie) nounwind noinline ssp uwtable { + %bletch.sroa.1 = alloca [7 x i8], align 1 + %1 = getelementptr inbounds %struct.foo* %foobie, i64 0, i32 0 + store i8 98, i8* %1, align 4 + %2 = getelementptr inbounds %struct.foo* %foobie, i64 0, i32 1, i64 0 + %3 = getelementptr inbounds [7 x i8]* %bletch.sroa.1, i64 0, i64 0 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 7, i32 1, i1 false) + %4 = getelementptr inbounds %struct.foo* %foobie, i64 0, i32 2 + store i32 20, i32* %4, align 4 + ret i32 undef + +; Check that the memcpy is removed. +; CHECK-LABEL: @test1( +; CHECK-NOT: call void @llvm.memcpy +} + +define void @test2(i8* sret noalias nocapture %out, i8* %in) nounwind noinline ssp uwtable { + call void @llvm.lifetime.start(i64 8, i8* %in) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 8, i32 1, i1 false) + ret void + +; Check that the memcpy is removed. +; CHECK-LABEL: @test2( +; CHECK-NOT: call void @llvm.memcpy +} + +define void @test3(i8* sret noalias nocapture %out, i8* %in) nounwind noinline ssp uwtable { + call void @llvm.lifetime.start(i64 4, i8* %in) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 8, i32 1, i1 false) + ret void + +; Check that the memcpy is not removed. +; CHECK-LABEL: @test3( +; CHECK: call void @llvm.memcpy +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind diff --git a/test/Transforms/MemCpyOpt/memcpy.ll b/test/Transforms/MemCpyOpt/memcpy.ll index 2417cd11f7ff..ee04f1951164 100644 --- a/test/Transforms/MemCpyOpt/memcpy.ll +++ b/test/Transforms/MemCpyOpt/memcpy.ll @@ -29,7 +29,7 @@ entry: ; CHECK: ret void } -declare void @ccoshl(%0* sret , x86_fp80, x86_fp80) nounwind +declare void @ccoshl(%0* nocapture sret, x86_fp80, x86_fp80) nounwind ; The intermediate alloca and one of the memcpy's should be eliminated, the @@ -78,6 +78,7 @@ define void @test4(i8 *%P) { declare void @test4a(i8* align 1 byval) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind +declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i32, i1) nounwind %struct.S = type { i128, [4 x i8]} @@ -152,6 +153,22 @@ declare noalias i8* @malloc(i32) ; rdar://11341081 %struct.big = type { [50 x i32] } +define void @test9_addrspacecast() nounwind ssp uwtable { +entry: +; CHECK-LABEL: @test9_addrspacecast( +; CHECK: f1 +; CHECK-NOT: memcpy +; CHECK: f2 + %b = alloca %struct.big, align 4 + %tmp = alloca %struct.big, align 4 + call void @f1(%struct.big* sret %tmp) + %0 = addrspacecast %struct.big* %b to i8 addrspace(1)* + %1 = addrspacecast %struct.big* %tmp to i8 addrspace(1)* + call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* %0, i8 addrspace(1)* %1, i64 200, i32 4, i1 false) + call void @f2(%struct.big* %b) + ret void +} + define void @test9() nounwind ssp uwtable { entry: ; CHECK: test9 @@ -185,7 +202,7 @@ define void @test10(%opaque* noalias nocapture sret %x, i32 %y) { ret void } -declare void @f1(%struct.big* sret) +declare void @f1(%struct.big* nocapture sret) declare void @f2(%struct.big*) ; CHECK: attributes [[NUW]] = { nounwind } diff --git a/test/Transforms/MemCpyOpt/sret.ll b/test/Transforms/MemCpyOpt/sret.ll index 1bbb5fe8651b..bfe5e0fbb993 100644 --- a/test/Transforms/MemCpyOpt/sret.ll +++ b/test/Transforms/MemCpyOpt/sret.ll @@ -25,6 +25,6 @@ entry: ret void } -declare void @ccoshl(%0* noalias sret, %0* byval) nounwind +declare void @ccoshl(%0* noalias nocapture sret, %0* byval) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind diff --git a/test/Transforms/MergeFunc/call-and-invoke-with-ranges.ll b/test/Transforms/MergeFunc/call-and-invoke-with-ranges.ll new file mode 100644 index 000000000000..9878b471500e --- /dev/null +++ b/test/Transforms/MergeFunc/call-and-invoke-with-ranges.ll @@ -0,0 +1,91 @@ +; RUN: opt -mergefunc -S < %s | FileCheck %s + +define i8 @call_with_range() { + bitcast i8 0 to i8 ; dummy to make the function large enough + %out = call i8 @dummy(), !range !0 + ret i8 %out +} + +define i8 @call_no_range() { +; CHECK-LABEL: @call_no_range +; CHECK-NEXT: bitcast i8 0 to i8 +; CHECK-NEXT: %out = call i8 @dummy() +; CHECK-NEXT: ret i8 %out + bitcast i8 0 to i8 + %out = call i8 @dummy() + ret i8 %out +} + +define i8 @call_different_range() { +; CHECK-LABEL: @call_different_range +; CHECK-NEXT: bitcast i8 0 to i8 +; CHECK-NEXT: %out = call i8 @dummy(), !range !1 +; CHECK-NEXT: ret i8 %out + bitcast i8 0 to i8 + %out = call i8 @dummy(), !range !1 + ret i8 %out +} + +define i8 @invoke_with_range() { + %out = invoke i8 @dummy() to label %next unwind label %lpad, !range !0 + +next: + ret i8 %out + +lpad: + %pad = landingpad { i8*, i32 } personality i8* undef cleanup + resume { i8*, i32 } zeroinitializer +} + +define i8 @invoke_no_range() { +; CHECK-LABEL: @invoke_no_range() +; CHECK-NEXT: invoke i8 @dummy + %out = invoke i8 @dummy() to label %next unwind label %lpad + +next: + ret i8 %out + +lpad: + %pad = landingpad { i8*, i32 } personality i8* undef cleanup + resume { i8*, i32 } zeroinitializer +} + +define i8 @invoke_different_range() { +; CHECK-LABEL: @invoke_different_range() +; CHECK-NEXT: invoke i8 @dummy + %out = invoke i8 @dummy() to label %next unwind label %lpad, !range !1 + +next: + ret i8 %out + +lpad: + %pad = landingpad { i8*, i32 } personality i8* undef cleanup + resume { i8*, i32 } zeroinitializer +} + +define i8 @call_same_range() { +; CHECK-LABEL: @call_same_range +; CHECK: tail call i8 @call_with_range + bitcast i8 0 to i8 + %out = call i8 @dummy(), !range !0 + ret i8 %out +} + +define i8 @invoke_same_range() { +; CHECK-LABEL: @invoke_same_range() +; CHECK: tail call i8 @invoke_with_range() + %out = invoke i8 @dummy() to label %next unwind label %lpad, !range !0 + +next: + ret i8 %out + +lpad: + %pad = landingpad { i8*, i32 } personality i8* undef cleanup + resume { i8*, i32 } zeroinitializer +} + +declare i8 @dummy(); +declare i32 @__gxx_personality_v0(...) + +!0 = metadata !{i8 0, i8 2} +!1 = metadata !{i8 5, i8 7}
\ No newline at end of file diff --git a/test/Transforms/MergeFunc/crash.ll b/test/Transforms/MergeFunc/crash.ll index 0897ba289337..3475e28a6565 100644 --- a/test/Transforms/MergeFunc/crash.ll +++ b/test/Transforms/MergeFunc/crash.ll @@ -8,9 +8,9 @@ target triple = "i386-pc-linux-gnu" %.qux.2585 = type { i32, i32, i8* } @g2 = external unnamed_addr constant [9 x i8], align 1 -@g3 = internal hidden unnamed_addr constant [1 x i8*] [i8* bitcast (i8* (%.qux.2585*)* @func35 to i8*)] +@g3 = internal unnamed_addr constant [1 x i8*] [i8* bitcast (i8* (%.qux.2585*)* @func35 to i8*)] -define internal hidden i32 @func1(i32* %ptr, { i32, i32 }* nocapture %method) align 2 { +define internal i32 @func1(i32* %ptr, { i32, i32 }* nocapture %method) align 2 { br label %1 ; <label>:1 @@ -20,26 +20,26 @@ define internal hidden i32 @func1(i32* %ptr, { i32, i32 }* nocapture %method) al ret i32 undef } -define internal hidden i32 @func10(%.qux.2496* nocapture %this) align 2 { +define internal i32 @func10(%.qux.2496* nocapture %this) align 2 { %1 = getelementptr inbounds %.qux.2496* %this, i32 0, i32 1, i32 1 %2 = load i32* %1, align 4 ret i32 %2 } -define internal hidden i8* @func29(i32* nocapture %this) align 2 { +define internal i8* @func29(i32* nocapture %this) align 2 { ret i8* getelementptr inbounds ([9 x i8]* @g2, i32 0, i32 0) } -define internal hidden i32* @func33(%.qux.2585* nocapture %this) align 2 { +define internal i32* @func33(%.qux.2585* nocapture %this) align 2 { ret i32* undef } -define internal hidden i32* @func34(%.qux.2585* nocapture %this) align 2 { +define internal i32* @func34(%.qux.2585* nocapture %this) align 2 { %1 = getelementptr inbounds %.qux.2585* %this, i32 0 ret i32* undef } -define internal hidden i8* @func35(%.qux.2585* nocapture %this) align 2 { +define internal i8* @func35(%.qux.2585* nocapture %this) align 2 { %1 = getelementptr inbounds %.qux.2585* %this, i32 0, i32 2 %2 = load i8** %1, align 4 ret i8* %2 diff --git a/test/Transforms/MergeFunc/functions.ll b/test/Transforms/MergeFunc/functions.ll new file mode 100644 index 000000000000..006fdf523670 --- /dev/null +++ b/test/Transforms/MergeFunc/functions.ll @@ -0,0 +1,27 @@ +; RUN: opt -S -mergefunc < %s | FileCheck %s + +; Be sure we don't merge cross-referenced functions of same type. + +; CHECK-LABEL: @left +; CHECK-LABEL: entry-block +; CHECK-LABEL: call void @right(i64 %p) +define void @left(i64 %p) { +entry-block: + call void @right(i64 %p) + call void @right(i64 %p) + call void @right(i64 %p) + call void @right(i64 %p) + ret void +} + +; CHECK-LABEL: @right +; CHECK-LABEL: entry-block +; CHECK-LABEL: call void @left(i64 %p) +define void @right(i64 %p) { +entry-block: + call void @left(i64 %p) + call void @left(i64 %p) + call void @left(i64 %p) + call void @left(i64 %p) + ret void +} diff --git a/test/Transforms/MergeFunc/inttoptr-address-space.ll b/test/Transforms/MergeFunc/inttoptr-address-space.ll index 0d834bc3b437..2e5e2fcc4865 100644 --- a/test/Transforms/MergeFunc/inttoptr-address-space.ll +++ b/test/Transforms/MergeFunc/inttoptr-address-space.ll @@ -6,10 +6,10 @@ target datalayout = "e-p:32:32:32-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32- %.qux.2585 = type { i32, i32, i8* } @g2 = external addrspace(1) constant [9 x i8], align 1 -@g3 = internal hidden unnamed_addr constant [1 x i8*] [i8* bitcast (i8* (%.qux.2585 addrspace(1)*)* @func35 to i8*)] +@g3 = internal unnamed_addr constant [1 x i8*] [i8* bitcast (i8* (%.qux.2585 addrspace(1)*)* @func35 to i8*)] -define internal hidden i32 @func10(%.qux.2496 addrspace(1)* nocapture %this) align 2 { +define internal i32 @func10(%.qux.2496 addrspace(1)* nocapture %this) align 2 { bb: %tmp = getelementptr inbounds %.qux.2496 addrspace(1)* %this, i32 0, i32 1, i32 1 %tmp1 = load i32 addrspace(1)* %tmp, align 4 @@ -17,7 +17,7 @@ bb: } ; Check for pointer bitwidth equal assertion failure -define internal hidden i8* @func35(%.qux.2585 addrspace(1)* nocapture %this) align 2 { +define internal i8* @func35(%.qux.2585 addrspace(1)* nocapture %this) align 2 { bb: ; CHECK-LABEL: @func35( ; CHECK: %[[V2:.+]] = bitcast %.qux.2585 addrspace(1)* %{{.*}} to %.qux.2496 addrspace(1)* diff --git a/test/Transforms/MergeFunc/inttoptr.ll b/test/Transforms/MergeFunc/inttoptr.ll index 6a69e3fcfd86..86c18a0c122b 100644 --- a/test/Transforms/MergeFunc/inttoptr.ll +++ b/test/Transforms/MergeFunc/inttoptr.ll @@ -8,9 +8,9 @@ target triple = "i386-pc-linux-gnu" %.qux.2585 = type { i32, i32, i8* } @g2 = external unnamed_addr constant [9 x i8], align 1 -@g3 = internal hidden unnamed_addr constant [1 x i8*] [i8* bitcast (i8* (%.qux.2585*)* @func35 to i8*)] +@g3 = internal unnamed_addr constant [1 x i8*] [i8* bitcast (i8* (%.qux.2585*)* @func35 to i8*)] -define internal hidden i32 @func1(i32* %ptr, { i32, i32 }* nocapture %method) align 2 { +define internal i32 @func1(i32* %ptr, { i32, i32 }* nocapture %method) align 2 { bb: br label %bb1 @@ -21,30 +21,30 @@ bb2: ; preds = %bb1 ret i32 undef } -define internal hidden i32 @func10(%.qux.2496* nocapture %this) align 2 { +define internal i32 @func10(%.qux.2496* nocapture %this) align 2 { bb: %tmp = getelementptr inbounds %.qux.2496* %this, i32 0, i32 1, i32 1 %tmp1 = load i32* %tmp, align 4 ret i32 %tmp1 } -define internal hidden i8* @func29(i32* nocapture %this) align 2 { +define internal i8* @func29(i32* nocapture %this) align 2 { bb: ret i8* getelementptr inbounds ([9 x i8]* @g2, i32 0, i32 0) } -define internal hidden i32* @func33(%.qux.2585* nocapture %this) align 2 { +define internal i32* @func33(%.qux.2585* nocapture %this) align 2 { bb: ret i32* undef } -define internal hidden i32* @func34(%.qux.2585* nocapture %this) align 2 { +define internal i32* @func34(%.qux.2585* nocapture %this) align 2 { bb: %tmp = getelementptr inbounds %.qux.2585* %this, i32 0 ret i32* undef } -define internal hidden i8* @func35(%.qux.2585* nocapture %this) align 2 { +define internal i8* @func35(%.qux.2585* nocapture %this) align 2 { bb: ; CHECK-LABEL: @func35( ; CHECK: %[[V2:.+]] = bitcast %.qux.2585* %{{.*}} to %.qux.2496* diff --git a/test/Transforms/MergeFunc/mergefunc-struct-return.ll b/test/Transforms/MergeFunc/mergefunc-struct-return.ll new file mode 100644 index 000000000000..d2cbe43da0c4 --- /dev/null +++ b/test/Transforms/MergeFunc/mergefunc-struct-return.ll @@ -0,0 +1,40 @@ +; RUN: opt -mergefunc -S < %s | FileCheck %s + +; This test makes sure that the mergefunc pass, uses extract and insert value +; to convert the struct result type; as struct types cannot be bitcast. + +target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32" + +%kv1 = type { i32*, i32* } +%kv2 = type { i8*, i8* } + +declare void @noop() + +define %kv1 @fn1() { +; CHECK-LABEL: @fn1( + %tmp = alloca %kv1 + %v1 = getelementptr %kv1* %tmp, i32 0, i32 0 + store i32* null, i32** %v1 + %v2 = getelementptr %kv1* %tmp, i32 0, i32 0 + store i32* null, i32** %v2 + call void @noop() + %v3 = load %kv1* %tmp + ret %kv1 %v3 +} + +define %kv2 @fn2() { +; CHECK-LABEL: @fn2( +; CHECK: %1 = tail call %kv1 @fn1() +; CHECK: %2 = extractvalue %kv1 %1, 0 +; CHECK: %3 = bitcast i32* %2 to i8* +; CHECK: %4 = insertvalue %kv2 undef, i8* %3, 0 + %tmp = alloca %kv2 + %v1 = getelementptr %kv2* %tmp, i32 0, i32 0 + store i8* null, i8** %v1 + %v2 = getelementptr %kv2* %tmp, i32 0, i32 0 + store i8* null, i8** %v2 + call void @noop() + + %v3 = load %kv2* %tmp + ret %kv2 %v3 +} diff --git a/test/Transforms/MergeFunc/ranges.ll b/test/Transforms/MergeFunc/ranges.ll new file mode 100644 index 000000000000..e25ff1d3acb1 --- /dev/null +++ b/test/Transforms/MergeFunc/ranges.ll @@ -0,0 +1,43 @@ +; RUN: opt -mergefunc -S < %s | FileCheck %s +define i1 @cmp_with_range(i8*, i8*) { + %v1 = load i8* %0, !range !0 + %v2 = load i8* %1, !range !0 + %out = icmp eq i8 %v1, %v2 + ret i1 %out +} + +define i1 @cmp_no_range(i8*, i8*) { +; CHECK-LABEL: @cmp_no_range +; CHECK-NEXT %v1 = load i8* %0 +; CHECK-NEXT %v2 = load i8* %1 +; CHECK-NEXT %out = icmp eq i8 %v1, %v2 +; CHECK-NEXT ret i1 %out + %v1 = load i8* %0 + %v2 = load i8* %1 + %out = icmp eq i8 %v1, %v2 + ret i1 %out +} + +define i1 @cmp_different_range(i8*, i8*) { +; CHECK-LABEL: @cmp_different_range +; CHECK-NEXT: %v1 = load i8* %0, !range !1 +; CHECK-NEXT: %v2 = load i8* %1, !range !1 +; CHECK-NEXT: %out = icmp eq i8 %v1, %v2 +; CHECK-NEXT: ret i1 %out + %v1 = load i8* %0, !range !1 + %v2 = load i8* %1, !range !1 + %out = icmp eq i8 %v1, %v2 + ret i1 %out +} + +define i1 @cmp_with_same_range(i8*, i8*) { +; CHECK-LABEL: @cmp_with_same_range +; CHECK: tail call i1 @cmp_with_range + %v1 = load i8* %0, !range !0 + %v2 = load i8* %1, !range !0 + %out = icmp eq i8 %v1, %v2 + ret i1 %out +} + +!0 = metadata !{i8 0, i8 2} +!1 = metadata !{i8 5, i8 7} diff --git a/test/Transforms/MetaRenamer/metarenamer.ll b/test/Transforms/MetaRenamer/metarenamer.ll index 4020e1045081..6297af62ff0c 100644 --- a/test/Transforms/MetaRenamer/metarenamer.ll +++ b/test/Transforms/MetaRenamer/metarenamer.ll @@ -14,7 +14,9 @@ target triple = "x86_64-pc-linux-gnu" @func_7_xxx = alias weak i32 (...)* @aliased_func_7_xxx -declare i32 @aliased_func_7_xxx(...) +define i32 @aliased_func_7_xxx(...) { + ret i32 0 +} define i32 @func_3_xxx() nounwind uwtable ssp { ret i32 3 diff --git a/test/Transforms/ObjCARC/allocas.ll b/test/Transforms/ObjCARC/allocas.ll index 50656739ae71..7347a8fd4447 100644 --- a/test/Transforms/ObjCARC/allocas.ll +++ b/test/Transforms/ObjCARC/allocas.ll @@ -28,7 +28,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) declare i8* @objc_msgSend(i8*, i8*, ...) -; In the presense of allocas, unconditionally remove retain/release pairs only +; In the presence of allocas, unconditionally remove retain/release pairs only ; if they are known safe in both directions. This prevents matching up an inner ; retain with the boundary guarding release in the following situation: ; @@ -336,7 +336,7 @@ bb3: ret void } -; Make sure in the presense of allocas, if we find a cfghazard we do not perform +; Make sure in the presence of allocas, if we find a cfghazard we do not perform ; code motion even if we are known safe. These two concepts are separate and ; should be treated as such. ; diff --git a/test/Transforms/ObjCARC/contract-end-of-use-list.ll b/test/Transforms/ObjCARC/contract-end-of-use-list.ll new file mode 100644 index 000000000000..a38cd8a1da17 --- /dev/null +++ b/test/Transforms/ObjCARC/contract-end-of-use-list.ll @@ -0,0 +1,30 @@ +; RUN: opt -S < %s -objc-arc-expand -objc-arc-contract | FileCheck %s +; Don't crash. Reproducer for a use_iterator bug from r203364. +; rdar://problem/16333235 +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-darwin13.2.0" + +%struct = type { i8*, i8* } + +; CHECK-LABEL: @foo() { +define internal i8* @foo() { +entry: + %call = call i8* @bar() +; CHECK: %retained1 = call i8* @objc_retainAutoreleasedReturnValue(i8* %call) + %retained1 = call i8* @objc_retain(i8* %call) + %isnull = icmp eq i8* %retained1, null + br i1 %isnull, label %cleanup, label %if.end + +if.end: +; CHECK: %retained2 = call i8* @objc_retain(i8* %retained1) + %retained2 = call i8* @objc_retain(i8* %retained1) + br label %cleanup + +cleanup: + %retval = phi i8* [ %retained2, %if.end ], [ null, %entry ] + ret i8* %retval +} + +declare i8* @bar() + +declare extern_weak i8* @objc_retain(i8*) diff --git a/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll b/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll index 072861720e63..79e300cb6b43 100644 --- a/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll +++ b/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll @@ -24,11 +24,11 @@ target triple = "x86_64-apple-macosx10.9.0" @"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"new\00", section "__TEXT,__objc_methname,cstring_literals", align 1 @"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip" @__CFConstantStringClassReference = external global [0 x i32] -@.str = linker_private unnamed_addr constant [11 x i8] c"Failed: %@\00", align 1 +@.str = private unnamed_addr constant [11 x i8] c"Failed: %@\00", align 1 @_unnamed_cfstring_ = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i64 10 }, section "__DATA,__cfstring" @"OBJC_CLASS_$_NSException" = external global %struct._class_t @"\01L_OBJC_CLASSLIST_REFERENCES_$_1" = internal global %struct._class_t* @"OBJC_CLASS_$_NSException", section "__DATA, __objc_classrefs, regular, no_dead_strip", align 8 -@.str2 = linker_private unnamed_addr constant [4 x i8] c"Foo\00", align 1 +@.str2 = private unnamed_addr constant [4 x i8] c"Foo\00", align 1 @_unnamed_cfstring_3 = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([4 x i8]* @.str2, i32 0, i32 0), i64 3 }, section "__DATA,__cfstring" @"\01L_OBJC_METH_VAR_NAME_4" = internal global [14 x i8] c"raise:format:\00", section "__TEXT,__objc_methname,cstring_literals", align 1 @"\01L_OBJC_SELECTOR_REFERENCES_5" = internal global i8* getelementptr inbounds ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_4", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip" diff --git a/test/Transforms/Reassociate/2002-05-15-AgressiveSubMove.ll b/test/Transforms/Reassociate/2002-05-15-AgressiveSubMove.ll index 5780990c7618..24300352a62c 100644 --- a/test/Transforms/Reassociate/2002-05-15-AgressiveSubMove.ll +++ b/test/Transforms/Reassociate/2002-05-15-AgressiveSubMove.ll @@ -1,9 +1,10 @@ -; RUN: opt < %s -reassociate -instcombine -constprop -dce -S | not grep add +; RUN: opt < %s -reassociate -S | FileCheck %s -define i32 @test(i32 %A) { - %X = add i32 %A, 1 ; <i32> [#uses=1] - %Y = add i32 %A, 1 ; <i32> [#uses=1] - %r = sub i32 %X, %Y ; <i32> [#uses=1] - ret i32 %r +define i32 @test1(i32 %A) { +; CHECK-LABEL: test1 +; CHECK: ret i32 0 + %X = add i32 %A, 1 + %Y = add i32 %A, 1 + %r = sub i32 %X, %Y + ret i32 %r } - diff --git a/test/Transforms/Reassociate/2002-05-15-MissedTree.ll b/test/Transforms/Reassociate/2002-05-15-MissedTree.ll index e8bccbde28e2..5f3c9209aeda 100644 --- a/test/Transforms/Reassociate/2002-05-15-MissedTree.ll +++ b/test/Transforms/Reassociate/2002-05-15-MissedTree.ll @@ -1,9 +1,11 @@ -; RUN: opt < %s -reassociate -instcombine -constprop -die -S | not grep 5 +; RUN: opt < %s -reassociate -instcombine -S | FileCheck %s -define i32 @test(i32 %A, i32 %B) { - %W = add i32 %B, -5 ; <i32> [#uses=1] - %Y = add i32 %A, 5 ; <i32> [#uses=1] - %Z = add i32 %W, %Y ; <i32> [#uses=1] +define i32 @test1(i32 %A, i32 %B) { +; CHECK-LABEL: test1 +; CHECK: %Z = add i32 %B, %A +; CHECK: ret i32 %Z + %W = add i32 %B, -5 + %Y = add i32 %A, 5 + %Z = add i32 %W, %Y ret i32 %Z } - diff --git a/test/Transforms/Reassociate/2002-05-15-SubReassociate.ll b/test/Transforms/Reassociate/2002-05-15-SubReassociate.ll index c18af5e07efd..29c178ffec3e 100644 --- a/test/Transforms/Reassociate/2002-05-15-SubReassociate.ll +++ b/test/Transforms/Reassociate/2002-05-15-SubReassociate.ll @@ -1,12 +1,30 @@ +; RUN: opt < %s -reassociate -constprop -instcombine -dce -S | FileCheck %s + ; With sub reassociation, constant folding can eliminate all of the constants. -; -; RUN: opt < %s -reassociate -constprop -instcombine -dce -S | not grep add +define i32 @test1(i32 %A, i32 %B) { +; CHECK-LABEL: test1 +; CHECK-NEXT: %Z = sub i32 %A, %B +; CHECK-NEXT: ret i32 %Z -define i32 @test(i32 %A, i32 %B) { - %W = add i32 5, %B ; <i32> [#uses=1] - %X = add i32 -7, %A ; <i32> [#uses=1] - %Y = sub i32 %X, %W ; <i32> [#uses=1] - %Z = add i32 %Y, 12 ; <i32> [#uses=1] - ret i32 %Z + %W = add i32 5, %B + %X = add i32 -7, %A + %Y = sub i32 %X, %W + %Z = add i32 %Y, 12 + ret i32 %Z } + +; With sub reassociation, constant folding can eliminate the two 12 constants. +define i32 @test2(i32 %A, i32 %B, i32 %C, i32 %D) { +; CHECK-LABEL: test2 +; CHECK-NEXT: %sum = add i32 %B, %A +; CHECK-NEXT: %sum1 = add i32 %sum, %C +; CHECK-NEXT: %Q = sub i32 %D, %sum1 +; CHECK-NEXT: ret i32 %Q + %M = add i32 %A, 12 + %N = add i32 %M, %B + %O = add i32 %N, %C + %P = sub i32 %D, %O + %Q = add i32 %P, 12 + ret i32 %Q +} diff --git a/test/Transforms/Reassociate/2002-05-15-SubReassociate2.ll b/test/Transforms/Reassociate/2002-05-15-SubReassociate2.ll deleted file mode 100644 index 5848821e10fd..000000000000 --- a/test/Transforms/Reassociate/2002-05-15-SubReassociate2.ll +++ /dev/null @@ -1,13 +0,0 @@ -; With sub reassociation, constant folding can eliminate the two 12 constants. -; -; RUN: opt < %s -reassociate -constprop -dce -S | not grep 12 - -define i32 @test(i32 %A, i32 %B, i32 %C, i32 %D) { - %M = add i32 %A, 12 ; <i32> [#uses=1] - %N = add i32 %M, %B ; <i32> [#uses=1] - %O = add i32 %N, %C ; <i32> [#uses=1] - %P = sub i32 %D, %O ; <i32> [#uses=1] - %Q = add i32 %P, 12 ; <i32> [#uses=1] - ret i32 %Q -} - diff --git a/test/Transforms/Reassociate/2005-09-01-ArrayOutOfBounds.ll b/test/Transforms/Reassociate/2005-09-01-ArrayOutOfBounds.ll index f66148bb4abc..f6cef35b1779 100644 --- a/test/Transforms/Reassociate/2005-09-01-ArrayOutOfBounds.ll +++ b/test/Transforms/Reassociate/2005-09-01-ArrayOutOfBounds.ll @@ -1,23 +1,24 @@ -; RUN: opt < %s -reassociate -instcombine -S |\ -; RUN: grep "ret i32 0" +; RUN: opt < %s -reassociate -instcombine -S | FileCheck %s -define i32 @f(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) { - %tmp.2 = add i32 %a4, %a3 ; <i32> [#uses=1] - %tmp.4 = add i32 %tmp.2, %a2 ; <i32> [#uses=1] - %tmp.6 = add i32 %tmp.4, %a1 ; <i32> [#uses=1] - %tmp.8 = add i32 %tmp.6, %a0 ; <i32> [#uses=1] - %tmp.11 = add i32 %a3, %a2 ; <i32> [#uses=1] - %tmp.13 = add i32 %tmp.11, %a1 ; <i32> [#uses=1] - %tmp.15 = add i32 %tmp.13, %a0 ; <i32> [#uses=1] - %tmp.18 = add i32 %a2, %a1 ; <i32> [#uses=1] - %tmp.20 = add i32 %tmp.18, %a0 ; <i32> [#uses=1] - %tmp.23 = add i32 %a1, %a0 ; <i32> [#uses=1] - %tmp.26 = sub i32 %tmp.8, %tmp.15 ; <i32> [#uses=1] - %tmp.28 = add i32 %tmp.26, %tmp.20 ; <i32> [#uses=1] - %tmp.30 = sub i32 %tmp.28, %tmp.23 ; <i32> [#uses=1] - %tmp.32 = sub i32 %tmp.30, %a4 ; <i32> [#uses=1] - %tmp.34 = sub i32 %tmp.32, %a2 ; <i32> [#uses=2] - %T = mul i32 %tmp.34, %tmp.34 ; <i32> [#uses=1] - ret i32 %T -} +define i32 @f1(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) { +; CHECK-LABEL: f1 +; CHECK-NEXT: ret i32 0 + %tmp.2 = add i32 %a4, %a3 + %tmp.4 = add i32 %tmp.2, %a2 + %tmp.6 = add i32 %tmp.4, %a1 + %tmp.8 = add i32 %tmp.6, %a0 + %tmp.11 = add i32 %a3, %a2 + %tmp.13 = add i32 %tmp.11, %a1 + %tmp.15 = add i32 %tmp.13, %a0 + %tmp.18 = add i32 %a2, %a1 + %tmp.20 = add i32 %tmp.18, %a0 + %tmp.23 = add i32 %a1, %a0 + %tmp.26 = sub i32 %tmp.8, %tmp.15 + %tmp.28 = add i32 %tmp.26, %tmp.20 + %tmp.30 = sub i32 %tmp.28, %tmp.23 + %tmp.32 = sub i32 %tmp.30, %a4 + %tmp.34 = sub i32 %tmp.32, %a2 + %T = mul i32 %tmp.34, %tmp.34 + ret i32 %T +} diff --git a/test/Transforms/Reassociate/2006-04-27-ReassociateVector.ll b/test/Transforms/Reassociate/2006-04-27-ReassociateVector.ll index 384cbc90a744..f78395540026 100644 --- a/test/Transforms/Reassociate/2006-04-27-ReassociateVector.ll +++ b/test/Transforms/Reassociate/2006-04-27-ReassociateVector.ll @@ -1,8 +1,12 @@ -; RUN: opt < %s -reassociate -disable-output +; RUN: opt < %s -reassociate -S | FileCheck %s -define void @foo() { - %tmp162 = fsub <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>> [#uses=1] - %tmp164 = fmul <4 x float> zeroinitializer, %tmp162 ; <<4 x float>> [#uses=0] - ret void -} +define <4 x float> @test1() { +; CHECK-LABEL: test1 +; CHECK-NEXT: %tmp1 = fsub <4 x float> zeroinitializer, zeroinitializer +; CHECK-NEXT: %tmp2 = fmul <4 x float> zeroinitializer, %tmp1 +; CHECK-NEXT: ret <4 x float> %tmp2 + %tmp1 = fsub <4 x float> zeroinitializer, zeroinitializer + %tmp2 = fmul <4 x float> zeroinitializer, %tmp1 + ret <4 x float> %tmp2 +} diff --git a/test/Transforms/Reassociate/basictest.ll b/test/Transforms/Reassociate/basictest.ll index fda0ca6be1aa..d70bfcbb72c6 100644 --- a/test/Transforms/Reassociate/basictest.ll +++ b/test/Transforms/Reassociate/basictest.ll @@ -1,46 +1,47 @@ -; With reassociation, constant folding can eliminate the 12 and -12 constants. -; -; RUN: opt < %s -reassociate -gvn -instcombine -S | FileCheck %s +; RUN: opt < %s -reassociate -gvn -instcombine -S | FileCheck %s define i32 @test1(i32 %arg) { - %tmp1 = sub i32 -12, %arg - %tmp2 = add i32 %tmp1, 12 - ret i32 %tmp2 -; CHECK-LABEL: @test1( + %tmp1 = sub i32 -12, %arg + %tmp2 = add i32 %tmp1, 12 + ret i32 %tmp2 + +; CHECK-LABEL: @test1 ; CHECK-NEXT: sub i32 0, %arg ; CHECK-NEXT: ret i32 } define i32 @test2(i32 %reg109, i32 %reg1111) { - %reg115 = add i32 %reg109, -30 ; <i32> [#uses=1] - %reg116 = add i32 %reg115, %reg1111 ; <i32> [#uses=1] - %reg117 = add i32 %reg116, 30 ; <i32> [#uses=1] - ret i32 %reg117 -; CHECK-LABEL: @test2( -; CHECK-NEXT: add i32 %reg1111, %reg109 -; CHECK-NEXT: ret i32 + %reg115 = add i32 %reg109, -30 + %reg116 = add i32 %reg115, %reg1111 + %reg117 = add i32 %reg116, 30 + ret i32 %reg117 + +; CHECK-LABEL: @test2 +; CHECK-NEXT: %reg117 = add i32 %reg1111, %reg109 +; CHECK-NEXT: ret i32 %reg117 } -@e = external global i32 ; <i32*> [#uses=3] -@a = external global i32 ; <i32*> [#uses=3] -@b = external global i32 ; <i32*> [#uses=3] -@c = external global i32 ; <i32*> [#uses=3] -@f = external global i32 ; <i32*> [#uses=3] +@e = external global i32 +@a = external global i32 +@b = external global i32 +@c = external global i32 +@f = external global i32 define void @test3() { - %A = load i32* @a ; <i32> [#uses=2] - %B = load i32* @b ; <i32> [#uses=2] - %C = load i32* @c ; <i32> [#uses=2] - %t1 = add i32 %A, %B ; <i32> [#uses=1] - %t2 = add i32 %t1, %C ; <i32> [#uses=1] - %t3 = add i32 %C, %A ; <i32> [#uses=1] - %t4 = add i32 %t3, %B ; <i32> [#uses=1] - ; e = (a+b)+c; - store i32 %t2, i32* @e - ; f = (a+c)+b - store i32 %t4, i32* @f - ret void -; CHECK-LABEL: @test3( + %A = load i32* @a + %B = load i32* @b + %C = load i32* @c + %t1 = add i32 %A, %B + %t2 = add i32 %t1, %C + %t3 = add i32 %C, %A + %t4 = add i32 %t3, %B + ; e = (a+b)+c; + store i32 %t2, i32* @e + ; f = (a+c)+b + store i32 %t4, i32* @f + ret void + +; CHECK-LABEL: @test3 ; CHECK: add i32 ; CHECK: add i32 ; CHECK-NOT: add i32 @@ -48,19 +49,20 @@ define void @test3() { } define void @test4() { - %A = load i32* @a ; <i32> [#uses=2] - %B = load i32* @b ; <i32> [#uses=2] - %C = load i32* @c ; <i32> [#uses=2] - %t1 = add i32 %A, %B ; <i32> [#uses=1] - %t2 = add i32 %t1, %C ; <i32> [#uses=1] - %t3 = add i32 %C, %A ; <i32> [#uses=1] - %t4 = add i32 %t3, %B ; <i32> [#uses=1] - ; e = c+(a+b) - store i32 %t2, i32* @e - ; f = (c+a)+b - store i32 %t4, i32* @f - ret void -; CHECK-LABEL: @test4( + %A = load i32* @a + %B = load i32* @b + %C = load i32* @c + %t1 = add i32 %A, %B + %t2 = add i32 %t1, %C + %t3 = add i32 %C, %A + %t4 = add i32 %t3, %B + ; e = c+(a+b) + store i32 %t2, i32* @e + ; f = (c+a)+b + store i32 %t4, i32* @f + ret void + +; CHECK-LABEL: @test4 ; CHECK: add i32 ; CHECK: add i32 ; CHECK-NOT: add i32 @@ -68,19 +70,20 @@ define void @test4() { } define void @test5() { - %A = load i32* @a ; <i32> [#uses=2] - %B = load i32* @b ; <i32> [#uses=2] - %C = load i32* @c ; <i32> [#uses=2] - %t1 = add i32 %B, %A ; <i32> [#uses=1] - %t2 = add i32 %t1, %C ; <i32> [#uses=1] - %t3 = add i32 %C, %A ; <i32> [#uses=1] - %t4 = add i32 %t3, %B ; <i32> [#uses=1] - ; e = c+(b+a) - store i32 %t2, i32* @e - ; f = (c+a)+b - store i32 %t4, i32* @f - ret void -; CHECK-LABEL: @test5( + %A = load i32* @a + %B = load i32* @b + %C = load i32* @c + %t1 = add i32 %B, %A + %t2 = add i32 %t1, %C + %t3 = add i32 %C, %A + %t4 = add i32 %t3, %B + ; e = c+(b+a) + store i32 %t2, i32* @e + ; f = (c+a)+b + store i32 %t4, i32* @f + ret void + +; CHECK-LABEL: @test5 ; CHECK: add i32 ; CHECK: add i32 ; CHECK-NOT: add i32 @@ -88,60 +91,61 @@ define void @test5() { } define i32 @test6() { - %tmp.0 = load i32* @a - %tmp.1 = load i32* @b - ; (a+b) - %tmp.2 = add i32 %tmp.0, %tmp.1 - %tmp.4 = load i32* @c - ; (a+b)+c - %tmp.5 = add i32 %tmp.2, %tmp.4 - ; (a+c) - %tmp.8 = add i32 %tmp.0, %tmp.4 - ; (a+c)+b - %tmp.11 = add i32 %tmp.8, %tmp.1 - ; X ^ X = 0 - %RV = xor i32 %tmp.5, %tmp.11 - ret i32 %RV -; CHECK-LABEL: @test6( + %tmp.0 = load i32* @a + %tmp.1 = load i32* @b + ; (a+b) + %tmp.2 = add i32 %tmp.0, %tmp.1 + %tmp.4 = load i32* @c + ; (a+b)+c + %tmp.5 = add i32 %tmp.2, %tmp.4 + ; (a+c) + %tmp.8 = add i32 %tmp.0, %tmp.4 + ; (a+c)+b + %tmp.11 = add i32 %tmp.8, %tmp.1 + ; X ^ X = 0 + %RV = xor i32 %tmp.5, %tmp.11 + ret i32 %RV + +; CHECK-LABEL: @test6 ; CHECK: ret i32 0 } ; This should be one add and two multiplies. define i32 @test7(i32 %A, i32 %B, i32 %C) { - ; A*A*B + A*C*A - %aa = mul i32 %A, %A - %aab = mul i32 %aa, %B - %ac = mul i32 %A, %C - %aac = mul i32 %ac, %A - %r = add i32 %aab, %aac - ret i32 %r -; CHECK-LABEL: @test7( + ; A*A*B + A*C*A + %aa = mul i32 %A, %A + %aab = mul i32 %aa, %B + %ac = mul i32 %A, %C + %aac = mul i32 %ac, %A + %r = add i32 %aab, %aac + ret i32 %r + +; CHECK-LABEL: @test7 ; CHECK-NEXT: add i32 %C, %B ; CHECK-NEXT: mul i32 ; CHECK-NEXT: mul i32 ; CHECK-NEXT: ret i32 } - define i32 @test8(i32 %X, i32 %Y, i32 %Z) { - %A = sub i32 0, %X - %B = mul i32 %A, %Y - ; (-X)*Y + Z -> Z-X*Y - %C = add i32 %B, %Z - ret i32 %C -; CHECK-LABEL: @test8( + %A = sub i32 0, %X + %B = mul i32 %A, %Y + ; (-X)*Y + Z -> Z-X*Y + %C = add i32 %B, %Z + ret i32 %C + +; CHECK-LABEL: @test8 ; CHECK-NEXT: %A = mul i32 %Y, %X ; CHECK-NEXT: %C = sub i32 %Z, %A ; CHECK-NEXT: ret i32 %C } - ; PR5458 define i32 @test9(i32 %X) { %Y = mul i32 %X, 47 %Z = add i32 %Y, %Y ret i32 %Z -; CHECK-LABEL: @test9( +; CHECK-LABEL: @test9 ; CHECK-NEXT: mul i32 %X, 94 ; CHECK-NEXT: ret i32 } @@ -150,7 +154,7 @@ define i32 @test10(i32 %X) { %Y = add i32 %X ,%X %Z = add i32 %Y, %X ret i32 %Z -; CHECK-LABEL: @test10( +; CHECK-LABEL: @test10 ; CHECK-NEXT: mul i32 %X, 3 ; CHECK-NEXT: ret i32 } @@ -160,7 +164,7 @@ define i32 @test11(i32 %W) { %Y = add i32 %X ,%X %Z = add i32 %Y, %X ret i32 %Z -; CHECK-LABEL: @test11( +; CHECK-LABEL: @test11 ; CHECK-NEXT: mul i32 %W, 381 ; CHECK-NEXT: ret i32 } @@ -169,11 +173,10 @@ define i32 @test12(i32 %X) { %A = sub i32 1, %X %B = sub i32 2, %X %C = sub i32 3, %X - %Y = add i32 %A ,%B %Z = add i32 %Y, %C ret i32 %Z -; CHECK-LABEL: @test12( +; CHECK-LABEL: @test12 ; CHECK-NEXT: mul i32 %X, -3 ; CHECK-NEXT: add i32{{.*}}, 6 ; CHECK-NEXT: ret i32 @@ -185,7 +188,7 @@ define i32 @test13(i32 %X1, i32 %X2, i32 %X3) { %C = mul i32 %X1, %X3 ; X1*X3 %D = add i32 %B, %C ; -X1*X2 + X1*X3 -> X1*(X3-X2) ret i32 %D -; CHECK-LABEL: @test13( +; CHECK-LABEL: @test13 ; CHECK-NEXT: sub i32 %X3, %X2 ; CHECK-NEXT: mul i32 {{.*}}, %X1 ; CHECK-NEXT: ret i32 @@ -197,9 +200,10 @@ define i32 @test14(i32 %X1, i32 %X2) { %C = mul i32 %X2, -47 ; X2*-47 %D = add i32 %B, %C ; X1*47 + X2*-47 -> 47*(X1-X2) ret i32 %D -; CHECK-LABEL: @test14( + +; CHECK-LABEL: @test14 ; CHECK-NEXT: sub i32 %X1, %X2 -; CHECK-NEXT: mul i32 {{.*}}, 47 +; CHECK-NEXT: mul i32 %tmp, 47 ; CHECK-NEXT: ret i32 } @@ -210,7 +214,6 @@ define i32 @test15(i32 %X1, i32 %X2, i32 %X3) { %C = and i1 %A, %B %D = select i1 %C, i32 %X1, i32 0 ret i32 %D -; CHECK-LABEL: @test15( +; CHECK-LABEL: @test15 ; CHECK: and i1 %A, %B } - diff --git a/test/Transforms/Reassociate/fp-commute.ll b/test/Transforms/Reassociate/fp-commute.ll index 025689bb0c10..eac5b5920ac1 100644 --- a/test/Transforms/Reassociate/fp-commute.ll +++ b/test/Transforms/Reassociate/fp-commute.ll @@ -1,18 +1,19 @@ ; RUN: opt -reassociate -S < %s | FileCheck %s -target triple = "armv7-apple-ios" - declare void @use(float) -; CHECK: test -define void @test(float %x, float %y) { -entry: +define void @test1(float %x, float %y) { +; CHECK-LABEL: test1 ; CHECK: fmul float %x, %y ; CHECK: fmul float %x, %y - %0 = fmul float %x, %y - %1 = fmul float %y, %x - %2 = fsub float %0, %1 - call void @use(float %0) - call void @use(float %2) +; CHECK: fsub float %1, %2 +; CHECK: call void @use(float %{{.*}}) +; CHECK: call void @use(float %{{.*}}) + + %1 = fmul float %x, %y + %2 = fmul float %y, %x + %3 = fsub float %1, %2 + call void @use(float %1) + call void @use(float %3) ret void } diff --git a/test/Transforms/Reassociate/inverses.ll b/test/Transforms/Reassociate/inverses.ll index afe076caea92..8500cd867fd3 100644 --- a/test/Transforms/Reassociate/inverses.ll +++ b/test/Transforms/Reassociate/inverses.ll @@ -32,3 +32,15 @@ define i32 @test3(i32 %b, i32 %a) { ; CHECK: %tmp.5 = add i32 %b, 1234 ; CHECK: ret i32 %tmp.5 } + +define i32 @test4(i32 %b, i32 %a) { + %tmp.1 = add i32 %a, 1234 + %tmp.2 = add i32 %b, %tmp.1 + %tmp.4 = xor i32 %a, -1 + ; (b+(a+1234))+~a -> b+1233 + %tmp.5 = add i32 %tmp.2, %tmp.4 + ret i32 %tmp.5 +; CHECK-LABEL: @test4( +; CHECK: %tmp.5 = add i32 %b, 1233 +; CHECK: ret i32 %tmp.5 +} diff --git a/test/Transforms/Reassociate/looptest.ll b/test/Transforms/Reassociate/looptest.ll index 91723bc37b01..aad3b206f69f 100644 --- a/test/Transforms/Reassociate/looptest.ll +++ b/test/Transforms/Reassociate/looptest.ll @@ -18,6 +18,7 @@ declare i32 @printf(i8*, ...) +; FIXME: No longer works. define void @test(i32 %Num, i32* %Array) { bb0: %cond221 = icmp eq i32 0, %Num ; <i1> [#uses=3] diff --git a/test/Transforms/Reassociate/mightymul.ll b/test/Transforms/Reassociate/mightymul.ll index cfbc485ffa03..ae915da8e576 100644 --- a/test/Transforms/Reassociate/mightymul.ll +++ b/test/Transforms/Reassociate/mightymul.ll @@ -1,7 +1,7 @@ -; RUN: opt < %s -reassociate +; RUN: opt < %s -reassociate -disable-output ; PR13021 -define i32 @foo(i32 %x) { +define i32 @test1(i32 %x) { %t0 = mul i32 %x, %x %t1 = mul i32 %t0, %t0 %t2 = mul i32 %t1, %t1 diff --git a/test/Transforms/Reassociate/multistep.ll b/test/Transforms/Reassociate/multistep.ll index d79464753f12..12eaeeea7b7b 100644 --- a/test/Transforms/Reassociate/multistep.ll +++ b/test/Transforms/Reassociate/multistep.ll @@ -28,4 +28,3 @@ define i64 @multistep2(i64 %a, i64 %b, i64 %c, i64 %d) { ; CHECK-NEXT: ret ret i64 %t3 } - diff --git a/test/Transforms/Reassociate/negation.ll b/test/Transforms/Reassociate/negation.ll index 6a3dfd3b8206..12d2c86192bb 100644 --- a/test/Transforms/Reassociate/negation.ll +++ b/test/Transforms/Reassociate/negation.ll @@ -1,21 +1,31 @@ -; RUN: opt < %s -reassociate -instcombine -S | not grep sub +; RUN: opt < %s -reassociate -instcombine -S | FileCheck %s ; Test that we can turn things like X*-(Y*Z) -> X*-1*Y*Z. define i32 @test1(i32 %a, i32 %b, i32 %z) { - %c = sub i32 0, %z ; <i32> [#uses=1] - %d = mul i32 %a, %b ; <i32> [#uses=1] - %e = mul i32 %c, %d ; <i32> [#uses=1] - %f = mul i32 %e, 12345 ; <i32> [#uses=1] - %g = sub i32 0, %f ; <i32> [#uses=1] - ret i32 %g +; CHECK-LABEL: test1 +; CHECK-NEXT: %e = mul i32 %a, 12345 +; CHECK-NEXT: %f = mul i32 %e, %b +; CHECK-NEXT: %g = mul i32 %f, %z +; CHECK-NEXT: ret i32 %g + + %c = sub i32 0, %z + %d = mul i32 %a, %b + %e = mul i32 %c, %d + %f = mul i32 %e, 12345 + %g = sub i32 0, %f + ret i32 %g } define i32 @test2(i32 %a, i32 %b, i32 %z) { - %d = mul i32 %z, 40 ; <i32> [#uses=1] - %c = sub i32 0, %d ; <i32> [#uses=1] - %e = mul i32 %a, %c ; <i32> [#uses=1] - %f = sub i32 0, %e ; <i32> [#uses=1] - ret i32 %f -} +; CHECK-LABEL: test2 +; CHECK-NEXT: %e = mul i32 %a, 40 +; CHECK-NEXT: %f = mul i32 %e, %z +; CHECK-NEXT: ret i32 %f + %d = mul i32 %z, 40 + %c = sub i32 0, %d + %e = mul i32 %a, %c + %f = sub i32 0, %e + ret i32 %f +} diff --git a/test/Transforms/Reassociate/otherops.ll b/test/Transforms/Reassociate/otherops.ll index d68d00818cb8..7718881d8e51 100644 --- a/test/Transforms/Reassociate/otherops.ll +++ b/test/Transforms/Reassociate/otherops.ll @@ -1,28 +1,42 @@ ; Reassociation should apply to Add, Mul, And, Or, & Xor ; -; RUN: opt < %s -reassociate -constprop -instcombine -die -S | not grep 12 +; RUN: opt < %s -reassociate -constprop -instcombine -die -S | FileCheck %s define i32 @test_mul(i32 %arg) { - %tmp1 = mul i32 12, %arg ; <i32> [#uses=1] - %tmp2 = mul i32 %tmp1, 12 ; <i32> [#uses=1] - ret i32 %tmp2 +; CHECK-LABEL: test_mul +; CHECK-NEXT: %tmp2 = mul i32 %arg, 144 +; CHECK-NEXT: ret i32 %tmp2 + + %tmp1 = mul i32 12, %arg + %tmp2 = mul i32 %tmp1, 12 + ret i32 %tmp2 } define i32 @test_and(i32 %arg) { - %tmp1 = and i32 14, %arg ; <i32> [#uses=1] - %tmp2 = and i32 %tmp1, 14 ; <i32> [#uses=1] - ret i32 %tmp2 +; CHECK-LABEL: test_and +; CHECK-NEXT: %tmp2 = and i32 %arg, 14 +; CHECK-NEXT: ret i32 %tmp2 + + %tmp1 = and i32 14, %arg + %tmp2 = and i32 %tmp1, 14 + ret i32 %tmp2 } define i32 @test_or(i32 %arg) { - %tmp1 = or i32 14, %arg ; <i32> [#uses=1] - %tmp2 = or i32 %tmp1, 14 ; <i32> [#uses=1] - ret i32 %tmp2 +; CHECK-LABEL: test_or +; CHECK-NEXT: %tmp2 = or i32 %arg, 14 +; CHECK-NEXT: ret i32 %tmp2 + + %tmp1 = or i32 14, %arg + %tmp2 = or i32 %tmp1, 14 + ret i32 %tmp2 } define i32 @test_xor(i32 %arg) { - %tmp1 = xor i32 12, %arg ; <i32> [#uses=1] - %tmp2 = xor i32 %tmp1, 12 ; <i32> [#uses=1] - ret i32 %tmp2 -} +; CHECK-LABEL: test_xor +; CHECK-NEXT: ret i32 %arg + %tmp1 = xor i32 12, %arg + %tmp2 = xor i32 %tmp1, 12 + ret i32 %tmp2 +} diff --git a/test/Transforms/Reassociate/shift-factor.ll b/test/Transforms/Reassociate/shift-factor.ll index 73af5e5304ee..8fbf1b9d4bc5 100644 --- a/test/Transforms/Reassociate/shift-factor.ll +++ b/test/Transforms/Reassociate/shift-factor.ll @@ -1,12 +1,14 @@ ; There should be exactly one shift and one add left. -; RUN: opt < %s -reassociate -instcombine -S > %t -; RUN: grep shl %t | count 1 -; RUN: grep add %t | count 1 +; RUN: opt < %s -reassociate -instcombine -S | FileCheck %s -define i32 @test(i32 %X, i32 %Y) { - %tmp.2 = shl i32 %X, 1 ; <i32> [#uses=1] - %tmp.6 = shl i32 %Y, 1 ; <i32> [#uses=1] - %tmp.4 = add i32 %tmp.6, %tmp.2 ; <i32> [#uses=1] - ret i32 %tmp.4 -} +define i32 @test1(i32 %X, i32 %Y) { +; CHECK-LABEL: test1 +; CHECK-NEXT: %tmp = add i32 %Y, %X +; CHECK-NEXT: %tmp1 = shl i32 %tmp, 1 +; CHECK-NEXT: ret i32 %tmp1 + %tmp.2 = shl i32 %X, 1 + %tmp.6 = shl i32 %Y, 1 + %tmp.4 = add i32 %tmp.6, %tmp.2 + ret i32 %tmp.4 +} diff --git a/test/Transforms/Reassociate/subtest.ll b/test/Transforms/Reassociate/subtest.ll index 4c63d1238a67..e6263d85522c 100644 --- a/test/Transforms/Reassociate/subtest.ll +++ b/test/Transforms/Reassociate/subtest.ll @@ -1,11 +1,26 @@ -; With sub reassociation, constant folding can eliminate the 12 and -12 constants. -; -; RUN: opt < %s -reassociate -instcombine -S | not grep 12 +; RUN: opt < %s -reassociate -instcombine -S | FileCheck %s -define i32 @test(i32 %A, i32 %B) { - %X = add i32 -12, %A ; <i32> [#uses=1] - %Y = sub i32 %X, %B ; <i32> [#uses=1] - %Z = add i32 %Y, 12 ; <i32> [#uses=1] - ret i32 %Z +; With sub reassociation, constant folding can eliminate the 12 and -12 constants. +define i32 @test1(i32 %A, i32 %B) { +; CHECK-LABEL: @test1 +; CHECK-NEXT: %Z = sub i32 %A, %B +; CHECK-NEXT: ret i32 %Z + %X = add i32 -12, %A + %Y = sub i32 %X, %B + %Z = add i32 %Y, 12 + ret i32 %Z } +; PR2047 +; With sub reassociation, constant folding can eliminate the uses of %a. +define i32 @test2(i32 %a, i32 %b, i32 %c) nounwind { +; CHECK-LABEL: @test2 +; CHECK-NEXT: %sum = add i32 %c, %b +; CHECK-NEXT: %tmp7 = sub i32 0, %sum +; CHECK-NEXT: ret i32 %tmp7 + + %tmp3 = sub i32 %a, %b + %tmp5 = sub i32 %tmp3, %c + %tmp7 = sub i32 %tmp5, %a + ret i32 %tmp7 +} diff --git a/test/Transforms/Reassociate/subtest2.ll b/test/Transforms/Reassociate/subtest2.ll deleted file mode 100644 index 0513c5fc1b63..000000000000 --- a/test/Transforms/Reassociate/subtest2.ll +++ /dev/null @@ -1,13 +0,0 @@ -; With sub reassociation, constant folding can eliminate the uses of %a. -; -; RUN: opt < %s -reassociate -instcombine -S | grep %a | count 1 -; PR2047 - -define i32 @test(i32 %a, i32 %b, i32 %c) nounwind { -entry: - %tmp3 = sub i32 %a, %b ; <i32> [#uses=1] - %tmp5 = sub i32 %tmp3, %c ; <i32> [#uses=1] - %tmp7 = sub i32 %tmp5, %a ; <i32> [#uses=1] - ret i32 %tmp7 -} - diff --git a/test/Transforms/SCCP/atomic.ll b/test/Transforms/SCCP/atomic.ll new file mode 100644 index 000000000000..60d4896ec2b0 --- /dev/null +++ b/test/Transforms/SCCP/atomic.ll @@ -0,0 +1,9 @@ +; RUN: opt < %s -sccp -S | FileCheck %s + +define i1 @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) { +; CHECK-LABEL: @test_cmpxchg +; CHECK: cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst + %val = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst + %res = extractvalue { i32, i1 } %val, 1 + ret i1 %res +} diff --git a/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg b/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg new file mode 100644 index 000000000000..7184443994b6 --- /dev/null +++ b/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'AArch64' in config.root.targets: + config.unsupported = True diff --git a/test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll b/test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll new file mode 100644 index 000000000000..3d6da124fc45 --- /dev/null +++ b/test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll @@ -0,0 +1,18 @@ +; RUN: opt -S -slp-vectorizer %s | FileCheck %s +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-ios5.0.0" + +define i64 @mismatched_intrinsics(<4 x i32> %in1, <2 x i32> %in2) nounwind { +; CHECK-LABEL: @mismatched_intrinsics +; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v4i32 +; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v2i32 + + %vaddlvq_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1) #2 + %vaddlv_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in2) #2 + %tst = icmp sgt i64 %vaddlvq_s32.i, %vaddlv_s32.i + %equal = sext i1 %tst to i64 + ret i64 %equal +} + +declare i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1) +declare i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in1) diff --git a/test/Transforms/SLPVectorizer/ARM/lit.local.cfg b/test/Transforms/SLPVectorizer/ARM/lit.local.cfg index 5fc35d80541d..236e1d344166 100644 --- a/test/Transforms/SLPVectorizer/ARM/lit.local.cfg +++ b/test/Transforms/SLPVectorizer/ARM/lit.local.cfg @@ -1,3 +1,2 @@ -targets = set(config.root.targets_to_build.split()) -if not 'ARM' in targets: +if not 'ARM' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/SLPVectorizer/R600/lit.local.cfg b/test/Transforms/SLPVectorizer/R600/lit.local.cfg index 9e0ab99235e0..4086e8d681c3 100644 --- a/test/Transforms/SLPVectorizer/R600/lit.local.cfg +++ b/test/Transforms/SLPVectorizer/R600/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'R600' in targets: +if not 'R600' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/SLPVectorizer/X86/addsub.ll b/test/Transforms/SLPVectorizer/X86/addsub.ll new file mode 100644 index 000000000000..8303bc8181ef --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/addsub.ll @@ -0,0 +1,181 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -S | FileCheck %s +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@b = common global [4 x i32] zeroinitializer, align 16 +@c = common global [4 x i32] zeroinitializer, align 16 +@d = common global [4 x i32] zeroinitializer, align 16 +@e = common global [4 x i32] zeroinitializer, align 16 +@a = common global [4 x i32] zeroinitializer, align 16 +@fb = common global [4 x float] zeroinitializer, align 16 +@fc = common global [4 x float] zeroinitializer, align 16 +@fa = common global [4 x float] zeroinitializer, align 16 + +; CHECK-LABEL: @addsub +; CHECK: %5 = add <4 x i32> %3, %4 +; CHECK: %6 = add <4 x i32> %2, %5 +; CHECK: %7 = sub <4 x i32> %2, %5 +; CHECK: %8 = shufflevector <4 x i32> %6, <4 x i32> %7, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + +; Function Attrs: nounwind uwtable +define void @addsub() #0 { +entry: + %0 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 0), align 4 + %1 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 0), align 4 + %add = add nsw i32 %0, %1 + %2 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 0), align 4 + %3 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 0), align 4 + %add1 = add nsw i32 %2, %3 + %add2 = add nsw i32 %add, %add1 + store i32 %add2, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 0), align 4 + %4 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 1), align 4 + %5 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 1), align 4 + %add3 = add nsw i32 %4, %5 + %6 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 1), align 4 + %7 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 1), align 4 + %add4 = add nsw i32 %6, %7 + %sub = sub nsw i32 %add3, %add4 + store i32 %sub, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 1), align 4 + %8 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 2), align 4 + %9 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 2), align 4 + %add5 = add nsw i32 %8, %9 + %10 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 2), align 4 + %11 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 2), align 4 + %add6 = add nsw i32 %10, %11 + %add7 = add nsw i32 %add5, %add6 + store i32 %add7, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 2), align 4 + %12 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 3), align 4 + %13 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 3), align 4 + %add8 = add nsw i32 %12, %13 + %14 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 3), align 4 + %15 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 3), align 4 + %add9 = add nsw i32 %14, %15 + %sub10 = sub nsw i32 %add8, %add9 + store i32 %sub10, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 3), align 4 + ret void +} + +; CHECK-LABEL: @subadd +; CHECK: %5 = add <4 x i32> %3, %4 +; CHECK: %6 = sub <4 x i32> %2, %5 +; CHECK: %7 = add <4 x i32> %2, %5 +; CHECK: %8 = shufflevector <4 x i32> %6, <4 x i32> %7, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + +; Function Attrs: nounwind uwtable +define void @subadd() #0 { +entry: + %0 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 0), align 4 + %1 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 0), align 4 + %add = add nsw i32 %0, %1 + %2 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 0), align 4 + %3 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 0), align 4 + %add1 = add nsw i32 %2, %3 + %sub = sub nsw i32 %add, %add1 + store i32 %sub, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 0), align 4 + %4 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 1), align 4 + %5 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 1), align 4 + %add2 = add nsw i32 %4, %5 + %6 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 1), align 4 + %7 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 1), align 4 + %add3 = add nsw i32 %6, %7 + %add4 = add nsw i32 %add2, %add3 + store i32 %add4, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 1), align 4 + %8 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 2), align 4 + %9 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 2), align 4 + %add5 = add nsw i32 %8, %9 + %10 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 2), align 4 + %11 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 2), align 4 + %add6 = add nsw i32 %10, %11 + %sub7 = sub nsw i32 %add5, %add6 + store i32 %sub7, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 2), align 4 + %12 = load i32* getelementptr inbounds ([4 x i32]* @b, i32 0, i64 3), align 4 + %13 = load i32* getelementptr inbounds ([4 x i32]* @c, i32 0, i64 3), align 4 + %add8 = add nsw i32 %12, %13 + %14 = load i32* getelementptr inbounds ([4 x i32]* @d, i32 0, i64 3), align 4 + %15 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i64 3), align 4 + %add9 = add nsw i32 %14, %15 + %add10 = add nsw i32 %add8, %add9 + store i32 %add10, i32* getelementptr inbounds ([4 x i32]* @a, i32 0, i64 3), align 4 + ret void +} + +; CHECK-LABEL: @faddfsub +; CHECK: %2 = fadd <4 x float> %0, %1 +; CHECK: %3 = fsub <4 x float> %0, %1 +; CHECK: %4 = shufflevector <4 x float> %2, <4 x float> %3, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; Function Attrs: nounwind uwtable +define void @faddfsub() #0 { +entry: + %0 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 0), align 4 + %1 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 0), align 4 + %add = fadd float %0, %1 + store float %add, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 0), align 4 + %2 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 1), align 4 + %3 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 1), align 4 + %sub = fsub float %2, %3 + store float %sub, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 1), align 4 + %4 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 2), align 4 + %5 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 2), align 4 + %add1 = fadd float %4, %5 + store float %add1, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 2), align 4 + %6 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 3), align 4 + %7 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 3), align 4 + %sub2 = fsub float %6, %7 + store float %sub2, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 3), align 4 + ret void +} + +; CHECK-LABEL: @fsubfadd +; CHECK: %2 = fsub <4 x float> %0, %1 +; CHECK: %3 = fadd <4 x float> %0, %1 +; CHECK: %4 = shufflevector <4 x float> %2, <4 x float> %3, <4 x i32> <i32 0, i32 5, i32 2, i32 7> +; Function Attrs: nounwind uwtable +define void @fsubfadd() #0 { +entry: + %0 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 0), align 4 + %1 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 0), align 4 + %sub = fsub float %0, %1 + store float %sub, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 0), align 4 + %2 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 1), align 4 + %3 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 1), align 4 + %add = fadd float %2, %3 + store float %add, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 1), align 4 + %4 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 2), align 4 + %5 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 2), align 4 + %sub1 = fsub float %4, %5 + store float %sub1, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 2), align 4 + %6 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 3), align 4 + %7 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 3), align 4 + %add2 = fadd float %6, %7 + store float %add2, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 3), align 4 + ret void +} + +; CHECK-LABEL: @No_faddfsub +; CHECK-NOT: fadd <4 x float> +; CHECK-NOT: fsub <4 x float> +; CHECK-NOT: shufflevector +; Function Attrs: nounwind uwtable +define void @No_faddfsub() #0 { +entry: + %0 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 0), align 4 + %1 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 0), align 4 + %add = fadd float %0, %1 + store float %add, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 0), align 4 + %2 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 1), align 4 + %3 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 1), align 4 + %add1 = fadd float %2, %3 + store float %add1, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 1), align 4 + %4 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 2), align 4 + %5 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 2), align 4 + %add2 = fadd float %4, %5 + store float %add2, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 2), align 4 + %6 = load float* getelementptr inbounds ([4 x float]* @fb, i32 0, i64 3), align 4 + %7 = load float* getelementptr inbounds ([4 x float]* @fc, i32 0, i64 3), align 4 + %sub = fsub float %6, %7 + store float %sub, float* getelementptr inbounds ([4 x float]* @fa, i32 0, i64 3), align 4 + ret void +} + +attributes #0 = { nounwind } + diff --git a/test/Transforms/SLPVectorizer/X86/align.ll b/test/Transforms/SLPVectorizer/X86/align.ll new file mode 100644 index 000000000000..f5865733ccb5 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/align.ll @@ -0,0 +1,27 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; Simple 3-pair chain with loads and stores +; CHECK: test1 +define void @test1(double* %a, double* %b, double* %c) { +entry: + %agg.tmp.i.i.sroa.0 = alloca [3 x double], align 16 +; CHECK: %[[V0:[0-9]+]] = load <2 x double>* %[[V2:[0-9]+]], align 8 + %i0 = load double* %a + %i1 = load double* %b + %mul = fmul double %i0, %i1 + %store1 = getelementptr inbounds [3 x double]* %agg.tmp.i.i.sroa.0, i64 0, i64 1 + %store2 = getelementptr inbounds [3 x double]* %agg.tmp.i.i.sroa.0, i64 0, i64 2 + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8 + %mul5 = fmul double %i3, %i4 +; CHECK: store <2 x double> %[[V1:[0-9]+]], <2 x double>* %[[V2:[0-9]+]], align 8 + store double %mul, double* %store1 + store double %mul5, double* %store2, align 16 +; CHECK: ret + ret void +} diff --git a/test/Transforms/SLPVectorizer/X86/call.ll b/test/Transforms/SLPVectorizer/X86/call.ll new file mode 100644 index 000000000000..83d45c0a9d72 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/call.ll @@ -0,0 +1,128 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -slp-threshold=-999 -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +declare double @sin(double) +declare double @cos(double) +declare double @pow(double, double) +declare double @exp2(double) +declare i64 @round(i64) + + +; CHECK: sin_libm +; CHECK: call <2 x double> @llvm.sin.v2f64 +; CHECK: ret void +define void @sin_libm(double* %a, double* %b, double* %c) { +entry: + %i0 = load double* %a, align 8 + %i1 = load double* %b, align 8 + %mul = fmul double %i0, %i1 + %call = tail call double @sin(double %mul) nounwind readnone + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8 + %mul5 = fmul double %i3, %i4 + %call5 = tail call double @sin(double %mul5) nounwind readnone + store double %call, double* %c, align 8 + %arrayidx5 = getelementptr inbounds double* %c, i64 1 + store double %call5, double* %arrayidx5, align 8 + ret void +} + +; CHECK: cos_libm +; CHECK: call <2 x double> @llvm.cos.v2f64 +; CHECK: ret void +define void @cos_libm(double* %a, double* %b, double* %c) { +entry: + %i0 = load double* %a, align 8 + %i1 = load double* %b, align 8 + %mul = fmul double %i0, %i1 + %call = tail call double @cos(double %mul) nounwind readnone + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8 + %mul5 = fmul double %i3, %i4 + %call5 = tail call double @cos(double %mul5) nounwind readnone + store double %call, double* %c, align 8 + %arrayidx5 = getelementptr inbounds double* %c, i64 1 + store double %call5, double* %arrayidx5, align 8 + ret void +} + +; CHECK: pow_libm +; CHECK: call <2 x double> @llvm.pow.v2f64 +; CHECK: ret void +define void @pow_libm(double* %a, double* %b, double* %c) { +entry: + %i0 = load double* %a, align 8 + %i1 = load double* %b, align 8 + %mul = fmul double %i0, %i1 + %call = tail call double @pow(double %mul,double %mul) nounwind readnone + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8 + %mul5 = fmul double %i3, %i4 + %call5 = tail call double @pow(double %mul5,double %mul5) nounwind readnone + store double %call, double* %c, align 8 + %arrayidx5 = getelementptr inbounds double* %c, i64 1 + store double %call5, double* %arrayidx5, align 8 + ret void +} + + +; CHECK: exp2_libm +; CHECK: call <2 x double> @llvm.exp2.v2f64 +; CHECK: ret void +define void @exp2_libm(double* %a, double* %b, double* %c) { +entry: + %i0 = load double* %a, align 8 + %i1 = load double* %b, align 8 + %mul = fmul double %i0, %i1 + %call = tail call double @exp2(double %mul) nounwind readnone + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8 + %mul5 = fmul double %i3, %i4 + %call5 = tail call double @exp2(double %mul5) nounwind readnone + store double %call, double* %c, align 8 + %arrayidx5 = getelementptr inbounds double* %c, i64 1 + store double %call5, double* %arrayidx5, align 8 + ret void +} + + +; Negative test case +; CHECK: round_custom +; CHECK-NOT: load <4 x i64> +; CHECK: ret void +define void @round_custom(i64* %a, i64* %b, i64* %c) { +entry: + %i0 = load i64* %a, align 8 + %i1 = load i64* %b, align 8 + %mul = mul i64 %i0, %i1 + %call = tail call i64 @round(i64 %mul) nounwind readnone + %arrayidx3 = getelementptr inbounds i64* %a, i64 1 + %i3 = load i64* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds i64* %b, i64 1 + %i4 = load i64* %arrayidx4, align 8 + %mul5 = mul i64 %i3, %i4 + %call5 = tail call i64 @round(i64 %mul5) nounwind readnone + store i64 %call, i64* %c, align 8 + %arrayidx5 = getelementptr inbounds i64* %c, i64 1 + store i64 %call5, i64* %arrayidx5, align 8 + ret void +} + + +; CHECK: declare <2 x double> @llvm.sin.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.cos.v2f64(<2 x double>) #0 +; CHECK: declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) #0 +; CHECK: declare <2 x double> @llvm.exp2.v2f64(<2 x double>) #0 + +; CHECK: attributes #0 = { nounwind readnone } + diff --git a/test/Transforms/SLPVectorizer/X86/consecutive-access.ll b/test/Transforms/SLPVectorizer/X86/consecutive-access.ll new file mode 100644 index 000000000000..f4f112fe32c6 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/consecutive-access.ll @@ -0,0 +1,175 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -S | FileCheck %s +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +@A = common global [2000 x double] zeroinitializer, align 16 +@B = common global [2000 x double] zeroinitializer, align 16 +@C = common global [2000 x float] zeroinitializer, align 16 +@D = common global [2000 x float] zeroinitializer, align 16 + +; Currently SCEV isn't smart enough to figure out that accesses +; A[3*i], A[3*i+1] and A[3*i+2] are consecutive, but in future +; that would hopefully be fixed. For now, check that this isn't +; vectorized. +; CHECK-LABEL: foo_3double +; CHECK-NOT: x double> +; Function Attrs: nounwind ssp uwtable +define void @foo_3double(i32 %u) #0 { +entry: + %u.addr = alloca i32, align 4 + store i32 %u, i32* %u.addr, align 4 + %mul = mul nsw i32 %u, 3 + %idxprom = sext i32 %mul to i64 + %arrayidx = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom + %0 = load double* %arrayidx, align 8 + %arrayidx4 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom + %1 = load double* %arrayidx4, align 8 + %add5 = fadd double %0, %1 + store double %add5, double* %arrayidx, align 8 + %add11 = add nsw i32 %mul, 1 + %idxprom12 = sext i32 %add11 to i64 + %arrayidx13 = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom12 + %2 = load double* %arrayidx13, align 8 + %arrayidx17 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom12 + %3 = load double* %arrayidx17, align 8 + %add18 = fadd double %2, %3 + store double %add18, double* %arrayidx13, align 8 + %add24 = add nsw i32 %mul, 2 + %idxprom25 = sext i32 %add24 to i64 + %arrayidx26 = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom25 + %4 = load double* %arrayidx26, align 8 + %arrayidx30 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom25 + %5 = load double* %arrayidx30, align 8 + %add31 = fadd double %4, %5 + store double %add31, double* %arrayidx26, align 8 + ret void +} + +; SCEV should be able to tell that accesses A[C1 + C2*i], A[C1 + C2*i], ... +; A[C1 + C2*i] are consecutive, if C2 is a power of 2, and C2 > C1 > 0. +; Thus, the following code should be vectorized. +; CHECK-LABEL: foo_2double +; CHECK: x double> +; Function Attrs: nounwind ssp uwtable +define void @foo_2double(i32 %u) #0 { +entry: + %u.addr = alloca i32, align 4 + store i32 %u, i32* %u.addr, align 4 + %mul = mul nsw i32 %u, 2 + %idxprom = sext i32 %mul to i64 + %arrayidx = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom + %0 = load double* %arrayidx, align 8 + %arrayidx4 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom + %1 = load double* %arrayidx4, align 8 + %add5 = fadd double %0, %1 + store double %add5, double* %arrayidx, align 8 + %add11 = add nsw i32 %mul, 1 + %idxprom12 = sext i32 %add11 to i64 + %arrayidx13 = getelementptr inbounds [2000 x double]* @A, i32 0, i64 %idxprom12 + %2 = load double* %arrayidx13, align 8 + %arrayidx17 = getelementptr inbounds [2000 x double]* @B, i32 0, i64 %idxprom12 + %3 = load double* %arrayidx17, align 8 + %add18 = fadd double %2, %3 + store double %add18, double* %arrayidx13, align 8 + ret void +} + +; Similar to the previous test, but with different datatype. +; CHECK-LABEL: foo_4float +; CHECK: x float> +; Function Attrs: nounwind ssp uwtable +define void @foo_4float(i32 %u) #0 { +entry: + %u.addr = alloca i32, align 4 + store i32 %u, i32* %u.addr, align 4 + %mul = mul nsw i32 %u, 4 + %idxprom = sext i32 %mul to i64 + %arrayidx = getelementptr inbounds [2000 x float]* @C, i32 0, i64 %idxprom + %0 = load float* %arrayidx, align 4 + %arrayidx4 = getelementptr inbounds [2000 x float]* @D, i32 0, i64 %idxprom + %1 = load float* %arrayidx4, align 4 + %add5 = fadd float %0, %1 + store float %add5, float* %arrayidx, align 4 + %add11 = add nsw i32 %mul, 1 + %idxprom12 = sext i32 %add11 to i64 + %arrayidx13 = getelementptr inbounds [2000 x float]* @C, i32 0, i64 %idxprom12 + %2 = load float* %arrayidx13, align 4 + %arrayidx17 = getelementptr inbounds [2000 x float]* @D, i32 0, i64 %idxprom12 + %3 = load float* %arrayidx17, align 4 + %add18 = fadd float %2, %3 + store float %add18, float* %arrayidx13, align 4 + %add24 = add nsw i32 %mul, 2 + %idxprom25 = sext i32 %add24 to i64 + %arrayidx26 = getelementptr inbounds [2000 x float]* @C, i32 0, i64 %idxprom25 + %4 = load float* %arrayidx26, align 4 + %arrayidx30 = getelementptr inbounds [2000 x float]* @D, i32 0, i64 %idxprom25 + %5 = load float* %arrayidx30, align 4 + %add31 = fadd float %4, %5 + store float %add31, float* %arrayidx26, align 4 + %add37 = add nsw i32 %mul, 3 + %idxprom38 = sext i32 %add37 to i64 + %arrayidx39 = getelementptr inbounds [2000 x float]* @C, i32 0, i64 %idxprom38 + %6 = load float* %arrayidx39, align 4 + %arrayidx43 = getelementptr inbounds [2000 x float]* @D, i32 0, i64 %idxprom38 + %7 = load float* %arrayidx43, align 4 + %add44 = fadd float %6, %7 + store float %add44, float* %arrayidx39, align 4 + ret void +} + +; Similar to the previous tests, but now we are dealing with AddRec SCEV. +; CHECK-LABEL: foo_loop +; CHECK: x double> +; Function Attrs: nounwind ssp uwtable +define i32 @foo_loop(double* %A, i32 %n) #0 { +entry: + %A.addr = alloca double*, align 8 + %n.addr = alloca i32, align 4 + %sum = alloca double, align 8 + %i = alloca i32, align 4 + store double* %A, double** %A.addr, align 8 + store i32 %n, i32* %n.addr, align 4 + store double 0.000000e+00, double* %sum, align 8 + store i32 0, i32* %i, align 4 + %cmp1 = icmp slt i32 0, %n + br i1 %cmp1, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %0 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] + %1 = phi double [ 0.000000e+00, %for.body.lr.ph ], [ %add7, %for.body ] + %mul = mul nsw i32 %0, 2 + %idxprom = sext i32 %mul to i64 + %arrayidx = getelementptr inbounds double* %A, i64 %idxprom + %2 = load double* %arrayidx, align 8 + %mul1 = fmul double 7.000000e+00, %2 + %add = add nsw i32 %mul, 1 + %idxprom3 = sext i32 %add to i64 + %arrayidx4 = getelementptr inbounds double* %A, i64 %idxprom3 + %3 = load double* %arrayidx4, align 8 + %mul5 = fmul double 7.000000e+00, %3 + %add6 = fadd double %mul1, %mul5 + %add7 = fadd double %1, %add6 + store double %add7, double* %sum, align 8 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* %i, align 4 + %cmp = icmp slt i32 %inc, %n + br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge + +for.cond.for.end_crit_edge: ; preds = %for.body + %split = phi double [ %add7, %for.body ] + br label %for.end + +for.end: ; preds = %for.cond.for.end_crit_edge, %entry + %.lcssa = phi double [ %split, %for.cond.for.end_crit_edge ], [ 0.000000e+00, %entry ] + %conv = fptosi double %.lcssa to i32 + ret i32 %conv +} + +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.ident = !{!0} + +!0 = metadata !{metadata !"clang version 3.5.0 "} diff --git a/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll b/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll new file mode 100644 index 000000000000..ed225743a6e2 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/continue_vectorizing.ll @@ -0,0 +1,31 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; We will keep trying to vectorize the basic block even we already find vectorized store. +; CHECK: test1 +; CHECK: store <2 x double> +; CHECK: ret +define void @test1(double* %a, double* %b, double* %c, double* %d) { +entry: + %i0 = load double* %a, align 8 + %i1 = load double* %b, align 8 + %mul = fmul double %i0, %i1 + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8 + %mul5 = fmul double %i3, %i4 + store double %mul, double* %c, align 8 + %arrayidx5 = getelementptr inbounds double* %c, i64 1 + store double %mul5, double* %arrayidx5, align 8 + %0 = bitcast double* %a to <4 x i32>* + %1 = load <4 x i32>* %0, align 8 + %2 = bitcast double* %b to <4 x i32>* + %3 = load <4 x i32>* %2, align 8 + %4 = mul <4 x i32> %1, %3 + %5 = bitcast double* %d to <4 x i32>* + store <4 x i32> %4, <4 x i32>* %5, align 8 + ret void +} diff --git a/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll b/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll new file mode 100644 index 000000000000..c7ec98adf135 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/crash_vectorizeTree.ll @@ -0,0 +1,65 @@ +; RUN: opt -slp-vectorizer -mtriple=x86_64-apple-macosx10.9.0 -mcpu=corei7-avx -S < %s | FileCheck %s +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + + +; This test used to crash because we were following phi chains incorrectly. +; We used indices to get the incoming value of two phi nodes rather than +; incoming block lookup. +; This can give wrong results when the ordering of incoming +; edges in the two phi nodes don't match. +;CHECK-LABEL: bar + +%0 = type { %1, %2 } +%1 = type { double, double } +%2 = type { double, double } + + +;define fastcc void @bar() { +define void @bar() { + %1 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 0 + %2 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 1 + %3 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 0 + %4 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 1 + %5 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 0 + %6 = getelementptr inbounds %0* undef, i64 0, i32 1, i32 1 + br label %7 + +; <label>:7 ; preds = %18, %17, %17, %0 + %8 = phi double [ 2.800000e+01, %0 ], [ %11, %18 ], [ %11, %17 ], [ %11, %17 ] + %9 = phi double [ 1.800000e+01, %0 ], [ %10, %18 ], [ %10, %17 ], [ %10, %17 ] + store double %9, double* %1, align 8 + store double %8, double* %2, align 8 + %10 = load double* %3, align 8 + %11 = load double* %4, align 8 + br i1 undef, label %12, label %13 + +; <label>:12 ; preds = %7 + ret void + +; <label>:13 ; preds = %7 + store double %10, double* %5, align 8 + store double %11, double* %6, align 8 + br i1 undef, label %14, label %15 + +; <label>:14 ; preds = %13 + br label %15 + +; <label>:15 ; preds = %14, %13 + br i1 undef, label %16, label %17 + +; <label>:16 ; preds = %15 + unreachable + +; <label>:17 ; preds = %15 + switch i32 undef, label %18 [ + i32 32, label %7 + i32 103, label %7 + ] + +; <label>:18 ; preds = %17 + br i1 undef, label %7, label %19 + +; <label>:19 ; preds = %18 + unreachable +} diff --git a/test/Transforms/SLPVectorizer/X86/cse.ll b/test/Transforms/SLPVectorizer/X86/cse.ll index bbfd6f28ea97..d2ad7eb1a82a 100644 --- a/test/Transforms/SLPVectorizer/X86/cse.ll +++ b/test/Transforms/SLPVectorizer/X86/cse.ll @@ -217,3 +217,33 @@ return: ; preds = %entry, %if.end ret i32 0 } +%class.B.53.55 = type { %class.A.52.54, double } +%class.A.52.54 = type { double, double, double } + +@a = external global double, align 8 + +define void @PR19646(%class.B.53.55* %this) { +entry: + br i1 undef, label %if.end13, label %if.end13 + +sw.epilog7: ; No predecessors! + %.in = getelementptr inbounds %class.B.53.55* %this, i64 0, i32 0, i32 1 + %0 = load double* %.in, align 8 + %add = fadd double undef, 0.000000e+00 + %add6 = fadd double %add, %0 + %1 = load double* @a, align 8 + %add8 = fadd double %1, 0.000000e+00 + %_dy = getelementptr inbounds %class.B.53.55* %this, i64 0, i32 0, i32 2 + %2 = load double* %_dy, align 8 + %add10 = fadd double %add8, %2 + br i1 undef, label %if.then12, label %if.end13 + +if.then12: ; preds = %sw.epilog7 + %3 = load double* undef, align 8 + br label %if.end13 + +if.end13: ; preds = %if.then12, %sw.epilog7, %entry + %x.1 = phi double [ 0.000000e+00, %if.then12 ], [ %add6, %sw.epilog7 ], [ undef, %entry ], [ undef, %entry ] + %b.0 = phi double [ %3, %if.then12 ], [ %add10, %sw.epilog7 ], [ undef, %entry], [ undef, %entry ] + unreachable +} diff --git a/test/Transforms/SLPVectorizer/X86/extractcost.ll b/test/Transforms/SLPVectorizer/X86/extractcost.ll new file mode 100644 index 000000000000..01baf66e2f95 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/extractcost.ll @@ -0,0 +1,30 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +;CHECK-LABEL: @foo( +;CHECK: store <4 x i32> +;CHECK: ret +define i32 @foo(i32* nocapture %A, i32 %n, i32 %m) { +entry: + %mul = mul nsw i32 %n, 5 + %add = add nsw i32 %mul, 9 + store i32 %add, i32* %A, align 4 + %mul1 = mul nsw i32 %n, 9 + %add2 = add nsw i32 %mul1, 9 + %arrayidx3 = getelementptr inbounds i32* %A, i64 1 + store i32 %add2, i32* %arrayidx3, align 4 + %mul4 = shl i32 %n, 3 + %add5 = add nsw i32 %mul4, 9 + %arrayidx6 = getelementptr inbounds i32* %A, i64 2 + store i32 %add5, i32* %arrayidx6, align 4 + %mul7 = mul nsw i32 %n, 10 + %add8 = add nsw i32 %mul7, 9 + %arrayidx9 = getelementptr inbounds i32* %A, i64 3 + store i32 %add8, i32* %arrayidx9, align 4 + %externaluse1 = add nsw i32 %add, %m + %externaluse2 = mul nsw i32 %add, %m ; we should add the extract cost only once and the store will be vectorized + %add10 = add nsw i32 %externaluse1, %externaluse2 + ret i32 %add10 +} diff --git a/test/Transforms/SLPVectorizer/X86/gep.ll b/test/Transforms/SLPVectorizer/X86/gep.ll new file mode 100644 index 000000000000..9e105ec98489 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/gep.ll @@ -0,0 +1,41 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -S |FileCheck %s +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + +; Test if SLP can handle GEP expressions. +; The test perform the following action: +; x->first = y->first + 16 +; x->second = y->second + 16 + +; CHECK-LABEL: foo1 +; CHECK: <2 x i32*> +define void @foo1 ({ i32*, i32* }* noalias %x, { i32*, i32* }* noalias %y) { + %1 = getelementptr inbounds { i32*, i32* }* %y, i64 0, i32 0 + %2 = load i32** %1, align 8 + %3 = getelementptr inbounds i32* %2, i64 16 + %4 = getelementptr inbounds { i32*, i32* }* %x, i64 0, i32 0 + store i32* %3, i32** %4, align 8 + %5 = getelementptr inbounds { i32*, i32* }* %y, i64 0, i32 1 + %6 = load i32** %5, align 8 + %7 = getelementptr inbounds i32* %6, i64 16 + %8 = getelementptr inbounds { i32*, i32* }* %x, i64 0, i32 1 + store i32* %7, i32** %8, align 8 + ret void +} + +; Test that we don't vectorize GEP expressions if indexes are not constants. +; We can't produce an efficient code in that case. +; CHECK-LABEL: foo2 +; CHECK-NOT: <2 x i32*> +define void @foo2 ({ i32*, i32* }* noalias %x, { i32*, i32* }* noalias %y, i32 %i) { + %1 = getelementptr inbounds { i32*, i32* }* %y, i64 0, i32 0 + %2 = load i32** %1, align 8 + %3 = getelementptr inbounds i32* %2, i32 %i + %4 = getelementptr inbounds { i32*, i32* }* %x, i64 0, i32 0 + store i32* %3, i32** %4, align 8 + %5 = getelementptr inbounds { i32*, i32* }* %y, i64 0, i32 1 + %6 = load i32** %5, align 8 + %7 = getelementptr inbounds i32* %6, i32 %i + %8 = getelementptr inbounds { i32*, i32* }* %x, i64 0, i32 1 + store i32* %7, i32** %8, align 8 + ret void +} diff --git a/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll b/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll index 43f7aed9f519..9eda29f101ac 100644 --- a/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll +++ b/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll @@ -1,4 +1,5 @@ ; RUN: opt -S -slp-vectorizer -slp-threshold=-10000 < %s | FileCheck %s +; RUN: opt -S -slp-vectorizer -slp-threshold=0 < %s | FileCheck %s -check-prefix=ZEROTHRESH target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" @@ -194,4 +195,88 @@ define <4 x float> @simple_select_partial_vector(<4 x float> %a, <4 x float> %b, ret <4 x float> %rb } +; Make sure that vectorization happens even if insertelements operations +; must be rescheduled. The case here is from compiling Julia. +define <4 x float> @reschedule_extract(<4 x float> %a, <4 x float> %b) { +; CHECK-LABEL: @reschedule_extract( +; CHECK: %1 = fadd <4 x float> %a, %b + %a0 = extractelement <4 x float> %a, i32 0 + %b0 = extractelement <4 x float> %b, i32 0 + %c0 = fadd float %a0, %b0 + %v0 = insertelement <4 x float> undef, float %c0, i32 0 + %a1 = extractelement <4 x float> %a, i32 1 + %b1 = extractelement <4 x float> %b, i32 1 + %c1 = fadd float %a1, %b1 + %v1 = insertelement <4 x float> %v0, float %c1, i32 1 + %a2 = extractelement <4 x float> %a, i32 2 + %b2 = extractelement <4 x float> %b, i32 2 + %c2 = fadd float %a2, %b2 + %v2 = insertelement <4 x float> %v1, float %c2, i32 2 + %a3 = extractelement <4 x float> %a, i32 3 + %b3 = extractelement <4 x float> %b, i32 3 + %c3 = fadd float %a3, %b3 + %v3 = insertelement <4 x float> %v2, float %c3, i32 3 + ret <4 x float> %v3 +} + +; Check that cost model for vectorization takes credit for +; instructions that are erased. +define <4 x float> @take_credit(<4 x float> %a, <4 x float> %b) { +; ZEROTHRESH-LABEL: @take_credit( +; ZEROTHRESH: %1 = fadd <4 x float> %a, %b + %a0 = extractelement <4 x float> %a, i32 0 + %b0 = extractelement <4 x float> %b, i32 0 + %c0 = fadd float %a0, %b0 + %a1 = extractelement <4 x float> %a, i32 1 + %b1 = extractelement <4 x float> %b, i32 1 + %c1 = fadd float %a1, %b1 + %a2 = extractelement <4 x float> %a, i32 2 + %b2 = extractelement <4 x float> %b, i32 2 + %c2 = fadd float %a2, %b2 + %a3 = extractelement <4 x float> %a, i32 3 + %b3 = extractelement <4 x float> %b, i32 3 + %c3 = fadd float %a3, %b3 + %v0 = insertelement <4 x float> undef, float %c0, i32 0 + %v1 = insertelement <4 x float> %v0, float %c1, i32 1 + %v2 = insertelement <4 x float> %v1, float %c2, i32 2 + %v3 = insertelement <4 x float> %v2, float %c3, i32 3 + ret <4 x float> %v3 +} + +; Make sure we handle multiple trees that feed one build vector correctly. +define <4 x double> @multi_tree(double %w, double %x, double %y, double %z) { +entry: + %t0 = fadd double %w , 0.000000e+00 + %t1 = fadd double %x , 1.000000e+00 + %t2 = fadd double %y , 2.000000e+00 + %t3 = fadd double %z , 3.000000e+00 + %t4 = fmul double %t0, 1.000000e+00 + %i1 = insertelement <4 x double> undef, double %t4, i32 3 + %t5 = fmul double %t1, 1.000000e+00 + %i2 = insertelement <4 x double> %i1, double %t5, i32 2 + %t6 = fmul double %t2, 1.000000e+00 + %i3 = insertelement <4 x double> %i2, double %t6, i32 1 + %t7 = fmul double %t3, 1.000000e+00 + %i4 = insertelement <4 x double> %i3, double %t7, i32 0 + ret <4 x double> %i4 +} +; CHECK-LABEL: @multi_tree +; CHECK-DAG: %[[V0:.+]] = insertelement <2 x double> undef, double %w, i32 0 +; CHECK-DAG: %[[V1:.+]] = insertelement <2 x double> %[[V0]], double %x, i32 1 +; CHECK-DAG: %[[V2:.+]] = fadd <2 x double> %[[V1]], <double 0.000000e+00, double 1.000000e+00> +; CHECK-DAG: %[[V3:.+]] = insertelement <2 x double> undef, double %y, i32 0 +; CHECK-DAG: %[[V4:.+]] = insertelement <2 x double> %[[V3]], double %z, i32 1 +; CHECK-DAG: %[[V5:.+]] = fadd <2 x double> %[[V4]], <double 2.000000e+00, double 3.000000e+00> +; CHECK-DAG: %[[V6:.+]] = fmul <2 x double> <double 1.000000e+00, double 1.000000e+00>, %[[V2]] +; CHECK-DAG: %[[V7:.+]] = extractelement <2 x double> %[[V6]], i32 0 +; CHECK-DAG: %[[I1:.+]] = insertelement <4 x double> undef, double %[[V7]], i32 3 +; CHECK-DAG: %[[V8:.+]] = extractelement <2 x double> %[[V6]], i32 1 +; CHECK-DAG: %[[I2:.+]] = insertelement <4 x double> %[[I1]], double %[[V8]], i32 2 +; CHECK-DAG: %[[V9:.+]] = fmul <2 x double> <double 1.000000e+00, double 1.000000e+00>, %[[V5]] +; CHECK-DAG: %[[V10:.+]] = extractelement <2 x double> %[[V9]], i32 0 +; CHECK-DAG: %[[I3:.+]] = insertelement <4 x double> %i2, double %[[V10]], i32 1 +; CHECK-DAG: %[[V11:.+]] = extractelement <2 x double> %[[V9]], i32 1 +; CHECK-DAG: %[[I4:.+]] = insertelement <4 x double> %i3, double %[[V11]], i32 0 +; CHECK: ret <4 x double> %[[I4]] + attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/Transforms/SLPVectorizer/X86/intrinsic.ll b/test/Transforms/SLPVectorizer/X86/intrinsic.ll new file mode 100644 index 000000000000..937252f4146b --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/intrinsic.ll @@ -0,0 +1,386 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -slp-threshold=-999 -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +declare double @llvm.fabs.f64(double) nounwind readnone + +;CHECK-LABEL: @vec_fabs_f64( +;CHECK: load <2 x double> +;CHECK: load <2 x double> +;CHECK: call <2 x double> @llvm.fabs.v2f64 +;CHECK: store <2 x double> +;CHECK: ret +define void @vec_fabs_f64(double* %a, double* %b, double* %c) { +entry: + %i0 = load double* %a, align 8 + %i1 = load double* %b, align 8 + %mul = fmul double %i0, %i1 + %call = tail call double @llvm.fabs.f64(double %mul) nounwind readnone + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8 + %mul5 = fmul double %i3, %i4 + %call5 = tail call double @llvm.fabs.f64(double %mul5) nounwind readnone + store double %call, double* %c, align 8 + %arrayidx5 = getelementptr inbounds double* %c, i64 1 + store double %call5, double* %arrayidx5, align 8 + ret void +} + +declare float @llvm.copysign.f32(float, float) nounwind readnone + +;CHECK-LABEL: @vec_copysign_f32( +;CHECK: load <4 x float> +;CHECK: load <4 x float> +;CHECK: call <4 x float> @llvm.copysign.v4f32 +;CHECK: store <4 x float> +;CHECK: ret +define void @vec_copysign_f32(float* %a, float* %b, float* noalias %c) { +entry: + %0 = load float* %a, align 4 + %1 = load float* %b, align 4 + %call0 = tail call float @llvm.copysign.f32(float %0, float %1) nounwind readnone + store float %call0, float* %c, align 4 + + %ix2 = getelementptr inbounds float* %a, i64 1 + %2 = load float* %ix2, align 4 + %ix3 = getelementptr inbounds float* %b, i64 1 + %3 = load float* %ix3, align 4 + %call1 = tail call float @llvm.copysign.f32(float %2, float %3) nounwind readnone + %c1 = getelementptr inbounds float* %c, i64 1 + store float %call1, float* %c1, align 4 + + %ix4 = getelementptr inbounds float* %a, i64 2 + %4 = load float* %ix4, align 4 + %ix5 = getelementptr inbounds float* %b, i64 2 + %5 = load float* %ix5, align 4 + %call2 = tail call float @llvm.copysign.f32(float %4, float %5) nounwind readnone + %c2 = getelementptr inbounds float* %c, i64 2 + store float %call2, float* %c2, align 4 + + %ix6 = getelementptr inbounds float* %a, i64 3 + %6 = load float* %ix6, align 4 + %ix7 = getelementptr inbounds float* %b, i64 3 + %7 = load float* %ix7, align 4 + %call3 = tail call float @llvm.copysign.f32(float %6, float %7) nounwind readnone + %c3 = getelementptr inbounds float* %c, i64 3 + store float %call3, float* %c3, align 4 + + ret void +} + +declare i32 @llvm.bswap.i32(i32) nounwind readnone + +define void @vec_bswap_i32(i32* %a, i32* %b, i32* %c) { +entry: + %i0 = load i32* %a, align 4 + %i1 = load i32* %b, align 4 + %add1 = add i32 %i0, %i1 + %call1 = tail call i32 @llvm.bswap.i32(i32 %add1) nounwind readnone + + %arrayidx2 = getelementptr inbounds i32* %a, i32 1 + %i2 = load i32* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i32 1 + %i3 = load i32* %arrayidx3, align 4 + %add2 = add i32 %i2, %i3 + %call2 = tail call i32 @llvm.bswap.i32(i32 %add2) nounwind readnone + + %arrayidx4 = getelementptr inbounds i32* %a, i32 2 + %i4 = load i32* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds i32* %b, i32 2 + %i5 = load i32* %arrayidx5, align 4 + %add3 = add i32 %i4, %i5 + %call3 = tail call i32 @llvm.bswap.i32(i32 %add3) nounwind readnone + + %arrayidx6 = getelementptr inbounds i32* %a, i32 3 + %i6 = load i32* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds i32* %b, i32 3 + %i7 = load i32* %arrayidx7, align 4 + %add4 = add i32 %i6, %i7 + %call4 = tail call i32 @llvm.bswap.i32(i32 %add4) nounwind readnone + + store i32 %call1, i32* %c, align 4 + %arrayidx8 = getelementptr inbounds i32* %c, i32 1 + store i32 %call2, i32* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds i32* %c, i32 2 + store i32 %call3, i32* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds i32* %c, i32 3 + store i32 %call4, i32* %arrayidx10, align 4 + ret void + +; CHECK-LABEL: @vec_bswap_i32( +; CHECK: load <4 x i32> +; CHECK: load <4 x i32> +; CHECK: call <4 x i32> @llvm.bswap.v4i32 +; CHECK: store <4 x i32> +; CHECK: ret +} + +declare i32 @llvm.ctlz.i32(i32,i1) nounwind readnone + +define void @vec_ctlz_i32(i32* %a, i32* %b, i32* %c, i1) { +entry: + %i0 = load i32* %a, align 4 + %i1 = load i32* %b, align 4 + %add1 = add i32 %i0, %i1 + %call1 = tail call i32 @llvm.ctlz.i32(i32 %add1,i1 true) nounwind readnone + + %arrayidx2 = getelementptr inbounds i32* %a, i32 1 + %i2 = load i32* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i32 1 + %i3 = load i32* %arrayidx3, align 4 + %add2 = add i32 %i2, %i3 + %call2 = tail call i32 @llvm.ctlz.i32(i32 %add2,i1 true) nounwind readnone + + %arrayidx4 = getelementptr inbounds i32* %a, i32 2 + %i4 = load i32* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds i32* %b, i32 2 + %i5 = load i32* %arrayidx5, align 4 + %add3 = add i32 %i4, %i5 + %call3 = tail call i32 @llvm.ctlz.i32(i32 %add3,i1 true) nounwind readnone + + %arrayidx6 = getelementptr inbounds i32* %a, i32 3 + %i6 = load i32* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds i32* %b, i32 3 + %i7 = load i32* %arrayidx7, align 4 + %add4 = add i32 %i6, %i7 + %call4 = tail call i32 @llvm.ctlz.i32(i32 %add4,i1 true) nounwind readnone + + store i32 %call1, i32* %c, align 4 + %arrayidx8 = getelementptr inbounds i32* %c, i32 1 + store i32 %call2, i32* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds i32* %c, i32 2 + store i32 %call3, i32* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds i32* %c, i32 3 + store i32 %call4, i32* %arrayidx10, align 4 + ret void + +; CHECK-LABEL: @vec_ctlz_i32( +; CHECK: load <4 x i32> +; CHECK: load <4 x i32> +; CHECK: call <4 x i32> @llvm.ctlz.v4i32 +; CHECK: store <4 x i32> +; CHECK: ret +} + +define void @vec_ctlz_i32_neg(i32* %a, i32* %b, i32* %c, i1) { +entry: + %i0 = load i32* %a, align 4 + %i1 = load i32* %b, align 4 + %add1 = add i32 %i0, %i1 + %call1 = tail call i32 @llvm.ctlz.i32(i32 %add1,i1 true) nounwind readnone + + %arrayidx2 = getelementptr inbounds i32* %a, i32 1 + %i2 = load i32* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i32 1 + %i3 = load i32* %arrayidx3, align 4 + %add2 = add i32 %i2, %i3 + %call2 = tail call i32 @llvm.ctlz.i32(i32 %add2,i1 false) nounwind readnone + + %arrayidx4 = getelementptr inbounds i32* %a, i32 2 + %i4 = load i32* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds i32* %b, i32 2 + %i5 = load i32* %arrayidx5, align 4 + %add3 = add i32 %i4, %i5 + %call3 = tail call i32 @llvm.ctlz.i32(i32 %add3,i1 true) nounwind readnone + + %arrayidx6 = getelementptr inbounds i32* %a, i32 3 + %i6 = load i32* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds i32* %b, i32 3 + %i7 = load i32* %arrayidx7, align 4 + %add4 = add i32 %i6, %i7 + %call4 = tail call i32 @llvm.ctlz.i32(i32 %add4,i1 false) nounwind readnone + + store i32 %call1, i32* %c, align 4 + %arrayidx8 = getelementptr inbounds i32* %c, i32 1 + store i32 %call2, i32* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds i32* %c, i32 2 + store i32 %call3, i32* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds i32* %c, i32 3 + store i32 %call4, i32* %arrayidx10, align 4 + ret void + +; CHECK-LABEL: @vec_ctlz_i32_neg( +; CHECK-NOT: call <4 x i32> @llvm.ctlz.v4i32 + +} + + +declare i32 @llvm.cttz.i32(i32,i1) nounwind readnone + +define void @vec_cttz_i32(i32* %a, i32* %b, i32* %c, i1) { +entry: + %i0 = load i32* %a, align 4 + %i1 = load i32* %b, align 4 + %add1 = add i32 %i0, %i1 + %call1 = tail call i32 @llvm.cttz.i32(i32 %add1,i1 true) nounwind readnone + + %arrayidx2 = getelementptr inbounds i32* %a, i32 1 + %i2 = load i32* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i32 1 + %i3 = load i32* %arrayidx3, align 4 + %add2 = add i32 %i2, %i3 + %call2 = tail call i32 @llvm.cttz.i32(i32 %add2,i1 true) nounwind readnone + + %arrayidx4 = getelementptr inbounds i32* %a, i32 2 + %i4 = load i32* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds i32* %b, i32 2 + %i5 = load i32* %arrayidx5, align 4 + %add3 = add i32 %i4, %i5 + %call3 = tail call i32 @llvm.cttz.i32(i32 %add3,i1 true) nounwind readnone + + %arrayidx6 = getelementptr inbounds i32* %a, i32 3 + %i6 = load i32* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds i32* %b, i32 3 + %i7 = load i32* %arrayidx7, align 4 + %add4 = add i32 %i6, %i7 + %call4 = tail call i32 @llvm.cttz.i32(i32 %add4,i1 true) nounwind readnone + + store i32 %call1, i32* %c, align 4 + %arrayidx8 = getelementptr inbounds i32* %c, i32 1 + store i32 %call2, i32* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds i32* %c, i32 2 + store i32 %call3, i32* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds i32* %c, i32 3 + store i32 %call4, i32* %arrayidx10, align 4 + ret void + +; CHECK-LABEL: @vec_cttz_i32( +; CHECK: load <4 x i32> +; CHECK: load <4 x i32> +; CHECK: call <4 x i32> @llvm.cttz.v4i32 +; CHECK: store <4 x i32> +; CHECK: ret +} + +define void @vec_cttz_i32_neg(i32* %a, i32* %b, i32* %c, i1) { +entry: + %i0 = load i32* %a, align 4 + %i1 = load i32* %b, align 4 + %add1 = add i32 %i0, %i1 + %call1 = tail call i32 @llvm.cttz.i32(i32 %add1,i1 true) nounwind readnone + + %arrayidx2 = getelementptr inbounds i32* %a, i32 1 + %i2 = load i32* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32* %b, i32 1 + %i3 = load i32* %arrayidx3, align 4 + %add2 = add i32 %i2, %i3 + %call2 = tail call i32 @llvm.cttz.i32(i32 %add2,i1 false) nounwind readnone + + %arrayidx4 = getelementptr inbounds i32* %a, i32 2 + %i4 = load i32* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds i32* %b, i32 2 + %i5 = load i32* %arrayidx5, align 4 + %add3 = add i32 %i4, %i5 + %call3 = tail call i32 @llvm.cttz.i32(i32 %add3,i1 true) nounwind readnone + + %arrayidx6 = getelementptr inbounds i32* %a, i32 3 + %i6 = load i32* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds i32* %b, i32 3 + %i7 = load i32* %arrayidx7, align 4 + %add4 = add i32 %i6, %i7 + %call4 = tail call i32 @llvm.cttz.i32(i32 %add4,i1 false) nounwind readnone + + store i32 %call1, i32* %c, align 4 + %arrayidx8 = getelementptr inbounds i32* %c, i32 1 + store i32 %call2, i32* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds i32* %c, i32 2 + store i32 %call3, i32* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds i32* %c, i32 3 + store i32 %call4, i32* %arrayidx10, align 4 + ret void + +; CHECK-LABEL: @vec_cttz_i32_neg( +; CHECK-NOT: call <4 x i32> @llvm.cttz.v4i32 +} + + +declare float @llvm.powi.f32(float, i32) +define void @vec_powi_f32(float* %a, float* %b, float* %c, i32 %P) { +entry: + %i0 = load float* %a, align 4 + %i1 = load float* %b, align 4 + %add1 = fadd float %i0, %i1 + %call1 = tail call float @llvm.powi.f32(float %add1,i32 %P) nounwind readnone + + %arrayidx2 = getelementptr inbounds float* %a, i32 1 + %i2 = load float* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds float* %b, i32 1 + %i3 = load float* %arrayidx3, align 4 + %add2 = fadd float %i2, %i3 + %call2 = tail call float @llvm.powi.f32(float %add2,i32 %P) nounwind readnone + + %arrayidx4 = getelementptr inbounds float* %a, i32 2 + %i4 = load float* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds float* %b, i32 2 + %i5 = load float* %arrayidx5, align 4 + %add3 = fadd float %i4, %i5 + %call3 = tail call float @llvm.powi.f32(float %add3,i32 %P) nounwind readnone + + %arrayidx6 = getelementptr inbounds float* %a, i32 3 + %i6 = load float* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds float* %b, i32 3 + %i7 = load float* %arrayidx7, align 4 + %add4 = fadd float %i6, %i7 + %call4 = tail call float @llvm.powi.f32(float %add4,i32 %P) nounwind readnone + + store float %call1, float* %c, align 4 + %arrayidx8 = getelementptr inbounds float* %c, i32 1 + store float %call2, float* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds float* %c, i32 2 + store float %call3, float* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds float* %c, i32 3 + store float %call4, float* %arrayidx10, align 4 + ret void + +; CHECK-LABEL: @vec_powi_f32( +; CHECK: load <4 x float> +; CHECK: load <4 x float> +; CHECK: call <4 x float> @llvm.powi.v4f32 +; CHECK: store <4 x float> +; CHECK: ret +} + + +define void @vec_powi_f32_neg(float* %a, float* %b, float* %c, i32 %P, i32 %Q) { +entry: + %i0 = load float* %a, align 4 + %i1 = load float* %b, align 4 + %add1 = fadd float %i0, %i1 + %call1 = tail call float @llvm.powi.f32(float %add1,i32 %P) nounwind readnone + + %arrayidx2 = getelementptr inbounds float* %a, i32 1 + %i2 = load float* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds float* %b, i32 1 + %i3 = load float* %arrayidx3, align 4 + %add2 = fadd float %i2, %i3 + %call2 = tail call float @llvm.powi.f32(float %add2,i32 %Q) nounwind readnone + + %arrayidx4 = getelementptr inbounds float* %a, i32 2 + %i4 = load float* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds float* %b, i32 2 + %i5 = load float* %arrayidx5, align 4 + %add3 = fadd float %i4, %i5 + %call3 = tail call float @llvm.powi.f32(float %add3,i32 %P) nounwind readnone + + %arrayidx6 = getelementptr inbounds float* %a, i32 3 + %i6 = load float* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds float* %b, i32 3 + %i7 = load float* %arrayidx7, align 4 + %add4 = fadd float %i6, %i7 + %call4 = tail call float @llvm.powi.f32(float %add4,i32 %Q) nounwind readnone + + store float %call1, float* %c, align 4 + %arrayidx8 = getelementptr inbounds float* %c, i32 1 + store float %call2, float* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds float* %c, i32 2 + store float %call3, float* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds float* %c, i32 3 + store float %call4, float* %arrayidx10, align 4 + ret void + +; CHECK-LABEL: @vec_powi_f32_neg( +; CHECK-NOT: call <4 x float> @llvm.powi.v4f32 +} diff --git a/test/Transforms/SLPVectorizer/X86/lit.local.cfg b/test/Transforms/SLPVectorizer/X86/lit.local.cfg index ba763cf03ffc..e71f3cc4c41e 100644 --- a/test/Transforms/SLPVectorizer/X86/lit.local.cfg +++ b/test/Transforms/SLPVectorizer/X86/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/SLPVectorizer/X86/metadata.ll b/test/Transforms/SLPVectorizer/X86/metadata.ll new file mode 100644 index 000000000000..5bd2fa4ea684 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/metadata.ll @@ -0,0 +1,61 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +;CHECK-LABEL: test1 +;CHECK: load <2 x double>{{.*}}!tbaa ![[TBAA:[0-9]+]] +;CHECK: load <2 x double>{{.*}}!tbaa ![[TBAA]] +;CHECK: fmul <2 x double>{{.*}}!fpmath ![[FP1:[0-9]+]] +;CHECK: store <2 x double>{{.*}}!tbaa ![[TBAA]] +;CHECK: ret void + +define void @test1(double* %a, double* %b, double* %c) { +entry: + %i0 = load double* %a, align 8, !tbaa !4 + %i1 = load double* %b, align 8, !tbaa !4 + %mul = fmul double %i0, %i1, !fpmath !0 + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8, !tbaa !4 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8, !tbaa !4 + %mul5 = fmul double %i3, %i4, !fpmath !0 + store double %mul, double* %c, align 8, !tbaa !4 + %arrayidx5 = getelementptr inbounds double* %c, i64 1 + store double %mul5, double* %arrayidx5, align 8, !tbaa !4 + ret void +} + +;CHECK-LABEL: test2 +;CHECK: load <2 x double>{{.*}}!tbaa ![[TBAA]] +;CHECK: load <2 x double>{{.*}}!tbaa ![[TBAA]] +;CHECK: fmul <2 x double>{{.*}}!fpmath ![[FP2:[0-9]+]] +;CHECK: store <2 x double>{{.*}}!tbaa ![[TBAA]] +;CHECK: ret void + +define void @test2(double* %a, double* %b, i8* %e) { +entry: + %i0 = load double* %a, align 8, !tbaa !4 + %i1 = load double* %b, align 8, !tbaa !4 + %mul = fmul double %i0, %i1, !fpmath !1 + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8, !tbaa !4 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8, !tbaa !4 + %mul5 = fmul double %i3, %i4, !fpmath !1 + %c = bitcast i8* %e to double* + store double %mul, double* %c, align 8, !tbaa !4 + %carrayidx5 = getelementptr inbounds i8* %e, i64 8 + %arrayidx5 = bitcast i8* %carrayidx5 to double* + store double %mul5, double* %arrayidx5, align 8, !tbaa !4 + ret void +} + +;CHECK-DAG: ![[TBAA]] = metadata !{metadata [[TYPEC:!.*]], metadata [[TYPEC]], i64 0} +;CHECK-DAG: ![[FP1]] = metadata !{float 5.000000e+00} +;CHECK-DAG: ![[FP2]] = metadata !{float 2.500000e+00} +!0 = metadata !{ float 5.0 } +!1 = metadata !{ float 2.5 } +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"omnipotent char", metadata !2} +!4 = metadata !{metadata !"double", metadata !3} diff --git a/test/Transforms/SLPVectorizer/X86/non-vectorizable-intrinsic.ll b/test/Transforms/SLPVectorizer/X86/non-vectorizable-intrinsic.ll new file mode 100644 index 000000000000..b250735874c5 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/non-vectorizable-intrinsic.ll @@ -0,0 +1,36 @@ +; RUN: opt < %s -slp-vectorizer -o - -S -slp-threshold=-1000 + +target datalayout = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64" +target triple = "nvptx--nvidiacl" + +; CTLZ cannot be vectorized currently because the second argument is a scalar +; for both the scalar and vector forms of the intrinsic. In the future it +; should be possible to vectorize such functions. +; Test causes an assert if LLVM tries to vectorize CTLZ. + +define <2 x i8> @cltz_test(<2 x i8> %x) #0 { +entry: + %0 = extractelement <2 x i8> %x, i32 0 + %call.i = call i8 @llvm.ctlz.i8(i8 %0, i1 false) + %vecinit = insertelement <2 x i8> undef, i8 %call.i, i32 0 + %1 = extractelement <2 x i8> %x, i32 1 + %call.i4 = call i8 @llvm.ctlz.i8(i8 %1, i1 false) + %vecinit2 = insertelement <2 x i8> %vecinit, i8 %call.i4, i32 1 + ret <2 x i8> %vecinit2 +} + +define <2 x i8> @cltz_test2(<2 x i8> %x) #1 { +entry: + %0 = extractelement <2 x i8> %x, i32 0 + %1 = extractelement <2 x i8> %x, i32 1 + %call.i = call i8 @llvm.ctlz.i8(i8 %0, i1 false) + %call.i4 = call i8 @llvm.ctlz.i8(i8 %1, i1 false) + %vecinit = insertelement <2 x i8> undef, i8 %call.i, i32 0 + %vecinit2 = insertelement <2 x i8> %vecinit, i8 %call.i4, i32 1 + ret <2 x i8> %vecinit2 +} + +declare i8 @llvm.ctlz.i8(i8, i1) #3 + +attributes #0 = { alwaysinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } diff --git a/test/Transforms/SLPVectorizer/X86/phi.ll b/test/Transforms/SLPVectorizer/X86/phi.ll index 964e0e4efee7..0c53b60f3df1 100644 --- a/test/Transforms/SLPVectorizer/X86/phi.ll +++ b/test/Transforms/SLPVectorizer/X86/phi.ll @@ -221,7 +221,7 @@ entry: ; CHECK: load x86_fp80* ; CHECK: load x86_fp80* ; CHECK-NOT: insertelement <2 x x86_fp80> -; CHECK_NOT: insertelement <2 x x86_fp80> +; CHECK-NOT: insertelement <2 x x86_fp80> br i1 undef, label %then, label %end then: diff --git a/test/Transforms/SLPVectorizer/X86/pr19657.ll b/test/Transforms/SLPVectorizer/X86/pr19657.ll new file mode 100644 index 000000000000..93523089c28b --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/pr19657.ll @@ -0,0 +1,73 @@ +; RUN: opt < %s -O1 -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +;CHECK: load <2 x double>* +;CHECK: fadd <2 x double> +;CHECK: store <2 x double> + +; Function Attrs: nounwind uwtable +define void @foo(double* %x) #0 { + %1 = alloca double*, align 8 + store double* %x, double** %1, align 8 + %2 = load double** %1, align 8 + %3 = getelementptr inbounds double* %2, i64 0 + %4 = load double* %3, align 8 + %5 = load double** %1, align 8 + %6 = getelementptr inbounds double* %5, i64 0 + %7 = load double* %6, align 8 + %8 = fadd double %4, %7 + %9 = load double** %1, align 8 + %10 = getelementptr inbounds double* %9, i64 0 + %11 = load double* %10, align 8 + %12 = fadd double %8, %11 + %13 = load double** %1, align 8 + %14 = getelementptr inbounds double* %13, i64 0 + store double %12, double* %14, align 8 + %15 = load double** %1, align 8 + %16 = getelementptr inbounds double* %15, i64 1 + %17 = load double* %16, align 8 + %18 = load double** %1, align 8 + %19 = getelementptr inbounds double* %18, i64 1 + %20 = load double* %19, align 8 + %21 = fadd double %17, %20 + %22 = load double** %1, align 8 + %23 = getelementptr inbounds double* %22, i64 1 + %24 = load double* %23, align 8 + %25 = fadd double %21, %24 + %26 = load double** %1, align 8 + %27 = getelementptr inbounds double* %26, i64 1 + store double %25, double* %27, align 8 + %28 = load double** %1, align 8 + %29 = getelementptr inbounds double* %28, i64 2 + %30 = load double* %29, align 8 + %31 = load double** %1, align 8 + %32 = getelementptr inbounds double* %31, i64 2 + %33 = load double* %32, align 8 + %34 = fadd double %30, %33 + %35 = load double** %1, align 8 + %36 = getelementptr inbounds double* %35, i64 2 + %37 = load double* %36, align 8 + %38 = fadd double %34, %37 + %39 = load double** %1, align 8 + %40 = getelementptr inbounds double* %39, i64 2 + store double %38, double* %40, align 8 + %41 = load double** %1, align 8 + %42 = getelementptr inbounds double* %41, i64 3 + %43 = load double* %42, align 8 + %44 = load double** %1, align 8 + %45 = getelementptr inbounds double* %44, i64 3 + %46 = load double* %45, align 8 + %47 = fadd double %43, %46 + %48 = load double** %1, align 8 + %49 = getelementptr inbounds double* %48, i64 3 + %50 = load double* %49, align 8 + %51 = fadd double %47, %50 + %52 = load double** %1, align 8 + %53 = getelementptr inbounds double* %52, i64 3 + store double %51, double* %53, align 8 + ret void +} + +attributes #0 = { nounwind } diff --git a/test/Transforms/SLPVectorizer/X86/tiny-tree.ll b/test/Transforms/SLPVectorizer/X86/tiny-tree.ll index 2747a1f48997..10c3130b424c 100644 --- a/test/Transforms/SLPVectorizer/X86/tiny-tree.ll +++ b/test/Transforms/SLPVectorizer/X86/tiny-tree.ll @@ -138,3 +138,18 @@ for.body: ; preds = %entry, %for.body for.end: ; preds = %for.body, %entry ret void } + + +; CHECK-LABEL: store_splat +; CHECK: store <4 x float> +define void @store_splat(float*, float) { + %3 = getelementptr inbounds float* %0, i64 0 + store float %1, float* %3, align 4 + %4 = getelementptr inbounds float* %0, i64 1 + store float %1, float* %4, align 4 + %5 = getelementptr inbounds float* %0, i64 2 + store float %1, float* %5, align 4 + %6 = getelementptr inbounds float* %0, i64 3 + store float %1, float* %6, align 4 + ret void +} diff --git a/test/Transforms/SLPVectorizer/X86/value-bug.ll b/test/Transforms/SLPVectorizer/X86/value-bug.ll new file mode 100644 index 000000000000..64d2ae1c7d79 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/value-bug.ll @@ -0,0 +1,80 @@ +; RUN: opt -slp-vectorizer < %s -S -mtriple="x86_64-grtev3-linux-gnu" -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-grtev3-linux-gnu" + +; We used to crash on this example because we were building a constant +; expression during vectorization and the vectorizer expects instructions +; as elements of the vectorized tree. +; CHECK-LABEL: @test +; PR19621 + +define void @test() { +bb279: + br label %bb283 + +bb283: + %Av.sroa.8.0 = phi float [ undef, %bb279 ], [ %tmp315, %exit ] + %Av.sroa.5.0 = phi float [ undef, %bb279 ], [ %tmp319, %exit ] + %Av.sroa.3.0 = phi float [ undef, %bb279 ], [ %tmp307, %exit ] + %Av.sroa.0.0 = phi float [ undef, %bb279 ], [ %tmp317, %exit ] + br label %bb284 + +bb284: + %tmp7.i = fpext float %Av.sroa.3.0 to double + %tmp8.i = fsub double %tmp7.i, undef + %tmp9.i = fsub double %tmp8.i, undef + %tmp17.i = fpext float %Av.sroa.8.0 to double + %tmp19.i = fsub double %tmp17.i, undef + %tmp20.i = fsub double %tmp19.i, undef + br label %bb21.i + +bb21.i: + br i1 undef, label %bb22.i, label %exit + +bb22.i: + %tmp24.i = fadd double undef, %tmp9.i + %tmp26.i = fadd double undef, %tmp20.i + br label %bb32.i + +bb32.i: + %xs.0.i = phi double [ %tmp24.i, %bb22.i ], [ 0.000000e+00, %bb32.i ] + %ys.0.i = phi double [ %tmp26.i, %bb22.i ], [ 0.000000e+00, %bb32.i ] + br i1 undef, label %bb32.i, label %bb21.i + +exit: + %tmp303 = fpext float %Av.sroa.0.0 to double + %tmp304 = fmul double %tmp303, undef + %tmp305 = fadd double undef, %tmp304 + %tmp306 = fadd double %tmp305, undef + %tmp307 = fptrunc double %tmp306 to float + %tmp311 = fpext float %Av.sroa.5.0 to double + %tmp312 = fmul double %tmp311, 0.000000e+00 + %tmp313 = fadd double undef, %tmp312 + %tmp314 = fadd double %tmp313, undef + %tmp315 = fptrunc double %tmp314 to float + %tmp317 = fptrunc double undef to float + %tmp319 = fptrunc double undef to float + br label %bb283 +} + +; Make sure that we probably handle constant folded vectorized trees. The +; vectorizer starts at the type (%t2, %t3) and wil constant fold the tree. +; The code that handles insertelement instructions must handle this. +define <4 x double> @constant_folding() { +entry: + %t0 = fadd double 1.000000e+00 , 0.000000e+00 + %t1 = fadd double 1.000000e+00 , 1.000000e+00 + %t2 = fmul double %t0, 1.000000e+00 + %i1 = insertelement <4 x double> undef, double %t2, i32 1 + %t3 = fmul double %t1, 1.000000e+00 + %i2 = insertelement <4 x double> %i1, double %t3, i32 0 + ret <4 x double> %i2 +} + +; CHECK-LABEL: @constant_folding +; CHECK: %[[V0:.+]] = extractelement <2 x double> <double 1.000000e+00, double 2.000000e+00>, i32 0 +; CHECK: %[[V1:.+]] = insertelement <4 x double> undef, double %[[V0]], i32 1 +; CHECK: %[[V2:.+]] = extractelement <2 x double> <double 1.000000e+00, double 2.000000e+00>, i32 1 +; CHECK: %[[V3:.+]] = insertelement <4 x double> %[[V1]], double %[[V2]], i32 0 +; CHECK: ret <4 x double> %[[V3]] diff --git a/test/Transforms/SLPVectorizer/XCore/lit.local.cfg b/test/Transforms/SLPVectorizer/XCore/lit.local.cfg index 4d17d4642045..bb48713fe33e 100644 --- a/test/Transforms/SLPVectorizer/XCore/lit.local.cfg +++ b/test/Transforms/SLPVectorizer/XCore/lit.local.cfg @@ -1,3 +1,2 @@ -targets = set(config.root.targets_to_build.split()) -if not 'XCore' in targets: +if not 'XCore' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/SROA/address-spaces.ll b/test/Transforms/SROA/address-spaces.ll new file mode 100644 index 000000000000..847f2851bbbf --- /dev/null +++ b/test/Transforms/SROA/address-spaces.ll @@ -0,0 +1,68 @@ +; RUN: opt < %s -sroa -S | FileCheck %s +target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) +declare void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture readonly, i32, i32, i1) +declare void @llvm.memcpy.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture readonly, i32, i32, i1) +declare void @llvm.memcpy.p1i8.p1i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture readonly, i32, i32, i1) + + +; Make sure an illegal bitcast isn't introduced +define void @test_address_space_1_1(<2 x i64> addrspace(1)* %a, i16 addrspace(1)* %b) { +; CHECK-LABEL: @test_address_space_1_1( +; CHECK: load <2 x i64> addrspace(1)* %a, align 2 +; CHECK: store <2 x i64> {{.*}}, <2 x i64> addrspace(1)* {{.*}}, align 2 +; CHECK: ret void + %aa = alloca <2 x i64>, align 16 + %aptr = bitcast <2 x i64> addrspace(1)* %a to i8 addrspace(1)* + %aaptr = bitcast <2 x i64>* %aa to i8* + call void @llvm.memcpy.p0i8.p1i8.i32(i8* %aaptr, i8 addrspace(1)* %aptr, i32 16, i32 2, i1 false) + %bptr = bitcast i16 addrspace(1)* %b to i8 addrspace(1)* + call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* %bptr, i8* %aaptr, i32 16, i32 2, i1 false) + ret void +} + +define void @test_address_space_1_0(<2 x i64> addrspace(1)* %a, i16* %b) { +; CHECK-LABEL: @test_address_space_1_0( +; CHECK: load <2 x i64> addrspace(1)* %a, align 2 +; CHECK: store <2 x i64> {{.*}}, <2 x i64>* {{.*}}, align 2 +; CHECK: ret void + %aa = alloca <2 x i64>, align 16 + %aptr = bitcast <2 x i64> addrspace(1)* %a to i8 addrspace(1)* + %aaptr = bitcast <2 x i64>* %aa to i8* + call void @llvm.memcpy.p0i8.p1i8.i32(i8* %aaptr, i8 addrspace(1)* %aptr, i32 16, i32 2, i1 false) + %bptr = bitcast i16* %b to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %bptr, i8* %aaptr, i32 16, i32 2, i1 false) + ret void +} + +define void @test_address_space_0_1(<2 x i64>* %a, i16 addrspace(1)* %b) { +; CHECK-LABEL: @test_address_space_0_1( +; CHECK: load <2 x i64>* %a, align 2 +; CHECK: store <2 x i64> {{.*}}, <2 x i64> addrspace(1)* {{.*}}, align 2 +; CHECK: ret void + %aa = alloca <2 x i64>, align 16 + %aptr = bitcast <2 x i64>* %a to i8* + %aaptr = bitcast <2 x i64>* %aa to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %aaptr, i8* %aptr, i32 16, i32 2, i1 false) + %bptr = bitcast i16 addrspace(1)* %b to i8 addrspace(1)* + call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* %bptr, i8* %aaptr, i32 16, i32 2, i1 false) + ret void +} + +%struct.struct_test_27.0.13 = type { i32, float, i64, i8, [4 x i32] } + +; Function Attrs: nounwind +define void @copy_struct([5 x i64] %in.coerce) { +; CHECK-LABEL: @copy_struct( +; CHECK-NOT: memcpy +for.end: + %in = alloca %struct.struct_test_27.0.13, align 8 + %0 = bitcast %struct.struct_test_27.0.13* %in to [5 x i64]* + store [5 x i64] %in.coerce, [5 x i64]* %0, align 8 + %scevgep9 = getelementptr %struct.struct_test_27.0.13* %in, i32 0, i32 4, i32 0 + %scevgep910 = bitcast i32* %scevgep9 to i8* + call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* undef, i8* %scevgep910, i32 16, i32 4, i1 false) + ret void +} + diff --git a/test/Transforms/SROA/basictest.ll b/test/Transforms/SROA/basictest.ll index 5d3e4b5d8b2c..dc2b16550a06 100644 --- a/test/Transforms/SROA/basictest.ll +++ b/test/Transforms/SROA/basictest.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -sroa -S | FileCheck %s ; RUN: opt < %s -sroa -force-ssa-updater -S | FileCheck %s -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" +target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" declare void @llvm.lifetime.start(i64, i8* nocapture) declare void @llvm.lifetime.end(i64, i8* nocapture) @@ -404,6 +404,7 @@ entry: } declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind +declare void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) nounwind declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind @@ -1150,6 +1151,24 @@ entry: ; CHECK: ret } +define void @PR14105_as1({ [16 x i8] } addrspace(1)* %ptr) { +; Make sure this the right address space pointer is used for type check. +; CHECK-LABEL: @PR14105_as1( + +entry: + %a = alloca { [16 x i8] }, align 8 +; CHECK: alloca [16 x i8], align 8 + + %gep = getelementptr inbounds { [16 x i8] } addrspace(1)* %ptr, i64 -1 +; CHECK-NEXT: getelementptr inbounds { [16 x i8] } addrspace(1)* %ptr, i16 -1, i32 0, i16 0 + + %cast1 = bitcast { [16 x i8 ] } addrspace(1)* %gep to i8 addrspace(1)* + %cast2 = bitcast { [16 x i8 ] }* %a to i8* + call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* %cast1, i8* %cast2, i32 16, i32 8, i1 true) + ret void +; CHECK: ret +} + define void @PR14465() { ; Ensure that we don't crash when analyzing a alloca larger than the maximum ; integer type width (MAX_INT_BITS) supported by llvm (1048576*32 > (1<<23)-1). @@ -1317,6 +1336,28 @@ define void @PR15805(i1 %a, i1 %b) { ret void } +define void @PR15805.1(i1 %a, i1 %b) { +; Same as the normal PR15805, but rigged to place the use before the def inside +; of looping unreachable code. This helps ensure that we aren't sensitive to the +; order in which the uses of the alloca are visited. +; +; CHECK-LABEL: @PR15805.1( +; CHECK-NOT: alloca +; CHECK: ret void + + %c = alloca i64, align 8 + br label %exit + +loop: + %cond.in = select i1 undef, i64* %c, i64* %p.0.c + %p.0.c = select i1 undef, i64* %c, i64* %c + %cond = load i64* %cond.in, align 8 + br i1 undef, label %loop, label %exit + +exit: + ret void +} + define void @PR16651.1(i8* %a) { ; This test case caused a crash due to the volatile memcpy in combination with ; lowering to integer loads and stores of a width other than that of the original @@ -1356,3 +1397,46 @@ entry: %cond105.i.i = load float* %cond105.in.i.i, align 8 ret void } + +define void @test23(i32 %x) { +; CHECK-LABEL: @test23( +; CHECK-NOT: alloca +; CHECK: ret void +entry: + %a = alloca i32, align 4 + store i32 %x, i32* %a, align 4 + %gep1 = getelementptr inbounds i32* %a, i32 1 + %gep0 = getelementptr inbounds i32* %a, i32 0 + %cast1 = bitcast i32* %gep1 to i8* + %cast0 = bitcast i32* %gep0 to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %cast1, i8* %cast0, i32 4, i32 1, i1 false) + ret void +} + +define void @PR18615() { +; CHECK-LABEL: @PR18615( +; CHECK-NOT: alloca +; CHECK: ret void +entry: + %f = alloca i8 + %gep = getelementptr i8* %f, i64 -1 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %gep, i32 1, i32 1, i1 false) + ret void +} + +define void @test24(i8* %src, i8* %dst) { +; CHECK-LABEL: @test24( +; CHECK: alloca i64, align 16 +; CHECK: load volatile i64* %{{[^,]*}}, align 1 +; CHECK: store volatile i64 %{{[^,]*}}, i64* %{{[^,]*}}, align 16 +; CHECK: load volatile i64* %{{[^,]*}}, align 16 +; CHECK: store volatile i64 %{{[^,]*}}, i64* %{{[^,]*}}, align 1 + +entry: + %a = alloca i64, align 16 + %ptr = bitcast i64* %a to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %ptr, i8* %src, i32 8, i32 1, i1 true) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %ptr, i32 8, i32 1, i1 true) + ret void +} + diff --git a/test/Transforms/SROA/slice-order-independence.ll b/test/Transforms/SROA/slice-order-independence.ll new file mode 100644 index 000000000000..364ef85f1d14 --- /dev/null +++ b/test/Transforms/SROA/slice-order-independence.ll @@ -0,0 +1,37 @@ +; RUN: opt < %s -sroa -S | FileCheck %s +target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind + +; Check that the chosen type for a split is independent from the order of +; slices even in case of types that are skipped because their width is not a +; byte width multiple +define void @skipped_inttype_first({ i16*, i32 }*) { +; CHECK-LABEL: @skipped_inttype_first +; CHECK: alloca i8* + %arg = alloca { i16*, i32 }, align 8 + %2 = bitcast { i16*, i32 }* %0 to i8* + %3 = bitcast { i16*, i32 }* %arg to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %3, i8* %2, i32 16, i32 8, i1 false) + %b = getelementptr inbounds { i16*, i32 }* %arg, i64 0, i32 0 + %pb0 = bitcast i16** %b to i63* + %b0 = load i63* %pb0 + %pb1 = bitcast i16** %b to i8** + %b1 = load i8** %pb1 + ret void +} + +define void @skipped_inttype_last({ i16*, i32 }*) { +; CHECK-LABEL: @skipped_inttype_last +; CHECK: alloca i8* + %arg = alloca { i16*, i32 }, align 8 + %2 = bitcast { i16*, i32 }* %0 to i8* + %3 = bitcast { i16*, i32 }* %arg to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %3, i8* %2, i32 16, i32 8, i1 false) + %b = getelementptr inbounds { i16*, i32 }* %arg, i64 0, i32 0 + %pb1 = bitcast i16** %b to i8** + %b1 = load i8** %pb1 + %pb0 = bitcast i16** %b to i63* + %b0 = load i63* %pb0 + ret void +} diff --git a/test/Transforms/SROA/slice-width.ll b/test/Transforms/SROA/slice-width.ll new file mode 100644 index 000000000000..179780b4afee --- /dev/null +++ b/test/Transforms/SROA/slice-width.ll @@ -0,0 +1,25 @@ +; RUN: opt < %s -sroa -S | FileCheck %s +target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind + +define void @no_split_on_non_byte_width(i32) { +; This tests that allocas are not split into slices that are not byte width multiple + %arg = alloca i32 , align 8 + store i32 %0, i32* %arg + br label %load_i32 + +load_i32: +; CHECK-LABEL: load_i32: +; CHECK-NOT: bitcast {{.*}} to i1 +; CHECK-NOT: zext i1 + %r0 = load i32* %arg + br label %load_i1 + +load_i1: +; CHECK-LABEL: load_i1: +; CHECK: bitcast {{.*}} to i1 + %p1 = bitcast i32* %arg to i1* + %t1 = load i1* %p1 + ret void +} diff --git a/test/Transforms/SROA/vector-promotion.ll b/test/Transforms/SROA/vector-promotion.ll index 4f084214d396..9c9f6a1d08d4 100644 --- a/test/Transforms/SROA/vector-promotion.ll +++ b/test/Transforms/SROA/vector-promotion.ll @@ -150,6 +150,53 @@ entry: ; CHECK-NEXT: ret } +declare void @llvm.memcpy.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) nounwind + +; Same as test4 with a different sized address space pointer source. +define i32 @test4_as1(<4 x i32> %x, <4 x i32> %y, <4 x i32> addrspace(1)* %z) { +; CHECK-LABEL: @test4_as1( +entry: + %a = alloca [2 x <4 x i32>] +; CHECK-NOT: alloca + + %a.x = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0 + store <4 x i32> %x, <4 x i32>* %a.x + %a.y = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1 + store <4 x i32> %y, <4 x i32>* %a.y +; CHECK-NOT: store + + %a.y.cast = bitcast <4 x i32>* %a.y to i8* + %z.cast = bitcast <4 x i32> addrspace(1)* %z to i8 addrspace(1)* + call void @llvm.memcpy.p0i8.p1i8.i32(i8* %a.y.cast, i8 addrspace(1)* %z.cast, i32 16, i32 1, i1 false) +; CHECK-NOT: memcpy + + %a.tmp1 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 0, i64 2 + %a.tmp1.cast = bitcast i32* %a.tmp1 to i8* + %z.tmp1 = getelementptr inbounds <4 x i32> addrspace(1)* %z, i16 0, i16 2 + %z.tmp1.cast = bitcast i32 addrspace(1)* %z.tmp1 to i8 addrspace(1)* + call void @llvm.memcpy.p0i8.p1i8.i32(i8* %a.tmp1.cast, i8 addrspace(1)* %z.tmp1.cast, i32 4, i32 1, i1 false) + %tmp1 = load i32* %a.tmp1 + %a.tmp2 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 3 + %tmp2 = load i32* %a.tmp2 + %a.tmp3 = getelementptr inbounds [2 x <4 x i32>]* %a, i64 0, i64 1, i64 0 + %tmp3 = load i32* %a.tmp3 +; CHECK-NOT: memcpy +; CHECK: %[[load:.*]] = load <4 x i32> addrspace(1)* %z +; CHECK-NEXT: %[[gep:.*]] = getelementptr inbounds <4 x i32> addrspace(1)* %z, i64 0, i64 2 +; CHECK-NEXT: %[[element_load:.*]] = load i32 addrspace(1)* %[[gep]] +; CHECK-NEXT: %[[insert:.*]] = insertelement <4 x i32> %x, i32 %[[element_load]], i32 2 +; CHECK-NEXT: extractelement <4 x i32> %[[insert]], i32 2 +; CHECK-NEXT: extractelement <4 x i32> %[[load]], i32 3 +; CHECK-NEXT: extractelement <4 x i32> %[[load]], i32 0 + + %tmp4 = add i32 %tmp1, %tmp2 + %tmp5 = add i32 %tmp3, %tmp4 + ret i32 %tmp5 +; CHECK-NEXT: add +; CHECK-NEXT: add +; CHECK-NEXT: ret +} + define i32 @test5(<4 x i32> %x, <4 x i32> %y, <4 x i32>* %z) { ; CHECK-LABEL: @test5( ; The same as the above, but with reversed source and destination for the diff --git a/test/Transforms/SampleProfile/Inputs/bad_discriminator_value.prof b/test/Transforms/SampleProfile/Inputs/bad_discriminator_value.prof new file mode 100644 index 000000000000..cc7f0d4f2773 --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/bad_discriminator_value.prof @@ -0,0 +1,2 @@ +empty:100:0 +1.-3: 10 diff --git a/test/Transforms/SampleProfile/Inputs/bad_fn_header.prof b/test/Transforms/SampleProfile/Inputs/bad_fn_header.prof new file mode 100644 index 000000000000..abcb0ba38415 --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/bad_fn_header.prof @@ -0,0 +1,3 @@ +3empty:100:BAD +0: 0 +1: 100 diff --git a/test/Transforms/SampleProfile/Inputs/bad_line_values.prof b/test/Transforms/SampleProfile/Inputs/bad_line_values.prof new file mode 100644 index 000000000000..61ba7c01591e --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/bad_line_values.prof @@ -0,0 +1,2 @@ +empty:100:0 +-1: 10 diff --git a/test/Transforms/SampleProfile/Inputs/bad_mangle.prof b/test/Transforms/SampleProfile/Inputs/bad_mangle.prof new file mode 100644 index 000000000000..50fe86119b71 --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/bad_mangle.prof @@ -0,0 +1,3 @@ +double convert<std::string, float>(float):2909472:181842 +0: 181842 +1: 181842 diff --git a/test/Transforms/SampleProfile/Inputs/bad_sample_line.prof b/test/Transforms/SampleProfile/Inputs/bad_sample_line.prof new file mode 100644 index 000000000000..038c45f77e30 --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/bad_sample_line.prof @@ -0,0 +1,3 @@ +empty:100:0 +0: 0 +1: BAD diff --git a/test/Transforms/SampleProfile/Inputs/bad_samples.prof b/test/Transforms/SampleProfile/Inputs/bad_samples.prof new file mode 100644 index 000000000000..a121d8c1ac40 --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/bad_samples.prof @@ -0,0 +1,2 @@ +empty:100:0 +1.3: -10 diff --git a/test/Transforms/SampleProfile/Inputs/branch.prof b/test/Transforms/SampleProfile/Inputs/branch.prof index d19894d428ce..cd1cb5b1f16b 100644 --- a/test/Transforms/SampleProfile/Inputs/branch.prof +++ b/test/Transforms/SampleProfile/Inputs/branch.prof @@ -1,7 +1,4 @@ -symbol table -1 -main -main:15680:0:7 +main:15680:0 0: 0 4: 0 7: 0 diff --git a/test/Transforms/SampleProfile/Inputs/calls.prof b/test/Transforms/SampleProfile/Inputs/calls.prof new file mode 100644 index 000000000000..57d3887dfb65 --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/calls.prof @@ -0,0 +1,10 @@ +_Z3sumii:105580:5279 +0: 5279 +1: 5279 +2: 5279 +main:225715:0 +2.1: 5553 +3: 5391 +# This indicates that at line 3 of this function, the 'then' branch +# of the conditional is taken (discriminator '1'). +3.1: 5752 _Z3sumii:5860 diff --git a/test/Transforms/SampleProfile/Inputs/discriminator.prof b/test/Transforms/SampleProfile/Inputs/discriminator.prof new file mode 100644 index 000000000000..a6bcbc511a16 --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/discriminator.prof @@ -0,0 +1,8 @@ +foo:1000:0 +1: 1 +2: 1 +2.1: 100 +3: 100 +3.1: 5 +4: 100 +5: 1 diff --git a/test/Transforms/SampleProfile/Inputs/propagate.prof b/test/Transforms/SampleProfile/Inputs/propagate.prof new file mode 100644 index 000000000000..b28609be66c1 --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/propagate.prof @@ -0,0 +1,17 @@ +_Z3fooiil:58139:0 +0: 0 +1: 0 +2: 0 +4: 1 +5: 10 +6: 0 +7: 5 +8: 3 +9: 0 +10: 0 +11: 6339 +12: 16191 +13: 8141 +16: 1 +18: 0 +19: 0 diff --git a/test/Transforms/SampleProfile/Inputs/syntax.prof b/test/Transforms/SampleProfile/Inputs/syntax.prof new file mode 100644 index 000000000000..f3738912a9dc --- /dev/null +++ b/test/Transforms/SampleProfile/Inputs/syntax.prof @@ -0,0 +1,3 @@ +empty:100:0 +0: 0 +1: 100 diff --git a/test/Transforms/SampleProfile/branch.ll b/test/Transforms/SampleProfile/branch.ll index 516762763d7b..65f1f1769934 100644 --- a/test/Transforms/SampleProfile/branch.ll +++ b/test/Transforms/SampleProfile/branch.ll @@ -46,8 +46,8 @@ if.end: ; preds = %entry tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !17), !dbg !30 %cmp1 = icmp sgt i32 %call, 100, !dbg !35 br i1 %cmp1, label %for.body, label %if.end6, !dbg !35 -; CHECK: edge if.end -> for.body probability is 2243 / 2244 = 99.9554% [HOT edge] -; CHECK: edge if.end -> if.end6 probability is 1 / 2244 = 0.0445633% +; CHECK: edge if.end -> for.body probability is 1 / 2 = 50% +; CHECK: edge if.end -> if.end6 probability is 1 / 2 = 50% for.body: ; preds = %if.end, %for.body %u.016 = phi i32 [ %inc, %for.body ], [ 0, %if.end ] @@ -65,8 +65,8 @@ for.body: ; preds = %if.end, %for.body tail call void @llvm.dbg.value(metadata !{i32 %inc}, i64 0, metadata !21), !dbg !38 %exitcond = icmp eq i32 %inc, %call, !dbg !38 br i1 %exitcond, label %if.end6, label %for.body, !dbg !38 -; CHECK: edge for.body -> if.end6 probability is 1 / 2244 = 0.0445633% -; CHECK: edge for.body -> for.body probability is 2243 / 2244 = 99.9554% [HOT edge] +; CHECK: edge for.body -> if.end6 probability is 1 / 10227 = 0.00977804 +; CHECK: edge for.body -> for.body probability is 10226 / 10227 = 99.9902% [HOT edge] if.end6: ; preds = %for.body, %if.end %result.0 = phi double [ 0.000000e+00, %if.end ], [ %sub, %for.body ] @@ -117,17 +117,17 @@ attributes #4 = { nounwind readonly } !16 = metadata !{i32 786468, null, null, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float] !17 = metadata !{i32 786688, metadata !4, metadata !"limit", metadata !5, i32 8, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [limit] [line 8] !18 = metadata !{i32 786688, metadata !19, metadata !"s", metadata !5, i32 10, metadata !16, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [s] [line 10] -!19 = metadata !{i32 786443, metadata !1, metadata !20, i32 9, i32 0, i32 2} ; [ DW_TAG_lexical_block ] [./branch.cc] -!20 = metadata !{i32 786443, metadata !1, metadata !4, i32 9, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [./branch.cc] +!19 = metadata !{i32 786443, metadata !1, metadata !20, i32 9, i32 0, i32 0, i32 2} ; [ DW_TAG_lexical_block ] [./branch.cc] +!20 = metadata !{i32 786443, metadata !1, metadata !4, i32 9, i32 0, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [./branch.cc] !21 = metadata !{i32 786688, metadata !22, metadata !"u", metadata !5, i32 11, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [u] [line 11] -!22 = metadata !{i32 786443, metadata !1, metadata !19, i32 11, i32 0, i32 3} ; [ DW_TAG_lexical_block ] [./branch.cc] +!22 = metadata !{i32 786443, metadata !1, metadata !19, i32 11, i32 0, i32 0, i32 3} ; [ DW_TAG_lexical_block ] [./branch.cc] !23 = metadata !{i32 786688, metadata !24, metadata !"x", metadata !5, i32 12, metadata !16, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [x] [line 12] -!24 = metadata !{i32 786443, metadata !1, metadata !22, i32 11, i32 0, i32 4} ; [ DW_TAG_lexical_block ] [./branch.cc] +!24 = metadata !{i32 786443, metadata !1, metadata !22, i32 11, i32 0, i32 0, i32 4} ; [ DW_TAG_lexical_block ] [./branch.cc] !25 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} !26 = metadata !{metadata !"clang version 3.4 (trunk 192896) (llvm/trunk 192895)"} !27 = metadata !{i32 4, i32 0, metadata !4, null} !28 = metadata !{i32 5, i32 0, metadata !29, null} -!29 = metadata !{i32 786443, metadata !1, metadata !4, i32 5, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [./branch.cc] +!29 = metadata !{i32 786443, metadata !1, metadata !4, i32 5, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [./branch.cc] !30 = metadata !{i32 8, i32 0, metadata !4, null} ; [ DW_TAG_imported_declaration ] !31 = metadata !{metadata !32, metadata !32, i64 0} !32 = metadata !{metadata !"any pointer", metadata !33, i64 0} diff --git a/test/Transforms/SampleProfile/calls.ll b/test/Transforms/SampleProfile/calls.ll new file mode 100644 index 000000000000..381be8714eb6 --- /dev/null +++ b/test/Transforms/SampleProfile/calls.ll @@ -0,0 +1,116 @@ +; RUN: opt < %s -sample-profile -sample-profile-file=%S/Inputs/calls.prof | opt -analyze -branch-prob | FileCheck %s + +; Original C++ test case +; +; #include <stdio.h> +; +; int sum(int x, int y) { +; return x + y; +; } +; +; int main() { +; int s, i = 0; +; while (i++ < 20000 * 20000) +; if (i != 100) s = sum(i, s); else s = 30; +; printf("sum is %d\n", s); +; return 0; +; } + +@.str = private unnamed_addr constant [11 x i8] c"sum is %d\0A\00", align 1 + +; Function Attrs: nounwind uwtable +define i32 @_Z3sumii(i32 %x, i32 %y) { +entry: + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + store i32 %y, i32* %y.addr, align 4 + %0 = load i32* %x.addr, align 4, !dbg !11 + %1 = load i32* %y.addr, align 4, !dbg !11 + %add = add nsw i32 %0, %1, !dbg !11 + ret i32 %add, !dbg !11 +} + +; Function Attrs: uwtable +define i32 @main() { +entry: + %retval = alloca i32, align 4 + %s = alloca i32, align 4 + %i = alloca i32, align 4 + store i32 0, i32* %retval + store i32 0, i32* %i, align 4, !dbg !12 + br label %while.cond, !dbg !13 + +while.cond: ; preds = %if.end, %entry + %0 = load i32* %i, align 4, !dbg !14 + %inc = add nsw i32 %0, 1, !dbg !14 + store i32 %inc, i32* %i, align 4, !dbg !14 + %cmp = icmp slt i32 %0, 400000000, !dbg !14 + br i1 %cmp, label %while.body, label %while.end, !dbg !14 +; CHECK: edge while.cond -> while.body probability is 5391 / 5392 = 99.9815% [HOT edge] +; CHECK: edge while.cond -> while.end probability is 1 / 5392 = 0.018546% + +while.body: ; preds = %while.cond + %1 = load i32* %i, align 4, !dbg !16 + %cmp1 = icmp ne i32 %1, 100, !dbg !16 + br i1 %cmp1, label %if.then, label %if.else, !dbg !16 +; Without discriminator information, the profiler used to think that +; both branches out of while.body had the same weight. In reality, +; the edge while.body->if.then is taken most of the time. +; +; CHECK: edge while.body -> if.then probability is 5752 / 5753 = 99.9826% [HOT edge] +; CHECK: edge while.body -> if.else probability is 1 / 5753 = 0.0173822% + + +if.then: ; preds = %while.body + %2 = load i32* %i, align 4, !dbg !18 + %3 = load i32* %s, align 4, !dbg !18 + %call = call i32 @_Z3sumii(i32 %2, i32 %3), !dbg !18 + store i32 %call, i32* %s, align 4, !dbg !18 + br label %if.end, !dbg !18 + +if.else: ; preds = %while.body + store i32 30, i32* %s, align 4, !dbg !20 + br label %if.end + +if.end: ; preds = %if.else, %if.then + br label %while.cond, !dbg !22 + +while.end: ; preds = %while.cond + %4 = load i32* %s, align 4, !dbg !24 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i32 %4), !dbg !24 + ret i32 0, !dbg !25 +} + +declare i32 @printf(i8*, ...) #2 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!8, !9} +!llvm.ident = !{!10} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [./calls.cc] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !"calls.cc", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4, metadata !7} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"sum", metadata !"sum", metadata !"", i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i32)* @_Z3sumii, null, null, metadata !2, i32 3} ; [ DW_TAG_subprogram ] [line 3] [def] [sum] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [./calls.cc] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 7, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !2, i32 7} ; [ DW_TAG_subprogram ] [line 7] [def] [main] +!8 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!9 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!10 = metadata !{metadata !"clang version 3.5 "} +!11 = metadata !{i32 4, i32 0, metadata !4, null} +!12 = metadata !{i32 8, i32 0, metadata !7, null} ; [ DW_TAG_imported_declaration ] +!13 = metadata !{i32 9, i32 0, metadata !7, null} +!14 = metadata !{i32 9, i32 0, metadata !15, null} +!15 = metadata !{i32 786443, metadata !1, metadata !7, i32 9, i32 0, i32 1, i32 1} ; [ DW_TAG_lexical_block ] [./calls.cc] +!16 = metadata !{i32 10, i32 0, metadata !17, null} +!17 = metadata !{i32 786443, metadata !1, metadata !7, i32 10, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [./calls.cc] +!18 = metadata !{i32 10, i32 0, metadata !19, null} +!19 = metadata !{i32 786443, metadata !1, metadata !17, i32 10, i32 0, i32 1, i32 2} ; [ DW_TAG_lexical_block ] [./calls.cc] +!20 = metadata !{i32 10, i32 0, metadata !21, null} +!21 = metadata !{i32 786443, metadata !1, metadata !17, i32 10, i32 0, i32 2, i32 3} ; [ DW_TAG_lexical_block ] [./calls.cc] +!22 = metadata !{i32 10, i32 0, metadata !23, null} +!23 = metadata !{i32 786443, metadata !1, metadata !17, i32 10, i32 0, i32 3, i32 4} ; [ DW_TAG_lexical_block ] [./calls.cc] +!24 = metadata !{i32 11, i32 0, metadata !7, null} +!25 = metadata !{i32 12, i32 0, metadata !7, null} diff --git a/test/Transforms/SampleProfile/discriminator.ll b/test/Transforms/SampleProfile/discriminator.ll new file mode 100644 index 000000000000..0f773a541a4e --- /dev/null +++ b/test/Transforms/SampleProfile/discriminator.ll @@ -0,0 +1,90 @@ +; RUN: opt < %s -sample-profile -sample-profile-file=%S/Inputs/discriminator.prof | opt -analyze -branch-prob | FileCheck %s + +; Original code +; +; 1 int foo(int i) { +; 2 int x = 0; +; 3 while (i < 100) { +; 4 if (i < 5) x--; +; 5 i++; +; 6 } +; 7 return x; +; 8 } +; +; In this test, if the loop is executed 100 times, the decrement operation +; at line 4 should only execute 5 times. This is reflected in the profile +; data for line offset 3. In Inputs/discriminator.prof, we have: +; +; 3: 100 +; 3.1: 5 +; +; This means that the predicate 'i < 5' (line 3) is executed 100 times, +; but the then branch (line 3.1) is only executed 5 times. + +define i32 @foo(i32 %i) #0 { +; CHECK: Printing analysis 'Branch Probability Analysis' for function 'foo': +entry: + %i.addr = alloca i32, align 4 + %x = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + store i32 0, i32* %x, align 4, !dbg !10 + br label %while.cond, !dbg !11 + +while.cond: ; preds = %if.end, %entry + %0 = load i32* %i.addr, align 4, !dbg !12 + %cmp = icmp slt i32 %0, 100, !dbg !12 + br i1 %cmp, label %while.body, label %while.end, !dbg !12 +; CHECK: edge while.cond -> while.body probability is 100 / 101 = 99.0099% [HOT edge] +; CHECK: edge while.cond -> while.end probability is 1 / 101 = 0.990099% + +while.body: ; preds = %while.cond + %1 = load i32* %i.addr, align 4, !dbg !14 + %cmp1 = icmp slt i32 %1, 50, !dbg !14 + br i1 %cmp1, label %if.then, label %if.end, !dbg !14 +; CHECK: edge while.body -> if.then probability is 5 / 100 = 5% +; CHECK: edge while.body -> if.end probability is 95 / 100 = 95% [HOT edge] + +if.then: ; preds = %while.body + %2 = load i32* %x, align 4, !dbg !17 + %dec = add nsw i32 %2, -1, !dbg !17 + store i32 %dec, i32* %x, align 4, !dbg !17 + br label %if.end, !dbg !17 + +if.end: ; preds = %if.then, %while.body + %3 = load i32* %i.addr, align 4, !dbg !19 + %inc = add nsw i32 %3, 1, !dbg !19 + store i32 %inc, i32* %i.addr, align 4, !dbg !19 + br label %while.cond, !dbg !20 + +while.end: ; preds = %while.cond + %4 = load i32* %x, align 4, !dbg !21 + ret i32 %4, !dbg !21 +} + + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} +!llvm.ident = !{!9} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [discriminator.c] [DW_LANG_C99] +!1 = metadata !{metadata !"discriminator.c", metadata !"."} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [discriminator.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!8 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!9 = metadata !{metadata !"clang version 3.5 "} +!10 = metadata !{i32 2, i32 0, metadata !4, null} +!11 = metadata !{i32 3, i32 0, metadata !4, null} +!12 = metadata !{i32 3, i32 0, metadata !13, null} +!13 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 0, i32 1, i32 2} ; [ DW_TAG_lexical_block ] [discriminator.c] +!14 = metadata !{i32 4, i32 0, metadata !15, null} +!15 = metadata !{i32 786443, metadata !1, metadata !16, i32 4, i32 0, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [discriminator.c] +!16 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [discriminator.c] +!17 = metadata !{i32 4, i32 0, metadata !18, null} +!18 = metadata !{i32 786443, metadata !1, metadata !15, i32 4, i32 0, i32 1, i32 3} ; [ DW_TAG_lexical_block ] [discriminator.c] +!19 = metadata !{i32 5, i32 0, metadata !16, null} +!20 = metadata !{i32 6, i32 0, metadata !16, null} +!21 = metadata !{i32 7, i32 0, metadata !4, null} diff --git a/test/Transforms/SampleProfile/propagate.ll b/test/Transforms/SampleProfile/propagate.ll new file mode 100644 index 000000000000..939361b23703 --- /dev/null +++ b/test/Transforms/SampleProfile/propagate.ll @@ -0,0 +1,243 @@ +; RUN: opt < %s -sample-profile -sample-profile-file=%S/Inputs/propagate.prof | opt -analyze -branch-prob | FileCheck %s + +; Original C++ code for this test case: +; +; #include <stdio.h> +; +; long foo(int x, int y, long N) { +; if (x < y) { +; return y - x; +; } else { +; for (long i = 0; i < N; i++) { +; if (i > N / 3) +; x--; +; if (i > N / 4) { +; y++; +; x += 3; +; } else { +; for (unsigned j = 0; j < i; j++) { +; x += j; +; y -= 3; +; } +; } +; } +; } +; return y * x; +; } +; +; int main() { +; int x = 5678; +; int y = 1234; +; long N = 999999; +; printf("foo(%d, %d, %ld) = %ld\n", x, y, N, foo(x, y, N)); +; return 0; +; } + +; ModuleID = 'propagate.cc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@.str = private unnamed_addr constant [24 x i8] c"foo(%d, %d, %ld) = %ld\0A\00", align 1 + +; Function Attrs: nounwind uwtable +define i64 @_Z3fooiil(i32 %x, i32 %y, i64 %N) #0 { +entry: + %retval = alloca i64, align 8 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + %N.addr = alloca i64, align 8 + %i = alloca i64, align 8 + %j = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + store i32 %y, i32* %y.addr, align 4 + store i64 %N, i64* %N.addr, align 8 + %0 = load i32* %x.addr, align 4, !dbg !11 + %1 = load i32* %y.addr, align 4, !dbg !11 + %cmp = icmp slt i32 %0, %1, !dbg !11 + br i1 %cmp, label %if.then, label %if.else, !dbg !11 + +if.then: ; preds = %entry + %2 = load i32* %y.addr, align 4, !dbg !13 + %3 = load i32* %x.addr, align 4, !dbg !13 + %sub = sub nsw i32 %2, %3, !dbg !13 + %conv = sext i32 %sub to i64, !dbg !13 + store i64 %conv, i64* %retval, !dbg !13 + br label %return, !dbg !13 + +if.else: ; preds = %entry + store i64 0, i64* %i, align 8, !dbg !15 + br label %for.cond, !dbg !15 + +for.cond: ; preds = %for.inc16, %if.else + %4 = load i64* %i, align 8, !dbg !15 + %5 = load i64* %N.addr, align 8, !dbg !15 + %cmp1 = icmp slt i64 %4, %5, !dbg !15 + br i1 %cmp1, label %for.body, label %for.end18, !dbg !15 +; CHECK: edge for.cond -> for.body probability is 10 / 11 = 90.9091% [HOT edge] +; CHECK: edge for.cond -> for.end18 probability is 1 / 11 = 9.09091% + +for.body: ; preds = %for.cond + %6 = load i64* %i, align 8, !dbg !18 + %7 = load i64* %N.addr, align 8, !dbg !18 + %div = sdiv i64 %7, 3, !dbg !18 + %cmp2 = icmp sgt i64 %6, %div, !dbg !18 + br i1 %cmp2, label %if.then3, label %if.end, !dbg !18 +; CHECK: edge for.body -> if.then3 probability is 1 / 5 = 20% +; CHECK: edge for.body -> if.end probability is 4 / 5 = 80% + +if.then3: ; preds = %for.body + %8 = load i32* %x.addr, align 4, !dbg !21 + %dec = add nsw i32 %8, -1, !dbg !21 + store i32 %dec, i32* %x.addr, align 4, !dbg !21 + br label %if.end, !dbg !21 + +if.end: ; preds = %if.then3, %for.body + %9 = load i64* %i, align 8, !dbg !22 + %10 = load i64* %N.addr, align 8, !dbg !22 + %div4 = sdiv i64 %10, 4, !dbg !22 + %cmp5 = icmp sgt i64 %9, %div4, !dbg !22 + br i1 %cmp5, label %if.then6, label %if.else7, !dbg !22 +; CHECK: edge if.end -> if.then6 probability is 3 / 6342 = 0.0473037% +; CHECK: edge if.end -> if.else7 probability is 6339 / 6342 = 99.9527% [HOT edge] + +if.then6: ; preds = %if.end + %11 = load i32* %y.addr, align 4, !dbg !24 + %inc = add nsw i32 %11, 1, !dbg !24 + store i32 %inc, i32* %y.addr, align 4, !dbg !24 + %12 = load i32* %x.addr, align 4, !dbg !26 + %add = add nsw i32 %12, 3, !dbg !26 + store i32 %add, i32* %x.addr, align 4, !dbg !26 + br label %if.end15, !dbg !27 + +if.else7: ; preds = %if.end + store i32 0, i32* %j, align 4, !dbg !28 + br label %for.cond8, !dbg !28 + +for.cond8: ; preds = %for.inc, %if.else7 + %13 = load i32* %j, align 4, !dbg !28 + %conv9 = zext i32 %13 to i64, !dbg !28 + %14 = load i64* %i, align 8, !dbg !28 + %cmp10 = icmp slt i64 %conv9, %14, !dbg !28 + br i1 %cmp10, label %for.body11, label %for.end, !dbg !28 +; CHECK: edge for.cond8 -> for.body11 probability is 16191 / 16192 = 99.9938% [HOT edge] +; CHECK: edge for.cond8 -> for.end probability is 1 / 16192 = 0.00617589% + +for.body11: ; preds = %for.cond8 + %15 = load i32* %j, align 4, !dbg !31 + %16 = load i32* %x.addr, align 4, !dbg !31 + %add12 = add i32 %16, %15, !dbg !31 + store i32 %add12, i32* %x.addr, align 4, !dbg !31 + %17 = load i32* %y.addr, align 4, !dbg !33 + %sub13 = sub nsw i32 %17, 3, !dbg !33 + store i32 %sub13, i32* %y.addr, align 4, !dbg !33 + br label %for.inc, !dbg !34 + +for.inc: ; preds = %for.body11 + %18 = load i32* %j, align 4, !dbg !28 + %inc14 = add i32 %18, 1, !dbg !28 + store i32 %inc14, i32* %j, align 4, !dbg !28 + br label %for.cond8, !dbg !28 + +for.end: ; preds = %for.cond8 + br label %if.end15 + +if.end15: ; preds = %for.end, %if.then6 + br label %for.inc16, !dbg !35 + +for.inc16: ; preds = %if.end15 + %19 = load i64* %i, align 8, !dbg !15 + %inc17 = add nsw i64 %19, 1, !dbg !15 + store i64 %inc17, i64* %i, align 8, !dbg !15 + br label %for.cond, !dbg !15 + +for.end18: ; preds = %for.cond + br label %if.end19 + +if.end19: ; preds = %for.end18 + %20 = load i32* %y.addr, align 4, !dbg !36 + %21 = load i32* %x.addr, align 4, !dbg !36 + %mul = mul nsw i32 %20, %21, !dbg !36 + %conv20 = sext i32 %mul to i64, !dbg !36 + store i64 %conv20, i64* %retval, !dbg !36 + br label %return, !dbg !36 + +return: ; preds = %if.end19, %if.then + %22 = load i64* %retval, !dbg !37 + ret i64 %22, !dbg !37 +} + +; Function Attrs: uwtable +define i32 @main() #1 { +entry: + %retval = alloca i32, align 4 + %x = alloca i32, align 4 + %y = alloca i32, align 4 + %N = alloca i64, align 8 + store i32 0, i32* %retval + store i32 5678, i32* %x, align 4, !dbg !38 + store i32 1234, i32* %y, align 4, !dbg !39 + store i64 999999, i64* %N, align 8, !dbg !40 + %0 = load i32* %x, align 4, !dbg !41 + %1 = load i32* %y, align 4, !dbg !41 + %2 = load i64* %N, align 8, !dbg !41 + %3 = load i32* %x, align 4, !dbg !41 + %4 = load i32* %y, align 4, !dbg !41 + %5 = load i64* %N, align 8, !dbg !41 + %call = call i64 @_Z3fooiil(i32 %3, i32 %4, i64 %5), !dbg !41 + %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([24 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i64 %2, i64 %call), !dbg !41 + ret i32 0, !dbg !42 +} + +declare i32 @printf(i8*, ...) #2 + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!8, !9} +!llvm.ident = !{!10} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.5 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [propagate.cc] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !"propagate.cc", metadata !"."} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4, metadata !7} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i64 (i32, i32, i64)* @_Z3fooiil, null, null, metadata !2, i32 3} ; [ DW_TAG_subprogram ] [line 3] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [propagate.cc] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 24, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !2, i32 24} ; [ DW_TAG_subprogram ] [line 24] [def] [main] +!8 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!9 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!10 = metadata !{metadata !"clang version 3.5 "} +!11 = metadata !{i32 4, i32 0, metadata !12, null} +!12 = metadata !{i32 786443, metadata !1, metadata !4, i32 4, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [propagate.cc] +!13 = metadata !{i32 5, i32 0, metadata !14, null} +!14 = metadata !{i32 786443, metadata !1, metadata !12, i32 4, i32 0, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [propagate.cc] +!15 = metadata !{i32 7, i32 0, metadata !16, null} +!16 = metadata !{i32 786443, metadata !1, metadata !17, i32 7, i32 0, i32 0, i32 3} ; [ DW_TAG_lexical_block ] [propagate.cc] +!17 = metadata !{i32 786443, metadata !1, metadata !12, i32 6, i32 0, i32 0, i32 2} ; [ DW_TAG_lexical_block ] [propagate.cc] +!18 = metadata !{i32 8, i32 0, metadata !19, null} ; [ DW_TAG_imported_declaration ] +!19 = metadata !{i32 786443, metadata !1, metadata !20, i32 8, i32 0, i32 0, i32 5} ; [ DW_TAG_lexical_block ] [propagate.cc] +!20 = metadata !{i32 786443, metadata !1, metadata !16, i32 7, i32 0, i32 0, i32 4} ; [ DW_TAG_lexical_block ] [propagate.cc] +!21 = metadata !{i32 9, i32 0, metadata !19, null} +!22 = metadata !{i32 10, i32 0, metadata !23, null} +!23 = metadata !{i32 786443, metadata !1, metadata !20, i32 10, i32 0, i32 0, i32 6} ; [ DW_TAG_lexical_block ] [propagate.cc] +!24 = metadata !{i32 11, i32 0, metadata !25, null} +!25 = metadata !{i32 786443, metadata !1, metadata !23, i32 10, i32 0, i32 0, i32 7} ; [ DW_TAG_lexical_block ] [propagate.cc] +!26 = metadata !{i32 12, i32 0, metadata !25, null} +!27 = metadata !{i32 13, i32 0, metadata !25, null} +!28 = metadata !{i32 14, i32 0, metadata !29, null} +!29 = metadata !{i32 786443, metadata !1, metadata !30, i32 14, i32 0, i32 0, i32 9} ; [ DW_TAG_lexical_block ] [propagate.cc] +!30 = metadata !{i32 786443, metadata !1, metadata !23, i32 13, i32 0, i32 0, i32 8} ; [ DW_TAG_lexical_block ] [propagate.cc] +!31 = metadata !{i32 15, i32 0, metadata !32, null} +!32 = metadata !{i32 786443, metadata !1, metadata !29, i32 14, i32 0, i32 0, i32 10} ; [ DW_TAG_lexical_block ] [propagate.cc] +!33 = metadata !{i32 16, i32 0, metadata !32, null} +!34 = metadata !{i32 17, i32 0, metadata !32, null} +!35 = metadata !{i32 19, i32 0, metadata !20, null} +!36 = metadata !{i32 21, i32 0, metadata !4, null} +!37 = metadata !{i32 22, i32 0, metadata !4, null} +!38 = metadata !{i32 25, i32 0, metadata !7, null} +!39 = metadata !{i32 26, i32 0, metadata !7, null} +!40 = metadata !{i32 27, i32 0, metadata !7, null} +!41 = metadata !{i32 28, i32 0, metadata !7, null} +!42 = metadata !{i32 29, i32 0, metadata !7, null} diff --git a/test/Transforms/SampleProfile/syntax.ll b/test/Transforms/SampleProfile/syntax.ll new file mode 100644 index 000000000000..53c65f44239c --- /dev/null +++ b/test/Transforms/SampleProfile/syntax.ll @@ -0,0 +1,20 @@ +; RUN: not opt < %s -sample-profile -sample-profile-file=%S/Inputs/syntax.prof 2>&1 | FileCheck -check-prefix=NO-DEBUG %s +; RUN: not opt < %s -sample-profile -sample-profile-file=missing.prof 2>&1 | FileCheck -check-prefix=MISSING-FILE %s +; RUN: not opt < %s -sample-profile -sample-profile-file=%S/Inputs/bad_fn_header.prof 2>&1 | FileCheck -check-prefix=BAD-FN-HEADER %s +; RUN: not opt < %s -sample-profile -sample-profile-file=%S/Inputs/bad_sample_line.prof 2>&1 | FileCheck -check-prefix=BAD-SAMPLE-LINE %s +; RUN: not opt < %s -sample-profile -sample-profile-file=%S/Inputs/bad_line_values.prof 2>&1 | FileCheck -check-prefix=BAD-LINE-VALUES %s +; RUN: not opt < %s -sample-profile -sample-profile-file=%S/Inputs/bad_discriminator_value.prof 2>&1 | FileCheck -check-prefix=BAD-DISCRIMINATOR-VALUE %s +; RUN: not opt < %s -sample-profile -sample-profile-file=%S/Inputs/bad_samples.prof 2>&1 | FileCheck -check-prefix=BAD-SAMPLES %s +; RUN: opt < %s -sample-profile -sample-profile-file=%S/Inputs/bad_mangle.prof 2>&1 >/dev/null + +define void @empty() { +entry: + ret void +} +; NO-DEBUG: error: No debug information found in function empty +; MISSING-FILE: error: missing.prof: +; BAD-FN-HEADER: error: {{.*}}bad_fn_header.prof:1: Expected 'mangled_name:NUM:NUM', found 3empty:100:BAD +; BAD-SAMPLE-LINE: error: {{.*}}bad_sample_line.prof:3: Expected 'NUM[.NUM]: NUM[ mangled_name:NUM]*', found 1: BAD +; BAD-LINE-VALUES: error: {{.*}}bad_line_values.prof:2: Expected 'mangled_name:NUM:NUM', found -1: 10 +; BAD-DISCRIMINATOR-VALUE: error: {{.*}}bad_discriminator_value.prof:2: Expected 'NUM[.NUM]: NUM[ mangled_name:NUM]*', found 1.-3: 10 +; BAD-SAMPLES: error: {{.*}}bad_samples.prof:2: Expected 'NUM[.NUM]: NUM[ mangled_name:NUM]*', found 1.3: -10 diff --git a/test/Transforms/ScalarRepl/memset-aggregate-byte-leader.ll b/test/Transforms/ScalarRepl/memset-aggregate-byte-leader.ll index 3510dfc24d9a..8ac1d2570a1c 100644 --- a/test/Transforms/ScalarRepl/memset-aggregate-byte-leader.ll +++ b/test/Transforms/ScalarRepl/memset-aggregate-byte-leader.ll @@ -1,6 +1,6 @@ ; PR1226 ; RUN: opt < %s -scalarrepl -S | \ -; RUN: not grep "call void @llvm.memcpy.i32" +; RUN: not grep "call void @llvm.memcpy.p0i8.p0i8.i32" ; RUN: opt < %s -scalarrepl -S | grep getelementptr ; END. @@ -14,10 +14,10 @@ entry: %L = alloca %struct.foo, align 2 ; <%struct.foo*> [#uses=1] %L2 = getelementptr %struct.foo* %L, i32 0, i32 0 ; <i8*> [#uses=2] %tmp13 = getelementptr %struct.foo* %P, i32 0, i32 0 ; <i8*> [#uses=1] - call void @llvm.memcpy.i32( i8* %L2, i8* %tmp13, i32 2, i32 1 ) + call void @llvm.memcpy.p0i8.p0i8.i32( i8* %L2, i8* %tmp13, i32 2, i32 1, i1 false) %tmp5 = load i8* %L2 ; <i8> [#uses=1] %tmp56 = sext i8 %tmp5 to i32 ; <i32> [#uses=1] ret i32 %tmp56 } -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) diff --git a/test/Transforms/ScalarRepl/vector_memcpy.ll b/test/Transforms/ScalarRepl/vector_memcpy.ll index 33e8034f5734..dfba9e2c8074 100644 --- a/test/Transforms/ScalarRepl/vector_memcpy.ll +++ b/test/Transforms/ScalarRepl/vector_memcpy.ll @@ -9,8 +9,7 @@ define <16 x float> @foo(<16 x float> %A) nounwind { store <16 x float> %A, <16 x float>* %tmp %s = bitcast <16 x float>* %tmp to i8* %s2 = bitcast <16 x float>* %tmp2 to i8* - call void @llvm.memcpy.i64(i8* %s2, i8* %s, i64 64, i32 16) - + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %s2, i8* %s, i64 64, i32 16, i1 false) %R = load <16 x float>* %tmp2 ret <16 x float> %R } @@ -19,12 +18,11 @@ define <16 x float> @foo2(<16 x float> %A) nounwind { %tmp2 = alloca <16 x float>, align 16 %s2 = bitcast <16 x float>* %tmp2 to i8* - call void @llvm.memset.i64(i8* %s2, i8 0, i64 64, i32 16) + call void @llvm.memset.p0i8.i64(i8* %s2, i8 0, i64 64, i32 16, i1 false) %R = load <16 x float>* %tmp2 ret <16 x float> %R } - -declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind -declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind diff --git a/test/Transforms/Scalarizer/basic.ll b/test/Transforms/Scalarizer/basic.ll new file mode 100644 index 000000000000..1cfc0dd29017 --- /dev/null +++ b/test/Transforms/Scalarizer/basic.ll @@ -0,0 +1,451 @@ +; RUN: opt %s -scalarizer -scalarize-load-store -dce -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +declare <4 x float> @ext(<4 x float>) +@g = global <4 x float> zeroinitializer + +define void @f1(<4 x float> %init, <4 x float> *%base, i32 %count) { +; CHECK-LABEL: @f1( +; CHECK: entry: +; CHECK: %init.i0 = extractelement <4 x float> %init, i32 0 +; CHECK: %init.i1 = extractelement <4 x float> %init, i32 1 +; CHECK: %init.i2 = extractelement <4 x float> %init, i32 2 +; CHECK: %init.i3 = extractelement <4 x float> %init, i32 3 +; CHECK: br label %loop +; CHECK: loop: +; CHECK: %i = phi i32 [ %count, %entry ], [ %nexti, %loop ] +; CHECK: %acc.i0 = phi float [ %init.i0, %entry ], [ %sel.i0, %loop ] +; CHECK: %acc.i1 = phi float [ %init.i1, %entry ], [ %sel.i1, %loop ] +; CHECK: %acc.i2 = phi float [ %init.i2, %entry ], [ %sel.i2, %loop ] +; CHECK: %acc.i3 = phi float [ %init.i3, %entry ], [ %sel.i3, %loop ] +; CHECK: %nexti = sub i32 %i, 1 +; CHECK: %ptr = getelementptr <4 x float>* %base, i32 %i +; CHECK: %ptr.i0 = bitcast <4 x float>* %ptr to float* +; CHECK: %val.i0 = load float* %ptr.i0, align 16 +; CHECK: %ptr.i1 = getelementptr float* %ptr.i0, i32 1 +; CHECK: %val.i1 = load float* %ptr.i1, align 4 +; CHECK: %ptr.i2 = getelementptr float* %ptr.i0, i32 2 +; CHECK: %val.i2 = load float* %ptr.i2, align 8 +; CHECK: %ptr.i3 = getelementptr float* %ptr.i0, i32 3 +; CHECK: %val.i3 = load float* %ptr.i3, align 4 +; CHECK: %add.i0 = fadd float %val.i0, %val.i2 +; CHECK: %add.i1 = fadd float %val.i1, %val.i3 +; CHECK: %add.i2 = fadd float %acc.i0, %acc.i2 +; CHECK: %add.i3 = fadd float %acc.i1, %acc.i3 +; CHECK: %add.upto0 = insertelement <4 x float> undef, float %add.i0, i32 0 +; CHECK: %add.upto1 = insertelement <4 x float> %add.upto0, float %add.i1, i32 1 +; CHECK: %add.upto2 = insertelement <4 x float> %add.upto1, float %add.i2, i32 2 +; CHECK: %add = insertelement <4 x float> %add.upto2, float %add.i3, i32 3 +; CHECK: %call = call <4 x float> @ext(<4 x float> %add) +; CHECK: %call.i0 = extractelement <4 x float> %call, i32 0 +; CHECK: %cmp.i0 = fcmp ogt float %call.i0, 1.0 +; CHECK: %call.i1 = extractelement <4 x float> %call, i32 1 +; CHECK: %cmp.i1 = fcmp ogt float %call.i1, 2.0 +; CHECK: %call.i2 = extractelement <4 x float> %call, i32 2 +; CHECK: %cmp.i2 = fcmp ogt float %call.i2, 3.0 +; CHECK: %call.i3 = extractelement <4 x float> %call, i32 3 +; CHECK: %cmp.i3 = fcmp ogt float %call.i3, 4.0 +; CHECK: %sel.i0 = select i1 %cmp.i0, float %call.i0, float 5.0 +; CHECK: %sel.i1 = select i1 %cmp.i1, float %call.i1, float 6.0 +; CHECK: %sel.i2 = select i1 %cmp.i2, float %call.i2, float 7.0 +; CHECK: %sel.i3 = select i1 %cmp.i3, float %call.i3, float 8.0 +; CHECK: store float %sel.i0, float* %ptr.i0 +; CHECK: store float %sel.i1, float* %ptr.i1 +; CHECK: store float %sel.i2, float* %ptr.i2 +; CHECK: store float %sel.i3, float* %ptr.i3 +; CHECK: %test = icmp eq i32 %nexti, 0 +; CHECK: br i1 %test, label %loop, label %exit +; CHECK: exit: +; CHECK: ret void +entry: + br label %loop + +loop: + %i = phi i32 [ %count, %entry ], [ %nexti, %loop ] + %acc = phi <4 x float> [ %init, %entry ], [ %sel, %loop ] + %nexti = sub i32 %i, 1 + + %ptr = getelementptr <4 x float> *%base, i32 %i + %val = load <4 x float> *%ptr + %dval = bitcast <4 x float> %val to <2 x double> + %dacc = bitcast <4 x float> %acc to <2 x double> + %shuffle1 = shufflevector <2 x double> %dval, <2 x double> %dacc, + <2 x i32> <i32 0, i32 2> + %shuffle2 = shufflevector <2 x double> %dval, <2 x double> %dacc, + <2 x i32> <i32 1, i32 3> + %f1 = bitcast <2 x double> %shuffle1 to <4 x float> + %f2 = bitcast <2 x double> %shuffle2 to <4 x float> + %add = fadd <4 x float> %f1, %f2 + %call = call <4 x float> @ext(<4 x float> %add) + %cmp = fcmp ogt <4 x float> %call, + <float 1.0, float 2.0, float 3.0, float 4.0> + %sel = select <4 x i1> %cmp, <4 x float> %call, + <4 x float> <float 5.0, float 6.0, float 7.0, float 8.0> + store <4 x float> %sel, <4 x float> *%ptr + + %test = icmp eq i32 %nexti, 0 + br i1 %test, label %loop, label %exit + +exit: + ret void +} + +define void @f2(<4 x i32> %init, <4 x i8> *%base, i32 %count) { +; CHECK-LABEL: define void @f2(<4 x i32> %init, <4 x i8>* %base, i32 %count) { +; CHECK: entry: +; CHECK: %init.i0 = extractelement <4 x i32> %init, i32 0 +; CHECK: %init.i1 = extractelement <4 x i32> %init, i32 1 +; CHECK: %init.i2 = extractelement <4 x i32> %init, i32 2 +; CHECK: %init.i3 = extractelement <4 x i32> %init, i32 3 +; CHECK: br label %loop +; CHECK: loop: +; CHECK: %i = phi i32 [ %count, %entry ], [ %nexti, %loop ] +; CHECK: %acc.i0 = phi i32 [ %init.i0, %entry ], [ %sel.i0, %loop ] +; CHECK: %acc.i1 = phi i32 [ %init.i1, %entry ], [ %sel.i1, %loop ] +; CHECK: %acc.i2 = phi i32 [ %init.i2, %entry ], [ %sel.i2, %loop ] +; CHECK: %acc.i3 = phi i32 [ %init.i3, %entry ], [ %sel.i3, %loop ] +; CHECK: %nexti = sub i32 %i, 1 +; CHECK: %ptr = getelementptr <4 x i8>* %base, i32 %i +; CHECK: %ptr.i0 = bitcast <4 x i8>* %ptr to i8* +; CHECK: %val.i0 = load i8* %ptr.i0, align 4 +; CHECK: %ptr.i1 = getelementptr i8* %ptr.i0, i32 1 +; CHECK: %val.i1 = load i8* %ptr.i1, align 1 +; CHECK: %ptr.i2 = getelementptr i8* %ptr.i0, i32 2 +; CHECK: %val.i2 = load i8* %ptr.i2, align 2 +; CHECK: %ptr.i3 = getelementptr i8* %ptr.i0, i32 3 +; CHECK: %val.i3 = load i8* %ptr.i3, align 1 +; CHECK: %ext.i0 = sext i8 %val.i0 to i32 +; CHECK: %ext.i1 = sext i8 %val.i1 to i32 +; CHECK: %ext.i2 = sext i8 %val.i2 to i32 +; CHECK: %ext.i3 = sext i8 %val.i3 to i32 +; CHECK: %add.i0 = add i32 %ext.i0, %acc.i0 +; CHECK: %add.i1 = add i32 %ext.i1, %acc.i1 +; CHECK: %add.i2 = add i32 %ext.i2, %acc.i2 +; CHECK: %add.i3 = add i32 %ext.i3, %acc.i3 +; CHECK: %cmp.i0 = icmp slt i32 %add.i0, -10 +; CHECK: %cmp.i1 = icmp slt i32 %add.i1, -11 +; CHECK: %cmp.i2 = icmp slt i32 %add.i2, -12 +; CHECK: %cmp.i3 = icmp slt i32 %add.i3, -13 +; CHECK: %sel.i0 = select i1 %cmp.i0, i32 %add.i0, i32 %i +; CHECK: %sel.i1 = select i1 %cmp.i1, i32 %add.i1, i32 %i +; CHECK: %sel.i2 = select i1 %cmp.i2, i32 %add.i2, i32 %i +; CHECK: %sel.i3 = select i1 %cmp.i3, i32 %add.i3, i32 %i +; CHECK: %trunc.i0 = trunc i32 %sel.i0 to i8 +; CHECK: %trunc.i1 = trunc i32 %sel.i1 to i8 +; CHECK: %trunc.i2 = trunc i32 %sel.i2 to i8 +; CHECK: %trunc.i3 = trunc i32 %sel.i3 to i8 +; CHECK: store i8 %trunc.i0, i8* %ptr.i0, align 4 +; CHECK: store i8 %trunc.i1, i8* %ptr.i1, align 1 +; CHECK: store i8 %trunc.i2, i8* %ptr.i2, align 2 +; CHECK: store i8 %trunc.i3, i8* %ptr.i3, align 1 +; CHECK: %test = icmp eq i32 %nexti, 0 +; CHECK: br i1 %test, label %loop, label %exit +; CHECK: exit: +; CHECK: ret void +entry: + br label %loop + +loop: + %i = phi i32 [ %count, %entry ], [ %nexti, %loop ] + %acc = phi <4 x i32> [ %init, %entry ], [ %sel, %loop ] + %nexti = sub i32 %i, 1 + + %ptr = getelementptr <4 x i8> *%base, i32 %i + %val = load <4 x i8> *%ptr + %ext = sext <4 x i8> %val to <4 x i32> + %add = add <4 x i32> %ext, %acc + %cmp = icmp slt <4 x i32> %add, <i32 -10, i32 -11, i32 -12, i32 -13> + %single = insertelement <4 x i32> undef, i32 %i, i32 0 + %limit = shufflevector <4 x i32> %single, <4 x i32> undef, + <4 x i32> zeroinitializer + %sel = select <4 x i1> %cmp, <4 x i32> %add, <4 x i32> %limit + %trunc = trunc <4 x i32> %sel to <4 x i8> + store <4 x i8> %trunc, <4 x i8> *%ptr + + %test = icmp eq i32 %nexti, 0 + br i1 %test, label %loop, label %exit + +exit: + ret void +} + +; Check that !tbaa information is preserved. +define void @f3(<4 x i32> *%src, <4 x i32> *%dst) { +; CHECK-LABEL: @f3( +; CHECK: %val.i0 = load i32* %src.i0, align 16, !tbaa ![[TAG:[0-9]*]] +; CHECK: %val.i1 = load i32* %src.i1, align 4, !tbaa ![[TAG]] +; CHECK: %val.i2 = load i32* %src.i2, align 8, !tbaa ![[TAG]] +; CHECK: %val.i3 = load i32* %src.i3, align 4, !tbaa ![[TAG]] +; CHECK: store i32 %add.i0, i32* %dst.i0, align 16, !tbaa ![[TAG:[0-9]*]] +; CHECK: store i32 %add.i1, i32* %dst.i1, align 4, !tbaa ![[TAG]] +; CHECK: store i32 %add.i2, i32* %dst.i2, align 8, !tbaa ![[TAG]] +; CHECK: store i32 %add.i3, i32* %dst.i3, align 4, !tbaa ![[TAG]] +; CHECK: ret void + %val = load <4 x i32> *%src, !tbaa !1 + %add = add <4 x i32> %val, %val + store <4 x i32> %add, <4 x i32> *%dst, !tbaa !2 + ret void +} + +; Check that !tbaa.struct information is preserved. +define void @f4(<4 x i32> *%src, <4 x i32> *%dst) { +; CHECK-LABEL: @f4( +; CHECK: %val.i0 = load i32* %src.i0, align 16, !tbaa.struct ![[TAG:[0-9]*]] +; CHECK: %val.i1 = load i32* %src.i1, align 4, !tbaa.struct ![[TAG]] +; CHECK: %val.i2 = load i32* %src.i2, align 8, !tbaa.struct ![[TAG]] +; CHECK: %val.i3 = load i32* %src.i3, align 4, !tbaa.struct ![[TAG]] +; CHECK: store i32 %add.i0, i32* %dst.i0, align 16, !tbaa.struct ![[TAG]] +; CHECK: store i32 %add.i1, i32* %dst.i1, align 4, !tbaa.struct ![[TAG]] +; CHECK: store i32 %add.i2, i32* %dst.i2, align 8, !tbaa.struct ![[TAG]] +; CHECK: store i32 %add.i3, i32* %dst.i3, align 4, !tbaa.struct ![[TAG]] +; CHECK: ret void + %val = load <4 x i32> *%src, !tbaa.struct !5 + %add = add <4 x i32> %val, %val + store <4 x i32> %add, <4 x i32> *%dst, !tbaa.struct !5 + ret void +} + +; Check that llvm.mem.parallel_loop_access information is preserved. +define void @f5(i32 %count, <4 x i32> *%src, <4 x i32> *%dst) { +; CHECK-LABEL: @f5( +; CHECK: %val.i0 = load i32* %this_src.i0, align 16, !llvm.mem.parallel_loop_access ![[TAG:[0-9]*]] +; CHECK: %val.i1 = load i32* %this_src.i1, align 4, !llvm.mem.parallel_loop_access ![[TAG]] +; CHECK: %val.i2 = load i32* %this_src.i2, align 8, !llvm.mem.parallel_loop_access ![[TAG]] +; CHECK: %val.i3 = load i32* %this_src.i3, align 4, !llvm.mem.parallel_loop_access ![[TAG]] +; CHECK: store i32 %add.i0, i32* %this_dst.i0, align 16, !llvm.mem.parallel_loop_access ![[TAG]] +; CHECK: store i32 %add.i1, i32* %this_dst.i1, align 4, !llvm.mem.parallel_loop_access ![[TAG]] +; CHECK: store i32 %add.i2, i32* %this_dst.i2, align 8, !llvm.mem.parallel_loop_access ![[TAG]] +; CHECK: store i32 %add.i3, i32* %this_dst.i3, align 4, !llvm.mem.parallel_loop_access ![[TAG]] +; CHECK: ret void +entry: + br label %loop + +loop: + %index = phi i32 [ 0, %entry ], [ %next_index, %loop ] + %this_src = getelementptr <4 x i32> *%src, i32 %index + %this_dst = getelementptr <4 x i32> *%dst, i32 %index + %val = load <4 x i32> *%this_src, !llvm.mem.parallel_loop_access !3 + %add = add <4 x i32> %val, %val + store <4 x i32> %add, <4 x i32> *%this_dst, !llvm.mem.parallel_loop_access !3 + %next_index = add i32 %index, -1 + %continue = icmp ne i32 %next_index, %count + br i1 %continue, label %loop, label %end, !llvm.loop !3 + +end: + ret void +} + +; Check that fpmath information is preserved. +define <4 x float> @f6(<4 x float> %x) { +; CHECK-LABEL: @f6( +; CHECK: %x.i0 = extractelement <4 x float> %x, i32 0 +; CHECK: %res.i0 = fadd float %x.i0, 1.0{{[e+0]*}}, !fpmath ![[TAG:[0-9]*]] +; CHECK: %x.i1 = extractelement <4 x float> %x, i32 1 +; CHECK: %res.i1 = fadd float %x.i1, 2.0{{[e+0]*}}, !fpmath ![[TAG]] +; CHECK: %x.i2 = extractelement <4 x float> %x, i32 2 +; CHECK: %res.i2 = fadd float %x.i2, 3.0{{[e+0]*}}, !fpmath ![[TAG]] +; CHECK: %x.i3 = extractelement <4 x float> %x, i32 3 +; CHECK: %res.i3 = fadd float %x.i3, 4.0{{[e+0]*}}, !fpmath ![[TAG]] +; CHECK: %res.upto0 = insertelement <4 x float> undef, float %res.i0, i32 0 +; CHECK: %res.upto1 = insertelement <4 x float> %res.upto0, float %res.i1, i32 1 +; CHECK: %res.upto2 = insertelement <4 x float> %res.upto1, float %res.i2, i32 2 +; CHECK: %res = insertelement <4 x float> %res.upto2, float %res.i3, i32 3 +; CHECK: ret <4 x float> %res + %res = fadd <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>, + !fpmath !4 + ret <4 x float> %res +} + +; Check that random metadata isn't kept. +define void @f7(<4 x i32> *%src, <4 x i32> *%dst) { +; CHECK-LABEL: @f7( +; CHECK-NOT: !foo +; CHECK: ret void + %val = load <4 x i32> *%src, !foo !5 + %add = add <4 x i32> %val, %val + store <4 x i32> %add, <4 x i32> *%dst, !foo !5 + ret void +} + +; Test GEP with vectors. +define void @f8(<4 x float *> *%dest, <4 x float *> %ptr0, <4 x i32> %i0, + float *%other) { +; CHECK-LABEL: @f8( +; CHECK: %dest.i0 = bitcast <4 x float*>* %dest to float** +; CHECK: %dest.i1 = getelementptr float** %dest.i0, i32 1 +; CHECK: %dest.i2 = getelementptr float** %dest.i0, i32 2 +; CHECK: %dest.i3 = getelementptr float** %dest.i0, i32 3 +; CHECK: %i0.i1 = extractelement <4 x i32> %i0, i32 1 +; CHECK: %i0.i3 = extractelement <4 x i32> %i0, i32 3 +; CHECK: %ptr0.i0 = extractelement <4 x float*> %ptr0, i32 0 +; CHECK: %val.i0 = getelementptr float* %ptr0.i0, i32 100 +; CHECK: %val.i1 = getelementptr float* %other, i32 %i0.i1 +; CHECK: %ptr0.i2 = extractelement <4 x float*> %ptr0, i32 2 +; CHECK: %val.i2 = getelementptr float* %ptr0.i2, i32 100 +; CHECK: %ptr0.i3 = extractelement <4 x float*> %ptr0, i32 3 +; CHECK: %val.i3 = getelementptr float* %ptr0.i3, i32 %i0.i3 +; CHECK: store float* %val.i0, float** %dest.i0, align 32 +; CHECK: store float* %val.i1, float** %dest.i1, align 8 +; CHECK: store float* %val.i2, float** %dest.i2, align 16 +; CHECK: store float* %val.i3, float** %dest.i3, align 8 +; CHECK: ret void + %i1 = insertelement <4 x i32> %i0, i32 100, i32 0 + %i2 = insertelement <4 x i32> %i1, i32 100, i32 2 + %ptr1 = insertelement <4 x float *> %ptr0, float *%other, i32 1 + %val = getelementptr <4 x float *> %ptr1, <4 x i32> %i2 + store <4 x float *> %val, <4 x float *> *%dest + ret void +} + +; Test the handling of unaligned loads. +define void @f9(<4 x float> *%dest, <4 x float> *%src) { +; CHECK: @f9( +; CHECK: %dest.i0 = bitcast <4 x float>* %dest to float* +; CHECK: %dest.i1 = getelementptr float* %dest.i0, i32 1 +; CHECK: %dest.i2 = getelementptr float* %dest.i0, i32 2 +; CHECK: %dest.i3 = getelementptr float* %dest.i0, i32 3 +; CHECK: %src.i0 = bitcast <4 x float>* %src to float* +; CHECK: %val.i0 = load float* %src.i0, align 4 +; CHECK: %src.i1 = getelementptr float* %src.i0, i32 1 +; CHECK: %val.i1 = load float* %src.i1, align 4 +; CHECK: %src.i2 = getelementptr float* %src.i0, i32 2 +; CHECK: %val.i2 = load float* %src.i2, align 4 +; CHECK: %src.i3 = getelementptr float* %src.i0, i32 3 +; CHECK: %val.i3 = load float* %src.i3, align 4 +; CHECK: store float %val.i0, float* %dest.i0, align 8 +; CHECK: store float %val.i1, float* %dest.i1, align 4 +; CHECK: store float %val.i2, float* %dest.i2, align 8 +; CHECK: store float %val.i3, float* %dest.i3, align 4 +; CHECK: ret void + %val = load <4 x float> *%src, align 4 + store <4 x float> %val, <4 x float> *%dest, align 8 + ret void +} + +; ...and again with subelement alignment. +define void @f10(<4 x float> *%dest, <4 x float> *%src) { +; CHECK: @f10( +; CHECK: %dest.i0 = bitcast <4 x float>* %dest to float* +; CHECK: %dest.i1 = getelementptr float* %dest.i0, i32 1 +; CHECK: %dest.i2 = getelementptr float* %dest.i0, i32 2 +; CHECK: %dest.i3 = getelementptr float* %dest.i0, i32 3 +; CHECK: %src.i0 = bitcast <4 x float>* %src to float* +; CHECK: %val.i0 = load float* %src.i0, align 1 +; CHECK: %src.i1 = getelementptr float* %src.i0, i32 1 +; CHECK: %val.i1 = load float* %src.i1, align 1 +; CHECK: %src.i2 = getelementptr float* %src.i0, i32 2 +; CHECK: %val.i2 = load float* %src.i2, align 1 +; CHECK: %src.i3 = getelementptr float* %src.i0, i32 3 +; CHECK: %val.i3 = load float* %src.i3, align 1 +; CHECK: store float %val.i0, float* %dest.i0, align 2 +; CHECK: store float %val.i1, float* %dest.i1, align 2 +; CHECK: store float %val.i2, float* %dest.i2, align 2 +; CHECK: store float %val.i3, float* %dest.i3, align 2 +; CHECK: ret void + %val = load <4 x float> *%src, align 1 + store <4 x float> %val, <4 x float> *%dest, align 2 + ret void +} + +; Test that sub-byte loads aren't scalarized. +define void @f11(<32 x i1> *%dest, <32 x i1> *%src0) { +; CHECK: @f11( +; CHECK: %val0 = load <32 x i1>* %src0 +; CHECK: %val1 = load <32 x i1>* %src1 +; CHECK: store <32 x i1> %and, <32 x i1>* %dest +; CHECK: ret void + %src1 = getelementptr <32 x i1> *%src0, i32 1 + %val0 = load <32 x i1> *%src0 + %val1 = load <32 x i1> *%src1 + %and = and <32 x i1> %val0, %val1 + store <32 x i1> %and, <32 x i1> *%dest + ret void +} + +; Test that variable inserts aren't scalarized. +define void @f12(<4 x i32> *%dest, <4 x i32> *%src, i32 %index) { +; CHECK: @f12( +; CHECK: %val1 = insertelement <4 x i32> %val0, i32 1, i32 %index +; CHECK-DAG: %val1.i0 = extractelement <4 x i32> %val1, i32 0 +; CHECK-DAG: %val1.i1 = extractelement <4 x i32> %val1, i32 1 +; CHECK-DAG: %val1.i2 = extractelement <4 x i32> %val1, i32 2 +; CHECK-DAG: %val1.i3 = extractelement <4 x i32> %val1, i32 3 +; CHECK-DAG: %val2.i0 = shl i32 1, %val1.i0 +; CHECK-DAG: %val2.i1 = shl i32 2, %val1.i1 +; CHECK-DAG: %val2.i2 = shl i32 3, %val1.i2 +; CHECK-DAG: %val2.i3 = shl i32 4, %val1.i3 +; CHECK: ret void + %val0 = load <4 x i32> *%src + %val1 = insertelement <4 x i32> %val0, i32 1, i32 %index + %val2 = shl <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %val1 + store <4 x i32> %val2, <4 x i32> *%dest + ret void +} + +; Test vector GEPs with more than one index. +define void @f13(<4 x float *> *%dest, <4 x [4 x float] *> %ptr, <4 x i32> %i, + float *%other) { +; CHECK-LABEL: @f13( +; CHECK: %dest.i0 = bitcast <4 x float*>* %dest to float** +; CHECK: %dest.i1 = getelementptr float** %dest.i0, i32 1 +; CHECK: %dest.i2 = getelementptr float** %dest.i0, i32 2 +; CHECK: %dest.i3 = getelementptr float** %dest.i0, i32 3 +; CHECK: %i.i0 = extractelement <4 x i32> %i, i32 0 +; CHECK: %ptr.i0 = extractelement <4 x [4 x float]*> %ptr, i32 0 +; CHECK: %val.i0 = getelementptr inbounds [4 x float]* %ptr.i0, i32 0, i32 %i.i0 +; CHECK: %i.i1 = extractelement <4 x i32> %i, i32 1 +; CHECK: %ptr.i1 = extractelement <4 x [4 x float]*> %ptr, i32 1 +; CHECK: %val.i1 = getelementptr inbounds [4 x float]* %ptr.i1, i32 1, i32 %i.i1 +; CHECK: %i.i2 = extractelement <4 x i32> %i, i32 2 +; CHECK: %ptr.i2 = extractelement <4 x [4 x float]*> %ptr, i32 2 +; CHECK: %val.i2 = getelementptr inbounds [4 x float]* %ptr.i2, i32 2, i32 %i.i2 +; CHECK: %i.i3 = extractelement <4 x i32> %i, i32 3 +; CHECK: %ptr.i3 = extractelement <4 x [4 x float]*> %ptr, i32 3 +; CHECK: %val.i3 = getelementptr inbounds [4 x float]* %ptr.i3, i32 3, i32 %i.i3 +; CHECK: store float* %val.i0, float** %dest.i0, align 32 +; CHECK: store float* %val.i1, float** %dest.i1, align 8 +; CHECK: store float* %val.i2, float** %dest.i2, align 16 +; CHECK: store float* %val.i3, float** %dest.i3, align 8 +; CHECK: ret void + %val = getelementptr inbounds <4 x [4 x float] *> %ptr, + <4 x i32> <i32 0, i32 1, i32 2, i32 3>, + <4 x i32> %i + store <4 x float *> %val, <4 x float *> *%dest + ret void +} + +; Test combinations of vector and non-vector PHIs. +define <4 x float> @f14(<4 x float> %acc, i32 %count) { +; CHECK-LABEL: @f14( +; CHECK: %this_acc.i0 = phi float [ %acc.i0, %entry ], [ %next_acc.i0, %loop ] +; CHECK: %this_acc.i1 = phi float [ %acc.i1, %entry ], [ %next_acc.i1, %loop ] +; CHECK: %this_acc.i2 = phi float [ %acc.i2, %entry ], [ %next_acc.i2, %loop ] +; CHECK: %this_acc.i3 = phi float [ %acc.i3, %entry ], [ %next_acc.i3, %loop ] +; CHECK: %this_count = phi i32 [ %count, %entry ], [ %next_count, %loop ] +; CHECK: %this_acc.upto0 = insertelement <4 x float> undef, float %this_acc.i0, i32 0 +; CHECK: %this_acc.upto1 = insertelement <4 x float> %this_acc.upto0, float %this_acc.i1, i32 1 +; CHECK: %this_acc.upto2 = insertelement <4 x float> %this_acc.upto1, float %this_acc.i2, i32 2 +; CHECK: %this_acc = insertelement <4 x float> %this_acc.upto2, float %this_acc.i3, i32 3 +; CHECK: ret <4 x float> %next_acc +entry: + br label %loop + +loop: + %this_acc = phi <4 x float> [ %acc, %entry ], [ %next_acc, %loop ] + %this_count = phi i32 [ %count, %entry ], [ %next_count, %loop ] + %foo = call <4 x float> @ext(<4 x float> %this_acc) + %next_acc = fadd <4 x float> %this_acc, %foo + %next_count = sub i32 %this_count, 1 + %cmp = icmp eq i32 %next_count, 0 + br i1 %cmp, label %loop, label %exit + +exit: + ret <4 x float> %next_acc +} + +!0 = metadata !{ metadata !"root" } +!1 = metadata !{ metadata !"set1", metadata !0 } +!2 = metadata !{ metadata !"set2", metadata !0 } +!3 = metadata !{ metadata !3 } +!4 = metadata !{ float 4.0 } +!5 = metadata !{ i64 0, i64 8, null } diff --git a/test/Transforms/Scalarizer/dbginfo.ll b/test/Transforms/Scalarizer/dbginfo.ll new file mode 100644 index 000000000000..546e89da80cb --- /dev/null +++ b/test/Transforms/Scalarizer/dbginfo.ll @@ -0,0 +1,86 @@ +; RUN: opt %s -scalarizer -scalarize-load-store -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +; Function Attrs: nounwind uwtable +define void @f1(<4 x i32>* nocapture %a, <4 x i32>* nocapture readonly %b, <4 x i32>* nocapture readonly %c) #0 { +; CHECK: @f1( +; CHECK: %a.i0 = bitcast <4 x i32>* %a to i32* +; CHECK: %a.i1 = getelementptr i32* %a.i0, i32 1 +; CHECK: %a.i2 = getelementptr i32* %a.i0, i32 2 +; CHECK: %a.i3 = getelementptr i32* %a.i0, i32 3 +; CHECK: %c.i0 = bitcast <4 x i32>* %c to i32* +; CHECK: %c.i1 = getelementptr i32* %c.i0, i32 1 +; CHECK: %c.i2 = getelementptr i32* %c.i0, i32 2 +; CHECK: %c.i3 = getelementptr i32* %c.i0, i32 3 +; CHECK: %b.i0 = bitcast <4 x i32>* %b to i32* +; CHECK: %b.i1 = getelementptr i32* %b.i0, i32 1 +; CHECK: %b.i2 = getelementptr i32* %b.i0, i32 2 +; CHECK: %b.i3 = getelementptr i32* %b.i0, i32 3 +; CHECK: tail call void @llvm.dbg.value(metadata !{<4 x i32>* %a}, i64 0, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} +; CHECK: tail call void @llvm.dbg.value(metadata !{<4 x i32>* %b}, i64 0, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} +; CHECK: tail call void @llvm.dbg.value(metadata !{<4 x i32>* %c}, i64 0, metadata !{{[0-9]+}}), !dbg !{{[0-9]+}} +; CHECK: %bval.i0 = load i32* %b.i0, align 16, !dbg ![[TAG1:[0-9]+]], !tbaa ![[TAG2:[0-9]+]] +; CHECK: %bval.i1 = load i32* %b.i1, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: %bval.i2 = load i32* %b.i2, align 8, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: %bval.i3 = load i32* %b.i3, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: %cval.i0 = load i32* %c.i0, align 16, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: %cval.i1 = load i32* %c.i1, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: %cval.i2 = load i32* %c.i2, align 8, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: %cval.i3 = load i32* %c.i3, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: %add.i0 = add i32 %bval.i0, %cval.i0, !dbg ![[TAG1]] +; CHECK: %add.i1 = add i32 %bval.i1, %cval.i1, !dbg ![[TAG1]] +; CHECK: %add.i2 = add i32 %bval.i2, %cval.i2, !dbg ![[TAG1]] +; CHECK: %add.i3 = add i32 %bval.i3, %cval.i3, !dbg ![[TAG1]] +; CHECK: store i32 %add.i0, i32* %a.i0, align 16, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: store i32 %add.i1, i32* %a.i1, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: store i32 %add.i2, i32* %a.i2, align 8, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: store i32 %add.i3, i32* %a.i3, align 4, !dbg ![[TAG1]], !tbaa ![[TAG2]] +; CHECK: ret void +entry: + tail call void @llvm.dbg.value(metadata !{<4 x i32>* %a}, i64 0, metadata !15), !dbg !20 + tail call void @llvm.dbg.value(metadata !{<4 x i32>* %b}, i64 0, metadata !16), !dbg !20 + tail call void @llvm.dbg.value(metadata !{<4 x i32>* %c}, i64 0, metadata !17), !dbg !20 + %bval = load <4 x i32>* %b, align 16, !dbg !21, !tbaa !22 + %cval = load <4 x i32>* %c, align 16, !dbg !21, !tbaa !22 + %add = add <4 x i32> %bval, %cval, !dbg !21 + store <4 x i32> %add, <4 x i32>* %a, align 16, !dbg !21, !tbaa !22 + ret void, !dbg !25 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata) #1 + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!18, !26} +!llvm.ident = !{!19} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4 (trunk 194134) (llvm/trunk 194126)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/home/richards/llvm/build//tmp/add.c] [DW_LANG_C99] +!1 = metadata !{metadata !"/tmp/add.c", metadata !"/home/richards/llvm/build"} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"f1", metadata !"f1", metadata !"", i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (<4 x i32>*, <4 x i32>*, <4 x i32>*)* @f1, null, null, metadata !14, i32 4} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [f] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/home/richards/llvm/build//tmp/add.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{null, metadata !8, metadata !8, metadata !8} +!8 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from V4SI] +!9 = metadata !{i32 786454, metadata !1, null, metadata !"V4SI", i32 1, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] [V4SI] [line 1, size 0, align 0, offset 0] [from ] +!10 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 128, i64 128, i32 0, i32 2048, metadata !11, metadata !12, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [vector] [from int] +!11 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 786465, i64 0, i64 4} ; [ DW_TAG_subrange_type ] [0, 3] +!14 = metadata !{metadata !15, metadata !16, metadata !17} +!15 = metadata !{i32 786689, metadata !4, metadata !"a", metadata !5, i32 16777219, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [a] [line 3] +!16 = metadata !{i32 786689, metadata !4, metadata !"b", metadata !5, i32 33554435, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [b] [line 3] +!17 = metadata !{i32 786689, metadata !4, metadata !"c", metadata !5, i32 50331651, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [c] [line 3] +!18 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!19 = metadata !{metadata !"clang version 3.4 (trunk 194134) (llvm/trunk 194126)"} +!20 = metadata !{i32 3, i32 0, metadata !4, null} +!21 = metadata !{i32 5, i32 0, metadata !4, null} +!22 = metadata !{metadata !23, metadata !23, i64 0} +!23 = metadata !{metadata !"omnipotent char", metadata !24, i64 0} +!24 = metadata !{metadata !"Simple C/C++ TBAA"} +!25 = metadata !{i32 6, i32 0, metadata !4, null} +!26 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/Transforms/Scalarizer/no-data-layout.ll b/test/Transforms/Scalarizer/no-data-layout.ll new file mode 100644 index 000000000000..3eaf669ef9dd --- /dev/null +++ b/test/Transforms/Scalarizer/no-data-layout.ll @@ -0,0 +1,25 @@ +; RUN: opt %s -scalarizer -scalarize-load-store -S | FileCheck %s + +; Test the handling of loads and stores when no data layout is available. +define void @f1(<4 x float> *%dest, <4 x float> *%src) { +; CHECK: @f1( +; CHECK: %val = load <4 x float>* %src, align 4 +; CHECK: %val.i0 = extractelement <4 x float> %val, i32 0 +; CHECK: %add.i0 = fadd float %val.i0, %val.i0 +; CHECK: %val.i1 = extractelement <4 x float> %val, i32 1 +; CHECK: %add.i1 = fadd float %val.i1, %val.i1 +; CHECK: %val.i2 = extractelement <4 x float> %val, i32 2 +; CHECK: %add.i2 = fadd float %val.i2, %val.i2 +; CHECK: %val.i3 = extractelement <4 x float> %val, i32 3 +; CHECK: %add.i3 = fadd float %val.i3, %val.i3 +; CHECK: %add.upto0 = insertelement <4 x float> undef, float %add.i0, i32 0 +; CHECK: %add.upto1 = insertelement <4 x float> %add.upto0, float %add.i1, i32 1 +; CHECK: %add.upto2 = insertelement <4 x float> %add.upto1, float %add.i2, i32 2 +; CHECK: %add = insertelement <4 x float> %add.upto2, float %add.i3, i32 3 +; CHECK: store <4 x float> %add, <4 x float>* %dest, align 8 +; CHECK: ret void + %val = load <4 x float> *%src, align 4 + %add = fadd <4 x float> %val, %val + store <4 x float> %add, <4 x float> *%dest, align 8 + ret void +} diff --git a/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/lit.local.cfg b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/lit.local.cfg new file mode 100644 index 000000000000..a5e90f8e3c1d --- /dev/null +++ b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'NVPTX' in config.root.targets: + config.unsupported = True + diff --git a/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll new file mode 100644 index 000000000000..d054a3b1b9f2 --- /dev/null +++ b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep-and-gvn.ll @@ -0,0 +1,196 @@ +; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX +; RUN: opt < %s -S -separate-const-offset-from-gep -gvn -dce | FileCheck %s --check-prefix=IR + +; Verifies the SeparateConstOffsetFromGEP pass. +; The following code computes +; *output = array[x][y] + array[x][y+1] + array[x+1][y] + array[x+1][y+1] +; +; We expect SeparateConstOffsetFromGEP to transform it to +; +; float *base = &a[x][y]; +; *output = base[0] + base[1] + base[32] + base[33]; +; +; so the backend can emit PTX that uses fewer virtual registers. + +target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" +target triple = "nvptx64-unknown-unknown" + +@array = internal addrspace(3) constant [32 x [32 x float]] zeroinitializer, align 4 + +define void @sum_of_array(i32 %x, i32 %y, float* nocapture %output) { +.preheader: + %0 = sext i32 %y to i64 + %1 = sext i32 %x to i64 + %2 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0 + %3 = addrspacecast float addrspace(3)* %2 to float* + %4 = load float* %3, align 4 + %5 = fadd float %4, 0.000000e+00 + %6 = add i32 %y, 1 + %7 = sext i32 %6 to i64 + %8 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %7 + %9 = addrspacecast float addrspace(3)* %8 to float* + %10 = load float* %9, align 4 + %11 = fadd float %5, %10 + %12 = add i32 %x, 1 + %13 = sext i32 %12 to i64 + %14 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %0 + %15 = addrspacecast float addrspace(3)* %14 to float* + %16 = load float* %15, align 4 + %17 = fadd float %11, %16 + %18 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7 + %19 = addrspacecast float addrspace(3)* %18 to float* + %20 = load float* %19, align 4 + %21 = fadd float %17, %20 + store float %21, float* %output, align 4 + ret void +} +; PTX-LABEL: sum_of_array( +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} + +; IR-LABEL: @sum_of_array( +; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1 +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32 +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33 + +; @sum_of_array2 is very similar to @sum_of_array. The only difference is in +; the order of "sext" and "add" when computing the array indices. @sum_of_array +; computes add before sext, e.g., array[sext(x + 1)][sext(y + 1)], while +; @sum_of_array2 computes sext before add, +; e.g., array[sext(x) + 1][sext(y) + 1]. SeparateConstOffsetFromGEP should be +; able to extract constant offsets from both forms. +define void @sum_of_array2(i32 %x, i32 %y, float* nocapture %output) { +.preheader: + %0 = sext i32 %y to i64 + %1 = sext i32 %x to i64 + %2 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0 + %3 = addrspacecast float addrspace(3)* %2 to float* + %4 = load float* %3, align 4 + %5 = fadd float %4, 0.000000e+00 + %6 = add i64 %0, 1 + %7 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %6 + %8 = addrspacecast float addrspace(3)* %7 to float* + %9 = load float* %8, align 4 + %10 = fadd float %5, %9 + %11 = add i64 %1, 1 + %12 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %0 + %13 = addrspacecast float addrspace(3)* %12 to float* + %14 = load float* %13, align 4 + %15 = fadd float %10, %14 + %16 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6 + %17 = addrspacecast float addrspace(3)* %16 to float* + %18 = load float* %17, align 4 + %19 = fadd float %15, %18 + store float %19, float* %output, align 4 + ret void +} +; PTX-LABEL: sum_of_array2( +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} + +; IR-LABEL: @sum_of_array2( +; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1 +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32 +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33 + + +; This function loads +; array[zext(x)][zext(y)] +; array[zext(x)][zext(y +nuw 1)] +; array[zext(x +nuw 1)][zext(y)] +; array[zext(x +nuw 1)][zext(y +nuw 1)]. +; +; This function is similar to @sum_of_array, but it +; 1) extends array indices using zext instead of sext; +; 2) annotates the addition with "nuw"; otherwise, zext(x + 1) => zext(x) + 1 +; may be invalid. +define void @sum_of_array3(i32 %x, i32 %y, float* nocapture %output) { +.preheader: + %0 = zext i32 %y to i64 + %1 = zext i32 %x to i64 + %2 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0 + %3 = addrspacecast float addrspace(3)* %2 to float* + %4 = load float* %3, align 4 + %5 = fadd float %4, 0.000000e+00 + %6 = add nuw i32 %y, 1 + %7 = zext i32 %6 to i64 + %8 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %7 + %9 = addrspacecast float addrspace(3)* %8 to float* + %10 = load float* %9, align 4 + %11 = fadd float %5, %10 + %12 = add nuw i32 %x, 1 + %13 = zext i32 %12 to i64 + %14 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %0 + %15 = addrspacecast float addrspace(3)* %14 to float* + %16 = load float* %15, align 4 + %17 = fadd float %11, %16 + %18 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7 + %19 = addrspacecast float addrspace(3)* %18 to float* + %20 = load float* %19, align 4 + %21 = fadd float %17, %20 + store float %21, float* %output, align 4 + ret void +} +; PTX-LABEL: sum_of_array3( +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} + +; IR-LABEL: @sum_of_array3( +; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1 +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32 +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33 + + +; This function loads +; array[zext(x)][zext(y)] +; array[zext(x)][zext(y)] +; array[zext(x) + 1][zext(y) + 1] +; array[zext(x) + 1][zext(y) + 1]. +; +; We expect the generated code to reuse the computation of +; &array[zext(x)][zext(y)]. See the expected IR and PTX for details. +define void @sum_of_array4(i32 %x, i32 %y, float* nocapture %output) { +.preheader: + %0 = zext i32 %y to i64 + %1 = zext i32 %x to i64 + %2 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0 + %3 = addrspacecast float addrspace(3)* %2 to float* + %4 = load float* %3, align 4 + %5 = fadd float %4, 0.000000e+00 + %6 = add i64 %0, 1 + %7 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %6 + %8 = addrspacecast float addrspace(3)* %7 to float* + %9 = load float* %8, align 4 + %10 = fadd float %5, %9 + %11 = add i64 %1, 1 + %12 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %0 + %13 = addrspacecast float addrspace(3)* %12 to float* + %14 = load float* %13, align 4 + %15 = fadd float %10, %14 + %16 = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6 + %17 = addrspacecast float addrspace(3)* %16 to float* + %18 = load float* %17, align 4 + %19 = fadd float %15, %18 + store float %19, float* %output, align 4 + ret void +} +; PTX-LABEL: sum_of_array4( +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} +; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} + +; IR-LABEL: @sum_of_array4( +; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1 +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32 +; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33 diff --git a/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll new file mode 100644 index 000000000000..1784171454d6 --- /dev/null +++ b/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/split-gep.ll @@ -0,0 +1,236 @@ +; RUN: opt < %s -separate-const-offset-from-gep -dce -S | FileCheck %s + +; Several unit tests for -separate-const-offset-from-gep. The transformation +; heavily relies on TargetTransformInfo, so we put these tests under +; target-specific folders. + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +; target triple is necessary; otherwise TargetTransformInfo rejects any +; addressing mode. +target triple = "nvptx64-unknown-unknown" + +%struct.S = type { float, double } + +@struct_array = global [1024 x %struct.S] zeroinitializer, align 16 +@float_2d_array = global [32 x [32 x float]] zeroinitializer, align 4 + +; We should not extract any struct field indices, because fields in a struct +; may have different types. +define double* @struct(i32 %i) { +entry: + %add = add nsw i32 %i, 5 + %idxprom = sext i32 %add to i64 + %p = getelementptr inbounds [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1 + ret double* %p +} +; CHECK-LABEL: @struct( +; CHECK: getelementptr [1024 x %struct.S]* @struct_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1 + +; We should be able to trace into sext(a + b) if a + b is non-negative +; (e.g., used as an index of an inbounds GEP) and one of a and b is +; non-negative. +define float* @sext_add(i32 %i, i32 %j) { +entry: + %0 = add i32 %i, 1 + %1 = sext i32 %0 to i64 ; inbound sext(i + 1) = sext(i) + 1 + %2 = add i32 %j, -2 + ; However, inbound sext(j + -2) != sext(j) + -2, e.g., j = INT_MIN + %3 = sext i32 %2 to i64 + %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %1, i64 %3 + ret float* %p +} +; CHECK-LABEL: @sext_add( +; CHECK-NOT: = add +; CHECK: add i32 %j, -2 +; CHECK: sext +; CHECK: getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; CHECK: getelementptr float* %{{[a-zA-Z0-9]+}}, i64 32 + +; We should be able to trace into sext/zext if it can be distributed to both +; operands, e.g., sext (add nsw a, b) == add nsw (sext a), (sext b) +; +; This test verifies we can transform +; gep base, a + sext(b +nsw 1), c + zext(d +nuw 1) +; to +; gep base, a + sext(b), c + zext(d); gep ..., 1 * 32 + 1 +define float* @ext_add_no_overflow(i64 %a, i32 %b, i64 %c, i32 %d) { + %b1 = add nsw i32 %b, 1 + %b2 = sext i32 %b1 to i64 + %i = add i64 %a, %b2 ; i = a + sext(b +nsw 1) + %d1 = add nuw i32 %d, 1 + %d2 = zext i32 %d1 to i64 + %j = add i64 %c, %d2 ; j = c + zext(d +nuw 1) + %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %j + ret float* %p +} +; CHECK-LABEL: @ext_add_no_overflow( +; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; CHECK: getelementptr float* [[BASE_PTR]], i64 33 + +; Verifies we handle nested sext/zext correctly. +define void @sext_zext(i32 %a, i32 %b, float** %out1, float** %out2) { +entry: + %0 = add nsw nuw i32 %a, 1 + %1 = sext i32 %0 to i48 + %2 = zext i48 %1 to i64 ; zext(sext(a +nsw nuw 1)) = zext(sext(a)) + 1 + %3 = add nsw i32 %b, 2 + %4 = sext i32 %3 to i48 + %5 = zext i48 %4 to i64 ; zext(sext(b +nsw 2)) != zext(sext(b)) + 2 + %p1 = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %2, i64 %5 + store float* %p1, float** %out1 + %6 = add nuw i32 %a, 3 + %7 = zext i32 %6 to i48 + %8 = sext i48 %7 to i64 ; sext(zext(a +nuw 3)) = zext(a +nuw 3) = zext(a) + 3 + %9 = add nsw i32 %b, 4 + %10 = zext i32 %9 to i48 + %11 = sext i48 %10 to i64 ; sext(zext(b +nsw 4)) != zext(b) + 4 + %p2 = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %8, i64 %11 + store float* %p2, float** %out2 + ret void +} +; CHECK-LABEL: @sext_zext( +; CHECK: [[BASE_PTR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; CHECK: getelementptr float* [[BASE_PTR_1]], i64 32 +; CHECK: [[BASE_PTR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; CHECK: getelementptr float* [[BASE_PTR_2]], i64 96 + +; Similar to @ext_add_no_overflow, we should be able to trace into s/zext if +; its operand is an OR and the two operands of the OR have no common bits. +define float* @sext_or(i64 %a, i32 %b) { +entry: + %b1 = shl i32 %b, 2 + %b2 = or i32 %b1, 1 ; (b << 2) and 1 have no common bits + %b3 = or i32 %b1, 4 ; (b << 2) and 4 may have common bits + %b2.ext = zext i32 %b2 to i64 + %b3.ext = sext i32 %b3 to i64 + %i = add i64 %a, %b2.ext + %j = add i64 %a, %b3.ext + %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %j + ret float* %p +} +; CHECK-LABEL: @sext_or( +; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} +; CHECK: getelementptr float* [[BASE_PTR]], i64 32 + +; The subexpression (b + 5) is used in both "i = a + (b + 5)" and "*out = b + +; 5". When extracting the constant offset 5, make sure "*out = b + 5" isn't +; affected. +define float* @expr(i64 %a, i64 %b, i64* %out) { +entry: + %b5 = add i64 %b, 5 + %i = add i64 %b5, %a + %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 0 + store i64 %b5, i64* %out + ret float* %p +} +; CHECK-LABEL: @expr( +; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 0 +; CHECK: getelementptr float* [[BASE_PTR]], i64 160 +; CHECK: store i64 %b5, i64* %out + +; d + sext(a +nsw (b +nsw (c +nsw 8))) => (d + sext(a) + sext(b) + sext(c)) + 8 +define float* @sext_expr(i32 %a, i32 %b, i32 %c, i64 %d) { +entry: + %0 = add nsw i32 %c, 8 + %1 = add nsw i32 %b, %0 + %2 = add nsw i32 %a, %1 + %3 = sext i32 %2 to i64 + %i = add i64 %d, %3 + %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i + ret float* %p +} +; CHECK-LABEL: @sext_expr( +; CHECK: sext i32 +; CHECK: sext i32 +; CHECK: sext i32 +; CHECK: getelementptr float* %{{[a-zA-Z0-9]+}}, i64 8 + +; Verifies we handle "sub" correctly. +define float* @sub(i64 %i, i64 %j) { + %i2 = sub i64 %i, 5 ; i - 5 + %j2 = sub i64 5, %j ; 5 - i + %p = getelementptr inbounds [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i2, i64 %j2 + ret float* %p +} +; CHECK-LABEL: @sub( +; CHECK: %[[j2:[a-zA-Z0-9]+]] = sub i64 0, %j +; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 %i, i64 %[[j2]] +; CHECK: getelementptr float* [[BASE_PTR]], i64 -155 + +%struct.Packed = type <{ [3 x i32], [8 x i64] }> ; <> means packed + +; Verifies we can emit correct uglygep if the address is not natually aligned. +define i64* @packed_struct(i32 %i, i32 %j) { +entry: + %s = alloca [1024 x %struct.Packed], align 16 + %add = add nsw i32 %j, 3 + %idxprom = sext i32 %add to i64 + %add1 = add nsw i32 %i, 1 + %idxprom2 = sext i32 %add1 to i64 + %arrayidx3 = getelementptr inbounds [1024 x %struct.Packed]* %s, i64 0, i64 %idxprom2, i32 1, i64 %idxprom + ret i64* %arrayidx3 +} +; CHECK-LABEL: @packed_struct( +; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [1024 x %struct.Packed]* %s, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1, i64 %{{[a-zA-Z0-9]+}} +; CHECK: [[CASTED_PTR:%[a-zA-Z0-9]+]] = bitcast i64* [[BASE_PTR]] to i8* +; CHECK: %uglygep = getelementptr i8* [[CASTED_PTR]], i64 100 +; CHECK: bitcast i8* %uglygep to i64* + +; We shouldn't be able to extract the 8 from "zext(a +nuw (b + 8))", +; because "zext(b + 8) != zext(b) + 8" +define float* @zext_expr(i32 %a, i32 %b) { +entry: + %0 = add i32 %b, 8 + %1 = add nuw i32 %a, %0 + %i = zext i32 %1 to i64 + %p = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i + ret float* %p +} +; CHECK-LABEL: zext_expr( +; CHECK: getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %i + +; Per http://llvm.org/docs/LangRef.html#id181, the indices of a off-bound gep +; should be considered sign-extended to the pointer size. Therefore, +; gep base, (add i32 a, b) != gep (gep base, i32 a), i32 b +; because +; sext(a + b) != sext(a) + sext(b) +; +; This test verifies we do not illegitimately extract the 8 from +; gep base, (i32 a + 8) +define float* @i32_add(i32 %a) { +entry: + %i = add i32 %a, 8 + %p = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i32 %i + ret float* %p +} +; CHECK-LABEL: @i32_add( +; CHECK: getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %{{[a-zA-Z0-9]+}} +; CHECK-NOT: getelementptr + +; Verifies that we compute the correct constant offset when the index is +; sign-extended and then zero-extended. The old version of our code failed to +; handle this case because it simply computed the constant offset as the +; sign-extended value of the constant part of the GEP index. +define float* @apint(i1 %a) { +entry: + %0 = add nsw nuw i1 %a, 1 + %1 = sext i1 %0 to i4 + %2 = zext i4 %1 to i64 ; zext (sext i1 1 to i4) to i64 = 15 + %p = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %2 + ret float* %p +} +; CHECK-LABEL: @apint( +; CHECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %{{[a-zA-Z0-9]+}} +; CHECK: getelementptr float* [[BASE_PTR]], i64 15 + +; Do not trace into binary operators other than ADD, SUB, and OR. +define float* @and(i64 %a) { +entry: + %0 = shl i64 %a, 2 + %1 = and i64 %0, 1 + %p = getelementptr [32 x [32 x float]]* @float_2d_array, i64 0, i64 0, i64 %1 + ret float* %p +} +; CHECK-LABEL: @and( +; CHECK: getelementptr [32 x [32 x float]]* @float_2d_array +; CHECK-NOT: getelementptr diff --git a/test/Transforms/SimplifyCFG/PR17073.ll b/test/Transforms/SimplifyCFG/PR17073.ll new file mode 100644 index 000000000000..8dc9fb28d617 --- /dev/null +++ b/test/Transforms/SimplifyCFG/PR17073.ll @@ -0,0 +1,73 @@ +; RUN: opt < %s -simplifycfg -S | FileCheck %s + +; In PR17073 ( http://llvm.org/pr17073 ), we illegally hoisted an operation that can trap. +; The first test confirms that we don't do that when the trapping op is reached by the current BB (block1). +; The second test confirms that we don't do that when the trapping op is reached by the previous BB (entry). +; The third test confirms that we can still do this optimization for an operation (add) that doesn't trap. +; The tests must be complicated enough to prevent previous SimplifyCFG actions from optimizing away +; the instructions that we're checking for. + +target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128" +target triple = "i386-apple-macosx10.9.0" + +@a = common global i32 0, align 4 +@b = common global i8 0, align 1 + +; CHECK-LABEL: can_trap1 +; CHECK-NOT: or i1 %tobool, icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) +; CHECK-NOT: select i1 %tobool, i32* null, i32* select (i1 icmp eq (i64 urem (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a) +define i32* @can_trap1() { +entry: + %0 = load i32* @a, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %exit, label %block1 + +block1: + br i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a), label %exit, label %block2 + +block2: + br label %exit + +exit: + %storemerge = phi i32* [ null, %entry ],[ null, %block2 ], [ select (i1 icmp eq (i64 urem (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a), %block1 ] + ret i32* %storemerge +} + +; CHECK-LABEL: can_trap2 +; CHECK-NOT: or i1 %tobool, icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) +; CHECK-NOT: select i1 %tobool, i32* select (i1 icmp eq (i64 urem (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a), i32* null +define i32* @can_trap2() { +entry: + %0 = load i32* @a, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %exit, label %block1 + +block1: + br i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a), label %exit, label %block2 + +block2: + br label %exit + +exit: + %storemerge = phi i32* [ select (i1 icmp eq (i64 urem (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a), %entry ],[ null, %block2 ], [ null, %block1 ] + ret i32* %storemerge +} + +; CHECK-LABEL: cannot_trap +; CHECK: select i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a), i32* select (i1 icmp eq (i64 add (i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64), i64 2), i64 0), i32* null, i32* @a), i32* null +define i32* @cannot_trap() { +entry: + %0 = load i32* @a, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %exit, label %block1 + +block1: + br i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a), label %exit, label %block2 + +block2: + br label %exit + +exit: + %storemerge = phi i32* [ null, %entry ],[ null, %block2 ], [ select (i1 icmp eq (i64 add (i64 2, i64 zext (i1 icmp eq (i32* bitcast (i8* @b to i32*), i32* @a) to i64)), i64 0), i32* null, i32* @a), %block1 ] + ret i32* %storemerge +} diff --git a/test/Transforms/SimplifyCFG/SPARC/lit.local.cfg b/test/Transforms/SimplifyCFG/SPARC/lit.local.cfg index 4d344fa91a9e..fa6a54e50132 100644 --- a/test/Transforms/SimplifyCFG/SPARC/lit.local.cfg +++ b/test/Transforms/SimplifyCFG/SPARC/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'Sparc' in targets: +if not 'Sparc' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/SimplifyCFG/X86/lit.local.cfg b/test/Transforms/SimplifyCFG/X86/lit.local.cfg index ba763cf03ffc..e71f3cc4c41e 100644 --- a/test/Transforms/SimplifyCFG/X86/lit.local.cfg +++ b/test/Transforms/SimplifyCFG/X86/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll b/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll new file mode 100644 index 000000000000..d0b8ab29d26b --- /dev/null +++ b/test/Transforms/SimplifyCFG/X86/switch-table-bug.ll @@ -0,0 +1,41 @@ +; RUN: opt -S -simplifycfg < %s -mtriple=x86_64-apple-darwin12.0.0 | FileCheck %s +; rdar://17735071 +target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin12.0.0" + +; When tableindex can't fit into i2, we should extend the type to i3. +; CHECK-LABEL: @_TFO6reduce1E5toRawfS0_FT_Si +; CHECK: entry: +; CHECK-NEXT: sub i2 %0, -2 +; CHECK-NEXT: zext i2 %switch.tableidx to i3 +; CHECK-NEXT: getelementptr inbounds [4 x i64]* @switch.table, i32 0, i3 %switch.tableidx.zext +; CHECK-NEXT: load i64* %switch.gep +; CHECK-NEXT: ret i64 %switch.load +define i64 @_TFO6reduce1E5toRawfS0_FT_Si(i2) { +entry: + switch i2 %0, label %1 [ + i2 0, label %2 + i2 1, label %3 + i2 -2, label %4 + i2 -1, label %5 + ] + +; <label>:1 ; preds = %entry + unreachable + +; <label>:2 ; preds = %2 + br label %6 + +; <label>:3 ; preds = %4 + br label %6 + +; <label>:4 ; preds = %6 + br label %6 + +; <label>:5 ; preds = %8 + br label %6 + +; <label>:6 ; preds = %3, %5, %7, %9 + %7 = phi i64 [ 3, %5 ], [ 2, %4 ], [ 1, %3 ], [ 0, %2 ] + ret i64 %7 +} diff --git a/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll b/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll index 368732711a70..51ced4099ac9 100644 --- a/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll +++ b/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll @@ -806,3 +806,170 @@ return: ; CHECK-NOT: @switch.table ; CHECK: switch i32 %c } + +; If we can build a lookup table without any holes, we don't need a default result. +declare void @exit(i32) +define i32 @nodefaultnoholes(i32 %c) { +entry: + switch i32 %c, label %sw.default [ + i32 0, label %return + i32 1, label %sw.bb1 + i32 2, label %sw.bb2 + i32 3, label %sw.bb3 + ] + +sw.bb1: br label %return +sw.bb2: br label %return +sw.bb3: br label %return +sw.default: call void @exit(i32 1) + unreachable +return: + %x = phi i32 [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ] + ret i32 %x + +; CHECK-LABEL: @nodefaultnoholes( +; CHECK: @switch.table +; CHECK-NOT: switch i32 +} + +; This lookup table will have holes, so we need to test for the holes. +define i32 @nodefaultwithholes(i32 %c) { +entry: + switch i32 %c, label %sw.default [ + i32 0, label %return + i32 1, label %sw.bb1 + i32 2, label %sw.bb2 + i32 3, label %sw.bb3 + i32 5, label %sw.bb3 + ] + +sw.bb1: br label %return +sw.bb2: br label %return +sw.bb3: br label %return +sw.default: call void @exit(i32 1) + unreachable +return: + %x = phi i32 [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ] + ret i32 %x + +; CHECK-LABEL: @nodefaultwithholes( +; CHECK: entry: +; CHECK: br i1 %{{.*}}, label %switch.hole_check, label %sw.default +; CHECK: switch.hole_check: +; CHECK-NEXT: %switch.maskindex = trunc i32 %switch.tableidx to i6 +; CHECK-NEXT: %switch.shifted = lshr i6 -17, %switch.maskindex +; The mask is binary 101111. +; CHECK-NEXT: %switch.lobit = trunc i6 %switch.shifted to i1 +; CHECK-NEXT: br i1 %switch.lobit, label %switch.lookup, label %sw.default +; CHECK-NOT: switch i32 +} + +; We don't build lookup tables with holes for switches with less than four cases. +define i32 @threecasesholes(i32 %c) { +entry: + switch i32 %c, label %sw.default [ + i32 0, label %return + i32 1, label %sw.bb1 + i32 3, label %sw.bb2 + ] +sw.bb1: br label %return +sw.bb2: br label %return +sw.default: br label %return +return: + %x = phi i32 [ %c, %sw.default ], [ 5, %sw.bb2 ], [ 7, %sw.bb1 ], [ 9, %entry ] + ret i32 %x +; CHECK-LABEL: @threecasesholes( +; CHECK: switch i32 +; CHECK-NOT: @switch.table +} + +; We build lookup tables for switches with three or more cases. +define i32 @threecases(i32 %c) { +entry: + switch i32 %c, label %sw.default [ + i32 0, label %return + i32 1, label %sw.bb1 + i32 2, label %sw.bb2 + ] +sw.bb1: br label %return +sw.bb2: br label %return +sw.default: br label %return +return: + %x = phi i32 [ 3, %sw.default ], [ 5, %sw.bb2 ], [ 7, %sw.bb1 ], [ 9, %entry ] + ret i32 %x +; CHECK-LABEL: @threecases( +; CHECK-NOT: switch i32 +; CHECK: @switch.table +} + +; We don't build tables for switches with two cases. +define i32 @twocases(i32 %c) { +entry: + switch i32 %c, label %sw.default [ + i32 0, label %return + i32 1, label %sw.bb1 + ] +sw.bb1: br label %return +sw.default: br label %return +return: + %x = phi i32 [ 3, %sw.default ], [ 7, %sw.bb1 ], [ 9, %entry ] + ret i32 %x +; CHECK-LABEL: @twocases( +; CHECK: switch i32 +; CHECK-NOT: @switch.table +} + +; Don't build tables for switches with TLS variables. +@tls_a = thread_local global i32 0 +@tls_b = thread_local global i32 0 +@tls_c = thread_local global i32 0 +@tls_d = thread_local global i32 0 +define i32* @tls(i32 %x) { +entry: + switch i32 %x, label %sw.default [ + i32 0, label %return + i32 1, label %sw.bb1 + i32 2, label %sw.bb2 + ] +sw.bb1: + br label %return +sw.bb2: + br label %return +sw.default: + br label %return +return: + %retval.0 = phi i32* [ @tls_d, %sw.default ], [ @tls_c, %sw.bb2 ], [ @tls_b, %sw.bb1 ], [ @tls_a, %entry ] + ret i32* %retval.0 +; CHECK-LABEL: @tls( +; CHECK: switch i32 +; CHECK-NOT: @switch.table +} + +; Don't build tables for switches with dllimport variables. +@dllimport_a = external dllimport global [3x i32] +@dllimport_b = external dllimport global [3x i32] +@dllimport_c = external dllimport global [3x i32] +@dllimport_d = external dllimport global [3x i32] +define i32* @dllimport(i32 %x) { +entry: + switch i32 %x, label %sw.default [ + i32 0, label %return + i32 1, label %sw.bb1 + i32 2, label %sw.bb2 + ] +sw.bb1: + br label %return +sw.bb2: + br label %return +sw.default: + br label %return +return: + %retval.0 = phi i32* [ getelementptr inbounds ([3 x i32]* @dllimport_d, i32 0, i32 0), %sw.default ], + [ getelementptr inbounds ([3 x i32]* @dllimport_c, i32 0, i32 0), %sw.bb2 ], + [ getelementptr inbounds ([3 x i32]* @dllimport_b, i32 0, i32 0), %sw.bb1 ], + [ getelementptr inbounds ([3 x i32]* @dllimport_a, i32 0, i32 0), %entry ] + ret i32* %retval.0 +; CHECK-LABEL: @dllimport( +; CHECK: switch i32 +; CHECK-NOT: @switch.table +} diff --git a/test/Transforms/SimplifyCFG/basictest.ll b/test/Transforms/SimplifyCFG/basictest.ll index 9c4edd68b800..d6958a9c111a 100644 --- a/test/Transforms/SimplifyCFG/basictest.ll +++ b/test/Transforms/SimplifyCFG/basictest.ll @@ -41,3 +41,33 @@ return: ; preds = %entry ; CHECK-LABEL: @test5( ; CHECK-NEXT: ret void } + + +; PR14893 +define i8 @test6f() { +; CHECK-LABEL: @test6f +; CHECK: alloca i8, align 1 +; CHECK-NEXT: call i8 @test6g +; CHECK-NEXT: icmp eq i8 %tmp, 0 +; CHECK-NEXT: load i8* %r, align 1{{$}} + +bb0: + %r = alloca i8, align 1 + %tmp = call i8 @test6g(i8* %r) + %tmp1 = icmp eq i8 %tmp, 0 + br i1 %tmp1, label %bb2, label %bb1 +bb1: + %tmp3 = load i8* %r, align 1, !range !2, !tbaa !1 + %tmp4 = icmp eq i8 %tmp3, 1 + br i1 %tmp4, label %bb2, label %bb3 +bb2: + br label %bb3 +bb3: + %tmp6 = phi i8 [ 0, %bb2 ], [ 1, %bb1 ] + ret i8 %tmp6 +} +declare i8 @test6g(i8*) + +!0 = metadata !{metadata !1, metadata !1, i64 0} +!1 = metadata !{metadata !"foo"} +!2 = metadata !{i8 0, i8 2} diff --git a/test/Transforms/SimplifyCFG/extract-cost.ll b/test/Transforms/SimplifyCFG/extract-cost.ll new file mode 100644 index 000000000000..9c867256e783 --- /dev/null +++ b/test/Transforms/SimplifyCFG/extract-cost.ll @@ -0,0 +1,22 @@ +; RUN: opt -simplifycfg -S < %s | FileCheck %s + +declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1 + +define i32 @f(i32 %a, i32 %b) #0 { +entry: + %uadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) + %cmp = extractvalue { i32, i1 } %uadd, 1 + br i1 %cmp, label %return, label %if.end + +if.end: ; preds = %entry + %0 = extractvalue { i32, i1 } %uadd, 0 + br label %return + +return: ; preds = %entry, %if.end + %retval.0 = phi i32 [ %0, %if.end ], [ 0, %entry ] + ret i32 %retval.0 + +; CHECK-LABEL: @f( +; CHECK-NOT: phi +; CHECK: select +} diff --git a/test/Transforms/SimplifyCFG/no_speculative_loads_with_tsan.ll b/test/Transforms/SimplifyCFG/no_speculative_loads_with_tsan.ll new file mode 100644 index 000000000000..b388cc5830f4 --- /dev/null +++ b/test/Transforms/SimplifyCFG/no_speculative_loads_with_tsan.ll @@ -0,0 +1,40 @@ +; RUN: opt -simplifycfg -S %s | FileCheck %s +; Make sure we don't speculate loads under ThreadSanitizer. +@g = global i32 0, align 4 + +define i32 @TestNoTsan(i32 %cond) nounwind readonly uwtable { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %return, label %if.then + +if.then: ; preds = %entry + %0 = load i32* @g, align 4 + br label %return + +return: ; preds = %entry, %if.then + %retval = phi i32 [ %0, %if.then ], [ 0, %entry ] + ret i32 %retval +; CHECK-LABEL: @TestNoTsan +; CHECK: %[[LOAD:[^ ]*]] = load +; CHECK: select{{.*}}[[LOAD]] +; CHECK: ret i32 +} + +define i32 @TestTsan(i32 %cond) nounwind readonly uwtable sanitize_thread { +entry: + %tobool = icmp eq i32 %cond, 0 + br i1 %tobool, label %return, label %if.then + +if.then: ; preds = %entry + %0 = load i32* @g, align 4 + br label %return + +return: ; preds = %entry, %if.then + %retval = phi i32 [ %0, %if.then ], [ 0, %entry ] + ret i32 %retval +; CHECK-LABEL: @TestTsan +; CHECK: br i1 +; CHECK: load i32* @g +; CHECK: br label +; CHECK: ret i32 +} diff --git a/test/Transforms/SimplifyCFG/preserve-branchweights.ll b/test/Transforms/SimplifyCFG/preserve-branchweights.ll index 4022ed6927ee..bdd25ba80585 100644 --- a/test/Transforms/SimplifyCFG/preserve-branchweights.ll +++ b/test/Transforms/SimplifyCFG/preserve-branchweights.ll @@ -87,7 +87,7 @@ entry: i32 2, label %sw.bb i32 3, label %sw.bb1 ], !prof !3 -; CHECK: test5 +; CHECK-LABEL: @test5( ; CHECK: switch i32 %N, label %sw2 [ ; CHECK: i32 3, label %sw.bb1 ; CHECK: i32 2, label %sw.bb @@ -119,7 +119,7 @@ entry: i32 2, label %sw.bb i32 3, label %sw.bb1 ], !prof !4 -; CHECK: test6 +; CHECK-LABEL: @test6( ; CHECK: switch i32 %N, label %sw.epilog ; CHECK: i32 3, label %sw.bb1 ; CHECK: i32 2, label %sw.bb @@ -266,7 +266,7 @@ lor.end: call void @helper(i32 0) nounwind ret void -; CHECK: test10 +; CHECK-LABEL: @test10( ; CHECK: %x.off = add i32 %x, -1 ; CHECK: %switch = icmp ult i32 %x.off, 3 ; CHECK: br i1 %switch, label %lor.end, label %lor.rhs, !prof !8 @@ -279,6 +279,7 @@ define void @test11(i32 %x) nounwind { i32 21, label %b i32 24, label %c ], !prof !8 +; CHECK-LABEL: @test11( ; CHECK: %cond = icmp eq i32 %i, 24 ; CHECK: br i1 %cond, label %c, label %a, !prof !9 @@ -293,6 +294,76 @@ c: ret void } +;; test12 - Don't crash if the whole switch is removed +define void @test12(i32 %M, i32 %N) nounwind uwtable { +entry: + switch i32 %N, label %sw.bb [ + i32 1, label %sw.bb + ], !prof !9 +; CHECK-LABEL: @test12( +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @helper +; CHECK-NEXT: ret void + +sw.bb: + call void @helper(i32 0) + br label %sw.epilog + +sw.epilog: + ret void +} + +;; If every case is dead, make sure they are all removed. This used to +;; crash trying to merge the metadata. +define void @test13(i32 %x) nounwind { +entry: + %i = shl i32 %x, 1 + switch i32 %i, label %a [ + i32 21, label %b + i32 25, label %c + ], !prof !8 +; CHECK-LABEL: @test13( +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @helper +; CHECK-NEXT: ret void + +a: + call void @helper(i32 0) nounwind + ret void +b: + call void @helper(i32 1) nounwind + ret void +c: + call void @helper(i32 2) nounwind + ret void +} + +;; When folding branches to common destination, the updated branch weights +;; can exceed uint32 by more than factor of 2. We should keep halving the +;; weights until they can fit into uint32. +@max_regno = common global i32 0, align 4 +define void @test14(i32* %old, i32 %final) { +; CHECK-LABEL: @test14 +; CHECK: br i1 %or.cond, label %for.exit, label %for.inc, !prof !10 +for.cond: + br label %for.cond2 +for.cond2: + %i.1 = phi i32 [ %inc19, %for.inc ], [ 0, %for.cond ] + %bit.0 = phi i32 [ %shl, %for.inc ], [ 1, %for.cond ] + %tobool = icmp eq i32 %bit.0, 0 + br i1 %tobool, label %for.exit, label %for.body3, !prof !10 +for.body3: + %v3 = load i32* @max_regno, align 4 + %cmp4 = icmp eq i32 %i.1, %v3 + br i1 %cmp4, label %for.exit, label %for.inc, !prof !11 +for.inc: + %shl = shl i32 %bit.0, 1 + %inc19 = add nsw i32 %i.1, 1 + br label %for.cond2 +for.exit: + ret void +} + !0 = metadata !{metadata !"branch_weights", i32 3, i32 5} !1 = metadata !{metadata !"branch_weights", i32 1, i32 1} !2 = metadata !{metadata !"branch_weights", i32 1, i32 2} @@ -302,6 +373,9 @@ c: !6 = metadata !{metadata !"branch_weights", i32 1, i32 3} !7 = metadata !{metadata !"branch_weights", i32 33, i32 9, i32 8, i32 7} !8 = metadata !{metadata !"branch_weights", i32 33, i32 9, i32 8} +!9 = metadata !{metadata !"branch_weights", i32 7, i32 6} +!10 = metadata !{metadata !"branch_weights", i32 672646, i32 21604207} +!11 = metadata !{metadata !"branch_weights", i32 6960, i32 21597248} ; CHECK: !0 = metadata !{metadata !"branch_weights", i32 5, i32 11} ; CHECK: !1 = metadata !{metadata !"branch_weights", i32 1, i32 5} @@ -313,4 +387,6 @@ c: ; CHECK: !7 = metadata !{metadata !"branch_weights", i32 17, i32 9, i32 8, i32 7, i32 17} ; CHECK: !8 = metadata !{metadata !"branch_weights", i32 24, i32 33} ; CHECK: !9 = metadata !{metadata !"branch_weights", i32 8, i32 33} -; CHECK-NOT: !9 +;; The false weight prints out as a negative integer here, but inside llvm, we +;; treat the weight as an unsigned integer. +; CHECK: !10 = metadata !{metadata !"branch_weights", i32 112017436, i32 -735157296} diff --git a/test/Transforms/SimplifyCFG/speculate-math.ll b/test/Transforms/SimplifyCFG/speculate-math.ll new file mode 100644 index 000000000000..fa7976d0689f --- /dev/null +++ b/test/Transforms/SimplifyCFG/speculate-math.ll @@ -0,0 +1,58 @@ +; RUN: opt -S -simplifycfg -phi-node-folding-threshold=2 < %s | FileCheck %s + +declare float @llvm.sqrt.f32(float) nounwind readonly +declare float @llvm.fma.f32(float, float, float) nounwind readonly +declare float @llvm.fmuladd.f32(float, float, float) nounwind readonly + +; CHECK-LABEL: @sqrt_test( +; CHECK: select +define void @sqrt_test(float addrspace(1)* noalias nocapture %out, float %a) nounwind { +entry: + %cmp.i = fcmp olt float %a, 0.000000e+00 + br i1 %cmp.i, label %test_sqrt.exit, label %cond.else.i + +cond.else.i: ; preds = %entry + %0 = tail call float @llvm.sqrt.f32(float %a) nounwind readnone + br label %test_sqrt.exit + +test_sqrt.exit: ; preds = %cond.else.i, %entry + %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] + store float %cond.i, float addrspace(1)* %out, align 4 + ret void +} + + +; CHECK-LABEL: @fma_test( +; CHECK: select +define void @fma_test(float addrspace(1)* noalias nocapture %out, float %a, float %b, float %c) nounwind { +entry: + %cmp.i = fcmp olt float %a, 0.000000e+00 + br i1 %cmp.i, label %test_fma.exit, label %cond.else.i + +cond.else.i: ; preds = %entry + %0 = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone + br label %test_fma.exit + +test_fma.exit: ; preds = %cond.else.i, %entry + %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] + store float %cond.i, float addrspace(1)* %out, align 4 + ret void +} + +; CHECK-LABEL: @fmuladd_test( +; CHECK: select +define void @fmuladd_test(float addrspace(1)* noalias nocapture %out, float %a, float %b, float %c) nounwind { +entry: + %cmp.i = fcmp olt float %a, 0.000000e+00 + br i1 %cmp.i, label %test_fmuladd.exit, label %cond.else.i + +cond.else.i: ; preds = %entry + %0 = tail call float @llvm.fmuladd.f32(float %a, float %b, float %c) nounwind readnone + br label %test_fmuladd.exit + +test_fmuladd.exit: ; preds = %cond.else.i, %entry + %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ] + store float %cond.i, float addrspace(1)* %out, align 4 + ret void +} + diff --git a/test/Transforms/SimplifyCFG/speculate-vector-ops.ll b/test/Transforms/SimplifyCFG/speculate-vector-ops.ll new file mode 100644 index 000000000000..91972eb5dd9f --- /dev/null +++ b/test/Transforms/SimplifyCFG/speculate-vector-ops.ll @@ -0,0 +1,60 @@ +; RUN: opt -S -simplifycfg < %s | FileCheck %s + +define i32 @speculate_vector_extract(i32 %d, <4 x i32> %v) #0 { +; CHECK-LABEL: @speculate_vector_extract( +; CHECK-NOT: br +entry: + %conv = insertelement <4 x i32> undef, i32 %d, i32 0 + %conv2 = insertelement <4 x i32> %conv, i32 %d, i32 1 + %conv3 = insertelement <4 x i32> %conv2, i32 %d, i32 2 + %conv4 = insertelement <4 x i32> %conv3, i32 %d, i32 3 + %tmp6 = add nsw <4 x i32> %conv4, <i32 0, i32 -1, i32 -2, i32 -3> + %cmp = icmp eq <4 x i32> %tmp6, zeroinitializer + %cmp.ext = sext <4 x i1> %cmp to <4 x i32> + %tmp8 = extractelement <4 x i32> %cmp.ext, i32 0 + %tobool = icmp eq i32 %tmp8, 0 + br i1 %tobool, label %cond.else, label %cond.then + +return: ; preds = %cond.end28 + ret i32 %cond32 + +cond.then: ; preds = %entry + %tmp10 = extractelement <4 x i32> %v, i32 0 + br label %cond.end + +cond.else: ; preds = %entry + %tmp12 = extractelement <4 x i32> %v, i32 3 + br label %cond.end + +cond.end: ; preds = %cond.else, %cond.then + %cond = phi i32 [ %tmp10, %cond.then ], [ %tmp12, %cond.else ] + %tmp14 = extractelement <4 x i32> %cmp.ext, i32 1 + %tobool15 = icmp eq i32 %tmp14, 0 + br i1 %tobool15, label %cond.else17, label %cond.then16 + +cond.then16: ; preds = %cond.end + %tmp20 = extractelement <4 x i32> %v, i32 1 + br label %cond.end18 + +cond.else17: ; preds = %cond.end + br label %cond.end18 + +cond.end18: ; preds = %cond.else17, %cond.then16 + %cond22 = phi i32 [ %tmp20, %cond.then16 ], [ %cond, %cond.else17 ] + %tmp24 = extractelement <4 x i32> %cmp.ext, i32 2 + %tobool25 = icmp eq i32 %tmp24, 0 + br i1 %tobool25, label %cond.else27, label %cond.then26 + +cond.then26: ; preds = %cond.end18 + %tmp30 = extractelement <4 x i32> %v, i32 2 + br label %cond.end28 + +cond.else27: ; preds = %cond.end18 + br label %cond.end28 + +cond.end28: ; preds = %cond.else27, %cond.then26 + %cond32 = phi i32 [ %tmp30, %cond.then26 ], [ %cond22, %cond.else27 ] + br label %return +} + +attributes #0 = { nounwind } diff --git a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll index e9d93e834a50..5ae62af54581 100644 --- a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll +++ b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll @@ -65,7 +65,7 @@ define void @test5(i1 %C, i32* %P) { entry: br i1 %C, label %T, label %F T: - cmpxchg volatile i32* %P, i32 0, i32 1 seq_cst + cmpxchg volatile i32* %P, i32 0, i32 1 seq_cst seq_cst unreachable F: ret void diff --git a/test/Transforms/Sink/basic.ll b/test/Transforms/Sink/basic.ll index 85ab3766002d..4aac6d613a8c 100644 --- a/test/Transforms/Sink/basic.ll +++ b/test/Transforms/Sink/basic.ll @@ -62,3 +62,82 @@ X: ; preds = %5, %3 ret i32 %R } +; We shouldn't sink constant sized allocas from the entry block, since CodeGen +; interprets allocas outside the entry block as dynamically sized stack objects. + +; CHECK-LABEL: @alloca_nosink +; CHECK: entry: +; CHECK-NEXT: alloca +define i32 @alloca_nosink(i32 %a, i32 %b) { +entry: + %0 = alloca i32 + %1 = icmp ne i32 %a, 0 + br i1 %1, label %if, label %endif + +if: + %2 = getelementptr i32* %0, i32 1 + store i32 0, i32* %0 + store i32 1, i32* %2 + %3 = getelementptr i32* %0, i32 %b + %4 = load i32* %3 + ret i32 %4 + +endif: + ret i32 0 +} + +; Make sure we sink dynamic sized allocas + +; CHECK-LABEL: @alloca_sink_dynamic +; CHECK: entry: +; CHECK-NOT: alloca +; CHECK: if: +; CHECK-NEXT: alloca +define i32 @alloca_sink_dynamic(i32 %a, i32 %b, i32 %size) { +entry: + %0 = alloca i32, i32 %size + %1 = icmp ne i32 %a, 0 + br i1 %1, label %if, label %endif + +if: + %2 = getelementptr i32* %0, i32 1 + store i32 0, i32* %0 + store i32 1, i32* %2 + %3 = getelementptr i32* %0, i32 %b + %4 = load i32* %3 + ret i32 %4 + +endif: + ret i32 0 +} + +; We also want to sink allocas that are not in the entry block. These +; will already be considered as dynamically sized stack objects, so sinking +; them does no further damage. + +; CHECK-LABEL: @alloca_sink_nonentry +; CHECK: if0: +; CHECK-NOT: alloca +; CHECK: if: +; CHECK-NEXT: alloca +define i32 @alloca_sink_nonentry(i32 %a, i32 %b, i32 %c) { +entry: + %cmp = icmp ne i32 %c, 0 + br i1 %cmp, label %endif, label %if0 + +if0: + %0 = alloca i32 + %1 = icmp ne i32 %a, 0 + br i1 %1, label %if, label %endif + +if: + %2 = getelementptr i32* %0, i32 1 + store i32 0, i32* %0 + store i32 1, i32* %2 + %3 = getelementptr i32* %0, i32 %b + %4 = load i32* %3 + ret i32 %4 + +endif: + ret i32 0 +} diff --git a/test/Transforms/StripSymbols/2010-08-25-crash.ll b/test/Transforms/StripSymbols/2010-08-25-crash.ll index 28784686bb68..b55ac3c08245 100644 --- a/test/Transforms/StripSymbols/2010-08-25-crash.ll +++ b/test/Transforms/StripSymbols/2010-08-25-crash.ll @@ -9,7 +9,7 @@ entry: !0 = metadata !{i32 524334, metadata !10, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 524329, metadata !10} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, metadata !10, i32 12, metadata !"clang version 2.8 (trunk 112062)", i1 true, metadata !"", i32 0, metadata !11, metadata !11, metadata !12, metadata !13, null, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 524305, metadata !10, i32 12, metadata !"clang version 2.8 (trunk 112062)", i1 true, metadata !"", i32 0, metadata !11, metadata !11, metadata !12, metadata !13, null, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 524309, metadata !10, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !4 = metadata !{metadata !5} !5 = metadata !{i32 524324, metadata !10, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/Transforms/StripSymbols/strip-dead-debug-info.ll b/test/Transforms/StripSymbols/strip-dead-debug-info.ll index 2d687ae65470..8ce7b87c8250 100644 --- a/test/Transforms/StripSymbols/strip-dead-debug-info.ll +++ b/test/Transforms/StripSymbols/strip-dead-debug-info.ll @@ -30,7 +30,7 @@ attributes #2 = { nounwind readonly ssp } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!25} -!0 = metadata !{i32 524305, metadata !1, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !23, metadata !24, null, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp//g.c] [DW_LANG_C89] +!0 = metadata !{i32 524305, metadata !1, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !23, metadata !24, null, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/tmp//g.c] [DW_LANG_C89] !1 = metadata !{metadata !"g.c", metadata !"/tmp/"} !2 = metadata !{null} !3 = metadata !{i32 524334, metadata !1, null, metadata !"bar", metadata !"bar", metadata !"", i32 5, metadata !4, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ] [line 5] [local] [def] [scope 0] [bar] diff --git a/test/Transforms/TailCallElim/basic.ll b/test/Transforms/TailCallElim/basic.ll index 35420ab08c33..8e9814b52bbc 100644 --- a/test/Transforms/TailCallElim/basic.ll +++ b/test/Transforms/TailCallElim/basic.ll @@ -143,3 +143,48 @@ cond_false: call void @noarg() ret i32* null } + +; Don't tail call if a byval arg is captured. +define void @test9(i32* byval %a) { +; CHECK-LABEL: define void @test9( +; CHECK: {{^ *}}call void @use( + call void @use(i32* %a) + ret void +} + +%struct.X = type { i8* } + +declare void @ctor(%struct.X*) +define void @test10(%struct.X* noalias sret %agg.result, i1 zeroext %b) { +; CHECK-LABEL @test10 +entry: + %x = alloca %struct.X, align 8 + br i1 %b, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @ctor(%struct.X* %agg.result) +; CHECK: tail call void @ctor + br label %return + +if.end: + call void @ctor(%struct.X* %x) +; CHECK: call void @ctor + br label %return + +return: + ret void +} + +declare void @test11_helper1(i8** nocapture, i8*) +declare void @test11_helper2(i8*) +define void @test11() { +; CHECK-LABEL: @test11 +; CHECK-NOT: tail + %a = alloca i8* + %b = alloca i8 + call void @test11_helper1(i8** %a, i8* %b) ; a = &b + %c = load i8** %a + call void @test11_helper2(i8* %c) +; CHECK: call void @test11_helper2 + ret void +} diff --git a/test/Transforms/TailDup/X86/lit.local.cfg b/test/Transforms/TailDup/X86/lit.local.cfg index ba763cf03ffc..e71f3cc4c41e 100644 --- a/test/Transforms/TailDup/X86/lit.local.cfg +++ b/test/Transforms/TailDup/X86/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/Transforms/TailDup/lit.local.cfg b/test/Transforms/TailDup/lit.local.cfg index 19840aa7574c..c8625f4d9d24 100644 --- a/test/Transforms/TailDup/lit.local.cfg +++ b/test/Transforms/TailDup/lit.local.cfg @@ -1,3 +1,2 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True |