vendor/llvm/llvm-trunk-r300890

28 files changed, 4842 insertions, 95 deletions

diff --git a/test/Transforms/CodeGenPrepare/split-indirect-loop.ll b/test/Transforms/CodeGenPrepare/split-indirect-loop.ll
new file mode 100644
index 000000000000..cb834bb5dd8f
--- /dev/null
+++ b/test/Transforms/CodeGenPrepare/split-indirect-loop.ll
@@ -0,0 +1,37 @@
+; RUN: opt -codegenprepare -S < %s | FileCheck %s
+
+; Test that an invalid CFG is not created by splitIndirectCriticalEdges
+; transformation when the 'target' block is a loop to itself.
+
+; CHECK: .split:
+; CHECK: br label %while.body.clone
+; CHECK: if.else1:
+; CHECK: indirectbr
+; CHECK: while.body.clone:
+; CHECK: br label %.split
+
+define void @test() {
+entry:
+  br label %if.else
+
+if.else:
+  br i1 undef, label %while.body, label %preheader
+
+preheader:
+  br label %if.else1
+
+if.then:
+  unreachable
+
+while.body:
+  %dest.sroa = phi i32 [ %1, %while.body ], [ undef, %if.else1 ], [ undef, %if.else ]
+  %0 = inttoptr i32 %dest.sroa to i8*
+  %incdec.ptr = getelementptr inbounds i8, i8* %0, i32 -1
+  %1 = ptrtoint i8* %incdec.ptr to i32
+  store i8 undef, i8* %incdec.ptr, align 1
+  br label %while.body
+
+if.else1:
+  indirectbr i8* undef, [label %if.then, label %while.body, label %if.else, label %if.else1]
+}
+
diff --git a/test/Transforms/GVN/non-integral-pointers.ll b/test/Transforms/GVN/non-integral-pointers.ll
new file mode 100644
index 000000000000..9ae4132231d8
--- /dev/null
+++ b/test/Transforms/GVN/non-integral-pointers.ll
@@ -0,0 +1,39 @@
+; RUN: opt -gvn -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:4"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @f0(i1 %alwaysFalse, i64 %val, i64* %loc) {
+; CHECK-LABEL: @f0(
+; CHECK-NOT: inttoptr
+; CHECK-NOT: ptrtoint
+ entry:
+  store i64 %val, i64* %loc
+  br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
+
+ neverTaken:
+  %loc.bc = bitcast i64* %loc to i8 addrspace(4)**
+  %ptr = load i8 addrspace(4)*, i8 addrspace(4)** %loc.bc
+  store i8 5, i8 addrspace(4)* %ptr
+  ret void
+
+ alwaysTaken:
+  ret void
+}
+
+define i64 @f1(i1 %alwaysFalse, i8 addrspace(4)* %val, i8 addrspace(4)** %loc) {
+; CHECK-LABEL: @f1(
+; CHECK-NOT: inttoptr
+; CHECK-NOT: ptrtoint
+ entry:
+  store i8 addrspace(4)* %val, i8 addrspace(4)** %loc
+  br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
+
+ neverTaken:
+  %loc.bc = bitcast i8 addrspace(4)** %loc to i64*
+  %int = load i64, i64* %loc.bc
+  ret i64 %int
+
+ alwaysTaken:
+  ret i64 42
+}
diff --git a/test/Transforms/InstCombine/2008-01-13-NoBitCastAttributes.ll b/test/Transforms/InstCombine/2008-01-13-NoBitCastAttributes.ll
deleted file mode 100644
index 510a68c3437e..000000000000
--- a/test/Transforms/InstCombine/2008-01-13-NoBitCastAttributes.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: opt < %s -instcombine -S | grep bitcast | count 2
-
-define signext i32 @b(i32* inreg  %x)   {
-	ret i32 0
-}
-
-define void @c(...) {
-	ret void
-}
-
-define void @g(i32* %y) {
-	call i32 bitcast (i32 (i32*)* @b to i32 (i32)*)( i32 zeroext  0 )		; <i32>:2 [#uses=0]
-	call void bitcast (void (...)* @c to void (i32*)*)( i32* sret  null )
-	ret void
-}
diff --git a/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll b/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll
index 888f51bf939d..0c4842c15988 100644
--- a/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll
+++ b/test/Transforms/InstCombine/amdgcn-demanded-vector-elts.ll
@@ -227,6 +227,12 @@ define amdgpu_ps float @preserve_metadata_extract_elt0_buffer_load_v2f32(<4 x i3
   ret float %elt0
 }
 
+declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1
+
 ; --------------------------------------------------------------------
 ; llvm.amdgcn.buffer.load.format
 ; --------------------------------------------------------------------
@@ -304,18 +310,1196 @@ define i16 @extract_lo16_0_bitcast_buffer_load_format_v4f32(i32 %arg) #0 {
   ret i16 %tmp2
 }
 
-declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32>, i32, i32, i1, i1) #1
-declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1
-
 declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1
 declare <1 x float> @llvm.amdgcn.buffer.load.format.v1f32(<4 x i32>, i32, i32, i1, i1) #1
 declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #1
 declare <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32>, i32, i32, i1, i1) #1
 declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
 
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_v4f32_v4f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_v4f32_v2f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_invalid_dmask_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 %dmask, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_invalid_dmask_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc, i32 %dmask) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 %dmask, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; FIXME: Should really fold to undef
+; CHECK-LABEL: @extract_elt0_dmask_0000_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0000_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 0, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0001_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0001_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; FIXME: Should really fold to undef
+; CHECK-LABEL: @extract_elt0_dmask_0010_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 2, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0010_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 2, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; FIXME: Should really fold to undef
+; CHECK-LABEL: @extract_elt0_dmask_0100_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 4, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0100_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 4, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; FIXME: Should really fold to undef
+; CHECK-LABEL: @extract_elt0_dmask_1000_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 8, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_1000_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 8, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_1001_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_1001_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 9, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0011_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0011_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0111_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0111_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 7, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.v2f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_dmask_0011_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.v2f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0011_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_dmask_0111_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.v2f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0111_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 7, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_dmask_0101_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.v2f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0101_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0011_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0011_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0101_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0101_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0111_image_sample_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 7, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0111_image_sample_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 7, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.d
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_d_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_d_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.d.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.d.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.d.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_d_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_d_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.d.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.d.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.l
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_l_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.l.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_l_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.l.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.l.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.b
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_b_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_b_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.b.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.b.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.b.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_b_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_b_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.b.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.b.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.lz
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_lz_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.lz.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_lz_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.lz.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.lz.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cd
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cd_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cd_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cd.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cd.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cd.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cd_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cd_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_v4f32_v4f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_v4f32_v2f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.d
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_d_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_d_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.d.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_d_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_d_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.l
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_l_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.l.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_l_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.l.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.l.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.b
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_b_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_b_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.b.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.b.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_b_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_b_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.lz
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_lz_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.lz.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_lz_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.lz.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.lz.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cd
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cd_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cd_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cd.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cd.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cd_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.cl.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cd_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_o_v4f32_v4f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.o.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_o_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_o_v4f32_v2f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.o.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_o_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.sample.o.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.d.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_d_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_d_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.d.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.d.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.d.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_d_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_d_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.d.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.l.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_l_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.l.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_l_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.l.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.b.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_b_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_b_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.b.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.b.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_b_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_b_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.b.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.lz.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_lz_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.lz.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_lz_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.lz.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cd.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cd_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cd_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cd.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cd.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cd.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cd_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cd_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_o_v4f32_v4f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.o.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_o_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_o_v4f32_v2f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.o.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_o_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.d.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_d_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_d_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.d.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_d_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_d_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.l.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_l_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.l.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_l_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.b.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_b_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_b_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.b.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_b_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_b_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.lz.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_lz_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.lz.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_lz_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.lz.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cd.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cd_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cd_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cd.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cd.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cd_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.cl.o.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cd_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4
+; --------------------------------------------------------------------
+
+; Don't handle gather4*
+
+; CHECK-LABEL: @extract_elt0_image_gather4_v4f32_v4f32_v8i32(
+; CHECK: %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i3
+define amdgpu_ps float @extract_elt0_image_gather4_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_gather4_v4f32_v4f32_v4i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_gather4_v4f32_v2f32_v4i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.gather4.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.gather4.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.l
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_l_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.l.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_l_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.l.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.l.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.b
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_b_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_b_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.b.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.b.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.b.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_b_cl_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_b_cl_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.lz
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_lz_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_lz_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_gather4_o_v4f32_v4f32_v4i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_o_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_gather4_o_v4f32_v2f32_v4i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_o_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.gather4.o.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.l.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_l_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_l_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.l.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.b.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_b_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_b_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.b.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.b.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_b_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_b_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.lz.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_lz_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_lz_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.lz.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_c_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_o_v4f32_v4f32_v4i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_c_o_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_o_v4f32_v2f32_v4i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_c_o_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_c_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.l.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_l_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_c_l_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.b.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_b_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_c_b_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.b.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_b_cl_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_c_b_cl_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.lz.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_lz_o_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+define amdgpu_ps float @extract_elt0_image_gather4_c_lz_o_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %gather4r, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.getlod
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_getlod_v4f32_v4f32_v8i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getlod.f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_getlod_v4f32_v4f32_v8i32(<4 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.getlod.v4f32.v4f32.v8i32(<4 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_getlod_v4f32_v4f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getlod.f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_getlod_v4f32_v4f32_v4i32(<4 x float> %vaddr, <4 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.getlod.v4f32.v4f32.v4i32(<4 x float> %vaddr, <4 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_getlod_v4f32_v2f32_v4i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getlod.f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 1, i1 false, i1 false, i1 false, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_getlod_v4f32_v2f32_v4i32(<2 x float> %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.getlod.v4f32.v2f32.v8i32(<2 x float> %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.getlod.v4f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.getlod.v4f32.v4f32.v4i32(<4 x float>, <4 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.image.getlod.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1
+
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readonly }
 
diff --git a/test/Transforms/InstCombine/call-cast-attrs.ll b/test/Transforms/InstCombine/call-cast-attrs.ll
new file mode 100644
index 000000000000..ddaf90c3e74f
--- /dev/null
+++ b/test/Transforms/InstCombine/call-cast-attrs.ll
@@ -0,0 +1,29 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define signext i32 @b(i32* inreg %x)   {
+  ret i32 0
+}
+
+define void @c(...) {
+  ret void
+}
+
+declare void @useit(i32)
+
+define void @d(i32 %x, ...) {
+  call void @useit(i32 %x)
+  ret void
+}
+
+define void @g(i32* %y) {
+  call i32 bitcast (i32 (i32*)* @b to i32 (i32)*)(i32 zeroext 0)
+  call void bitcast (void (...)* @c to void (i32*)*)(i32* %y)
+  call void bitcast (void (...)* @c to void (i32*)*)(i32* sret %y)
+  call void bitcast (void (i32, ...)* @d to void (i32, i32*)*)(i32 0, i32* sret %y)
+  ret void
+}
+; CHECK-LABEL: define void @g(i32* %y)
+; CHECK: call i32 bitcast (i32 (i32*)* @b to i32 (i32)*)(i32 zeroext 0)
+; CHECK: call void (...) @c(i32* %y)
+; CHECK: call void bitcast (void (...)* @c to void (i32*)*)(i32* sret %y)
+; CHECK: call void bitcast (void (i32, ...)* @d to void (i32, i32*)*)(i32 0, i32* sret %y)
diff --git a/test/Transforms/InstCombine/constant-fold-math.ll b/test/Transforms/InstCombine/constant-fold-math.ll
index 50cd6070896e..27578387f827 100644
--- a/test/Transforms/InstCombine/constant-fold-math.ll
+++ b/test/Transforms/InstCombine/constant-fold-math.ll
@@ -45,4 +45,22 @@ define double @constant_fold_fmuladd_f64() #0 {
   ret double %x
 }
 
+; PR32177
+
+; CHECK-LABEL: @constant_fold_frem_f32
+; CHECK-NEXT: ret float 0x41A61B2000000000
+define float @constant_fold_frem_f32() #0 {
+  %x = frem float 0x43cbfcd960000000, 0xc1e2b34a00000000
+  ret float %x
+}
+
+; PR3316
+
+; CHECK-LABEL: @constant_fold_frem_f64
+; CHECK-NEXT: ret double 0.000000e+00
+define double @constant_fold_frem_f64() {
+  %x = frem double 0x43E0000000000000, 1.000000e+00
+  ret double %x
+}
+
 attributes #0 = { nounwind readnone }
diff --git a/test/Transforms/InstCombine/div-shift.ll b/test/Transforms/InstCombine/div-shift.ll
index 517313ed8e4e..b5a65048fda0 100644
--- a/test/Transforms/InstCombine/div-shift.ll
+++ b/test/Transforms/InstCombine/div-shift.ll
@@ -16,6 +16,21 @@ entry:
   ret i32 %d
 }
 
+define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
+; CHECK-LABEL: @t1vec(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[TMP0:%.*]] = add <2 x i32> [[Y:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[D:%.*]] = lshr <2 x i32> [[CONV]], [[TMP0]]
+; CHECK-NEXT:    ret <2 x i32> [[D]]
+;
+entry:
+  %conv = zext <2 x i16> %x to <2 x i32>
+  %s = shl <2 x i32> <i32 2, i32 2>, %y
+  %d = sdiv <2 x i32> %conv, %s
+  ret <2 x i32> %d
+}
+
 ; rdar://11721329
 define i64 @t2(i64 %x, i32 %y) {
 ; CHECK-LABEL: @t2(
diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll
index a037607267ac..796fce020fd3 100644
--- a/test/Transforms/InstCombine/div.ll
+++ b/test/Transforms/InstCombine/div.ll
@@ -225,6 +225,16 @@ define i32 @test19(i32 %x) {
   ret i32 %A
 }
 
+define <2 x i32> @test19vec(<2 x i32> %x) {
+; CHECK-LABEL: @test19vec(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[A:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[A]]
+;
+  %A = udiv <2 x i32> <i32 1, i32 1>, %x
+  ret <2 x i32> %A
+}
+
 define i32 @test20(i32 %x) {
 ; CHECK-LABEL: @test20(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 %x, 1
@@ -236,6 +246,17 @@ define i32 @test20(i32 %x) {
   ret i32 %A
 }
 
+define <2 x i32> @test20vec(<2 x i32> %x) {
+; CHECK-LABEL: @test20vec(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 3, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[X]], <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[A]]
+;
+  %A = sdiv <2 x i32> <i32 1, i32 1>, %x
+  ret <2 x i32> %A
+}
+
 define i32 @test21(i32 %a) {
 ; CHECK-LABEL: @test21(
 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, 3
@@ -388,6 +409,17 @@ define i32 @test35(i32 %A) {
   ret i32 %mul
 }
 
+define <2 x i32> @test35vec(<2 x i32> %A) {
+; CHECK-LABEL: @test35vec(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    [[MUL:%.*]] = udiv exact <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    ret <2 x i32> [[MUL]]
+;
+  %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
+  %mul = sdiv exact <2 x i32> %and, <i32 2147483647, i32 2147483647>
+  ret <2 x i32> %mul
+}
+
 define i32 @test36(i32 %A) {
 ; CHECK-LABEL: @test36(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %A, 2147483647
@@ -400,13 +432,10 @@ define i32 @test36(i32 %A) {
   ret i32 %mul
 }
 
-; FIXME: Vector should get same transform as scalar.
-
 define <2 x i32> @test36vec(<2 x i32> %A) {
 ; CHECK-LABEL: @test36vec(
-; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
-; CHECK-NEXT:    [[SHL:%.*]] = shl nuw nsw <2 x i32> <i32 1, i32 1>, %A
-; CHECK-NEXT:    [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], [[SHL]]
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    [[MUL:%.*]] = lshr exact <2 x i32> [[AND]], [[A]]
 ; CHECK-NEXT:    ret <2 x i32> [[MUL]]
 ;
   %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
diff --git a/test/Transforms/InstCombine/pr32686.ll b/test/Transforms/InstCombine/pr32686.ll
new file mode 100644
index 000000000000..b2d2aff2fde8
--- /dev/null
+++ b/test/Transforms/InstCombine/pr32686.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine %s | FileCheck %s
+
+@a = external global i8
+@b = external global i32
+
+define void @tinkywinky() {
+; CHECK-LABEL: @tinkywinky(
+; CHECK-NEXT:    [[PATATINO:%.*]] = load i8, i8* @a, align 1
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i8 [[PATATINO]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i1 [[TOBOOL]] to i32
+; CHECK-NEXT:    [[OR1:%.*]] = or i32 [[TMP1]], or (i32 zext (i1 icmp ne (i32* bitcast (i8* @a to i32*), i32* @b) to i32), i32 2)
+; CHECK-NEXT:    store i32 [[OR1]], i32* @b, align 4
+; CHECK-NEXT:    ret void
+;
+  %patatino = load i8, i8* @a
+  %tobool = icmp ne i8 %patatino, 0
+  %lnot = xor i1 %tobool, true
+  %lnot.ext = zext i1 %lnot to i32
+  %or = or i32 xor (i32 zext (i1 icmp ne (i32* bitcast (i8* @a to i32*), i32* @b) to i32), i32 2), %lnot.ext
+  store i32 %or, i32* @b, align 4
+  ret void
+}
diff --git a/test/Transforms/InstCombine/rem.ll b/test/Transforms/InstCombine/rem.ll
index 7a7a134db9c5..86a3580189fd 100644
--- a/test/Transforms/InstCombine/rem.ll
+++ b/test/Transforms/InstCombine/rem.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i64 @rem_signed(i64 %x1, i64 %y2) {
@@ -571,3 +572,24 @@ rem.is.unsafe:
   ret i32 0
 }
 
+define i32 @test22(i32 %A) {
+; CHECK-LABEL: @test22(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[A:%.*]], 2147483647
+; CHECK-NEXT:    [[MUL:%.*]] = urem i32 [[AND]], 2147483647
+; CHECK-NEXT:    ret i32 [[MUL]]
+;
+  %and = and i32 %A, 2147483647
+  %mul = srem i32 %and, 2147483647
+  ret i32 %mul
+}
+
+define <2 x i32> @test23(<2 x i32> %A) {
+; CHECK-LABEL: @test23(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    [[MUL:%.*]] = urem <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    ret <2 x i32> [[MUL]]
+;
+  %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
+  %mul = srem <2 x i32> %and, <i32 2147483647, i32 2147483647>
+  ret <2 x i32> %mul
+}
diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll
index 60ba35557f70..d5f489280a03 100644
--- a/test/Transforms/InstCombine/shift.ll
+++ b/test/Transforms/InstCombine/shift.ll
@@ -1268,3 +1268,23 @@ define <2 x i64> @test_64_splat_vec(<2 x i32> %t) {
   ret <2 x i64> %shl
 }
 
+define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) {
+; CHECK-LABEL: @ashr_demanded_bits_splat(
+; CHECK-NEXT:    [[SHR:%.*]] = ashr <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT:    ret <2 x i8> [[SHR]]
+;
+  %and = and <2 x i8> %x, <i8 128, i8 128>
+  %shr = ashr <2 x i8> %and, <i8 7, i8 7>
+  ret <2 x i8> %shr
+}
+
+define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_demanded_bits_splat(
+; CHECK-NEXT:    [[SHR:%.*]] = lshr <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT:    ret <2 x i8> [[SHR]]
+;
+  %and = and <2 x i8> %x, <i8 128, i8 128>
+  %shr = lshr <2 x i8> %and, <i8 7, i8 7>
+  ret <2 x i8> %shr
+}
+
diff --git a/test/Transforms/InstCombine/vector-casts.ll b/test/Transforms/InstCombine/vector-casts.ll
index 643ab6c5348f..2197c250ace2 100644
--- a/test/Transforms/InstCombine/vector-casts.ll
+++ b/test/Transforms/InstCombine/vector-casts.ll
@@ -15,9 +15,9 @@ define <2 x i1> @test1(<2 x i64> %a) {
 ; The ashr turns into an lshr.
 define <2 x i64> @test2(<2 x i64> %a) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT:    [[B:%.*]] = and <2 x i64> %a, <i64 65535, i64 65535>
-; CHECK-NEXT:    [[T:%.*]] = lshr <2 x i64> [[B]], <i64 1, i64 1>
-; CHECK-NEXT:    ret <2 x i64> [[T]]
+; CHECK-NEXT:    [[B:%.*]] = and <2 x i64> %a, <i64 65534, i64 65534>
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr exact <2 x i64> [[B]], <i64 1, i64 1>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 ;
   %b = and <2 x i64> %a, <i64 65535, i64 65535>
   %t = ashr <2 x i64> %b, <i64 1, i64 1>
diff --git a/test/Transforms/InstSimplify/AndOrXor.ll b/test/Transforms/InstSimplify/AndOrXor.ll
index 33fd978277d4..aa71c6ba86ae 100644
--- a/test/Transforms/InstSimplify/AndOrXor.ll
+++ b/test/Transforms/InstSimplify/AndOrXor.ll
@@ -376,26 +376,6 @@ define i1 @or_icmp3(i32 %x, i32 %y) {
   ret i1 %3
 }
 
-define i1 @disjoint_cmps(i32 %A) {
-; CHECK-LABEL: @disjoint_cmps(
-; CHECK-NEXT:    ret i1 false
-;
-  %B = icmp eq i32 %A, 1
-  %C = icmp sge i32 %A, 3
-  %D = and i1 %B, %C
-  ret i1 %D
-}
-
-define i1 @disjoint_cmps2(i32 %X) {
-; CHECK-LABEL: @disjoint_cmps2(
-; CHECK-NEXT:    ret i1 false
-;
-  %a = icmp ult i32 %X, 31
-  %b = icmp slt i32 %X, 0
-  %c = and i1 %a, %b
-  ret i1 %c
-}
-
 ; PR27869 - Look through casts to eliminate cmps and bitwise logic.
 
 define i32 @and_of_zexted_icmps(i32 %i) {
diff --git a/test/Transforms/InstSimplify/icmp-ranges.ll b/test/Transforms/InstSimplify/icmp-ranges.ll
new file mode 100644
index 000000000000..dcbbe0bc7fb9
--- /dev/null
+++ b/test/Transforms/InstSimplify/icmp-ranges.ll
@@ -0,0 +1,2912 @@
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+; Cycle through all pairs of predicates to test
+; simplification of range-intersection or range-union.
+
+; eq
+; x == 13 && x == 17
+
+define i1 @and_eq_eq(i8 %x) {
+; CHECK-LABEL: @and_eq_eq(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x != 17
+
+define i1 @and_eq_ne(i8 %x) {
+; CHECK-LABEL: @and_eq_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x >=s 17
+
+define i1 @and_eq_sge(i8 %x) {
+; CHECK-LABEL: @and_eq_sge(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x >s 17
+
+define i1 @and_eq_sgt(i8 %x) {
+; CHECK-LABEL: @and_eq_sgt(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x <=s 17
+
+define i1 @and_eq_sle(i8 %x) {
+; CHECK-LABEL: @and_eq_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x <s 17
+
+define i1 @and_eq_slt(i8 %x) {
+; CHECK-LABEL: @and_eq_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x >=u 17
+
+define i1 @and_eq_uge(i8 %x) {
+; CHECK-LABEL: @and_eq_uge(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x >u 17
+
+define i1 @and_eq_ugt(i8 %x) {
+; CHECK-LABEL: @and_eq_ugt(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x <=u 17
+
+define i1 @and_eq_ule(i8 %x) {
+; CHECK-LABEL: @and_eq_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 13 && x <u 17
+
+define i1 @and_eq_ult(i8 %x) {
+; CHECK-LABEL: @and_eq_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; ne
+; x != 13 && x == 17
+
+define i1 @and_ne_eq(i8 %x) {
+; CHECK-LABEL: @and_ne_eq(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x != 17
+
+define i1 @and_ne_ne(i8 %x) {
+; CHECK-LABEL: @and_ne_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x >=s 17
+
+define i1 @and_ne_sge(i8 %x) {
+; CHECK-LABEL: @and_ne_sge(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x >s 17
+
+define i1 @and_ne_sgt(i8 %x) {
+; CHECK-LABEL: @and_ne_sgt(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x <=s 17
+
+define i1 @and_ne_sle(i8 %x) {
+; CHECK-LABEL: @and_ne_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x <s 17
+
+define i1 @and_ne_slt(i8 %x) {
+; CHECK-LABEL: @and_ne_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x >=u 17
+
+define i1 @and_ne_uge(i8 %x) {
+; CHECK-LABEL: @and_ne_uge(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x >u 17
+
+define i1 @and_ne_ugt(i8 %x) {
+; CHECK-LABEL: @and_ne_ugt(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x <=u 17
+
+define i1 @and_ne_ule(i8 %x) {
+; CHECK-LABEL: @and_ne_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 13 && x <u 17
+
+define i1 @and_ne_ult(i8 %x) {
+; CHECK-LABEL: @and_ne_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; sge
+; x >=s 13 && x == 17
+
+define i1 @and_sge_eq(i8 %x) {
+; CHECK-LABEL: @and_sge_eq(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x != 17
+
+define i1 @and_sge_ne(i8 %x) {
+; CHECK-LABEL: @and_sge_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x >=s 17
+
+define i1 @and_sge_sge(i8 %x) {
+; CHECK-LABEL: @and_sge_sge(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x >s 17
+
+define i1 @and_sge_sgt(i8 %x) {
+; CHECK-LABEL: @and_sge_sgt(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x <=s 17
+
+define i1 @and_sge_sle(i8 %x) {
+; CHECK-LABEL: @and_sge_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x <s 17
+
+define i1 @and_sge_slt(i8 %x) {
+; CHECK-LABEL: @and_sge_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x >=u 17
+
+define i1 @and_sge_uge(i8 %x) {
+; CHECK-LABEL: @and_sge_uge(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x >u 17
+
+define i1 @and_sge_ugt(i8 %x) {
+; CHECK-LABEL: @and_sge_ugt(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x <=u 17
+
+define i1 @and_sge_ule(i8 %x) {
+; CHECK-LABEL: @and_sge_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 13 && x <u 17
+
+define i1 @and_sge_ult(i8 %x) {
+; CHECK-LABEL: @and_sge_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; sgt
+; x >s 13 && x == 17
+
+define i1 @and_sgt_eq(i8 %x) {
+; CHECK-LABEL: @and_sgt_eq(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x != 17
+
+define i1 @and_sgt_ne(i8 %x) {
+; CHECK-LABEL: @and_sgt_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x >=s 17
+
+define i1 @and_sgt_sge(i8 %x) {
+; CHECK-LABEL: @and_sgt_sge(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x >s 17
+
+define i1 @and_sgt_sgt(i8 %x) {
+; CHECK-LABEL: @and_sgt_sgt(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x <=s 17
+
+define i1 @and_sgt_sle(i8 %x) {
+; CHECK-LABEL: @and_sgt_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x <s 17
+
+define i1 @and_sgt_slt(i8 %x) {
+; CHECK-LABEL: @and_sgt_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x >=u 17
+
+define i1 @and_sgt_uge(i8 %x) {
+; CHECK-LABEL: @and_sgt_uge(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x >u 17
+
+define i1 @and_sgt_ugt(i8 %x) {
+; CHECK-LABEL: @and_sgt_ugt(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x <=u 17
+
+define i1 @and_sgt_ule(i8 %x) {
+; CHECK-LABEL: @and_sgt_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 13 && x <u 17
+
+define i1 @and_sgt_ult(i8 %x) {
+; CHECK-LABEL: @and_sgt_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; sle
+; x <=s 13 && x == 17
+
+define i1 @and_sle_eq(i8 %x) {
+; CHECK-LABEL: @and_sle_eq(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x != 17
+
+define i1 @and_sle_ne(i8 %x) {
+; CHECK-LABEL: @and_sle_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x >=s 17
+
+define i1 @and_sle_sge(i8 %x) {
+; CHECK-LABEL: @and_sle_sge(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x >s 17
+
+define i1 @and_sle_sgt(i8 %x) {
+; CHECK-LABEL: @and_sle_sgt(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x <=s 17
+
+define i1 @and_sle_sle(i8 %x) {
+; CHECK-LABEL: @and_sle_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x <s 17
+
+define i1 @and_sle_slt(i8 %x) {
+; CHECK-LABEL: @and_sle_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x >=u 17
+
+define i1 @and_sle_uge(i8 %x) {
+; CHECK-LABEL: @and_sle_uge(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x >u 17
+
+define i1 @and_sle_ugt(i8 %x) {
+; CHECK-LABEL: @and_sle_ugt(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x <=u 17
+
+define i1 @and_sle_ule(i8 %x) {
+; CHECK-LABEL: @and_sle_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 13 && x <u 17
+
+define i1 @and_sle_ult(i8 %x) {
+; CHECK-LABEL: @and_sle_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; slt
+; x <s 13 && x == 17
+
+define i1 @and_slt_eq(i8 %x) {
+; CHECK-LABEL: @and_slt_eq(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x != 17
+
+define i1 @and_slt_ne(i8 %x) {
+; CHECK-LABEL: @and_slt_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x >=s 17
+
+define i1 @and_slt_sge(i8 %x) {
+; CHECK-LABEL: @and_slt_sge(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x >s 17
+
+define i1 @and_slt_sgt(i8 %x) {
+; CHECK-LABEL: @and_slt_sgt(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x <=s 17
+
+define i1 @and_slt_sle(i8 %x) {
+; CHECK-LABEL: @and_slt_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x <s 17
+
+define i1 @and_slt_slt(i8 %x) {
+; CHECK-LABEL: @and_slt_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x >=u 17
+
+define i1 @and_slt_uge(i8 %x) {
+; CHECK-LABEL: @and_slt_uge(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x >u 17
+
+define i1 @and_slt_ugt(i8 %x) {
+; CHECK-LABEL: @and_slt_ugt(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x <=u 17
+
+define i1 @and_slt_ule(i8 %x) {
+; CHECK-LABEL: @and_slt_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 13 && x <u 17
+
+define i1 @and_slt_ult(i8 %x) {
+; CHECK-LABEL: @and_slt_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; uge
+; x >=u 13 && x == 17
+
+define i1 @and_uge_eq(i8 %x) {
+; CHECK-LABEL: @and_uge_eq(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x != 17
+
+define i1 @and_uge_ne(i8 %x) {
+; CHECK-LABEL: @and_uge_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x >=s 17
+
+define i1 @and_uge_sge(i8 %x) {
+; CHECK-LABEL: @and_uge_sge(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x >s 17
+
+define i1 @and_uge_sgt(i8 %x) {
+; CHECK-LABEL: @and_uge_sgt(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x <=s 17
+
+define i1 @and_uge_sle(i8 %x) {
+; CHECK-LABEL: @and_uge_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x <s 17
+
+define i1 @and_uge_slt(i8 %x) {
+; CHECK-LABEL: @and_uge_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x >=u 17
+
+define i1 @and_uge_uge(i8 %x) {
+; CHECK-LABEL: @and_uge_uge(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x >u 17
+
+define i1 @and_uge_ugt(i8 %x) {
+; CHECK-LABEL: @and_uge_ugt(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x <=u 17
+
+define i1 @and_uge_ule(i8 %x) {
+; CHECK-LABEL: @and_uge_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 13 && x <u 17
+
+define i1 @and_uge_ult(i8 %x) {
+; CHECK-LABEL: @and_uge_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; ugt
+; x >u 13 && x == 17
+
+define i1 @and_ugt_eq(i8 %x) {
+; CHECK-LABEL: @and_ugt_eq(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x != 17
+
+define i1 @and_ugt_ne(i8 %x) {
+; CHECK-LABEL: @and_ugt_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x >=s 17
+
+define i1 @and_ugt_sge(i8 %x) {
+; CHECK-LABEL: @and_ugt_sge(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x >s 17
+
+define i1 @and_ugt_sgt(i8 %x) {
+; CHECK-LABEL: @and_ugt_sgt(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x <=s 17
+
+define i1 @and_ugt_sle(i8 %x) {
+; CHECK-LABEL: @and_ugt_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x <s 17
+
+define i1 @and_ugt_slt(i8 %x) {
+; CHECK-LABEL: @and_ugt_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x >=u 17
+
+define i1 @and_ugt_uge(i8 %x) {
+; CHECK-LABEL: @and_ugt_uge(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x >u 17
+
+define i1 @and_ugt_ugt(i8 %x) {
+; CHECK-LABEL: @and_ugt_ugt(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x <=u 17
+
+define i1 @and_ugt_ule(i8 %x) {
+; CHECK-LABEL: @and_ugt_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 13 && x <u 17
+
+define i1 @and_ugt_ult(i8 %x) {
+; CHECK-LABEL: @and_ugt_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; ule
+; x <=u 13 && x == 17
+
+define i1 @and_ule_eq(i8 %x) {
+; CHECK-LABEL: @and_ule_eq(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x != 17
+
+define i1 @and_ule_ne(i8 %x) {
+; CHECK-LABEL: @and_ule_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x >=s 17
+
+define i1 @and_ule_sge(i8 %x) {
+; CHECK-LABEL: @and_ule_sge(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x >s 17
+
+define i1 @and_ule_sgt(i8 %x) {
+; CHECK-LABEL: @and_ule_sgt(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x <=s 17
+
+define i1 @and_ule_sle(i8 %x) {
+; CHECK-LABEL: @and_ule_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x <s 17
+
+define i1 @and_ule_slt(i8 %x) {
+; CHECK-LABEL: @and_ule_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x >=u 17
+
+define i1 @and_ule_uge(i8 %x) {
+; CHECK-LABEL: @and_ule_uge(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x >u 17
+
+define i1 @and_ule_ugt(i8 %x) {
+; CHECK-LABEL: @and_ule_ugt(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x <=u 17
+
+define i1 @and_ule_ule(i8 %x) {
+; CHECK-LABEL: @and_ule_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 13 && x <u 17
+
+define i1 @and_ule_ult(i8 %x) {
+; CHECK-LABEL: @and_ule_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; ult
+; x <u 13 && x == 17
+
+define i1 @and_ult_eq(i8 %x) {
+; CHECK-LABEL: @and_ult_eq(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x != 17
+
+define i1 @and_ult_ne(i8 %x) {
+; CHECK-LABEL: @and_ult_ne(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x >=s 17
+
+define i1 @and_ult_sge(i8 %x) {
+; CHECK-LABEL: @and_ult_sge(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x >s 17
+
+define i1 @and_ult_sgt(i8 %x) {
+; CHECK-LABEL: @and_ult_sgt(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x <=s 17
+
+define i1 @and_ult_sle(i8 %x) {
+; CHECK-LABEL: @and_ult_sle(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x <s 17
+
+define i1 @and_ult_slt(i8 %x) {
+; CHECK-LABEL: @and_ult_slt(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x >=u 17
+
+define i1 @and_ult_uge(i8 %x) {
+; CHECK-LABEL: @and_ult_uge(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x >u 17
+
+define i1 @and_ult_ugt(i8 %x) {
+; CHECK-LABEL: @and_ult_ugt(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x <=u 17
+
+define i1 @and_ult_ule(i8 %x) {
+; CHECK-LABEL: @and_ult_ule(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 13 && x <u 17
+
+define i1 @and_ult_ult(i8 %x) {
+; CHECK-LABEL: @and_ult_ult(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 13
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 13
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; eq
+; x == 23 && x == 17
+
+define i1 @and_eq_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_eq_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x != 17
+
+define i1 @and_eq_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x >=s 17
+
+define i1 @and_eq_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x >s 17
+
+define i1 @and_eq_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x <=s 17
+
+define i1 @and_eq_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_sle_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x <s 17
+
+define i1 @and_eq_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_slt_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x >=u 17
+
+define i1 @and_eq_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x >u 17
+
+define i1 @and_eq_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp eq i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x <=u 17
+
+define i1 @and_eq_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_ule_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x == 23 && x <u 17
+
+define i1 @and_eq_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_eq_ult_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp eq i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; ne
+; x != 23 && x == 17
+
+define i1 @and_ne_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_eq_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x != 17
+
+define i1 @and_ne_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x >=s 17
+
+define i1 @and_ne_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x >s 17
+
+define i1 @and_ne_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x <=s 17
+
+define i1 @and_ne_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_sle_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x <s 17
+
+define i1 @and_ne_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_slt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x >=u 17
+
+define i1 @and_ne_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x >u 17
+
+define i1 @and_ne_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x <=u 17
+
+define i1 @and_ne_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_ule_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x != 23 && x <u 17
+
+define i1 @and_ne_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_ne_ult_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ne i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ne i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; sge
+; x >=s 23 && x == 17
+
+define i1 @and_sge_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_eq_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x != 17
+
+define i1 @and_sge_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x >=s 17
+
+define i1 @and_sge_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x >s 17
+
+define i1 @and_sge_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x <=s 17
+
+define i1 @and_sge_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_sle_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x <s 17
+
+define i1 @and_sge_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_slt_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x >=u 17
+
+define i1 @and_sge_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x >u 17
+
+define i1 @and_sge_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x <=u 17
+
+define i1 @and_sge_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_ule_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=s 23 && x <u 17
+
+define i1 @and_sge_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_sge_ult_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sge i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; sgt
+; x >s 23 && x == 17
+
+define i1 @and_sgt_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_eq_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x != 17
+
+define i1 @and_sgt_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x >=s 17
+
+define i1 @and_sgt_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x >s 17
+
+define i1 @and_sgt_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x <=s 17
+
+define i1 @and_sgt_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_sle_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x <s 17
+
+define i1 @and_sgt_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_slt_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x >=u 17
+
+define i1 @and_sgt_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x >u 17
+
+define i1 @and_sgt_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sgt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x <=u 17
+
+define i1 @and_sgt_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_ule_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >s 23 && x <u 17
+
+define i1 @and_sgt_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_sgt_ult_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp sgt i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; sle
+; x <=s 23 && x == 17
+
+define i1 @and_sle_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_eq_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x != 17
+
+define i1 @and_sle_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x >=s 17
+
+define i1 @and_sle_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x >s 17
+
+define i1 @and_sle_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x <=s 17
+
+define i1 @and_sle_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_sle_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x <s 17
+
+define i1 @and_sle_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_slt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x >=u 17
+
+define i1 @and_sle_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x >u 17
+
+define i1 @and_sle_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x <=u 17
+
+define i1 @and_sle_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_ule_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=s 23 && x <u 17
+
+define i1 @and_sle_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_sle_ult_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp sle i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp sle i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; slt
+; x <s 23 && x == 17
+
+define i1 @and_slt_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_eq_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x != 17
+
+define i1 @and_slt_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x >=s 17
+
+define i1 @and_slt_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x >s 17
+
+define i1 @and_slt_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x <=s 17
+
+define i1 @and_slt_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_sle_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x <s 17
+
+define i1 @and_slt_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_slt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x >=u 17
+
+define i1 @and_slt_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x >u 17
+
+define i1 @and_slt_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x <=u 17
+
+define i1 @and_slt_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_ule_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <s 23 && x <u 17
+
+define i1 @and_slt_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_slt_ult_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp slt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp slt i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; uge
+; x >=u 23 && x == 17
+
+define i1 @and_uge_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_eq_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x != 17
+
+define i1 @and_uge_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x >=s 17
+
+define i1 @and_uge_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x >s 17
+
+define i1 @and_uge_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x <=s 17
+
+define i1 @and_uge_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_sle_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x <s 17
+
+define i1 @and_uge_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_slt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x >=u 17
+
+define i1 @and_uge_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x >u 17
+
+define i1 @and_uge_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp uge i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x <=u 17
+
+define i1 @and_uge_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_ule_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >=u 23 && x <u 17
+
+define i1 @and_uge_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_uge_ult_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp uge i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; ugt
+; x >u 23 && x == 17
+
+define i1 @and_ugt_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_eq_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x != 17
+
+define i1 @and_ugt_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x >=s 17
+
+define i1 @and_ugt_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x >s 17
+
+define i1 @and_ugt_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x <=s 17
+
+define i1 @and_ugt_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_sle_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x <s 17
+
+define i1 @and_ugt_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_slt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x >=u 17
+
+define i1 @and_ugt_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x >u 17
+
+define i1 @and_ugt_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ugt i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x <=u 17
+
+define i1 @and_ugt_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_ule_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x >u 23 && x <u 17
+
+define i1 @and_ugt_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_ugt_ult_swap(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ugt i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; ule
+; x <=u 23 && x == 17
+
+define i1 @and_ule_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_eq_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x != 17
+
+define i1 @and_ule_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x >=s 17
+
+define i1 @and_ule_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x >s 17
+
+define i1 @and_ule_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x <=s 17
+
+define i1 @and_ule_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_sle_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x <s 17
+
+define i1 @and_ule_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_slt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x >=u 17
+
+define i1 @and_ule_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x >u 17
+
+define i1 @and_ule_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x <=u 17
+
+define i1 @and_ule_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_ule_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <=u 23 && x <u 17
+
+define i1 @and_ule_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_ule_ult_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ule i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ule i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; ult
+; x <u 23 && x == 17
+
+define i1 @and_ult_eq_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_eq_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp eq i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp eq i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x != 17
+
+define i1 @and_ult_ne_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_ne_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ne i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp ne i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x >=s 17
+
+define i1 @and_ult_sge_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_sge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp sge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x >s 17
+
+define i1 @and_ult_sgt_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_sgt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sgt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp sgt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x <=s 17
+
+define i1 @and_ult_sle_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_sle_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp sle i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp sle i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x <s 17
+
+define i1 @and_ult_slt_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_slt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp slt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp slt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x >=u 17
+
+define i1 @and_ult_uge_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_uge_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp uge i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp uge i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x >u 17
+
+define i1 @and_ult_ugt_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_ugt_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ugt i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp ugt i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x <=u 17
+
+define i1 @and_ult_ule_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_ule_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ule i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp ule i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; x <u 23 && x <u 17
+
+define i1 @and_ult_ult_swap(i8 %x) {
+; CHECK-LABEL: @and_ult_ult_swap(
+; CHECK-NEXT:    [[A:%.*]] = icmp ult i8 %x, 23
+; CHECK-NEXT:    [[B:%.*]] = icmp ult i8 %x, 17
+; CHECK-NEXT:    [[C:%.*]] = and i1 [[A]], [[B]]
+; CHECK-NEXT:    ret i1 [[C]]
+;
+  %a = icmp ult i8 %x, 23
+  %b = icmp ult i8 %x, 17
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
+; Special case - slt is uge
+; x <u 31 && x <s 0
+
+define i1 @empty2(i32 %x) {
+; CHECK-LABEL: @empty2(
+; CHECK-NEXT:    ret i1 false
+;
+  %a = icmp ult i32 %x, 31
+  %b = icmp slt i32 %x, 0
+  %c = and i1 %a, %b
+  ret i1 %c
+}
+
diff --git a/test/Transforms/InstSimplify/shufflevector.ll b/test/Transforms/InstSimplify/shufflevector.ll
index c6d180da293f..e03916c5b90d 100644
--- a/test/Transforms/InstSimplify/shufflevector.ll
+++ b/test/Transforms/InstSimplify/shufflevector.ll
@@ -120,8 +120,7 @@ define <4 x i32> @undef_mask(<4 x i32> %x) {
 
 define <4 x i32> @identity_mask_0(<4 x i32> %x) {
 ; CHECK-LABEL: @identity_mask_0(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT:    ret <4 x i32> [[SHUF]]
+; CHECK-NEXT:    ret <4 x i32> [[X:%.*]]
 ;
   %shuf = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %shuf
@@ -129,8 +128,7 @@ define <4 x i32> @identity_mask_0(<4 x i32> %x) {
 
 define <4 x i32> @identity_mask_1(<4 x i32> %x) {
 ; CHECK-LABEL: @identity_mask_1(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> undef, <4 x i32> [[X:%.*]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT:    ret <4 x i32> [[SHUF]]
+; CHECK-NEXT:    ret <4 x i32> [[X:%.*]]
 ;
   %shuf = shufflevector <4 x i32> undef, <4 x i32> %x, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   ret <4 x i32> %shuf
@@ -138,13 +136,32 @@ define <4 x i32> @identity_mask_1(<4 x i32> %x) {
 
 define <4 x i32> @pseudo_identity_mask(<4 x i32> %x) {
 ; CHECK-LABEL: @pseudo_identity_mask(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> [[X]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
-; CHECK-NEXT:    ret <4 x i32> [[SHUF]]
+; CHECK-NEXT:    ret <4 x i32> [[X:%.*]]
 ;
   %shuf = shufflevector <4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
   ret <4 x i32> %shuf
 }
 
+define <4 x i32> @not_identity_mask(<4 x i32> %x) {
+; CHECK-LABEL: @not_identity_mask(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> [[X]], <4 x i32> <i32 0, i32 1, i32 2, i32 6>
+; CHECK-NEXT:    ret <4 x i32> [[SHUF]]
+;
+  %shuf = shufflevector <4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
+  ret <4 x i32> %shuf
+}
+
+; TODO: Should we simplify if the mask has an undef element?
+
+define <4 x i32> @possible_identity_mask(<4 x i32> %x) {
+; CHECK-LABEL: @possible_identity_mask(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
+; CHECK-NEXT:    ret <4 x i32> [[SHUF]]
+;
+  %shuf = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
+  ret <4 x i32> %shuf
+}
+
 define <4 x i32> @const_operand(<4 x i32> %x) {
 ; CHECK-LABEL: @const_operand(
 ; CHECK-NEXT:    ret <4 x i32> <i32 42, i32 45, i32 44, i32 43>
@@ -155,10 +172,7 @@ define <4 x i32> @const_operand(<4 x i32> %x) {
 
 define <4 x i32> @merge(<4 x i32> %x) {
 ; CHECK-LABEL: @merge(
-; CHECK-NEXT:    [[LOWER:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <2 x i32> <i32 1, i32 0>
-; CHECK-NEXT:    [[UPPER:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT:    [[MERGED:%.*]] = shufflevector <2 x i32> [[UPPER]], <2 x i32> [[LOWER]], <4 x i32> <i32 3, i32 2, i32 0, i32 1>
-; CHECK-NEXT:    ret <4 x i32> [[MERGED]]
+; CHECK-NEXT:    ret <4 x i32> [[X:%.*]]
 ;
   %lower = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 1, i32 0>
   %upper = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -166,16 +180,24 @@ define <4 x i32> @merge(<4 x i32> %x) {
   ret <4 x i32> %merged
 }
 
+; This crosses lanes from the source op.
+
+define <4 x i32> @not_merge(<4 x i32> %x) {
+; CHECK-LABEL: @not_merge(
+; CHECK-NEXT:    [[L:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT:    [[U:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+; CHECK-NEXT:    [[MERGED:%.*]] = shufflevector <2 x i32> [[U]], <2 x i32> [[L]], <4 x i32> <i32 3, i32 2, i32 0, i32 1>
+; CHECK-NEXT:    ret <4 x i32> [[MERGED]]
+;
+  %l = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
+  %u = shufflevector <4 x i32> %x, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+  %merged = shufflevector <2 x i32> %u, <2 x i32> %l, <4 x i32> <i32 3, i32 2, i32 0, i32 1>
+  ret <4 x i32> %merged
+}
+
 define <8 x double> @extract_and_concat(<8 x double> %x) {
 ; CHECK-LABEL: @extract_and_concat(
-; CHECK-NEXT:    [[S1:%.*]] = shufflevector <8 x double> [[X:%.*]], <8 x double> undef, <2 x i32> <i32 0, i32 1>
-; CHECK-NEXT:    [[S2:%.*]] = shufflevector <8 x double> [[X]], <8 x double> undef, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT:    [[S3:%.*]] = shufflevector <8 x double> [[X]], <8 x double> undef, <2 x i32> <i32 4, i32 5>
-; CHECK-NEXT:    [[S4:%.*]] = shufflevector <8 x double> [[X]], <8 x double> undef, <2 x i32> <i32 6, i32 7>
-; CHECK-NEXT:    [[S5:%.*]] = shufflevector <2 x double> [[S1]], <2 x double> [[S2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT:    [[S6:%.*]] = shufflevector <2 x double> [[S3]], <2 x double> [[S4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT:    [[S7:%.*]] = shufflevector <4 x double> [[S5]], <4 x double> [[S6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT:    ret <8 x double> [[S7]]
+; CHECK-NEXT:    ret <8 x double> [[X:%.*]]
 ;
   %s1 = shufflevector <8 x double> %x, <8 x double> undef, <2 x i32> <i32 0, i32 1>
   %s2 = shufflevector <8 x double> %x, <8 x double> undef, <2 x i32> <i32 2, i32 3>
@@ -191,14 +213,7 @@ define <8 x double> @extract_and_concat(<8 x double> %x) {
 
 define <8 x i64> @PR30630(<8 x i64> %x) {
 ; CHECK-LABEL: @PR30630(
-; CHECK-NEXT:    [[S1:%.*]] = shufflevector <8 x i64> [[X:%.*]], <8 x i64> undef, <2 x i32> <i32 0, i32 4>
-; CHECK-NEXT:    [[S2:%.*]] = shufflevector <8 x i64> [[X]], <8 x i64> undef, <2 x i32> <i32 1, i32 5>
-; CHECK-NEXT:    [[S3:%.*]] = shufflevector <8 x i64> [[X]], <8 x i64> undef, <2 x i32> <i32 2, i32 6>
-; CHECK-NEXT:    [[S4:%.*]] = shufflevector <8 x i64> [[X]], <8 x i64> undef, <2 x i32> <i32 3, i32 7>
-; CHECK-NEXT:    [[S5:%.*]] = shufflevector <2 x i64> [[S1]], <2 x i64> [[S2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT:    [[S6:%.*]] = shufflevector <2 x i64> [[S3]], <2 x i64> [[S4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT:    [[S7:%.*]] = shufflevector <4 x i64> [[S5]], <4 x i64> [[S6]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
-; CHECK-NEXT:    ret <8 x i64> [[S7]]
+; CHECK-NEXT:    ret <8 x i64> [[X:%.*]]
 ;
   %s1 = shufflevector <8 x i64> %x, <8 x i64> undef, <2 x i32> <i32 0, i32 4>
   %s2 = shufflevector <8 x i64> %x, <8 x i64> undef, <2 x i32> <i32 1, i32 5>
diff --git a/test/Transforms/InstSimplify/vector_gep.ll b/test/Transforms/InstSimplify/vector_gep.ll
index 54887e99ee38..b8e61a05cc0c 100644
--- a/test/Transforms/InstSimplify/vector_gep.ll
+++ b/test/Transforms/InstSimplify/vector_gep.ll
@@ -61,4 +61,28 @@ define <16 x i32*> @test6() {
 ; CHECK-NEXT: ret <16 x i32*> getelementptr ([24 x [42 x [3 x i32]]], [24 x [42 x [3 x i32]]]* @v, <16 x i64> zeroinitializer, <16 x i64> zeroinitializer, <16 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>, <16 x i64> zeroinitializer)
   %VectorGep = getelementptr [24 x [42 x [3 x i32]]], [24 x [42 x [3 x i32]]]* @v, i64 0, i64 0, <16 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>, i64 0
   ret <16 x i32*> %VectorGep
-}
\ No newline at end of file
+}
+
+; PR32697
+; CHECK-LABEL: tinkywinky(
+; CHECK-NEXT: ret <4 x i8*> undef
+define <4 x i8*> @tinkywinky() {
+  %patatino = getelementptr i8, i8* undef, <4 x i64> undef
+  ret <4 x i8*> %patatino
+}
+
+; PR32697
+; CHECK-LABEL: dipsy(
+; CHECK-NEXT: ret <4 x i8*> undef
+define <4 x i8*> @dipsy() {
+  %patatino = getelementptr i8, <4 x i8 *> undef, <4 x i64> undef
+  ret <4 x i8*> %patatino
+}
+
+; PR32697
+; CHECK-LABEL: laalaa(
+; CHECK-NEXT: ret <4 x i8*> undef
+define <4 x i8*> @laalaa() {
+  %patatino = getelementptr i8, <4 x i8 *> undef, i64 undef
+  ret <4 x i8*> %patatino
+}
diff --git a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
index a9d1e8758766..728f5dcac7b1 100644
--- a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
+++ b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
@@ -198,7 +198,7 @@ for.end:                                          ; preds = %for.body
 
 ; @testNeon is an important example of the nead for ivchains.
 ;
-; Currently we have three extra add.w's that keep the store address
+; Currently we have two extra add.w's that keep the store address
 ; live past the next increment because ISEL is unfortunately undoing
 ; the store chain. ISEL also fails to convert all but one of the stores to
 ; post-increment addressing. However, the loads should use
@@ -207,12 +207,10 @@ for.end:                                          ; preds = %for.body
 ;
 ; A9: testNeon:
 ; A9: %.lr.ph
-; A9-NOT: lsl.w
-; A9-NOT: {{ldr|str|adds|add r}}
-; A9: vst1.8 {{.*}} [r{{[0-9]+}}]!
-; A9-NOT: {{ldr|str|adds|add r}}
 ; A9: add.w r
+; A9-NOT: lsl.w
 ; A9-NOT: {{ldr|str|adds|add r}}
+; A9: vst1.8 {{.*}} [r{{[0-9]+}}], r{{[0-9]+}}
 ; A9: add.w r
 ; A9-NOT: {{ldr|str|adds|add r}}
 ; A9-NOT: add.w r
diff --git a/test/Transforms/LoopUnroll/peel-loop-negative.ll b/test/Transforms/LoopUnroll/peel-loop-negative.ll
new file mode 100644
index 000000000000..eab609a3002d
--- /dev/null
+++ b/test/Transforms/LoopUnroll/peel-loop-negative.ll
@@ -0,0 +1,28 @@
+; RUN: opt < %s -S -loop-unroll -unroll-threshold=800 -unroll-peel-max-count=0 | FileCheck %s
+
+; We should not peel this loop even though we can, because the max count is set
+; to zero.
+define i32 @invariant_backedge_neg_1(i32 %a, i32 %b) {
+; CHECK-LABEL: @invariant_backedge_neg_1
+; CHECK-NOT    loop.peel{{.*}}:
+; CHECK:       loop:
+; CHECK:         %i = phi
+; CHECK:         %sum = phi
+; CHECK:         %plus = phi
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ 0, %entry ], [ %inc, %loop ]
+  %sum = phi i32 [ 0, %entry ], [ %incsum, %loop ]
+  %plus = phi i32 [ %a, %entry ], [ %b, %loop ]
+
+  %incsum = add i32 %sum, %plus
+  %inc = add i32 %i, 1
+  %cmp = icmp slt i32 %i, 1000
+
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  ret i32 %sum
+}
diff --git a/test/Transforms/LoopUnroll/peel-loop-not-forced.ll b/test/Transforms/LoopUnroll/peel-loop-not-forced.ll
index 3dcac87f8242..8691481acc12 100644
--- a/test/Transforms/LoopUnroll/peel-loop-not-forced.ll
+++ b/test/Transforms/LoopUnroll/peel-loop-not-forced.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -S -loop-unroll -unroll-threshold=4 | FileCheck %s
+; RUN: opt < %s -S -loop-unroll -unroll-threshold=30 | FileCheck %s
 
 define i32 @invariant_backedge_1(i32 %a, i32 %b) {
 ; CHECK-LABEL: @invariant_backedge_1
@@ -25,10 +25,112 @@ exit:
   ret i32 %sum
 }
 
-; Peeling should fail due to method size.
 define i32 @invariant_backedge_2(i32 %a, i32 %b) {
+; This loop should be peeled twice because it has a Phi which becomes invariant
+; starting from 3rd iteration.
 ; CHECK-LABEL: @invariant_backedge_2
-; CHECK-NOT:   loop.peel:
+; CHECK:       loop.peel{{.*}}:
+; CHECK:       loop.peel{{.*}}:
+; CHECK:         %i = phi
+; CHECK:         %sum = phi
+; CHECK-NOT:     %half.inv = phi
+; CHECK-NOT:     %plus = phi
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ 0, %entry ], [ %inc, %loop ]
+  %sum = phi i32 [ 0, %entry ], [ %incsum, %loop ]
+  %half.inv = phi i32 [ %a, %entry ], [ %b, %loop ]
+  %plus = phi i32 [ %a, %entry ], [ %half.inv, %loop ]
+
+  %incsum = add i32 %sum, %plus
+  %inc = add i32 %i, 1
+  %cmp = icmp slt i32 %i, 1000
+
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  ret i32 %sum
+}
+
+define i32 @invariant_backedge_3(i32 %a, i32 %b) {
+; This loop should be peeled thrice because it has a Phi which becomes invariant
+; starting from 4th iteration.
+; CHECK-LABEL: @invariant_backedge_3
+; CHECK:       loop.peel{{.*}}:
+; CHECK:       loop.peel{{.*}}:
+; CHECK:       loop.peel{{.*}}:
+; CHECK:         %i = phi
+; CHECK:         %sum = phi
+; CHECK-NOT:     %half.inv = phi
+; CHECK-NOT:     %half.inv.2 = phi
+; CHECK-NOT:     %plus = phi
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ 0, %entry ], [ %inc, %loop ]
+  %sum = phi i32 [ 0, %entry ], [ %incsum, %loop ]
+  %half.inv = phi i32 [ %a, %entry ], [ %b, %loop ]
+  %half.inv.2 = phi i32 [ %a, %entry ], [ %half.inv, %loop ]
+  %plus = phi i32 [ %a, %entry ], [ %half.inv.2, %loop ]
+
+  %incsum = add i32 %sum, %plus
+  %inc = add i32 %i, 1
+  %cmp = icmp slt i32 %i, 1000
+
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  ret i32 %sum
+}
+
+define i32 @invariant_backedge_limited_by_size(i32 %a, i32 %b) {
+; This loop should normally be peeled thrice because it has a Phi which becomes
+; invariant starting from 4th iteration, but the size of the loop only allows
+; us to peel twice because we are restricted to 30 instructions in resulting
+; code. Thus, %plus Phi node should stay in loop even despite its backedge
+; input is an invariant.
+; CHECK-LABEL: @invariant_backedge_limited_by_size
+; CHECK:       loop.peel{{.*}}:
+; CHECK:       loop.peel{{.*}}:
+; CHECK:         %i = phi
+; CHECK:         %sum = phi
+; CHECK:         %plus = phi i32 [ %a, {{.*}} ], [ %b, %loop ]
+; CHECK-NOT:     %half.inv = phi
+; CHECK-NOT:     %half.inv.2 = phi
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ 0, %entry ], [ %inc, %loop ]
+  %sum = phi i32 [ 0, %entry ], [ %incsum, %loop ]
+  %half.inv = phi i32 [ %a, %entry ], [ %b, %loop ]
+  %half.inv.2 = phi i32 [ %a, %entry ], [ %half.inv, %loop ]
+  %plus = phi i32 [ %a, %entry ], [ %half.inv.2, %loop ]
+
+  %incsum = add i32 %sum, %plus
+  %inc = add i32 %i, 1
+  %cmp = icmp slt i32 %i, 1000
+
+  %incsum2 = add i32 %incsum, %plus
+  %incsum3 = add i32 %incsum, %plus
+  %incsum4 = add i32 %incsum, %plus
+  %incsum5 = add i32 %incsum, %plus
+  %incsum6 = add i32 %incsum, %plus
+  %incsum7 = add i32 %incsum, %plus
+
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  ret i32 %sum
+}
+
+; Peeling should fail due to method size.
+define i32 @invariant_backedge_negative(i32 %a, i32 %b) {
+; CHECK-LABEL: @invariant_backedge_negative
+; CHECK-NOT:   loop.peel{{.*}}:
 ; CHECK:       loop:
 ; CHECK:         %i = phi
 ; CHECK:         %sum = phi
@@ -43,6 +145,47 @@ loop:
 
   %incsum = add i32 %sum, %plus
   %incsum2 = add i32 %incsum, %plus
+  %incsum3 = add i32 %incsum, %plus
+  %incsum4 = add i32 %incsum, %plus
+  %incsum5 = add i32 %incsum, %plus
+  %incsum6 = add i32 %incsum, %plus
+  %incsum7 = add i32 %incsum, %plus
+  %incsum8 = add i32 %incsum, %plus
+  %incsum9 = add i32 %incsum, %plus
+  %incsum10 = add i32 %incsum, %plus
+  %incsum11 = add i32 %incsum, %plus
+  %incsum12 = add i32 %incsum, %plus
+  %incsum13 = add i32 %incsum, %plus
+  %incsum14 = add i32 %incsum, %plus
+  %incsum15 = add i32 %incsum, %plus
+  %inc = add i32 %i, 1
+  %cmp = icmp slt i32 %i, 1000
+
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  ret i32 %sum
+}
+
+define i32 @cycled_phis(i32 %a, i32 %b) {
+; Make sure that we do not crash working with cycled Phis and don't peel it.
+; TODO: Actually this loop should be partially unrolled with factor 2.
+; CHECK-LABEL: @cycled_phis
+; CHECK-NOT:   loop.peel{{.*}}:
+; CHECK:       loop:
+; CHECK:         %i = phi
+; CHECK:         %phi.a = phi
+; CHECK:         %phi.b = phi
+; CHECK:         %sum = phi
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ 0, %entry ], [ %inc, %loop ]
+  %phi.a = phi i32 [ %a, %entry ], [ %phi.b, %loop ]
+  %phi.b = phi i32 [ %b, %entry ], [ %phi.a, %loop ]
+  %sum = phi i32 [ 0, %entry], [ %incsum, %loop ]
+  %incsum = add i32 %sum, %phi.a
   %inc = add i32 %i, 1
   %cmp = icmp slt i32 %i, 1000
 
diff --git a/test/Transforms/NewGVN/non-integral-pointers.ll b/test/Transforms/NewGVN/non-integral-pointers.ll
new file mode 100644
index 000000000000..75b8285d51f9
--- /dev/null
+++ b/test/Transforms/NewGVN/non-integral-pointers.ll
@@ -0,0 +1,39 @@
+; RUN: opt -newgvn -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:4"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @f0(i1 %alwaysFalse, i64 %val, i64* %loc) {
+; CHECK-LABEL: @f0(
+; CHECK-NOT: inttoptr
+; CHECK-NOT: ptrtoint
+ entry:
+  store i64 %val, i64* %loc
+  br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
+
+ neverTaken:
+  %loc.bc = bitcast i64* %loc to i8 addrspace(4)**
+  %ptr = load i8 addrspace(4)*, i8 addrspace(4)** %loc.bc
+  store i8 5, i8 addrspace(4)* %ptr
+  ret void
+
+ alwaysTaken:
+  ret void
+}
+
+define i64 @f1(i1 %alwaysFalse, i8 addrspace(4)* %val, i8 addrspace(4)** %loc) {
+; CHECK-LABEL: @f1(
+; CHECK-NOT: inttoptr
+; CHECK-NOT: ptrtoint
+ entry:
+  store i8 addrspace(4)* %val, i8 addrspace(4)** %loc
+  br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
+
+ neverTaken:
+  %loc.bc = bitcast i8 addrspace(4)** %loc to i64*
+  %int = load i64, i64* %loc.bc
+  ret i64 %int
+
+ alwaysTaken:
+  ret i64 42
+}
diff --git a/test/Transforms/PhaseOrdering/globalaa-retained.ll b/test/Transforms/PhaseOrdering/globalaa-retained.ll
index bce193b5e851..47b8e4d7a9ed 100644
--- a/test/Transforms/PhaseOrdering/globalaa-retained.ll
+++ b/test/Transforms/PhaseOrdering/globalaa-retained.ll
@@ -5,6 +5,37 @@ target triple = "aarch64"
 @v = internal unnamed_addr global i32 0, align 4
 @p = common global i32* null, align 8
 
+
+; This test checks that a number of loads and stores are eliminated,
+; that can only be eliminated based on GlobalsAA information. As such,
+; it tests that GlobalsAA information is retained until the passes
+; that perform this optimization, and it protects against accidentally
+; dropping the GlobalsAA information earlier in the pipeline, which
+; has happened a few times.
+
+; GlobalsAA invalidation might happen later in the FunctionPassManager
+; pipeline than the optimization eliminating unnecessary loads/stores.
+; Since GlobalsAA is a module-level analysis, any FunctionPass
+; invalidating the GlobalsAA information will affect FunctionPass
+; pipelines that execute later. For example, assume a FunctionPass1 |
+; FunctionPass2 pipeline and 2 functions to be processed: f1 and f2.
+; Assume furthermore that FunctionPass1 uses GlobalsAA info to do an
+; optimization, and FunctionPass2 invalidates GlobalsAA. Assume the
+; function passes run in the following order: FunctionPass1(f1),
+; FunctionPass2(f1), FunctionPass1(f2), FunctionPass2(f2). Then
+; FunctionPass1 will not be able to optimize f2, since GlobalsAA will
+; have been invalidated in FuntionPass2(f1).
+
+; To try and also test this scenario, there is an empty function
+; before and after the function we're checking so that one of them
+; will be processed by the whole set of FunctionPasses before @f. That
+; will ensure that if the invalidation happens, it happens before the
+; actual optimizations on @f start.
+define void @bar() {
+entry:
+  ret void
+}
+
 ; Function Attrs: norecurse nounwind
 define void @f(i32 %n) {
 entry:
@@ -19,8 +50,17 @@ entry:
   ret void
 }
 
-; check variable v is loaded only once after optimization, which should be
-; prove that globalsAA survives until the optimization that can use it to
-; optimize away the duplicate load/stores on variable v.
+; check variable v is loaded/stored only once after optimization,
+; which should be prove that globalsAA survives until the optimization
+; that can use it to optimize away the duplicate load/stores on
+; variable v.
 ; CHECK:     load i32, i32* @v, align 4
+; CHECK:     store i32 {{.*}}, i32* @v, align 4
 ; CHECK-NOT: load i32, i32* @v, align 4
+; CHECK-NOT:     store i32 {{.*}}, i32* @v, align 4
+
+; Same as @bar above, in case the functions are processed in reverse order.
+define void @bar2() {
+entry:
+  ret void
+}
diff --git a/test/Transforms/SLPVectorizer/X86/reorder_phi.ll b/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
new file mode 100644
index 000000000000..f7f58d7350b3
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
@@ -0,0 +1,54 @@
+; RUN: opt < %s -basicaa -slp-vectorizer  -S -mtriple=x86_64-unknown -mcpu=corei7-avx | FileCheck %s
+
+%struct.complex = type { float, float }
+
+; CHECK-LABEL: void @foo
+define  void @foo (%struct.complex* %A, %struct.complex* %B, %struct.complex* %Result) {
+
+entry:
+  %0 = add i64 256, 0
+  br label %loop
+
+; CHECK-LABEL: loop
+; CHECK: [[REG0:%[0-9]+]] = phi <2 x float> {{.*}}[ [[REG1:%[0-9]+]], %loop ]
+; CHECK: [[REG2:%[0-9]+]] = load <2 x float>, <2 x float>*
+; CHECK: [[REG3:%[0-9]+]] = fmul <2 x float> [[REG2]]
+; CHECK: [[REG4:%[0-9]+]] = fmul <2 x float>
+; CHECK: fsub <2 x float> [[REG3]], [[REG4]]
+; CHECK: fadd <2 x float> [[REG3]], [[REG4]]
+; CHECK: shufflevector <2 x float>
+; CHECK: [[REG1]] = fadd <2 x float>{{.*}}[[REG0]]
+loop:
+
+  %1 = phi i64 [ 0, %entry ], [ %20, %loop ]
+  %2 = phi float [ 0.000000e+00, %entry ], [ %19, %loop ]
+  %3 = phi float [ 0.000000e+00, %entry ], [ %18, %loop ]
+  %4 = getelementptr inbounds %"struct.complex", %"struct.complex"* %A, i64 %1, i32 0
+  %5 = load float, float* %4, align 4
+  %6 = getelementptr inbounds %"struct.complex", %"struct.complex"* %A, i64 %1, i32 1
+  %7 = load float, float* %6, align 4
+  %8 = getelementptr inbounds %"struct.complex", %"struct.complex"* %B, i64 %1, i32 0
+  %9 = load float, float* %8, align 4
+  %10 = getelementptr inbounds %"struct.complex", %"struct.complex"* %B, i64 %1, i32 1
+  %11 = load float, float* %10, align 4
+  %12 = fmul float %5, %9
+  %13 = fmul float %7, %11
+  %14 = fsub float %12, %13
+  %15 = fmul float %7, %9
+  %16 = fmul float %5, %11
+  %17 = fadd float %15, %16
+  %18 = fadd float %3, %14
+  %19 = fadd float %2, %17
+  %20 = add nuw nsw i64 %1, 1
+  %21 = icmp eq i64 %20, %0
+  br i1 %21, label %exit, label %loop
+
+exit:
+  %22 = getelementptr inbounds %"struct.complex", %"struct.complex"* %Result,  i32 0, i32 0
+  store float %18, float* %22, align 4
+  %23 = getelementptr inbounds %"struct.complex", %"struct.complex"* %Result,  i32 0, i32 1
+  store float %19, float* %23, align 4
+
+  ret void
+
+}
diff --git a/test/Transforms/SafeStack/X86/debug-loc.ll b/test/Transforms/SafeStack/X86/debug-loc.ll
index fc0b6f911f7e..88cda693b293 100644
--- a/test/Transforms/SafeStack/X86/debug-loc.ll
+++ b/test/Transforms/SafeStack/X86/debug-loc.ll
@@ -37,10 +37,10 @@ entry:
 
 ; CHECK-DAG: ![[VAR_ARG]] = !DILocalVariable(name: "zzz"
 ; 100 aligned up to 8
-; CHECK-DAG: ![[EXPR_ARG]] = !DIExpression(DW_OP_deref, DW_OP_minus, 104
+; CHECK-DAG: ![[EXPR_ARG]] = !DIExpression(DW_OP_minus, 104)
 
 ; CHECK-DAG: ![[VAR_LOCAL]] = !DILocalVariable(name: "xxx"
-; CHECK-DAG: ![[EXPR_LOCAL]] = !DIExpression(DW_OP_deref, DW_OP_minus, 208
+; CHECK-DAG: ![[EXPR_LOCAL]] = !DIExpression(DW_OP_minus, 208)
 
 ; Function Attrs: nounwind readnone
 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
diff --git a/test/Transforms/SampleProfile/Inputs/indirect-call.prof b/test/Transforms/SampleProfile/Inputs/indirect-call.prof
index 428d4cedef5a..aaf9ec15d02e 100644
--- a/test/Transforms/SampleProfile/Inputs/indirect-call.prof
+++ b/test/Transforms/SampleProfile/Inputs/indirect-call.prof
@@ -11,3 +11,9 @@ test_noinline:3000:0
 test_direct:3000:0
  5: foo_direct:3000
   1: 3000
+test_inline_strip:3000:0
+ 5: foo_inline_strip:3000
+  1: 3000
+test_inline_strip_confilict:3000:0
+ 5: foo_inline_strip_conflict:3000
+  1: 3000
diff --git a/test/Transforms/SampleProfile/indirect-call.ll b/test/Transforms/SampleProfile/indirect-call.ll
index 5a4913d6358f..4647dd421299 100644
--- a/test/Transforms/SampleProfile/indirect-call.ll
+++ b/test/Transforms/SampleProfile/indirect-call.ll
@@ -29,6 +29,34 @@ define void @test_inline(i64* (i32*)*, i32* %x) !dbg !3 {
   ret void
 }
 
+; CHECK-LABEL: @test_inline_strip
+; If the indirect call is promoted and inlined in profile, and the callee name
+; is stripped we should promote and inline it.
+define void @test_inline_strip(i64* (i32*)*, i32* %x) !dbg !3 {
+  %2 = alloca i64* (i32*)*
+  store i64* (i32*)* %0, i64* (i32*)** %2
+  %3 = load i64* (i32*)*, i64* (i32*)** %2
+; CHECK: icmp {{.*}} @foo_inline_strip.suffix
+; CHECK: if.true.direct_targ:
+; CHECK-NOT: call
+; CHECK: if.false.orig_indirect:
+; CHECK: call
+  call i64* %3(i32* %x), !dbg !5
+  ret void
+}
+
+; CHECK-LABEL: @test_inline_strip_conflict
+; If the indirect call is promoted and inlined in profile, and the callee name
+; is stripped, but have more than 1 potential match, we should not promote.
+define void @test_inline_strip_conflict(i64* (i32*)*, i32* %x) !dbg !3 {
+  %2 = alloca i64* (i32*)*
+  store i64* (i32*)* %0, i64* (i32*)** %2
+  %3 = load i64* (i32*)*, i64* (i32*)** %2
+; CHECK-NOT: if.true.direct_targ:
+  call i64* %3(i32* %x), !dbg !5
+  ret void
+}
+
 ; CHECK-LABEL: @test_noinline
 ; If the indirect call target is not available, we should not promote it.
 define void @test_noinline(void ()*) !dbg !3 {
@@ -47,6 +75,22 @@ define i32* @foo_inline1(i32* %x) !dbg !3 {
   ret i32* %x
 }
 
+define i32* @foo_inline_strip.suffix(i32* %x) !dbg !3 {
+  ret i32* %x
+}
+
+define i32* @foo_inline_strip_conflict.suffix1(i32* %x) !dbg !3 {
+  ret i32* %x
+}
+
+define i32* @foo_inline_strip_conflict.suffix2(i32* %x) !dbg !3 {
+  ret i32* %x
+}
+
+define i32* @foo_inline_strip_conflict.suffix3(i32* %x) !dbg !3 {
+  ret i32* %x
+}
+
 define i32* @foo_inline2(i32* %x) !dbg !3 {
   ret i32* %x
 }
diff --git a/test/Transforms/StructurizeCFG/invert-compare.ll b/test/Transforms/StructurizeCFG/invert-compare.ll
new file mode 100644
index 000000000000..87d9c6d10569
--- /dev/null
+++ b/test/Transforms/StructurizeCFG/invert-compare.ll
@@ -0,0 +1,60 @@
+; RUN: opt -S -structurizecfg %s | FileCheck %s
+
+; CHECK-LABEL: @directly_invert_compare_condition_jump_into_loop(
+; CHECK: %cmp0 = fcmp uge float %arg0, %arg1
+; CHECK-NEXT: br i1 %cmp0, label %end.loop, label %Flow
+define void @directly_invert_compare_condition_jump_into_loop(i32 addrspace(1)* %out, i32 %n, float %arg0, float %arg1) #0 {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i32 [0, %entry], [%i.inc, %end.loop]
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %i
+  store i32 %i, i32 addrspace(1)* %ptr, align 4
+  %cmp0 = fcmp olt float %arg0, %arg1
+  br i1 %cmp0, label %mid.loop, label %end.loop
+
+mid.loop:
+  store i32 333, i32 addrspace(1)* %out, align 4
+  br label %for.end
+
+end.loop:
+  %i.inc = add i32 %i, 1
+  %cmp = icmp ne i32 %i.inc, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+; CHECK-LABEL: @invert_multi_use_compare_condition_jump_into_loop(
+; CHECK: %cmp0 = fcmp olt float %arg0, %arg1
+; CHECK: store volatile i1 %cmp0, i1 addrspace(1)* undef
+; CHECK: %0 = xor i1 %cmp0, true
+; CHECK-NEXT: br i1 %0, label %end.loop, label %Flow
+define void @invert_multi_use_compare_condition_jump_into_loop(i32 addrspace(1)* %out, i32 %n, float %arg0, float %arg1) #0 {
+entry:
+  br label %for.body
+
+for.body:
+  %i = phi i32 [0, %entry], [%i.inc, %end.loop]
+  %ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %i
+  store i32 %i, i32 addrspace(1)* %ptr, align 4
+  %cmp0 = fcmp olt float %arg0, %arg1
+  store volatile i1 %cmp0, i1 addrspace(1)* undef
+  br i1 %cmp0, label %mid.loop, label %end.loop
+
+mid.loop:
+  store i32 333, i32 addrspace(1)* %out, align 4
+  br label %for.end
+
+end.loop:
+  %i.inc = add i32 %i, 1
+  %cmp = icmp ne i32 %i.inc, %n
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+attributes #0 = { nounwind }
\ No newline at end of file
diff --git a/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll b/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll
index 668a1e99d814..aff59642cbcb 100644
--- a/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll
+++ b/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll
@@ -11,8 +11,8 @@ bb:
 bb3:                                              ; preds = %bb7, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb7 ]
   %tmp4 = fcmp ult float %arg1, 3.500000e+00
-; CHECK: %0 = xor i1 %tmp4, true
-; CHECK: br i1 %0, label %bb5, label %Flow
+; CHECK: %tmp4 = fcmp oge float %arg1, 3.500000e+00
+; CHECK: br i1 %tmp4, label %bb5, label %Flow
   br i1 %tmp4, label %bb7, label %bb5
 
 ; CHECK: bb5:
@@ -22,7 +22,8 @@ bb5:                                              ; preds = %bb3
   br i1 %tmp6, label %bb10, label %bb7
 
 ; CHECK: Flow:
-; CHECK: br i1 %3, label %bb7, label %Flow1
+; CHECK: %1 = phi i1 [ %tmp6, %bb5 ], [ %tmp4, %bb3 ]
+; CHECK-NEXT: br i1 %1, label %bb7, label %Flow1
 
 ; CHECK: bb7
 bb7:                                              ; preds = %bb5, %bb3
@@ -32,9 +33,10 @@ bb7:                                              ; preds = %bb5, %bb3
   br i1 %tmp9, label %bb3, label %bb10
 
 ; CHECK: Flow1:
-; CHECK: br i1 %7, label %bb10, label %bb3
+; CHECK: %4 = phi i1 [ %tmp9, %bb7 ], [ true, %Flow ]
+; CHECK-NEXT: br i1 %4, label %bb10, label %bb3
 
-; CHECK: bb10
+; CHECK: bb10:
 bb10:                                             ; preds = %bb7, %bb5
   %tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ]
   store i32 %tmp11, i32 addrspace(1)* %arg, align 4
diff --git a/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll b/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll
index ba9aa2913061..a8835f19d447 100644
--- a/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll
+++ b/test/Transforms/StructurizeCFG/post-order-traversal-bug.ll
@@ -59,7 +59,8 @@ for.end:                                          ; preds = %for.body.1, %if.the
 ; CHECK: br i1 %{{[0-9]}}, label %for.body.1, label %Flow2
 
 ; CHECK: for.body.1:
-; CHECK: br i1 %{{[0-9]+}}, label %for.body.6, label %Flow3
+; CHECK: %cmp1.5 = icmp ne i32 %tmp22, %K1
+; CHECK-NEXT: br i1 %cmp1.5, label %for.body.6, label %Flow3
 for.body.1:                                       ; preds = %if.then, %lor.lhs.false
   %best_val.233 = phi float [ %tmp5, %if.then ], [ %best_val.027, %lor.lhs.false ]
   %best_count.231 = phi i32 [ %sub4, %if.then ], [ %best_count.025, %lor.lhs.false ]