vendor/llvm/llvm-release_360-r229040

51 files changed, 670 insertions, 967 deletions

diff --git a/test/Bindings/llvm-c/Inputs/invalid.ll.bc b/test/Bindings/llvm-c/Inputs/invalid.ll.bc
new file mode 100644
index 000000000000..a85c3644b3ab
--- /dev/null
+++ b/test/Bindings/llvm-c/Inputs/invalid.ll.bc
diff --git a/test/Bindings/llvm-c/invalid-bitcode.test b/test/Bindings/llvm-c/invalid-bitcode.test
new file mode 100644
index 000000000000..6318a9bf13d9
--- /dev/null
+++ b/test/Bindings/llvm-c/invalid-bitcode.test
@@ -0,0 +1,3 @@
+; RUN: not llvm-c-test --module-dump < %S/Inputs/invalid.ll.bc 2>&1 | FileCheck %s
+
+CHECK: Error parsing bitcode: Unknown attribute kind (48)
diff --git a/test/CodeGen/AArch64/setcc-type-mismatch.ll b/test/CodeGen/AArch64/setcc-type-mismatch.ll
new file mode 100644
index 000000000000..86817fa4fa40
--- /dev/null
+++ b/test/CodeGen/AArch64/setcc-type-mismatch.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s
+
+define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) {
+; CHECK-LABEL: test_mismatched_setcc:
+; CHECK: cmeq [[CMP128:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK: xtn {{v[0-9]+}}.4h, [[CMP128]].4s
+
+  %tst = icmp eq <4 x i22> %l, %r
+  store <4 x i1> %tst, <4 x i1>* %addr
+  ret void
+}
diff --git a/test/CodeGen/ARM/Windows/read-only-data.ll b/test/CodeGen/ARM/Windows/read-only-data.ll
index 0ccb5ededff2..0438d68b55c6 100644
--- a/test/CodeGen/ARM/Windows/read-only-data.ll
+++ b/test/CodeGen/ARM/Windows/read-only-data.ll
@@ -10,6 +10,6 @@ entry:
   ret void
 }
 
-; CHECK: .section .rdata,"rd"
+; CHECK: .section .rdata,"dr"
 ; CHECK-NOT: .section ".rodata.str1.1"
 
diff --git a/test/CodeGen/ARM/Windows/structors.ll b/test/CodeGen/ARM/Windows/structors.ll
index a1a90265c03a..874b5bf35b81 100644
--- a/test/CodeGen/ARM/Windows/structors.ll
+++ b/test/CodeGen/ARM/Windows/structors.ll
@@ -7,6 +7,6 @@ entry:
   ret void
 }
 
-; CHECK: .section .CRT$XCU,"rd"
+; CHECK: .section .CRT$XCU,"dr"
 ; CHECK: .long function
 
diff --git a/test/CodeGen/ARM/alloc-no-stack-realign.ll b/test/CodeGen/ARM/alloc-no-stack-realign.ll
index 5ad87191efe9..24c28baff881 100644
--- a/test/CodeGen/ARM/alloc-no-stack-realign.ll
+++ b/test/CodeGen/ARM/alloc-no-stack-realign.ll
@@ -9,8 +9,8 @@
 define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
 entry:
 ; NO-REALIGN-LABEL: test1
-; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
-; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
+; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
+; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
@@ -21,14 +21,16 @@ entry:
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
-; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
+; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
+; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
 
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
-; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
+; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
+; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
  %retval = alloca <16 x float>, align 16
  %0 = load <16 x float>* @T3_retval, align 16
@@ -42,8 +44,8 @@ define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
 entry:
 ; REALIGN-LABEL: test2
 ; REALIGN: bfc sp, #0, #6
-; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
-; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
+; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
+; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
 ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
@@ -63,7 +65,8 @@ entry:
 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
 ; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
-; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
+; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16
+; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
  %retval = alloca <16 x float>, align 16
  %0 = load <16 x float>* @T3_retval, align 16
diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll
index 33ac4e125633..84ce4a7f0e79 100644
--- a/test/CodeGen/ARM/memcpy-inline.ll
+++ b/test/CodeGen/ARM/memcpy-inline.ll
@@ -46,8 +46,10 @@ entry:
 ; CHECK: movw [[REG2:r[0-9]+]], #16716
 ; CHECK: movt [[REG2:r[0-9]+]], #72
 ; CHECK: str [[REG2]], [r0, #32]
-; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
-; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
+; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
+; CHECK: adds r0, #16
+; CHECK: adds r1, #16
 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
@@ -57,8 +59,10 @@ entry:
 define void @t3(i8* nocapture %C) nounwind {
 entry:
 ; CHECK-LABEL: t3:
-; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
-; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
+; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
+; CHECK: adds r0, #16
+; CHECK: adds r1, #16
 ; CHECK: vld1.8 {d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}}, [r0]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
@@ -69,8 +73,7 @@ define void @t4(i8* nocapture %C) nounwind {
 entry:
 ; CHECK-LABEL: t4:
 ; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
-; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]!
-; CHECK: strh [[REG5:r[0-9]+]], [r0]
+; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
   ret void
 }
diff --git a/test/CodeGen/ARM/setcc-type-mismatch.ll b/test/CodeGen/ARM/setcc-type-mismatch.ll
new file mode 100644
index 000000000000..2cfdba12db54
--- /dev/null
+++ b/test/CodeGen/ARM/setcc-type-mismatch.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s
+
+define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) {
+; CHECK-LABEL: test_mismatched_setcc:
+; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}}
+; CHECK: vmovn.i32 {{d[0-9]+}}, [[CMP128]]
+
+  %tst = icmp eq <4 x i22> %l, %r
+  store <4 x i1> %tst, <4 x i1>* %addr
+  ret void
+}
diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll
index 19727dabf09e..f7328dc580ef 100644
--- a/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -88,6 +88,19 @@ if.end11:                                         ; preds = %num2long.exit
   ret i32 23
 }
 
+; When considering the producer of cmp's src as the subsuming instruction,
+; only consider that when the comparison is to 0.
+define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) {
+entry:
+; CHECK-LABEL: cmp_src_nonzero:
+; CHECK: sub
+; CHECK: cmp
+  %sub = sub i32 %a, %b
+  %cmp = icmp eq i32 %sub, 17
+  %ret = select i1 %cmp, i32 %x, i32 %y
+  ret i32 %ret
+}
+
 define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
 entry:
 ; CHECK-LABEL: float_sel:
@@ -144,3 +157,50 @@ entry:
   store i32 %sub, i32* @t
   ret double %ret
 }
+
+declare void @abort()
+declare void @exit(i32)
+
+; If the comparison uses the V bit (signed overflow/underflow), we can't
+; omit the comparison.
+define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
+entry:
+; CHECK-LABEL: cmp_slt0
+; CHECK: sub
+; CHECK: cmp
+; CHECK: bge
+  %load = load i32* @t, align 4
+  %sub = sub i32 %load, 17
+  %cmp = icmp slt i32 %sub, 0
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:
+  call void @abort()
+  unreachable
+
+if.else:
+  call void @exit(i32 0)
+  unreachable
+}
+
+; Same for the C bit. (Note the ult X, 0 is trivially
+; false, so the DAG combiner may or may not optimize it).
+define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
+entry:
+; CHECK-LABEL: cmp_ult0
+; CHECK: sub
+; CHECK: cmp
+; CHECK: bhs
+  %load = load i32* @t, align 4
+  %sub = sub i32 %load, 17
+  %cmp = icmp ult i32 %sub, 0
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:
+  call void @abort()
+  unreachable
+
+if.else:
+  call void @exit(i32 0)
+  unreachable
+}
diff --git a/test/CodeGen/ARM/vector-load.ll b/test/CodeGen/ARM/vector-load.ll
deleted file mode 100644
index 008bd1f6f8c8..000000000000
--- a/test/CodeGen/ARM/vector-load.ll
+++ /dev/null
@@ -1,253 +0,0 @@
-; RUN: llc < %s | FileCheck %s
-
-target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
-target triple = "thumbv7s-apple-ios8.0.0"
-
-define <8 x i8> @load_v8i8(<8 x i8>** %ptr) {
-;CHECK-LABEL: load_v8i8:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <8 x i8>** %ptr
-	%lA = load <8 x i8>* %A, align 1
-	ret <8 x i8> %lA
-}
-
-define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) {
-;CHECK-LABEL: load_v8i8_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <8 x i8>** %ptr
-	%lA = load <8 x i8>* %A, align 1
-	%inc = getelementptr <8 x i8>* %A, i38 1
-        store <8 x i8>* %inc, <8 x i8>** %ptr
-	ret <8 x i8> %lA
-}
-
-define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
-;CHECK-LABEL: load_v4i16:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <4 x i16>** %ptr
-	%lA = load <4 x i16>* %A, align 1
-	ret <4 x i16> %lA
-}
-
-define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
-;CHECK-LABEL: load_v4i16_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <4 x i16>** %ptr
-	%lA = load <4 x i16>* %A, align 1
-	%inc = getelementptr <4 x i16>* %A, i34 1
-        store <4 x i16>* %inc, <4 x i16>** %ptr
-	ret <4 x i16> %lA
-}
-
-define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
-;CHECK-LABEL: load_v2i32:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <2 x i32>** %ptr
-	%lA = load <2 x i32>* %A, align 1
-	ret <2 x i32> %lA
-}
-
-define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
-;CHECK-LABEL: load_v2i32_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x i32>** %ptr
-	%lA = load <2 x i32>* %A, align 1
-	%inc = getelementptr <2 x i32>* %A, i32 1
-        store <2 x i32>* %inc, <2 x i32>** %ptr
-	ret <2 x i32> %lA
-}
-
-define <2 x float> @load_v2f32(<2 x float>** %ptr) {
-;CHECK-LABEL: load_v2f32:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <2 x float>** %ptr
-	%lA = load <2 x float>* %A, align 1
-	ret <2 x float> %lA
-}
-
-define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
-;CHECK-LABEL: load_v2f32_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x float>** %ptr
-	%lA = load <2 x float>* %A, align 1
-	%inc = getelementptr <2 x float>* %A, i32 1
-        store <2 x float>* %inc, <2 x float>** %ptr
-	ret <2 x float> %lA
-}
-
-define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
-;CHECK-LABEL: load_v1i64:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <1 x i64>** %ptr
-	%lA = load <1 x i64>* %A, align 1
-	ret <1 x i64> %lA
-}
-
-define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
-;CHECK-LABEL: load_v1i64_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <1 x i64>** %ptr
-	%lA = load <1 x i64>* %A, align 1
-	%inc = getelementptr <1 x i64>* %A, i31 1
-        store <1 x i64>* %inc, <1 x i64>** %ptr
-	ret <1 x i64> %lA
-}
-
-define <16 x i8> @load_v16i8(<16 x i8>** %ptr) {
-;CHECK-LABEL: load_v16i8:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <16 x i8>** %ptr
-	%lA = load <16 x i8>* %A, align 1
-	ret <16 x i8> %lA
-}
-
-define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) {
-;CHECK-LABEL: load_v16i8_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <16 x i8>** %ptr
-	%lA = load <16 x i8>* %A, align 1
-	%inc = getelementptr <16 x i8>* %A, i316 1
-        store <16 x i8>* %inc, <16 x i8>** %ptr
-	ret <16 x i8> %lA
-}
-
-define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
-;CHECK-LABEL: load_v8i16:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <8 x i16>** %ptr
-	%lA = load <8 x i16>* %A, align 1
-	ret <8 x i16> %lA
-}
-
-define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
-;CHECK-LABEL: load_v8i16_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <8 x i16>** %ptr
-	%lA = load <8 x i16>* %A, align 1
-	%inc = getelementptr <8 x i16>* %A, i38 1
-        store <8 x i16>* %inc, <8 x i16>** %ptr
-	ret <8 x i16> %lA
-}
-
-define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
-;CHECK-LABEL: load_v4i32:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <4 x i32>** %ptr
-	%lA = load <4 x i32>* %A, align 1
-	ret <4 x i32> %lA
-}
-
-define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
-;CHECK-LABEL: load_v4i32_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <4 x i32>** %ptr
-	%lA = load <4 x i32>* %A, align 1
-	%inc = getelementptr <4 x i32>* %A, i34 1
-        store <4 x i32>* %inc, <4 x i32>** %ptr
-	ret <4 x i32> %lA
-}
-
-define <4 x float> @load_v4f32(<4 x float>** %ptr) {
-;CHECK-LABEL: load_v4f32:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <4 x float>** %ptr
-	%lA = load <4 x float>* %A, align 1
-	ret <4 x float> %lA
-}
-
-define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
-;CHECK-LABEL: load_v4f32_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <4 x float>** %ptr
-	%lA = load <4 x float>* %A, align 1
-	%inc = getelementptr <4 x float>* %A, i34 1
-        store <4 x float>* %inc, <4 x float>** %ptr
-	ret <4 x float> %lA
-}
-
-define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <2 x i64>** %ptr
-	%lA = load <2 x i64>* %A, align 1
-	ret <2 x i64> %lA
-}
-
-define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x i64>** %ptr
-	%lA = load <2 x i64>* %A, align 1
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret <2 x i64> %lA
-}
-
-; Make sure we change the type to match alignment if necessary.
-define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update_aligned2:
-;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x i64>** %ptr
-	%lA = load <2 x i64>* %A, align 2
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret <2 x i64> %lA
-}
-
-define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update_aligned4:
-;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x i64>** %ptr
-	%lA = load <2 x i64>* %A, align 4
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret <2 x i64> %lA
-}
-
-define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update_aligned8:
-;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:64]!
-	%A = load <2 x i64>** %ptr
-	%lA = load <2 x i64>* %A, align 8
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret <2 x i64> %lA
-}
-
-define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update_aligned16:
-;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
-	%A = load <2 x i64>** %ptr
-	%lA = load <2 x i64>* %A, align 16
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret <2 x i64> %lA
-}
-
-; Make sure we don't break smaller-than-dreg extloads.
-define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
-;CHECK-LABEL: zextload_v8i8tov8i32:
-;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32]
-;CHECK: vmovl.u8        {{q[0-9]+}}, {{d[0-9]+}}
-;CHECK: vmovl.u16       {{q[0-9]+}}, {{d[0-9]+}}
-	%A = load <4 x i8>** %ptr
-	%lA = load <4 x i8>* %A, align 4
-        %zlA = zext <4 x i8> %lA to <4 x i32>
-	ret <4 x i32> %zlA
-}
-
-define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
-;CHECK-LABEL: zextload_v8i8tov8i32_fake_update:
-;CHECK: ldr.w   r[[PTRREG:[0-9]+]], [r0]
-;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32]
-;CHECK: add.w   r[[INCREG:[0-9]+]], r[[PTRREG]], #16
-;CHECK: str.w   r[[INCREG]], [r0]
-;CHECK: vmovl.u8        {{q[0-9]+}}, {{d[0-9]+}}
-;CHECK: vmovl.u16       {{q[0-9]+}}, {{d[0-9]+}}
-	%A = load <4 x i8>** %ptr
-	%lA = load <4 x i8>* %A, align 4
-	%inc = getelementptr <4 x i8>* %A, i38 4
-        store <4 x i8>* %inc, <4 x i8>** %ptr
-        %zlA = zext <4 x i8> %lA to <4 x i32>
-	ret <4 x i32> %zlA
-}
diff --git a/test/CodeGen/ARM/vector-store.ll b/test/CodeGen/ARM/vector-store.ll
deleted file mode 100644
index 9036a31d141d..000000000000
--- a/test/CodeGen/ARM/vector-store.ll
+++ /dev/null
@@ -1,258 +0,0 @@
-; RUN: llc < %s | FileCheck %s
-
-target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
-target triple = "thumbv7s-apple-ios8.0.0"
-
-define void @store_v8i8(<8 x i8>** %ptr, <8 x i8> %val) {
-;CHECK-LABEL: store_v8i8:
-;CHECK: str r1, [r0]
-	%A = load <8 x i8>** %ptr
-	store  <8 x i8> %val, <8 x i8>* %A, align 1
-	ret void
-}
-
-define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) {
-;CHECK-LABEL: store_v8i8_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <8 x i8>** %ptr
-	store  <8 x i8> %val, <8 x i8>* %A, align 1
-	%inc = getelementptr <8 x i8>* %A, i38 1
-        store <8 x i8>* %inc, <8 x i8>** %ptr
-	ret void
-}
-
-define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) {
-;CHECK-LABEL: store_v4i16:
-;CHECK: str r1, [r0]
-	%A = load <4 x i16>** %ptr
-	store  <4 x i16> %val, <4 x i16>* %A, align 1
-	ret void
-}
-
-define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
-;CHECK-LABEL: store_v4i16_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <4 x i16>** %ptr
-	store  <4 x i16> %val, <4 x i16>* %A, align 1
-	%inc = getelementptr <4 x i16>* %A, i34 1
-        store <4 x i16>* %inc, <4 x i16>** %ptr
-	ret void
-}
-
-define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) {
-;CHECK-LABEL: store_v2i32:
-;CHECK: str r1, [r0]
-	%A = load <2 x i32>** %ptr
-	store  <2 x i32> %val, <2 x i32>* %A, align 1
-	ret void
-}
-
-define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
-;CHECK-LABEL: store_v2i32_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x i32>** %ptr
-	store  <2 x i32> %val, <2 x i32>* %A, align 1
-	%inc = getelementptr <2 x i32>* %A, i32 1
-        store <2 x i32>* %inc, <2 x i32>** %ptr
-	ret void
-}
-
-define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) {
-;CHECK-LABEL: store_v2f32:
-;CHECK: str r1, [r0]
-	%A = load <2 x float>** %ptr
-	store  <2 x float> %val, <2 x float>* %A, align 1
-	ret void
-}
-
-define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
-;CHECK-LABEL: store_v2f32_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x float>** %ptr
-	store  <2 x float> %val, <2 x float>* %A, align 1
-	%inc = getelementptr <2 x float>* %A, i32 1
-        store <2 x float>* %inc, <2 x float>** %ptr
-	ret void
-}
-
-define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) {
-;CHECK-LABEL: store_v1i64:
-;CHECK: str r1, [r0]
-	%A = load <1 x i64>** %ptr
-	store  <1 x i64> %val, <1 x i64>* %A, align 1
-	ret void
-}
-
-define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
-;CHECK-LABEL: store_v1i64_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <1 x i64>** %ptr
-	store  <1 x i64> %val, <1 x i64>* %A, align 1
-	%inc = getelementptr <1 x i64>* %A, i31 1
-        store <1 x i64>* %inc, <1 x i64>** %ptr
-	ret void
-}
-
-define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) {
-;CHECK-LABEL: store_v16i8:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <16 x i8>** %ptr
-	store  <16 x i8> %val, <16 x i8>* %A, align 1
-	ret void
-}
-
-define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) {
-;CHECK-LABEL: store_v16i8_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <16 x i8>** %ptr
-	store  <16 x i8> %val, <16 x i8>* %A, align 1
-	%inc = getelementptr <16 x i8>* %A, i316 1
-        store <16 x i8>* %inc, <16 x i8>** %ptr
-	ret void
-}
-
-define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) {
-;CHECK-LABEL: store_v8i16:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <8 x i16>** %ptr
-	store  <8 x i16> %val, <8 x i16>* %A, align 1
-	ret void
-}
-
-define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
-;CHECK-LABEL: store_v8i16_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <8 x i16>** %ptr
-	store  <8 x i16> %val, <8 x i16>* %A, align 1
-	%inc = getelementptr <8 x i16>* %A, i38 1
-        store <8 x i16>* %inc, <8 x i16>** %ptr
-	ret void
-}
-
-define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) {
-;CHECK-LABEL: store_v4i32:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <4 x i32>** %ptr
-	store  <4 x i32> %val, <4 x i32>* %A, align 1
-	ret void
-}
-
-define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
-;CHECK-LABEL: store_v4i32_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <4 x i32>** %ptr
-	store  <4 x i32> %val, <4 x i32>* %A, align 1
-	%inc = getelementptr <4 x i32>* %A, i34 1
-        store <4 x i32>* %inc, <4 x i32>** %ptr
-	ret void
-}
-
-define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) {
-;CHECK-LABEL: store_v4f32:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <4 x float>** %ptr
-	store  <4 x float> %val, <4 x float>* %A, align 1
-	ret void
-}
-
-define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
-;CHECK-LABEL: store_v4f32_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <4 x float>** %ptr
-	store  <4 x float> %val, <4 x float>* %A, align 1
-	%inc = getelementptr <4 x float>* %A, i34 1
-        store <4 x float>* %inc, <4 x float>** %ptr
-	ret void
-}
-
-define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
-	%A = load <2 x i64>** %ptr
-	store  <2 x i64> %val, <2 x i64>* %A, align 1
-	ret void
-}
-
-define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x i64>** %ptr
-	store  <2 x i64> %val, <2 x i64>* %A, align 1
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret void
-}
-
-define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update_aligned2:
-;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x i64>** %ptr
-	store  <2 x i64> %val, <2 x i64>* %A, align 2
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret void
-}
-
-define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update_aligned4:
-;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
-	%A = load <2 x i64>** %ptr
-	store  <2 x i64> %val, <2 x i64>* %A, align 4
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret void
-}
-
-define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update_aligned8:
-;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:64]!
-	%A = load <2 x i64>** %ptr
-	store  <2 x i64> %val, <2 x i64>* %A, align 8
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret void
-}
-
-define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update_aligned16:
-;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
-	%A = load <2 x i64>** %ptr
-	store  <2 x i64> %val, <2 x i64>* %A, align 16
-	%inc = getelementptr <2 x i64>* %A, i32 1
-        store <2 x i64>* %inc, <2 x i64>** %ptr
-	ret void
-}
-
-define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
-;CHECK-LABEL: truncstore_v4i32tov4i8:
-;CHECK: ldr.w   r9, [sp]
-;CHECK: vmov    {{d[0-9]+}}, r3, r9
-;CHECK: vmov    {{d[0-9]+}}, r1, r2
-;CHECK: vmovn.i32       [[VECLO:d[0-9]+]], {{q[0-9]+}}
-;CHECK: vuzp.8  [[VECLO]], {{d[0-9]+}}
-;CHECK: ldr     r[[PTRREG:[0-9]+]], [r0]
-;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32]
-	%A = load <4 x i8>** %ptr
-        %trunc = trunc <4 x i32> %val to <4 x i8>
-	store  <4 x i8> %trunc, <4 x i8>* %A, align 4
-	ret void
-}
-
-define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) {
-;CHECK-LABEL: truncstore_v4i32tov4i8_fake_update:
-;CHECK: ldr.w   r9, [sp]
-;CHECK: vmov    {{d[0-9]+}}, r3, r9
-;CHECK: vmov    {{d[0-9]+}}, r1, r2
-;CHECK: movs    [[IMM16:r[0-9]+]], #16
-;CHECK: vmovn.i32       [[VECLO:d[0-9]+]], {{q[0-9]+}}
-;CHECK: vuzp.8  [[VECLO]], {{d[0-9]+}}
-;CHECK: ldr     r[[PTRREG:[0-9]+]], [r0]
-;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]]
-;CHECK: str     r[[PTRREG]], [r0]
-	%A = load <4 x i8>** %ptr
-        %trunc = trunc <4 x i32> %val to <4 x i8>
-	store  <4 x i8> %trunc, <4 x i8>* %A, align 4
-	%inc = getelementptr <4 x i8>* %A, i38 4
-        store <4 x i8>* %inc, <4 x i8>** %ptr
-	ret void
-}
diff --git a/test/CodeGen/PowerPC/vsel-prom.ll b/test/CodeGen/PowerPC/vsel-prom.ll
new file mode 100644
index 000000000000..dd219ec0da6f
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsel-prom.ll
@@ -0,0 +1,23 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @Compute_Lateral() #0 {
+entry:
+  br i1 undef, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  unreachable
+
+if.end:                                           ; preds = %entry
+  %0 = select i1 undef, <2 x double> undef, <2 x double> zeroinitializer
+  %1 = extractelement <2 x double> %0, i32 1
+  store double %1, double* undef, align 8
+  ret void
+
+; CHECK-LABEL: @Compute_Lateral
+}
+
+attributes #0 = { nounwind }
+
diff --git a/test/CodeGen/R600/endcf-loop-header.ll b/test/CodeGen/R600/endcf-loop-header.ll
new file mode 100644
index 000000000000..e3c5b3c1c364
--- /dev/null
+++ b/test/CodeGen/R600/endcf-loop-header.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
+
+; This tests that the llvm.SI.end.cf intrinsic is not inserted into the
+; loop block.  This intrinsic will be lowered to s_or_b64 by the code
+; generator.
+
+; CHECK-LABEL: {{^}}test:
+
+; This is was lowered from the llvm.SI.end.cf intrinsic:
+; CHECK: s_or_b64 exec, exec
+
+; CHECK: [[LOOP_LABEL:[0-9A-Za-z_]+]]: ; %loop{{$}}
+; CHECK-NOT: s_or_b64 exec, exec
+; CHECK: s_cbranch_execnz [[LOOP_LABEL]]
+define void @test(i32 addrspace(1)* %out, i32 %cond) {
+entry:
+  %tmp0 = icmp eq i32 %cond, 0
+  br i1 %tmp0, label %if, label %loop
+
+if:
+  store i32 0, i32 addrspace(1)* %out
+  br label %loop
+
+loop:
+  %tmp1 = phi i32 [0, %entry], [0, %if], [%inc, %loop]
+  %inc = add i32 %tmp1, %cond
+  %tmp2 = icmp ugt i32 %inc, 10
+  br i1 %tmp2, label %done, label %loop
+
+done:
+  %tmp3 = getelementptr i32 addrspace(1)* %out, i64 1
+  store i32 %inc, i32 addrspace(1)* %tmp3
+  ret void
+}
diff --git a/test/CodeGen/R600/tti-unroll-prefs.ll b/test/CodeGen/R600/tti-unroll-prefs.ll
new file mode 100644
index 000000000000..0009c42f79bc
--- /dev/null
+++ b/test/CodeGen/R600/tti-unroll-prefs.ll
@@ -0,0 +1,58 @@
+; RUN: opt -loop-unroll -S -mtriple=amdgcn-- -mcpu=SI %s | FileCheck %s
+
+; This IR comes from this OpenCL C code:
+;
+; if (b + 4 > a) {
+;   for (int i = 0; i < 4; i++, b++) {
+;     if (b + 1 <= a)
+;       *(dst + c + b) = 0;
+;     else
+;       break;
+;   }
+; }
+;
+; This test is meant to check that this loop isn't unrolled into more than
+; four iterations.  The loop unrolling preferences we currently use cause this
+; loop to not be unrolled at all, but that may change in the future.
+
+; CHECK-LABEL: @test
+; CHECK: store i8 0, i8 addrspace(1)*
+; CHECK-NOT: store i8 0, i8 addrspace(1)*
+; CHECK: ret void
+define void @test(i8 addrspace(1)* nocapture %dst, i32 %a, i32 %b, i32 %c) {
+entry:
+  %add = add nsw i32 %b, 4
+  %cmp = icmp sgt i32 %add, %a
+  br i1 %cmp, label %for.cond.preheader, label %if.end7
+
+for.cond.preheader:                               ; preds = %entry
+  %cmp313 = icmp slt i32 %b, %a
+  br i1 %cmp313, label %if.then4.lr.ph, label %if.end7.loopexit
+
+if.then4.lr.ph:                                   ; preds = %for.cond.preheader
+  %0 = sext i32 %c to i64
+  br label %if.then4
+
+if.then4:                                         ; preds = %if.then4.lr.ph, %if.then4
+  %i.015 = phi i32 [ 0, %if.then4.lr.ph ], [ %inc, %if.then4 ]
+  %b.addr.014 = phi i32 [ %b, %if.then4.lr.ph ], [ %add2, %if.then4 ]
+  %add2 = add nsw i32 %b.addr.014, 1
+  %1 = sext i32 %b.addr.014 to i64
+  %add.ptr.sum = add nsw i64 %1, %0
+  %add.ptr5 = getelementptr inbounds i8 addrspace(1)* %dst, i64 %add.ptr.sum
+  store i8 0, i8 addrspace(1)* %add.ptr5, align 1
+  %inc = add nsw i32 %i.015, 1
+  %cmp1 = icmp slt i32 %inc, 4
+  %cmp3 = icmp slt i32 %add2, %a
+  %or.cond = and i1 %cmp3, %cmp1
+  br i1 %or.cond, label %if.then4, label %for.cond.if.end7.loopexit_crit_edge
+
+for.cond.if.end7.loopexit_crit_edge:              ; preds = %if.then4
+  br label %if.end7.loopexit
+
+if.end7.loopexit:                                 ; preds = %for.cond.if.end7.loopexit_crit_edge, %for.cond.preheader
+  br label %if.end7
+
+if.end7:                                          ; preds = %if.end7.loopexit, %entry
+  ret void
+}
diff --git a/test/CodeGen/X86/coff-comdat.ll b/test/CodeGen/X86/coff-comdat.ll
index dcbbe1097d53..44e1cb236e91 100644
--- a/test/CodeGen/X86/coff-comdat.ll
+++ b/test/CodeGen/X86/coff-comdat.ll
@@ -73,20 +73,20 @@ $vftable = comdat largest
 ; CHECK: .globl  @v8@0
 ; CHECK: .section        .text,"xr",discard,@f8@0
 ; CHECK: .globl  @f8@0
-; CHECK: .section        .bss,"wb",associative,_f1
+; CHECK: .section        .bss,"bw",associative,_f1
 ; CHECK: .globl  _v1
-; CHECK: .section        .bss,"wb",associative,_f2
+; CHECK: .section        .bss,"bw",associative,_f2
 ; CHECK: .globl  _v2
-; CHECK: .section        .bss,"wb",associative,_f3
+; CHECK: .section        .bss,"bw",associative,_f3
 ; CHECK: .globl  _v3
-; CHECK: .section        .bss,"wb",associative,_f4
+; CHECK: .section        .bss,"bw",associative,_f4
 ; CHECK: .globl  _v4
-; CHECK: .section        .bss,"wb",associative,_f5
+; CHECK: .section        .bss,"bw",associative,_f5
 ; CHECK: .globl  _v5
-; CHECK: .section        .bss,"wb",associative,_f6
+; CHECK: .section        .bss,"bw",associative,_f6
 ; CHECK: .globl  _v6
-; CHECK: .section        .bss,"wb",same_size,_f6
+; CHECK: .section        .bss,"bw",same_size,_f6
 ; CHECK: .globl  _f6
-; CHECK: .section        .rdata,"rd",largest,_vftable
+; CHECK: .section        .rdata,"dr",largest,_vftable
 ; CHECK: .globl  _vftable
 ; CHECK: _vftable = L_some_name+4
diff --git a/test/CodeGen/X86/constant-combines.ll b/test/CodeGen/X86/constant-combines.ll
new file mode 100644
index 000000000000..d2a6ef4f5d25
--- /dev/null
+++ b/test/CodeGen/X86/constant-combines.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+define void @PR22524({ float, float }* %arg) {
+; Check that we can materialize the zero constants we store in two places here,
+; and at least form a legal store of the floating point value at the end.
+; The DAG combiner at one point contained bugs that given enough permutations
+; would incorrectly form an illegal operation for the last of these stores when
+; it folded it to a zero too late to legalize the zero store operation. If this
+; ever starts forming a zero store instead of movss, the test case has stopped
+; being useful.
+; 
+; CHECK-LABEL: PR22524:
+entry:
+  %0 = getelementptr inbounds { float, float }* %arg,  i32 0, i32 1
+  store float 0.000000e+00, float* %0, align 4
+; CHECK: movl $0, 4(%rdi)
+
+  %1 = getelementptr inbounds { float, float }* %arg, i64 0,  i32 0
+  %2 = bitcast float* %1 to i64*
+  %3 = load i64* %2, align 8
+  %4 = trunc i64 %3 to i32
+  %5 = lshr i64 %3, 32
+  %6 = trunc i64 %5 to i32
+  %7 = bitcast i32 %6 to float
+  %8 = fmul float %7, 0.000000e+00
+  %9 = bitcast float* %1 to i32*
+  store i32 %6, i32* %9, align 4
+; CHECK: movl $0, (%rdi)
+  store float %8, float* %0, align 4
+; CHECK: movss %{{.*}}, 4(%rdi)
+  ret void
+}
diff --git a/test/CodeGen/X86/dllexport-x86_64.ll b/test/CodeGen/X86/dllexport-x86_64.ll
index c673f5d485f9..cf4557d12716 100644
--- a/test/CodeGen/X86/dllexport-x86_64.ll
+++ b/test/CodeGen/X86/dllexport-x86_64.ll
@@ -40,18 +40,18 @@ define weak_odr dllexport void @weak1() {
 ; CHECK: .globl Var1
 @Var1 = dllexport global i32 1, align 4
 
-; CHECK: .rdata,"rd"
+; CHECK: .rdata,"dr"
 ; CHECK: .globl Var2
 @Var2 = dllexport unnamed_addr constant i32 1
 
 ; CHECK: .comm Var3
 @Var3 = common dllexport global i32 0, align 4
 
-; CHECK: .section .data,"wd",discard,WeakVar1
+; CHECK: .section .data,"dw",discard,WeakVar1
 ; CHECK: .globl WeakVar1
 @WeakVar1 = weak_odr dllexport global i32 1, align 4
 
-; CHECK: .section .rdata,"rd",discard,WeakVar2
+; CHECK: .section .rdata,"dr",discard,WeakVar2
 ; CHECK: .globl WeakVar2
 @WeakVar2 = weak_odr dllexport unnamed_addr constant i32 1
 
diff --git a/test/CodeGen/X86/dllexport.ll b/test/CodeGen/X86/dllexport.ll
index 5035aa153301..145b48aaf635 100644
--- a/test/CodeGen/X86/dllexport.ll
+++ b/test/CodeGen/X86/dllexport.ll
@@ -21,6 +21,8 @@ define dllexport void @f2() unnamed_addr {
 	ret void
 }
 
+declare dllexport void @not_defined()
+
 ; CHECK: .globl _stdfun@0
 define dllexport x86_stdcallcc void @stdfun() nounwind {
 	ret void
@@ -59,18 +61,18 @@ define weak_odr dllexport void @weak1() {
 ; CHECK: .globl _Var1
 @Var1 = dllexport global i32 1, align 4
 
-; CHECK: .rdata,"rd"
+; CHECK: .rdata,"dr"
 ; CHECK: .globl _Var2
 @Var2 = dllexport unnamed_addr constant i32 1
 
 ; CHECK: .comm _Var3
 @Var3 = common dllexport global i32 0, align 4
 
-; CHECK: .section .data,"wd",discard,_WeakVar1
+; CHECK: .section .data,"dw",discard,_WeakVar1
 ; CHECK: .globl _WeakVar1
 @WeakVar1 = weak_odr dllexport global i32 1, align 4
 
-; CHECK: .section .rdata,"rd",discard,_WeakVar2
+; CHECK: .section .rdata,"dr",discard,_WeakVar2
 ; CHECK: .globl _WeakVar2
 @WeakVar2 = weak_odr dllexport unnamed_addr constant i32 1
 
@@ -91,7 +93,6 @@ define weak_odr dllexport void @weak1() {
 ; CHECK: _weak_alias = _f1
 @weak_alias = weak_odr dllexport alias void()* @f1
 
-
 ; CHECK: .section .drectve
 ; CHECK-CL: " /EXPORT:_Var1,DATA"
 ; CHECK-CL: " /EXPORT:_Var2,DATA"
@@ -100,6 +101,7 @@ define weak_odr dllexport void @weak1() {
 ; CHECK-CL: " /EXPORT:_WeakVar2,DATA"
 ; CHECK-CL: " /EXPORT:_f1"
 ; CHECK-CL: " /EXPORT:_f2"
+; CHECK-CL-NOT: not_exported
 ; CHECK-CL: " /EXPORT:_stdfun@0"
 ; CHECK-CL: " /EXPORT:@fastfun@0"
 ; CHECK-CL: " /EXPORT:_thisfun"
@@ -117,6 +119,7 @@ define weak_odr dllexport void @weak1() {
 ; CHECK-GCC: " -export:WeakVar2,data"
 ; CHECK-GCC: " -export:f1"
 ; CHECK-GCC: " -export:f2"
+; CHECK-CL-NOT: not_exported
 ; CHECK-GCC: " -export:stdfun@0"
 ; CHECK-GCC: " -export:@fastfun@0"
 ; CHECK-GCC: " -export:thisfun"
diff --git a/test/CodeGen/X86/fold-vex.ll b/test/CodeGen/X86/fold-vex.ll
index 2bb5b441c7c0..5a8b1d8cbfdf 100644
--- a/test/CodeGen/X86/fold-vex.ll
+++ b/test/CodeGen/X86/fold-vex.ll
@@ -1,16 +1,31 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s
+; Use CPU parameters to ensure that a CPU-specific attribute is not overriding the AVX definition.
 
-;CHECK: @test
-; No need to load from memory. The operand will be loaded as part of th AND instr.
-;CHECK-NOT: vmovaps
-;CHECK: vandps
-;CHECK: ret
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown                  -mattr=+avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx             | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2                 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown                  -mattr=-avx | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx -mattr=-avx | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2     -mattr=-avx | FileCheck %s --check-prefix=SSE
 
-define void @test1(<8 x i32>* %p0, <8 x i32> %in1) nounwind {
-entry:
-  %in0 = load <8 x i32>* %p0, align 2
-  %a = and <8 x i32> %in0, %in1
-  store <8 x i32> %a, <8 x i32>* undef
-  ret void
+; No need to load unaligned operand from memory using an explicit instruction with AVX.
+; The operand should be folded into the AND instr.
+
+; With SSE, folding memory operands into math/logic ops requires 16-byte alignment
+; unless specially configured on some CPUs such as AMD Family 10H.
+
+define <4 x i32> @test1(<4 x i32>* %p0, <4 x i32> %in1) nounwind {
+  %in0 = load <4 x i32>* %p0, align 2
+  %a = and <4 x i32> %in0, %in1
+  ret <4 x i32> %a
+
+; CHECK-LABEL: @test1
+; CHECK-NOT:   vmovups
+; CHECK:       vandps (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:  ret
+
+; SSE-LABEL: @test1
+; SSE:       movups (%rdi), %xmm1
+; SSE-NEXT:  andps %xmm1, %xmm0
+; SSE-NEXT:  ret
 }
 
diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll
index fa1169d8a8e3..d6e45ad79ea9 100644
--- a/test/CodeGen/X86/global-sections.ll
+++ b/test/CodeGen/X86/global-sections.ll
@@ -48,7 +48,7 @@ define void @F1() {
 ; LINUX-SECTIONS: .section        .rodata.G3,"a",@progbits
 ; LINUX-SECTIONS: .globl  G3
 
-; WIN32-SECTIONS: .section        .rdata,"rd",one_only,_G3
+; WIN32-SECTIONS: .section        .rdata,"dr",one_only,_G3
 ; WIN32-SECTIONS: .globl  _G3
 
 
@@ -126,7 +126,7 @@ define void @F1() {
 ; LINUX-SECTIONS: .section        .rodata.G7,"aMS",@progbits,1
 ; LINUX-SECTIONS:       .globl G7
 
-; WIN32-SECTIONS: .section        .rdata,"rd",one_only,_G7
+; WIN32-SECTIONS: .section        .rdata,"dr",one_only,_G7
 ; WIN32-SECTIONS:       .globl _G7
 
 
@@ -189,7 +189,7 @@ define void @F1() {
 ; LINUX-SECTIONS:        .asciz  "foo"
 ; LINUX-SECTIONS:        .size   .LG14, 4
 
-; WIN32-SECTIONS:        .section        .rdata,"rd"
+; WIN32-SECTIONS:        .section        .rdata,"dr"
 ; WIN32-SECTIONS: L_G14:
 ; WIN32-SECTIONS:        .asciz  "foo"
 
@@ -211,5 +211,5 @@ define void @F1() {
 ; LINUX-SECTIONS: .section      .rodata.G15,"aM",@progbits,8
 ; LINUX-SECTIONS: G15:
 
-; WIN32-SECTIONS: .section      .rdata,"rd",one_only,_G15
+; WIN32-SECTIONS: .section      .rdata,"dr",one_only,_G15
 ; WIN32-SECTIONS: _G15:
diff --git a/test/CodeGen/X86/pr15267.ll b/test/CodeGen/X86/pr15267.ll
index b4dc5fd47168..90df9905fe1a 100644
--- a/test/CodeGen/X86/pr15267.ll
+++ b/test/CodeGen/X86/pr15267.ll
@@ -4,8 +4,7 @@ define <4 x i3> @test1(<4 x i3>* %in) nounwind {
   %ret = load <4 x i3>* %in, align 1
   ret <4 x i3> %ret
 }
-
-; CHECK: test1
+; CHECK-LABEL: test1
 ; CHECK: movzwl
 ; CHECK: shrl $3
 ; CHECK: andl $7
@@ -25,7 +24,7 @@ define <4 x i1> @test2(<4 x i1>* %in) nounwind {
   ret <4 x i1> %ret
 }
 
-; CHECK: test2
+; CHECK-LABEL: test2
 ; CHECK: movzbl
 ; CHECK: shrl
 ; CHECK: andl $1
@@ -46,7 +45,7 @@ define <4 x i64> @test3(<4 x i1>* %in) nounwind {
   ret <4 x i64> %sext
 }
 
-; CHECK: test3
+; CHECK-LABEL: test3
 ; CHECK: movzbl
 ; CHECK: movq
 ; CHECK: shlq
@@ -67,3 +66,71 @@ define <4 x i64> @test3(<4 x i1>* %in) nounwind {
 ; CHECK: vpunpcklqdq
 ; CHECK: vinsertf128
 ; CHECK: ret
+
+define <16 x i4> @test4(<16 x i4>* %in) nounwind {
+  %ret = load <16 x i4>* %in, align 1
+  ret <16 x i4> %ret
+}
+
+; CHECK-LABEL: test4
+; CHECK: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: movl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vmovd
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: shrq
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: retq
diff --git a/test/CodeGen/X86/pshufb-mask-comments.ll b/test/CodeGen/X86/pshufb-mask-comments.ll
index 303c4a684761..ca5a02ce8d3a 100644
--- a/test/CodeGen/X86/pshufb-mask-comments.ll
+++ b/test/CodeGen/X86/pshufb-mask-comments.ll
@@ -37,4 +37,16 @@ define <16 x i8> @test4(<2 x i64>* %V) {
   ret <16 x i8> %1
 }
 
+define <16 x i8> @test5() {
+; CHECK-LABEL: test5
+; CHECK: pshufb {{.*}}
+  store <2 x i64> <i64 1, i64 0>, <2 x i64>* undef, align 16
+  %l = load <2 x i64>* undef, align 16
+  %shuffle = shufflevector <2 x i64> %l, <2 x i64> undef, <2 x i32> zeroinitializer
+  store <2 x i64> %shuffle, <2 x i64>* undef, align 16
+  %1 = load <16 x i8>* undef, align 16
+  %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> undef, <16 x i8> %1)
+  ret <16 x i8> %2
+}
+
 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
diff --git a/test/CodeGen/X86/seh-basic.ll b/test/CodeGen/X86/seh-basic.ll
deleted file mode 100644
index 69d70d70948c..000000000000
--- a/test/CodeGen/X86/seh-basic.ll
+++ /dev/null
@@ -1,175 +0,0 @@
-; RUN: llc -mtriple x86_64-pc-windows-msvc < %s | FileCheck %s
-
-define void @two_invoke_merged() {
-entry:
-  invoke void @try_body()
-          to label %again unwind label %lpad
-
-again:
-  invoke void @try_body()
-          to label %done unwind label %lpad
-
-done:
-  ret void
-
-lpad:
-  %vals = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
-          catch i8* bitcast (i32 (i8*, i8*)* @filt0 to i8*)
-          catch i8* bitcast (i32 (i8*, i8*)* @filt1 to i8*)
-  %sel = extractvalue { i8*, i32 } %vals, 1
-  call void @use_selector(i32 %sel)
-  ret void
-}
-
-; Normal path code
-
-; CHECK-LABEL: {{^}}two_invoke_merged:
-; CHECK: .seh_proc two_invoke_merged
-; CHECK: .seh_handler __C_specific_handler, @unwind, @except
-; CHECK: .Ltmp0:
-; CHECK: callq try_body
-; CHECK-NEXT: .Ltmp1:
-; CHECK: .Ltmp2:
-; CHECK: callq try_body
-; CHECK-NEXT: .Ltmp3:
-; CHECK: retq
-
-; Landing pad code
-
-; CHECK: .Ltmp5:
-; CHECK: movl $1, %ecx
-; CHECK: jmp
-; CHECK: .Ltmp6:
-; CHECK: movl $2, %ecx
-; CHECK: callq use_selector
-
-; CHECK: .seh_handlerdata
-; CHECK-NEXT: .long 2
-; CHECK-NEXT: .long .Ltmp0@IMGREL
-; CHECK-NEXT: .long .Ltmp3@IMGREL+1
-; CHECK-NEXT: .long filt0@IMGREL
-; CHECK-NEXT: .long .Ltmp5@IMGREL
-; CHECK-NEXT: .long .Ltmp0@IMGREL
-; CHECK-NEXT: .long .Ltmp3@IMGREL+1
-; CHECK-NEXT: .long filt1@IMGREL
-; CHECK-NEXT: .long .Ltmp6@IMGREL
-; CHECK: .text
-; CHECK: .seh_endproc
-
-define void @two_invoke_gap() {
-entry:
-  invoke void @try_body()
-          to label %again unwind label %lpad
-
-again:
-  call void @do_nothing_on_unwind()
-  invoke void @try_body()
-          to label %done unwind label %lpad
-
-done:
-  ret void
-
-lpad:
-  %vals = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
-          catch i8* bitcast (i32 (i8*, i8*)* @filt0 to i8*)
-  %sel = extractvalue { i8*, i32 } %vals, 1
-  call void @use_selector(i32 %sel)
-  ret void
-}
-
-; Normal path code
-
-; CHECK-LABEL: {{^}}two_invoke_gap:
-; CHECK: .seh_proc two_invoke_gap
-; CHECK: .seh_handler __C_specific_handler, @unwind, @except
-; CHECK: .Ltmp11:
-; CHECK: callq try_body
-; CHECK-NEXT: .Ltmp12:
-; CHECK: callq do_nothing_on_unwind
-; CHECK: .Ltmp13:
-; CHECK: callq try_body
-; CHECK-NEXT: .Ltmp14:
-; CHECK: retq
-
-; Landing pad code
-
-; CHECK: .Ltmp16:
-; CHECK: movl $1, %ecx
-; CHECK: callq use_selector
-
-; CHECK: .seh_handlerdata
-; CHECK-NEXT: .long 2
-; CHECK-NEXT: .long .Ltmp11@IMGREL
-; CHECK-NEXT: .long .Ltmp12@IMGREL+1
-; CHECK-NEXT: .long filt0@IMGREL
-; CHECK-NEXT: .long .Ltmp16@IMGREL
-; CHECK-NEXT: .long .Ltmp13@IMGREL
-; CHECK-NEXT: .long .Ltmp14@IMGREL+1
-; CHECK-NEXT: .long filt0@IMGREL
-; CHECK-NEXT: .long .Ltmp16@IMGREL
-; CHECK: .text
-; CHECK: .seh_endproc
-
-define void @two_invoke_nounwind_gap() {
-entry:
-  invoke void @try_body()
-          to label %again unwind label %lpad
-
-again:
-  call void @cannot_unwind()
-  invoke void @try_body()
-          to label %done unwind label %lpad
-
-done:
-  ret void
-
-lpad:
-  %vals = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
-          catch i8* bitcast (i32 (i8*, i8*)* @filt0 to i8*)
-  %sel = extractvalue { i8*, i32 } %vals, 1
-  call void @use_selector(i32 %sel)
-  ret void
-}
-
-; Normal path code
-
-; CHECK-LABEL: {{^}}two_invoke_nounwind_gap:
-; CHECK: .seh_proc two_invoke_nounwind_gap
-; CHECK: .seh_handler __C_specific_handler, @unwind, @except
-; CHECK: .Ltmp21:
-; CHECK: callq try_body
-; CHECK-NEXT: .Ltmp22:
-; CHECK: callq cannot_unwind
-; CHECK: .Ltmp23:
-; CHECK: callq try_body
-; CHECK-NEXT: .Ltmp24:
-; CHECK: retq
-
-; Landing pad code
-
-; CHECK: .Ltmp26:
-; CHECK: movl $1, %ecx
-; CHECK: callq use_selector
-
-; CHECK: .seh_handlerdata
-; CHECK-NEXT: .long 1
-; CHECK-NEXT: .long .Ltmp21@IMGREL
-; CHECK-NEXT: .long .Ltmp24@IMGREL+1
-; CHECK-NEXT: .long filt0@IMGREL
-; CHECK-NEXT: .long .Ltmp26@IMGREL
-; CHECK: .text
-; CHECK: .seh_endproc
-
-declare void @try_body()
-declare void @do_nothing_on_unwind()
-declare void @cannot_unwind() nounwind
-declare void @use_selector(i32)
-
-declare i32 @filt0(i8* %eh_info, i8* %rsp)
-declare i32 @filt1(i8* %eh_info, i8* %rsp)
-
-declare void @handler0()
-declare void @handler1()
-
-declare i32 @__C_specific_handler(...)
-declare i32 @llvm.eh.typeid.for(i8*) readnone nounwind
diff --git a/test/CodeGen/X86/seh-safe-div.ll b/test/CodeGen/X86/seh-safe-div.ll
deleted file mode 100644
index e911df04ded4..000000000000
--- a/test/CodeGen/X86/seh-safe-div.ll
+++ /dev/null
@@ -1,196 +0,0 @@
-; RUN: llc -mtriple x86_64-pc-windows-msvc < %s | FileCheck %s
-
-; This test case is also intended to be run manually as a complete functional
-; test. It should link, print something, and exit zero rather than crashing.
-; It is the hypothetical lowering of a C source program that looks like:
-;
-;   int safe_div(int *n, int *d) {
-;     int r;
-;     __try {
-;       __try {
-;         r = *n / *d;
-;       } __except(GetExceptionCode() == EXCEPTION_ACCESS_VIOLATION) {
-;         puts("EXCEPTION_ACCESS_VIOLATION");
-;         r = -1;
-;       }
-;     } __except(GetExceptionCode() == EXCEPTION_INT_DIVIDE_BY_ZERO) {
-;       puts("EXCEPTION_INT_DIVIDE_BY_ZERO");
-;       r = -2;
-;     }
-;     return r;
-;   }
-
-@str1 = internal constant [27 x i8] c"EXCEPTION_ACCESS_VIOLATION\00"
-@str2 = internal constant [29 x i8] c"EXCEPTION_INT_DIVIDE_BY_ZERO\00"
-
-define i32 @safe_div(i32* %n, i32* %d) {
-entry:
-  %r = alloca i32, align 4
-  invoke void @try_body(i32* %r, i32* %n, i32* %d)
-          to label %__try.cont unwind label %lpad
-
-lpad:
-  %vals = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
-          catch i8* bitcast (i32 (i8*, i8*)* @safe_div_filt0 to i8*)
-          catch i8* bitcast (i32 (i8*, i8*)* @safe_div_filt1 to i8*)
-  %ehptr = extractvalue { i8*, i32 } %vals, 0
-  %sel = extractvalue { i8*, i32 } %vals, 1
-  %filt0_val = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @safe_div_filt0 to i8*))
-  %is_filt0 = icmp eq i32 %sel, %filt0_val
-  br i1 %is_filt0, label %handler0, label %eh.dispatch1
-
-eh.dispatch1:
-  %filt1_val = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 (i8*, i8*)* @safe_div_filt1 to i8*))
-  %is_filt1 = icmp eq i32 %sel, %filt1_val
-  br i1 %is_filt1, label %handler1, label %eh.resume
-
-handler0:
-  call void @puts(i8* getelementptr ([27 x i8]* @str1, i32 0, i32 0))
-  store i32 -1, i32* %r, align 4
-  br label %__try.cont
-
-handler1:
-  call void @puts(i8* getelementptr ([29 x i8]* @str2, i32 0, i32 0))
-  store i32 -2, i32* %r, align 4
-  br label %__try.cont
-
-eh.resume:
-  resume { i8*, i32 } %vals
-
-__try.cont:
-  %safe_ret = load i32* %r, align 4
-  ret i32 %safe_ret
-}
-
-; Normal path code
-
-; CHECK: {{^}}safe_div:
-; CHECK: .seh_proc safe_div
-; CHECK: .seh_handler __C_specific_handler, @unwind, @except
-; CHECK: .Ltmp0:
-; CHECK: leaq [[rloc:.*\(%rsp\)]], %rcx
-; CHECK: callq try_body
-; CHECK-NEXT: .Ltmp1
-; CHECK: .LBB0_7:
-; CHECK: movl [[rloc]], %eax
-; CHECK: retq
-
-; Landing pad code
-
-; CHECK: .Ltmp3:
-; CHECK: movl $1, %[[sel:[a-z]+]]
-; CHECK: .Ltmp4
-; CHECK: movl $2, %[[sel]]
-; CHECK: .L{{.*}}:
-; CHECK: cmpl $1, %[[sel]]
-
-; CHECK: # %handler0
-; CHECK: callq puts
-; CHECK: movl $-1, [[rloc]]
-; CHECK: jmp .LBB0_7
-
-; CHECK: cmpl $2, %[[sel]]
-
-; CHECK: # %handler1
-; CHECK: callq puts
-; CHECK: movl $-2, [[rloc]]
-; CHECK: jmp .LBB0_7
-
-; FIXME: EH preparation should not call _Unwind_Resume.
-; CHECK: callq _Unwind_Resume
-; CHECK: ud2
-
-; CHECK: .seh_handlerdata
-; CHECK: .long 2
-; CHECK: .long .Ltmp0@IMGREL
-; CHECK: .long .Ltmp1@IMGREL+1
-; CHECK: .long safe_div_filt0@IMGREL
-; CHECK: .long .Ltmp3@IMGREL
-; CHECK: .long .Ltmp0@IMGREL
-; CHECK: .long .Ltmp1@IMGREL+1
-; CHECK: .long safe_div_filt1@IMGREL
-; CHECK: .long .Ltmp4@IMGREL
-; CHECK: .text
-; CHECK: .seh_endproc
-
-
-define void @try_body(i32* %r, i32* %n, i32* %d) {
-entry:
-  %0 = load i32* %n, align 4
-  %1 = load i32* %d, align 4
-  %div = sdiv i32 %0, %1
-  store i32 %div, i32* %r, align 4
-  ret void
-}
-
-; The prototype of these filter functions is:
-; int filter(EXCEPTION_POINTERS *eh_ptrs, void *rbp);
-
-; The definition of EXCEPTION_POINTERS is:
-;   typedef struct _EXCEPTION_POINTERS {
-;     EXCEPTION_RECORD *ExceptionRecord;
-;     CONTEXT          *ContextRecord;
-;   } EXCEPTION_POINTERS;
-
-; The definition of EXCEPTION_RECORD is:
-;   typedef struct _EXCEPTION_RECORD {
-;     DWORD ExceptionCode;
-;     ...
-;   } EXCEPTION_RECORD;
-
-; The exception code can be retreived with two loads, one for the record
-; pointer and one for the code.  The values of local variables can be
-; accessed via rbp, but that would require additional not yet implemented LLVM
-; support.
-
-define i32 @safe_div_filt0(i8* %eh_ptrs, i8* %rbp) {
-  %eh_ptrs_c = bitcast i8* %eh_ptrs to i32**
-  %eh_rec = load i32** %eh_ptrs_c
-  %eh_code = load i32* %eh_rec
-  ; EXCEPTION_ACCESS_VIOLATION = 0xC0000005
-  %cmp = icmp eq i32 %eh_code, 3221225477
-  %filt.res = zext i1 %cmp to i32
-  ret i32 %filt.res
-}
-
-define i32 @safe_div_filt1(i8* %eh_ptrs, i8* %rbp) {
-  %eh_ptrs_c = bitcast i8* %eh_ptrs to i32**
-  %eh_rec = load i32** %eh_ptrs_c
-  %eh_code = load i32* %eh_rec
-  ; EXCEPTION_INT_DIVIDE_BY_ZERO = 0xC0000094
-  %cmp = icmp eq i32 %eh_code, 3221225620
-  %filt.res = zext i1 %cmp to i32
-  ret i32 %filt.res
-}
-
-@str_result = internal constant [21 x i8] c"safe_div result: %d\0A\00"
-
-define i32 @main() {
-  %d.addr = alloca i32, align 4
-  %n.addr = alloca i32, align 4
-
-  store i32 10, i32* %n.addr, align 4
-  store i32 2, i32* %d.addr, align 4
-  %r1 = call i32 @safe_div(i32* %n.addr, i32* %d.addr)
-  call void (i8*, ...)* @printf(i8* getelementptr ([21 x i8]* @str_result, i32 0, i32 0), i32 %r1)
-
-  store i32 10, i32* %n.addr, align 4
-  store i32 0, i32* %d.addr, align 4
-  %r2 = call i32 @safe_div(i32* %n.addr, i32* %d.addr)
-  call void (i8*, ...)* @printf(i8* getelementptr ([21 x i8]* @str_result, i32 0, i32 0), i32 %r2)
-
-  %r3 = call i32 @safe_div(i32* %n.addr, i32* null)
-  call void (i8*, ...)* @printf(i8* getelementptr ([21 x i8]* @str_result, i32 0, i32 0), i32 %r3)
-  ret i32 0
-}
-
-define void @_Unwind_Resume() {
-  call void @abort()
-  unreachable
-}
-
-declare i32 @__C_specific_handler(...)
-declare i32 @llvm.eh.typeid.for(i8*) readnone nounwind
-declare void @puts(i8*)
-declare void @printf(i8*, ...)
-declare void @abort()
diff --git a/test/CodeGen/X86/2010-01-07-UAMemFeature.ll b/test/CodeGen/X86/sse-unaligned-mem-feature.ll
index bb24adb41817..15f91ee04eaf 100644
--- a/test/CodeGen/X86/2010-01-07-UAMemFeature.ll
+++ b/test/CodeGen/X86/sse-unaligned-mem-feature.ll
@@ -1,5 +1,4 @@
-; RUN: llc -mcpu=yonah -mattr=vector-unaligned-mem -march=x86 < %s | FileCheck %s
-; CHECK: addps (
+; RUN: llc -mcpu=yonah -mattr=sse-unaligned-mem -march=x86 < %s | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
@@ -8,4 +7,7 @@ define <4 x float> @foo(<4 x float>* %P, <4 x float> %In) nounwind {
 	%A = load <4 x float>* %P, align 4
 	%B = fadd <4 x float> %A, %In
 	ret <4 x float> %B
+
+; CHECK-LABEL: @foo
+; CHECK:       addps (
 }
diff --git a/test/CodeGen/X86/win_cst_pool.ll b/test/CodeGen/X86/win_cst_pool.ll
index e8b853a03dae..d534b126b192 100644
--- a/test/CodeGen/X86/win_cst_pool.ll
+++ b/test/CodeGen/X86/win_cst_pool.ll
@@ -6,7 +6,7 @@ define double @double() {
   ret double 0x0000000000800000
 }
 ; CHECK:              .globl  __real@0000000000800000
-; CHECK-NEXT:         .section        .rdata,"rd",discard,__real@0000000000800000
+; CHECK-NEXT:         .section        .rdata,"dr",discard,__real@0000000000800000
 ; CHECK-NEXT:         .align  8
 ; CHECK-NEXT: __real@0000000000800000:
 ; CHECK-NEXT:         .quad   8388608
@@ -18,7 +18,7 @@ define <4 x i32> @vec1() {
   ret <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 }
 ; CHECK:              .globl  __xmm@00000000000000010000000200000003
-; CHECK-NEXT:         .section        .rdata,"rd",discard,__xmm@00000000000000010000000200000003
+; CHECK-NEXT:         .section        .rdata,"dr",discard,__xmm@00000000000000010000000200000003
 ; CHECK-NEXT:         .align  16
 ; CHECK-NEXT: __xmm@00000000000000010000000200000003:
 ; CHECK-NEXT:         .long   3
@@ -33,7 +33,7 @@ define <8 x i16> @vec2() {
   ret <8 x i16> <i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
 }
 ; CHECK:             .globl  __xmm@00000001000200030004000500060007
-; CHECK-NEXT:        .section        .rdata,"rd",discard,__xmm@00000001000200030004000500060007
+; CHECK-NEXT:        .section        .rdata,"dr",discard,__xmm@00000001000200030004000500060007
 ; CHECK-NEXT:        .align  16
 ; CHECK-NEXT: __xmm@00000001000200030004000500060007:
 ; CHECK-NEXT:        .short  7
@@ -53,7 +53,7 @@ define <4 x float> @undef1() {
   ret <4 x float> <float 1.0, float 1.0, float undef, float undef>
 
 ; CHECK:             .globl  __xmm@00000000000000003f8000003f800000
-; CHECK-NEXT:        .section        .rdata,"rd",discard,__xmm@00000000000000003f8000003f800000
+; CHECK-NEXT:        .section        .rdata,"dr",discard,__xmm@00000000000000003f8000003f800000
 ; CHECK-NEXT:        .align  16
 ; CHECK-NEXT: __xmm@00000000000000003f8000003f800000:
 ; CHECK-NEXT:        .long   1065353216              # float 1
diff --git a/test/DebugInfo/COFF/asm.ll b/test/DebugInfo/COFF/asm.ll
index 44ee4f9ce4f4..4d5cdda5659a 100644
--- a/test/DebugInfo/COFF/asm.ll
+++ b/test/DebugInfo/COFF/asm.ll
@@ -22,7 +22,7 @@
 ; X86-NEXT: L{{.*}}:
 ; X86-NEXT: [[END_OF_F:^L.*]]:
 ;
-; X86-LABEL: .section        .debug$S,"rd"
+; X86-LABEL: .section        .debug$S,"dr"
 ; X86-NEXT: .long   4
 ; Symbol subsection
 ; X86-NEXT: .long   241
@@ -127,7 +127,7 @@
 ; X64-NEXT: .L{{.*}}:
 ; X64-NEXT: [[END_OF_F:.*]]:
 ;
-; X64-LABEL: .section        .debug$S,"rd"
+; X64-LABEL: .section        .debug$S,"dr"
 ; X64-NEXT: .long   4
 ; Symbol subsection
 ; X64-NEXT: .long   241
diff --git a/test/DebugInfo/COFF/multifile.ll b/test/DebugInfo/COFF/multifile.ll
index 5cdd6dc2e51b..52a62d1c3ca9 100644
--- a/test/DebugInfo/COFF/multifile.ll
+++ b/test/DebugInfo/COFF/multifile.ll
@@ -29,7 +29,7 @@
 ; X86-NEXT: L{{.*}}:
 ; X86-NEXT: [[END_OF_F:.*]]:
 ;
-; X86-LABEL: .section        .debug$S,"rd"
+; X86-LABEL: .section        .debug$S,"dr"
 ; X86-NEXT: .long   4
 ; Symbol subsection
 ; X86-NEXT: .long   241
@@ -159,7 +159,7 @@
 ; X64-NEXT: .L{{.*}}:
 ; X64-NEXT: [[END_OF_F:.*]]:
 ;
-; X64-LABEL: .section        .debug$S,"rd"
+; X64-LABEL: .section        .debug$S,"dr"
 ; X64-NEXT: .long   4
 ; Symbol subsection
 ; X64-NEXT: .long   241
diff --git a/test/DebugInfo/COFF/multifunction.ll b/test/DebugInfo/COFF/multifunction.ll
index 8f9a3f8b9b75..01ba617dc1d7 100644
--- a/test/DebugInfo/COFF/multifunction.ll
+++ b/test/DebugInfo/COFF/multifunction.ll
@@ -53,7 +53,7 @@
 ; X86-NEXT: L{{.*}}:
 ; X86-NEXT: [[END_OF_F:.*]]:
 ;
-; X86-LABEL: .section        .debug$S,"rd"
+; X86-LABEL: .section        .debug$S,"dr"
 ; X86-NEXT: .long   4
 ; Symbol subsection for x
 ; X86-NEXT: .long   241
@@ -317,7 +317,7 @@
 ; X64-NEXT: .L{{.*}}:
 ; X64-NEXT: [[END_OF_F:.*]]:
 ;
-; X64-LABEL: .section        .debug$S,"rd"
+; X64-LABEL: .section        .debug$S,"dr"
 ; X64-NEXT: .long   4
 ; Symbol subsection for x
 ; X64-NEXT: .long   241
diff --git a/test/DebugInfo/COFF/simple.ll b/test/DebugInfo/COFF/simple.ll
index bcb8a695c7f1..196deefe8c4e 100644
--- a/test/DebugInfo/COFF/simple.ll
+++ b/test/DebugInfo/COFF/simple.ll
@@ -20,7 +20,7 @@
 ; X86-NEXT: L{{.*}}:
 ; X86-NEXT: [[END_OF_F:.*]]:
 ;
-; X86-LABEL: .section        .debug$S,"rd"
+; X86-LABEL: .section        .debug$S,"dr"
 ; X86-NEXT: .long   4
 ; Symbol subsection
 ; X86-NEXT: .long   241
@@ -118,7 +118,7 @@
 ; X64-NEXT: .L{{.*}}:
 ; X64-NEXT: [[END_OF_F:.*]]:
 ;
-; X64-LABEL: .section        .debug$S,"rd"
+; X64-LABEL: .section        .debug$S,"dr"
 ; X64-NEXT: .long   4
 ; Symbol subsection
 ; X64-NEXT: .long   241
diff --git a/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll b/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll
index 181359b905ab..83d976d24056 100644
--- a/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll
+++ b/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll
@@ -22,7 +22,7 @@
 ; X86-NEXT: [[END_OF_BAR:^L.*]]:{{$}}
 ; X86-NOT:  ret
 
-; X86-LABEL: .section        .debug$S,"rd"
+; X86-LABEL: .section        .debug$S,"dr"
 ; X86:       .secrel32 "?bar@@YAXHZZ"
 ; X86-NEXT:  .secidx   "?bar@@YAXHZZ"
 ; X86:       .long   0
diff --git a/test/DebugInfo/X86/coff_debug_info_type.ll b/test/DebugInfo/X86/coff_debug_info_type.ll
index d34f50b7244b..89859d246af8 100644
--- a/test/DebugInfo/X86/coff_debug_info_type.ll
+++ b/test/DebugInfo/X86/coff_debug_info_type.ll
@@ -6,7 +6,7 @@
 ; CHECK:    .section  .apple_types
 
 ; RUN: llc -mtriple=i686-pc-win32 -filetype=asm -O0 < %s | FileCheck -check-prefix=WIN32 %s
-; WIN32:    .section .debug$S,"rd"
+; WIN32:    .section .debug$S,"dr"
 
 ; RUN: llc -mtriple=i686-pc-win32 -filetype=null -O0 < %s
 
diff --git a/test/DebugInfo/location-verifier.ll b/test/DebugInfo/location-verifier.ll
new file mode 100644
index 000000000000..0e56be42e1f9
--- /dev/null
+++ b/test/DebugInfo/location-verifier.ll
@@ -0,0 +1,33 @@
+; RUN: not llvm-as -disable-output -verify-debug-info < %s 2>&1 | FileCheck %s
+; ModuleID = 'test.c'
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.10.0"
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @foo() #0 {
+entry:
+  ret i32 42, !dbg !13
+}
+
+attributes #0 = { nounwind ssp uwtable }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!9, !10, !11}
+!llvm.ident = !{!12}
+
+!0 = !{!"0x11\0012\00clang version 3.7.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/test.c] [DW_LANG_C99]
+!1 = !{!"test.c", !""}
+!2 = !{}
+!3 = !{!4}
+!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\000\000\000\001", !1, !5, !6, null, i32 ()* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
+!5 = !{!"0x29", !1}                               ; [ DW_TAG_file_type ] [/test.c]
+!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = !{!8}
+!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = !{i32 2, !"Dwarf Version", i32 2}
+!10 = !{i32 2, !"Debug Info Version", i32 2}
+!11 = !{i32 1, !"PIC Level", i32 2}
+!12 = !{!"clang version 3.7.0 "}
+; An old-style MDLocation should not pass verify.
+; CHECK: DISubprogram does not Verify
+!13 = !{i32 2, i32 2, !4, null}
diff --git a/test/Instrumentation/MemorySanitizer/atomics.ll b/test/Instrumentation/MemorySanitizer/atomics.ll
index c8f3b88815bb..28736ad79029 100644
--- a/test/Instrumentation/MemorySanitizer/atomics.ll
+++ b/test/Instrumentation/MemorySanitizer/atomics.ll
@@ -1,4 +1,6 @@
 ; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
+; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck %s
+; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=2 -S | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/test/Linker/distinct-cycles.ll b/test/Linker/distinct-cycles.ll
new file mode 100644
index 000000000000..b9b496c50c14
--- /dev/null
+++ b/test/Linker/distinct-cycles.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-link -o - -S %s | FileCheck %s
+; Crasher for PR22456: MapMetadata() should resolve all cycles.
+
+; CHECK: !named = !{!0}
+!named = !{!0}
+
+; CHECK: !0 = distinct !{!1}
+!0 = distinct !{!1}
+
+; CHECK-NEXT: !1 = !{!2}
+; CHECK-NEXT: !2 = !{!1}
+!1 = !{!2}
+!2 = !{!1}
diff --git a/test/MC/ARM/pr22395-2.s b/test/MC/ARM/pr22395-2.s
new file mode 100644
index 000000000000..3d2a10d6bbbc
--- /dev/null
+++ b/test/MC/ARM/pr22395-2.s
@@ -0,0 +1,37 @@
+@ RUN: llvm-mc -triple armv4t-eabi -mattr +d16 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+	.text
+	.thumb
+
+	.p2align 2
+
+	.fpu vfpv3
+	vldmia r0, {d16-d31}
+@ CHECK: vldmia	r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
+@ CHECK-NOT: error: register expected
+
+	.fpu vfpv4
+	vldmia r0, {d16-d31}
+@ CHECK: vldmia	r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
+@ CHECK-NOT: error: register expected
+
+	.fpu neon
+	vldmia r0, {d16-d31}
+@ CHECK: vldmia	r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
+@ CHECK-NOT: error: register expected
+
+	.fpu neon-vfpv4
+	vldmia r0, {d16-d31}
+@ CHECK: vldmia	r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
+@ CHECK-NOT: error: register expected
+
+	.fpu neon-fp-armv8
+	vldmia r0, {d16-d31}
+@ CHECK: vldmia	r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
+@ CHECK-NOT: error: register expected
+
+	.fpu crypto-neon-fp-armv8
+	vldmia r0, {d16-d31}
+@ CHECK: vldmia	r0, {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31}
+@ CHECK-NOT: error: register expected
+
diff --git a/test/MC/COFF/bss_section.ll b/test/MC/COFF/bss_section.ll
index 1921eeb61a65..477b3dfbd3a6 100644
--- a/test/MC/COFF/bss_section.ll
+++ b/test/MC/COFF/bss_section.ll
@@ -6,4 +6,4 @@
 ; CHECK: .bss
 
 @thingy_linkonce = linkonce_odr global %struct.foo zeroinitializer, align 4
-; CHECK: .section .bss,"wb",discard,_thingy_linkonce
+; CHECK: .section .bss,"bw",discard,_thingy_linkonce
diff --git a/test/MC/COFF/const-gv-with-rel-init.ll b/test/MC/COFF/const-gv-with-rel-init.ll
index 7d3c5f631881..5d0460dbaeff 100644
--- a/test/MC/COFF/const-gv-with-rel-init.ll
+++ b/test/MC/COFF/const-gv-with-rel-init.ll
@@ -5,7 +5,7 @@ define void @f() {
 }
 
 @ptr = constant void ()* @f, section ".CRT$XLB", align 8
-; CHECK:  .section  .CRT$XLB,"rd"
+; CHECK:  .section  .CRT$XLB,"dr"
 
 @weak_array = weak_odr unnamed_addr constant [1 x i8*] [i8* bitcast (void ()* @f to i8*)]
-; CHECK:  .section  .rdata,"rd",discard,weak_array
+; CHECK:  .section  .rdata,"dr",discard,weak_array
diff --git a/test/MC/COFF/diff.s b/test/MC/COFF/diff.s
index 820272a40bf4..5111600c7449 100644
--- a/test/MC/COFF/diff.s
+++ b/test/MC/COFF/diff.s
@@ -1,5 +1,23 @@
 // RUN: llvm-mc -filetype=obj -triple i686-pc-mingw32 %s | llvm-readobj -s -sr -sd | FileCheck %s
 
+.section baz, "xr"
+	.def	X
+	.scl	2;
+	.type	32;
+	.endef
+	.globl	X
+X:
+	mov	Y-X+42,	%eax
+	retl
+
+	.def	Y
+	.scl	2;
+	.type	32;
+	.endef
+	.globl	Y
+Y:
+	retl
+
 	.def	 _foobar;
 	.scl	2;
 	.type	32;
@@ -30,3 +48,10 @@ _rust_crate:
 // CHECK:        SectionData (
 // CHECK-NEXT:     0000: 00000000 00000000 1C000000 20000000
 // CHECK-NEXT:   )
+
+// CHECK:        Name: baz
+// CHECK:        Relocations [
+// CHECK-NEXT:   ]
+// CHECK:        SectionData (
+// CHECK-NEXT:     0000: A1300000 00C3C3
+// CHECK-NEXT:   )
diff --git a/test/MC/COFF/global_ctors_dtors.ll b/test/MC/COFF/global_ctors_dtors.ll
index ca17f24a68e0..be92c27c0d8a 100644
--- a/test/MC/COFF/global_ctors_dtors.ll
+++ b/test/MC/COFF/global_ctors_dtors.ll
@@ -49,17 +49,17 @@ define i32 @main() nounwind {
   ret i32 0
 }
 
-; WIN32: .section .CRT$XCU,"rd"
+; WIN32: .section .CRT$XCU,"dr"
 ; WIN32: a_global_ctor
-; WIN32: .section .CRT$XCU,"rd",associative,{{_?}}b
+; WIN32: .section .CRT$XCU,"dr",associative,{{_?}}b
 ; WIN32: b_global_ctor
 ; WIN32-NOT: c_global_ctor
-; WIN32: .section .CRT$XTX,"rd"
+; WIN32: .section .CRT$XTX,"dr"
 ; WIN32: a_global_dtor
-; MINGW32: .section .ctors,"wd"
+; MINGW32: .section .ctors,"dw"
 ; MINGW32: a_global_ctor
-; MINGW32: .section .ctors,"wd",associative,{{_?}}b
+; MINGW32: .section .ctors,"dw",associative,{{_?}}b
 ; MINGW32: b_global_ctor
 ; MINGW32-NOT: c_global_ctor
-; MINGW32: .section .dtors,"wd"
+; MINGW32: .section .dtors,"dw"
 ; MINGW32: a_global_dtor
diff --git a/test/MC/COFF/initialised-data.ll b/test/MC/COFF/initialised-data.ll
index c4284696b8ca..a2faac748567 100644
--- a/test/MC/COFF/initialised-data.ll
+++ b/test/MC/COFF/initialised-data.ll
@@ -3,5 +3,5 @@
 
 @data = dllexport constant [5 x i8] c"data\00", align 1
 
-; CHECK: .section	.rdata,"rd"
+; CHECK: .section	.rdata,"dr"
 
diff --git a/test/MC/COFF/section-passthru-flags.s b/test/MC/COFF/section-passthru-flags.s
index 3bd061b391d1..96e42d23351e 100644
--- a/test/MC/COFF/section-passthru-flags.s
+++ b/test/MC/COFF/section-passthru-flags.s
@@ -3,5 +3,5 @@
 // CHECK: .section .klaatu,"wn"
 .section .barada,"y"
 // CHECK: .section .barada,"y"
-.section .nikto,"wds"
-// CHECK: .section .nikto,"wds"
+.section .nikto,"dws"
+// CHECK: .section .nikto,"dws"
diff --git a/test/MC/COFF/weak-symbol.ll b/test/MC/COFF/weak-symbol.ll
index fd78307c1f22..0ab860cad462 100644
--- a/test/MC/COFF/weak-symbol.ll
+++ b/test/MC/COFF/weak-symbol.ll
@@ -28,20 +28,20 @@ define weak void @f() section ".sect" {
 }

 

 ; Weak global

-; X86: .section .data,"rd",discard,_a

+; X86: .section .data,"dr",discard,_a

 ; X86: .globl _a

 ; X86: .zero 12

 ;

-; X64: .section .data,"rd",discard,a

+; X64: .section .data,"dr",discard,a

 ; X64: .globl a

 ; X64: .zero 12

 @a = weak unnamed_addr constant { i32, i32, i32 } { i32 0, i32 0, i32 0}, section ".data"

 

-; X86:  .section        .tls$,"wd",discard,_b

+; X86:  .section        .tls$,"dw",discard,_b

 ; X86:  .globl  _b

 ; X86:  .long   0

 ;

-; X64:  .section        .tls$,"wd",discard,b

+; X64:  .section        .tls$,"dw",discard,b

 ; X64:  .globl  b

 ; X64:  .long   0

 

diff --git a/test/Transforms/EarlyCSE/basic.ll b/test/Transforms/EarlyCSE/basic.ll
index 155d36f60e21..3ec8831def18 100644
--- a/test/Transforms/EarlyCSE/basic.ll
+++ b/test/Transforms/EarlyCSE/basic.ll
@@ -192,4 +192,13 @@ define void @test11(i32 *%P) {
   ; CHECK-NEXT: ret void
 }
 
-
+; CHECK-LABEL: @test12(
+define i32 @test12(i1 %B, i32* %P1, i32* %P2) {
+  %load0 = load i32* %P1
+  %1 = load atomic i32* %P2 seq_cst, align 4
+  %load1 = load i32* %P1
+  %sel = select i1 %B, i32 %load0, i32 %load1
+  ret i32 %sel
+  ; CHECK: load i32* %P1
+  ; CHECK: load i32* %P1
+}
diff --git a/test/Transforms/Inline/inline-indirect.ll b/test/Transforms/Inline/inline-indirect.ll
new file mode 100644
index 000000000000..f6eb528e0650
--- /dev/null
+++ b/test/Transforms/Inline/inline-indirect.ll
@@ -0,0 +1,19 @@
+; RUN: opt < %s -inline -disable-output 2>/dev/null
+; This test used to trigger an assertion in the assumption cache when
+; inlining the indirect call
+declare void @llvm.assume(i1)
+
+define void @foo() {
+  ret void
+}
+
+define void @bar(void ()*) {
+  call void @llvm.assume(i1 true)
+  call void %0();
+  ret void
+}
+
+define void @baz() {
+  call void @bar(void ()* @foo)
+  ret void
+}
diff --git a/test/Transforms/InstCombine/loadstore-metadata.ll b/test/Transforms/InstCombine/loadstore-metadata.ll
index ad6a11cf6eb1..3d18ac0e3344 100644
--- a/test/Transforms/InstCombine/loadstore-metadata.ll
+++ b/test/Transforms/InstCombine/loadstore-metadata.ll
@@ -1,5 +1,7 @@
 ; RUN: opt -instcombine -S < %s | FileCheck %s
 
+target datalayout = "e-m:e-p:64:64:64-i64:64-f80:128-n8:16:32:64-S128"
+
 define i32 @test_load_cast_combine_tbaa(float* %ptr) {
 ; Ensure (cast (load (...))) -> (load (cast (...))) preserves TBAA.
 ; CHECK-LABEL: @test_load_cast_combine_tbaa(
diff --git a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
index 26b294042d42..f4edf092641f 100644
--- a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
+++ b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
@@ -201,7 +201,7 @@ for.end:                                          ; preds = %for.body
 ;
 ; Currently we have three extra add.w's that keep the store address
 ; live past the next increment because ISEL is unfortunately undoing
-; the store chain. ISEL also fails to convert all but one of the stores to
+; the store chain. ISEL also fails to convert the stores to
 ; post-increment addressing. However, the loads should use
 ; post-increment addressing, no add's or add.w's beyond the three
 ; mentioned. Most importantly, there should be no spills or reloads!
@@ -210,7 +210,7 @@ for.end:                                          ; preds = %for.body
 ; A9: %.lr.ph
 ; A9-NOT: lsl.w
 ; A9-NOT: {{ldr|str|adds|add r}}
-; A9: vst1.8 {{.*}} [r{{[0-9]+}}]!
+; A9: add.w r
 ; A9-NOT: {{ldr|str|adds|add r}}
 ; A9: add.w r
 ; A9-NOT: {{ldr|str|adds|add r}}
diff --git a/test/Transforms/MemCpyOpt/callslot_aa.ll b/test/Transforms/MemCpyOpt/callslot_aa.ll
new file mode 100644
index 000000000000..b6ea129ccfa7
--- /dev/null
+++ b/test/Transforms/MemCpyOpt/callslot_aa.ll
@@ -0,0 +1,22 @@
+; RUN: opt < %s -S -basicaa -memcpyopt | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+%T = type { i64, i64 }
+
+define void @test(i8* %src) {
+  %tmp = alloca i8
+  %dst = alloca i8
+; CHECK:   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 1, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp, i8* %src, i64 1, i32 8, i1 false), !noalias !2
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %tmp, i64 1, i32 8, i1 false)
+
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)
+
+; Check that the noalias for "dst" was removed by checking that the metadata is gone
+; CHECK-NOT: "dst"
+!0 = !{!0}
+!1 = distinct !{!1, !0, !"dst"}
+!2 = distinct !{!1}
diff --git a/test/Transforms/SLPVectorizer/X86/bad_types.ll b/test/Transforms/SLPVectorizer/X86/bad_types.ll
new file mode 100644
index 000000000000..38ed18dad2ac
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/bad_types.ll
@@ -0,0 +1,50 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -S -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @test1(x86_mmx %a, x86_mmx %b, i64* %ptr) {
+; Ensure we can handle x86_mmx values which are primitive and can be bitcast
+; with integer types but can't be put into a vector.
+;
+; CHECK-LABEL: @test1
+; CHECK:         store i64
+; CHECK:         store i64
+; CHECK:         ret void
+entry:
+  %a.cast = bitcast x86_mmx %a to i64
+  %b.cast = bitcast x86_mmx %b to i64
+  %a.and = and i64 %a.cast, 42
+  %b.and = and i64 %b.cast, 42
+  %gep = getelementptr i64* %ptr, i32 1
+  store i64 %a.and, i64* %ptr
+  store i64 %b.and, i64* %gep
+  ret void
+}
+
+define void @test2(x86_mmx %a, x86_mmx %b) {
+; Same as @test1 but using phi-input vectorization instead of store
+; vectorization.
+;
+; CHECK-LABEL: @test2
+; CHECK:         and i64
+; CHECK:         and i64
+; CHECK:         ret void
+entry:
+  br i1 undef, label %if.then, label %exit
+
+if.then:
+  %a.cast = bitcast x86_mmx %a to i64
+  %b.cast = bitcast x86_mmx %b to i64
+  %a.and = and i64 %a.cast, 42
+  %b.and = and i64 %b.cast, 42
+  br label %exit
+
+exit:
+  %a.phi = phi i64 [ 0, %entry ], [ %a.and, %if.then ]
+  %b.phi = phi i64 [ 0, %entry ], [ %b.and, %if.then ]
+  tail call void @f(i64 %a.phi, i64 %b.phi)
+  ret void
+}
+
+declare void @f(i64, i64)
diff --git a/test/Transforms/Util/combine-alias-scope-metadata.ll b/test/Transforms/Util/combine-alias-scope-metadata.ll
new file mode 100644
index 000000000000..fd0a3d5c5b92
--- /dev/null
+++ b/test/Transforms/Util/combine-alias-scope-metadata.ll
@@ -0,0 +1,24 @@
+; RUN: opt < %s -S -basicaa -memcpyopt | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define void @test(i8* noalias dereferenceable(1) %in, i8* noalias dereferenceable(1) %out) {
+  %tmp = alloca i8
+  %tmp2 = alloca i8
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 1, i32 8, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp, i8* %in, i64 1, i32 8, i1 false), !alias.scope !4
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp2, i8* %tmp, i64 1, i32 8, i1 false), !alias.scope !5
+
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %tmp2, i64 1, i32 8, i1 false), !noalias !6
+
+  ret void
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)
+
+!0 = !{!0}
+!1 = distinct !{!1, !0, !"in"}
+!2 = distinct !{!2, !0, !"tmp"}
+!3 = distinct !{!3, !0, !"tmp2"}
+!4 = distinct !{!1, !2}
+!5 = distinct !{!2, !3}
+!6 = distinct !{!1, !2}
diff --git a/test/tools/gold/no-map-whole-file.ll b/test/tools/gold/no-map-whole-file.ll
new file mode 100644
index 000000000000..21a0c46d28b0
--- /dev/null
+++ b/test/tools/gold/no-map-whole-file.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as -o %t.bc %s
+; RUN: ld -plugin %llvmshlibdir/LLVMgold.so -plugin-opt=emit-llvm \
+; RUN:    --no-map-whole-files -r -o %t2.bc %t.bc
+; RUN: llvm-dis < %t2.bc -o - | FileCheck %s
+
+; CHECK: main
+define i32 @main() {
+  ret i32 0
+}