diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2018-08-02 17:32:43 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-08-02 17:32:43 +0000 |
| commit | b7eb8e35e481a74962664b63dfb09483b200209a (patch) | |
| tree | 1937fb4a348458ce2d02ade03ac3bb0aa18d2fcd /test | |
| parent | eb11fae6d08f479c0799db45860a98af528fa6e7 (diff) | |
| download | src-test2-b7eb8e35e481a74962664b63dfb09483b200209a.tar.gz src-test2-b7eb8e35e481a74962664b63dfb09483b200209a.zip | |
Notes
Diffstat (limited to 'test')
556 files changed, 18516 insertions, 2437 deletions
diff --git a/test/Analysis/BasicAA/invalidation.ll b/test/Analysis/BasicAA/invalidation.ll index 0eaf7752f89b..27e94cb6a2e2 100644 --- a/test/Analysis/BasicAA/invalidation.ll +++ b/test/Analysis/BasicAA/invalidation.ll @@ -24,6 +24,18 @@ ; CHECK-LI-INVALIDATE: Invalidating analysis: BasicAA ; CHECK-LI-INVALIDATE: Running pass: AAEvaluator ; CHECK-LI-INVALIDATE: Running analysis: BasicAA +; +; Check PhiValues specifically. +; RUN: opt -disable-output -disable-verify -debug-pass-manager %s 2>&1 \ +; RUN: -passes='require<phi-values>,require<aa>,invalidate<phi-values>,aa-eval' -aa-pipeline='basic-aa' \ +; RUN: | FileCheck %s --check-prefix=CHECK-PV-INVALIDATE +; CHECK-PV-INVALIDATE: Running pass: RequireAnalysisPass +; CHECK-PV-INVALIDATE: Running analysis: BasicAA +; CHECK-PV-INVALIDATE: Running pass: InvalidateAnalysisPass +; CHECK-PV-INVALIDATE: Invalidating analysis: PhiValuesAnalysis +; CHECK-PV-INVALIDATE: Invalidating analysis: BasicAA +; CHECK-PV-INVALIDATE: Running pass: AAEvaluator +; CHECK-PV-INVALIDATE: Running analysis: BasicAA ; Some code that will result in actual AA queries, including inside of a loop. ; FIXME: Sadly, none of these queries managed to use either the domtree or diff --git a/test/Analysis/BasicAA/phi-aa.ll b/test/Analysis/BasicAA/phi-aa.ll index e410520bc0fc..e57dd40f0047 100644 --- a/test/Analysis/BasicAA/phi-aa.ll +++ b/test/Analysis/BasicAA/phi-aa.ll @@ -1,5 +1,5 @@ -; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s -; RUN: opt < %s -aa-pipeline=basic-aa -passes=aa-eval -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s +; RUN: opt < %s -phi-values -basicaa -aa-eval -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s +; RUN: opt < %s -aa-pipeline=basic-aa -passes='require<phi-values>,aa-eval' -print-all-alias-modref-info -disable-output 2>&1 | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -78,3 +78,39 @@ declare i1 @cond(i32*) declare void @inc(i32*) +; When we have a chain of phis in nested loops we should recognise if there's +; actually only one underlying value. +; CHECK-LABEL: loop_phi_chain +; CHECK: NoAlias: i32* %val1, i32* @Y +; CHECK: NoAlias: i32* %val2, i32* @Y +; CHECK: NoAlias: i32* %val3, i32* @Y +define void @loop_phi_chain(i32 %a, i32 %b, i32 %c) { +entry: + br label %loop1 + +loop1: + %n1 = phi i32 [ 0, %entry ], [ %add1, %loop2 ] + %val1 = phi i32* [ @X, %entry ], [ %val2, %loop2 ] + %add1 = add i32 %n1, 1 + %cmp1 = icmp ne i32 %n1, 32 + br i1 %cmp1, label %loop2, label %end + +loop2: + %n2 = phi i32 [ 0, %loop1 ], [ %add2, %loop3 ] + %val2 = phi i32* [ %val1, %loop1 ], [ %val3, %loop3 ] + %add2 = add i32 %n2, 1 + %cmp2 = icmp ne i32 %n2, 32 + br i1 %cmp2, label %loop3, label %loop1 + +loop3: + %n3 = phi i32 [ 0, %loop2 ], [ %add3, %loop3 ] + %val3 = phi i32* [ %val2, %loop2 ], [ %val3, %loop3 ] + store i32 0, i32* %val3, align 4 + store i32 0, i32* @Y, align 4 + %add3 = add i32 %n3, 1 + %cmp3 = icmp ne i32 %n3, 32 + br i1 %cmp3, label %loop3, label %loop2 + +end: + ret void +} diff --git a/test/Analysis/BasicAA/phi-values-usage.ll b/test/Analysis/BasicAA/phi-values-usage.ll new file mode 100644 index 000000000000..c5120a31f43c --- /dev/null +++ b/test/Analysis/BasicAA/phi-values-usage.ll @@ -0,0 +1,50 @@ +; RUN: opt -debug-pass=Executions -phi-values -memcpyopt -instcombine -disable-output < %s 2>&1 | FileCheck %s + +; Check that phi values is not run when it's not already available, and that +; basicaa is freed after a pass that preserves CFG. + +; CHECK: Executing Pass 'Phi Values Analysis' +; CHECK: Executing Pass 'Basic Alias Analysis (stateless AA impl)' +; CHECK: Executing Pass 'Memory Dependence Analysis' +; CHECK: Executing Pass 'MemCpy Optimization' +; CHECK-DAG: Freeing Pass 'MemCpy Optimization' +; CHECK-DAG: Freeing Pass 'Phi Values Analysis' +; CHECK-DAG: Freeing Pass 'Memory Dependence Analysis' +; CHECK-DAG: Freeing Pass 'Basic Alias Analysis (stateless AA impl)' +; CHECK-NOT: Executing Pass 'Phi Values Analysis' +; CHECK: Executing Pass 'Basic Alias Analysis (stateless AA impl)' +; CHECK: Executing Pass 'Combine redundant instructions' + +declare void @otherfn([4 x i8]*) +declare i32 @__gxx_personality_v0(...) + +; This function is one where if we didn't free basicaa after memcpyopt then the +; usage of basicaa in instcombine would cause a segfault due to stale phi-values +; results being used. +define void @fn(i8* %this, i64* %ptr) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + %arr = alloca [4 x i8], align 8 + %gep1 = getelementptr inbounds [4 x i8], [4 x i8]* %arr, i64 0, i32 0 + br i1 undef, label %then, label %if + +if: + br label %then + +then: + %phi = phi i64* [ %ptr, %if ], [ null, %entry ] + store i8 1, i8* %gep1, align 8 + %load = load i64, i64* %phi, align 8 + %gep2 = getelementptr inbounds i8, i8* undef, i64 %load + %gep3 = getelementptr inbounds i8, i8* %gep2, i64 40 + invoke i32 undef(i8* undef) + to label %invoke unwind label %lpad + +invoke: + unreachable + +lpad: + landingpad { i8*, i32 } + catch i8* null + call void @otherfn([4 x i8]* nonnull %arr) + unreachable +} diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 9c9d22d8ff6c..c0a1a2a149db 100644 --- a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -141,7 +141,7 @@ define fp128 @test_quad_dump() { ret fp128 0xL00000000000000004000000000000000 } -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0:_(p0) = G_EXTRACT_VECTOR_ELT %1:_(<2 x p0>), %2:_(s32) (in function: vector_of_pointers_extractelement) +; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(p0) = G_EXTRACT_VECTOR_ELT %0:_(<2 x p0>), %3:_(s32) (in function: vector_of_pointers_extractelement) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement: @var = global <2 x i16*> zeroinitializer @@ -158,7 +158,7 @@ end: br label %block } -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0:_(<2 x p0>), %5:_(p0) :: (store 16 into `<2 x i16*>* undef`) (in function: vector_of_pointers_insertelement) +; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %2:_(<2 x p0>), %1:_(p0) :: (store 16 into `<2 x i16*>* undef`) (in function: vector_of_pointers_insertelement) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement: define void @vector_of_pointers_insertelement() { diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 65c6a4f90c70..2c8ee439d247 100644 --- a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -138,9 +138,9 @@ false: ; CHECK: %0:_(s32) = COPY $w0 ; CHECK: %[[reg100:[0-9]+]]:_(s32) = G_CONSTANT i32 100 ; CHECK: %[[reg200:[0-9]+]]:_(s32) = G_CONSTANT i32 200 -; CHECK: %[[reg0:[0-9]+]]:_(s32) = G_CONSTANT i32 0 -; CHECK: %[[reg1:[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: %[[reg2:[0-9]+]]:_(s32) = G_CONSTANT i32 2 +; CHECK: %[[reg1:[0-9]+]]:_(s32) = G_CONSTANT i32 1 +; CHECK: %[[reg0:[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: %[[regicmp100:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg100]](s32), %0 ; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]] ; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]] @@ -413,9 +413,9 @@ define i64* @trivial_bitcast(i8* %a) { ; CHECK: G_BR %[[CAST:bb\.[0-9]+]] ; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}: +; CHECK: $x0 = COPY [[A]] ; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}: -; CHECK: {{%[0-9]+}}:_(p0) = COPY [[A]] ; CHECK: G_BR %[[END]] define i64* @trivial_bitcast_with_copy(i8* %a) { br label %cast @@ -2147,3 +2147,15 @@ define i32 @test_atomicrmw_umax(i256* %addr) { %oldval.trunc = trunc i256 %oldval to i32 ret i32 %oldval.trunc } + +@addr = global i8* null + +define void @test_blockaddress() { +; CHECK-LABEL: name: test_blockaddress +; CHECK: [[BADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block) +; CHECK: G_STORE [[BADDR]](p0) + store i8* blockaddress(@test_blockaddress, %block), i8** @addr + indirectbr i8* blockaddress(@test_blockaddress, %block), [label %block] +block: + ret void +} diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-block-order.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-block-order.ll new file mode 100644 index 000000000000..89e2fecbe0f5 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-block-order.ll @@ -0,0 +1,19 @@ +; RUN: llc -O0 -o - %s | FileCheck %s +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64-unknown-linux-gnu" + +; CHECK-LABEL: testfn +; CHECK: ret +define void @testfn() { +start: + br label %bb2 + +bb1: + store i8 %0, i8* undef, align 4 + ret void + +bb2: + %0 = extractvalue { i32, i8 } undef, 1 + br label %bb1 +} + diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir b/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir new file mode 100644 index 000000000000..60b47db98ed6 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir @@ -0,0 +1,45 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - | FileCheck %s +--- | + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-none-linux-gnu" + + @addr = global i8* null + + define void @test_blockaddress() { + store i8* blockaddress(@test_blockaddress, %block), i8** @addr + indirectbr i8* blockaddress(@test_blockaddress, %block), [label %block] + + block: ; preds = %0 + ret void + } + +... +--- +name: test_blockaddress +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + ; CHECK-LABEL: name: test_blockaddress + ; CHECK: bb.0 (%ir-block.0): + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: [[BLOCK_ADDR:%[0-9]+]]:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block) + ; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @addr + ; CHECK: G_STORE [[BLOCK_ADDR]](p0), [[GV]](p0) :: (store 8 into @addr) + ; CHECK: G_BRINDIRECT [[BLOCK_ADDR]](p0) + ; CHECK: bb.1.block (address-taken): + ; CHECK: RET_ReallyLR + bb.1 (%ir-block.0): + %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block) + %1:_(p0) = G_GLOBAL_VALUE @addr + G_STORE %0(p0), %1(p0) :: (store 8 into @addr) + G_BRINDIRECT %0(p0) + + bb.2.block (address-taken): + RET_ReallyLR + +... + diff --git a/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir b/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir new file mode 100644 index 000000000000..43e77eba48f3 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir @@ -0,0 +1,64 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s +# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select -code-model=large %s | FileCheck %s --check-prefix=LARGE +--- | + ; ModuleID = 'blockaddress.ll' + source_filename = "blockaddress.ll" + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-none-linux-gnu" + + @addr = global i8* null + + define void @test_blockaddress() { + store i8* blockaddress(@test_blockaddress, %block), i8** @addr + indirectbr i8* blockaddress(@test_blockaddress, %block), [label %block] + + block: ; preds = %0 + ret void + } + +... +--- +name: test_blockaddress +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } +body: | + ; CHECK-LABEL: name: test_blockaddress + ; CHECK: bb.0 (%ir-block.0): + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: [[MOVaddrBA:%[0-9]+]]:gpr64 = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block) + ; CHECK: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr + ; CHECK: STRXui [[MOVaddrBA]], [[MOVaddr]], 0 :: (store 8 into @addr) + ; CHECK: BR [[MOVaddrBA]] + ; CHECK: bb.1.block (address-taken): + ; CHECK: RET_ReallyLR + ; LARGE-LABEL: name: test_blockaddress + ; LARGE: bb.0 (%ir-block.0): + ; LARGE: successors: %bb.1(0x80000000) + ; LARGE: [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 0 + ; LARGE: [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 16 + ; LARGE: [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block), 32 + ; LARGE: [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) blockaddress(@test_blockaddress, %ir-block.block), 48 + ; LARGE: [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0 + ; LARGE: [[MOVKXi3:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi1]], target-flags(aarch64-g1, aarch64-nc) @addr, 16 + ; LARGE: [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @addr, 32 + ; LARGE: [[MOVKXi5:%[0-9]+]]:gpr64common = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @addr, 48 + ; LARGE: STRXui [[MOVKXi2]], [[MOVKXi5]], 0 :: (store 8 into @addr) + ; LARGE: BR [[MOVKXi2]] + ; LARGE: bb.1.block (address-taken): + ; LARGE: RET_ReallyLR + bb.1 (%ir-block.0): + %0:gpr(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block) + %1:gpr(p0) = G_GLOBAL_VALUE @addr + G_STORE %0(p0), %1(p0) :: (store 8 into @addr) + G_BRINDIRECT %0(p0) + + bb.2.block (address-taken): + RET_ReallyLR + +... diff --git a/test/CodeGen/AArch64/O3-pipeline.ll b/test/CodeGen/AArch64/O3-pipeline.ll index e482682fc9d9..f0c7e4e67c12 100644 --- a/test/CodeGen/AArch64/O3-pipeline.ll +++ b/test/CodeGen/AArch64/O3-pipeline.ll @@ -154,6 +154,8 @@ ; CHECK-NEXT: Insert fentry calls ; CHECK-NEXT: Insert XRay ops ; CHECK-NEXT: Implement the 'patchable-function' attribute +; CHECK-NEXT: Machine Outliner +; CHECK-NEXT: FunctionPass Manager ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: AArch64 Assembly Printer diff --git a/test/CodeGen/AArch64/arm64-cse.ll b/test/CodeGen/AArch64/arm64-cse.ll index 030857df7779..36aa036c3c0f 100644 --- a/test/CodeGen/AArch64/arm64-cse.ll +++ b/test/CodeGen/AArch64/arm64-cse.ll @@ -12,7 +12,7 @@ entry: ; CHECK-NOT: sub ; CHECK: b.ge ; CHECK: sub -; CHECK: sub +; CHECK-NEXT: add ; CHECK-NOT: sub ; CHECK: ret %0 = load i32, i32* %offset, align 4 diff --git a/test/CodeGen/AArch64/arm64-memset-to-bzero.ll b/test/CodeGen/AArch64/arm64-memset-to-bzero.ll index 0afe1c006b0f..ab819a42729a 100644 --- a/test/CodeGen/AArch64/arm64-memset-to-bzero.ll +++ b/test/CodeGen/AArch64/arm64-memset-to-bzero.ll @@ -1,6 +1,6 @@ -; RUN: llc %s -mtriple=arm64-apple-darwin -o - | \ -; RUN: FileCheck --check-prefixes=CHECK,CHECK-DARWIN %s -; RUN: llc %s -mtriple=arm64-linux-gnu -o - | \ +; RUN: llc %s -enable-machine-outliner=never -mtriple=arm64-apple-darwin -o - \ +; RUN: | FileCheck --check-prefixes=CHECK,CHECK-DARWIN %s +; RUN: llc %s -enable-machine-outliner=never -mtriple=arm64-linux-gnu -o - | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK-LINUX %s ; <rdar://problem/14199482> ARM64: Calls to bzero() replaced with calls to memset() diff --git a/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll b/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll index 7efb4bf6d596..79cf99008433 100644 --- a/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll +++ b/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll @@ -1,9 +1,11 @@ ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -pass-remarks-analysis=asm-printer \ +; RUN: -verify-machineinstrs \ ; RUN: -pass-remarks-with-hotness=1 -asm-verbose=0 \ ; RUN: -debug-only=lazy-machine-block-freq,block-freq \ ; RUN: -debug-pass=Executions 2>&1 | FileCheck %s -check-prefix=HOTNESS ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -pass-remarks-analysis=asm-printer \ +; RUN: -verify-machineinstrs \ ; RUN: -pass-remarks-with-hotness=0 -asm-verbose=0 \ ; RUN: -debug-only=lazy-machine-block-freq,block-freq \ ; RUN: -debug-pass=Executions 2>&1 | FileCheck %s -check-prefix=NO_HOTNESS @@ -26,8 +28,10 @@ ; requested. (This hard-codes the previous pass to the Assembly Printer, ; please adjust accordingly.) -; HOTNESS: Executing Pass 'Implement the 'patchable-function' attribute' -; HOTNESS-NEXT: Freeing Pass 'Implement the 'patchable-function' attribute' +; HOTNESS: Freeing Pass 'Machine Outliner' +; HOTNESS-NEXT: Executing Pass 'Function Pass Manager' +; HOTNESS-NEXT: Executing Pass 'Verify generated machine code' +; HOTNESS-NEXT: Freeing Pass 'Verify generated machine code' ; HOTNESS-NEXT: Executing Pass 'Lazy Machine Block Frequency Analysis' ; HOTNESS-NEXT: Executing Pass 'Machine Optimization Remark Emitter' ; HOTNESS-NEXT: Building MachineBlockFrequencyInfo on the fly @@ -41,8 +45,10 @@ ; HOTNESS: arm64-summary-remarks.ll:5:0: 1 instructions in function (hotness: 33) -; NO_HOTNESS: Executing Pass 'Implement the 'patchable-function' attribute' -; NO_HOTNESS-NEXT: Freeing Pass 'Implement the 'patchable-function' attribute' +; NO_HOTNESS: Freeing Pass 'Machine Outliner' +; NO_HOTNESS-NEXT: Executing Pass 'Function Pass Manager' +; NO_HOTNESS-NEXT: Executing Pass 'Verify generated machine code' +; NO_HOTNESS-NEXT: Freeing Pass 'Verify generated machine code' ; NO_HOTNESS-NEXT: Executing Pass 'Lazy Machine Block Frequency Analysis' ; NO_HOTNESS-NEXT: Executing Pass 'Machine Optimization Remark Emitter' ; NO_HOTNESS-NEXT: Executing Pass 'AArch64 Assembly Printer' diff --git a/test/CodeGen/AArch64/cond-sel.ll b/test/CodeGen/AArch64/cond-sel.ll index b39cea1f6192..691cbcf1a5df 100644 --- a/test/CodeGen/AArch64/cond-sel.ll +++ b/test/CodeGen/AArch64/cond-sel.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s +; RUN: llc -enable-machine-outliner=never -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s +; RUN: llc -enable-machine-outliner=never -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s @var32 = global i32 0 @var64 = global i64 0 diff --git a/test/CodeGen/AArch64/machine-outliner-default.mir b/test/CodeGen/AArch64/machine-outliner-default.mir new file mode 100644 index 000000000000..698a2fc55b58 --- /dev/null +++ b/test/CodeGen/AArch64/machine-outliner-default.mir @@ -0,0 +1,71 @@ +# RUN: llc -mtriple=aarch64--- -run-pass=machine-outliner \ +# RUN: -verify-machineinstrs %s -o - | FileCheck %s + +--- | + define void @outline_1() #0 { ret void } + define void @outline_2() #0 { ret void } + define void @outline_3() #0 { ret void } + define void @dont_outline() #1 { ret void } + + attributes #0 = { noredzone minsize optsize } + attributes #1 = { noredzone } +... +--- + +name: outline_1 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: bb.0: + ; CHECK: OUTLINED + liveins: $w8, $wzr + $w8 = ORRWri $wzr, 1 + $w8 = ORRWri $wzr, 2 + $w8 = ORRWri $wzr, 3 + $w8 = ORRWri $wzr, 4 + RET undef $lr +... +--- + +name: outline_2 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: bb.0: + ; CHECK: OUTLINED + liveins: $w8, $wzr + $w8 = ORRWri $wzr, 1 + $w8 = ORRWri $wzr, 2 + $w8 = ORRWri $wzr, 3 + $w8 = ORRWri $wzr, 4 + RET undef $lr +... +--- + +name: outline_3 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: bb.0: + ; CHECK: OUTLINED + liveins: $w8, $wzr + $w8 = ORRWri $wzr, 1 + $w8 = ORRWri $wzr, 2 + $w8 = ORRWri $wzr, 3 + $w8 = ORRWri $wzr, 4 + RET undef $lr +... +--- + +name: dont_outline +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: bb.0: + ; CHECK-NOT: BL + liveins: $w8, $wzr + $w8 = ORRWri $wzr, 1 + $w8 = ORRWri $wzr, 2 + $w8 = ORRWri $wzr, 3 + $w8 = ORRWri $wzr, 4 + RET undef $lr diff --git a/test/CodeGen/AArch64/machine-outliner-flags.ll b/test/CodeGen/AArch64/machine-outliner-flags.ll index e00a19099cf2..c435093b794e 100644 --- a/test/CodeGen/AArch64/machine-outliner-flags.ll +++ b/test/CodeGen/AArch64/machine-outliner-flags.ll @@ -14,7 +14,7 @@ ; RUN: | FileCheck %s -check-prefix=NEVER ; RUN: llc %s -debug-pass=Structure -verify-machineinstrs \ -; RUN: -mtriple arm64---- -o /dev/null 2>&1 \ +; RUN: --debug-only=machine-outliner -mtriple arm64---- -o /dev/null 2>&1 \ ; RUN: | FileCheck %s -check-prefix=NOT-ADDED ; RUN: llc %s -O=0 -debug-pass=Structure -verify-machineinstrs \ @@ -27,10 +27,11 @@ ; Cases where it should be added: ; * -enable-machine-outliner ; * -enable-machine-outliner=always +; * -enable-machine-outliner is not passed (AArch64 supports +; target-default outlining) ; ; Cases where it should not be added: ; * -O0 or equivalent -; * -enable-machine-outliner is not passed ; * -enable-machine-outliner=never is passed ; ALWAYS: Machine Outliner @@ -38,7 +39,8 @@ ; ENABLE: Machine Outliner ; ENABLE: Machine Outliner: Running on all functions ; NEVER-NOT: Machine Outliner -; NOT-ADDED-NOT: Machine Outliner +; NOT-ADDED: Machine Outliner +; NOT-ADDED: Machine Outliner: Running on target-default functions ; OPTNONE-NOT: Machine Outliner define void @foo() { diff --git a/test/CodeGen/AArch64/machine-outliner-regsave.mir b/test/CodeGen/AArch64/machine-outliner-regsave.mir new file mode 100644 index 000000000000..6d00bd39cde7 --- /dev/null +++ b/test/CodeGen/AArch64/machine-outliner-regsave.mir @@ -0,0 +1,112 @@ +# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=prologepilog \ +# RUN: -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s +# Check that we save LR to a callee-saved register when possible. +# foo() should use a callee-saved register. However, bar() should not. +--- | + + define void @foo() #0 { + ret void + } + + define void @bar() #0 { + ret void + } + + attributes #0 = { minsize noinline noredzone "no-frame-pointer-elim"="true" } +... +--- +# Make sure that when we outline and a register is available, we +# use it to save + restore LR instead of SP. +# CHECK: name: foo +# CHECK-DAG: bb.0 +# CHECK-DAG: $x[[REG:[0-9]+]] = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0 +# CHECK-DAG: bb.1 +# CHECK-DAG: $x[[REG]] = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0 +# CHECK-DAG: bb.2 +# CHECK-DAG: $x[[REG]] = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0 +name: foo +tracksRegLiveness: true +fixedStack: +body: | + bb.0: + liveins: $lr, $w9 + $x25 = ORRXri $xzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 2 + bb.1: + liveins: $lr, $w9 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 2 + bb.2: + liveins: $lr, $w9 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 2 + RET undef $lr + +... +--- +# Convoluted case that shows that we'll still save to the stack when there are +# no approprate registers available. +# The live-in lists do not contain x16 or x17 since including them would cause +# nothing to be outlined. +# They also deliberately don't contain x18 to show that on Darwin we won't store +# to that. +# CHECK-LABEL: name: bar +# CHECK: early-clobber $sp = STRXpre $lr, $sp, -16 +# CHECK-NEXT: BL +# CHECK-DAG: early-clobber $sp, $lr = LDRXpost $sp, 16 +# CHECK: early-clobber $sp = STRXpre $lr, $sp, -16 +# CHECK-NEXT: BL +# CHECK-DAG: early-clobber $sp, $lr = LDRXpost $sp, 16 +# CHECK: early-clobber $sp = STRXpre $lr, $sp, -16 +# CHECK-NEXT: BL +# CHECK-NEXT: early-clobber $sp, $lr = LDRXpost $sp, 16 +name: bar +tracksRegLiveness: true +body: | + bb.0: + liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w12 = ORRWri $wzr, 2 + bb.1: + liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w12 = ORRWri $wzr, 2 + bb.2: + liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w12 = ORRWri $wzr, 2 + bb.3: + liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28 + RET undef $lr + diff --git a/test/CodeGen/AArch64/machine-outliner.ll b/test/CodeGen/AArch64/machine-outliner.ll index 1b45409b799a..9d922c27f884 100644 --- a/test/CodeGen/AArch64/machine-outliner.ll +++ b/test/CodeGen/AArch64/machine-outliner.ll @@ -82,17 +82,17 @@ define void @dog() #0 { ; CHECK: .p2align 2 ; CHECK-NEXT: [[OUTLINED]]: ; CHECK: orr w8, wzr, #0x1 -; CHECK-NEXT: str w8, [sp, #44] +; CHECK-NEXT: str w8, [sp, #28] ; CHECK-NEXT: orr w8, wzr, #0x2 -; CHECK-NEXT: str w8, [sp, #40] +; CHECK-NEXT: str w8, [sp, #24] ; CHECK-NEXT: orr w8, wzr, #0x3 -; CHECK-NEXT: str w8, [sp, #36] +; CHECK-NEXT: str w8, [sp, #20] ; CHECK-NEXT: orr w8, wzr, #0x4 -; CHECK-NEXT: str w8, [sp, #32] +; CHECK-NEXT: str w8, [sp, #16] ; CHECK-NEXT: mov w8, #5 -; CHECK-NEXT: str w8, [sp, #28] +; CHECK-NEXT: str w8, [sp, #12] ; CHECK-NEXT: orr w8, wzr, #0x6 -; CHECK-NEXT: str w8, [sp, #24] +; CHECK-NEXT: str w8, [sp, #8] ; CHECK-NEXT: ret attributes #0 = { noredzone "target-cpu"="cyclone" } diff --git a/test/CodeGen/AArch64/machine-outliner.mir b/test/CodeGen/AArch64/machine-outliner.mir index 024bee47075b..bd1abdccd44c 100644 --- a/test/CodeGen/AArch64/machine-outliner.mir +++ b/test/CodeGen/AArch64/machine-outliner.mir @@ -28,19 +28,19 @@ # CHECK-LABEL: name: main # CHECK: BL @OUTLINED_FUNCTION_[[F0:[0-9]+]] -# CHECK-NEXT: early-clobber $sp, $lr = LDRXpost $sp, 16 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG:[0-9]+]], 0 # CHECK-NEXT: $x16 = ADDXri $sp, 48, 0 # CHECK-NEXT: STRHHroW $w16, $x9, $w30, 1, 1 # CHECK-NEXT: $lr = ORRXri $xzr, 1 # CHECK: BL @OUTLINED_FUNCTION_[[F0]] -# CHECK-NEXT: early-clobber $sp, $lr = LDRXpost $sp, 16 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0 # CHECK-NEXT: $x16 = ADDXri $sp, 48, 0 # CHECK-NEXT: STRHHroW $w16, $x9, $w30, 1, 1 # CHECK-NEXT: $lr = ORRXri $xzr, 1 # CHECK: BL @OUTLINED_FUNCTION_[[F0]] -# CHECK-NEXT: early-clobber $sp, $lr = LDRXpost $sp, 16 +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0 # CHECK-NEXT: $x16 = ADDXri $sp, 48, 0 # CHECK-NEXT: STRHHroW $w16, $x9, $w30, 1, 1 # CHECK-NEXT: $lr = ORRXri $xzr, 1 diff --git a/test/CodeGen/AArch64/max-jump-table.ll b/test/CodeGen/AArch64/max-jump-table.ll index 612eba8f2ceb..44dde7b1cd06 100644 --- a/test/CodeGen/AArch64/max-jump-table.ll +++ b/test/CodeGen/AArch64/max-jump-table.ll @@ -89,6 +89,7 @@ entry: ; CHECKM1-NOT: %jump-table.1 ; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}} ; CHECKM3-NOT: %jump-table.1 +; CHECK-DAG: End machine code for function jt2. bb1: tail call void @ext(i32 1) br label %return bb2: tail call void @ext(i32 2) br label %return diff --git a/test/CodeGen/AArch64/rotate-extract.ll b/test/CodeGen/AArch64/rotate-extract.ll index 4f5313ca4a77..41664294b1c2 100644 --- a/test/CodeGen/AArch64/rotate-extract.ll +++ b/test/CodeGen/AArch64/rotate-extract.ll @@ -11,9 +11,8 @@ define i64 @ror_extract_shl(i64 %i) nounwind { ; CHECK-LABEL: ror_extract_shl: ; CHECK: // %bb.0: -; CHECK-NEXT: lsl x8, x0, #10 -; CHECK-NEXT: bfxil x8, x0, #54, #7 -; CHECK-NEXT: mov x0, x8 +; CHECK-NEXT: lsl x8, x0, #3 +; CHECK-NEXT: ror x0, x8, #57 ; CHECK-NEXT: ret %lhs_mul = shl i64 %i, 3 %rhs_mul = shl i64 %i, 10 @@ -25,8 +24,8 @@ define i64 @ror_extract_shl(i64 %i) nounwind { define i32 @ror_extract_shrl(i32 %i) nounwind { ; CHECK-LABEL: ror_extract_shrl: ; CHECK: // %bb.0: -; CHECK-NEXT: ror w8, w0, #7 -; CHECK-NEXT: and w0, w8, #0xf1ffffff +; CHECK-NEXT: lsr w8, w0, #3 +; CHECK-NEXT: ror w0, w8, #4 ; CHECK-NEXT: ret %lhs_div = lshr i32 %i, 7 %rhs_div = lshr i32 %i, 3 @@ -54,8 +53,8 @@ define i64 @ror_extract_udiv(i64 %i) nounwind { ; CHECK-NEXT: mov x8, #-6148914691236517206 ; CHECK-NEXT: movk x8, #43691 ; CHECK-NEXT: umulh x8, x0, x8 -; CHECK-NEXT: ror x8, x8, #5 -; CHECK-NEXT: and x0, x8, #0xf7ffffffffffffff +; CHECK-NEXT: lsr x8, x8, #1 +; CHECK-NEXT: ror x0, x8, #4 ; CHECK-NEXT: ret %lhs_div = udiv i64 %i, 3 %rhs_div = udiv i64 %i, 48 @@ -67,11 +66,9 @@ define i64 @ror_extract_udiv(i64 %i) nounwind { define i64 @ror_extract_mul_with_mask(i64 %i) nounwind { ; CHECK-LABEL: ror_extract_mul_with_mask: ; CHECK: // %bb.0: -; CHECK-NEXT: add w8, w0, w0, lsl #3 -; CHECK-NEXT: lsl w8, w8, #7 -; CHECK-NEXT: add x9, x0, x0, lsl #3 -; CHECK-NEXT: and x0, x8, #0x80 -; CHECK-NEXT: bfxil x0, x9, #57, #7 +; CHECK-NEXT: add x8, x0, x0, lsl #3 +; CHECK-NEXT: ror x8, x8, #57 +; CHECK-NEXT: and x0, x8, #0xff ; CHECK-NEXT: ret %lhs_mul = mul i64 %i, 1152 %rhs_mul = mul i64 %i, 9 diff --git a/test/CodeGen/AArch64/signbit-shift.ll b/test/CodeGen/AArch64/signbit-shift.ll index b554ce15872c..250290aa2348 100644 --- a/test/CodeGen/AArch64/signbit-shift.ll +++ b/test/CodeGen/AArch64/signbit-shift.ll @@ -150,8 +150,8 @@ define i32 @sext_ifneg(i32 %x) { define i32 @add_sext_ifneg(i32 %x) { ; CHECK-LABEL: add_sext_ifneg: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #42 -; CHECK-NEXT: sub w0, w8, w0, lsr #31 +; CHECK-NEXT: asr w8, w0, #31 +; CHECK-NEXT: add w0, w8, #42 // =42 ; CHECK-NEXT: ret %c = icmp slt i32 %x, 0 %e = sext i1 %c to i32 @@ -225,7 +225,7 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) { define i32 @sub_lshr(i32 %x, i32 %y) { ; CHECK-LABEL: sub_lshr: ; CHECK: // %bb.0: -; CHECK-NEXT: sub w0, w1, w0, lsr #31 +; CHECK-NEXT: add w0, w1, w0, asr #31 ; CHECK-NEXT: ret %sh = lshr i32 %x, 31 %r = sub i32 %y, %sh @@ -235,8 +235,8 @@ define i32 @sub_lshr(i32 %x, i32 %y) { define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: sub_lshr_vec: ; CHECK: // %bb.0: -; CHECK-NEXT: ushr v0.4s, v0.4s, #31 -; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s +; CHECK-NEXT: ssra v1.4s, v0.4s, #31 +; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: ret %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %r = sub <4 x i32> %y, %sh @@ -246,8 +246,8 @@ define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) { define i32 @sub_const_op_lshr(i32 %x) { ; CHECK-LABEL: sub_const_op_lshr: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #43 -; CHECK-NEXT: sub w0, w8, w0, lsr #31 +; CHECK-NEXT: asr w8, w0, #31 +; CHECK-NEXT: add w0, w8, #43 // =43 ; CHECK-NEXT: ret %sh = lshr i32 %x, 31 %r = sub i32 43, %sh @@ -257,9 +257,9 @@ define i32 @sub_const_op_lshr(i32 %x) { define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) { ; CHECK-LABEL: sub_const_op_lshr_vec: ; CHECK: // %bb.0: -; CHECK-NEXT: ushr v0.4s, v0.4s, #31 ; CHECK-NEXT: movi v1.4s, #42 -; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s +; CHECK-NEXT: ssra v1.4s, v0.4s, #31 +; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: ret %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh diff --git a/test/CodeGen/AMDGPU/bfi_int.ll b/test/CodeGen/AMDGPU/bfi_int.ll index 77c5e53481e7..66f8a2b111a5 100644 --- a/test/CodeGen/AMDGPU/bfi_int.ll +++ b/test/CodeGen/AMDGPU/bfi_int.ll @@ -54,8 +54,8 @@ entry: ; FUNC-LABEL: {{^}}v_bitselect_v2i32_pat1: ; GCN: s_waitcnt -; GCN-NEXT: v_bfi_b32 v1, v3, v1, v5 ; GCN-NEXT: v_bfi_b32 v0, v2, v0, v4 +; GCN-NEXT: v_bfi_b32 v1, v3, v1, v5 ; GCN-NEXT: s_setpc_b64 define <2 x i32> @v_bitselect_v2i32_pat1(<2 x i32> %a, <2 x i32> %b, <2 x i32> %mask) { %xor.0 = xor <2 x i32> %a, %mask diff --git a/test/CodeGen/AMDGPU/call-argument-types.ll b/test/CodeGen/AMDGPU/call-argument-types.ll index b0998355395d..2cea1414507b 100644 --- a/test/CodeGen/AMDGPU/call-argument-types.ll +++ b/test/CodeGen/AMDGPU/call-argument-types.ll @@ -17,16 +17,27 @@ declare void @external_void_func_i16_zeroext(i16 zeroext) #0 declare void @external_void_func_i32(i32) #0 declare void @external_void_func_i64(i64) #0 +declare void @external_void_func_v2i64(<2 x i64>) #0 +declare void @external_void_func_v3i64(<3 x i64>) #0 +declare void @external_void_func_v4i64(<4 x i64>) #0 declare void @external_void_func_f16(half) #0 declare void @external_void_func_f32(float) #0 declare void @external_void_func_f64(double) #0 +declare void @external_void_func_v2f32(<2 x float>) #0 +declare void @external_void_func_v2f64(<2 x double>) #0 +declare void @external_void_func_v3f64(<3 x double>) #0 declare void @external_void_func_v2i16(<2 x i16>) #0 declare void @external_void_func_v2f16(<2 x half>) #0 +declare void @external_void_func_v3i16(<3 x i16>) #0 +declare void @external_void_func_v3f16(<3 x half>) #0 +declare void @external_void_func_v4i16(<4 x i16>) #0 +declare void @external_void_func_v4f16(<4 x half>) #0 declare void @external_void_func_v2i32(<2 x i32>) #0 declare void @external_void_func_v3i32(<3 x i32>) #0 +declare void @external_void_func_v3i32_i32(<3 x i32>, i32) #0 declare void @external_void_func_v4i32(<4 x i32>) #0 declare void @external_void_func_v8i32(<8 x i32>) #0 declare void @external_void_func_v16i32(<16 x i32>) #0 @@ -255,6 +266,57 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 { ret void } +; GCN-LABEL: {{^}}test_call_external_void_func_v2i64: +; GCN: buffer_load_dwordx4 v[0:3] +; GCN: s_waitcnt +; GCN-NEXT: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 { + %val = load <2 x i64>, <2 x i64> addrspace(1)* null + call void @external_void_func_v2i64(<2 x i64> %val) + ret void +} + +; GCN-LABEL: {{^}}test_call_external_void_func_v2i64_imm: +; GCN-DAG: v_mov_b32_e32 v0, 1 +; GCN-DAG: v_mov_b32_e32 v1, 2 +; GCN-DAG: v_mov_b32_e32 v2, 3 +; GCN-DAG: v_mov_b32_e32 v3, 4 +; GCN: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 { + call void @external_void_func_v2i64(<2 x i64> <i64 8589934593, i64 17179869187>) + ret void +} + +; GCN-LABEL: {{^}}test_call_external_void_func_v3i64: +; GCN: buffer_load_dwordx4 v[0:3] +; GCN: v_mov_b32_e32 v4, 1 +; GCN: v_mov_b32_e32 v5, 2 +; GCN: s_waitcnt +; GCN-NEXT: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 { + %load = load <2 x i64>, <2 x i64> addrspace(1)* null + %val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 undef>, <3 x i32> <i32 0, i32 1, i32 2> + + call void @external_void_func_v3i64(<3 x i64> %val) + ret void +} + +; GCN-LABEL: {{^}}test_call_external_void_func_v4i64: +; GCN: buffer_load_dwordx4 v[0:3] +; GCN-DAG: v_mov_b32_e32 v4, 1 +; GCN-DAG: v_mov_b32_e32 v5, 2 +; GCN-DAG: v_mov_b32_e32 v6, 3 +; GCN-DAG: v_mov_b32_e32 v7, 4 + +; GCN: s_waitcnt +; GCN-NEXT: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 { + %load = load <2 x i64>, <2 x i64> addrspace(1)* null + %val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 17179869187>, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + call void @external_void_func_v4i64(<4 x i64> %val) + ret void +} + ; GCN-LABEL: {{^}}test_call_external_void_func_f16_imm: ; VI: v_mov_b32_e32 v0, 0x4400 ; CI: v_mov_b32_e32 v0, 4.0 @@ -274,6 +336,15 @@ define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 { ret void } +; GCN-LABEL: {{^}}test_call_external_void_func_v2f32_imm: +; GCN-DAG: v_mov_b32_e32 v0, 1.0 +; GCN-DAG: v_mov_b32_e32 v1, 2.0 +; GCN: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 { + call void @external_void_func_v2f32(<2 x float> <float 1.0, float 2.0>) + ret void +} + ; GCN-LABEL: {{^}}test_call_external_void_func_f64_imm: ; GCN: v_mov_b32_e32 v0, 0{{$}} ; GCN: v_mov_b32_e32 v1, 0x40100000 @@ -283,6 +354,30 @@ define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 { ret void } +; GCN-LABEL: {{^}}test_call_external_void_func_v2f64_imm: +; GCN: v_mov_b32_e32 v0, 0{{$}} +; GCN: v_mov_b32_e32 v1, 2.0 +; GCN: v_mov_b32_e32 v2, 0{{$}} +; GCN: v_mov_b32_e32 v3, 0x40100000 +; GCN: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 { + call void @external_void_func_v2f64(<2 x double> <double 2.0, double 4.0>) + ret void +} + +; GCN-LABEL: {{^}}test_call_external_void_func_v3f64_imm: +; GCN-DAG: v_mov_b32_e32 v0, 0{{$}} +; GCN-DAG: v_mov_b32_e32 v1, 2.0 +; GCN-DAG: v_mov_b32_e32 v2, 0{{$}} +; GCN-DAG: v_mov_b32_e32 v3, 0x40100000 +; GCN-DAG: v_mov_b32_e32 v4, 0{{$}} +; GCN-DAG: v_mov_b32_e32 v5, 0x40200000 +; GCN-DAG: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 { + call void @external_void_func_v3f64(<3 x double> <double 2.0, double 4.0, double 8.0>) + ret void +} + ; GCN-LABEL: {{^}}test_call_external_void_func_v2i16: ; GFX9: buffer_load_dword v0 ; GFX9-NOT: v0 @@ -293,6 +388,49 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 { ret void } +; GCN-LABEL: {{^}}test_call_external_void_func_v3i16: +; GFX9: buffer_load_dwordx2 v[0:1] +; GFX9-NOT: v0 +; GFX9-NOT: v1 +; GFX9: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 { + %val = load <3 x i16>, <3 x i16> addrspace(1)* undef + call void @external_void_func_v3i16(<3 x i16> %val) + ret void +} + +; FIXME: materialize constant directly in VGPR +; GCN-LABEL: {{^}}test_call_external_void_func_v3i16_imm: +; GFX9-DAG: s_mov_b32 [[K01:s[0-9]+]], 0x20001 +; GFX9-DAG: s_pack_ll_b32_b16 [[K23:s[0-9]+]], 3, s{{[0-9]+}} +; GFX9: v_mov_b32_e32 v0, [[K01]] +; GFX9: v_mov_b32_e32 v1, [[K23]] +; GFX9: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v3i16_imm() #0 { + call void @external_void_func_v3i16(<3 x i16> <i16 1, i16 2, i16 3>) + ret void +} + +; GCN-LABEL: {{^}}test_call_external_void_func_v4i16: +; GFX9: buffer_load_dwordx2 v[0:1] +; GFX9-NOT: v0 +; GFX9-NOT: v1 +; GFX9: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 { + %val = load <4 x i16>, <4 x i16> addrspace(1)* undef + call void @external_void_func_v4i16(<4 x i16> %val) + ret void +} + +; GCN-LABEL: {{^}}test_call_external_void_func_v4i16_imm: +; GFX9-DAG: v_mov_b32_e32 v0, 0x20001 +; GFX9-DAG: v_mov_b32_e32 v1, 0x40003 +; GFX9: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 { + call void @external_void_func_v4i16(<4 x i16> <i16 1, i16 2, i16 3, i16 4>) + ret void +} + ; GCN-LABEL: {{^}}test_call_external_void_func_v2f16: ; GFX9: buffer_load_dword v0 ; GFX9-NOT: v0 @@ -313,15 +451,23 @@ define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 { ret void } -; FIXME: Passing 4th +; GCN-LABEL: {{^}}test_call_external_void_func_v2i32_imm: +; GCN-DAG: v_mov_b32_e32 v0, 1 +; GCN-DAG: v_mov_b32_e32 v1, 2 +; GCN: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 { + call void @external_void_func_v2i32(<2 x i32> <i32 1, i32 2>) + ret void +} + ; GCN-LABEL: {{^}}test_call_external_void_func_v3i32_imm: ; HSA-DAG: s_mov_b32 s33, s9 ; MESA-DAG: s_mov_b32 s33, s3{{$}} -; GCN-DAG: v_mov_b32_e32 v0 -; GCN-DAG: v_mov_b32_e32 v1 -; GCN-DAG: v_mov_b32_e32 v2 -; GCN-DAG: v_mov_b32_e32 v3 +; GCN-DAG: v_mov_b32_e32 v0, 3 +; GCN-DAG: v_mov_b32_e32 v1, 4 +; GCN-DAG: v_mov_b32_e32 v2, 5 +; GCN-NOT: v3 ; GCN: s_swappc_b64 define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 { @@ -329,6 +475,16 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 { ret void } +; GCN-LABEL: {{^}}test_call_external_void_func_v3i32_i32: +; GCN-DAG: v_mov_b32_e32 v0, 3 +; GCN-DAG: v_mov_b32_e32 v1, 4 +; GCN-DAG: v_mov_b32_e32 v2, 5 +; GCN-DAG: v_mov_b32_e32 v3, 6 +define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 { + call void @external_void_func_v3i32_i32(<3 x i32> <i32 3, i32 4, i32 5>, i32 6) + ret void +} + ; GCN-LABEL: {{^}}test_call_external_void_func_v4i32: ; GCN: buffer_load_dwordx4 v[0:3] ; GCN: s_waitcnt @@ -339,6 +495,17 @@ define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 { ret void } +; GCN-LABEL: {{^}}test_call_external_void_func_v4i32_imm: +; GCN-DAG: v_mov_b32_e32 v0, 1 +; GCN-DAG: v_mov_b32_e32 v1, 2 +; GCN-DAG: v_mov_b32_e32 v2, 3 +; GCN-DAG: v_mov_b32_e32 v3, 4 +; GCN: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 { + call void @external_void_func_v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>) + ret void +} + ; GCN-LABEL: {{^}}test_call_external_void_func_v8i32: ; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off @@ -351,6 +518,21 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 { ret void } +; GCN-LABEL: {{^}}test_call_external_void_func_v8i32_imm: +; GCN-DAG: v_mov_b32_e32 v0, 1 +; GCN-DAG: v_mov_b32_e32 v1, 2 +; GCN-DAG: v_mov_b32_e32 v2, 3 +; GCN-DAG: v_mov_b32_e32 v3, 4 +; GCN-DAG: v_mov_b32_e32 v4, 5 +; GCN-DAG: v_mov_b32_e32 v5, 6 +; GCN-DAG: v_mov_b32_e32 v6, 7 +; GCN-DAG: v_mov_b32_e32 v7, 8 +; GCN: s_swappc_b64 +define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 { + call void @external_void_func_v8i32(<8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>) + ret void +} + ; GCN-LABEL: {{^}}test_call_external_void_func_v16i32: ; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off diff --git a/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll b/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll index a4db46b47500..d72dbf9e6ec0 100644 --- a/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll +++ b/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll @@ -225,7 +225,7 @@ define amdgpu_kernel void @test_fold_canonicalize_fpround_value_v2f16_v2f32(<2 x } ; GCN-LABEL: test_no_fold_canonicalize_fneg_value_f32: -; GCN-FLUSH: v_mul_f32_e64 v{{[0-9]+}}, 1.0, -v{{[0-9]+}} +; GCN-FLUSH: v_mul_f32_e32 v{{[0-9]+}}, -1.0, v{{[0-9]+}} ; GCN-DENORM: v_max_f32_e64 v{{[0-9]+}}, -v{{[0-9]+}}, -v{{[0-9]+}} define amdgpu_kernel void @test_no_fold_canonicalize_fneg_value_f32(float addrspace(1)* %arg) { %id = tail call i32 @llvm.amdgcn.workitem.id.x() diff --git a/test/CodeGen/AMDGPU/fcanonicalize.f16.ll b/test/CodeGen/AMDGPU/fcanonicalize.f16.ll index 7cc556ce168d..52d891964c48 100644 --- a/test/CodeGen/AMDGPU/fcanonicalize.f16.ll +++ b/test/CodeGen/AMDGPU/fcanonicalize.f16.ll @@ -1,5 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s +; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s declare half @llvm.fabs.f16(half) #0 declare half @llvm.canonicalize.f16(half) #0 @@ -9,18 +10,21 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0 ; GCN-LABEL: {{^}}v_test_canonicalize_var_f16: -; GCN: v_max_f16_e32 [[REG:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_max_f16_e32 [[REG:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] + +; CI: v_cvt_f32_f16_e32 +; CI: v_mul_f32_e32 {{v[0-9]+}}, 1.0, {{v[0-9]+}} define amdgpu_kernel void @v_test_canonicalize_var_f16(half addrspace(1)* %out) #1 { %val = load half, half addrspace(1)* %out %canonicalized = call half @llvm.canonicalize.f16(half %val) - store half %canonicalized, half addrspace(1)* %out + store half %canonicalized, half addrspace(1)* undef ret void } ; GCN-LABEL: {{^}}s_test_canonicalize_var_f16: -; GCN: v_max_f16_e64 [[REG:v[0-9]+]], {{s[0-9]+}}, {{s[0-9]+}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_max_f16_e64 [[REG:v[0-9]+]], {{s[0-9]+}}, {{s[0-9]+}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @s_test_canonicalize_var_f16(half addrspace(1)* %out, i16 zeroext %val.arg) #1 { %val = bitcast i16 %val.arg to half %canonicalized = call half @llvm.canonicalize.f16(half %val) @@ -29,8 +33,8 @@ define amdgpu_kernel void @s_test_canonicalize_var_f16(half addrspace(1)* %out, } ; GCN-LABEL: {{^}}v_test_canonicalize_fabs_var_f16: -; GCN: v_max_f16_e64 [[REG:v[0-9]+]], |{{v[0-9]+}}|, |{{v[0-9]+}}| -; GCN: buffer_store_short [[REG]] +; GFX89: v_max_f16_e64 [[REG:v[0-9]+]], |{{v[0-9]+}}|, |{{v[0-9]+}}| +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @v_test_canonicalize_fabs_var_f16(half addrspace(1)* %out) #1 { %val = load half, half addrspace(1)* %out %val.fabs = call half @llvm.fabs.f16(half %val) @@ -40,8 +44,11 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_f16(half addrspace(1)* % } ; GCN-LABEL: {{^}}v_test_canonicalize_fneg_fabs_var_f16: -; GCN: v_max_f16_e64 [[REG:v[0-9]+]], -|{{v[0-9]+}}|, -|{{v[0-9]+}}| -; GCN: buffer_store_short [[REG]] +; GFX89: v_max_f16_e64 [[REG:v[0-9]+]], -|{{v[0-9]+}}|, -|{{v[0-9]+}}| +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] + +; CI: v_cvt_f32_f16_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| +; CI: v_mul_f32_e32 {{v[0-9]+}}, 1.0, {{v[0-9]+}} define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_f16(half addrspace(1)* %out) #1 { %val = load half, half addrspace(1)* %out %val.fabs = call half @llvm.fabs.f16(half %val) @@ -52,8 +59,11 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_f16(half addrspace( } ; GCN-LABEL: {{^}}v_test_canonicalize_fneg_var_f16: -; GCN: v_max_f16_e64 [[REG:v[0-9]+]], -{{v[0-9]+}}, -{{v[0-9]+}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_max_f16_e64 [[REG:v[0-9]+]], -{{v[0-9]+}}, -{{v[0-9]+}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] + +; CI: v_cvt_f32_f16_e64 {{v[0-9]+}}, -{{v[0-9]+}} +; CI: v_mul_f32_e32 {{v[0-9]+}}, 1.0, {{v[0-9]+}} define amdgpu_kernel void @v_test_canonicalize_fneg_var_f16(half addrspace(1)* %out) #1 { %val = load half, half addrspace(1)* %out %val.fneg = fsub half -0.0, %val @@ -62,9 +72,35 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_var_f16(half addrspace(1)* % ret void } +; GCN-LABEL: {{^}}v_test_no_denormals_canonicalize_fneg_var_f16: +; GFX89: v_mul_f16_e32 [[REG:v[0-9]+]], -1.0, v{{[0-9]+}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] +define amdgpu_kernel void @v_test_no_denormals_canonicalize_fneg_var_f16(half addrspace(1)* %out) #2 { + %val = load half, half addrspace(1)* %out + %val.fneg = fsub half -0.0, %val + %canonicalized = call half @llvm.canonicalize.f16(half %val.fneg) + store half %canonicalized, half addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_test_no_denormals_canonicalize_fneg_fabs_var_f16: +; GFX89: v_mul_f16_e64 [[REG:v[0-9]+]], -1.0, |v{{[0-9]+}}| +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] + +; CI: v_cvt_f32_f16_e64 {{v[0-9]+}}, -|{{v[0-9]+}}| +; CI: v_mul_f32_e32 {{v[0-9]+}}, 1.0, {{v[0-9]+}} +define amdgpu_kernel void @v_test_no_denormals_canonicalize_fneg_fabs_var_f16(half addrspace(1)* %out) #2 { + %val = load half, half addrspace(1)* %out + %val.fabs = call half @llvm.fabs.f16(half %val) + %val.fabs.fneg = fsub half -0.0, %val.fabs + %canonicalized = call half @llvm.canonicalize.f16(half %val.fabs.fneg) + store half %canonicalized, half addrspace(1)* %out + ret void +} + ; GCN-LABEL: {{^}}test_fold_canonicalize_p0_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_p0_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 0.0) store half %canonicalized, half addrspace(1)* %out @@ -72,8 +108,8 @@ define amdgpu_kernel void @test_fold_canonicalize_p0_f16(half addrspace(1)* %out } ; GCN-LABEL: {{^}}test_fold_canonicalize_n0_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff8000{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff8000{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_n0_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half -0.0) store half %canonicalized, half addrspace(1)* %out @@ -81,8 +117,8 @@ define amdgpu_kernel void @test_fold_canonicalize_n0_f16(half addrspace(1)* %out } ; GCN-LABEL: {{^}}test_fold_canonicalize_p1_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3c00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3c00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_p1_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 1.0) store half %canonicalized, half addrspace(1)* %out @@ -90,8 +126,8 @@ define amdgpu_kernel void @test_fold_canonicalize_p1_f16(half addrspace(1)* %out } ; GCN-LABEL: {{^}}test_fold_canonicalize_n1_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffbc00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffbc00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_n1_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half -1.0) store half %canonicalized, half addrspace(1)* %out @@ -99,8 +135,8 @@ define amdgpu_kernel void @test_fold_canonicalize_n1_f16(half addrspace(1)* %out } ; GCN-LABEL: {{^}}test_fold_canonicalize_literal_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x4c00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x4c00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_literal_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 16.0) store half %canonicalized, half addrspace(1)* %out @@ -108,8 +144,8 @@ define amdgpu_kernel void @test_fold_canonicalize_literal_f16(half addrspace(1)* } ; GCN-LABEL: {{^}}test_default_denormals_fold_canonicalize_denormal0_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3ff{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3ff{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_default_denormals_fold_canonicalize_denormal0_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 0xH03FF) store half %canonicalized, half addrspace(1)* %out @@ -117,8 +153,8 @@ define amdgpu_kernel void @test_default_denormals_fold_canonicalize_denormal0_f1 } ; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal0_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3ff{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3ff{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_f16(half addrspace(1)* %out) #3 { %canonicalized = call half @llvm.canonicalize.f16(half 0xH03FF) store half %canonicalized, half addrspace(1)* %out @@ -126,8 +162,8 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_f16(half a } ; GCN-LABEL: {{^}}test_default_denormals_fold_canonicalize_denormal1_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff83ff{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff83ff{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_default_denormals_fold_canonicalize_denormal1_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 0xH83FF) store half %canonicalized, half addrspace(1)* %out @@ -135,8 +171,8 @@ define amdgpu_kernel void @test_default_denormals_fold_canonicalize_denormal1_f1 } ; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal1_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff83ff{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff83ff{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_f16(half addrspace(1)* %out) #3 { %canonicalized = call half @llvm.canonicalize.f16(half 0xH83FF) store half %canonicalized, half addrspace(1)* %out @@ -144,8 +180,8 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_f16(half a } ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7c00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7c00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_qnan_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 0xH7C00) store half %canonicalized, half addrspace(1)* %out @@ -153,8 +189,8 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_f16(half addrspace(1)* %o } ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg1_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half bitcast (i16 -1 to half)) store half %canonicalized, half addrspace(1)* %out @@ -162,8 +198,8 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_f16(half addrs } ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg2_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half bitcast (i16 -2 to half)) store half %canonicalized, half addrspace(1)* %out @@ -171,8 +207,8 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_f16(half addrs } ; GCN-LABEL: {{^}}test_fold_canonicalize_snan0_value_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_snan0_value_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 0xH7C01) store half %canonicalized, half addrspace(1)* %out @@ -180,8 +216,8 @@ define amdgpu_kernel void @test_fold_canonicalize_snan0_value_f16(half addrspace } ; GCN-LABEL: {{^}}test_fold_canonicalize_snan1_value_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_snan1_value_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 0xH7DFF) store half %canonicalized, half addrspace(1)* %out @@ -189,8 +225,8 @@ define amdgpu_kernel void @test_fold_canonicalize_snan1_value_f16(half addrspace } ; GCN-LABEL: {{^}}test_fold_canonicalize_snan2_value_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_snan2_value_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 0xHFDFF) store half %canonicalized, half addrspace(1)* %out @@ -198,8 +234,8 @@ define amdgpu_kernel void @test_fold_canonicalize_snan2_value_f16(half addrspace } ; GCN-LABEL: {{^}}test_fold_canonicalize_snan3_value_f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} -; GCN: buffer_store_short [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e00{{$}} +; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f16(half addrspace(1)* %out) #1 { %canonicalized = call half @llvm.canonicalize.f16(half 0xHFC01) store half %canonicalized, half addrspace(1)* %out @@ -212,7 +248,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f16(half addrspace ; VI-NOT: v_and_b32 ; GFX9: v_pk_max_f16 [[REG:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+$}} -; GFX9: buffer_store_dword [[REG]] +; GFX9: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @v_test_canonicalize_var_v2f16(<2 x half> addrspace(1)* %out) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid @@ -230,7 +266,7 @@ define amdgpu_kernel void @v_test_canonicalize_var_v2f16(<2 x half> addrspace(1) ; GFX9: v_and_b32_e32 [[ABS:v[0-9]+]], 0x7fff7fff, v{{[0-9]+}} ; GFX9: v_pk_max_f16 [[REG:v[0-9]+]], [[ABS]], [[ABS]]{{$}} -; GCN: buffer_store_dword +; GFX89: {{flat|global}}_store_dword define amdgpu_kernel void @v_test_canonicalize_fabs_var_v2f16(<2 x half> addrspace(1)* %out) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid @@ -248,7 +284,12 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_v2f16(<2 x half> addrspa ; GFX9: v_and_b32_e32 [[ABS:v[0-9]+]], 0x7fff7fff, v{{[0-9]+}} ; GFX9: v_pk_max_f16 [[REG:v[0-9]+]], [[ABS]], [[ABS]] neg_lo:[1,1] neg_hi:[1,1]{{$}} -; GCN: buffer_store_dword +; GFX89: {{flat|global}}_store_dword + +; CI: v_cvt_f32_f16 +; CI: v_cvt_f32_f16 +; CI: v_mul_f32_e32 v{{[0-9]+}}, 1.0 +; CI: v_mul_f32_e32 v{{[0-9]+}}, 1.0 define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_v2f16(<2 x half> addrspace(1)* %out) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid @@ -266,7 +307,7 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_v2f16(<2 x half> ad ; VI-NOT: 0xffff ; GFX9: v_pk_max_f16 [[REG:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} neg_lo:[1,1] neg_hi:[1,1]{{$}} -; GFX9: buffer_store_dword [[REG]] +; GFX9: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @v_test_canonicalize_fneg_var_v2f16(<2 x half> addrspace(1)* %out) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep = getelementptr <2 x half>, <2 x half> addrspace(1)* %out, i32 %tid @@ -283,7 +324,7 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_var_v2f16(<2 x half> addrspa ; VI-NOT: v_and_b32 ; GFX9: v_pk_max_f16 [[REG:v[0-9]+]], {{s[0-9]+}}, {{s[0-9]+$}} -; GFX9: buffer_store_dword [[REG]] +; GFX9: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @s_test_canonicalize_var_v2f16(<2 x half> addrspace(1)* %out, i32 zeroext %val.arg) #1 { %val = bitcast i32 %val.arg to <2 x half> %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %val) @@ -292,8 +333,8 @@ define amdgpu_kernel void @s_test_canonicalize_var_v2f16(<2 x half> addrspace(1) } ; GCN-LABEL: {{^}}test_fold_canonicalize_p0_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_p0_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> zeroinitializer) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -301,8 +342,8 @@ define amdgpu_kernel void @test_fold_canonicalize_p0_v2f16(<2 x half> addrspace( } ; GCN-LABEL: {{^}}test_fold_canonicalize_n0_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80008000{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80008000{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_n0_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half -0.0, half -0.0>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -310,8 +351,8 @@ define amdgpu_kernel void @test_fold_canonicalize_n0_v2f16(<2 x half> addrspace( } ; GCN-LABEL: {{^}}test_fold_canonicalize_p1_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3c003c00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3c003c00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_p1_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 1.0, half 1.0>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -319,8 +360,8 @@ define amdgpu_kernel void @test_fold_canonicalize_p1_v2f16(<2 x half> addrspace( } ; GCN-LABEL: {{^}}test_fold_canonicalize_n1_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbc00bc00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbc00bc00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_n1_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half -1.0, half -1.0>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -328,8 +369,8 @@ define amdgpu_kernel void @test_fold_canonicalize_n1_v2f16(<2 x half> addrspace( } ; GCN-LABEL: {{^}}test_fold_canonicalize_literal_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x4c004c00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x4c004c00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_literal_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 16.0, half 16.0>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -337,8 +378,8 @@ define amdgpu_kernel void @test_fold_canonicalize_literal_v2f16(<2 x half> addrs } ; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal0_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3ff03ff{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3ff03ff{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xH03FF, half 0xH03FF>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -346,8 +387,8 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal0_v2f16(< } ; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal0_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3ff03ff{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3ff03ff{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_v2f16(<2 x half> addrspace(1)* %out) #3 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xH03FF, half 0xH03FF>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -355,8 +396,8 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal0_v2f16(<2 x } ; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal1_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x83ff83ff{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x83ff83ff{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal1_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xH83FF, half 0xH83FF>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -364,8 +405,8 @@ define amdgpu_kernel void @test_no_denormals_fold_canonicalize_denormal1_v2f16(< } ; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal1_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x83ff83ff{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x83ff83ff{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_v2f16(<2 x half> addrspace(1)* %out) #3 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xH83FF, half 0xH83FF>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -373,8 +414,8 @@ define amdgpu_kernel void @test_denormals_fold_canonicalize_denormal1_v2f16(<2 x } ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7c007c00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7c007c00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_qnan_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xH7C00, half 0xH7C00>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -382,8 +423,8 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_v2f16(<2 x half> addrspac } ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg1_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> bitcast (i32 -1 to <2 x half>)) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -391,8 +432,8 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg1_v2f16(<2 x hal } ; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg2_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half bitcast (i16 -2 to half), half bitcast (i16 -2 to half)>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -400,8 +441,8 @@ define amdgpu_kernel void @test_fold_canonicalize_qnan_value_neg2_v2f16(<2 x hal } ; GCN-LABEL: {{^}}test_fold_canonicalize_snan0_value_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_snan0_value_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xH7C01, half 0xH7C01>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -409,8 +450,8 @@ define amdgpu_kernel void @test_fold_canonicalize_snan0_value_v2f16(<2 x half> a } ; GCN-LABEL: {{^}}test_fold_canonicalize_snan1_value_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_snan1_value_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xH7DFF, half 0xH7DFF>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -418,8 +459,8 @@ define amdgpu_kernel void @test_fold_canonicalize_snan1_value_v2f16(<2 x half> a } ; GCN-LABEL: {{^}}test_fold_canonicalize_snan2_value_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_snan2_value_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xHFDFF, half 0xHFDFF>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out @@ -427,8 +468,8 @@ define amdgpu_kernel void @test_fold_canonicalize_snan2_value_v2f16(<2 x half> a } ; GCN-LABEL: {{^}}test_fold_canonicalize_snan3_value_v2f16: -; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} -; GCN: buffer_store_dword [[REG]] +; GFX89: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7e007e00{{$}} +; GFX89: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REG]] define amdgpu_kernel void @test_fold_canonicalize_snan3_value_v2f16(<2 x half> addrspace(1)* %out) #1 { %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> <half 0xHFC01, half 0xHFC01>) store <2 x half> %canonicalized, <2 x half> addrspace(1)* %out diff --git a/test/CodeGen/AMDGPU/fcanonicalize.ll b/test/CodeGen/AMDGPU/fcanonicalize.ll index 1c6d176c6762..6b2d58db804e 100644 --- a/test/CodeGen/AMDGPU/fcanonicalize.ll +++ b/test/CodeGen/AMDGPU/fcanonicalize.ll @@ -40,7 +40,7 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_f32(float addrspace(1)* } ; GCN-LABEL: {{^}}v_test_canonicalize_fneg_fabs_var_f32: -; GCN: v_mul_f32_e64 [[REG:v[0-9]+]], 1.0, -|{{v[0-9]+}}| +; GCN: v_mul_f32_e64 [[REG:v[0-9]+]], -1.0, |{{v[0-9]+}}| ; GCN: buffer_store_dword [[REG]] define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_f32(float addrspace(1)* %out) #1 { %val = load float, float addrspace(1)* %out @@ -52,7 +52,7 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_f32(float addrspace } ; GCN-LABEL: {{^}}v_test_canonicalize_fneg_var_f32: -; GCN: v_mul_f32_e64 [[REG:v[0-9]+]], 1.0, -{{v[0-9]+}} +; GCN: v_mul_f32_e32 [[REG:v[0-9]+]], -1.0, {{v[0-9]+}} ; GCN: buffer_store_dword [[REG]] define amdgpu_kernel void @v_test_canonicalize_fneg_var_f32(float addrspace(1)* %out) #1 { %val = load float, float addrspace(1)* %out @@ -62,6 +62,15 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_var_f32(float addrspace(1)* ret void } +; GCN-LABEL: {{^}}test_fold_canonicalize_undef_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}} +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @test_fold_canonicalize_undef_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float undef) + store float %canonicalized, float addrspace(1)* %out + ret void +} + ; GCN-LABEL: {{^}}test_fold_canonicalize_p0_f32: ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} ; GCN: buffer_store_dword [[REG]] diff --git a/test/CodeGen/AMDGPU/fmax3.ll b/test/CodeGen/AMDGPU/fmax3.ll index 39455acad484..1f67ace72df7 100644 --- a/test/CodeGen/AMDGPU/fmax3.ll +++ b/test/CodeGen/AMDGPU/fmax3.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; GCN-LABEL: {{^}}test_fmax3_olt_0_f32: ; GCN: buffer_load_dword [[REGC:v[0-9]+]] @@ -38,20 +38,23 @@ define amdgpu_kernel void @test_fmax3_olt_1_f32(float addrspace(1)* %out, float } ; GCN-LABEL: {{^}}test_fmax3_olt_0_f16: -; GCN: buffer_load_ushort [[REGC:v[0-9]+]] -; GCN: buffer_load_ushort [[REGB:v[0-9]+]] ; GCN: buffer_load_ushort [[REGA:v[0-9]+]] +; GCN: buffer_load_ushort [[REGB:v[0-9]+]] +; GCN: buffer_load_ushort [[REGC:v[0-9]+]] -; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]], -; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]] +; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_A]], [[CVT_B]], [[CVT_C]] +; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]] ; VI: v_max_f16_e32 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], -; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], [[REGC]] ; GCN: buffer_store_short [[RESULT]], define amdgpu_kernel void @test_fmax3_olt_0_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 { - %a = load volatile half, half addrspace(1)* %aptr, align 2 + %a = load volatile half, half addrspace(1)* %aptr, align 2 %b = load volatile half, half addrspace(1)* %bptr, align 2 %c = load volatile half, half addrspace(1)* %cptr, align 2 %f0 = call half @llvm.maxnum.f16(half %a, half %b) @@ -62,17 +65,20 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(half addrspace(1)* %out, half ad ; Commute operand of second fmax ; GCN-LABEL: {{^}}test_fmax3_olt_1_f16: -; GCN: buffer_load_ushort [[REGB:v[0-9]+]] ; GCN: buffer_load_ushort [[REGA:v[0-9]+]] +; GCN: buffer_load_ushort [[REGB:v[0-9]+]] ; GCN: buffer_load_ushort [[REGC:v[0-9]+]] -; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]], -; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]] +; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_C]], [[CVT_A]], [[CVT_B]] +; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]] ; VI: v_max_f16_e32 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], -; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]] ; GCN: buffer_store_short [[RESULT]], define amdgpu_kernel void @test_fmax3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 { %a = load volatile half, half addrspace(1)* %aptr, align 2 diff --git a/test/CodeGen/AMDGPU/fmaxnum.ll b/test/CodeGen/AMDGPU/fmaxnum.ll index 277b8ce04c4e..58b5b5282b09 100644 --- a/test/CodeGen/AMDGPU/fmaxnum.ll +++ b/test/CodeGen/AMDGPU/fmaxnum.ll @@ -1,283 +1,214 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -declare float @llvm.maxnum.f32(float, float) #0 -declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #0 -declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #0 -declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #0 -declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #0 - -declare double @llvm.maxnum.f64(double, double) - -; FUNC-LABEL: @test_fmax_f32 -; SI: v_max_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MAX_DX10 {{.*}}[[OUT]] -define amdgpu_kernel void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) nounwind { - %val = call float @llvm.maxnum.f32(float %a, float %b) #0 +; GCN-LABEL: {{^}}test_fmax_f32: +; GCN: v_max_f32_e32 +define amdgpu_kernel void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) #0 { + %val = call float @llvm.maxnum.f32(float %a, float %b) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @test_fmax_v2f32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] -; EG: MAX_DX10 {{.*}}[[OUT]] -; EG: MAX_DX10 {{.*}}[[OUT]] -define amdgpu_kernel void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind { - %val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b) #0 +; GCN-LABEL: {{^}}test_fmax_v2f32: +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +define amdgpu_kernel void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 { + %val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b) store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: @test_fmax_v4f32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 +; GCN-LABEL: {{^}}test_fmax_v3f32: +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN-NOT: v_max_f32 +define amdgpu_kernel void @test_fmax_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, <3 x float> %b) nounwind { + %val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b) #0 + store <3 x float> %val, <3 x float> addrspace(1)* %out, align 16 + ret void +} -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] -; EG: MAX_DX10 {{.*}}[[OUT]] -; EG: MAX_DX10 {{.*}}[[OUT]] -; EG: MAX_DX10 {{.*}}[[OUT]] -; EG: MAX_DX10 {{.*}}[[OUT]] -define amdgpu_kernel void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind { - %val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) #0 +; GCN-LABEL: {{^}}test_fmax_v4f32: +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +define amdgpu_kernel void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) #0 { + %val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16 ret void } -; FUNC-LABEL: @test_fmax_v8f32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] -; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X -; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y -; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z -; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W -; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X -; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y -; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z -; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W -define amdgpu_kernel void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind { - %val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b) #0 +; GCN-LABEL: {{^}}test_fmax_v8f32: +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +define amdgpu_kernel void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) #0 { + %val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b) store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32 ret void } -; FUNC-LABEL: @test_fmax_v16f32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 -; SI: v_max_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]] -; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X -; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y -; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z -; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W -; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X -; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y -; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z -; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W -; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].X -; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Y -; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Z -; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].W -; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].X -; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Y -; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Z -; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].W -define amdgpu_kernel void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind { - %val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) #0 +; GCN-LABEL: {{^}}test_fmax_v16f32: +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +define amdgpu_kernel void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) #0 { + %val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64 ret void } -; FUNC-LABEL: @constant_fold_fmax_f32 -; SI-NOT: v_max_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmax_f32(float addrspace(1)* %out) nounwind { - %val = call float @llvm.maxnum.f32(float 1.0, float 2.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmax_f32: +; GCN-NOT: v_max_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmax_f32(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 1.0, float 2.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmax_f32_nan_nan -; SI-NOT: v_max_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -; EG: 2143289344(nan) -define amdgpu_kernel void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) nounwind { - %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0 +; GCN-LABEL: {{^}}constant_fold_fmax_f32_nan_nan: +; GCN-NOT: v_max_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmax_f32_val_nan -; SI-NOT: v_max_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) nounwind { - %val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000) #0 +; GCN-LABEL: {{^}}constant_fold_fmax_f32_val_nan: +; GCN-NOT: v_max_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmax_f32_nan_val -; SI-NOT: v_max_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) nounwind { - %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmax_f32_nan_val: +; GCN-NOT: v_max_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmax_f32_p0_p0 -; SI-NOT: v_max_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) nounwind { - %val = call float @llvm.maxnum.f32(float 0.0, float 0.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmax_f32_p0_p0: +; GCN-NOT: v_max_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 0.0, float 0.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmax_f32_p0_n0 -; SI-NOT: v_max_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind { - %val = call float @llvm.maxnum.f32(float 0.0, float -0.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmax_f32_p0_n0: +; GCN-NOT: v_max_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 0.0, float -0.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmax_f32_n0_p0 -; SI-NOT: v_max_f32_e32 -; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind { - %val = call float @llvm.maxnum.f32(float -0.0, float 0.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmax_f32_n0_p0: +; GCN-NOT: v_max_f32_e32 +; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float -0.0, float 0.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmax_f32_n0_n0 -; SI-NOT: v_max_f32_e32 -; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) nounwind { - %val = call float @llvm.maxnum.f32(float -0.0, float -0.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmax_f32_n0_n0: +; GCN-NOT: v_max_f32_e32 +; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float -0.0, float -0.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @fmax_var_immediate_f32 -; SI: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MAX_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind { - %val = call float @llvm.maxnum.f32(float %a, float 2.0) #0 +; GCN-LABEL: {{^}}fmax_var_immediate_f32: +; GCN: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0 +define amdgpu_kernel void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.maxnum.f32(float %a, float 2.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @fmax_immediate_var_f32 -; SI: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} -define amdgpu_kernel void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind { - %val = call float @llvm.maxnum.f32(float 2.0, float %a) #0 +; GCN-LABEL: {{^}}fmax_immediate_var_f32: +; GCN: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0 +define amdgpu_kernel void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.maxnum.f32(float 2.0, float %a) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @fmax_var_literal_f32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 -; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} -define amdgpu_kernel void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) nounwind { - %val = call float @llvm.maxnum.f32(float %a, float 99.0) #0 +; GCN-LABEL: {{^}}fmax_var_literal_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 +; GCN: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] +define amdgpu_kernel void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.maxnum.f32(float %a, float 99.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @fmax_literal_var_f32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 -; SI: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} -define amdgpu_kernel void @fmax_literal_var_f32(float addrspace(1)* %out, float %a) nounwind { - %val = call float @llvm.maxnum.f32(float 99.0, float %a) #0 +; GCN-LABEL: {{^}}fmax_literal_var_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 +; GCN: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] +define amdgpu_kernel void @fmax_literal_var_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.maxnum.f32(float 99.0, float %a) store float %val, float addrspace(1)* %out, align 4 ret void } -attributes #0 = { nounwind readnone } +; GCN-LABEL: {{^}}test_func_fmax_v3f32: +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN: v_max_f32_e32 +; GCN-NOT: v_max_f32 +define <3 x float> @test_func_fmax_v3f32(<3 x float> %a, <3 x float> %b) nounwind { + %val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b) #0 + ret <3 x float> %val +} + +declare float @llvm.maxnum.f32(float, float) #1 +declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #1 +declare <3 x float> @llvm.maxnum.v3f32(<3 x float>, <3 x float>) #1 +declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 +declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #1 +declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #1 +declare double @llvm.maxnum.f64(double, double) + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/fmaxnum.r600.ll b/test/CodeGen/AMDGPU/fmaxnum.r600.ll new file mode 100644 index 000000000000..71bb4afa64ef --- /dev/null +++ b/test/CodeGen/AMDGPU/fmaxnum.r600.ll @@ -0,0 +1,203 @@ +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s + +; EG-LABEL: {{^}}test_fmax_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MAX_DX10 {{.*}}[[OUT]] +define amdgpu_kernel void @test_fmax_f32(float addrspace(1)* %out, float %a, float %b) #0 { + %val = call float @llvm.maxnum.f32(float %a, float %b) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}test_fmax_v2f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] +; EG: MAX_DX10 {{.*}}[[OUT]] +; EG: MAX_DX10 {{.*}}[[OUT]] +define amdgpu_kernel void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 { + %val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b) + store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8 + ret void +} + +; EG-LABEL: {{^}}test_fmax_v4f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] +; EG: MAX_DX10 {{.*}}[[OUT]] +; EG: MAX_DX10 {{.*}}[[OUT]] +; EG: MAX_DX10 {{.*}}[[OUT]] +; EG: MAX_DX10 {{.*}}[[OUT]] +define amdgpu_kernel void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) #0 { + %val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) + store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16 + ret void +} + +; EG-LABEL: {{^}}test_fmax_v8f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] +; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X +; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y +; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z +; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W +; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X +; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y +; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z +; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W +define amdgpu_kernel void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) #0 { + %val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b) + store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32 + ret void +} + +; EG-LABEL: {{^}}test_fmax_v16f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]] +; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].X +; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Y +; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].Z +; EG-DAG: MAX_DX10 {{.*}}[[OUT1]].W +; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].X +; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Y +; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].Z +; EG-DAG: MAX_DX10 {{.*}}[[OUT2]].W +; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].X +; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Y +; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].Z +; EG-DAG: MAX_DX10 {{.*}}[[OUT3]].W +; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].X +; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Y +; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].Z +; EG-DAG: MAX_DX10 {{.*}}[[OUT4]].W +define amdgpu_kernel void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) #0 { + %val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b) + store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmax_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MAX_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmax_f32(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 1.0, float 2.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmax_f32_nan_nan: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MAX_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +; EG: 2143289344(nan) +define amdgpu_kernel void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmax_f32_val_nan: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MAX_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmax_f32_nan_val: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MAX_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmax_f32_p0_p0: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MAX_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 0.0, float 0.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmax_f32_p0_n0: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MAX_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float 0.0, float -0.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmax_f32_n0_p0: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MAX_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float -0.0, float 0.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmax_f32_n0_n0: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MAX_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) #0 { + %val = call float @llvm.maxnum.f32(float -0.0, float -0.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}fmax_var_immediate_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MAX_DX10 * [[OUT]] +define amdgpu_kernel void @fmax_var_immediate_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.maxnum.f32(float %a, float 2.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}fmax_immediate_var_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} +define amdgpu_kernel void @fmax_immediate_var_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.maxnum.f32(float 2.0, float %a) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}fmax_var_literal_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} +define amdgpu_kernel void @fmax_var_literal_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.maxnum.f32(float %a, float 99.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}fmax_literal_var_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MAX_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} +define amdgpu_kernel void @fmax_literal_var_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.maxnum.f32(float 99.0, float %a) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +declare float @llvm.maxnum.f32(float, float) #1 +declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #1 +declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 +declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #1 +declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #1 +declare double @llvm.maxnum.f64(double, double) + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/fmin3.ll b/test/CodeGen/AMDGPU/fmin3.ll index 06befaa64b5c..fa93fbcfb917 100644 --- a/test/CodeGen/AMDGPU/fmin3.ll +++ b/test/CodeGen/AMDGPU/fmin3.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; GCN-LABEL: {{^}}test_fmin3_olt_0_f32: ; GCN: buffer_load_dword [[REGC:v[0-9]+]] @@ -60,17 +60,20 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(half addrspace(1)* %out, half ad ; Commute operand of second fmin ; GCN-LABEL: {{^}}test_fmin3_olt_1_f16: -; GCN: buffer_load_ushort [[REGB:v[0-9]+]] ; GCN: buffer_load_ushort [[REGA:v[0-9]+]] +; GCN: buffer_load_ushort [[REGB:v[0-9]+]] ; GCN: buffer_load_ushort [[REGC:v[0-9]+]] -; SI: v_min3_f32 [[RESULT_F32:v[0-9]+]], -; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]] +; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]] +; SI: v_min3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_C]], [[CVT_A]], [[CVT_B]] +; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]] ; VI: v_min_f16_e32 ; VI: v_min_f16_e32 [[RESULT:v[0-9]+]], -; GFX9: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GFX9: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]] ; GCN: buffer_store_short [[RESULT]], define amdgpu_kernel void @test_fmin3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 { %a = load volatile half, half addrspace(1)* %aptr, align 2 diff --git a/test/CodeGen/AMDGPU/fminnum.ll b/test/CodeGen/AMDGPU/fminnum.ll index 9e997c7a1045..a0642e211f13 100644 --- a/test/CodeGen/AMDGPU/fminnum.ll +++ b/test/CodeGen/AMDGPU/fminnum.ll @@ -1,281 +1,202 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s -declare float @llvm.minnum.f32(float, float) #0 -declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0 -declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #0 -declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #0 -declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #0 - -; FUNC-LABEL: @test_fmin_f32 -; SI: v_min_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MIN_DX10 {{.*}}[[OUT]] -define amdgpu_kernel void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwind { - %val = call float @llvm.minnum.f32(float %a, float %b) #0 +; GCN-LABEL: {{^}}test_fmin_f32: +; GCN: v_min_f32_e32 +define amdgpu_kernel void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) #0 { + %val = call float @llvm.minnum.f32(float %a, float %b) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @test_fmin_v2f32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] -; EG: MIN_DX10 {{.*}}[[OUT]] -; EG: MIN_DX10 {{.*}}[[OUT]] -define amdgpu_kernel void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind { - %val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b) #0 +; GCN-LABEL: {{^}}test_fmin_v2f32: +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +define amdgpu_kernel void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 { + %val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b) store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: @test_fmin_v4f32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] -; EG: MIN_DX10 {{.*}}[[OUT]] -; EG: MIN_DX10 {{.*}}[[OUT]] -; EG: MIN_DX10 {{.*}}[[OUT]] -; EG: MIN_DX10 {{.*}}[[OUT]] -define amdgpu_kernel void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind { - %val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) #0 +; GCN-LABEL: {{^}}test_fmin_v4f32: +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +define amdgpu_kernel void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) #0 { + %val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16 ret void } -; FUNC-LABEL: @test_fmin_v8f32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] -; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X -; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y -; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z -; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W -; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X -; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y -; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z -; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W -define amdgpu_kernel void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind { - %val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b) #0 +; GCN-LABEL: {{^}}test_fmin_v8f32: +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +define amdgpu_kernel void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) #0 { + %val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b) store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32 ret void } -; FUNC-LABEL: @test_fmin_v16f32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 -; SI: v_min_f32_e32 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]] -; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X -; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y -; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z -; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W -; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X -; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y -; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z -; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W -; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].X -; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Y -; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Z -; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].W -; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].X -; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Y -; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Z -; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].W -define amdgpu_kernel void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind { - %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) #0 +; GCN-LABEL: {{^}}test_fmin_v16f32: +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +define amdgpu_kernel void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) #0 { + %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64 ret void } -; FUNC-LABEL: @constant_fold_fmin_f32 -; SI-NOT: v_min_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MIN_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind { - %val = call float @llvm.minnum.f32(float 1.0, float 2.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmin_f32: +; GCN-NOT: v_min_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmin_f32(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 1.0, float 2.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmin_f32_nan_nan -; SI-NOT: v_min_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MIN_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -; EG: 2143289344({{nan|1\.#QNAN0e\+00}}) -define amdgpu_kernel void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind { - %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0 +; GCN-LABEL: {{^}}constant_fold_fmin_f32_nan_nan: +; GCN-NOT: v_min_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmin_f32_val_nan -; SI-NOT: v_min_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MIN_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind { - %val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000) #0 +; GCN-LABEL: {{^}}constant_fold_fmin_f32_val_nan: +; GCN-NOT: v_min_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmin_f32_nan_val -; SI-NOT: v_min_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MIN_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind { - %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmin_f32_nan_val: +; GCN-NOT: v_min_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmin_f32_p0_p0 -; SI-NOT: v_min_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MIN_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind { - %val = call float @llvm.minnum.f32(float 0.0, float 0.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmin_f32_p0_p0: +; GCN-NOT: v_min_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 0.0, float 0.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmin_f32_p0_n0 -; SI-NOT: v_min_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MIN_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind { - %val = call float @llvm.minnum.f32(float 0.0, float -0.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmin_f32_p0_n0: +; GCN-NOT: v_min_f32_e32 +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0 +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 0.0, float -0.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmin_f32_n0_p0 -; SI-NOT: v_min_f32_e32 -; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MIN_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind { - %val = call float @llvm.minnum.f32(float -0.0, float 0.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmin_f32_n0_p0: +; GCN-NOT: v_min_f32_e32 +; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float -0.0, float 0.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @constant_fold_fmin_f32_n0_n0 -; SI-NOT: v_min_f32_e32 -; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} -; SI: buffer_store_dword [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG-NOT: MIN_DX10 -; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} -define amdgpu_kernel void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind { - %val = call float @llvm.minnum.f32(float -0.0, float -0.0) #0 +; GCN-LABEL: {{^}}constant_fold_fmin_f32_n0_n0: +; GCN-NOT: v_min_f32_e32 +; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} +; GCN: buffer_store_dword [[REG]] +define amdgpu_kernel void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float -0.0, float -0.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @fmin_var_immediate_f32 -; SI: v_min_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} -define amdgpu_kernel void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind { - %val = call float @llvm.minnum.f32(float %a, float 2.0) #0 +; GCN-LABEL: {{^}}fmin_var_immediate_f32: +; GCN: v_min_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0 +define amdgpu_kernel void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.minnum.f32(float %a, float 2.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @fmin_immediate_var_f32 -; SI: v_min_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0 - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} -define amdgpu_kernel void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind { - %val = call float @llvm.minnum.f32(float 2.0, float %a) #0 +; GCN-LABEL: {{^}}fmin_immediate_var_f32: +; GCN: v_min_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0 +define amdgpu_kernel void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.minnum.f32(float 2.0, float %a) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @fmin_var_literal_f32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 -; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} -define amdgpu_kernel void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind { - %val = call float @llvm.minnum.f32(float %a, float 99.0) #0 +; GCN-LABEL: {{^}}fmin_var_literal_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 +; GCN: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] +define amdgpu_kernel void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.minnum.f32(float %a, float 99.0) store float %val, float addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: @fmin_literal_var_f32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 -; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] - -; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] -; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} -define amdgpu_kernel void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) nounwind { - %val = call float @llvm.minnum.f32(float 99.0, float %a) #0 +; GCN-LABEL: {{^}}fmin_literal_var_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 +; GCN: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] +define amdgpu_kernel void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.minnum.f32(float 99.0, float %a) store float %val, float addrspace(1)* %out, align 4 ret void } -attributes #0 = { nounwind readnone } +; GCN-LABEL: {{^}}test_func_fmin_v3f32: +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN: v_min_f32_e32 +; GCN-NOT: v_min_f32 +define <3 x float> @test_func_fmin_v3f32(<3 x float> %a, <3 x float> %b) nounwind { + %val = call <3 x float> @llvm.minnum.v3f32(<3 x float> %a, <3 x float> %b) #0 + ret <3 x float> %val +} + +declare float @llvm.minnum.f32(float, float) #1 +declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #1 +declare <3 x float> @llvm.minnum.v3f32(<3 x float>, <3 x float>) #1 +declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 +declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #1 +declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/fminnum.r600.ll b/test/CodeGen/AMDGPU/fminnum.r600.ll new file mode 100644 index 000000000000..713e95c7f46e --- /dev/null +++ b/test/CodeGen/AMDGPU/fminnum.r600.ll @@ -0,0 +1,202 @@ +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s + +; EG-LABEL: {{^}}test_fmin_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MIN_DX10 {{.*}}[[OUT]] +define amdgpu_kernel void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) #0 { + %val = call float @llvm.minnum.f32(float %a, float %b) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}test_fmin_v2f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] +; EG: MIN_DX10 {{.*}}[[OUT]] +; EG: MIN_DX10 {{.*}}[[OUT]] +define amdgpu_kernel void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 { + %val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b) + store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8 + ret void +} + +; EG-LABEL: {{^}}test_fmin_v4f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] +; EG: MIN_DX10 {{.*}}[[OUT]] +; EG: MIN_DX10 {{.*}}[[OUT]] +; EG: MIN_DX10 {{.*}}[[OUT]] +; EG: MIN_DX10 {{.*}}[[OUT]] +define amdgpu_kernel void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) #0 { + %val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) + store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16 + ret void +} + +; EG-LABEL: {{^}}test_fmin_v8f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] +; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X +; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y +; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z +; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W +; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X +; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y +; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z +; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W +define amdgpu_kernel void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) #0 { + %val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b) + store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32 + ret void +} + +; EG-LABEL: {{^}}test_fmin_v16f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]] +; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X +; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y +; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z +; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W +; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X +; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y +; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z +; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W +; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].X +; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Y +; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Z +; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].W +; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].X +; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Y +; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Z +; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].W +define amdgpu_kernel void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) #0 { + %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) + store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmin_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MIN_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmin_f32(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 1.0, float 2.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmin_f32_nan_nan: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MIN_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +; EG: 2143289344({{nan|1\.#QNAN0e\+00}}) +define amdgpu_kernel void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmin_f32_val_nan: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MIN_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmin_f32_nan_val: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MIN_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmin_f32_p0_p0: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MIN_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 0.0, float 0.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmin_f32_p0_n0: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MIN_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float 0.0, float -0.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmin_f32_n0_p0: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MIN_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float -0.0, float 0.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}constant_fold_fmin_f32_n0_n0: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG-NOT: MIN_DX10 +; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} +define amdgpu_kernel void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) #0 { + %val = call float @llvm.minnum.f32(float -0.0, float -0.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}fmin_var_immediate_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} +define amdgpu_kernel void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.minnum.f32(float %a, float 2.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}fmin_immediate_var_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} +define amdgpu_kernel void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.minnum.f32(float 2.0, float %a) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}fmin_var_literal_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} +define amdgpu_kernel void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.minnum.f32(float %a, float 99.0) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}fmin_literal_var_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] +; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} +define amdgpu_kernel void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.minnum.f32(float 99.0, float %a) + store float %val, float addrspace(1)* %out, align 4 + ret void +} + +declare float @llvm.minnum.f32(float, float) #1 +declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #1 +declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 +declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #1 +declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll b/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll index 4d08651dcb4c..e14d4019c184 100644 --- a/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll +++ b/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll @@ -1,6 +1,6 @@ -; XUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-DENORM %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=VI-FLUSH %s +; XUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,VI-DENORM %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,VI-FLUSH %s ; Make sure (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c)) doesn't diff --git a/test/CodeGen/AMDGPU/fneg-combines.ll b/test/CodeGen/AMDGPU/fneg-combines.ll index fd3d4f053e95..c065227012f6 100644 --- a/test/CodeGen/AMDGPU/fneg-combines.ll +++ b/test/CodeGen/AMDGPU/fneg-combines.ll @@ -1725,6 +1725,26 @@ define amdgpu_kernel void @v_fneg_nearbyint_f32(float addrspace(1)* %out, float } ; -------------------------------------------------------------------------------- +; fcanonicalize tests +; -------------------------------------------------------------------------------- + +; GCN-LABEL: {{^}}v_fneg_canonicalize_f32: +; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] +; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], -1.0, [[A]] +; GCN: buffer_store_dword [[RESULT]] +define amdgpu_kernel void @v_fneg_canonicalize_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext + %a = load volatile float, float addrspace(1)* %a.gep + %trunc = call float @llvm.canonicalize.f32(float %a) + %fneg = fsub float -0.0, %trunc + store float %fneg, float addrspace(1)* %out.gep + ret void +} + +; -------------------------------------------------------------------------------- ; vintrp tests ; -------------------------------------------------------------------------------- @@ -2117,6 +2137,7 @@ declare float @llvm.trunc.f32(float) #1 declare float @llvm.round.f32(float) #1 declare float @llvm.rint.f32(float) #1 declare float @llvm.nearbyint.f32(float) #1 +declare float @llvm.canonicalize.f32(float) #1 declare float @llvm.minnum.f32(float, float) #1 declare float @llvm.maxnum.f32(float, float) #1 diff --git a/test/CodeGen/AMDGPU/function-args.ll b/test/CodeGen/AMDGPU/function-args.ll index 48d94465c131..71541b295537 100644 --- a/test/CodeGen/AMDGPU/function-args.ll +++ b/test/CodeGen/AMDGPU/function-args.ll @@ -739,6 +739,45 @@ define void @void_func_v32i32_v16i32_v16f32(<32 x i32> %arg0, <16 x i32> %arg1, ret void } +; Make sure v3 isn't a wasted register because of v3 types being promoted to v4 +; GCN-LABEL: {{^}}void_func_v3f32_wasted_reg: +; GCN: s_waitcnt +; GCN: ds_write_b32 v{{[0-9]+}}, v0 +; GCN-NEXT: ds_write_b32 v{{[0-9]+}}, v1 +; GCN-NEXT: ds_write_b32 v{{[0-9]+}}, v2 +; GCN-NEXT: ds_write_b32 v{{[0-9]+}}, v3 +; GCN-NEXT: s_waitcnt +; GCN-NEXT: s_setpc_b64 +define void @void_func_v3f32_wasted_reg(<3 x float> %arg0, i32 %arg1) #0 { + %arg0.0 = extractelement <3 x float> %arg0, i32 0 + %arg0.1 = extractelement <3 x float> %arg0, i32 1 + %arg0.2 = extractelement <3 x float> %arg0, i32 2 + store volatile float %arg0.0, float addrspace(3)* undef + store volatile float %arg0.1, float addrspace(3)* undef + store volatile float %arg0.2, float addrspace(3)* undef + store volatile i32 %arg1, i32 addrspace(3)* undef + ret void +} + +; GCN-LABEL: {{^}}void_func_v3i32_wasted_reg: +; GCN: s_waitcnt +; GCN: ds_write_b32 v{{[0-9]+}}, v0 +; GCN-NEXT: ds_write_b32 v{{[0-9]+}}, v1 +; GCN-NEXT: ds_write_b32 v{{[0-9]+}}, v2 +; GCN-NEXT: ds_write_b32 v{{[0-9]+}}, v3 +; GCN-NEXT: s_waitcnt +; GCN-NEXT: s_setpc_b64 +define void @void_func_v3i32_wasted_reg(<3 x i32> %arg0, i32 %arg1) #0 { + %arg0.0 = extractelement <3 x i32> %arg0, i32 0 + %arg0.1 = extractelement <3 x i32> %arg0, i32 1 + %arg0.2 = extractelement <3 x i32> %arg0, i32 2 + store volatile i32 %arg0.0, i32 addrspace(3)* undef + store volatile i32 %arg0.1, i32 addrspace(3)* undef + store volatile i32 %arg0.2, i32 addrspace(3)* undef + store volatile i32 %arg1, i32 addrspace(3)* undef + ret void +} + ; Check there is no crash. ; GCN-LABEL: {{^}}void_func_v16i8: define void @void_func_v16i8(<16 x i8> %arg0) #0 { diff --git a/test/CodeGen/AMDGPU/function-returns.ll b/test/CodeGen/AMDGPU/function-returns.ll index 32ecc417feda..20208b188d78 100644 --- a/test/CodeGen/AMDGPU/function-returns.ll +++ b/test/CodeGen/AMDGPU/function-returns.ll @@ -531,4 +531,43 @@ define { i32, <32 x i32> } @struct_i32_v32i32_func_void() #0 { ret { i32, <32 x i32> }%val } +; Make sure the last struct component is returned in v3, not v4. +; GCN-LABEL: {{^}}v3i32_struct_func_void_wasted_reg: +; GCN: ds_read_b32 v0, +; GCN: ds_read_b32 v1, +; GCN: ds_read_b32 v2, +; GCN: ds_read_b32 v3, +define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 { + %load0 = load volatile i32, i32 addrspace(3)* undef + %load1 = load volatile i32, i32 addrspace(3)* undef + %load2 = load volatile i32, i32 addrspace(3)* undef + %load3 = load volatile i32, i32 addrspace(3)* undef + + %insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0 + %insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1 + %insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2 + %insert.3 = insertvalue { <3 x i32>, i32 } undef, <3 x i32> %insert.2, 0 + %insert.4 = insertvalue { <3 x i32>, i32 } %insert.3, i32 %load3, 1 + ret { <3 x i32>, i32 } %insert.4 +} + +; GCN-LABEL: {{^}}v3f32_struct_func_void_wasted_reg: +; GCN: ds_read_b32 v0, +; GCN: ds_read_b32 v1, +; GCN: ds_read_b32 v2, +; GCN: ds_read_b32 v3, +define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 { + %load0 = load volatile float, float addrspace(3)* undef + %load1 = load volatile float, float addrspace(3)* undef + %load2 = load volatile float, float addrspace(3)* undef + %load3 = load volatile i32, i32 addrspace(3)* undef + + %insert.0 = insertelement <3 x float> undef, float %load0, i32 0 + %insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1 + %insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2 + %insert.3 = insertvalue { <3 x float>, i32 } undef, <3 x float> %insert.2, 0 + %insert.4 = insertvalue { <3 x float>, i32 } %insert.3, i32 %load3, 1 + ret { <3 x float>, i32 } %insert.4 +} + attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/kernel-args.ll b/test/CodeGen/AMDGPU/kernel-args.ll index 9492b710d13e..9d1f582f4a88 100644 --- a/test/CodeGen/AMDGPU/kernel-args.ll +++ b/test/CodeGen/AMDGPU/kernel-args.ll @@ -1,19 +1,28 @@ ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=SI,GCN,MESA-GCN,FUNC %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s -; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefix=EG --check-prefix=FUNC %s -; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=EG --check-prefix=FUNC %s +; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=EG,EGCM,FUNC %s +; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=CM,EGCM,FUNC %s ; FUNC-LABEL: {{^}}i8_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z + ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c ; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff + + +; EG: LSHR T0.X, KC0[2].Y, literal.x, +; EG-NEXT: MOV * T1.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) + +; CM: LSHR * T0.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T1.X, KC0[2].Z, define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { %ext = zext i8 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -23,12 +32,21 @@ define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) noun ; FUNC-LABEL: {{^}}i8_zext_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff + + +; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) + +; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { %ext = zext i8 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -38,7 +56,6 @@ define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zero ; FUNC-LABEL: {{^}}i8_sext_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c @@ -46,6 +63,16 @@ define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zero ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_sext_i32_i8 s{{[0-9]+}}, [[VAL]] ; HSA-VI: flat_store_dword + + +; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) + +; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind { %ext = sext i8 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -56,7 +83,6 @@ define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 sign ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c @@ -65,6 +91,15 @@ define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 sign ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} ; HSA-VI: flat_store_dword + + +; EG: LSHR T0.X, KC0[2].Y, literal.x, +; EG-NEXT: MOV * T1.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) + +; CM: LSHR * T0.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T1.X, KC0[2].Z, define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { %ext = zext i16 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -75,13 +110,21 @@ define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) no ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} ; HSA-VI: flat_store_dword + +; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) + +; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { %ext = zext i16 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -92,7 +135,6 @@ define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 ze ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c @@ -100,6 +142,15 @@ define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 ze ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_sext_i32_i16 s{{[0-9]+}}, [[VAL]] ; HSA-VI: flat_store_dword + +; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) + +; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind { %ext = sext i16 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -110,7 +161,7 @@ define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 si ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z +; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c ; HSA-VI: s_load_dword s{{[0-9]}}, s[4:5], 0x8 @@ -123,7 +174,7 @@ entry: ; FUNC-LABEL: {{^}}f32_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z +; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c ; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 @@ -137,8 +188,8 @@ entry: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_8 -; EG: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 ; GCN: s_load_dword s ; GCN-NOT: {{buffer|flat|global}}_load_ @@ -152,8 +203,8 @@ entry: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_16 -; EG: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 ; SI: s_load_dword s{{[0-9]+}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c @@ -168,8 +219,8 @@ entry: ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb ; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c ; HSA-VI: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8 @@ -183,8 +234,8 @@ entry: ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb ; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c ; HSA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[4:5], 0x8 @@ -198,9 +249,9 @@ entry: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40 -; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41 -; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42 +; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40 +; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41 +; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42 ; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb @@ -216,9 +267,9 @@ entry: ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44 -; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46 -; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48 +; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44 +; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46 +; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48 ; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb @@ -233,9 +284,9 @@ entry: ; FUNC-LABEL: {{^}}v3i32_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 @@ -248,9 +299,9 @@ entry: ; FUNC-LABEL: {{^}}v3f32_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 @@ -263,10 +314,10 @@ entry: ; FUNC-LABEL: {{^}}v4i8_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 ; GCN-DAG: s_load_dwordx2 s ; GCN-DAG: s_load_dword s @@ -279,10 +330,10 @@ entry: ; FUNC-LABEL: {{^}}v4i16_arg: ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 ; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0xb ; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x9 @@ -305,10 +356,10 @@ entry: ; FUNC-LABEL: {{^}}v4i32_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34 @@ -322,10 +373,10 @@ entry: ; FUNC-LABEL: {{^}}v4f32_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 @@ -339,14 +390,14 @@ entry: ; FUNC-LABEL: {{^}}v8i8_arg: ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 ; SI-NOT: {{buffer|flat|global}}_load ; SI: s_load_dwordx2 s @@ -367,14 +418,14 @@ entry: ; FUNC-LABEL: {{^}}v8i16_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 ; SI: s_load_dwordx4 ; SI-NEXT: s_load_dwordx2 @@ -393,14 +444,14 @@ entry: ; FUNC-LABEL: {{^}}v8i32_arg: ; HSA-VI: kernarg_segment_byte_size = 64 ; HSA-VI: kernarg_segment_alignment = 5 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11 ; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44 @@ -414,14 +465,14 @@ entry: ; FUNC-LABEL: {{^}}v8f32_arg: ; HSA-VI: kernarg_segment_byte_size = 64 ; HSA-VI: kernarg_segment_alignment = 5 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11 define amdgpu_kernel void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind { entry: @@ -434,22 +485,22 @@ entry: ; FUNC-LABEL: {{^}}v16i8_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 ; SI: s_load_dwordx4 s ; SI-NEXT: s_load_dwordx2 s @@ -470,23 +521,23 @@ entry: ; FUNC-LABEL: {{^}}v16i16_arg: ; HSA-VI: kernarg_segment_byte_size = 64 ; HSA-VI: kernarg_segment_alignment = 5 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 - -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 + +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 ; SI: s_load_dwordx8 s ; SI-NEXT: s_load_dwordx2 s @@ -505,22 +556,22 @@ entry: ; FUNC-LABEL: {{^}}v16i32_arg: ; HSA-VI: kernarg_segment_byte_size = 128 ; HSA-VI: kernarg_segment_alignment = 6 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X ; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19 ; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64 ; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 @@ -533,22 +584,22 @@ entry: ; FUNC-LABEL: {{^}}v16f32_arg: ; HSA-VI: kernarg_segment_byte_size = 128 ; HSA-VI: kernarg_segment_alignment = 6 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X ; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19 ; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64 ; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll index 6d2de108829d..cdfe9b460a01 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll @@ -480,5 +480,65 @@ define amdgpu_kernel void @test_export_vm_i32() #0 { ret void } +; GCN-LABEL: {{^}}test_if_export_f32: +; GCN: s_cbranch_execz +; GCN: exp +define amdgpu_ps void @test_if_export_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 { + %cc = icmp eq i32 %flag, 0 + br i1 %cc, label %end, label %exp + +exp: + call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 false, i1 false) + br label %end + +end: + ret void +} + +; GCN-LABEL: {{^}}test_if_export_vm_f32: +; GCN: s_cbranch_execz +; GCN: exp +define amdgpu_ps void @test_if_export_vm_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 { + %cc = icmp eq i32 %flag, 0 + br i1 %cc, label %end, label %exp + +exp: + call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 false, i1 true) + br label %end + +end: + ret void +} + +; GCN-LABEL: {{^}}test_if_export_done_f32: +; GCN: s_cbranch_execz +; GCN: exp +define amdgpu_ps void @test_if_export_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 { + %cc = icmp eq i32 %flag, 0 + br i1 %cc, label %end, label %exp + +exp: + call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 false) + br label %end + +end: + ret void +} + +; GCN-LABEL: {{^}}test_if_export_vm_done_f32: +; GCN: s_cbranch_execz +; GCN: exp +define amdgpu_ps void @test_if_export_vm_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 { + %cc = icmp eq i32 %flag, 0 + br i1 %cc, label %end, label %exp + +exp: + call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true) + br label %end + +end: + ret void +} + attributes #0 = { nounwind } attributes #1 = { nounwind inaccessiblememonly } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll index 65ab3e04237b..7efb1850a277 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX906 -declare float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c) +declare float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 %clamp) -; GFX906-LABEL: {{^}}test_llvm_amdgcn_fdot2 -; GFX906: v_dot2_f32_f16 -define amdgpu_kernel void @test_llvm_amdgcn_fdot2( +; GFX906-LABEL: {{^}}test_llvm_amdgcn_fdot2_clamp +; GFX906: v_dot2_f32_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_fdot2_clamp( float addrspace(1)* %r, <2 x half> addrspace(1)* %a, <2 x half> addrspace(1)* %b, @@ -13,7 +13,23 @@ entry: %a.val = load <2 x half>, <2 x half> addrspace(1)* %a %b.val = load <2 x half>, <2 x half> addrspace(1)* %b %c.val = load float, float addrspace(1)* %c - %r.val = call float @llvm.amdgcn.fdot2(<2 x half> %a.val, <2 x half> %b.val, float %c.val) + %r.val = call float @llvm.amdgcn.fdot2(<2 x half> %a.val, <2 x half> %b.val, float %c.val, i1 1) + store float %r.val, float addrspace(1)* %r + ret void +} + +; GFX906-LABEL: {{^}}test_llvm_amdgcn_fdot2_no_clamp +; GFX906: v_dot2_f32_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_fdot2_no_clamp( + float addrspace(1)* %r, + <2 x half> addrspace(1)* %a, + <2 x half> addrspace(1)* %b, + float addrspace(1)* %c) { +entry: + %a.val = load <2 x half>, <2 x half> addrspace(1)* %a + %b.val = load <2 x half>, <2 x half> addrspace(1)* %b + %c.val = load float, float addrspace(1)* %c + %r.val = call float @llvm.amdgcn.fdot2(<2 x half> %a.val, <2 x half> %b.val, float %c.val, i1 0) store float %r.val, float addrspace(1)* %r ret void } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.ltolz.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.ltolz.ll new file mode 100644 index 000000000000..2d66a0be0690 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.ltolz.ll @@ -0,0 +1,113 @@ +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s + + +; GCN-LABEL: {{^}}sample_l_1d: +; GCN: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32(i32 15, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}sample_l_2d: +; GCN: image_sample_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %s, float %t, float -0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}sample_c_l_1d: +; GCN: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32(i32 15, float %zcompare, float %s, float -2.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}sample_c_l_2d: +; GCN: image_sample_c_lz v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}sample_l_o_1d: +; GCN: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @sample_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}sample_l_o_2d: +; GCN: image_sample_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @sample_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}sample_c_l_o_1d: +; GCN: image_sample_c_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @sample_c_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}sample_c_l_o_2d: +; GCN: image_sample_c_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @sample_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}gather4_l_2d: +; GCN: image_gather4_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 15, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}gather4_c_l_2d: +; GCN: image_gather4_c_lz v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}gather4_l_o_2d: +; GCN: image_gather4_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @gather4_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}gather4_c_l_o_2d: +; GCN: image_gather4_c_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf{{$}} +define amdgpu_ps <4 x float> @gather4_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) { +main_body: + %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0) + ret <4 x float> %v +} + +declare <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 + +declare <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 +declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll index 0d8f28bbef16..f1894cc14cc3 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot2.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX906 -declare i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c) +declare i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp) -; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2 -; GFX906: v_dot2_i32_i16 -define amdgpu_kernel void @test_llvm_amdgcn_sdot2( +; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2_clamp +; GFX906: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_sdot2_clamp( i32 addrspace(1)* %r, <2 x i16> addrspace(1)* %a, <2 x i16> addrspace(1)* %b, @@ -13,7 +13,23 @@ entry: %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b %c.val = load i32, i32 addrspace(1)* %c - %r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val) + %r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1) + store i32 %r.val, i32 addrspace(1)* %r + ret void +} + +; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2_no_clamp +; GFX906: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_sdot2_no_clamp( + i32 addrspace(1)* %r, + <2 x i16> addrspace(1)* %a, + <2 x i16> addrspace(1)* %b, + i32 addrspace(1)* %c) { +entry: + %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a + %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b + %c.val = load i32, i32 addrspace(1)* %c + %r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0) store i32 %r.val, i32 addrspace(1)* %r ret void } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll index 8b664e6f9a4c..2651200a344e 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX906 -declare i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c) +declare i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 %clamp) -; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4 -; GFX906: v_dot4_i32_i8 -define amdgpu_kernel void @test_llvm_amdgcn_sdot4( +; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_clamp +; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_sdot4_clamp( i32 addrspace(1)* %r, <4 x i8> addrspace(1)* %a, <4 x i8> addrspace(1)* %b, @@ -15,7 +15,25 @@ entry: %a.val.cast = bitcast <4 x i8> %a.val to i32 %b.val.cast = bitcast <4 x i8> %b.val to i32 %c.val = load i32, i32 addrspace(1)* %c - %r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val) + %r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1) + store i32 %r.val, i32 addrspace(1)* %r + ret void +} + +; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_no_clamp +; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_sdot4_no_clamp( + i32 addrspace(1)* %r, + <4 x i8> addrspace(1)* %a, + <4 x i8> addrspace(1)* %b, + i32 addrspace(1)* %c) { +entry: + %a.val = load <4 x i8>, <4 x i8> addrspace(1)* %a + %b.val = load <4 x i8>, <4 x i8> addrspace(1)* %b + %a.val.cast = bitcast <4 x i8> %a.val to i32 + %b.val.cast = bitcast <4 x i8> %b.val to i32 + %c.val = load i32, i32 addrspace(1)* %c + %r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0) store i32 %r.val, i32 addrspace(1)* %r ret void } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll index e2466eae5394..456421c4984a 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX906 -declare i32 @llvm.amdgcn.sdot8(i32 %a, i32 %b, i32 %c) +declare i32 @llvm.amdgcn.sdot8(i32 %a, i32 %b, i32 %c, i1 %clamp) -; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot8 -; GFX906: v_dot8_i32_i4 -define amdgpu_kernel void @test_llvm_amdgcn_sdot8( +; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot8_clamp +; GFX906: v_dot8_i32_i4 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_sdot8_clamp( i32 addrspace(1)* %r, <8 x i4> addrspace(1)* %a, <8 x i4> addrspace(1)* %b, @@ -15,7 +15,25 @@ entry: %a.val.cast = bitcast <8 x i4> %a.val to i32 %b.val.cast = bitcast <8 x i4> %b.val to i32 %c.val = load i32, i32 addrspace(1)* %c - %r.val = call i32 @llvm.amdgcn.sdot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val) + %r.val = call i32 @llvm.amdgcn.sdot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1) + store i32 %r.val, i32 addrspace(1)* %r + ret void +} + +; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot8_no_clamp +; GFX906: v_dot8_i32_i4 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_sdot8_no_clamp( + i32 addrspace(1)* %r, + <8 x i4> addrspace(1)* %a, + <8 x i4> addrspace(1)* %b, + i32 addrspace(1)* %c) { +entry: + %a.val = load <8 x i4>, <8 x i4> addrspace(1)* %a + %b.val = load <8 x i4>, <8 x i4> addrspace(1)* %b + %a.val.cast = bitcast <8 x i4> %a.val to i32 + %b.val.cast = bitcast <8 x i4> %b.val to i32 + %c.val = load i32, i32 addrspace(1)* %c + %r.val = call i32 @llvm.amdgcn.sdot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0) store i32 %r.val, i32 addrspace(1)* %r ret void } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll index 594f76048790..4f8cd6f682e6 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll @@ -136,6 +136,21 @@ body: ret void } +; GCN-LABEL: {{^}}if_sendmsg: +; GCN: s_cbranch_execz +; GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) +define amdgpu_gs void @if_sendmsg(i32 %flag) #0 { + %cc = icmp eq i32 %flag, 0 + br i1 %cc, label %sendmsg, label %end + +sendmsg: + call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) + br label %end + +end: + ret void +} + declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0 declare void @llvm.amdgcn.s.sendmsghalt(i32, i32) #0 diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll index b2912cb23343..18ca71d33bcc 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX906 -declare i32 @llvm.amdgcn.udot2(<2 x i16> %a, <2 x i16> %b, i32 %c) +declare i32 @llvm.amdgcn.udot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp) -; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2 -; GFX906: v_dot2_u32_u16 -define amdgpu_kernel void @test_llvm_amdgcn_udot2( +; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_clamp +; GFX906: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_udot2_clamp( i32 addrspace(1)* %r, <2 x i16> addrspace(1)* %a, <2 x i16> addrspace(1)* %b, @@ -13,7 +13,23 @@ entry: %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b %c.val = load i32, i32 addrspace(1)* %c - %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val) + %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1) + store i32 %r.val, i32 addrspace(1)* %r + ret void +} + +; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_no_clamp +; GFX906: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_udot2_no_clamp( + i32 addrspace(1)* %r, + <2 x i16> addrspace(1)* %a, + <2 x i16> addrspace(1)* %b, + i32 addrspace(1)* %c) { +entry: + %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a + %b.val = load <2 x i16>, <2 x i16> addrspace(1)* %b + %c.val = load i32, i32 addrspace(1)* %c + %r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0) store i32 %r.val, i32 addrspace(1)* %r ret void } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll index 5ce060de7003..73d6a9ce968b 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.udot4.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX906 -declare i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c) +declare i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 %clamp) -; GCN-LABEL: {{^}}test_llvm_amdgcn_udot4 -; GFX906: v_dot4_u32_u8 -define amdgpu_kernel void @test_llvm_amdgcn_udot4( +; GCN-LABEL: {{^}}test_llvm_amdgcn_udot4_clamp +; GFX906: v_dot4_u32_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_udot4_clamp( i32 addrspace(1)* %r, <4 x i8> addrspace(1)* %a, <4 x i8> addrspace(1)* %b, @@ -15,7 +15,25 @@ entry: %a.val.cast = bitcast <4 x i8> %a.val to i32 %b.val.cast = bitcast <4 x i8> %b.val to i32 %c.val = load i32, i32 addrspace(1)* %c - %r.val = call i32 @llvm.amdgcn.udot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val) + %r.val = call i32 @llvm.amdgcn.udot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1) + store i32 %r.val, i32 addrspace(1)* %r + ret void +} + +; GCN-LABEL: {{^}}test_llvm_amdgcn_udot4_no_clamp +; GFX906: v_dot4_u32_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_udot4_no_clamp( + i32 addrspace(1)* %r, + <4 x i8> addrspace(1)* %a, + <4 x i8> addrspace(1)* %b, + i32 addrspace(1)* %c) { +entry: + %a.val = load <4 x i8>, <4 x i8> addrspace(1)* %a + %b.val = load <4 x i8>, <4 x i8> addrspace(1)* %b + %a.val.cast = bitcast <4 x i8> %a.val to i32 + %b.val.cast = bitcast <4 x i8> %b.val to i32 + %c.val = load i32, i32 addrspace(1)* %c + %r.val = call i32 @llvm.amdgcn.udot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0) store i32 %r.val, i32 addrspace(1)* %r ret void } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll index 2599305bc8e0..c2f80cac8f7f 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.udot8.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX906 -declare i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c) +declare i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 %clamp) -; GCN-LABEL: {{^}}test_llvm_amdgcn_udot8 -; GFX906: v_dot8_u32_u4 -define amdgpu_kernel void @test_llvm_amdgcn_udot8( +; GCN-LABEL: {{^}}test_llvm_amdgcn_udot8_clamp +; GFX906: v_dot8_u32_u4 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_udot8_clamp( i32 addrspace(1)* %r, <8 x i4> addrspace(1)* %a, <8 x i4> addrspace(1)* %b, @@ -15,7 +15,25 @@ entry: %a.val.cast = bitcast <8 x i4> %a.val to i32 %b.val.cast = bitcast <8 x i4> %b.val to i32 %c.val = load i32, i32 addrspace(1)* %c - %r.val = call i32 @llvm.amdgcn.udot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val) + %r.val = call i32 @llvm.amdgcn.udot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1) + store i32 %r.val, i32 addrspace(1)* %r + ret void +} + +; GCN-LABEL: {{^}}test_llvm_amdgcn_udot8_no_clamp +; GFX906: v_dot8_u32_u4 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_udot8_no_clamp( + i32 addrspace(1)* %r, + <8 x i4> addrspace(1)* %a, + <8 x i4> addrspace(1)* %b, + i32 addrspace(1)* %c) { +entry: + %a.val = load <8 x i4>, <8 x i4> addrspace(1)* %a + %b.val = load <8 x i4>, <8 x i4> addrspace(1)* %b + %a.val.cast = bitcast <8 x i4> %a.val to i32 + %b.val.cast = bitcast <8 x i4> %b.val to i32 + %c.val = load i32, i32 addrspace(1)* %c + %r.val = call i32 @llvm.amdgcn.udot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0) store i32 %r.val, i32 addrspace(1)* %r ret void } diff --git a/test/CodeGen/AMDGPU/lower-kernargs.ll b/test/CodeGen/AMDGPU/lower-kernargs.ll index fb903cfd8e97..630aa4a96bfb 100644 --- a/test/CodeGen/AMDGPU/lower-kernargs.ll +++ b/test/CodeGen/AMDGPU/lower-kernargs.ll @@ -98,7 +98,7 @@ define amdgpu_kernel void @kern_zeroext_i8(i8 zeroext %arg) #0 { ; MESA-NEXT: [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)* -; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !1, !invariant.load !0 +; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0 ; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 ; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1 ; MESA-NEXT: ret void @@ -121,7 +121,7 @@ define amdgpu_kernel void @kern_zeroext_i16(i16 zeroext %arg) #0 { ; MESA-NEXT: [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)* -; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !2, !invariant.load !0 +; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0 ; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16 ; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1 ; MESA-NEXT: ret void @@ -144,7 +144,7 @@ define amdgpu_kernel void @kern_signext_i8(i8 signext %arg) #0 { ; MESA-NEXT: [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)* -; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !3, !invariant.load !0 +; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0 ; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 ; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1 ; MESA-NEXT: ret void @@ -167,7 +167,7 @@ define amdgpu_kernel void @kern_signext_i16(i16 signext %arg) #0 { ; MESA-NEXT: [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)* -; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !4, !invariant.load !0 +; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0 ; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16 ; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1 ; MESA-NEXT: ret void @@ -1160,7 +1160,7 @@ define amdgpu_kernel void @kern_global_ptr_dereferencable(i8 addrspace(1)* deref ; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)* -; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable !5 +; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable !1 ; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef ; MESA-NEXT: ret void ; @@ -1181,7 +1181,7 @@ define amdgpu_kernel void @kern_global_ptr_dereferencable_or_null(i8 addrspace(1 ; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)* -; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable_or_null !6 +; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable_or_null !2 ; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef ; MESA-NEXT: ret void ; @@ -1223,7 +1223,7 @@ define amdgpu_kernel void @kern_align32_global_ptr(i8 addrspace(1)* align 1024 % ; MESA-NEXT: [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)* -; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !align !7 +; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !align !3 ; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef ; MESA-NEXT: ret void ; @@ -1432,17 +1432,7 @@ attributes #0 = { nounwind "target-cpu"="kaveri" } attributes #1 = { nounwind "target-cpu"="kaveri" "amdgpu-implicitarg-num-bytes"="40" } attributes #2 = { nounwind "target-cpu"="tahiti" } -; HSA: 0 = !{} -; HSA: !1 = !{i64 42} -; HSA: !2 = !{i64 128} -; HSA: !3 = !{i64 1024} - - -; MESA: !0 = !{} -; MESA: !1 = !{i32 0, i32 256} -; MESA: !2 = !{i32 0, i32 65536} -; MESA: !3 = !{i32 -128, i32 128} -; MESA: !4 = !{i32 -32768, i32 32768} -; MESA: !5 = !{i64 42} -; MESA: !6 = !{i64 128} -; MESA: !7 = !{i64 1024} +; GCN: 0 = !{} +; GCN: !1 = !{i64 42} +; GCN: !2 = !{i64 128} +; GCN: !3 = !{i64 1024} diff --git a/test/CodeGen/AMDGPU/mad-mix-lo.ll b/test/CodeGen/AMDGPU/mad-mix-lo.ll index 848e8830a1a4..ed7b67f7e6a2 100644 --- a/test/CodeGen/AMDGPU/mad-mix-lo.ll +++ b/test/CodeGen/AMDGPU/mad-mix-lo.ll @@ -112,12 +112,12 @@ define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half ; GCN-LABEL: {{^}}v_mad_mix_v4f32: ; GCN: s_waitcnt -; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] -; GFX9-NEXT: v_mad_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1] -; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] -; GFX9-NEXT: v_mad_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] -; GFX9-NEXT: v_mov_b32_e32 v0, v6 -; GFX9-NEXT: v_mov_b32_e32 v1, v7 +; GFX9-NEXT: v_mad_mixlo_f16 v6, v1, v3, v5 op_sel_hi:[1,1,1] +; GFX9-NEXT: v_mad_mixlo_f16 v7, v0, v2, v4 op_sel_hi:[1,1,1] +; GFX9-NEXT: v_mad_mixhi_f16 v7, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] +; GFX9-NEXT: v_mad_mixhi_f16 v6, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] +; GFX9-NEXT: v_mov_b32_e32 v0, v7 +; GFX9-NEXT: v_mov_b32_e32 v1, v6 ; GFX9-NEXT: s_setpc_b64 define <4 x half> @v_mad_mix_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half> %src2) #0 { %src0.ext = fpext <4 x half> %src0 to <4 x float> @@ -169,11 +169,11 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s ; GCN-LABEL: {{^}}v_mad_mix_v4f32_clamp_postcvt: ; GCN: s_waitcnt ; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp -; GFX9-NEXT: v_mad_mixlo_f16 v7, v1, v3, v5 op_sel_hi:[1,1,1] clamp ; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp -; GFX9-NEXT: v_mad_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp +; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp +; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp ; GFX9-NEXT: v_mov_b32_e32 v0, v6 -; GFX9-NEXT: v_mov_b32_e32 v1, v7 +; GFX9-NEXT: v_mov_b32_e32 v1, v2 ; GFX9-NEXT: s_setpc_b64 define <4 x half> @v_mad_mix_v4f32_clamp_postcvt(<4 x half> %src0, <4 x half> %src1, <4 x half> %src2) #0 { %src0.ext = fpext <4 x half> %src0 to <4 x float> @@ -267,10 +267,11 @@ define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %sr } ; GCN-LABEL: {{^}}v_mad_mix_v4f32_clamp_precvt: -; GFX9: v_mad_mix_f32 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp -; GFX9: v_mad_mix_f32 v0, v0, v2, v4 op_sel_hi:[1,1,1] clamp -; GFX9: v_mad_mix_f32 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp +; GFX9: v_mad_mix_f32 v6, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp ; GFX9: v_mad_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp +; GFX9: v_mad_mix_f32 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp +; GFX9: v_mad_mix_f32 v0, v0, v2, v4 op_sel_hi:[1,1,1] clamp + ; GFX9: v_cvt_f16_f32 ; GFX9: v_cvt_f16_f32 ; GFX9: v_cvt_f16_f32 diff --git a/test/CodeGen/AMDGPU/mad-mix.ll b/test/CodeGen/AMDGPU/mad-mix.ll index 6f56be1a8a23..b68a43ecb8c0 100644 --- a/test/CodeGen/AMDGPU/mad-mix.ll +++ b/test/CodeGen/AMDGPU/mad-mix.ll @@ -54,13 +54,13 @@ define float @v_mad_mix_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> % } ; GCN-LABEL: {{^}}v_mad_mix_v2f32: -; GFX900: v_mov_b32_e32 v3, v1 -; GFX900-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] -; GFX900-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel_hi:[1,1,1] +; GFX900: v_mad_mix_f32 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] +; GFX900-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] +; GFX900-NEXT: v_mov_b32_e32 v1, v3 -; GFX906: v_mov_b32_e32 v3, v1 -; GFX906-NEXT: v_fma_mix_f32 v1, v0, v3, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] -; GFX906-NEXT: v_fma_mix_f32 v0, v0, v3, v2 op_sel_hi:[1,1,1] +; GFX906: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] +; GFX906-NEXT: v_mov_b32_e32 v1, v3 ; CIVI: v_mac_f32 define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 { @@ -73,14 +73,14 @@ define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x hal ; GCN-LABEL: {{^}}v_mad_mix_v2f32_shuffle: ; GCN: s_waitcnt -; GFX900-NEXT: v_mov_b32_e32 v3, v1 -; GFX900-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1] -; GFX900-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX900: v_mad_mix_f32 v3, v0, v1, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX900-NEXT: v_mad_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1] +; GFX900-NEXT: v_mov_b32_e32 v0, v3 ; GFX900-NEXT: s_setpc_b64 -; GFX906-NEXT: v_mov_b32_e32 v3, v1 -; GFX906-NEXT: v_fma_mix_f32 v1, v0, v3, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1] -; GFX906-NEXT: v_fma_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: v_fma_mix_f32 v3, v0, v1, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: v_mov_b32_e32 v0, v3 ; GFX906-NEXT: s_setpc_b64 ; CIVI: v_mac_f32 @@ -274,13 +274,14 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imm63(half %src0, half %src1) #0 { } ; GCN-LABEL: {{^}}v_mad_mix_v2f32_f32imm1: -; GFX9: v_mov_b32_e32 v2, v1 ; GFX9: v_mov_b32_e32 v3, 1.0 -; GFX900: v_mad_mix_f32 v1, v0, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding -; GFX900: v_mad_mix_f32 v0, v0, v2, v3 op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mad_mix_f32 v2, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mad_mix_f32 v0, v0, v1, v3 op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mov_b32_e32 v1, v2 -; GFX906: v_fma_mix_f32 v1, v0, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding -; GFX906: v_fma_mix_f32 v0, v0, v2, v3 op_sel_hi:[1,1,0] ; encoding +; GFX906: v_fma_mix_f32 v2, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding +; GFX906: v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[1,1,0] ; encoding +; GFX906: v_mov_b32_e32 v1, v2 define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1) #0 { %src0.ext = fpext <2 x half> %src0 to <2 x float> %src1.ext = fpext <2 x half> %src1 to <2 x float> @@ -289,13 +290,15 @@ define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1) } ; GCN-LABEL: {{^}}v_mad_mix_v2f32_cvtf16imminv2pi: -; GFX9: v_mov_b32_e32 v2, v1 ; GFX9: v_mov_b32_e32 v3, 0x3e230000 -; GFX900: v_mad_mix_f32 v1, v0, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding -; GFX900: v_mad_mix_f32 v0, v0, v2, v3 op_sel_hi:[1,1,0] ; encoding -; GFX906: v_fma_mix_f32 v1, v0, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding -; GFX906: v_fma_mix_f32 v0, v0, v2, v3 op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mad_mix_f32 v2, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mad_mix_f32 v0, v0, v1, v3 op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mov_b32_e32 v1, v2 + +; GFX906: v_fma_mix_f32 v2, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding +; GFX906: v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[1,1,0] ; encoding +; GFX906: v_mov_b32_e32 v1, v2 define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half> %src1) #0 { %src0.ext = fpext <2 x half> %src0 to <2 x float> %src1.ext = fpext <2 x half> %src1 to <2 x float> @@ -305,14 +308,15 @@ define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half> } ; GCN-LABEL: {{^}}v_mad_mix_v2f32_f32imminv2pi: -; GFX9: v_mov_b32_e32 v2, v1 ; GFX9: v_mov_b32_e32 v3, 0.15915494 -; GFX900: v_mad_mix_f32 v1, v0, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding -; GFX900: v_mad_mix_f32 v0, v0, v2, v3 op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mad_mix_f32 v2, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mad_mix_f32 v0, v0, v1, v3 op_sel_hi:[1,1,0] ; encoding +; GFX900: v_mov_b32_e32 v1, v2 -; GFX906: v_fma_mix_f32 v1, v0, v2, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding -; GFX906: v_fma_mix_f32 v0, v0, v2, v3 op_sel_hi:[1,1,0] ; encoding +; GFX906: v_fma_mix_f32 v2, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0] ; encoding +; GFX906: v_fma_mix_f32 v0, v0, v1, v3 op_sel_hi:[1,1,0] ; encoding +; GFX906: v_mov_b32_e32 v1, v2 define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %src1) #0 { %src0.ext = fpext <2 x half> %src0 to <2 x float> %src1.ext = fpext <2 x half> %src1 to <2 x float> diff --git a/test/CodeGen/AMDGPU/mul.i16.ll b/test/CodeGen/AMDGPU/mul.i16.ll index 678fc3d1daf3..d8274105b823 100644 --- a/test/CodeGen/AMDGPU/mul.i16.ll +++ b/test/CodeGen/AMDGPU/mul.i16.ll @@ -90,8 +90,8 @@ define <3 x i16> @v_mul_v3i16(<3 x i16> %a, <3 x i16> %b) { ; VI: v_or_b32_e32 ; GFX9: s_waitcnt -; GFX9-NEXT: v_pk_mul_lo_u16 v1, v1, v3 ; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v2 +; GFX9-NEXT: v_pk_mul_lo_u16 v1, v1, v3 ; GFX9-NEXT: s_setpc_b64 define <4 x i16> @v_mul_v4i16(<4 x i16> %a, <4 x i16> %b) { %r.val = mul <4 x i16> %a, %b diff --git a/test/CodeGen/AMDGPU/r600.extract-lowbits.ll b/test/CodeGen/AMDGPU/r600.extract-lowbits.ll index bd02008096f0..71af6a9a4f51 100644 --- a/test/CodeGen/AMDGPU/r600.extract-lowbits.ll +++ b/test/CodeGen/AMDGPU/r600.extract-lowbits.ll @@ -1,5 +1,6 @@ -; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=EG %s -; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=CM %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s +; RUN: llc -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM %s ; Loosely based on test/CodeGen/{X86,AArch64}/extract-lowbits.ll, ; but with all 64-bit tests, and tests with loads dropped. @@ -15,11 +16,28 @@ ; Pattern a. 32-bit ; ---------------------------------------------------------------------------- ; -; R600-LABEL: bzhi32_a0: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_a0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_a0: +; EG: ; %bb.0: +; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, +; +; CM-LABEL: bzhi32_a0: +; CM: ; %bb.0: +; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, %onebit = shl i32 1, %numlowbits %mask = add nsw i32 %onebit, -1 %masked = and i32 %mask, %val @@ -27,11 +45,44 @@ define amdgpu_kernel void @bzhi32_a0(i32 %val, i32 %numlowbits, i32 addrspace(1) ret void } -; R600-LABEL: bzhi32_a1_indexzext: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_a1_indexzext: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, 0.0, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_UINT T0.X, KC0[2].Y, 0.0, PV.W, +; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: bzhi32_a1_indexzext: +; CM: ; %bb.0: +; CM-NEXT: ALU 0, @8, KC0[], KC1[] +; CM-NEXT: TEX 0 @6 +; CM-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3 +; CM-NEXT: ALU clause starting at 8: +; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: ALU clause starting at 9: +; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T0.X, KC0[2].Y, 0.0, PV.W, +; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) %conv = zext i8 %numlowbits to i32 %onebit = shl i32 1, %conv %mask = add nsw i32 %onebit, -1 @@ -40,11 +91,28 @@ define amdgpu_kernel void @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits, ret void } -; R600-LABEL: bzhi32_a4_commutative: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_a4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_a4_commutative: +; EG: ; %bb.0: +; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, +; +; CM-LABEL: bzhi32_a4_commutative: +; CM: ; %bb.0: +; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, %onebit = shl i32 1, %numlowbits %mask = add nsw i32 %onebit, -1 %masked = and i32 %val, %mask ; swapped order @@ -56,11 +124,28 @@ define amdgpu_kernel void @bzhi32_a4_commutative(i32 %val, i32 %numlowbits, i32 ; Pattern b. 32-bit ; ---------------------------------------------------------------------------- ; -; R600-LABEL: bzhi32_b0: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_b0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_b0: +; EG: ; %bb.0: +; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, +; +; CM-LABEL: bzhi32_b0: +; CM: ; %bb.0: +; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, %notmask = shl i32 -1, %numlowbits %mask = xor i32 %notmask, -1 %masked = and i32 %mask, %val @@ -68,11 +153,44 @@ define amdgpu_kernel void @bzhi32_b0(i32 %val, i32 %numlowbits, i32 addrspace(1) ret void } -; R600-LABEL: bzhi32_b1_indexzext: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_b1_indexzext: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, 0.0, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, +; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; EG-NEXT: BFE_UINT T0.X, KC0[2].Y, 0.0, PV.W, +; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: bzhi32_b1_indexzext: +; CM: ; %bb.0: +; CM-NEXT: ALU 0, @8, KC0[], KC1[] +; CM-NEXT: TEX 0 @6 +; CM-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3 +; CM-NEXT: ALU clause starting at 8: +; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: ALU clause starting at 9: +; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T0.X, KC0[2].Y, 0.0, PV.W, +; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) %conv = zext i8 %numlowbits to i32 %notmask = shl i32 -1, %conv %mask = xor i32 %notmask, -1 @@ -81,11 +199,28 @@ define amdgpu_kernel void @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits, ret void } -; R600-LABEL: bzhi32_b4_commutative: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_b4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_b4_commutative: +; EG: ; %bb.0: +; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, +; +; CM-LABEL: bzhi32_b4_commutative: +; CM: ; %bb.0: +; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, %notmask = shl i32 -1, %numlowbits %mask = xor i32 %notmask, -1 %masked = and i32 %val, %mask ; swapped order @@ -97,11 +232,28 @@ define amdgpu_kernel void @bzhi32_b4_commutative(i32 %val, i32 %numlowbits, i32 ; Pattern c. 32-bit ; ---------------------------------------------------------------------------- ; -; R600-LABEL: bzhi32_c0: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_c0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_c0: +; EG: ; %bb.0: +; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, +; +; CM-LABEL: bzhi32_c0: +; CM: ; %bb.0: +; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, %numhighbits = sub i32 32, %numlowbits %mask = lshr i32 -1, %numhighbits %masked = and i32 %mask, %val @@ -109,17 +261,52 @@ define amdgpu_kernel void @bzhi32_c0(i32 %val, i32 %numlowbits, i32 addrspace(1) ret void } -; R600-LABEL: bzhi32_c1_indexzext: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: SUB_INT {{\*?}} [[SUBR:T[0-9]+]].[[SUBC:[XYZW]]], literal.x, KC0[2].Z -; R600-NEXT: 32 -; R600-NEXT: AND_INT {{\*?}} {{T[0-9]+}}.[[AND1C:[XYZW]]], {{T[0-9]+|PV}}.[[SUBC]], literal.x -; R600-NEXT: 255 -; R600: LSHR {{\*?}} {{T[0-9]}}.[[LSHRC:[XYZW]]], literal.x, {{T[0-9]+|PV}}.[[AND1C]] -; R600-NEXT: -1 -; R600-NEXT: AND_INT {{[* ]*}}[[RET]], {{T[0-9]+|PV}}.[[LSHRC]], KC0[2].Y define amdgpu_kernel void @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_c1_indexzext: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, 0.0, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X, +; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; EG-NEXT: LSHR * T0.W, literal.x, PV.W, +; EG-NEXT: -1(nan), 0(0.000000e+00) +; EG-NEXT: AND_INT T0.X, PV.W, KC0[2].Y, +; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: bzhi32_c1_indexzext: +; CM: ; %bb.0: +; CM-NEXT: ALU 0, @8, KC0[], KC1[] +; CM-NEXT: TEX 0 @6 +; CM-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3 +; CM-NEXT: ALU clause starting at 8: +; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: ALU clause starting at 9: +; CM-NEXT: SUB_INT * T0.W, literal.x, T0.X, +; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT * T0.W, PV.W, literal.x, +; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; CM-NEXT: LSHR * T0.W, literal.x, PV.W, +; CM-NEXT: -1(nan), 0(0.000000e+00) +; CM-NEXT: AND_INT * T0.X, PV.W, KC0[2].Y, +; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) %numhighbits = sub i8 32, %numlowbits %sh_prom = zext i8 %numhighbits to i32 %mask = lshr i32 -1, %sh_prom @@ -128,11 +315,28 @@ define amdgpu_kernel void @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits, i32 add ret void } -; R600-LABEL: bzhi32_c4_commutative: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_c4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_c4_commutative: +; EG: ; %bb.0: +; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, +; +; CM-LABEL: bzhi32_c4_commutative: +; CM: ; %bb.0: +; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, %numhighbits = sub i32 32, %numlowbits %mask = lshr i32 -1, %numhighbits %masked = and i32 %val, %mask ; swapped order @@ -144,11 +348,28 @@ define amdgpu_kernel void @bzhi32_c4_commutative(i32 %val, i32 %numlowbits, i32 ; Pattern d. 32-bit. ; ---------------------------------------------------------------------------- ; -; R600-LABEL: bzhi32_d0: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z define amdgpu_kernel void @bzhi32_d0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_d0: +; EG: ; %bb.0: +; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: ALU clause starting at 4: +; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, +; +; CM-LABEL: bzhi32_d0: +; CM: ; %bb.0: +; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: ALU clause starting at 4: +; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z, %numhighbits = sub i32 32, %numlowbits %highbitscleared = shl i32 %val, %numhighbits %masked = lshr i32 %highbitscleared, %numhighbits @@ -156,16 +377,50 @@ define amdgpu_kernel void @bzhi32_d0(i32 %val, i32 %numlowbits, i32 addrspace(1) ret void } -; R600-LABEL: bzhi32_d1_indexzext: -; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]] -; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]] -; R600: SUB_INT {{\*?}} [[SUBR:T[0-9]+]].[[SUBC:[XYZW]]], literal.x, KC0[2].Z -; R600-NEXT: 32 -; R600-NEXT: AND_INT {{\*?}} [[AND:T[0-9]+\.[XYZW]]], {{T[0-9]+|PV}}.[[SUBC]], literal.x -; R600-NEXT: 255 -; R600: LSHL {{\*?}} {{T[0-9]}}.[[LSHLC:[XYZW]]], KC0[2].Y, {{T[0-9]+|PV}}.[[AND1C]] -; R600: LSHR {{[* ]*}}[[RET]], {{T[0-9]+|PV}}.[[LSHLC]], [[AND]] define amdgpu_kernel void @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) { +; EG-LABEL: bzhi32_d1_indexzext: +; EG: ; %bb.0: +; EG-NEXT: ALU 0, @8, KC0[], KC1[] +; EG-NEXT: TEX 0 @6 +; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[] +; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG-NEXT: CF_END +; EG-NEXT: PAD +; EG-NEXT: Fetch clause starting at 6: +; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3 +; EG-NEXT: ALU clause starting at 8: +; EG-NEXT: MOV * T0.X, 0.0, +; EG-NEXT: ALU clause starting at 9: +; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X, +; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; EG-NEXT: AND_INT * T0.W, PV.W, literal.x, +; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; EG-NEXT: LSHL * T1.W, KC0[2].Y, PV.W, +; EG-NEXT: LSHR T0.X, PV.W, T0.W, +; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; +; CM-LABEL: bzhi32_d1_indexzext: +; CM: ; %bb.0: +; CM-NEXT: ALU 0, @8, KC0[], KC1[] +; CM-NEXT: TEX 0 @6 +; CM-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[] +; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X +; CM-NEXT: CF_END +; CM-NEXT: PAD +; CM-NEXT: Fetch clause starting at 6: +; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3 +; CM-NEXT: ALU clause starting at 8: +; CM-NEXT: MOV * T0.X, 0.0, +; CM-NEXT: ALU clause starting at 9: +; CM-NEXT: SUB_INT * T0.W, literal.x, T0.X, +; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00) +; CM-NEXT: AND_INT * T0.W, PV.W, literal.x, +; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00) +; CM-NEXT: LSHL * T1.W, KC0[2].Y, PV.W, +; CM-NEXT: LSHR * T0.X, PV.W, T0.W, +; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) %numhighbits = sub i8 32, %numlowbits %sh_prom = zext i8 %numhighbits to i32 %highbitscleared = shl i32 %val, %sh_prom diff --git a/test/CodeGen/AMDGPU/skip-if-dead.ll b/test/CodeGen/AMDGPU/skip-if-dead.ll index 49c171e03de2..42a28b952739 100644 --- a/test/CodeGen/AMDGPU/skip-if-dead.ll +++ b/test/CodeGen/AMDGPU/skip-if-dead.ll @@ -72,10 +72,18 @@ define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { ; CHECK-LABEL: {{^}}test_kill_depth_var_x2_instructions: ; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 +; CHECK-NEXT: s_cbranch_execnz BB6_2 ; CHECK-NEXT: ; %bb.1: +; CHECK-NEXT: exp +; CHECK-NEXT: s_endpgm +; CHECK-NEXT: BB6_2: ; CHECK: v_mov_b32_e64 v7, -1 ; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 -; CHECK-NEXT: ; %bb.2: +; CHECK-NEXT: s_cbranch_execnz BB6_4 +; CHECK-NEXT: ; %bb.3: +; CHECK-NEXT: exp +; CHECK-NEXT: s_endpgm +; CHECK-NEXT: BB6_4: ; CHECK-NEXT: s_endpgm define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { call void @llvm.AMDGPU.kill(float %x) diff --git a/test/CodeGen/AMDGPU/store-global.ll b/test/CodeGen/AMDGPU/store-global.ll index a40e6b2683e5..8f8df884502b 100644 --- a/test/CodeGen/AMDGPU/store-global.ll +++ b/test/CodeGen/AMDGPU/store-global.ll @@ -24,23 +24,12 @@ entry: ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X ; EG-NOT: MEM_RAT MSKOR -; IG 0: Get the byte index and truncate the value -; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x -; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y -; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43) - - -; IG 1: Truncate the calculated the shift amount for the mask - -; IG 2: Shift the value and the mask -; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] -; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] -; EG-NEXT: 255 -; IG 3: Initialize the Y and Z channels to zero -; XXX: An optimal scheduler should merge this into one of the prevous IGs. -; EG: MOV T[[RW_GPR]].Y, 0.0 -; EG: MOV * T[[RW_GPR]].Z, 0.0 +; EG: VTX_READ_8 +; EG: AND_INT +; EG: AND_INT +; EG: LSHL +; EG: LSHL +; EG: LSHL ; SIVI: buffer_store_byte ; GFX9: global_store_byte @@ -55,26 +44,13 @@ entry: ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X ; EG-NOT: MEM_RAT MSKOR -; IG 0: Get the byte index and truncate the value - - -; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG-NEXT: 3(4.203895e-45), - -; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x -; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y - -; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41) -; IG 1: Truncate the calculated the shift amount for the mask +; EG: VTX_READ_16 +; EG: AND_INT +; EG: AND_INT +; EG: LSHL +; EG: LSHL +; EG: LSHL -; IG 2: Shift the value and the mask -; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] -; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] -; EG-NEXT: 65535 -; IG 3: Initialize the Y and Z channels to zero -; XXX: An optimal scheduler should merge this into one of the prevous IGs. -; EG: MOV T[[RW_GPR]].Y, 0.0 -; EG: MOV * T[[RW_GPR]].Z, 0.0 ; SIVI: buffer_store_short ; GFX9: global_store_short diff --git a/test/CodeGen/AMDGPU/store-private.ll b/test/CodeGen/AMDGPU/store-private.ll index f9fc75023d4f..840dc509d28c 100644 --- a/test/CodeGen/AMDGPU/store-private.ll +++ b/test/CodeGen/AMDGPU/store-private.ll @@ -32,7 +32,9 @@ entry: ; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x ; EG: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x ; EG-NEXT: 3(4.203895e-45) -; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.x + + +; EG: LSHL * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], literal.x, PV.W ; EG-NEXT: 255(3.573311e-43) ; EG: NOT_INT @@ -57,12 +59,12 @@ entry: ; EG: MOVA_INT * AR.x (MASKED) ; EG: MOV [[OLD:T[0-9]\.[XYZW]]], {{.*}}AR.x +; EG: VTX_READ_16 + ; IG 0: Get the byte index and truncate the value ; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x ; EG: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x ; EG-NEXT: 3(4.203895e-45) -; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.x -; EG-NEXT: 65535(9.183409e-41) ; EG: NOT_INT ; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]] diff --git a/test/CodeGen/AMDGPU/zero_extend.ll b/test/CodeGen/AMDGPU/zero_extend.ll index ee9bbb67c0e6..2f365cb503e1 100644 --- a/test/CodeGen/AMDGPU/zero_extend.ll +++ b/test/CodeGen/AMDGPU/zero_extend.ll @@ -51,11 +51,11 @@ define amdgpu_kernel void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, ; GCN: s_load_dword [[A:s[0-9]+]] ; GCN: s_load_dword [[B:s[0-9]+]] -; SI: v_mov_b32_e32 [[V_A:v[0-9]+]], [[A]] -; SI: v_cmp_eq_u32_e32 vcc, [[B]], [[V_A]] - -; VI: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]] -; VI: v_cmp_eq_u32_e32 vcc, [[A]], [[V_B]] +; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}} +; GCN-DAG: s_and_b32 [[MASK_A:s[0-9]+]], [[A]], [[MASK]] +; GCN-DAG: s_and_b32 [[MASK_B:s[0-9]+]], [[B]], [[MASK]] +; GCN: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]] +; GCN: v_cmp_eq_u32_e32 vcc, [[MASK_A]], [[V_B]] ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: buffer_store_short [[RESULT]] diff --git a/test/CodeGen/ARM/aggregate-padding.ll b/test/CodeGen/ARM/aggregate-padding.ll index bc46a9cdf913..ae7ab90fcd2f 100644 --- a/test/CodeGen/ARM/aggregate-padding.ll +++ b/test/CodeGen/ARM/aggregate-padding.ll @@ -99,3 +99,19 @@ define i16 @test_i16_forced_stack([8 x double], double, i32, i32, [3 x i16] %arg %sum = add i16 %val0, %val2 ret i16 %sum } + +; [2 x <4 x i32>] should be aligned only on a 64-bit boundary and contiguous. +; None of the two <4 x i32> elements should introduce any padding to 128 bits. +define i32 @test_4xi32_64bit_aligned_and_contiguous([8 x double], float, [2 x <4 x i32>] %arg) nounwind { +; CHECK-LABEL: test_4xi32_64bit_aligned_and_contiguous: +; CHECK-DAG: ldr [[VAL0_0:r[0-9]+]], [sp, #8] +; CHECK-DAG: ldr [[VAL1_0:r[0-9]+]], [sp, #24] +; CHECK: add r0, [[VAL0_0]], [[VAL1_0]] + + %val0 = extractvalue [2 x <4 x i32>] %arg, 0 + %val0_0 = extractelement <4 x i32> %val0, i32 0 + %val1 = extractvalue [2 x <4 x i32>] %arg, 1 + %val1_0 = extractelement <4 x i32> %val1, i32 0 + %sum = add i32 %val0_0, %val1_0 + ret i32 %sum +} diff --git a/test/CodeGen/ARM/inline-asm-operand-implicit-cast.ll b/test/CodeGen/ARM/inline-asm-operand-implicit-cast.ll index 8bb671e10fbf..45bdb124e032 100644 --- a/test/CodeGen/ARM/inline-asm-operand-implicit-cast.ll +++ b/test/CodeGen/ARM/inline-asm-operand-implicit-cast.ll @@ -17,6 +17,42 @@ define arm_aapcscc double @zerobits_double_soft() #0 { ret double %1 } +; Check support for returning a float in GPR with matching float input with +; soft float ABI +define arm_aapcscc float @flt_gpr_matching_in_op_soft(float %f) #0 { +; CHECK-LABEL: flt_gpr_matching_in_op_soft +; CHECK: mov r0, r0 + %1 = call float asm "mov $0, $1", "=&r,0"(float %f) + ret float %1 +} + +; Check support for returning a double in GPR with matching double input with +; soft float ABI +define arm_aapcscc double @dbl_gpr_matching_in_op_soft(double %d) #0 { +; CHECK-LABEL: dbl_gpr_matching_in_op_soft +; CHECK: mov r1, r0 + %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d) + ret double %1 +} + +; Check support for returning a float in specific GPR with matching float input +; with soft float ABI +define arm_aapcscc float @flt_gpr_matching_spec_reg_in_op_soft(float %f) #0 { +; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_soft +; CHECK: mov r3, r3 + %1 = call float asm "mov $0, $1", "=&{r3},0"(float %f) + ret float %1 +} + +; Check support for returning a double in specific GPR with matching double +; input with soft float ABI +define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_op_soft(double %d) #0 { +; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_soft +; CHECK: mov r3, r2 + %1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d) + ret double %1 +} + attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="true" } @@ -39,4 +75,48 @@ define double @zerobits_double_hard() #1 { ret double %1 } +; Check support for returning a float in GPR with matching float input with +; hard float ABI +define float @flt_gpr_matching_in_op_hard(float %f) #1 { +; CHECK-LABEL: flt_gpr_matching_in_op_hard +; CHECK: vmov r0, s0 +; CHECK: mov r0, r0 +; CHECK: vmov s0, r0 + %1 = call float asm "mov $0, $1", "=&r,0"(float %f) + ret float %1 +} + +; Check support for returning a double in GPR with matching double input with +; hard float ABI +define double @dbl_gpr_matching_in_op_hard(double %d) #1 { +; CHECK-LABEL: dbl_gpr_matching_in_op_hard +; CHECK: vmov r0, r1, d0 +; CHECK: mov r1, r0 +; CHECK: vmov d0, r0, r1 + %1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d) + ret double %1 +} + +; Check support for returning a float in specific GPR with matching float +; input with hard float ABI +define float @flt_gpr_matching_spec_reg_in_op_hard(float %f) #1 { +; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_hard +; CHECK: vmov r3, s0 +; CHECK: mov r3, r3 +; CHECK: vmov s0, r3 + %1 = call float asm "mov $0, $1", "=&{r3},0"(float %f) + ret float %1 +} + +; Check support for returning a double in specific GPR with matching double +; input with hard float ABI +define double @dbl_gpr_matching_spec_reg_in_op_hard(double %d) #1 { +; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_hard +; CHECK: vmov r2, r3, d0 +; CHECK: mov r3, r2 +; CHECK: vmov d0, r2, r3 + %1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d) + ret double %1 +} + attributes #1 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="false" } diff --git a/test/CodeGen/ARM/inlineasm-64bit.ll b/test/CodeGen/ARM/inlineasm-64bit.ll index 8e747c5eb650..62c71ab375c8 100644 --- a/test/CodeGen/ARM/inlineasm-64bit.ll +++ b/test/CodeGen/ARM/inlineasm-64bit.ll @@ -104,3 +104,11 @@ define i64 @tied_64bit_lookback_test(i64 %in) nounwind { %res = extractvalue {i64, i32, i64} %vars, 2 ret i64 %res } + +; Check access to low and high part with a specific register pair constraint +define i64 @low_high_specific_reg_pair(i64 %in) nounwind { +; CHECK-LABEL: low_high_specific_reg_pair +; CHECK: mov r3, r2 + %res = call i64 asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(i64 %in) + ret i64 %res +} diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll index 10e56a346a2a..49dbb03135f5 100644 --- a/test/CodeGen/ARM/machine-cse-cmp.ll +++ b/test/CodeGen/ARM/machine-cse-cmp.ll @@ -65,8 +65,8 @@ if.end: %s2 = sub nsw i32 %s, %size %s3 = sub nsw i32 %sub, %s2 ; CHECK: sub [[R1:r[0-9]+]], [[R2:r[0-9]+]], r2 -; CHECK: sub [[R3:r[0-9]+]], [[R1]], r2 -; CHECK: sub [[R4:r[0-9]+]], [[R1]], [[R3]] +; CHECK: sub [[R3:r[0-9]+]], r2, [[R1]] +; CHECK: add [[R4:r[0-9]+]], [[R1]], [[R3]] ; CHECK-NOT: sub ; CHECK: str store i32 %s3, i32* %offset, align 4 diff --git a/test/CodeGen/Hexagon/bit-cmp0.mir b/test/CodeGen/Hexagon/bit-cmp0.mir new file mode 100644 index 000000000000..e4a2514f0030 --- /dev/null +++ b/test/CodeGen/Hexagon/bit-cmp0.mir @@ -0,0 +1,154 @@ +# RUN: llc -march=hexagon -run-pass hexagon-bit-simplify -o - %s | FileCheck %s + +--- | + @g0 = global i32 0, align 4 + + define i32 @f0() { ret i32 0 } + define i32 @f1() { ret i32 0 } + define i32 @f2() { ret i32 0 } + define i32 @f3() { ret i32 0 } + define i32 @f4() { ret i32 0 } + define i32 @f5() { ret i32 0 } + define i32 @f6() { ret i32 0 } + define i32 @f7() { ret i32 0 } +... + +# Case 0: is-zero with known zero register +# CHECK-LABEL: name: f0 +# CHECK: %[[R00:[0-9]+]]:intregs = A2_tfrsi 1 +# CHECK: $r0 = COPY %[[R00]] +# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0 + +name: f0 +tracksRegLiveness: true +body: | + bb.0: + %0:intregs = A2_tfrsi 0 + %2:intregs = A4_rcmpeqi killed %0, 0 + $r0 = COPY %2 + PS_jmpret $r31, implicit-def dead $pc, implicit $r0 +... + +# Case 1: is-zero with known non-zero register +# CHECK-LABEL: name: f1 +# CHECK: %[[R10:[0-9]+]]:intregs = A2_tfrsi 0 +# CHECK: $r0 = COPY %[[R10]] +# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0 + +name: f1 +tracksRegLiveness: true +body: | + bb.0: + %0:intregs = A2_tfrsi 128 + %2:intregs = A4_rcmpeqi killed %0, 0 + $r0 = COPY %2 + PS_jmpret $r31, implicit-def dead $pc, implicit $r0 +... + +# Case 2: is-not-zero with known zero register +# CHECK-LABEL: name: f2 +# CHECK: %[[R20:[0-9]+]]:intregs = A2_tfrsi 0 +# CHECK: $r0 = COPY %[[R20]] +# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0 + +name: f2 +tracksRegLiveness: true +body: | + bb.0: + %0:intregs = A2_tfrsi 0 + %2:intregs = A4_rcmpneqi killed %0, 0 + $r0 = COPY %2 + PS_jmpret $r31, implicit-def dead $pc, implicit $r0 +... + +# Case 3: is-not-zero with known non-zero register +# CHECK-LABEL: name: f3 +# CHECK: %[[R30:[0-9]+]]:intregs = A2_tfrsi 1 +# CHECK: $r0 = COPY %[[R30]] +# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0 + +name: f3 +tracksRegLiveness: true +body: | + bb.0: + %0:intregs = A2_tfrsi 1024 + %2:intregs = A4_rcmpneqi killed %0, 0 + $r0 = COPY %2 + PS_jmpret $r31, implicit-def dead $pc, implicit $r0 +... + + +# Case 4: is-zero with mux(p, 1, 0) +# CHECK-LABEL: name: f4 +# CHECK: %[[R40:[0-9]+]]:predregs = COPY $p0 +# CHECK: %[[R41:[0-9]+]]:intregs = C2_muxii %[[R40]], 0, 1 +# CHECK: $r0 = COPY %[[R41]] +# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0 + +name: f4 +tracksRegLiveness: true +body: | + bb.0: + liveins: $p0 + %0:predregs = COPY $p0 + %1:intregs = C2_muxii %0, 1, 0 + %2:intregs = A4_rcmpeqi killed %1, 0 + $r0 = COPY %2 + PS_jmpret $r31, implicit-def dead $pc, implicit $r0 +... + +# Case 5: is-zero with mux(p, 0, 1) +# CHECK-LABEL: name: f5 +# CHECK: %[[R50:[0-9]+]]:predregs = COPY $p0 +# CHECK: %[[R51:[0-9]+]]:intregs = C2_muxii %[[R50]], 1, 0 +# CHECK: $r0 = COPY %[[R51]] +# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0 + +name: f5 +tracksRegLiveness: true +body: | + bb.0: + liveins: $p0 + %0:predregs = COPY $p0 + %1:intregs = C2_muxii %0, 0, 1 + %2:intregs = A4_rcmpeqi killed %1, 0 + $r0 = COPY %2 + PS_jmpret $r31, implicit-def dead $pc, implicit $r0 +... + +# Case 6: is-not-zero with mux(p, 1, 2) +# CHECK-LABEL: name: f6 +# CHECK: %[[R60:[0-9]+]]:intregs = A2_tfrsi 1 +# CHECK: $r0 = COPY %[[R60]] +# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0 + +name: f6 +tracksRegLiveness: true +body: | + bb.0: + liveins: $p0 + %0:predregs = COPY $p0 + %1:intregs = C2_muxii %0, 1, 2 + %2:intregs = A4_rcmpneqi killed %1, 0 + $r0 = COPY %2 + PS_jmpret $r31, implicit-def dead $pc, implicit $r0 +... + +# Case 7: is-not-zero with mux(p, @g0, 2) +# CHECK-LABEL: name: f7 +# CHECK: %[[R70:[0-9]+]]:intregs = A2_tfrsi 1 +# CHECK: $r0 = COPY %[[R70]] +# CHECK: PS_jmpret $r31, implicit-def dead $pc, implicit $r0 + +name: f7 +tracksRegLiveness: true +body: | + bb.0: + liveins: $p0 + %0:predregs = COPY $p0 + %1:intregs = C2_muxii %0, @g0, 2 + %2:intregs = A4_rcmpneqi killed %1, 0 + $r0 = COPY %2 + PS_jmpret $r31, implicit-def dead $pc, implicit $r0 +... + diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir new file mode 100644 index 000000000000..2c9bf5a827d4 --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir @@ -0,0 +1,46 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + @.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00" + + define void @main() {entry: ret void} + declare i32 @printf(i8*, ...) + +... +--- +name: main +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + ; MIPS32-LABEL: name: main + ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @.str + ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str + ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 18838 + ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi1]], 722 + ; MIPS32: [[LUi2:%[0-9]+]]:gpr32 = LUi 0 + ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi2]], 0 + ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; MIPS32: $a0 = COPY [[ADDiu]] + ; MIPS32: $a1 = COPY [[ORi]] + ; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0 + ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; MIPS32: $v0 = COPY [[ORi1]] + ; MIPS32: RetRA implicit $v0 + %2:gprb(p0) = G_GLOBAL_VALUE @.str + %1:gprb(p0) = COPY %2(p0) + %3:gprb(s32) = G_CONSTANT i32 1234567890 + %4:gprb(s32) = G_CONSTANT i32 0 + ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + $a0 = COPY %1(p0) + $a1 = COPY %3(s32) + JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0 + %0:gprb(s32) = COPY $v0 + ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... diff --git a/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll b/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll new file mode 100644 index 000000000000..a96028645f01 --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 + +@.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00" + +define i32 @main() { + ; MIPS32-LABEL: name: main + ; MIPS32: bb.1.entry: + ; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @.str + ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY [[GV]](p0) + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1234567890 + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; MIPS32: $a0 = COPY [[COPY]](p0) + ; MIPS32: $a1 = COPY [[C]](s32) + ; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0 + ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; MIPS32: $v0 = COPY [[C1]](s32) + ; MIPS32: RetRA implicit $v0 +entry: + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 signext 1234567890) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir b/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir new file mode 100644 index 000000000000..9fcc82164b1e --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir @@ -0,0 +1,43 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + @.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00" + + define void @main() {entry: ret void} + declare i32 @printf(i8*, ...) + +... +--- +name: main +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + ; MIPS32-LABEL: name: main + ; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @.str + ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY [[GV]](p0) + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1234567890 + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; MIPS32: $a0 = COPY [[COPY]](p0) + ; MIPS32: $a1 = COPY [[C]](s32) + ; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $v0 + ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; MIPS32: $v0 = COPY [[C1]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(p0) = G_GLOBAL_VALUE @.str + %1:_(p0) = COPY %2(p0) + %3:_(s32) = G_CONSTANT i32 1234567890 + %4:_(s32) = G_CONSTANT i32 0 + ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + $a0 = COPY %1(p0) + $a1 = COPY %3(s32) + JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0 + %0:_(s32) = COPY $v0 + ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll new file mode 100644 index 000000000000..ec98a3643596 --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 + +@.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00" + +define i32 @main() { +; MIPS32-LABEL: main: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: addiu $sp, $sp, -24 +; MIPS32-NEXT: .cfi_def_cfa_offset 24 +; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; MIPS32-NEXT: .cfi_offset 31, -4 +; MIPS32-NEXT: lui $1, %hi($.str) +; MIPS32-NEXT: addiu $4, $1, %lo($.str) +; MIPS32-NEXT: lui $1, 18838 +; MIPS32-NEXT: ori $5, $1, 722 +; MIPS32-NEXT: lui $1, 0 +; MIPS32-NEXT: ori $2, $1, 0 +; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill +; MIPS32-NEXT: jal printf +; MIPS32-NEXT: nop +; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload +; MIPS32-NEXT: move $2, $1 +; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; MIPS32-NEXT: addiu $sp, $sp, 24 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 signext 1234567890) + ret i32 0 +} + +declare i32 @printf(i8*, ...) + diff --git a/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir b/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir new file mode 100644 index 000000000000..11815516f64e --- /dev/null +++ b/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + @.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00" + + define void @main() {entry: ret void} + declare i32 @printf(i8*, ...) + +... +--- +name: main +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + ; MIPS32-LABEL: name: main + ; MIPS32: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @.str + ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY [[GV]](p0) + ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1234567890 + ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0 + ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + ; MIPS32: $a0 = COPY [[COPY]](p0) + ; MIPS32: $a1 = COPY [[C]](s32) + ; MIPS32: JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0 + ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $v0 + ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + ; MIPS32: $v0 = COPY [[C1]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(p0) = G_GLOBAL_VALUE @.str + %1:_(p0) = COPY %2(p0) + %3:_(s32) = G_CONSTANT i32 1234567890 + %4:_(s32) = G_CONSTANT i32 0 + ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp + $a0 = COPY %1(p0) + $a1 = COPY %3(s32) + JAL @printf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0 + %0:_(s32) = COPY $v0 + ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll index dc4f2f9c862b..cbb3c91299fa 100644 --- a/test/CodeGen/Mips/const-mult.ll +++ b/test/CodeGen/Mips/const-mult.ll @@ -312,20 +312,20 @@ define i32 @mul22224078_32(i32 %a) { ; MIPS32-NEXT: sll $2, $4, 4 ; MIPS32-NEXT: subu $1, $2, $1 ; MIPS32-NEXT: sll $2, $4, 6 -; MIPS32-NEXT: subu $1, $2, $1 +; MIPS32-NEXT: subu $1, $1, $2 ; MIPS32-NEXT: sll $2, $4, 8 -; MIPS32-NEXT: subu $1, $2, $1 +; MIPS32-NEXT: addu $1, $2, $1 ; MIPS32-NEXT: sll $2, $4, 10 -; MIPS32-NEXT: subu $1, $2, $1 +; MIPS32-NEXT: subu $1, $1, $2 ; MIPS32-NEXT: sll $2, $4, 13 -; MIPS32-NEXT: subu $1, $2, $1 +; MIPS32-NEXT: addu $1, $2, $1 ; MIPS32-NEXT: sll $2, $4, 16 -; MIPS32-NEXT: subu $1, $2, $1 +; MIPS32-NEXT: subu $1, $1, $2 ; MIPS32-NEXT: sll $2, $4, 24 ; MIPS32-NEXT: sll $3, $4, 22 ; MIPS32-NEXT: sll $5, $4, 20 ; MIPS32-NEXT: sll $4, $4, 18 -; MIPS32-NEXT: subu $1, $4, $1 +; MIPS32-NEXT: addu $1, $4, $1 ; MIPS32-NEXT: addu $1, $5, $1 ; MIPS32-NEXT: addu $1, $3, $1 ; MIPS32-NEXT: jr $ra @@ -338,20 +338,20 @@ define i32 @mul22224078_32(i32 %a) { ; MIPS64-NEXT: sll $3, $1, 4 ; MIPS64-NEXT: subu $2, $3, $2 ; MIPS64-NEXT: sll $3, $1, 6 -; MIPS64-NEXT: subu $2, $3, $2 +; MIPS64-NEXT: subu $2, $2, $3 ; MIPS64-NEXT: sll $3, $1, 8 -; MIPS64-NEXT: subu $2, $3, $2 +; MIPS64-NEXT: addu $2, $3, $2 ; MIPS64-NEXT: sll $3, $1, 10 -; MIPS64-NEXT: subu $2, $3, $2 +; MIPS64-NEXT: subu $2, $2, $3 ; MIPS64-NEXT: sll $3, $1, 13 -; MIPS64-NEXT: subu $2, $3, $2 +; MIPS64-NEXT: addu $2, $3, $2 ; MIPS64-NEXT: sll $3, $1, 16 -; MIPS64-NEXT: subu $2, $3, $2 +; MIPS64-NEXT: subu $2, $2, $3 ; MIPS64-NEXT: sll $3, $1, 24 ; MIPS64-NEXT: sll $4, $1, 22 ; MIPS64-NEXT: sll $5, $1, 20 ; MIPS64-NEXT: sll $1, $1, 18 -; MIPS64-NEXT: subu $1, $1, $2 +; MIPS64-NEXT: addu $1, $1, $2 ; MIPS64-NEXT: addu $1, $5, $1 ; MIPS64-NEXT: addu $1, $4, $1 ; MIPS64-NEXT: jr $ra @@ -373,20 +373,20 @@ define i64 @mul22224078_64(i64 %a) { ; MIPS32-NEXT: sll $4, $5, 4 ; MIPS32-NEXT: subu $3, $4, $3 ; MIPS32-NEXT: sll $4, $5, 6 -; MIPS32-NEXT: subu $3, $4, $3 +; MIPS32-NEXT: subu $3, $3, $4 ; MIPS32-NEXT: sll $4, $5, 8 -; MIPS32-NEXT: subu $3, $4, $3 +; MIPS32-NEXT: addu $3, $4, $3 ; MIPS32-NEXT: sll $4, $5, 10 -; MIPS32-NEXT: subu $3, $4, $3 +; MIPS32-NEXT: subu $3, $3, $4 ; MIPS32-NEXT: sll $4, $5, 13 -; MIPS32-NEXT: subu $3, $4, $3 +; MIPS32-NEXT: addu $3, $4, $3 ; MIPS32-NEXT: sll $4, $5, 16 -; MIPS32-NEXT: subu $3, $4, $3 +; MIPS32-NEXT: subu $3, $3, $4 ; MIPS32-NEXT: sll $4, $5, 24 ; MIPS32-NEXT: sll $6, $5, 22 ; MIPS32-NEXT: sll $7, $5, 20 ; MIPS32-NEXT: sll $5, $5, 18 -; MIPS32-NEXT: subu $3, $5, $3 +; MIPS32-NEXT: addu $3, $5, $3 ; MIPS32-NEXT: addu $3, $7, $3 ; MIPS32-NEXT: addu $3, $6, $3 ; MIPS32-NEXT: addu $3, $4, $3 @@ -399,20 +399,20 @@ define i64 @mul22224078_64(i64 %a) { ; MIPS64-NEXT: dsll $2, $4, 4 ; MIPS64-NEXT: dsubu $1, $2, $1 ; MIPS64-NEXT: dsll $2, $4, 6 -; MIPS64-NEXT: dsubu $1, $2, $1 +; MIPS64-NEXT: dsubu $1, $1, $2 ; MIPS64-NEXT: dsll $2, $4, 8 -; MIPS64-NEXT: dsubu $1, $2, $1 +; MIPS64-NEXT: daddu $1, $2, $1 ; MIPS64-NEXT: dsll $2, $4, 10 -; MIPS64-NEXT: dsubu $1, $2, $1 +; MIPS64-NEXT: dsubu $1, $1, $2 ; MIPS64-NEXT: dsll $2, $4, 13 -; MIPS64-NEXT: dsubu $1, $2, $1 +; MIPS64-NEXT: daddu $1, $2, $1 ; MIPS64-NEXT: dsll $2, $4, 16 -; MIPS64-NEXT: dsubu $1, $2, $1 +; MIPS64-NEXT: dsubu $1, $1, $2 ; MIPS64-NEXT: dsll $2, $4, 24 ; MIPS64-NEXT: dsll $3, $4, 22 ; MIPS64-NEXT: dsll $5, $4, 20 ; MIPS64-NEXT: dsll $4, $4, 18 -; MIPS64-NEXT: dsubu $1, $4, $1 +; MIPS64-NEXT: daddu $1, $4, $1 ; MIPS64-NEXT: daddu $1, $5, $1 ; MIPS64-NEXT: daddu $1, $3, $1 ; MIPS64-NEXT: jr $ra diff --git a/test/CodeGen/PowerPC/signbit-shift.ll b/test/CodeGen/PowerPC/signbit-shift.ll index 758758781448..41d250e924e2 100644 --- a/test/CodeGen/PowerPC/signbit-shift.ll +++ b/test/CodeGen/PowerPC/signbit-shift.ll @@ -243,8 +243,8 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) { define i32 @sub_lshr(i32 %x, i32 %y) { ; CHECK-LABEL: sub_lshr: ; CHECK: # %bb.0: -; CHECK-NEXT: srwi 3, 3, 31 -; CHECK-NEXT: subf 3, 3, 4 +; CHECK-NEXT: srawi 3, 3, 31 +; CHECK-NEXT: add 3, 4, 3 ; CHECK-NEXT: blr %sh = lshr i32 %x, 31 %r = sub i32 %y, %sh @@ -257,8 +257,8 @@ define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-NEXT: vspltisw 4, -16 ; CHECK-NEXT: vspltisw 5, 15 ; CHECK-NEXT: vsubuwm 4, 5, 4 -; CHECK-NEXT: vsrw 2, 2, 4 -; CHECK-NEXT: vsubuwm 2, 3, 2 +; CHECK-NEXT: vsraw 2, 2, 4 +; CHECK-NEXT: vadduwm 2, 3, 2 ; CHECK-NEXT: blr %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %r = sub <4 x i32> %y, %sh @@ -268,8 +268,8 @@ define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) { define i32 @sub_const_op_lshr(i32 %x) { ; CHECK-LABEL: sub_const_op_lshr: ; CHECK: # %bb.0: -; CHECK-NEXT: srwi 3, 3, 31 -; CHECK-NEXT: subfic 3, 3, 43 +; CHECK-NEXT: srawi 3, 3, 31 +; CHECK-NEXT: addi 3, 3, 43 ; CHECK-NEXT: blr %sh = lshr i32 %x, 31 %r = sub i32 43, %sh @@ -284,9 +284,9 @@ define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) { ; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l ; CHECK-NEXT: vsubuwm 3, 4, 3 -; CHECK-NEXT: vsrw 2, 2, 3 +; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: lvx 3, 0, 3 -; CHECK-NEXT: vsubuwm 2, 3, 2 +; CHECK-NEXT: vadduwm 2, 2, 3 ; CHECK-NEXT: blr %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh diff --git a/test/CodeGen/RISCV/tail-calls.ll b/test/CodeGen/RISCV/tail-calls.ll index 2279e8c37792..4d7db01d1fb7 100644 --- a/test/CodeGen/RISCV/tail-calls.ll +++ b/test/CodeGen/RISCV/tail-calls.ll @@ -106,7 +106,7 @@ entry: tail call void @callee_irq() ret void } -attributes #0 = { "interrupt" } +attributes #0 = { "interrupt"="machine" } ; Byval parameters hand the function a pointer directly into the stack area ; we want to reuse during a tail call. Do not tail call optimize functions with diff --git a/test/CodeGen/SystemZ/shift-12.ll b/test/CodeGen/SystemZ/shift-12.ll index 4ebc42b44a47..53d3d5362dfd 100644 --- a/test/CodeGen/SystemZ/shift-12.ll +++ b/test/CodeGen/SystemZ/shift-12.ll @@ -104,3 +104,15 @@ define i32 @f10(i32 %a, i32 %sh) { %reuse = add i32 %and, %shift ret i32 %reuse } + +; Test that AND is not removed for i128 (which calls __ashlti3) +define i128 @f11(i128 %a, i32 %sh) { +; CHECK-LABEL: f11: +; CHECK: risbg %r4, %r4, 57, 191, 0 +; CHECK: brasl %r14, __ashlti3@PLT + %and = and i32 %sh, 127 + %ext = zext i32 %and to i128 + %shift = shl i128 %a, %ext + ret i128 %shift +} + diff --git a/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll b/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll index 8714a5a5703c..9ed7ca217973 100644 --- a/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll +++ b/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll @@ -688,8 +688,8 @@ define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %va ; CHECK-NEXT: vpkg %v6, %v6, %v7 ; CHECK-NEXT: vpkg %v4, %v4, %v5 ; CHECK-NEXT: vn %v5, %v16, %v6 -; CHECK-NEXT: vsel %v24, %v3, %v2, %v5 -; CHECK-NEXT: vldeb %v17, %v17 +; CHECK-DAG: vsel %v24, %v3, %v2, %v5 +; CHECK-DAG: vldeb %v17, %v17 ; CHECK-NEXT: vldeb %v18, %v18 ; CHECK-NEXT: vfchdb %v17, %v18, %v17 ; CHECK-NEXT: vmrhf %v18, %v30, %v30 diff --git a/test/CodeGen/X86/atom-fixup-lea2.ll b/test/CodeGen/X86/atom-fixup-lea2.ll index 9b0b472be0f3..b8a0369a45f4 100644 --- a/test/CodeGen/X86/atom-fixup-lea2.ll +++ b/test/CodeGen/X86/atom-fixup-lea2.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s -; RUN: llc < %s -mcpu=goldmont -mtriple=i686-linux | FileCheck %s ; CHECK:%bb.5 ; CHECK-NEXT:leal diff --git a/test/CodeGen/X86/combine-sdiv.ll b/test/CodeGen/X86/combine-sdiv.ll index cc99d71009c6..7f0573c6175c 100644 --- a/test/CodeGen/X86/combine-sdiv.ll +++ b/test/CodeGen/X86/combine-sdiv.ll @@ -285,43 +285,23 @@ define <16 x i8> @combine_vec_sdiv_by_pow2b_v16i8(<16 x i8> %x) { ; SSE-LABEL: combine_vec_sdiv_by_pow2b_v16i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: pxor %xmm2, %xmm2 -; SSE-NEXT: pcmpgtb %xmm0, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm3 -; SSE-NEXT: psrlw $4, %xmm3 -; SSE-NEXT: pand {{.*}}(%rip), %xmm3 -; SSE-NEXT: movdqa {{.*#+}} xmm0 = [49408,32992,24736,57408,49408,32992,24736,57408] -; SSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm3 -; SSE-NEXT: psrlw $2, %xmm3 -; SSE-NEXT: pand {{.*}}(%rip), %xmm3 -; SSE-NEXT: paddb %xmm0, %xmm0 -; SSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm3 -; SSE-NEXT: psrlw $1, %xmm3 -; SSE-NEXT: pand {{.*}}(%rip), %xmm3 -; SSE-NEXT: paddb %xmm0, %xmm0 -; SSE-NEXT: pblendvb %xmm0, %xmm3, %xmm2 -; SSE-NEXT: paddb %xmm1, %xmm2 -; SSE-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15] -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psraw $4, %xmm4 -; SSE-NEXT: movdqa {{.*#+}} xmm5 = [16384,32800,41056,8384,16384,32800,41056,8384] -; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm5[8],xmm0[9],xmm5[9],xmm0[10],xmm5[10],xmm0[11],xmm5[11],xmm0[12],xmm5[12],xmm0[13],xmm5[13],xmm0[14],xmm5[14],xmm0[15],xmm5[15] -; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psraw $2, %xmm4 -; SSE-NEXT: paddw %xmm0, %xmm0 -; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psraw $1, %xmm4 -; SSE-NEXT: paddw %xmm0, %xmm0 -; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 +; SSE-NEXT: pxor %xmm0, %xmm0 +; SSE-NEXT: pcmpgtb %xmm1, %xmm0 +; SSE-NEXT: pmovzxbw {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [1,4,2,16,8,32,64,2] +; SSE-NEXT: pmullw %xmm2, %xmm3 ; SSE-NEXT: psrlw $8, %xmm3 -; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero +; SSE-NEXT: pmullw %xmm2, %xmm0 +; SSE-NEXT: psrlw $8, %xmm0 +; SSE-NEXT: packuswb %xmm0, %xmm3 +; SSE-NEXT: paddb %xmm1, %xmm3 +; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm3[8],xmm2[9],xmm3[9],xmm2[10],xmm3[10],xmm2[11],xmm3[11],xmm2[12],xmm3[12],xmm2[13],xmm3[13],xmm2[14],xmm3[14],xmm2[15],xmm3[15] ; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: psraw $4, %xmm4 -; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3],xmm0[4],xmm5[4],xmm0[5],xmm5[5],xmm0[6],xmm5[6],xmm0[7],xmm5[7] +; SSE-NEXT: movdqa {{.*#+}} xmm5 = [16384,32800,41056,8384,16384,32800,41056,8384] +; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm5[8],xmm0[9],xmm5[9],xmm0[10],xmm5[10],xmm0[11],xmm5[11],xmm0[12],xmm5[12],xmm0[13],xmm5[13],xmm0[14],xmm5[14],xmm0[15],xmm5[15] ; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm2 ; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: psraw $2, %xmm4 @@ -332,9 +312,23 @@ define <16 x i8> @combine_vec_sdiv_by_pow2b_v16i8(<16 x i8> %x) { ; SSE-NEXT: paddw %xmm0, %xmm0 ; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm2 ; SSE-NEXT: psrlw $8, %xmm2 -; SSE-NEXT: packuswb %xmm3, %xmm2 +; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE-NEXT: movdqa %xmm3, %xmm4 +; SSE-NEXT: psraw $4, %xmm4 +; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3],xmm0[4],xmm5[4],xmm0[5],xmm5[5],xmm0[6],xmm5[6],xmm0[7],xmm5[7] +; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 +; SSE-NEXT: movdqa %xmm3, %xmm4 +; SSE-NEXT: psraw $2, %xmm4 +; SSE-NEXT: paddw %xmm0, %xmm0 +; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 +; SSE-NEXT: movdqa %xmm3, %xmm4 +; SSE-NEXT: psraw $1, %xmm4 +; SSE-NEXT: paddw %xmm0, %xmm0 +; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 +; SSE-NEXT: psrlw $8, %xmm3 +; SSE-NEXT: packuswb %xmm2, %xmm3 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] -; SSE-NEXT: pblendvb %xmm0, %xmm2, %xmm1 +; SSE-NEXT: pblendvb %xmm0, %xmm3, %xmm1 ; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: retq ; @@ -342,18 +336,15 @@ define <16 x i8> @combine_vec_sdiv_by_pow2b_v16i8(<16 x i8> %x) { ; AVX1: # %bb.0: ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1 -; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 -; AVX1-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [49408,32992,24736,57408,49408,32992,24736,57408] -; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 -; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm2 -; AVX1-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3 -; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 -; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm2 -; AVX1-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX1-NEXT: vpaddb %xmm3, %xmm3, %xmm3 -; AVX1-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,4,2,16,8,32,64,2] +; AVX1-NEXT: vpmullw %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] +; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero +; AVX1-NEXT: vpmullw %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1 +; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm1 ; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] ; AVX1-NEXT: vpsraw $4, %xmm2, %xmm3 @@ -387,18 +378,11 @@ define <16 x i8> @combine_vec_sdiv_by_pow2b_v16i8(<16 x i8> %x) { ; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm1 -; AVX2-NEXT: vpsrlw $4, %xmm1, %xmm2 -; AVX2-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [49408,32992,24736,57408,49408,32992,24736,57408] -; AVX2-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 -; AVX2-NEXT: vpsrlw $2, %xmm1, %xmm2 -; AVX2-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX2-NEXT: vpaddb %xmm3, %xmm3, %xmm3 -; AVX2-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 -; AVX2-NEXT: vpsrlw $1, %xmm1, %xmm2 -; AVX2-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2 -; AVX2-NEXT: vpaddb %xmm3, %xmm3, %xmm3 -; AVX2-NEXT: vpblendvb %xmm3, %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero +; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm1, %ymm1 +; AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1 +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpaddb %xmm1, %xmm0, %xmm1 ; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] ; AVX2-NEXT: vpsraw $4, %xmm2, %xmm3 @@ -426,6 +410,7 @@ define <16 x i8> @combine_vec_sdiv_by_pow2b_v16i8(<16 x i8> %x) { ; AVX2-NEXT: vpackuswb %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; AVX2-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; ; AVX512F-LABEL: combine_vec_sdiv_by_pow2b_v16i8: @@ -481,18 +466,7 @@ define <8 x i16> @combine_vec_sdiv_by_pow2b_v8i16(<8 x i16> %x) { ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: psraw $15, %xmm1 -; SSE-NEXT: movdqa %xmm1, %xmm2 -; SSE-NEXT: psrlw $8, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm2, %xmm1 -; SSE-NEXT: psrlw $4, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3,4],xmm2[5,6],xmm1[7] -; SSE-NEXT: movdqa %xmm1, %xmm2 -; SSE-NEXT: psrlw $2, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2],xmm1[3,4],xmm2[5,6,7] -; SSE-NEXT: movdqa %xmm2, %xmm1 -; SSE-NEXT: psrlw $1, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2],xmm2[3],xmm1[4,5],xmm2[6],xmm1[7] +; SSE-NEXT: pmulhuw {{.*}}(%rip), %xmm1 ; SSE-NEXT: paddw %xmm0, %xmm1 ; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: psraw $4, %xmm2 @@ -510,14 +484,7 @@ define <8 x i16> @combine_vec_sdiv_by_pow2b_v8i16(<8 x i16> %x) { ; AVX1-LABEL: combine_vec_sdiv_by_pow2b_v8i16: ; AVX1: # %bb.0: ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm1 -; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7] -; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4],xmm1[5,6],xmm2[7] -; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2],xmm1[3,4],xmm2[5,6,7] -; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3],xmm2[4,5],xmm1[6],xmm2[7] +; AVX1-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm1 ; AVX1-NEXT: vpsraw $4, %xmm1, %xmm2 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3],xmm1[4],xmm2[5,6],xmm1[7] @@ -531,10 +498,7 @@ define <8 x i16> @combine_vec_sdiv_by_pow2b_v8i16(<8 x i16> %x) { ; AVX2-LABEL: combine_vec_sdiv_by_pow2b_v8i16: ; AVX2: # %bb.0: ; AVX2-NEXT: vpsraw $15, %xmm0, %xmm1 -; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero -; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %ymm1, %ymm1 -; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] -; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] +; AVX2-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1 ; AVX2-NEXT: vpaddw %xmm1, %xmm0, %xmm1 ; AVX2-NEXT: vpmovsxwd %xmm1, %ymm1 ; AVX2-NEXT: vpsravd {{.*}}(%rip), %ymm1, %ymm1 @@ -547,9 +511,7 @@ define <8 x i16> @combine_vec_sdiv_by_pow2b_v8i16(<8 x i16> %x) { ; AVX512F-LABEL: combine_vec_sdiv_by_pow2b_v8i16: ; AVX512F: # %bb.0: ; AVX512F-NEXT: vpsraw $15, %xmm0, %xmm1 -; AVX512F-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero -; AVX512F-NEXT: vpsrlvd {{.*}}(%rip), %ymm1, %ymm1 -; AVX512F-NEXT: vpmovdw %zmm1, %ymm1 +; AVX512F-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1 ; AVX512F-NEXT: vpaddw %xmm1, %xmm0, %xmm1 ; AVX512F-NEXT: vpmovsxwd %xmm1, %ymm1 ; AVX512F-NEXT: vpsravd {{.*}}(%rip), %ymm1, %ymm1 @@ -583,70 +545,44 @@ define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) { ; SSE-LABEL: combine_vec_sdiv_by_pow2b_v16i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: psraw $15, %xmm2 +; SSE-NEXT: movdqa {{.*#+}} xmm3 = [1,4,2,16,8,32,64,2] +; SSE-NEXT: pmulhuw %xmm3, %xmm2 +; SSE-NEXT: paddw %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm2, %xmm4 +; SSE-NEXT: psraw $4, %xmm4 +; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm2[0,1,2],xmm4[3],xmm2[4],xmm4[5,6],xmm2[7] +; SSE-NEXT: movdqa %xmm4, %xmm5 +; SSE-NEXT: psraw $2, %xmm5 +; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm4[0],xmm5[1],xmm4[2,3],xmm5[4],xmm4[5],xmm5[6],xmm4[7] +; SSE-NEXT: movdqa %xmm5, %xmm2 +; SSE-NEXT: psraw $1, %xmm2 +; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm5[0,1],xmm2[2],xmm5[3],xmm2[4,5],xmm5[6],xmm2[7] +; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3,4,5,6,7] +; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: psraw $15, %xmm0 -; SSE-NEXT: movdqa %xmm0, %xmm3 -; SSE-NEXT: psrlw $8, %xmm3 -; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm3, %xmm0 -; SSE-NEXT: psrlw $4, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0],xmm0[1,2,3,4],xmm3[5,6],xmm0[7] -; SSE-NEXT: movdqa %xmm0, %xmm3 -; SSE-NEXT: psrlw $2, %xmm3 -; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm0[0],xmm3[1,2],xmm0[3,4],xmm3[5,6,7] -; SSE-NEXT: movdqa %xmm3, %xmm0 -; SSE-NEXT: psrlw $1, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1],xmm0[2],xmm3[3],xmm0[4,5],xmm3[6],xmm0[7] -; SSE-NEXT: paddw %xmm2, %xmm0 +; SSE-NEXT: pmulhuw %xmm3, %xmm0 +; SSE-NEXT: paddw %xmm1, %xmm0 ; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: psraw $4, %xmm3 ; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm0[0,1,2],xmm3[3],xmm0[4],xmm3[5,6],xmm0[7] -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psraw $2, %xmm4 -; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm3[0],xmm4[1],xmm3[2,3],xmm4[4],xmm3[5],xmm4[6],xmm3[7] -; SSE-NEXT: movdqa %xmm4, %xmm0 -; SSE-NEXT: psraw $1, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm4[0,1],xmm0[2],xmm4[3],xmm0[4,5],xmm4[6],xmm0[7] -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm1, %xmm2 -; SSE-NEXT: psraw $15, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm3 -; SSE-NEXT: psrlw $8, %xmm3 -; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0],xmm3[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm3, %xmm2 -; SSE-NEXT: psrlw $4, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3,4],xmm3[5,6],xmm2[7] -; SSE-NEXT: movdqa %xmm2, %xmm3 -; SSE-NEXT: psrlw $2, %xmm3 -; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0],xmm3[1,2],xmm2[3,4],xmm3[5,6,7] -; SSE-NEXT: movdqa %xmm3, %xmm2 -; SSE-NEXT: psrlw $1, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2],xmm3[3],xmm2[4,5],xmm3[6],xmm2[7] -; SSE-NEXT: paddw %xmm1, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm3 -; SSE-NEXT: psraw $4, %xmm3 -; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1,2],xmm3[3],xmm2[4],xmm3[5,6],xmm2[7] -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psraw $2, %xmm4 -; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm3[0],xmm4[1],xmm3[2,3],xmm4[4],xmm3[5],xmm4[6],xmm3[7] -; SSE-NEXT: movdqa %xmm4, %xmm2 -; SSE-NEXT: psraw $1, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm4[0,1],xmm2[2],xmm4[3],xmm2[4,5],xmm4[6],xmm2[7] -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm2, %xmm1 +; SSE-NEXT: movdqa %xmm3, %xmm0 +; SSE-NEXT: psraw $2, %xmm0 +; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0],xmm0[1],xmm3[2,3],xmm0[4],xmm3[5],xmm0[6],xmm3[7] +; SSE-NEXT: movdqa %xmm0, %xmm3 +; SSE-NEXT: psraw $1, %xmm3 +; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm0[0,1],xmm3[2],xmm0[3],xmm3[4,5],xmm0[6],xmm3[7] +; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3,4,5,6,7] +; SSE-NEXT: movdqa %xmm2, %xmm0 +; SSE-NEXT: movdqa %xmm3, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: combine_vec_sdiv_by_pow2b_v16i16: ; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpsraw $15, %xmm1, %xmm2 -; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3,4,5,6,7] -; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3,4],xmm2[5,6],xmm3[7] -; AVX1-NEXT: vpsrlw $2, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2],xmm2[3,4],xmm3[5,6,7] -; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2],xmm2[3],xmm3[4,5],xmm2[6],xmm3[7] +; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,4,2,16,8,32,64,2] +; AVX1-NEXT: vpmulhuw %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpsraw $4, %xmm1, %xmm2 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3],xmm1[4],xmm2[5,6],xmm1[7] @@ -655,14 +591,7 @@ define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) { ; AVX1-NEXT: vpsraw $1, %xmm1, %xmm2 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3],xmm2[4,5],xmm1[6],xmm2[7] ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm2 -; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3,4,5,6,7] -; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3,4],xmm2[5,6],xmm3[7] -; AVX1-NEXT: vpsrlw $2, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2],xmm2[3,4],xmm3[5,6,7] -; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2],xmm2[3],xmm3[4,5],xmm2[6],xmm3[7] +; AVX1-NEXT: vpmulhuw %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpaddw %xmm2, %xmm0, %xmm2 ; AVX1-NEXT: vpsraw $4, %xmm2, %xmm3 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[3],xmm2[4],xmm3[5,6],xmm2[7] @@ -680,26 +609,17 @@ define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) { ; AVX2-LABEL: combine_vec_sdiv_by_pow2b_v16i16: ; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [16,14,15,12,13,11,10,15,16,14,15,12,13,11,10,15] +; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2,1,4,3,5,6,1,0,2,1,4,3,5,6,1] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm1[4],ymm2[5],ymm1[5],ymm2[6],ymm1[6],ymm2[7],ymm1[7],ymm2[12],ymm1[12],ymm2[13],ymm1[13],ymm2[14],ymm1[14],ymm2[15],ymm1[15] ; AVX2-NEXT: vpsraw $15, %ymm0, %ymm4 +; AVX2-NEXT: vpmulhuw {{.*}}(%rip), %ymm4, %ymm4 +; AVX2-NEXT: vpaddw %ymm4, %ymm0, %ymm4 ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm1[4],ymm4[4],ymm1[5],ymm4[5],ymm1[6],ymm4[6],ymm1[7],ymm4[7],ymm1[12],ymm4[12],ymm1[13],ymm4[13],ymm1[14],ymm4[14],ymm1[15],ymm4[15] -; AVX2-NEXT: vpsrlvd %ymm3, %ymm5, %ymm3 +; AVX2-NEXT: vpsravd %ymm3, %ymm5, %ymm3 ; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm1[0],ymm2[1],ymm1[1],ymm2[2],ymm1[2],ymm2[3],ymm1[3],ymm2[8],ymm1[8],ymm2[9],ymm1[9],ymm2[10],ymm1[10],ymm2[11],ymm1[11] -; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm4 = ymm1[0],ymm4[0],ymm1[1],ymm4[1],ymm1[2],ymm4[2],ymm1[3],ymm4[3],ymm1[8],ymm4[8],ymm1[9],ymm4[9],ymm1[10],ymm4[10],ymm1[11],ymm4[11] -; AVX2-NEXT: vpsrlvd %ymm2, %ymm4, %ymm2 -; AVX2-NEXT: vpsrld $16, %ymm2, %ymm2 -; AVX2-NEXT: vpackusdw %ymm3, %ymm2, %ymm2 -; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm2 -; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15] -; AVX2-NEXT: vmovdqa {{.*#+}} ymm4 = [0,2,1,4,3,5,6,1,0,2,1,4,3,5,6,1] -; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15] -; AVX2-NEXT: vpsravd %ymm5, %ymm3, %ymm3 -; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 -; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11] -; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm4[0],ymm1[0],ymm4[1],ymm1[1],ymm4[2],ymm1[2],ymm4[3],ymm1[3],ymm4[8],ymm1[8],ymm4[9],ymm1[9],ymm4[10],ymm1[10],ymm4[11],ymm1[11] -; AVX2-NEXT: vpsravd %ymm1, %ymm2, %ymm1 +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm4[0],ymm1[1],ymm4[1],ymm1[2],ymm4[2],ymm1[3],ymm4[3],ymm1[8],ymm4[8],ymm1[9],ymm4[9],ymm1[10],ymm4[10],ymm1[11],ymm4[11] +; AVX2-NEXT: vpsravd %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 ; AVX2-NEXT: vpackusdw %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7],ymm0[8],ymm1[9,10,11,12,13,14,15] @@ -708,9 +628,7 @@ define <16 x i16> @combine_vec_sdiv_by_pow2b_v16i16(<16 x i16> %x) { ; AVX512F-LABEL: combine_vec_sdiv_by_pow2b_v16i16: ; AVX512F: # %bb.0: ; AVX512F-NEXT: vpsraw $15, %ymm0, %ymm1 -; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero -; AVX512F-NEXT: vpsrlvd {{.*}}(%rip), %zmm1, %zmm1 -; AVX512F-NEXT: vpmovdw %zmm1, %ymm1 +; AVX512F-NEXT: vpmulhuw {{.*}}(%rip), %ymm1, %ymm1 ; AVX512F-NEXT: vpaddw %ymm1, %ymm0, %ymm1 ; AVX512F-NEXT: vpmovsxwd %ymm1, %zmm1 ; AVX512F-NEXT: vpsravd {{.*}}(%rip), %zmm1, %zmm1 @@ -753,93 +671,50 @@ define <32 x i16> @combine_vec_sdiv_by_pow2b_v32i16(<32 x i16> %x) { ; SSE-NEXT: movdqa %xmm1, %xmm4 ; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: psraw $15, %xmm0 -; SSE-NEXT: movdqa %xmm0, %xmm5 -; SSE-NEXT: psrlw $8, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm0[0],xmm5[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm5, %xmm0 -; SSE-NEXT: psrlw $4, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm5[0],xmm0[1,2,3,4],xmm5[5,6],xmm0[7] -; SSE-NEXT: movdqa %xmm0, %xmm5 -; SSE-NEXT: psrlw $2, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm0[0],xmm5[1,2],xmm0[3,4],xmm5[5,6,7] -; SSE-NEXT: movdqa %xmm5, %xmm0 -; SSE-NEXT: psrlw $1, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm5[0,1],xmm0[2],xmm5[3],xmm0[4,5],xmm5[6],xmm0[7] +; SSE-NEXT: movdqa {{.*#+}} xmm5 = [1,4,2,16,8,32,64,2] +; SSE-NEXT: pmulhuw %xmm5, %xmm0 ; SSE-NEXT: paddw %xmm1, %xmm0 -; SSE-NEXT: movdqa %xmm0, %xmm5 -; SSE-NEXT: psraw $4, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm0[0,1,2],xmm5[3],xmm0[4],xmm5[5,6],xmm0[7] -; SSE-NEXT: movdqa %xmm5, %xmm6 -; SSE-NEXT: psraw $2, %xmm6 -; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm5[0],xmm6[1],xmm5[2,3],xmm6[4],xmm5[5],xmm6[6],xmm5[7] -; SSE-NEXT: movdqa %xmm6, %xmm0 +; SSE-NEXT: movdqa %xmm0, %xmm6 +; SSE-NEXT: psraw $4, %xmm6 +; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm0[0,1,2],xmm6[3],xmm0[4],xmm6[5,6],xmm0[7] +; SSE-NEXT: movdqa %xmm6, %xmm7 +; SSE-NEXT: psraw $2, %xmm7 +; SSE-NEXT: pblendw {{.*#+}} xmm7 = xmm6[0],xmm7[1],xmm6[2,3],xmm7[4],xmm6[5],xmm7[6],xmm6[7] +; SSE-NEXT: movdqa %xmm7, %xmm0 ; SSE-NEXT: psraw $1, %xmm0 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm6[0,1],xmm0[2],xmm6[3],xmm0[4,5],xmm6[6],xmm0[7] +; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm7[0,1],xmm0[2],xmm7[3],xmm0[4,5],xmm7[6],xmm0[7] ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7] ; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: psraw $15, %xmm1 -; SSE-NEXT: movdqa %xmm1, %xmm5 -; SSE-NEXT: psrlw $8, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm1[0],xmm5[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm5, %xmm1 -; SSE-NEXT: psrlw $4, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm5[0],xmm1[1,2,3,4],xmm5[5,6],xmm1[7] -; SSE-NEXT: movdqa %xmm1, %xmm5 -; SSE-NEXT: psrlw $2, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm1[0],xmm5[1,2],xmm1[3,4],xmm5[5,6,7] -; SSE-NEXT: movdqa %xmm5, %xmm1 -; SSE-NEXT: psrlw $1, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm5[0,1],xmm1[2],xmm5[3],xmm1[4,5],xmm5[6],xmm1[7] +; SSE-NEXT: pmulhuw %xmm5, %xmm1 ; SSE-NEXT: paddw %xmm4, %xmm1 -; SSE-NEXT: movdqa %xmm1, %xmm5 -; SSE-NEXT: psraw $4, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm1[0,1,2],xmm5[3],xmm1[4],xmm5[5,6],xmm1[7] -; SSE-NEXT: movdqa %xmm5, %xmm6 -; SSE-NEXT: psraw $2, %xmm6 -; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm5[0],xmm6[1],xmm5[2,3],xmm6[4],xmm5[5],xmm6[6],xmm5[7] -; SSE-NEXT: movdqa %xmm6, %xmm1 +; SSE-NEXT: movdqa %xmm1, %xmm6 +; SSE-NEXT: psraw $4, %xmm6 +; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm1[0,1,2],xmm6[3],xmm1[4],xmm6[5,6],xmm1[7] +; SSE-NEXT: movdqa %xmm6, %xmm7 +; SSE-NEXT: psraw $2, %xmm7 +; SSE-NEXT: pblendw {{.*#+}} xmm7 = xmm6[0],xmm7[1],xmm6[2,3],xmm7[4],xmm6[5],xmm7[6],xmm6[7] +; SSE-NEXT: movdqa %xmm7, %xmm1 ; SSE-NEXT: psraw $1, %xmm1 -; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm6[0,1],xmm1[2],xmm6[3],xmm1[4,5],xmm6[6],xmm1[7] +; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm7[0,1],xmm1[2],xmm7[3],xmm1[4,5],xmm7[6],xmm1[7] ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm4[0],xmm1[1,2,3,4,5,6,7] ; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: psraw $15, %xmm4 -; SSE-NEXT: movdqa %xmm4, %xmm5 -; SSE-NEXT: psrlw $8, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm4[0],xmm5[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm5, %xmm4 -; SSE-NEXT: psrlw $4, %xmm4 -; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm5[0],xmm4[1,2,3,4],xmm5[5,6],xmm4[7] -; SSE-NEXT: movdqa %xmm4, %xmm5 -; SSE-NEXT: psrlw $2, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm4[0],xmm5[1,2],xmm4[3,4],xmm5[5,6,7] -; SSE-NEXT: movdqa %xmm5, %xmm4 -; SSE-NEXT: psrlw $1, %xmm4 -; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm5[0,1],xmm4[2],xmm5[3],xmm4[4,5],xmm5[6],xmm4[7] +; SSE-NEXT: pmulhuw %xmm5, %xmm4 ; SSE-NEXT: paddw %xmm2, %xmm4 -; SSE-NEXT: movdqa %xmm4, %xmm5 -; SSE-NEXT: psraw $4, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm4[0,1,2],xmm5[3],xmm4[4],xmm5[5,6],xmm4[7] -; SSE-NEXT: movdqa %xmm5, %xmm6 -; SSE-NEXT: psraw $2, %xmm6 -; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm5[0],xmm6[1],xmm5[2,3],xmm6[4],xmm5[5],xmm6[6],xmm5[7] -; SSE-NEXT: movdqa %xmm6, %xmm4 +; SSE-NEXT: movdqa %xmm4, %xmm6 +; SSE-NEXT: psraw $4, %xmm6 +; SSE-NEXT: pblendw {{.*#+}} xmm6 = xmm4[0,1,2],xmm6[3],xmm4[4],xmm6[5,6],xmm4[7] +; SSE-NEXT: movdqa %xmm6, %xmm7 +; SSE-NEXT: psraw $2, %xmm7 +; SSE-NEXT: pblendw {{.*#+}} xmm7 = xmm6[0],xmm7[1],xmm6[2,3],xmm7[4],xmm6[5],xmm7[6],xmm6[7] +; SSE-NEXT: movdqa %xmm7, %xmm4 ; SSE-NEXT: psraw $1, %xmm4 -; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm6[0,1],xmm4[2],xmm6[3],xmm4[4,5],xmm6[6],xmm4[7] +; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm7[0,1],xmm4[2],xmm7[3],xmm4[4,5],xmm7[6],xmm4[7] ; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm2[0],xmm4[1,2,3,4,5,6,7] ; SSE-NEXT: movdqa %xmm3, %xmm2 ; SSE-NEXT: psraw $15, %xmm2 -; SSE-NEXT: movdqa %xmm2, %xmm5 -; SSE-NEXT: psrlw $8, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm2[0],xmm5[1,2,3,4,5,6,7] -; SSE-NEXT: movdqa %xmm5, %xmm2 -; SSE-NEXT: psrlw $4, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm5[0],xmm2[1,2,3,4],xmm5[5,6],xmm2[7] -; SSE-NEXT: movdqa %xmm2, %xmm5 -; SSE-NEXT: psrlw $2, %xmm5 -; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm2[0],xmm5[1,2],xmm2[3,4],xmm5[5,6,7] -; SSE-NEXT: movdqa %xmm5, %xmm2 -; SSE-NEXT: psrlw $1, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm5[0,1],xmm2[2],xmm5[3],xmm2[4,5],xmm5[6],xmm2[7] +; SSE-NEXT: pmulhuw %xmm5, %xmm2 ; SSE-NEXT: paddw %xmm3, %xmm2 ; SSE-NEXT: movdqa %xmm2, %xmm5 ; SSE-NEXT: psraw $4, %xmm5 @@ -857,54 +732,10 @@ define <32 x i16> @combine_vec_sdiv_by_pow2b_v32i16(<32 x i16> %x) { ; ; AVX1-LABEL: combine_vec_sdiv_by_pow2b_v32i16: ; AVX1: # %bb.0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; AVX1-NEXT: vpsraw $15, %xmm2, %xmm3 -; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1,2,3,4,5,6,7] -; AVX1-NEXT: vpsrlw $4, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1,2,3,4],xmm3[5,6],xmm4[7] -; AVX1-NEXT: vpsrlw $2, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1,2],xmm3[3,4],xmm4[5,6,7] -; AVX1-NEXT: vpsrlw $1, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2],xmm3[3],xmm4[4,5],xmm3[6],xmm4[7] -; AVX1-NEXT: vpaddw %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpsraw $4, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[3],xmm2[4],xmm3[5,6],xmm2[7] -; AVX1-NEXT: vpsraw $2, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1],xmm2[2,3],xmm3[4],xmm2[5],xmm3[6],xmm2[7] -; AVX1-NEXT: vpsraw $1, %xmm2, %xmm3 -; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2],xmm2[3],xmm3[4,5],xmm2[6],xmm3[7] -; AVX1-NEXT: vpsraw $15, %xmm0, %xmm3 -; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1,2,3,4,5,6,7] -; AVX1-NEXT: vpsrlw $4, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1,2,3,4],xmm3[5,6],xmm4[7] -; AVX1-NEXT: vpsrlw $2, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1,2],xmm3[3,4],xmm4[5,6,7] -; AVX1-NEXT: vpsrlw $1, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2],xmm3[3],xmm4[4,5],xmm3[6],xmm4[7] -; AVX1-NEXT: vpaddw %xmm3, %xmm0, %xmm3 -; AVX1-NEXT: vpsraw $4, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[3],xmm3[4],xmm4[5,6],xmm3[7] -; AVX1-NEXT: vpsraw $2, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2,3],xmm4[4],xmm3[5],xmm4[6],xmm3[7] -; AVX1-NEXT: vpsraw $1, %xmm3, %xmm4 -; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2],xmm3[3],xmm4[4,5],xmm3[6],xmm4[7] -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm3 -; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [0,65535,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,65535] -; AVX1-NEXT: vandps %ymm2, %ymm3, %ymm3 -; AVX1-NEXT: vandnps %ymm0, %ymm2, %ymm0 -; AVX1-NEXT: vorps %ymm0, %ymm3, %ymm0 -; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpsraw $15, %xmm3, %xmm4 -; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm5 -; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2,3,4,5,6,7] -; AVX1-NEXT: vpsrlw $4, %xmm4, %xmm5 -; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2,3,4],xmm4[5,6],xmm5[7] -; AVX1-NEXT: vpsrlw $2, %xmm4, %xmm5 -; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2],xmm4[3,4],xmm5[5,6,7] -; AVX1-NEXT: vpsrlw $1, %xmm4, %xmm5 -; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1],xmm5[2],xmm4[3],xmm5[4,5],xmm4[6],xmm5[7] +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1,4,2,16,8,32,64,2] +; AVX1-NEXT: vpmulhuw %xmm2, %xmm4, %xmm4 ; AVX1-NEXT: vpaddw %xmm4, %xmm3, %xmm3 ; AVX1-NEXT: vpsraw $4, %xmm3, %xmm4 ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[3],xmm3[4],xmm4[5,6],xmm3[7] @@ -912,16 +743,9 @@ define <32 x i16> @combine_vec_sdiv_by_pow2b_v32i16(<32 x i16> %x) { ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1],xmm3[2,3],xmm4[4],xmm3[5],xmm4[6],xmm3[7] ; AVX1-NEXT: vpsraw $1, %xmm3, %xmm4 ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2],xmm3[3],xmm4[4,5],xmm3[6],xmm4[7] -; AVX1-NEXT: vpsraw $15, %xmm1, %xmm4 -; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm5 -; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2,3,4,5,6,7] -; AVX1-NEXT: vpsrlw $4, %xmm4, %xmm5 -; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2,3,4],xmm4[5,6],xmm5[7] -; AVX1-NEXT: vpsrlw $2, %xmm4, %xmm5 -; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2],xmm4[3,4],xmm5[5,6,7] -; AVX1-NEXT: vpsrlw $1, %xmm4, %xmm5 -; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1],xmm5[2],xmm4[3],xmm5[4,5],xmm4[6],xmm5[7] -; AVX1-NEXT: vpaddw %xmm4, %xmm1, %xmm4 +; AVX1-NEXT: vpsraw $15, %xmm0, %xmm4 +; AVX1-NEXT: vpmulhuw %xmm2, %xmm4, %xmm4 +; AVX1-NEXT: vpaddw %xmm4, %xmm0, %xmm4 ; AVX1-NEXT: vpsraw $4, %xmm4, %xmm5 ; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1,2],xmm5[3],xmm4[4],xmm5[5,6],xmm4[7] ; AVX1-NEXT: vpsraw $2, %xmm4, %xmm5 @@ -929,51 +753,62 @@ define <32 x i16> @combine_vec_sdiv_by_pow2b_v32i16(<32 x i16> %x) { ; AVX1-NEXT: vpsraw $1, %xmm4, %xmm5 ; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1],xmm5[2],xmm4[3],xmm5[4,5],xmm4[6],xmm5[7] ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm4, %ymm3 -; AVX1-NEXT: vandps %ymm2, %ymm3, %ymm3 -; AVX1-NEXT: vandnps %ymm1, %ymm2, %ymm1 -; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1 +; AVX1-NEXT: vmovaps {{.*#+}} ymm4 = [0,65535,65535,65535,65535,65535,65535,65535,0,65535,65535,65535,65535,65535,65535,65535] +; AVX1-NEXT: vandps %ymm4, %ymm3, %ymm3 +; AVX1-NEXT: vandnps %ymm0, %ymm4, %ymm0 +; AVX1-NEXT: vorps %ymm0, %ymm3, %ymm0 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpsraw $15, %xmm3, %xmm5 +; AVX1-NEXT: vpmulhuw %xmm2, %xmm5, %xmm5 +; AVX1-NEXT: vpaddw %xmm5, %xmm3, %xmm3 +; AVX1-NEXT: vpsraw $4, %xmm3, %xmm5 +; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2],xmm5[3],xmm3[4],xmm5[5,6],xmm3[7] +; AVX1-NEXT: vpsraw $2, %xmm3, %xmm5 +; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm5[1],xmm3[2,3],xmm5[4],xmm3[5],xmm5[6],xmm3[7] +; AVX1-NEXT: vpsraw $1, %xmm3, %xmm5 +; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm5[2],xmm3[3],xmm5[4,5],xmm3[6],xmm5[7] +; AVX1-NEXT: vpsraw $15, %xmm1, %xmm5 +; AVX1-NEXT: vpmulhuw %xmm2, %xmm5, %xmm2 +; AVX1-NEXT: vpaddw %xmm2, %xmm1, %xmm2 +; AVX1-NEXT: vpsraw $4, %xmm2, %xmm5 +; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2],xmm5[3],xmm2[4],xmm5[5,6],xmm2[7] +; AVX1-NEXT: vpsraw $2, %xmm2, %xmm5 +; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm5[1],xmm2[2,3],xmm5[4],xmm2[5],xmm5[6],xmm2[7] +; AVX1-NEXT: vpsraw $1, %xmm2, %xmm5 +; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2],xmm2[3],xmm5[4,5],xmm2[6],xmm5[7] +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 +; AVX1-NEXT: vandps %ymm4, %ymm2, %ymm2 +; AVX1-NEXT: vandnps %ymm1, %ymm4, %ymm1 +; AVX1-NEXT: vorps %ymm1, %ymm2, %ymm1 ; AVX1-NEXT: retq ; ; AVX2-LABEL: combine_vec_sdiv_by_pow2b_v32i16: ; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 -; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [16,14,15,12,13,11,10,15,16,14,15,12,13,11,10,15] +; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,2,1,4,3,5,6,1,0,2,1,4,3,5,6,1] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm3[4],ymm2[4],ymm3[5],ymm2[5],ymm3[6],ymm2[6],ymm3[7],ymm2[7],ymm3[12],ymm2[12],ymm3[13],ymm2[13],ymm3[14],ymm2[14],ymm3[15],ymm2[15] ; AVX2-NEXT: vpsraw $15, %ymm0, %ymm5 -; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm6 = ymm2[4],ymm5[4],ymm2[5],ymm5[5],ymm2[6],ymm5[6],ymm2[7],ymm5[7],ymm2[12],ymm5[12],ymm2[13],ymm5[13],ymm2[14],ymm5[14],ymm2[15],ymm5[15] -; AVX2-NEXT: vpsrlvd %ymm4, %ymm6, %ymm6 -; AVX2-NEXT: vpsrld $16, %ymm6, %ymm6 -; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm3 = ymm3[0],ymm2[0],ymm3[1],ymm2[1],ymm3[2],ymm2[2],ymm3[3],ymm2[3],ymm3[8],ymm2[8],ymm3[9],ymm2[9],ymm3[10],ymm2[10],ymm3[11],ymm2[11] -; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm2[0],ymm5[0],ymm2[1],ymm5[1],ymm2[2],ymm5[2],ymm2[3],ymm5[3],ymm2[8],ymm5[8],ymm2[9],ymm5[9],ymm2[10],ymm5[10],ymm2[11],ymm5[11] -; AVX2-NEXT: vpsrlvd %ymm3, %ymm5, %ymm5 -; AVX2-NEXT: vpsrld $16, %ymm5, %ymm5 -; AVX2-NEXT: vpackusdw %ymm6, %ymm5, %ymm5 +; AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm6 = [1,4,2,16,8,32,64,2,1,4,2,16,8,32,64,2] +; AVX2-NEXT: # ymm6 = mem[0,1,0,1] +; AVX2-NEXT: vpmulhuw %ymm6, %ymm5, %ymm5 ; AVX2-NEXT: vpaddw %ymm5, %ymm0, %ymm5 -; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm6 = ymm2[4],ymm5[4],ymm2[5],ymm5[5],ymm2[6],ymm5[6],ymm2[7],ymm5[7],ymm2[12],ymm5[12],ymm2[13],ymm5[13],ymm2[14],ymm5[14],ymm2[15],ymm5[15] -; AVX2-NEXT: vmovdqa {{.*#+}} ymm7 = [0,2,1,4,3,5,6,1,0,2,1,4,3,5,6,1] -; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm8 = ymm7[4],ymm2[4],ymm7[5],ymm2[5],ymm7[6],ymm2[6],ymm7[7],ymm2[7],ymm7[12],ymm2[12],ymm7[13],ymm2[13],ymm7[14],ymm2[14],ymm7[15],ymm2[15] -; AVX2-NEXT: vpsravd %ymm8, %ymm6, %ymm6 -; AVX2-NEXT: vpsrld $16, %ymm6, %ymm6 +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm7 = ymm2[4],ymm5[4],ymm2[5],ymm5[5],ymm2[6],ymm5[6],ymm2[7],ymm5[7],ymm2[12],ymm5[12],ymm2[13],ymm5[13],ymm2[14],ymm5[14],ymm2[15],ymm5[15] +; AVX2-NEXT: vpsravd %ymm4, %ymm7, %ymm7 +; AVX2-NEXT: vpsrld $16, %ymm7, %ymm7 +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm3 = ymm3[0],ymm2[0],ymm3[1],ymm2[1],ymm3[2],ymm2[2],ymm3[3],ymm2[3],ymm3[8],ymm2[8],ymm3[9],ymm2[9],ymm3[10],ymm2[10],ymm3[11],ymm2[11] ; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm2[0],ymm5[0],ymm2[1],ymm5[1],ymm2[2],ymm5[2],ymm2[3],ymm5[3],ymm2[8],ymm5[8],ymm2[9],ymm5[9],ymm2[10],ymm5[10],ymm2[11],ymm5[11] -; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm7 = ymm7[0],ymm2[0],ymm7[1],ymm2[1],ymm7[2],ymm2[2],ymm7[3],ymm2[3],ymm7[8],ymm2[8],ymm7[9],ymm2[9],ymm7[10],ymm2[10],ymm7[11],ymm2[11] -; AVX2-NEXT: vpsravd %ymm7, %ymm5, %ymm5 +; AVX2-NEXT: vpsravd %ymm3, %ymm5, %ymm5 ; AVX2-NEXT: vpsrld $16, %ymm5, %ymm5 -; AVX2-NEXT: vpackusdw %ymm6, %ymm5, %ymm5 +; AVX2-NEXT: vpackusdw %ymm7, %ymm5, %ymm5 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm5[1,2,3,4,5,6,7],ymm0[8],ymm5[9,10,11,12,13,14,15] ; AVX2-NEXT: vpsraw $15, %ymm1, %ymm5 +; AVX2-NEXT: vpmulhuw %ymm6, %ymm5, %ymm5 +; AVX2-NEXT: vpaddw %ymm5, %ymm1, %ymm5 ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm6 = ymm2[4],ymm5[4],ymm2[5],ymm5[5],ymm2[6],ymm5[6],ymm2[7],ymm5[7],ymm2[12],ymm5[12],ymm2[13],ymm5[13],ymm2[14],ymm5[14],ymm2[15],ymm5[15] -; AVX2-NEXT: vpsrlvd %ymm4, %ymm6, %ymm4 -; AVX2-NEXT: vpsrld $16, %ymm4, %ymm4 -; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm2[0],ymm5[0],ymm2[1],ymm5[1],ymm2[2],ymm5[2],ymm2[3],ymm5[3],ymm2[8],ymm5[8],ymm2[9],ymm5[9],ymm2[10],ymm5[10],ymm2[11],ymm5[11] -; AVX2-NEXT: vpsrlvd %ymm3, %ymm5, %ymm3 -; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3 -; AVX2-NEXT: vpackusdw %ymm4, %ymm3, %ymm3 -; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm3 -; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm3[4],ymm2[5],ymm3[5],ymm2[6],ymm3[6],ymm2[7],ymm3[7],ymm2[12],ymm3[12],ymm2[13],ymm3[13],ymm2[14],ymm3[14],ymm2[15],ymm3[15] -; AVX2-NEXT: vpsravd %ymm8, %ymm4, %ymm4 +; AVX2-NEXT: vpsravd %ymm4, %ymm6, %ymm4 ; AVX2-NEXT: vpsrld $16, %ymm4, %ymm4 -; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm3[0],ymm2[1],ymm3[1],ymm2[2],ymm3[2],ymm2[3],ymm3[3],ymm2[8],ymm3[8],ymm2[9],ymm3[9],ymm2[10],ymm3[10],ymm2[11],ymm3[11] -; AVX2-NEXT: vpsravd %ymm7, %ymm2, %ymm2 +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm5[0],ymm2[1],ymm5[1],ymm2[2],ymm5[2],ymm2[3],ymm5[3],ymm2[8],ymm5[8],ymm2[9],ymm5[9],ymm2[10],ymm5[10],ymm2[11],ymm5[11] +; AVX2-NEXT: vpsravd %ymm3, %ymm2, %ymm2 ; AVX2-NEXT: vpsrld $16, %ymm2, %ymm2 ; AVX2-NEXT: vpackusdw %ymm4, %ymm2, %ymm2 ; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1,2,3,4,5,6,7],ymm1[8],ymm2[9,10,11,12,13,14,15] @@ -982,11 +817,9 @@ define <32 x i16> @combine_vec_sdiv_by_pow2b_v32i16(<32 x i16> %x) { ; AVX512F-LABEL: combine_vec_sdiv_by_pow2b_v32i16: ; AVX512F: # %bb.0: ; AVX512F-NEXT: vpsraw $15, %ymm0, %ymm2 -; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero -; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm3 = [16,14,15,12,13,11,10,15,16,14,15,12,13,11,10,15] -; AVX512F-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3] -; AVX512F-NEXT: vpsrlvd %zmm3, %zmm2, %zmm2 -; AVX512F-NEXT: vpmovdw %zmm2, %ymm2 +; AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [1,4,2,16,8,32,64,2,1,4,2,16,8,32,64,2] +; AVX512F-NEXT: # ymm3 = mem[0,1,0,1] +; AVX512F-NEXT: vpmulhuw %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpaddw %ymm2, %ymm0, %ymm2 ; AVX512F-NEXT: vpmovsxwd %ymm2, %zmm2 ; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [0,2,1,4,3,5,6,1,0,2,1,4,3,5,6,1] @@ -995,9 +828,7 @@ define <32 x i16> @combine_vec_sdiv_by_pow2b_v32i16(<32 x i16> %x) { ; AVX512F-NEXT: vpmovdw %zmm2, %ymm2 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3,4,5,6,7],ymm0[8],ymm2[9,10,11,12,13,14,15] ; AVX512F-NEXT: vpsraw $15, %ymm1, %ymm2 -; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero -; AVX512F-NEXT: vpsrlvd %zmm3, %zmm2, %zmm2 -; AVX512F-NEXT: vpmovdw %zmm2, %ymm2 +; AVX512F-NEXT: vpmulhuw %ymm3, %ymm2, %ymm2 ; AVX512F-NEXT: vpaddw %ymm2, %ymm1, %ymm2 ; AVX512F-NEXT: vpmovsxwd %ymm2, %zmm2 ; AVX512F-NEXT: vpsravd %zmm4, %zmm2, %zmm2 @@ -2021,43 +1852,22 @@ define <16 x i8> @non_splat_minus_one_divisor_1(<16 x i8> %A) { ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: pxor %xmm2, %xmm2 -; SSE-NEXT: pxor %xmm3, %xmm3 -; SSE-NEXT: pcmpgtb %xmm0, %xmm3 -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psrlw $4, %xmm4 -; SSE-NEXT: pand {{.*}}(%rip), %xmm4 -; SSE-NEXT: movdqa {{.*#+}} xmm0 = [256,224,256,224,57600,57568,8416,8416] -; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psrlw $2, %xmm4 -; SSE-NEXT: pand {{.*}}(%rip), %xmm4 -; SSE-NEXT: paddb %xmm0, %xmm0 -; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 -; SSE-NEXT: movdqa %xmm3, %xmm4 -; SSE-NEXT: psrlw $1, %xmm4 -; SSE-NEXT: pand {{.*}}(%rip), %xmm4 -; SSE-NEXT: paddb %xmm0, %xmm0 -; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm3 -; SSE-NEXT: paddb %xmm1, %xmm3 -; SSE-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15] -; SSE-NEXT: movdqa %xmm4, %xmm5 -; SSE-NEXT: psraw $4, %xmm5 -; SSE-NEXT: movdqa {{.*#+}} xmm6 = [0,32,0,32,8192,8224,57376,57376] -; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm6[8],xmm0[9],xmm6[9],xmm0[10],xmm6[10],xmm0[11],xmm6[11],xmm0[12],xmm6[12],xmm0[13],xmm6[13],xmm0[14],xmm6[14],xmm0[15],xmm6[15] -; SSE-NEXT: pblendvb %xmm0, %xmm5, %xmm4 -; SSE-NEXT: movdqa %xmm4, %xmm5 -; SSE-NEXT: psraw $2, %xmm5 -; SSE-NEXT: paddw %xmm0, %xmm0 -; SSE-NEXT: pblendvb %xmm0, %xmm5, %xmm4 -; SSE-NEXT: movdqa %xmm4, %xmm5 -; SSE-NEXT: psraw $1, %xmm5 -; SSE-NEXT: paddw %xmm0, %xmm0 -; SSE-NEXT: pblendvb %xmm0, %xmm5, %xmm4 +; SSE-NEXT: pxor %xmm0, %xmm0 +; SSE-NEXT: pcmpgtb %xmm1, %xmm0 +; SSE-NEXT: pmovzxbw {{.*#+}} xmm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero +; SSE-NEXT: pmullw {{.*}}(%rip), %xmm4 ; SSE-NEXT: psrlw $8, %xmm4 -; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] +; SSE-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero +; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 +; SSE-NEXT: psrlw $8, %xmm0 +; SSE-NEXT: packuswb %xmm0, %xmm4 +; SSE-NEXT: paddb %xmm1, %xmm4 +; SSE-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm4[8],xmm3[9],xmm4[9],xmm3[10],xmm4[10],xmm3[11],xmm4[11],xmm3[12],xmm4[12],xmm3[13],xmm4[13],xmm3[14],xmm4[14],xmm3[15],xmm4[15] ; SSE-NEXT: movdqa %xmm3, %xmm5 ; SSE-NEXT: psraw $4, %xmm5 -; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1],xmm0[2],xmm6[2],xmm0[3],xmm6[3],xmm0[4],xmm6[4],xmm0[5],xmm6[5],xmm0[6],xmm6[6],xmm0[7],xmm6[7] +; SSE-NEXT: movdqa {{.*#+}} xmm6 = [0,32,0,32,8192,8224,57376,57376] +; SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm6[8],xmm0[9],xmm6[9],xmm0[10],xmm6[10],xmm0[11],xmm6[11],xmm0[12],xmm6[12],xmm0[13],xmm6[13],xmm0[14],xmm6[14],xmm0[15],xmm6[15] ; SSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm3, %xmm5 ; SSE-NEXT: psraw $2, %xmm5 @@ -2068,9 +1878,23 @@ define <16 x i8> @non_splat_minus_one_divisor_1(<16 x i8> %A) { ; SSE-NEXT: paddw %xmm0, %xmm0 ; SSE-NEXT: pblendvb %xmm0, %xmm5, %xmm3 ; SSE-NEXT: psrlw $8, %xmm3 -; SSE-NEXT: packuswb %xmm4, %xmm3 +; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] +; SSE-NEXT: movdqa %xmm4, %xmm5 +; SSE-NEXT: psraw $4, %xmm5 +; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1],xmm0[2],xmm6[2],xmm0[3],xmm6[3],xmm0[4],xmm6[4],xmm0[5],xmm6[5],xmm0[6],xmm6[6],xmm0[7],xmm6[7] +; SSE-NEXT: pblendvb %xmm0, %xmm5, %xmm4 +; SSE-NEXT: movdqa %xmm4, %xmm5 +; SSE-NEXT: psraw $2, %xmm5 +; SSE-NEXT: paddw %xmm0, %xmm0 +; SSE-NEXT: pblendvb %xmm0, %xmm5, %xmm4 +; SSE-NEXT: movdqa %xmm4, %xmm5 +; SSE-NEXT: psraw $1, %xmm5 +; SSE-NEXT: paddw %xmm0, %xmm0 +; SSE-NEXT: pblendvb %xmm0, %xmm5, %xmm4 +; SSE-NEXT: psrlw $8, %xmm4 +; SSE-NEXT: packuswb %xmm3, %xmm4 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,255,0,0,0,255,0,0,255,255,255,255,255,255,255] -; SSE-NEXT: pblendvb %xmm0, %xmm3, %xmm1 +; SSE-NEXT: pblendvb %xmm0, %xmm4, %xmm1 ; SSE-NEXT: psubb %xmm1, %xmm2 ; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,255,0,255,255,255,0,255,255,0,0,0,0,255,0,255] ; SSE-NEXT: pblendvb %xmm0, %xmm2, %xmm1 @@ -2081,18 +1905,14 @@ define <16 x i8> @non_splat_minus_one_divisor_1(<16 x i8> %A) { ; AVX1: # %bb.0: ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm2 -; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3 -; AVX1-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [256,224,256,224,57600,57568,8416,8416] -; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpsrlw $2, %xmm2, %xmm3 -; AVX1-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3 -; AVX1-NEXT: vpaddb %xmm4, %xmm4, %xmm4 -; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm3 -; AVX1-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3 -; AVX1-NEXT: vpaddb %xmm4, %xmm4, %xmm4 -; AVX1-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero +; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3 +; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] +; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero +; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2 +; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 +; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2 ; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm2 ; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8],xmm2[8],xmm0[9],xmm2[9],xmm0[10],xmm2[10],xmm0[11],xmm2[11],xmm0[12],xmm2[12],xmm0[13],xmm2[13],xmm0[14],xmm2[14],xmm0[15],xmm2[15] ; AVX1-NEXT: vpsraw $4, %xmm3, %xmm4 @@ -2129,18 +1949,11 @@ define <16 x i8> @non_splat_minus_one_divisor_1(<16 x i8> %A) { ; AVX2: # %bb.0: ; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm2 -; AVX2-NEXT: vpsrlw $4, %xmm2, %xmm3 -; AVX2-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3 -; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = [256,224,256,224,57600,57568,8416,8416] -; AVX2-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 -; AVX2-NEXT: vpsrlw $2, %xmm2, %xmm3 -; AVX2-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3 -; AVX2-NEXT: vpaddb %xmm4, %xmm4, %xmm4 -; AVX2-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 -; AVX2-NEXT: vpsrlw $1, %xmm2, %xmm3 -; AVX2-NEXT: vpand {{.*}}(%rip), %xmm3, %xmm3 -; AVX2-NEXT: vpaddb %xmm4, %xmm4, %xmm4 -; AVX2-NEXT: vpblendvb %xmm4, %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero +; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm2, %ymm2 +; AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 +; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3 +; AVX2-NEXT: vpackuswb %xmm3, %xmm2, %xmm2 ; AVX2-NEXT: vpaddb %xmm2, %xmm0, %xmm2 ; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8],xmm2[8],xmm0[9],xmm2[9],xmm0[10],xmm2[10],xmm0[11],xmm2[11],xmm0[12],xmm2[12],xmm0[13],xmm2[13],xmm0[14],xmm2[14],xmm0[15],xmm2[15] ; AVX2-NEXT: vpsraw $4, %xmm3, %xmm4 @@ -2171,6 +1984,7 @@ define <16 x i8> @non_splat_minus_one_divisor_1(<16 x i8> %A) { ; AVX2-NEXT: vpsubb %xmm0, %xmm1, %xmm1 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,0,255,255,255,0,255,255,0,0,0,0,255,0,255] ; AVX2-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; ; AVX512F-LABEL: non_splat_minus_one_divisor_1: diff --git a/test/CodeGen/X86/combine-shl.ll b/test/CodeGen/X86/combine-shl.ll index c037b0f0aa4b..1fc557f008fe 100644 --- a/test/CodeGen/X86/combine-shl.ll +++ b/test/CodeGen/X86/combine-shl.ll @@ -337,30 +337,7 @@ define <8 x i32> @combine_vec_shl_zext_lshr0(<8 x i16> %x) { define <8 x i32> @combine_vec_shl_zext_lshr1(<8 x i16> %x) { ; SSE2-LABEL: combine_vec_shl_zext_lshr1: ; SSE2: # %bb.0: -; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535,65535,65535,65535,0] -; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: pand %xmm1, %xmm2 -; SSE2-NEXT: psrlw $8, %xmm0 -; SSE2-NEXT: pandn %xmm0, %xmm1 -; SSE2-NEXT: por %xmm2, %xmm1 -; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,65535,65535,0,0,0,0,65535] -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pand %xmm0, %xmm2 -; SSE2-NEXT: psrlw $4, %xmm1 -; SSE2-NEXT: pandn %xmm1, %xmm0 -; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,0,0,65535,65535,0] -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pandn %xmm0, %xmm2 -; SSE2-NEXT: psrlw $2, %xmm0 -; SSE2-NEXT: pand %xmm1, %xmm0 -; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0] -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pandn %xmm0, %xmm2 -; SSE2-NEXT: psrlw $1, %xmm0 -; SSE2-NEXT: pand %xmm1, %xmm0 -; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] @@ -385,18 +362,7 @@ define <8 x i32> @combine_vec_shl_zext_lshr1(<8 x i16> %x) { ; ; SSE41-LABEL: combine_vec_shl_zext_lshr1: ; SSE41: # %bb.0: -; SSE41-NEXT: movdqa %xmm0, %xmm1 -; SSE41-NEXT: psrlw $8, %xmm1 -; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5,6],xmm1[7] -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: psrlw $4, %xmm0 -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6],xmm1[7] -; SSE41-NEXT: movdqa %xmm0, %xmm1 -; SSE41-NEXT: psrlw $2, %xmm1 -; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2],xmm0[3,4],xmm1[5,6],xmm0[7] -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: psrlw $1, %xmm0 -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] +; SSE41-NEXT: pmulhuw {{.*}}(%rip), %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero @@ -406,13 +372,9 @@ define <8 x i32> @combine_vec_shl_zext_lshr1(<8 x i16> %x) { ; ; AVX-LABEL: combine_vec_shl_zext_lshr1: ; AVX: # %bb.0: +; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,3,4,5,6,7,8] -; AVX-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 -; AVX-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] -; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 +; AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 ; AVX-NEXT: retq %1 = lshr <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8> %2 = zext <8 x i16> %1 to <8 x i32> diff --git a/test/CodeGen/X86/dagcombine-select.ll b/test/CodeGen/X86/dagcombine-select.ll index 2b05154676e6..1ef6cfdfd40a 100644 --- a/test/CodeGen/X86/dagcombine-select.ll +++ b/test/CodeGen/X86/dagcombine-select.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=x86_64-unknown-unknown -verify-machineinstrs < %s | FileCheck -enable-var-scope %s -; RUN: llc -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=+bmi < %s | FileCheck -check-prefix=BMI -enable-var-scope %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,NOBMI -enable-var-scope +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=+bmi | FileCheck %s -check-prefixes=CHECK,BMI -enable-var-scope define i32 @select_and1(i32 %x, i32 %y) { ; CHECK-LABEL: select_and1: @@ -283,14 +283,14 @@ define double @frem_constant_sel_constants(i1 %cond) { declare i64 @llvm.cttz.i64(i64, i1) define i64 @cttz_64_eq_select(i64 %v) nounwind { -; CHECK-LABEL: cttz_64_eq_select: -; CHECK: # %bb.0: -; CHECK-NEXT: bsfq %rdi, %rcx -; CHECK-NEXT: movq $-1, %rax -; CHECK-NEXT: cmovneq %rcx, %rax -; CHECK-NEXT: addq $6, %rax -; CHECK-NEXT: retq - +; NOBMI-LABEL: cttz_64_eq_select: +; NOBMI: # %bb.0: +; NOBMI-NEXT: bsfq %rdi, %rcx +; NOBMI-NEXT: movq $-1, %rax +; NOBMI-NEXT: cmovneq %rcx, %rax +; NOBMI-NEXT: addq $6, %rax +; NOBMI-NEXT: retq +; ; BMI-LABEL: cttz_64_eq_select: ; BMI: # %bb.0: ; BMI-NEXT: tzcntq %rdi, %rcx @@ -298,6 +298,7 @@ define i64 @cttz_64_eq_select(i64 %v) nounwind { ; BMI-NEXT: cmovaeq %rcx, %rax ; BMI-NEXT: addq $6, %rax ; BMI-NEXT: retq + %cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true) %tobool = icmp eq i64 %v, 0 %.op = add nuw nsw i64 %cnt, 6 @@ -306,14 +307,14 @@ define i64 @cttz_64_eq_select(i64 %v) nounwind { } define i64 @cttz_64_ne_select(i64 %v) nounwind { -; CHECK-LABEL: cttz_64_ne_select: -; CHECK: # %bb.0: -; CHECK-NEXT: bsfq %rdi, %rcx -; CHECK-NEXT: movq $-1, %rax -; CHECK-NEXT: cmovneq %rcx, %rax -; CHECK-NEXT: addq $6, %rax -; CHECK-NEXT: retq - +; NOBMI-LABEL: cttz_64_ne_select: +; NOBMI: # %bb.0: +; NOBMI-NEXT: bsfq %rdi, %rcx +; NOBMI-NEXT: movq $-1, %rax +; NOBMI-NEXT: cmovneq %rcx, %rax +; NOBMI-NEXT: addq $6, %rax +; NOBMI-NEXT: retq +; ; BMI-LABEL: cttz_64_ne_select: ; BMI: # %bb.0: ; BMI-NEXT: tzcntq %rdi, %rcx @@ -321,6 +322,7 @@ define i64 @cttz_64_ne_select(i64 %v) nounwind { ; BMI-NEXT: cmovaeq %rcx, %rax ; BMI-NEXT: addq $6, %rax ; BMI-NEXT: retq + %cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true) %tobool = icmp ne i64 %v, 0 %.op = add nuw nsw i64 %cnt, 6 @@ -330,14 +332,14 @@ define i64 @cttz_64_ne_select(i64 %v) nounwind { declare i32 @llvm.cttz.i32(i32, i1) define i32 @cttz_32_eq_select(i32 %v) nounwind { -; CHECK-LABEL: cttz_32_eq_select: -; CHECK: # %bb.0: -; CHECK-NEXT: bsfl %edi, %ecx -; CHECK-NEXT: movl $-1, %eax -; CHECK-NEXT: cmovnel %ecx, %eax -; CHECK-NEXT: addl $6, %eax -; CHECK-NEXT: retq - +; NOBMI-LABEL: cttz_32_eq_select: +; NOBMI: # %bb.0: +; NOBMI-NEXT: bsfl %edi, %ecx +; NOBMI-NEXT: movl $-1, %eax +; NOBMI-NEXT: cmovnel %ecx, %eax +; NOBMI-NEXT: addl $6, %eax +; NOBMI-NEXT: retq +; ; BMI-LABEL: cttz_32_eq_select: ; BMI: # %bb.0: ; BMI-NEXT: tzcntl %edi, %ecx @@ -345,6 +347,7 @@ define i32 @cttz_32_eq_select(i32 %v) nounwind { ; BMI-NEXT: cmovael %ecx, %eax ; BMI-NEXT: addl $6, %eax ; BMI-NEXT: retq + %cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true) %tobool = icmp eq i32 %v, 0 %.op = add nuw nsw i32 %cnt, 6 @@ -353,14 +356,14 @@ define i32 @cttz_32_eq_select(i32 %v) nounwind { } define i32 @cttz_32_ne_select(i32 %v) nounwind { -; CHECK-LABEL: cttz_32_ne_select: -; CHECK: # %bb.0: -; CHECK-NEXT: bsfl %edi, %ecx -; CHECK-NEXT: movl $-1, %eax -; CHECK-NEXT: cmovnel %ecx, %eax -; CHECK-NEXT: addl $6, %eax -; CHECK-NEXT: retq - +; NOBMI-LABEL: cttz_32_ne_select: +; NOBMI: # %bb.0: +; NOBMI-NEXT: bsfl %edi, %ecx +; NOBMI-NEXT: movl $-1, %eax +; NOBMI-NEXT: cmovnel %ecx, %eax +; NOBMI-NEXT: addl $6, %eax +; NOBMI-NEXT: retq +; ; BMI-LABEL: cttz_32_ne_select: ; BMI: # %bb.0: ; BMI-NEXT: tzcntl %edi, %ecx @@ -368,6 +371,7 @@ define i32 @cttz_32_ne_select(i32 %v) nounwind { ; BMI-NEXT: cmovael %ecx, %eax ; BMI-NEXT: addl $6, %eax ; BMI-NEXT: retq + %cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true) %tobool = icmp ne i32 %v, 0 %.op = add nuw nsw i32 %cnt, 6 diff --git a/test/CodeGen/X86/fast-isel-fold-mem.ll b/test/CodeGen/X86/fast-isel-fold-mem.ll index 5686484ef935..1c5171926c4b 100644 --- a/test/CodeGen/X86/fast-isel-fold-mem.ll +++ b/test/CodeGen/X86/fast-isel-fold-mem.ll @@ -1,10 +1,13 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin | FileCheck %s define i64 @fold_load(i64* %a, i64 %b) { -; CHECK-LABEL: fold_load -; CHECK: addq (%rdi), %rsi -; CHECK-NEXT: movq %rsi, %rax +; CHECK-LABEL: fold_load: +; CHECK: ## %bb.0: +; CHECK-NEXT: addq (%rdi), %rsi +; CHECK-NEXT: movq %rsi, %rax +; CHECK-NEXT: retq %1 = load i64, i64* %a, align 8 %2 = add i64 %1, %b ret i64 %2 diff --git a/test/CodeGen/X86/fast-isel-select.ll b/test/CodeGen/X86/fast-isel-select.ll index 7b3c99f13cca..cf459f85b33e 100644 --- a/test/CodeGen/X86/fast-isel-select.ll +++ b/test/CodeGen/X86/fast-isel-select.ll @@ -1,14 +1,23 @@ -; RUN: llc -mtriple x86_64-apple-darwin -O0 -o - < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-apple-darwin -O0 | FileCheck %s + ; Make sure we only use the less significant bit of the value that feeds the ; select. Otherwise, we may account for a non-zero value whereas the ; lsb is zero. ; <rdar://problem/15651765> -; CHECK-LABEL: fastisel_select: -; CHECK: subb {{%[a-z0-9]+}}, [[RES:%[a-z0-9]+]] -; CHECK: testb $1, [[RES]] -; CHECK: cmovnel %edi, %esi define i32 @fastisel_select(i1 %exchSub2211_, i1 %trunc_8766) { +; CHECK-LABEL: fastisel_select: +; CHECK: ## %bb.0: +; CHECK-NEXT: movb %sil, %al +; CHECK-NEXT: movb %dil, %cl +; CHECK-NEXT: xorl %esi, %esi +; CHECK-NEXT: subb %al, %cl +; CHECK-NEXT: testb $1, %cl +; CHECK-NEXT: movl $1204476887, %edi ## imm = 0x47CADBD7 +; CHECK-NEXT: cmovnel %edi, %esi +; CHECK-NEXT: movl %esi, %eax +; CHECK-NEXT: retq %shuffleInternal15257_8932 = sub i1 %exchSub2211_, %trunc_8766 %counter_diff1345 = select i1 %shuffleInternal15257_8932, i32 1204476887, i32 0 ret i32 %counter_diff1345 diff --git a/test/CodeGen/X86/fast-isel-sext-zext.ll b/test/CodeGen/X86/fast-isel-sext-zext.ll index 5e54c98b0d14..82ed6c72ebca 100644 --- a/test/CodeGen/X86/fast-isel-sext-zext.ll +++ b/test/CodeGen/X86/fast-isel-sext-zext.ll @@ -9,7 +9,6 @@ define i8 @test1(i8 %x) nounwind { ; X32-NEXT: andb $1, %al ; X32-NEXT: negb %al ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test1: ; X64: ## %bb.0: @@ -17,7 +16,6 @@ define i8 @test1(i8 %x) nounwind { ; X64-NEXT: negb %dil ; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %z = trunc i8 %x to i1 %u = sext i1 %z to i8 ret i8 %u @@ -32,7 +30,6 @@ define i16 @test2(i16 %x) nounwind { ; X32-NEXT: movsbl %al, %eax ; X32-NEXT: ## kill: def $ax killed $ax killed $eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test2: ; X64: ## %bb.0: @@ -41,7 +38,6 @@ define i16 @test2(i16 %x) nounwind { ; X64-NEXT: movsbl %dil, %eax ; X64-NEXT: ## kill: def $ax killed $ax killed $eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %z = trunc i16 %x to i1 %u = sext i1 %z to i16 ret i16 %u @@ -55,7 +51,6 @@ define i32 @test3(i32 %x) nounwind { ; X32-NEXT: negb %al ; X32-NEXT: movsbl %al, %eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test3: ; X64: ## %bb.0: @@ -63,7 +58,6 @@ define i32 @test3(i32 %x) nounwind { ; X64-NEXT: negb %dil ; X64-NEXT: movsbl %dil, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %z = trunc i32 %x to i1 %u = sext i1 %z to i32 ret i32 %u @@ -77,7 +71,6 @@ define i32 @test4(i32 %x) nounwind { ; X32-NEXT: negb %al ; X32-NEXT: movsbl %al, %eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test4: ; X64: ## %bb.0: @@ -85,7 +78,6 @@ define i32 @test4(i32 %x) nounwind { ; X64-NEXT: negb %dil ; X64-NEXT: movsbl %dil, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %z = trunc i32 %x to i1 %u = sext i1 %z to i32 ret i32 %u @@ -97,14 +89,12 @@ define i8 @test5(i8 %x) nounwind { ; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: andb $1, %al ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test5: ; X64: ## %bb.0: ; X64-NEXT: andb $1, %dil ; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %z = trunc i8 %x to i1 %u = zext i1 %z to i8 ret i8 %u @@ -118,7 +108,6 @@ define i16 @test6(i16 %x) nounwind { ; X32-NEXT: movzbl %al, %eax ; X32-NEXT: ## kill: def $ax killed $ax killed $eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test6: ; X64: ## %bb.0: @@ -126,7 +115,6 @@ define i16 @test6(i16 %x) nounwind { ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: ## kill: def $ax killed $ax killed $eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %z = trunc i16 %x to i1 %u = zext i1 %z to i16 ret i16 %u @@ -139,14 +127,12 @@ define i32 @test7(i32 %x) nounwind { ; X32-NEXT: andb $1, %al ; X32-NEXT: movzbl %al, %eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test7: ; X64: ## %bb.0: ; X64-NEXT: andb $1, %dil ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %z = trunc i32 %x to i1 %u = zext i1 %z to i32 ret i32 %u @@ -159,14 +145,12 @@ define i32 @test8(i32 %x) nounwind { ; X32-NEXT: andb $1, %al ; X32-NEXT: movzbl %al, %eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test8: ; X64: ## %bb.0: ; X64-NEXT: andb $1, %dil ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %z = trunc i32 %x to i1 %u = zext i1 %z to i32 ret i32 %u @@ -178,14 +162,12 @@ define i16 @test9(i8 %x) nounwind { ; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: ## kill: def $ax killed $ax killed $eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test9: ; X64: ## %bb.0: ; X64-NEXT: movsbl %dil, %eax ; X64-NEXT: ## kill: def $ax killed $ax killed $eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = sext i8 %x to i16 ret i16 %u } @@ -195,13 +177,11 @@ define i32 @test10(i8 %x) nounwind { ; X32: ## %bb.0: ; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test10: ; X64: ## %bb.0: ; X64-NEXT: movsbl %dil, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = sext i8 %x to i32 ret i32 %u } @@ -213,13 +193,11 @@ define i64 @test11(i8 %x) nounwind { ; X32-NEXT: movl %eax, %edx ; X32-NEXT: sarl $31, %edx ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test11: ; X64: ## %bb.0: ; X64-NEXT: movsbq %dil, %rax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = sext i8 %x to i64 ret i64 %u } @@ -230,14 +208,12 @@ define i16 @test12(i8 %x) nounwind { ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: ## kill: def $ax killed $ax killed $eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test12: ; X64: ## %bb.0: ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: ## kill: def $ax killed $ax killed $eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = zext i8 %x to i16 ret i16 %u } @@ -247,13 +223,11 @@ define i32 @test13(i8 %x) nounwind { ; X32: ## %bb.0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test13: ; X64: ## %bb.0: ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = zext i8 %x to i32 ret i32 %u } @@ -264,13 +238,11 @@ define i64 @test14(i8 %x) nounwind { ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: xorl %edx, %edx ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test14: ; X64: ## %bb.0: ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = zext i8 %x to i64 ret i64 %u } @@ -280,13 +252,11 @@ define i32 @test15(i16 %x) nounwind { ; X32: ## %bb.0: ; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test15: ; X64: ## %bb.0: ; X64-NEXT: movswl %di, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = sext i16 %x to i32 ret i32 %u } @@ -298,13 +268,11 @@ define i64 @test16(i16 %x) nounwind { ; X32-NEXT: movl %eax, %edx ; X32-NEXT: sarl $31, %edx ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test16: ; X64: ## %bb.0: ; X64-NEXT: movswq %di, %rax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = sext i16 %x to i64 ret i64 %u } @@ -314,13 +282,11 @@ define i32 @test17(i16 %x) nounwind { ; X32: ## %bb.0: ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test17: ; X64: ## %bb.0: ; X64-NEXT: movzwl %di, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = zext i16 %x to i32 ret i32 %u } @@ -331,13 +297,11 @@ define i64 @test18(i16 %x) nounwind { ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X32-NEXT: xorl %edx, %edx ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test18: ; X64: ## %bb.0: ; X64-NEXT: movzwl %di, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = zext i16 %x to i64 ret i64 %u } @@ -349,13 +313,11 @@ define i64 @test19(i32 %x) nounwind { ; X32-NEXT: movl %eax, %edx ; X32-NEXT: sarl $31, %edx ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test19: ; X64: ## %bb.0: ; X64-NEXT: movslq %edi, %rax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = sext i32 %x to i64 ret i64 %u } @@ -366,13 +328,11 @@ define i64 @test20(i32 %x) nounwind { ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: xorl %edx, %edx ; X32-NEXT: retl -; X32-NEXT: ## -- End function ; ; X64-LABEL: test20: ; X64: ## %bb.0: ; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq -; X64-NEXT: ## -- End function %u = zext i32 %x to i64 ret i64 %u } diff --git a/test/CodeGen/X86/flags-copy-lowering.mir b/test/CodeGen/X86/flags-copy-lowering.mir index 54ce02aaca58..d5991754d40b 100644 --- a/test/CodeGen/X86/flags-copy-lowering.mir +++ b/test/CodeGen/X86/flags-copy-lowering.mir @@ -90,6 +90,18 @@ call void @foo() ret i64 0 } + + define i32 @test_existing_setcc(i64 %a, i64 %b) { + entry: + call void @foo() + ret i32 0 + } + + define i32 @test_existing_setcc_memory(i64 %a, i64 %b) { + entry: + call void @foo() + ret i32 0 + } ... --- name: test_branch @@ -936,3 +948,110 @@ body: | ; CHECK: %8:gr64 = CMOVE64rr %0, %1, implicit killed $eflags ... +--- +name: test_existing_setcc +# CHECK-LABEL: name: test_existing_setcc +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } +body: | + bb.0: + successors: %bb.1, %bb.2, %bb.3 + liveins: $rdi, $rsi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY $rsi + CMP64rr %0, %1, implicit-def $eflags + %2:gr8 = SETAr implicit $eflags + %3:gr8 = SETAEr implicit $eflags + %4:gr64 = COPY $eflags + ; CHECK: CMP64rr %0, %1, implicit-def $eflags + ; CHECK-NEXT: %[[A_REG:[^:]*]]:gr8 = SETAr implicit $eflags + ; CHECK-NEXT: %[[AE_REG:[^:]*]]:gr8 = SETAEr implicit $eflags + ; CHECK-NOT: COPY{{( killed)?}} $eflags + + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + + $eflags = COPY %4 + JA_1 %bb.1, implicit $eflags + JB_1 %bb.2, implicit $eflags + JMP_1 %bb.3 + ; CHECK-NOT: $eflags = + ; + ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags + ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags + ; CHECK-SAME: {{$[[:space:]]}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: {{.*$}} + ; CHECK-SAME: {{$[[:space:]]}} + ; CHECK-NEXT: TEST8rr %[[AE_REG]], %[[AE_REG]], implicit-def $eflags + ; CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags + ; CHECK-NEXT: JMP_1 %bb.3 + + bb.1: + %5:gr32 = MOV32ri64 42 + $eax = COPY %5 + RET 0, $eax + + bb.2: + %6:gr32 = MOV32ri64 43 + $eax = COPY %6 + RET 0, $eax + + bb.3: + %7:gr32 = MOV32r0 implicit-def dead $eflags + $eax = COPY %7 + RET 0, $eax + +... +--- +name: test_existing_setcc_memory +# CHECK-LABEL: name: test_existing_setcc_memory +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } +body: | + bb.0: + successors: %bb.1, %bb.2 + liveins: $rdi, $rsi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY $rsi + CMP64rr %0, %1, implicit-def $eflags + SETEm %0, 1, $noreg, -16, $noreg, implicit $eflags + %2:gr64 = COPY $eflags + ; CHECK: CMP64rr %0, %1, implicit-def $eflags + ; We cannot reuse this SETE because it stores the flag directly to memory, + ; so we have two SETEs here. FIXME: It'd be great if something could fold + ; these automatically. If not, maybe we want to unfold SETcc instructions + ; writing to memory so we can reuse them. + ; CHECK-NEXT: SETEm {{.*}} implicit $eflags + ; CHECK-NEXT: %[[E_REG:[^:]*]]:gr8 = SETEr implicit $eflags + ; CHECK-NOT: COPY{{( killed)?}} $eflags + + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + + $eflags = COPY %2 + JE_1 %bb.1, implicit $eflags + JMP_1 %bb.2 + ; CHECK-NOT: $eflags = + ; + ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags + ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags + ; CHECK-NEXT: JMP_1 %bb.2 + + bb.1: + %3:gr32 = MOV32ri64 42 + $eax = COPY %3 + RET 0, $eax + + bb.2: + %4:gr32 = MOV32ri64 43 + $eax = COPY %4 + RET 0, $eax + +... diff --git a/test/CodeGen/X86/lea-opt.ll b/test/CodeGen/X86/lea-opt.ll index b285a4ed5224..6899babf31de 100644 --- a/test/CodeGen/X86/lea-opt.ll +++ b/test/CodeGen/X86/lea-opt.ll @@ -307,3 +307,154 @@ sw.bb.2: ; preds = %entry sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry ret void } + +define i32 @test5(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test5: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl %esi, %esi +; CHECK-NEXT: subl %esi, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i32 %y, -2 + %add = add nsw i32 %mul, %x + ret i32 %add +} + +define i32 @test6(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test6: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $esi killed $esi def $rsi +; CHECK-NEXT: leal (%rsi,%rsi,2), %eax +; CHECK-NEXT: subl %eax, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i32 %y, -3 + %add = add nsw i32 %mul, %x + ret i32 %add +} + +define i32 @test7(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test7: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: shll $2, %esi +; CHECK-NEXT: subl %esi, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i32 %y, -4 + %add = add nsw i32 %mul, %x + ret i32 %add +} + +define i32 @test8(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $esi killed $esi def $rsi +; CHECK-NEXT: leal (,%rsi,4), %eax +; CHECK-NEXT: subl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = shl nsw i32 %y, 2 + %sub = sub nsw i32 %mul, %x + ret i32 %sub +} + + +define i32 @test9(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test9: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addl %esi, %esi +; CHECK-NEXT: subl %esi, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i32 -2, %y + %add = add nsw i32 %x, %mul + ret i32 %add +} + +define i32 @test10(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test10: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $esi killed $esi def $rsi +; CHECK-NEXT: leal (%rsi,%rsi,2), %eax +; CHECK-NEXT: subl %eax, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i32 -3, %y + %add = add nsw i32 %x, %mul + ret i32 %add +} + +define i32 @test11(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test11: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: shll $2, %esi +; CHECK-NEXT: subl %esi, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i32 -4, %y + %add = add nsw i32 %x, %mul + ret i32 %add +} + +define i32 @test12(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test12: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $esi killed $esi def $rsi +; CHECK-NEXT: leal (,%rsi,4), %eax +; CHECK-NEXT: subl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i32 4, %y + %sub = sub nsw i32 %mul, %x + ret i32 %sub +} + +define i64 @test13(i64 %x, i64 %y) #0 { +; CHECK-LABEL: test13: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: shlq $2, %rsi +; CHECK-NEXT: subq %rsi, %rdi +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i64 -4, %y + %add = add nsw i64 %x, %mul + ret i64 %add +} + +define i32 @test14(i32 %x, i32 %y) #0 { +; CHECK-LABEL: test14: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $esi killed $esi def $rsi +; CHECK-NEXT: leal (,%rsi,4), %eax +; CHECK-NEXT: subl %edi, %eax +; CHECK-NEXT: retq +entry: + %mul = mul nsw i32 4, %y + %sub = sub nsw i32 %mul, %x + ret i32 %sub +} + +define zeroext i16 @test15(i16 zeroext %x, i16 zeroext %y) #0 { +; CHECK-LABEL: test15: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: shll $3, %esi +; CHECK-NEXT: subl %esi, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq +entry: + %conv = zext i16 %x to i32 + %conv1 = zext i16 %y to i32 + %mul = mul nsw i32 -8, %conv1 + %add = add nsw i32 %conv, %mul + %conv2 = trunc i32 %add to i16 + ret i16 %conv2 +} + +attributes #0 = { norecurse nounwind optsize readnone uwtable} diff --git a/test/CodeGen/X86/machine-outliner-tailcalls.ll b/test/CodeGen/X86/machine-outliner-tailcalls.ll index 6f28354c386b..71ebade623cf 100644 --- a/test/CodeGen/X86/machine-outliner-tailcalls.ll +++ b/test/CodeGen/X86/machine-outliner-tailcalls.ll @@ -1,4 +1,4 @@ -; RUN: llc -enable-machine-outliner -mtriple=x86_64-apple-darwin < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=x86_64-apple-darwin < %s | FileCheck %s @x = common local_unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/X86/mul-constant-i16.ll b/test/CodeGen/X86/mul-constant-i16.ll index 737bcc7c864d..cf367ecbb98e 100644 --- a/test/CodeGen/X86/mul-constant-i16.ll +++ b/test/CodeGen/X86/mul-constant-i16.ll @@ -766,6 +766,50 @@ define i16 @test_mul_by_520(i16 %x) { ret i16 %mul } +define i16 @test_mul_by_neg10(i16 %x) { +; X86-LABEL: test_mul_by_neg10: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: addl %eax, %eax +; X86-NEXT: leal (%eax,%eax,4), %eax +; X86-NEXT: negl %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax +; X86-NEXT: retl +; +; X64-LABEL: test_mul_by_neg10: +; X64: # %bb.0: +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: addl %edi, %edi +; X64-NEXT: leal (%rdi,%rdi,4), %eax +; X64-NEXT: negl %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NEXT: retq + %mul = mul nsw i16 %x, -10 + ret i16 %mul +} + +define i16 @test_mul_by_neg36(i16 %x) { +; X86-LABEL: test_mul_by_neg36: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: shll $2, %eax +; X86-NEXT: leal (%eax,%eax,8), %eax +; X86-NEXT: negl %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax +; X86-NEXT: retl +; +; X64-LABEL: test_mul_by_neg36: +; X64: # %bb.0: +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: shll $2, %edi +; X64-NEXT: leal (%rdi,%rdi,8), %eax +; X64-NEXT: negl %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NEXT: retq + %mul = mul nsw i16 %x, -36 + ret i16 %mul +} + ; (x*9+42)*(x*5+2) define i16 @test_mul_spec(i16 %x) nounwind { ; X86-LABEL: test_mul_spec: diff --git a/test/CodeGen/X86/mul-constant-i32.ll b/test/CodeGen/X86/mul-constant-i32.ll index 356d5a00abf6..04f867bb4e16 100644 --- a/test/CodeGen/X86/mul-constant-i32.ll +++ b/test/CodeGen/X86/mul-constant-i32.ll @@ -1997,6 +1997,118 @@ define i32 @test_mul_by_520(i32 %x) { ret i32 %mul } +define i32 @test_mul_by_neg10(i32 %x) { +; X86-LABEL: test_mul_by_neg10: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: addl %eax, %eax +; X86-NEXT: leal (%eax,%eax,4), %eax +; X86-NEXT: negl %eax +; X86-NEXT: retl +; +; X64-HSW-LABEL: test_mul_by_neg10: +; X64-HSW: # %bb.0: +; X64-HSW-NEXT: # kill: def $edi killed $edi def $rdi +; X64-HSW-NEXT: addl %edi, %edi # sched: [1:0.25] +; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] +; X64-HSW-NEXT: negl %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [7:1.00] +; +; X64-JAG-LABEL: test_mul_by_neg10: +; X64-JAG: # %bb.0: +; X64-JAG-NEXT: # kill: def $edi killed $edi def $rdi +; X64-JAG-NEXT: addl %edi, %edi # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [2:1.00] +; X64-JAG-NEXT: negl %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_neg10: +; X86-NOOPT: # %bb.0: +; X86-NOOPT-NEXT: imull $-10, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_neg10: +; HSW-NOOPT: # %bb.0: +; HSW-NOOPT-NEXT: imull $-10, %edi, %eax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [7:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_neg10: +; JAG-NOOPT: # %bb.0: +; JAG-NOOPT-NEXT: imull $-10, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_neg10: +; X64-SLM: # %bb.0: +; X64-SLM-NEXT: # kill: def $edi killed $edi def $rdi +; X64-SLM-NEXT: addl %edi, %edi # sched: [1:0.50] +; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] +; X64-SLM-NEXT: negl %eax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_neg10: +; SLM-NOOPT: # %bb.0: +; SLM-NOOPT-NEXT: imull $-10, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] + %mul = mul nsw i32 %x, -10 + ret i32 %mul +} + +define i32 @test_mul_by_neg36(i32 %x) { +; X86-LABEL: test_mul_by_neg36: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: shll $2, %eax +; X86-NEXT: leal (%eax,%eax,8), %eax +; X86-NEXT: negl %eax +; X86-NEXT: retl +; +; X64-HSW-LABEL: test_mul_by_neg36: +; X64-HSW: # %bb.0: +; X64-HSW-NEXT: # kill: def $edi killed $edi def $rdi +; X64-HSW-NEXT: shll $2, %edi # sched: [1:0.50] +; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] +; X64-HSW-NEXT: negl %eax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [7:1.00] +; +; X64-JAG-LABEL: test_mul_by_neg36: +; X64-JAG: # %bb.0: +; X64-JAG-NEXT: # kill: def $edi killed $edi def $rdi +; X64-JAG-NEXT: shll $2, %edi # sched: [1:0.50] +; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [2:1.00] +; X64-JAG-NEXT: negl %eax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_neg36: +; X86-NOOPT: # %bb.0: +; X86-NOOPT-NEXT: imull $-36, {{[0-9]+}}(%esp), %eax +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_neg36: +; HSW-NOOPT: # %bb.0: +; HSW-NOOPT-NEXT: imull $-36, %edi, %eax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [7:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_neg36: +; JAG-NOOPT: # %bb.0: +; JAG-NOOPT-NEXT: imull $-36, %edi, %eax # sched: [3:1.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_neg36: +; X64-SLM: # %bb.0: +; X64-SLM-NEXT: # kill: def $edi killed $edi def $rdi +; X64-SLM-NEXT: shll $2, %edi # sched: [1:1.00] +; X64-SLM-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] +; X64-SLM-NEXT: negl %eax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_neg36: +; SLM-NOOPT: # %bb.0: +; SLM-NOOPT-NEXT: imull $-36, %edi, %eax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] + %mul = mul nsw i32 %x, -36 + ret i32 %mul +} + ; (x*9+42)*(x*5+2) define i32 @test_mul_spec(i32 %x) nounwind { ; X86-LABEL: test_mul_spec: diff --git a/test/CodeGen/X86/mul-constant-i64.ll b/test/CodeGen/X86/mul-constant-i64.ll index 332ad7f01299..761ca67ab31b 100644 --- a/test/CodeGen/X86/mul-constant-i64.ll +++ b/test/CodeGen/X86/mul-constant-i64.ll @@ -2107,6 +2107,144 @@ define i64 @test_mul_by_520(i64 %x) { ret i64 %mul } +define i64 @test_mul_by_neg10(i64 %x) { +; X86-LABEL: test_mul_by_neg10: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl $-10, %edx +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: subl %ecx, %edx +; X86-NEXT: leal (%esi,%esi,4), %ecx +; X86-NEXT: addl %ecx, %ecx +; X86-NEXT: subl %ecx, %edx +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-HSW-LABEL: test_mul_by_neg10: +; X64-HSW: # %bb.0: +; X64-HSW-NEXT: addq %rdi, %rdi # sched: [1:0.25] +; X64-HSW-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:0.50] +; X64-HSW-NEXT: negq %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [7:1.00] +; +; X64-JAG-LABEL: test_mul_by_neg10: +; X64-JAG: # %bb.0: +; X64-JAG-NEXT: addq %rdi, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [2:1.00] +; X64-JAG-NEXT: negq %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_neg10: +; X86-NOOPT: # %bb.0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: movl $-10, %edx +; X86-NOOPT-NEXT: movl %ecx, %eax +; X86-NOOPT-NEXT: mull %edx +; X86-NOOPT-NEXT: subl %ecx, %edx +; X86-NOOPT-NEXT: imull $-10, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_neg10: +; HSW-NOOPT: # %bb.0: +; HSW-NOOPT-NEXT: imulq $-10, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [7:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_neg10: +; JAG-NOOPT: # %bb.0: +; JAG-NOOPT-NEXT: imulq $-10, %rdi, %rax # sched: [6:4.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_neg10: +; X64-SLM: # %bb.0: +; X64-SLM-NEXT: addq %rdi, %rdi # sched: [1:0.50] +; X64-SLM-NEXT: leaq (%rdi,%rdi,4), %rax # sched: [1:1.00] +; X64-SLM-NEXT: negq %rax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_neg10: +; SLM-NOOPT: # %bb.0: +; SLM-NOOPT-NEXT: imulq $-10, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] + %mul = mul nsw i64 %x, -10 + ret i64 %mul +} + +define i64 @test_mul_by_neg36(i64 %x) { +; X86-LABEL: test_mul_by_neg36: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: .cfi_def_cfa_offset 8 +; X86-NEXT: .cfi_offset %esi, -8 +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl $-36, %edx +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: mull %edx +; X86-NEXT: subl %ecx, %edx +; X86-NEXT: leal (%esi,%esi,8), %ecx +; X86-NEXT: shll $2, %ecx +; X86-NEXT: subl %ecx, %edx +; X86-NEXT: popl %esi +; X86-NEXT: .cfi_def_cfa_offset 4 +; X86-NEXT: retl +; +; X64-HSW-LABEL: test_mul_by_neg36: +; X64-HSW: # %bb.0: +; X64-HSW-NEXT: shlq $2, %rdi # sched: [1:0.50] +; X64-HSW-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:0.50] +; X64-HSW-NEXT: negq %rax # sched: [1:0.25] +; X64-HSW-NEXT: retq # sched: [7:1.00] +; +; X64-JAG-LABEL: test_mul_by_neg36: +; X64-JAG: # %bb.0: +; X64-JAG-NEXT: shlq $2, %rdi # sched: [1:0.50] +; X64-JAG-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [2:1.00] +; X64-JAG-NEXT: negq %rax # sched: [1:0.50] +; X64-JAG-NEXT: retq # sched: [4:1.00] +; +; X86-NOOPT-LABEL: test_mul_by_neg36: +; X86-NOOPT: # %bb.0: +; X86-NOOPT-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: movl $-36, %edx +; X86-NOOPT-NEXT: movl %ecx, %eax +; X86-NOOPT-NEXT: mull %edx +; X86-NOOPT-NEXT: subl %ecx, %edx +; X86-NOOPT-NEXT: imull $-36, {{[0-9]+}}(%esp), %ecx +; X86-NOOPT-NEXT: addl %ecx, %edx +; X86-NOOPT-NEXT: retl +; +; HSW-NOOPT-LABEL: test_mul_by_neg36: +; HSW-NOOPT: # %bb.0: +; HSW-NOOPT-NEXT: imulq $-36, %rdi, %rax # sched: [3:1.00] +; HSW-NOOPT-NEXT: retq # sched: [7:1.00] +; +; JAG-NOOPT-LABEL: test_mul_by_neg36: +; JAG-NOOPT: # %bb.0: +; JAG-NOOPT-NEXT: imulq $-36, %rdi, %rax # sched: [6:4.00] +; JAG-NOOPT-NEXT: retq # sched: [4:1.00] +; +; X64-SLM-LABEL: test_mul_by_neg36: +; X64-SLM: # %bb.0: +; X64-SLM-NEXT: shlq $2, %rdi # sched: [1:1.00] +; X64-SLM-NEXT: leaq (%rdi,%rdi,8), %rax # sched: [1:1.00] +; X64-SLM-NEXT: negq %rax # sched: [1:0.50] +; X64-SLM-NEXT: retq # sched: [4:1.00] +; +; SLM-NOOPT-LABEL: test_mul_by_neg36: +; SLM-NOOPT: # %bb.0: +; SLM-NOOPT-NEXT: imulq $-36, %rdi, %rax # sched: [3:1.00] +; SLM-NOOPT-NEXT: retq # sched: [4:1.00] + %mul = mul nsw i64 %x, -36 + ret i64 %mul +} + ; (x*9+42)*(x*5+2) define i64 @test_mul_spec(i64 %x) nounwind { ; X86-LABEL: test_mul_spec: diff --git a/test/CodeGen/X86/pku.ll b/test/CodeGen/X86/pku.ll index 96ee97341749..6031bafb0972 100644 --- a/test/CodeGen/X86/pku.ll +++ b/test/CodeGen/X86/pku.ll @@ -26,17 +26,11 @@ define void @test_x86_wrpkru(i32 %src) { } define i32 @test_x86_rdpkru() { -; X86-LABEL: test_x86_rdpkru: -; X86: ## %bb.0: -; X86-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9] -; X86-NEXT: rdpkru ## encoding: [0x0f,0x01,0xee] -; X86-NEXT: retl ## encoding: [0xc3] -; -; X64-LABEL: test_x86_rdpkru: -; X64: ## %bb.0: -; X64-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9] -; X64-NEXT: rdpkru ## encoding: [0x0f,0x01,0xee] -; X64-NEXT: retq ## encoding: [0xc3] +; CHECK-LABEL: test_x86_rdpkru: +; CHECK: ## %bb.0: +; CHECK-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9] +; CHECK-NEXT: rdpkru ## encoding: [0x0f,0x01,0xee] +; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3] %res = call i32 @llvm.x86.rdpkru() ret i32 %res } diff --git a/test/CodeGen/X86/pmaddubsw.ll b/test/CodeGen/X86/pmaddubsw.ll new file mode 100644 index 000000000000..d44315af2c6b --- /dev/null +++ b/test/CodeGen/X86/pmaddubsw.ll @@ -0,0 +1,553 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX256,AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX256,AVX512,AVX512F +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX,AVX256,AVX512,AVX512BW + +; NOTE: We're testing with loads because ABI lowering creates a concat_vectors that extract_vector_elt creation can see through. +; This would require the combine to recreate the concat_vectors. +define <8 x i16> @pmaddubsw_128(<16 x i8>* %Aptr, <16 x i8>* %Bptr) { +; SSE-LABEL: pmaddubsw_128: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rsi), %xmm0 +; SSE-NEXT: pmaddubsw (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: pmaddubsw_128: +; AVX: # %bb.0: +; AVX-NEXT: vmovdqa (%rsi), %xmm0 +; AVX-NEXT: vpmaddubsw (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %A = load <16 x i8>, <16 x i8>* %Aptr + %B = load <16 x i8>, <16 x i8>* %Bptr + %A_even = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %A_odd = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %B_even = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %B_odd = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %A_even_ext = sext <8 x i8> %A_even to <8 x i32> + %B_even_ext = zext <8 x i8> %B_even to <8 x i32> + %A_odd_ext = sext <8 x i8> %A_odd to <8 x i32> + %B_odd_ext = zext <8 x i8> %B_odd to <8 x i32> + %even_mul = mul <8 x i32> %A_even_ext, %B_even_ext + %odd_mul = mul <8 x i32> %A_odd_ext, %B_odd_ext + %add = add <8 x i32> %even_mul, %odd_mul + %cmp_max = icmp sgt <8 x i32> %add, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %max = select <8 x i1> %cmp_max, <8 x i32> %add, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %cmp_min = icmp slt <8 x i32> %max, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %min = select <8 x i1> %cmp_min, <8 x i32> %max, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %trunc = trunc <8 x i32> %min to <8 x i16> + ret <8 x i16> %trunc +} + +define <16 x i16> @pmaddubsw_256(<32 x i8>* %Aptr, <32 x i8>* %Bptr) { +; SSE-LABEL: pmaddubsw_256: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rsi), %xmm0 +; SSE-NEXT: movdqa 16(%rsi), %xmm1 +; SSE-NEXT: pmaddubsw (%rdi), %xmm0 +; SSE-NEXT: pmaddubsw 16(%rdi), %xmm1 +; SSE-NEXT: retq +; +; AVX1-LABEL: pmaddubsw_256: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovdqa (%rdi), %ymm0 +; AVX1-NEXT: vmovdqa (%rsi), %ymm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vpmaddubsw %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpmaddubsw %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX256-LABEL: pmaddubsw_256: +; AVX256: # %bb.0: +; AVX256-NEXT: vmovdqa (%rsi), %ymm0 +; AVX256-NEXT: vpmaddubsw (%rdi), %ymm0, %ymm0 +; AVX256-NEXT: retq + %A = load <32 x i8>, <32 x i8>* %Aptr + %B = load <32 x i8>, <32 x i8>* %Bptr + %A_even = shufflevector <32 x i8> %A, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> + %A_odd = shufflevector <32 x i8> %A, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> + %B_even = shufflevector <32 x i8> %B, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> + %B_odd = shufflevector <32 x i8> %B, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> + %A_even_ext = sext <16 x i8> %A_even to <16 x i32> + %B_even_ext = zext <16 x i8> %B_even to <16 x i32> + %A_odd_ext = sext <16 x i8> %A_odd to <16 x i32> + %B_odd_ext = zext <16 x i8> %B_odd to <16 x i32> + %even_mul = mul <16 x i32> %A_even_ext, %B_even_ext + %odd_mul = mul <16 x i32> %A_odd_ext, %B_odd_ext + %add = add <16 x i32> %even_mul, %odd_mul + %cmp_max = icmp sgt <16 x i32> %add, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %max = select <16 x i1> %cmp_max, <16 x i32> %add, <16 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %cmp_min = icmp slt <16 x i32> %max, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %min = select <16 x i1> %cmp_min, <16 x i32> %max, <16 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %trunc = trunc <16 x i32> %min to <16 x i16> + ret <16 x i16> %trunc +} + +define <64 x i16> @pmaddubsw_512(<128 x i8>* %Aptr, <128 x i8>* %Bptr) { +; SSE-LABEL: pmaddubsw_512: +; SSE: # %bb.0: +; SSE-NEXT: movdqa 112(%rdx), %xmm0 +; SSE-NEXT: movdqa 96(%rdx), %xmm1 +; SSE-NEXT: movdqa 80(%rdx), %xmm2 +; SSE-NEXT: movdqa 64(%rdx), %xmm3 +; SSE-NEXT: movdqa (%rdx), %xmm4 +; SSE-NEXT: movdqa 16(%rdx), %xmm5 +; SSE-NEXT: movdqa 32(%rdx), %xmm6 +; SSE-NEXT: movdqa 48(%rdx), %xmm7 +; SSE-NEXT: pmaddubsw (%rsi), %xmm4 +; SSE-NEXT: pmaddubsw 16(%rsi), %xmm5 +; SSE-NEXT: pmaddubsw 32(%rsi), %xmm6 +; SSE-NEXT: pmaddubsw 48(%rsi), %xmm7 +; SSE-NEXT: pmaddubsw 64(%rsi), %xmm3 +; SSE-NEXT: pmaddubsw 80(%rsi), %xmm2 +; SSE-NEXT: pmaddubsw 96(%rsi), %xmm1 +; SSE-NEXT: pmaddubsw 112(%rsi), %xmm0 +; SSE-NEXT: movdqa %xmm0, 112(%rdi) +; SSE-NEXT: movdqa %xmm1, 96(%rdi) +; SSE-NEXT: movdqa %xmm2, 80(%rdi) +; SSE-NEXT: movdqa %xmm3, 64(%rdi) +; SSE-NEXT: movdqa %xmm7, 48(%rdi) +; SSE-NEXT: movdqa %xmm6, 32(%rdi) +; SSE-NEXT: movdqa %xmm5, 16(%rdi) +; SSE-NEXT: movdqa %xmm4, (%rdi) +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: retq +; +; AVX1-LABEL: pmaddubsw_512: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovdqa (%rdi), %ymm0 +; AVX1-NEXT: vmovdqa 32(%rdi), %ymm1 +; AVX1-NEXT: vmovdqa 64(%rdi), %ymm2 +; AVX1-NEXT: vmovdqa 96(%rdi), %ymm8 +; AVX1-NEXT: vmovdqa (%rsi), %ymm4 +; AVX1-NEXT: vmovdqa 32(%rsi), %ymm5 +; AVX1-NEXT: vmovdqa 64(%rsi), %ymm6 +; AVX1-NEXT: vmovdqa 96(%rsi), %ymm9 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm7 +; AVX1-NEXT: vpmaddubsw %xmm3, %xmm7, %xmm3 +; AVX1-NEXT: vpmaddubsw %xmm0, %xmm4, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm5, %xmm4 +; AVX1-NEXT: vpmaddubsw %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpmaddubsw %xmm1, %xmm5, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm4 +; AVX1-NEXT: vpmaddubsw %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpmaddubsw %xmm2, %xmm6, %xmm2 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 +; AVX1-NEXT: vextractf128 $1, %ymm8, %xmm3 +; AVX1-NEXT: vextractf128 $1, %ymm9, %xmm4 +; AVX1-NEXT: vpmaddubsw %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpmaddubsw %xmm8, %xmm9, %xmm4 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm4, %ymm3 +; AVX1-NEXT: retq +; +; AVX2-LABEL: pmaddubsw_512: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovdqa (%rsi), %ymm0 +; AVX2-NEXT: vmovdqa 32(%rsi), %ymm1 +; AVX2-NEXT: vmovdqa 64(%rsi), %ymm2 +; AVX2-NEXT: vmovdqa 96(%rsi), %ymm3 +; AVX2-NEXT: vpmaddubsw (%rdi), %ymm0, %ymm0 +; AVX2-NEXT: vpmaddubsw 32(%rdi), %ymm1, %ymm1 +; AVX2-NEXT: vpmaddubsw 64(%rdi), %ymm2, %ymm2 +; AVX2-NEXT: vpmaddubsw 96(%rdi), %ymm3, %ymm3 +; AVX2-NEXT: retq +; +; AVX512F-LABEL: pmaddubsw_512: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqa (%rsi), %ymm0 +; AVX512F-NEXT: vmovdqa 32(%rsi), %ymm1 +; AVX512F-NEXT: vmovdqa 64(%rsi), %ymm2 +; AVX512F-NEXT: vmovdqa 96(%rsi), %ymm3 +; AVX512F-NEXT: vpmaddubsw (%rdi), %ymm0, %ymm0 +; AVX512F-NEXT: vpmaddubsw 32(%rdi), %ymm1, %ymm1 +; AVX512F-NEXT: vpmaddubsw 64(%rdi), %ymm2, %ymm2 +; AVX512F-NEXT: vpmaddubsw 96(%rdi), %ymm3, %ymm3 +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: pmaddubsw_512: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm0 +; AVX512BW-NEXT: vmovdqa64 64(%rsi), %zmm1 +; AVX512BW-NEXT: vpmaddubsw (%rdi), %zmm0, %zmm0 +; AVX512BW-NEXT: vpmaddubsw 64(%rdi), %zmm1, %zmm1 +; AVX512BW-NEXT: retq + %A = load <128 x i8>, <128 x i8>* %Aptr + %B = load <128 x i8>, <128 x i8>* %Bptr + %A_even = shufflevector <128 x i8> %A, <128 x i8> undef, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62, i32 64, i32 66, i32 68, i32 70, i32 72, i32 74, i32 76, i32 78, i32 80, i32 82, i32 84, i32 86, i32 88, i32 90, i32 92, i32 94, i32 96, i32 98, i32 100, i32 102, i32 104, i32 106, i32 108, i32 110, i32 112, i32 114, i32 116, i32 118, i32 120, i32 122, i32 124, i32 126> + %A_odd = shufflevector <128 x i8> %A, <128 x i8> undef, <64 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 33, i32 35, i32 37, i32 39, i32 41, i32 43, i32 45, i32 47, i32 49, i32 51, i32 53, i32 55, i32 57, i32 59, i32 61, i32 63, i32 65, i32 67, i32 69, i32 71, i32 73, i32 75, i32 77, i32 79, i32 81, i32 83, i32 85, i32 87, i32 89, i32 91, i32 93, i32 95, i32 97, i32 99, i32 101, i32 103, i32 105, i32 107, i32 109, i32 111, i32 113, i32 115, i32 117, i32 119, i32 121, i32 123, i32 125, i32 127> + %B_even = shufflevector <128 x i8> %B, <128 x i8> undef, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62, i32 64, i32 66, i32 68, i32 70, i32 72, i32 74, i32 76, i32 78, i32 80, i32 82, i32 84, i32 86, i32 88, i32 90, i32 92, i32 94, i32 96, i32 98, i32 100, i32 102, i32 104, i32 106, i32 108, i32 110, i32 112, i32 114, i32 116, i32 118, i32 120, i32 122, i32 124, i32 126> + %B_odd = shufflevector <128 x i8> %B, <128 x i8> undef, <64 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 33, i32 35, i32 37, i32 39, i32 41, i32 43, i32 45, i32 47, i32 49, i32 51, i32 53, i32 55, i32 57, i32 59, i32 61, i32 63, i32 65, i32 67, i32 69, i32 71, i32 73, i32 75, i32 77, i32 79, i32 81, i32 83, i32 85, i32 87, i32 89, i32 91, i32 93, i32 95, i32 97, i32 99, i32 101, i32 103, i32 105, i32 107, i32 109, i32 111, i32 113, i32 115, i32 117, i32 119, i32 121, i32 123, i32 125, i32 127> + %A_even_ext = sext <64 x i8> %A_even to <64 x i32> + %B_even_ext = zext <64 x i8> %B_even to <64 x i32> + %A_odd_ext = sext <64 x i8> %A_odd to <64 x i32> + %B_odd_ext = zext <64 x i8> %B_odd to <64 x i32> + %even_mul = mul <64 x i32> %A_even_ext, %B_even_ext + %odd_mul = mul <64 x i32> %A_odd_ext, %B_odd_ext + %add = add <64 x i32> %even_mul, %odd_mul + %cmp_max = icmp sgt <64 x i32> %add, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %max = select <64 x i1> %cmp_max, <64 x i32> %add, <64 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %cmp_min = icmp slt <64 x i32> %max, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %min = select <64 x i1> %cmp_min, <64 x i32> %max, <64 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %trunc = trunc <64 x i32> %min to <64 x i16> + ret <64 x i16> %trunc +} + +define <8 x i16> @pmaddubsw_swapped_indices(<16 x i8>* %Aptr, <16 x i8>* %Bptr) { +; SSE-LABEL: pmaddubsw_swapped_indices: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rsi), %xmm0 +; SSE-NEXT: pmaddubsw (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: pmaddubsw_swapped_indices: +; AVX: # %bb.0: +; AVX-NEXT: vmovdqa (%rsi), %xmm0 +; AVX-NEXT: vpmaddubsw (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %A = load <16 x i8>, <16 x i8>* %Aptr + %B = load <16 x i8>, <16 x i8>* %Bptr + %A_even = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14> ;indices aren't all even + %A_odd = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 0, i32 3, i32 4, i32 7, i32 8, i32 11, i32 12, i32 15> ;indices aren't all odd + %B_even = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14> ;same indices as A + %B_odd = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 0, i32 3, i32 4, i32 7, i32 8, i32 11, i32 12, i32 15> ;same indices as A + %A_even_ext = sext <8 x i8> %A_even to <8 x i32> + %B_even_ext = zext <8 x i8> %B_even to <8 x i32> + %A_odd_ext = sext <8 x i8> %A_odd to <8 x i32> + %B_odd_ext = zext <8 x i8> %B_odd to <8 x i32> + %even_mul = mul <8 x i32> %A_even_ext, %B_even_ext + %odd_mul = mul <8 x i32> %A_odd_ext, %B_odd_ext + %add = add <8 x i32> %even_mul, %odd_mul + %cmp_max = icmp sgt <8 x i32> %add, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %max = select <8 x i1> %cmp_max, <8 x i32> %add, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %cmp_min = icmp slt <8 x i32> %max, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %min = select <8 x i1> %cmp_min, <8 x i32> %max, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %trunc = trunc <8 x i32> %min to <8 x i16> + ret <8 x i16> %trunc +} + +define <8 x i16> @pmaddubsw_swapped_extend(<16 x i8>* %Aptr, <16 x i8>* %Bptr) { +; SSE-LABEL: pmaddubsw_swapped_extend: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rdi), %xmm0 +; SSE-NEXT: pmaddubsw (%rsi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: pmaddubsw_swapped_extend: +; AVX: # %bb.0: +; AVX-NEXT: vmovdqa (%rdi), %xmm0 +; AVX-NEXT: vpmaddubsw (%rsi), %xmm0, %xmm0 +; AVX-NEXT: retq + %A = load <16 x i8>, <16 x i8>* %Aptr + %B = load <16 x i8>, <16 x i8>* %Bptr + %A_even = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %A_odd = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %B_even = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %B_odd = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %A_even_ext = zext <8 x i8> %A_even to <8 x i32> + %B_even_ext = sext <8 x i8> %B_even to <8 x i32> + %A_odd_ext = zext <8 x i8> %A_odd to <8 x i32> + %B_odd_ext = sext <8 x i8> %B_odd to <8 x i32> + %even_mul = mul <8 x i32> %A_even_ext, %B_even_ext + %odd_mul = mul <8 x i32> %A_odd_ext, %B_odd_ext + %add = add <8 x i32> %even_mul, %odd_mul + %cmp_max = icmp sgt <8 x i32> %add, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %max = select <8 x i1> %cmp_max, <8 x i32> %add, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %cmp_min = icmp slt <8 x i32> %max, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %min = select <8 x i1> %cmp_min, <8 x i32> %max, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %trunc = trunc <8 x i32> %min to <8 x i16> + ret <8 x i16> %trunc +} + +define <8 x i16> @pmaddubsw_commuted_mul(<16 x i8>* %Aptr, <16 x i8>* %Bptr) { +; SSE-LABEL: pmaddubsw_commuted_mul: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rsi), %xmm0 +; SSE-NEXT: pmaddubsw (%rdi), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: pmaddubsw_commuted_mul: +; AVX: # %bb.0: +; AVX-NEXT: vmovdqa (%rsi), %xmm0 +; AVX-NEXT: vpmaddubsw (%rdi), %xmm0, %xmm0 +; AVX-NEXT: retq + %A = load <16 x i8>, <16 x i8>* %Aptr + %B = load <16 x i8>, <16 x i8>* %Bptr + %A_even = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %A_odd = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %B_even = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %B_odd = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %A_even_ext = sext <8 x i8> %A_even to <8 x i32> + %B_even_ext = zext <8 x i8> %B_even to <8 x i32> + %A_odd_ext = sext <8 x i8> %A_odd to <8 x i32> + %B_odd_ext = zext <8 x i8> %B_odd to <8 x i32> + %even_mul = mul <8 x i32> %B_even_ext, %A_even_ext + %odd_mul = mul <8 x i32> %A_odd_ext, %B_odd_ext + %add = add <8 x i32> %even_mul, %odd_mul + %cmp_max = icmp sgt <8 x i32> %add, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %max = select <8 x i1> %cmp_max, <8 x i32> %add, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %cmp_min = icmp slt <8 x i32> %max, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %min = select <8 x i1> %cmp_min, <8 x i32> %max, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %trunc = trunc <8 x i32> %min to <8 x i16> + ret <8 x i16> %trunc +} + +define <8 x i16> @pmaddubsw_bad_extend(<16 x i8>* %Aptr, <16 x i8>* %Bptr) { +; SSE-LABEL: pmaddubsw_bad_extend: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rdi), %xmm1 +; SSE-NEXT: movdqa (%rsi), %xmm0 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] +; SSE-NEXT: pand %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm1, %xmm3 +; SSE-NEXT: psllw $8, %xmm3 +; SSE-NEXT: psraw $8, %xmm3 +; SSE-NEXT: movdqa %xmm3, %xmm4 +; SSE-NEXT: pmulhw %xmm2, %xmm4 +; SSE-NEXT: pmullw %xmm2, %xmm3 +; SSE-NEXT: movdqa %xmm3, %xmm2 +; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] +; SSE-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] +; SSE-NEXT: psraw $8, %xmm0 +; SSE-NEXT: psrlw $8, %xmm1 +; SSE-NEXT: movdqa %xmm1, %xmm4 +; SSE-NEXT: pmulhw %xmm0, %xmm4 +; SSE-NEXT: pmullw %xmm0, %xmm1 +; SSE-NEXT: movdqa %xmm1, %xmm0 +; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3] +; SSE-NEXT: paddd %xmm2, %xmm0 +; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] +; SSE-NEXT: paddd %xmm3, %xmm1 +; SSE-NEXT: packssdw %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: pmaddubsw_bad_extend: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovdqa (%rdi), %xmm0 +; AVX1-NEXT: vmovdqa (%rsi), %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <8,10,12,14,u,u,u,u,u,u,u,u,u,u,u,u> +; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm3 +; AVX1-NEXT: vpmovsxbd %xmm3, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,u,u,u,u,u,u,u,u,u,u,u,u> +; AVX1-NEXT: vpshufb %xmm4, %xmm0, %xmm5 +; AVX1-NEXT: vpmovsxbd %xmm5, %xmm5 +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm2 +; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero +; AVX1-NEXT: vpmulld %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpshufb %xmm4, %xmm1, %xmm3 +; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero,xmm3[2],zero,zero,zero,xmm3[3],zero,zero,zero +; AVX1-NEXT: vpmulld %xmm3, %xmm5, %xmm3 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = <9,11,13,15,u,u,u,u,u,u,u,u,u,u,u,u> +; AVX1-NEXT: vpshufb %xmm4, %xmm0, %xmm5 +; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm5 = xmm5[0],zero,zero,zero,xmm5[1],zero,zero,zero,xmm5[2],zero,zero,zero,xmm5[3],zero,zero,zero +; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = <1,3,5,7,u,u,u,u,u,u,u,u,u,u,u,u> +; AVX1-NEXT: vpshufb %xmm6, %xmm0, %xmm0 +; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero +; AVX1-NEXT: vpshufb %xmm4, %xmm1, %xmm4 +; AVX1-NEXT: vpmovsxbd %xmm4, %xmm4 +; AVX1-NEXT: vpmulld %xmm4, %xmm5, %xmm4 +; AVX1-NEXT: vpaddd %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm6, %xmm1, %xmm1 +; AVX1-NEXT: vpmovsxbd %xmm1, %xmm1 +; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpaddd %xmm0, %xmm3, %xmm0 +; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: pmaddubsw_bad_extend: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovdqa (%rdi), %xmm0 +; AVX2-NEXT: vmovdqa (%rsi), %xmm1 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm3 +; AVX2-NEXT: vpmovsxbd %xmm3, %ymm3 +; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm2 +; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero,xmm2[4],zero,zero,zero,xmm2[5],zero,zero,zero,xmm2[6],zero,zero,zero,xmm2[7],zero,zero,zero +; AVX2-NEXT: vpmulld %ymm2, %ymm3, %ymm2 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u> +; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero +; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-NEXT: vpmovsxbd %xmm1, %ymm1 +; AVX2-NEXT: vpmulld %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpaddd %ymm0, %ymm2, %ymm0 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: pmaddubsw_bad_extend: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512-NEXT: vmovdqa (%rsi), %xmm1 +; AVX512-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; AVX512-NEXT: vpshufb %xmm2, %xmm0, %xmm3 +; AVX512-NEXT: vpmovsxbd %xmm3, %ymm3 +; AVX512-NEXT: vpshufb %xmm2, %xmm1, %xmm2 +; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero,xmm2[4],zero,zero,zero,xmm2[5],zero,zero,zero,xmm2[6],zero,zero,zero,xmm2[7],zero,zero,zero +; AVX512-NEXT: vpmulld %ymm2, %ymm3, %ymm2 +; AVX512-NEXT: vmovdqa {{.*#+}} xmm3 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u> +; AVX512-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero +; AVX512-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX512-NEXT: vpmovsxbd %xmm1, %ymm1 +; AVX512-NEXT: vpmulld %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vpaddd %ymm0, %ymm2, %ymm0 +; AVX512-NEXT: vpbroadcastd {{.*#+}} ymm1 = [4294934528,4294934528,4294934528,4294934528,4294934528,4294934528,4294934528,4294934528] +; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vpbroadcastd {{.*#+}} ymm1 = [32767,32767,32767,32767,32767,32767,32767,32767] +; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vpmovdw %zmm0, %ymm0 +; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %A = load <16 x i8>, <16 x i8>* %Aptr + %B = load <16 x i8>, <16 x i8>* %Bptr + %A_even = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %A_odd = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %B_even = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %B_odd = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %A_even_ext = sext <8 x i8> %A_even to <8 x i32> + %B_even_ext = zext <8 x i8> %B_even to <8 x i32> + %A_odd_ext = zext <8 x i8> %A_odd to <8 x i32> + %B_odd_ext = sext <8 x i8> %B_odd to <8 x i32> + %even_mul = mul <8 x i32> %A_even_ext, %B_even_ext + %odd_mul = mul <8 x i32> %A_odd_ext, %B_odd_ext + %add = add <8 x i32> %even_mul, %odd_mul + %cmp_max = icmp sgt <8 x i32> %add, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %max = select <8 x i1> %cmp_max, <8 x i32> %add, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %cmp_min = icmp slt <8 x i32> %max, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %min = select <8 x i1> %cmp_min, <8 x i32> %max, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %trunc = trunc <8 x i32> %min to <8 x i16> + ret <8 x i16> %trunc +} + +define <8 x i16> @pmaddubsw_bad_indices(<16 x i8>* %Aptr, <16 x i8>* %Bptr) { +; SSE-LABEL: pmaddubsw_bad_indices: +; SSE: # %bb.0: +; SSE-NEXT: movdqa (%rdi), %xmm1 +; SSE-NEXT: movdqa (%rsi), %xmm0 +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] +; SSE-NEXT: pand %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm1, %xmm3 +; SSE-NEXT: pshufb {{.*#+}} xmm3 = xmm3[u,1,u,2,u,5,u,6,u,9,u,10,u,13,u,14] +; SSE-NEXT: psraw $8, %xmm3 +; SSE-NEXT: movdqa %xmm3, %xmm4 +; SSE-NEXT: pmulhw %xmm2, %xmm4 +; SSE-NEXT: pmullw %xmm2, %xmm3 +; SSE-NEXT: movdqa %xmm3, %xmm2 +; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] +; SSE-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] +; SSE-NEXT: psrlw $8, %xmm0 +; SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[u,0,u,3,u,4,u,7,u,8,u,11,u,12,u,15] +; SSE-NEXT: psraw $8, %xmm1 +; SSE-NEXT: movdqa %xmm1, %xmm4 +; SSE-NEXT: pmulhw %xmm0, %xmm4 +; SSE-NEXT: pmullw %xmm0, %xmm1 +; SSE-NEXT: movdqa %xmm1, %xmm0 +; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3] +; SSE-NEXT: paddd %xmm2, %xmm0 +; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] +; SSE-NEXT: paddd %xmm3, %xmm1 +; SSE-NEXT: packssdw %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: pmaddubsw_bad_indices: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovdqa (%rdi), %xmm0 +; AVX1-NEXT: vmovdqa (%rsi), %xmm1 +; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = xmm0[9,10,13,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpmovsxbd %xmm2, %xmm2 +; AVX1-NEXT: vpshufb {{.*#+}} xmm3 = xmm0[1,2,5,6,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpmovsxbd %xmm3, %xmm3 +; AVX1-NEXT: vpshufb {{.*#+}} xmm4 = xmm1[8,10,12,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero +; AVX1-NEXT: vpmulld %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb {{.*#+}} xmm4 = xmm1[0,2,4,6,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero +; AVX1-NEXT: vpmulld %xmm4, %xmm3, %xmm3 +; AVX1-NEXT: vpshufb {{.*#+}} xmm4 = xmm0[8,11,12,15,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpmovsxbd %xmm4, %xmm4 +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,3,4,7,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0 +; AVX1-NEXT: vpshufb {{.*#+}} xmm5 = xmm1[9,11,13,15,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm5 = xmm5[0],zero,zero,zero,xmm5[1],zero,zero,zero,xmm5[2],zero,zero,zero,xmm5[3],zero,zero,zero +; AVX1-NEXT: vpmulld %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpaddd %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[1,3,5,7,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero +; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpaddd %xmm0, %xmm3, %xmm0 +; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: pmaddubsw_bad_indices: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovdqa (%rdi), %xmm0 +; AVX2-NEXT: vmovdqa (%rsi), %xmm1 +; AVX2-NEXT: vpshufb {{.*#+}} xmm2 = xmm0[1,2,5,6,9,10,13,14,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpmovsxbd %xmm2, %ymm2 +; AVX2-NEXT: vpshufb {{.*#+}} xmm3 = xmm1[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero,xmm3[2],zero,zero,zero,xmm3[3],zero,zero,zero,xmm3[4],zero,zero,zero,xmm3[5],zero,zero,zero,xmm3[6],zero,zero,zero,xmm3[7],zero,zero,zero +; AVX2-NEXT: vpmulld %ymm3, %ymm2, %ymm2 +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,3,4,7,8,11,12,15,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero +; AVX2-NEXT: vpmulld %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpaddd %ymm0, %ymm2, %ymm0 +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: pmaddubsw_bad_indices: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512-NEXT: vmovdqa (%rsi), %xmm1 +; AVX512-NEXT: vpshufb {{.*#+}} xmm2 = xmm0[1,2,5,6,9,10,13,14,u,u,u,u,u,u,u,u] +; AVX512-NEXT: vpmovsxbd %xmm2, %ymm2 +; AVX512-NEXT: vpshufb {{.*#+}} xmm3 = xmm1[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] +; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero,xmm3[2],zero,zero,zero,xmm3[3],zero,zero,zero,xmm3[4],zero,zero,zero,xmm3[5],zero,zero,zero,xmm3[6],zero,zero,zero,xmm3[7],zero,zero,zero +; AVX512-NEXT: vpmulld %ymm3, %ymm2, %ymm2 +; AVX512-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,3,4,7,8,11,12,15,u,u,u,u,u,u,u,u] +; AVX512-NEXT: vpmovsxbd %xmm0, %ymm0 +; AVX512-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u] +; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero +; AVX512-NEXT: vpmulld %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vpaddd %ymm0, %ymm2, %ymm0 +; AVX512-NEXT: vpbroadcastd {{.*#+}} ymm1 = [4294934528,4294934528,4294934528,4294934528,4294934528,4294934528,4294934528,4294934528] +; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vpbroadcastd {{.*#+}} ymm1 = [32767,32767,32767,32767,32767,32767,32767,32767] +; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vpmovdw %zmm0, %ymm0 +; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %A = load <16 x i8>, <16 x i8>* %Aptr + %B = load <16 x i8>, <16 x i8>* %Bptr + %A_even = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14> ;indices aren't all even + %A_odd = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 0, i32 3, i32 4, i32 7, i32 8, i32 11, i32 12, i32 15> ;indices aren't all odd + %B_even = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> ;different than A + %B_odd = shufflevector <16 x i8> %B, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> ;different than A + %A_even_ext = sext <8 x i8> %A_even to <8 x i32> + %B_even_ext = zext <8 x i8> %B_even to <8 x i32> + %A_odd_ext = sext <8 x i8> %A_odd to <8 x i32> + %B_odd_ext = zext <8 x i8> %B_odd to <8 x i32> + %even_mul = mul <8 x i32> %A_even_ext, %B_even_ext + %odd_mul = mul <8 x i32> %A_odd_ext, %B_odd_ext + %add = add <8 x i32> %even_mul, %odd_mul + %cmp_max = icmp sgt <8 x i32> %add, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %max = select <8 x i1> %cmp_max, <8 x i32> %add, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> + %cmp_min = icmp slt <8 x i32> %max, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %min = select <8 x i1> %cmp_min, <8 x i32> %max, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> + %trunc = trunc <8 x i32> %min to <8 x i16> + ret <8 x i16> %trunc +} diff --git a/test/CodeGen/X86/rem.ll b/test/CodeGen/X86/rem.ll index 672baa5c1bdc..5f2cc199bcf4 100644 --- a/test/CodeGen/X86/rem.ll +++ b/test/CodeGen/X86/rem.ll @@ -15,8 +15,8 @@ define i32 @test1(i32 %X) { ; CHECK-NEXT: addl %eax, %edx ; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: shll $8, %eax -; CHECK-NEXT: subl %edx, %eax -; CHECK-NEXT: subl %eax, %ecx +; CHECK-NEXT: subl %eax, %edx +; CHECK-NEXT: addl %edx, %ecx ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retl %tmp1 = srem i32 %X, 255 @@ -48,8 +48,8 @@ define i32 @test3(i32 %X) { ; CHECK-NEXT: shrl $7, %edx ; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: shll $8, %eax -; CHECK-NEXT: subl %edx, %eax -; CHECK-NEXT: subl %eax, %ecx +; CHECK-NEXT: subl %eax, %edx +; CHECK-NEXT: addl %edx, %ecx ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retl %tmp1 = urem i32 %X, 255 diff --git a/test/CodeGen/X86/rotate-extract-vector.ll b/test/CodeGen/X86/rotate-extract-vector.ll index 6059a76259ba..e2679dded8b5 100644 --- a/test/CodeGen/X86/rotate-extract-vector.ll +++ b/test/CodeGen/X86/rotate-extract-vector.ll @@ -12,10 +12,10 @@ define <4 x i32> @vroll_v4i32_extract_shl(<4 x i32> %i) { ; CHECK-LABEL: vroll_v4i32_extract_shl: ; CHECK: # %bb.0: -; CHECK-NEXT: vpslld $3, %xmm0, %xmm1 -; CHECK-NEXT: vpslld $10, %xmm0, %xmm0 -; CHECK-NEXT: vpsrld $25, %xmm1, %xmm1 -; CHECK-NEXT: vpor %xmm0, %xmm1, %xmm0 +; CHECK-NEXT: vpslld $3, %xmm0, %xmm0 +; CHECK-NEXT: vprold $7, %zmm0, %zmm0 +; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 +; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} %lhs_mul = shl <4 x i32> %i, <i32 3, i32 3, i32 3, i32 3> %rhs_mul = shl <4 x i32> %i, <i32 10, i32 10, i32 10, i32 10> @@ -25,20 +25,12 @@ define <4 x i32> @vroll_v4i32_extract_shl(<4 x i32> %i) { } define <4 x i64> @vrolq_v4i64_extract_shrl(<4 x i64> %i) nounwind { -; X86-LABEL: vrolq_v4i64_extract_shrl: -; X86: # %bb.0: -; X86-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; X86-NEXT: vprolq $24, %zmm0, %zmm0 -; X86-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 -; X86-NEXT: retl -; -; X64-LABEL: vrolq_v4i64_extract_shrl: -; X64: # %bb.0: -; X64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; X64-NEXT: vprolq $24, %zmm0, %zmm0 -; X64-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744073189457919,18446744073189457919,18446744073189457919,18446744073189457919] -; X64-NEXT: vpand %ymm1, %ymm0, %ymm0 -; X64-NEXT: retq +; CHECK-LABEL: vrolq_v4i64_extract_shrl: +; CHECK: # %bb.0: +; CHECK-NEXT: vpsrlq $5, %ymm0, %ymm0 +; CHECK-NEXT: vprolq $29, %zmm0, %zmm0 +; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 +; CHECK-NEXT: ret{{[l|q]}} %lhs_div = lshr <4 x i64> %i, <i64 40, i64 40, i64 40, i64 40> %rhs_div = lshr <4 x i64> %i, <i64 5, i64 5, i64 5, i64 5> %rhs_shift = shl <4 x i64> %rhs_div, <i64 29, i64 29, i64 29, i64 29> @@ -49,12 +41,10 @@ define <4 x i64> @vrolq_v4i64_extract_shrl(<4 x i64> %i) nounwind { define <8 x i32> @vroll_extract_mul(<8 x i32> %i) nounwind { ; CHECK-LABEL: vroll_extract_mul: ; CHECK: # %bb.0: -; CHECK-NEXT: vpbroadcastd {{.*#+}} ymm1 = [640,640,640,640,640,640,640,640] -; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm1 -; CHECK-NEXT: vpbroadcastd {{.*#+}} ymm2 = [10,10,10,10,10,10,10,10] -; CHECK-NEXT: vpmulld %ymm2, %ymm0, %ymm0 -; CHECK-NEXT: vpsrld $26, %ymm0, %ymm0 -; CHECK-NEXT: vpor %ymm0, %ymm1, %ymm0 +; CHECK-NEXT: vpbroadcastd {{.*#+}} ymm1 = [10,10,10,10,10,10,10,10] +; CHECK-NEXT: vpmulld %ymm1, %ymm0, %ymm0 +; CHECK-NEXT: vprold $6, %zmm0, %zmm0 +; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; CHECK-NEXT: ret{{[l|q]}} %lhs_mul = mul <8 x i32> %i, <i32 640, i32 640, i32 640, i32 640, i32 640, i32 640, i32 640, i32 640> %rhs_mul = mul <8 x i32> %i, <i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10> @@ -66,7 +56,7 @@ define <8 x i32> @vroll_extract_mul(<8 x i32> %i) nounwind { define <2 x i64> @vrolq_extract_udiv(<2 x i64> %i) nounwind { ; X86-LABEL: vrolq_extract_udiv: ; X86: # %bb.0: -; X86-NEXT: subl $60, %esp +; X86-NEXT: subl $44, %esp ; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; X86-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ; X86-NEXT: vmovss %xmm0, (%esp) @@ -85,53 +75,27 @@ define <2 x i64> @vrolq_extract_udiv(<2 x i64> %i) nounwind { ; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload ; X86-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0 ; X86-NEXT: vpinsrd $3, %edx, %xmm0, %xmm0 -; X86-NEXT: vmovdqu %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill -; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload -; X86-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) -; X86-NEXT: vmovss %xmm0, (%esp) -; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl $384, {{[0-9]+}}(%esp) # imm = 0x180 -; X86-NEXT: calll __udivdi3 -; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload -; X86-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) -; X86-NEXT: vextractps $2, %xmm0, (%esp) -; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl $384, {{[0-9]+}}(%esp) # imm = 0x180 -; X86-NEXT: vmovd %eax, %xmm0 -; X86-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0 -; X86-NEXT: vmovdqu %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill -; X86-NEXT: calll __udivdi3 -; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload -; X86-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0 -; X86-NEXT: vpinsrd $3, %edx, %xmm0, %xmm0 -; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 # 16-byte Reload -; X86-NEXT: vpsllq $57, %xmm1, %xmm1 -; X86-NEXT: vpor %xmm0, %xmm1, %xmm0 -; X86-NEXT: addl $60, %esp +; X86-NEXT: vprolq $57, %zmm0, %zmm0 +; X86-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 +; X86-NEXT: addl $44, %esp +; X86-NEXT: vzeroupper ; X86-NEXT: retl ; ; X64-LABEL: vrolq_extract_udiv: ; X64: # %bb.0: ; X64-NEXT: vpextrq $1, %xmm0, %rax -; X64-NEXT: movabsq $-6148914691236517205, %rsi # imm = 0xAAAAAAAAAAAAAAAB -; X64-NEXT: mulq %rsi -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rdx, %rax -; X64-NEXT: shrq %rax -; X64-NEXT: vmovq %rax, %xmm1 +; X64-NEXT: movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB +; X64-NEXT: mulq %rcx +; X64-NEXT: shrq %rdx +; X64-NEXT: vmovq %rdx, %xmm1 ; X64-NEXT: vmovq %xmm0, %rax -; X64-NEXT: mulq %rsi -; X64-NEXT: movq %rdx, %rax -; X64-NEXT: shrq %rax -; X64-NEXT: vmovq %rax, %xmm0 +; X64-NEXT: mulq %rcx +; X64-NEXT: shrq %rdx +; X64-NEXT: vmovq %rdx, %xmm0 ; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] -; X64-NEXT: shrq $8, %rcx -; X64-NEXT: vmovq %rcx, %xmm1 -; X64-NEXT: shrq $8, %rdx -; X64-NEXT: vmovq %rdx, %xmm2 -; X64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0] -; X64-NEXT: vpsllq $57, %xmm0, %xmm0 -; X64-NEXT: vpor %xmm1, %xmm0, %xmm0 +; X64-NEXT: vprolq $57, %zmm0, %zmm0 +; X64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 +; X64-NEXT: vzeroupper ; X64-NEXT: retq %lhs_div = udiv <2 x i64> %i, <i64 3, i64 3> %rhs_div = udiv <2 x i64> %i, <i64 384, i64 384> @@ -141,17 +105,23 @@ define <2 x i64> @vrolq_extract_udiv(<2 x i64> %i) nounwind { } define <4 x i32> @vrolw_extract_mul_with_mask(<4 x i32> %i) nounwind { -; CHECK-LABEL: vrolw_extract_mul_with_mask: -; CHECK: # %bb.0: -; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1152,1152,1152,1152] -; CHECK-NEXT: vpmulld %xmm1, %xmm0, %xmm1 -; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm2 = [9,9,9,9] -; CHECK-NEXT: vpmulld %xmm2, %xmm0, %xmm0 -; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm2 = [160,160,160,160] -; CHECK-NEXT: vpand %xmm2, %xmm1, %xmm1 -; CHECK-NEXT: vpsrld $25, %xmm0, %xmm0 -; CHECK-NEXT: vpor %xmm0, %xmm1, %xmm0 -; CHECK-NEXT: ret{{[l|q]}} +; X86-LABEL: vrolw_extract_mul_with_mask: +; X86: # %bb.0: +; X86-NEXT: vpbroadcastd {{.*#+}} xmm1 = [9,9,9,9] +; X86-NEXT: vpmulld %xmm1, %xmm0, %xmm0 +; X86-NEXT: vprold $7, %zmm0, %zmm0 +; X86-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-NEXT: vzeroupper +; X86-NEXT: retl +; +; X64-LABEL: vrolw_extract_mul_with_mask: +; X64: # %bb.0: +; X64-NEXT: vpbroadcastd {{.*#+}} xmm1 = [9,9,9,9] +; X64-NEXT: vpmulld %xmm1, %xmm0, %xmm0 +; X64-NEXT: vprold $7, %zmm0, %zmm0 +; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 +; X64-NEXT: vzeroupper +; X64-NEXT: retq %lhs_mul = mul <4 x i32> %i, <i32 1152, i32 1152, i32 1152, i32 1152> %rhs_mul = mul <4 x i32> %i, <i32 9, i32 9, i32 9, i32 9> %lhs_and = and <4 x i32> %lhs_mul, <i32 160, i32 160, i32 160, i32 160> diff --git a/test/CodeGen/X86/rotate-extract.ll b/test/CodeGen/X86/rotate-extract.ll index 6ce3db13e954..a1babd1d3cc3 100644 --- a/test/CodeGen/X86/rotate-extract.ll +++ b/test/CodeGen/X86/rotate-extract.ll @@ -24,9 +24,7 @@ define i64 @rolq_extract_shl(i64 %i) nounwind { ; X64-LABEL: rolq_extract_shl: ; X64: # %bb.0: ; X64-NEXT: leaq (,%rdi,8), %rax -; X64-NEXT: shlq $10, %rdi -; X64-NEXT: shrq $57, %rax -; X64-NEXT: orq %rdi, %rax +; X64-NEXT: rolq $7, %rax ; X64-NEXT: retq %lhs_mul = shl i64 %i, 3 %rhs_mul = shl i64 %i, 10 @@ -39,16 +37,17 @@ define i16 @rolw_extract_shrl(i16 %i) nounwind { ; X86-LABEL: rolw_extract_shrl: ; X86: # %bb.0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax -; X86-NEXT: rolw $9, %ax -; X86-NEXT: andl $61951, %eax # imm = 0xF1FF +; X86-NEXT: shrl $3, %eax +; X86-NEXT: rolw $12, %ax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; ; X64-LABEL: rolw_extract_shrl: ; X64: # %bb.0: -; X64-NEXT: rolw $9, %di -; X64-NEXT: andl $61951, %edi # imm = 0xF1FF -; X64-NEXT: movl %edi, %eax +; X64-NEXT: movzwl %di, %eax +; X64-NEXT: shrl $3, %eax +; X64-NEXT: rolw $12, %ax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: retq %lhs_div = lshr i16 %i, 7 %rhs_div = lshr i16 %i, 3 @@ -60,22 +59,16 @@ define i16 @rolw_extract_shrl(i16 %i) nounwind { define i32 @roll_extract_mul(i32 %i) nounwind { ; X86-LABEL: roll_extract_mul: ; X86: # %bb.0: -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: leal (%ecx,%ecx,8), %eax -; X86-NEXT: shll $7, %ecx -; X86-NEXT: leal (%ecx,%ecx,8), %ecx -; X86-NEXT: shrl $25, %eax -; X86-NEXT: orl %ecx, %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: leal (%eax,%eax,8), %eax +; X86-NEXT: roll $7, %eax ; X86-NEXT: retl ; ; X64-LABEL: roll_extract_mul: ; X64: # %bb.0: ; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: leal (%rdi,%rdi,8), %eax -; X64-NEXT: shll $7, %edi -; X64-NEXT: leal (%rdi,%rdi,8), %ecx -; X64-NEXT: shrl $25, %eax -; X64-NEXT: orl %ecx, %eax +; X64-NEXT: roll $7, %eax ; X64-NEXT: retq %lhs_mul = mul i32 %i, 9 %rhs_mul = mul i32 %i, 1152 @@ -89,11 +82,8 @@ define i8 @rolb_extract_udiv(i8 %i) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: imull $171, %eax, %eax -; X86-NEXT: movb %ah, %cl -; X86-NEXT: shlb $3, %cl -; X86-NEXT: andb $-16, %cl -; X86-NEXT: shrl $13, %eax -; X86-NEXT: orb %cl, %al +; X86-NEXT: shrl $9, %eax +; X86-NEXT: rolb $4, %al ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; @@ -101,12 +91,8 @@ define i8 @rolb_extract_udiv(i8 %i) nounwind { ; X64: # %bb.0: ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: imull $171, %eax, %eax -; X64-NEXT: movl %eax, %ecx -; X64-NEXT: shrl $8, %ecx -; X64-NEXT: shlb $3, %cl -; X64-NEXT: andb $-16, %cl -; X64-NEXT: shrl $13, %eax -; X64-NEXT: orb %cl, %al +; X64-NEXT: shrl $9, %eax +; X64-NEXT: rolb $4, %al ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq %lhs_div = udiv i8 %i, 3 @@ -139,12 +125,8 @@ define i64 @rolq_extract_mul_with_mask(i64 %i) nounwind { ; X64-LABEL: rolq_extract_mul_with_mask: ; X64: # %bb.0: ; X64-NEXT: leaq (%rdi,%rdi,8), %rax -; X64-NEXT: # kill: def $edi killed $edi killed $rdi def $rdi -; X64-NEXT: shll $7, %edi -; X64-NEXT: leal (%rdi,%rdi,8), %ecx -; X64-NEXT: movzbl %cl, %ecx -; X64-NEXT: shrq $57, %rax -; X64-NEXT: orq %rcx, %rax +; X64-NEXT: rolq $7, %rax +; X64-NEXT: movzbl %al, %eax ; X64-NEXT: retq %lhs_mul = mul i64 %i, 1152 %rhs_mul = mul i64 %i, 9 diff --git a/test/CodeGen/X86/signbit-shift.ll b/test/CodeGen/X86/signbit-shift.ll index cee647931bcb..1579a77a2e9b 100644 --- a/test/CodeGen/X86/signbit-shift.ll +++ b/test/CodeGen/X86/signbit-shift.ll @@ -156,9 +156,9 @@ define i32 @sext_ifneg(i32 %x) { define i32 @add_sext_ifneg(i32 %x) { ; CHECK-LABEL: add_sext_ifneg: ; CHECK: # %bb.0: -; CHECK-NEXT: shrl $31, %edi -; CHECK-NEXT: movl $42, %eax -; CHECK-NEXT: subl %edi, %eax +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi +; CHECK-NEXT: sarl $31, %edi +; CHECK-NEXT: leal 42(%rdi), %eax ; CHECK-NEXT: retq %c = icmp slt i32 %x, 0 %e = sext i1 %c to i32 @@ -169,9 +169,9 @@ define i32 @add_sext_ifneg(i32 %x) { define i32 @sel_ifneg_fval_bigger(i32 %x) { ; CHECK-LABEL: sel_ifneg_fval_bigger: ; CHECK: # %bb.0: -; CHECK-NEXT: shrl $31, %edi -; CHECK-NEXT: movl $42, %eax -; CHECK-NEXT: subl %edi, %eax +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi +; CHECK-NEXT: sarl $31, %edi +; CHECK-NEXT: leal 42(%rdi), %eax ; CHECK-NEXT: retq %c = icmp slt i32 %x, 0 %r = select i1 %c, i32 41, i32 42 @@ -231,9 +231,10 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) { define i32 @sub_lshr(i32 %x, i32 %y) { ; CHECK-LABEL: sub_lshr: ; CHECK: # %bb.0: -; CHECK-NEXT: shrl $31, %edi -; CHECK-NEXT: subl %edi, %esi -; CHECK-NEXT: movl %esi, %eax +; CHECK-NEXT: # kill: def $esi killed $esi def $rsi +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi +; CHECK-NEXT: sarl $31, %edi +; CHECK-NEXT: leal (%rdi,%rsi), %eax ; CHECK-NEXT: retq %sh = lshr i32 %x, 31 %r = sub i32 %y, %sh @@ -243,9 +244,8 @@ define i32 @sub_lshr(i32 %x, i32 %y) { define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: sub_lshr_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: psrld $31, %xmm0 -; CHECK-NEXT: psubd %xmm0, %xmm1 -; CHECK-NEXT: movdqa %xmm1, %xmm0 +; CHECK-NEXT: psrad $31, %xmm0 +; CHECK-NEXT: paddd %xmm1, %xmm0 ; CHECK-NEXT: retq %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %r = sub <4 x i32> %y, %sh @@ -255,9 +255,9 @@ define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) { define i32 @sub_const_op_lshr(i32 %x) { ; CHECK-LABEL: sub_const_op_lshr: ; CHECK: # %bb.0: -; CHECK-NEXT: shrl $31, %edi -; CHECK-NEXT: xorl $43, %edi -; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi +; CHECK-NEXT: sarl $31, %edi +; CHECK-NEXT: leal 43(%rdi), %eax ; CHECK-NEXT: retq %sh = lshr i32 %x, 31 %r = sub i32 43, %sh @@ -267,10 +267,8 @@ define i32 @sub_const_op_lshr(i32 %x) { define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) { ; CHECK-LABEL: sub_const_op_lshr_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: psrld $31, %xmm0 -; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42] -; CHECK-NEXT: psubd %xmm0, %xmm1 -; CHECK-NEXT: movdqa %xmm1, %xmm0 +; CHECK-NEXT: psrad $31, %xmm0 +; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh diff --git a/test/CodeGen/X86/speculative-load-hardening.ll b/test/CodeGen/X86/speculative-load-hardening.ll index 45b9c2f29807..55f7949c0da0 100644 --- a/test/CodeGen/X86/speculative-load-hardening.ll +++ b/test/CodeGen/X86/speculative-load-hardening.ll @@ -8,7 +8,7 @@ declare void @leak(i32 %v1, i32 %v2) declare void @sink(i32) -define i32 @test_trivial_entry_load(i32* %ptr) nounwind { +define i32 @test_trivial_entry_load(i32* %ptr) { ; X64-LABEL: test_trivial_entry_load: ; X64: # %bb.0: # %entry ; X64-NEXT: movq %rsp, %rcx @@ -29,12 +29,18 @@ entry: ret i32 %v } -define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %ptr2, i32** %ptr3) nounwind { +define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %ptr2, i32** %ptr3) { ; X64-LABEL: test_basic_conditions: ; X64: # %bb.0: # %entry ; X64-NEXT: pushq %r15 +; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: pushq %r14 +; X64-NEXT: .cfi_def_cfa_offset 24 ; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 32 +; X64-NEXT: .cfi_offset %rbx, -32 +; X64-NEXT: .cfi_offset %r14, -24 +; X64-NEXT: .cfi_offset %r15, -16 ; X64-NEXT: movq %rsp, %rax ; X64-NEXT: movq $-1, %rbx ; X64-NEXT: sarq $63, %rax @@ -50,10 +56,14 @@ define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %ptr ; X64-NEXT: shlq $47, %rax ; X64-NEXT: orq %rax, %rsp ; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 24 ; X64-NEXT: popq %r14 +; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: popq %r15 +; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq ; X64-NEXT: .LBB1_4: # %then2 +; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: movq %r8, %r15 ; X64-NEXT: cmovneq %rbx, %rax ; X64-NEXT: testl %edx, %edx @@ -90,19 +100,21 @@ define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %ptr ; ; X64-LFENCE-LABEL: test_basic_conditions: ; X64-LFENCE: # %bb.0: # %entry +; X64-LFENCE-NEXT: pushq %r14 +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 16 +; X64-LFENCE-NEXT: pushq %rbx +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 24 +; X64-LFENCE-NEXT: pushq %rax +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 32 +; X64-LFENCE-NEXT: .cfi_offset %rbx, -24 +; X64-LFENCE-NEXT: .cfi_offset %r14, -16 ; X64-LFENCE-NEXT: testl %edi, %edi ; X64-LFENCE-NEXT: jne .LBB1_6 ; X64-LFENCE-NEXT: # %bb.1: # %then1 ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: testl %esi, %esi -; X64-LFENCE-NEXT: je .LBB1_2 -; X64-LFENCE-NEXT: .LBB1_6: # %exit -; X64-LFENCE-NEXT: lfence -; X64-LFENCE-NEXT: retq -; X64-LFENCE-NEXT: .LBB1_2: # %then2 -; X64-LFENCE-NEXT: pushq %r14 -; X64-LFENCE-NEXT: pushq %rbx -; X64-LFENCE-NEXT: pushq %rax +; X64-LFENCE-NEXT: jne .LBB1_6 +; X64-LFENCE-NEXT: # %bb.2: # %then2 ; X64-LFENCE-NEXT: movq %r8, %rbx ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: testl %edx, %edx @@ -126,10 +138,14 @@ define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, i32* %ptr1, i32* %ptr ; X64-LFENCE-NEXT: .LBB1_5: # %merge ; X64-LFENCE-NEXT: movslq (%r14), %rax ; X64-LFENCE-NEXT: movl $0, (%rbx,%rax,4) +; X64-LFENCE-NEXT: .LBB1_6: # %exit +; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: addq $8, %rsp +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 24 ; X64-LFENCE-NEXT: popq %rbx +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 16 ; X64-LFENCE-NEXT: popq %r14 -; X64-LFENCE-NEXT: lfence +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 8 ; X64-LFENCE-NEXT: retq entry: %a.cmp = icmp eq i32 %a, 0 @@ -465,12 +481,18 @@ declare i8* @__cxa_allocate_exception(i64) local_unnamed_addr declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr -define void @test_basic_eh(i32 %a, i32* %ptr1, i32* %ptr2) nounwind personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define void @test_basic_eh(i32 %a, i32* %ptr1, i32* %ptr2) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { ; X64-LABEL: test_basic_eh: ; X64: # %bb.0: # %entry ; X64-NEXT: pushq %rbp +; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: pushq %r14 +; X64-NEXT: .cfi_def_cfa_offset 24 ; X64-NEXT: pushq %rbx +; X64-NEXT: .cfi_def_cfa_offset 32 +; X64-NEXT: .cfi_offset %rbx, -32 +; X64-NEXT: .cfi_offset %r14, -24 +; X64-NEXT: .cfi_offset %rbp, -16 ; X64-NEXT: movq %rsp, %rax ; X64-NEXT: movq $-1, %rcx ; X64-NEXT: sarq $63, %rax @@ -507,10 +529,14 @@ define void @test_basic_eh(i32 %a, i32* %ptr1, i32* %ptr2) nounwind personality ; X64-NEXT: shlq $47, %rax ; X64-NEXT: orq %rax, %rsp ; X64-NEXT: popq %rbx +; X64-NEXT: .cfi_def_cfa_offset 24 ; X64-NEXT: popq %r14 +; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: popq %rbp +; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: retq ; X64-NEXT: .LBB4_4: # %lpad +; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .Ltmp2: ; X64-NEXT: movq %rsp, %rcx ; X64-NEXT: sarq $63, %rcx @@ -529,8 +555,14 @@ define void @test_basic_eh(i32 %a, i32* %ptr1, i32* %ptr2) nounwind personality ; X64-LFENCE-LABEL: test_basic_eh: ; X64-LFENCE: # %bb.0: # %entry ; X64-LFENCE-NEXT: pushq %rbp +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 16 ; X64-LFENCE-NEXT: pushq %r14 +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 24 ; X64-LFENCE-NEXT: pushq %rbx +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 32 +; X64-LFENCE-NEXT: .cfi_offset %rbx, -32 +; X64-LFENCE-NEXT: .cfi_offset %r14, -24 +; X64-LFENCE-NEXT: .cfi_offset %rbp, -16 ; X64-LFENCE-NEXT: cmpl $41, %edi ; X64-LFENCE-NEXT: jg .LBB4_2 ; X64-LFENCE-NEXT: # %bb.1: # %thrower @@ -551,10 +583,14 @@ define void @test_basic_eh(i32 %a, i32* %ptr1, i32* %ptr2) nounwind personality ; X64-LFENCE-NEXT: .LBB4_2: # %exit ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: popq %rbx +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 24 ; X64-LFENCE-NEXT: popq %r14 +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 16 ; X64-LFENCE-NEXT: popq %rbp +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 8 ; X64-LFENCE-NEXT: retq ; X64-LFENCE-NEXT: .LBB4_3: # %lpad +; X64-LFENCE-NEXT: .cfi_def_cfa_offset 32 ; X64-LFENCE-NEXT: .Ltmp2: ; X64-LFENCE-NEXT: movl (%rax), %eax ; X64-LFENCE-NEXT: addl (%rbx), %eax diff --git a/test/CodeGen/X86/vector-idiv-sdiv-128.ll b/test/CodeGen/X86/vector-idiv-sdiv-128.ll index 2416a177228e..3f251dd8d62c 100644 --- a/test/CodeGen/X86/vector-idiv-sdiv-128.ll +++ b/test/CodeGen/X86/vector-idiv-sdiv-128.ll @@ -301,9 +301,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; SSE2-NEXT: sarq %rdx ; SSE2-NEXT: addq %rax, %rdx ; SSE2-NEXT: leaq (,%rdx,8), %rax -; SSE2-NEXT: subq %rdx, %rax -; SSE2-NEXT: subq %rax, %rcx -; SSE2-NEXT: movq %rcx, %xmm1 +; SSE2-NEXT: subq %rax, %rdx +; SSE2-NEXT: addq %rcx, %rdx +; SSE2-NEXT: movq %rdx, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE2-NEXT: movq %xmm0, %rcx ; SSE2-NEXT: movq %rcx, %rax @@ -313,9 +313,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; SSE2-NEXT: sarq %rdx ; SSE2-NEXT: addq %rax, %rdx ; SSE2-NEXT: leaq (,%rdx,8), %rax -; SSE2-NEXT: subq %rdx, %rax -; SSE2-NEXT: subq %rax, %rcx -; SSE2-NEXT: movq %rcx, %xmm0 +; SSE2-NEXT: subq %rax, %rdx +; SSE2-NEXT: addq %rcx, %rdx +; SSE2-NEXT: movq %rdx, %xmm0 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: retq @@ -331,9 +331,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; SSE41-NEXT: sarq %rdx ; SSE41-NEXT: addq %rax, %rdx ; SSE41-NEXT: leaq (,%rdx,8), %rax -; SSE41-NEXT: subq %rdx, %rax -; SSE41-NEXT: subq %rax, %rcx -; SSE41-NEXT: movq %rcx, %xmm1 +; SSE41-NEXT: subq %rax, %rdx +; SSE41-NEXT: addq %rcx, %rdx +; SSE41-NEXT: movq %rdx, %xmm1 ; SSE41-NEXT: movq %xmm0, %rcx ; SSE41-NEXT: movq %rcx, %rax ; SSE41-NEXT: imulq %rsi @@ -342,9 +342,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; SSE41-NEXT: sarq %rdx ; SSE41-NEXT: addq %rax, %rdx ; SSE41-NEXT: leaq (,%rdx,8), %rax -; SSE41-NEXT: subq %rdx, %rax -; SSE41-NEXT: subq %rax, %rcx -; SSE41-NEXT: movq %rcx, %xmm0 +; SSE41-NEXT: subq %rax, %rdx +; SSE41-NEXT: addq %rcx, %rdx +; SSE41-NEXT: movq %rdx, %xmm0 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: retq ; @@ -359,9 +359,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm1 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm1 ; AVX-NEXT: vmovq %xmm0, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: imulq %rsi @@ -370,9 +370,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm0 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm0 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX-NEXT: retq %res = srem <2 x i64> %a, <i64 7, i64 7> diff --git a/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/test/CodeGen/X86/vector-idiv-sdiv-256.ll index c112e84fbf73..5df4d09e9715 100644 --- a/test/CodeGen/X86/vector-idiv-sdiv-256.ll +++ b/test/CodeGen/X86/vector-idiv-sdiv-256.ll @@ -263,9 +263,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: sarq %rdx ; AVX1-NEXT: addq %rax, %rdx ; AVX1-NEXT: leaq (,%rdx,8), %rax -; AVX1-NEXT: subq %rdx, %rax -; AVX1-NEXT: subq %rax, %rcx -; AVX1-NEXT: vmovq %rcx, %xmm2 +; AVX1-NEXT: subq %rax, %rdx +; AVX1-NEXT: addq %rcx, %rdx +; AVX1-NEXT: vmovq %rdx, %xmm2 ; AVX1-NEXT: vmovq %xmm1, %rcx ; AVX1-NEXT: movq %rcx, %rax ; AVX1-NEXT: imulq %rsi @@ -274,9 +274,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: sarq %rdx ; AVX1-NEXT: addq %rax, %rdx ; AVX1-NEXT: leaq (,%rdx,8), %rax -; AVX1-NEXT: subq %rdx, %rax -; AVX1-NEXT: subq %rax, %rcx -; AVX1-NEXT: vmovq %rcx, %xmm1 +; AVX1-NEXT: subq %rax, %rdx +; AVX1-NEXT: addq %rcx, %rdx +; AVX1-NEXT: vmovq %rdx, %xmm1 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX1-NEXT: vpextrq $1, %xmm0, %rcx ; AVX1-NEXT: movq %rcx, %rax @@ -286,9 +286,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: sarq %rdx ; AVX1-NEXT: addq %rax, %rdx ; AVX1-NEXT: leaq (,%rdx,8), %rax -; AVX1-NEXT: subq %rdx, %rax -; AVX1-NEXT: subq %rax, %rcx -; AVX1-NEXT: vmovq %rcx, %xmm2 +; AVX1-NEXT: subq %rax, %rdx +; AVX1-NEXT: addq %rcx, %rdx +; AVX1-NEXT: vmovq %rdx, %xmm2 ; AVX1-NEXT: vmovq %xmm0, %rcx ; AVX1-NEXT: movq %rcx, %rax ; AVX1-NEXT: imulq %rsi @@ -297,9 +297,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: sarq %rdx ; AVX1-NEXT: addq %rax, %rdx ; AVX1-NEXT: leaq (,%rdx,8), %rax -; AVX1-NEXT: subq %rdx, %rax -; AVX1-NEXT: subq %rax, %rcx -; AVX1-NEXT: vmovq %rcx, %xmm0 +; AVX1-NEXT: subq %rax, %rdx +; AVX1-NEXT: addq %rcx, %rdx +; AVX1-NEXT: vmovq %rdx, %xmm0 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: retq @@ -316,9 +316,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX2-NEXT: sarq %rdx ; AVX2-NEXT: addq %rax, %rdx ; AVX2-NEXT: leaq (,%rdx,8), %rax -; AVX2-NEXT: subq %rdx, %rax -; AVX2-NEXT: subq %rax, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm2 +; AVX2-NEXT: subq %rax, %rdx +; AVX2-NEXT: addq %rcx, %rdx +; AVX2-NEXT: vmovq %rdx, %xmm2 ; AVX2-NEXT: vmovq %xmm1, %rcx ; AVX2-NEXT: movq %rcx, %rax ; AVX2-NEXT: imulq %rsi @@ -327,9 +327,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX2-NEXT: sarq %rdx ; AVX2-NEXT: addq %rax, %rdx ; AVX2-NEXT: leaq (,%rdx,8), %rax -; AVX2-NEXT: subq %rdx, %rax -; AVX2-NEXT: subq %rax, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm1 +; AVX2-NEXT: subq %rax, %rdx +; AVX2-NEXT: addq %rcx, %rdx +; AVX2-NEXT: vmovq %rdx, %xmm1 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX2-NEXT: vpextrq $1, %xmm0, %rcx ; AVX2-NEXT: movq %rcx, %rax @@ -339,9 +339,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX2-NEXT: sarq %rdx ; AVX2-NEXT: addq %rax, %rdx ; AVX2-NEXT: leaq (,%rdx,8), %rax -; AVX2-NEXT: subq %rdx, %rax -; AVX2-NEXT: subq %rax, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm2 +; AVX2-NEXT: subq %rax, %rdx +; AVX2-NEXT: addq %rcx, %rdx +; AVX2-NEXT: vmovq %rdx, %xmm2 ; AVX2-NEXT: vmovq %xmm0, %rcx ; AVX2-NEXT: movq %rcx, %rax ; AVX2-NEXT: imulq %rsi @@ -350,9 +350,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX2-NEXT: sarq %rdx ; AVX2-NEXT: addq %rax, %rdx ; AVX2-NEXT: leaq (,%rdx,8), %rax -; AVX2-NEXT: subq %rdx, %rax -; AVX2-NEXT: subq %rax, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm0 +; AVX2-NEXT: subq %rax, %rdx +; AVX2-NEXT: addq %rcx, %rdx +; AVX2-NEXT: vmovq %rdx, %xmm0 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: retq diff --git a/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/test/CodeGen/X86/vector-idiv-sdiv-512.ll index 310e1fc7057a..893c7d1bbd7b 100644 --- a/test/CodeGen/X86/vector-idiv-sdiv-512.ll +++ b/test/CodeGen/X86/vector-idiv-sdiv-512.ll @@ -214,9 +214,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm2 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm2 ; AVX-NEXT: vmovq %xmm1, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: imulq %rsi @@ -225,9 +225,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm1 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm1 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2 ; AVX-NEXT: vpextrq $1, %xmm2, %rcx @@ -238,9 +238,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm3 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm3 ; AVX-NEXT: vmovq %xmm2, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: imulq %rsi @@ -249,9 +249,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm2 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm2 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] ; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2 @@ -263,9 +263,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm3 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm3 ; AVX-NEXT: vmovq %xmm2, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: imulq %rsi @@ -274,9 +274,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm2 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm2 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] ; AVX-NEXT: vpextrq $1, %xmm0, %rcx ; AVX-NEXT: movq %rcx, %rax @@ -286,9 +286,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm3 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm3 ; AVX-NEXT: vmovq %xmm0, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: imulq %rsi @@ -297,9 +297,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: sarq %rdx ; AVX-NEXT: addq %rax, %rdx ; AVX-NEXT: leaq (,%rdx,8), %rax -; AVX-NEXT: subq %rdx, %rax -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: vmovq %rcx, %xmm0 +; AVX-NEXT: subq %rax, %rdx +; AVX-NEXT: addq %rcx, %rdx +; AVX-NEXT: vmovq %rdx, %xmm0 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] ; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 ; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 diff --git a/test/CodeGen/X86/vector-idiv-udiv-128.ll b/test/CodeGen/X86/vector-idiv-udiv-128.ll index c991a905c054..598782ddd639 100644 --- a/test/CodeGen/X86/vector-idiv-udiv-128.ll +++ b/test/CodeGen/X86/vector-idiv-udiv-128.ll @@ -278,9 +278,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; SSE2-NEXT: addq %rdx, %rax ; SSE2-NEXT: shrq $2, %rax ; SSE2-NEXT: leaq (,%rax,8), %rdx -; SSE2-NEXT: subq %rax, %rdx -; SSE2-NEXT: subq %rdx, %rcx -; SSE2-NEXT: movq %rcx, %xmm1 +; SSE2-NEXT: subq %rdx, %rax +; SSE2-NEXT: addq %rcx, %rax +; SSE2-NEXT: movq %rax, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE2-NEXT: movq %xmm0, %rcx ; SSE2-NEXT: movq %rcx, %rax @@ -291,9 +291,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; SSE2-NEXT: addq %rdx, %rax ; SSE2-NEXT: shrq $2, %rax ; SSE2-NEXT: leaq (,%rax,8), %rdx -; SSE2-NEXT: subq %rax, %rdx -; SSE2-NEXT: subq %rdx, %rcx -; SSE2-NEXT: movq %rcx, %xmm0 +; SSE2-NEXT: subq %rdx, %rax +; SSE2-NEXT: addq %rcx, %rax +; SSE2-NEXT: movq %rax, %xmm0 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: retq @@ -310,9 +310,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; SSE41-NEXT: addq %rdx, %rax ; SSE41-NEXT: shrq $2, %rax ; SSE41-NEXT: leaq (,%rax,8), %rdx -; SSE41-NEXT: subq %rax, %rdx -; SSE41-NEXT: subq %rdx, %rcx -; SSE41-NEXT: movq %rcx, %xmm1 +; SSE41-NEXT: subq %rdx, %rax +; SSE41-NEXT: addq %rcx, %rax +; SSE41-NEXT: movq %rax, %xmm1 ; SSE41-NEXT: movq %xmm0, %rcx ; SSE41-NEXT: movq %rcx, %rax ; SSE41-NEXT: mulq %rsi @@ -322,9 +322,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; SSE41-NEXT: addq %rdx, %rax ; SSE41-NEXT: shrq $2, %rax ; SSE41-NEXT: leaq (,%rax,8), %rdx -; SSE41-NEXT: subq %rax, %rdx -; SSE41-NEXT: subq %rdx, %rcx -; SSE41-NEXT: movq %rcx, %xmm0 +; SSE41-NEXT: subq %rdx, %rax +; SSE41-NEXT: addq %rcx, %rax +; SSE41-NEXT: movq %rax, %xmm0 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: retq ; @@ -340,9 +340,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm1 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm1 ; AVX-NEXT: vmovq %xmm0, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: mulq %rsi @@ -352,9 +352,9 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm0 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm0 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX-NEXT: retq %res = urem <2 x i64> %a, <i64 7, i64 7> diff --git a/test/CodeGen/X86/vector-idiv-udiv-256.ll b/test/CodeGen/X86/vector-idiv-udiv-256.ll index 81d93984e261..377ff5ea77af 100644 --- a/test/CodeGen/X86/vector-idiv-udiv-256.ll +++ b/test/CodeGen/X86/vector-idiv-udiv-256.ll @@ -264,9 +264,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: addq %rdx, %rax ; AVX1-NEXT: shrq $2, %rax ; AVX1-NEXT: leaq (,%rax,8), %rdx -; AVX1-NEXT: subq %rax, %rdx -; AVX1-NEXT: subq %rdx, %rcx -; AVX1-NEXT: vmovq %rcx, %xmm2 +; AVX1-NEXT: subq %rdx, %rax +; AVX1-NEXT: addq %rcx, %rax +; AVX1-NEXT: vmovq %rax, %xmm2 ; AVX1-NEXT: vmovq %xmm1, %rcx ; AVX1-NEXT: movq %rcx, %rax ; AVX1-NEXT: mulq %rsi @@ -276,9 +276,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: addq %rdx, %rax ; AVX1-NEXT: shrq $2, %rax ; AVX1-NEXT: leaq (,%rax,8), %rdx -; AVX1-NEXT: subq %rax, %rdx -; AVX1-NEXT: subq %rdx, %rcx -; AVX1-NEXT: vmovq %rcx, %xmm1 +; AVX1-NEXT: subq %rdx, %rax +; AVX1-NEXT: addq %rcx, %rax +; AVX1-NEXT: vmovq %rax, %xmm1 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX1-NEXT: vpextrq $1, %xmm0, %rcx ; AVX1-NEXT: movq %rcx, %rax @@ -289,9 +289,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: addq %rdx, %rax ; AVX1-NEXT: shrq $2, %rax ; AVX1-NEXT: leaq (,%rax,8), %rdx -; AVX1-NEXT: subq %rax, %rdx -; AVX1-NEXT: subq %rdx, %rcx -; AVX1-NEXT: vmovq %rcx, %xmm2 +; AVX1-NEXT: subq %rdx, %rax +; AVX1-NEXT: addq %rcx, %rax +; AVX1-NEXT: vmovq %rax, %xmm2 ; AVX1-NEXT: vmovq %xmm0, %rcx ; AVX1-NEXT: movq %rcx, %rax ; AVX1-NEXT: mulq %rsi @@ -301,9 +301,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX1-NEXT: addq %rdx, %rax ; AVX1-NEXT: shrq $2, %rax ; AVX1-NEXT: leaq (,%rax,8), %rdx -; AVX1-NEXT: subq %rax, %rdx -; AVX1-NEXT: subq %rdx, %rcx -; AVX1-NEXT: vmovq %rcx, %xmm0 +; AVX1-NEXT: subq %rdx, %rax +; AVX1-NEXT: addq %rcx, %rax +; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: retq @@ -321,9 +321,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX2-NEXT: addq %rdx, %rax ; AVX2-NEXT: shrq $2, %rax ; AVX2-NEXT: leaq (,%rax,8), %rdx -; AVX2-NEXT: subq %rax, %rdx -; AVX2-NEXT: subq %rdx, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm2 +; AVX2-NEXT: subq %rdx, %rax +; AVX2-NEXT: addq %rcx, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 ; AVX2-NEXT: vmovq %xmm1, %rcx ; AVX2-NEXT: movq %rcx, %rax ; AVX2-NEXT: mulq %rsi @@ -333,9 +333,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX2-NEXT: addq %rdx, %rax ; AVX2-NEXT: shrq $2, %rax ; AVX2-NEXT: leaq (,%rax,8), %rdx -; AVX2-NEXT: subq %rax, %rdx -; AVX2-NEXT: subq %rdx, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm1 +; AVX2-NEXT: subq %rdx, %rax +; AVX2-NEXT: addq %rcx, %rax +; AVX2-NEXT: vmovq %rax, %xmm1 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX2-NEXT: vpextrq $1, %xmm0, %rcx ; AVX2-NEXT: movq %rcx, %rax @@ -346,9 +346,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX2-NEXT: addq %rdx, %rax ; AVX2-NEXT: shrq $2, %rax ; AVX2-NEXT: leaq (,%rax,8), %rdx -; AVX2-NEXT: subq %rax, %rdx -; AVX2-NEXT: subq %rdx, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm2 +; AVX2-NEXT: subq %rdx, %rax +; AVX2-NEXT: addq %rcx, %rax +; AVX2-NEXT: vmovq %rax, %xmm2 ; AVX2-NEXT: vmovq %xmm0, %rcx ; AVX2-NEXT: movq %rcx, %rax ; AVX2-NEXT: mulq %rsi @@ -358,9 +358,9 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind { ; AVX2-NEXT: addq %rdx, %rax ; AVX2-NEXT: shrq $2, %rax ; AVX2-NEXT: leaq (,%rax,8), %rdx -; AVX2-NEXT: subq %rax, %rdx -; AVX2-NEXT: subq %rdx, %rcx -; AVX2-NEXT: vmovq %rcx, %xmm0 +; AVX2-NEXT: subq %rdx, %rax +; AVX2-NEXT: addq %rcx, %rax +; AVX2-NEXT: vmovq %rax, %xmm0 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: retq diff --git a/test/CodeGen/X86/vector-idiv-udiv-512.ll b/test/CodeGen/X86/vector-idiv-udiv-512.ll index 1288f5a5d5be..22c359cb7e98 100644 --- a/test/CodeGen/X86/vector-idiv-udiv-512.ll +++ b/test/CodeGen/X86/vector-idiv-udiv-512.ll @@ -218,9 +218,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm2 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm2 ; AVX-NEXT: vmovq %xmm1, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: mulq %rsi @@ -230,9 +230,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm1 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm1 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2 ; AVX-NEXT: vpextrq $1, %xmm2, %rcx @@ -244,9 +244,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm3 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm3 ; AVX-NEXT: vmovq %xmm2, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: mulq %rsi @@ -256,9 +256,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm2 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm2 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] ; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2 @@ -271,9 +271,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm3 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm3 ; AVX-NEXT: vmovq %xmm2, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: mulq %rsi @@ -283,9 +283,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm2 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm2 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] ; AVX-NEXT: vpextrq $1, %xmm0, %rcx ; AVX-NEXT: movq %rcx, %rax @@ -296,9 +296,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm3 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm3 ; AVX-NEXT: vmovq %xmm0, %rcx ; AVX-NEXT: movq %rcx, %rax ; AVX-NEXT: mulq %rsi @@ -308,9 +308,9 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind { ; AVX-NEXT: addq %rdx, %rax ; AVX-NEXT: shrq $2, %rax ; AVX-NEXT: leaq (,%rax,8), %rdx -; AVX-NEXT: subq %rax, %rdx -; AVX-NEXT: subq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm0 +; AVX-NEXT: subq %rdx, %rax +; AVX-NEXT: addq %rcx, %rax +; AVX-NEXT: vmovq %rax, %xmm0 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] ; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 ; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 diff --git a/test/CodeGen/X86/vector-shift-lshr-128.ll b/test/CodeGen/X86/vector-shift-lshr-128.ll index 90a0c6f291b2..b50680ff56ee 100644 --- a/test/CodeGen/X86/vector-shift-lshr-128.ll +++ b/test/CodeGen/X86/vector-shift-lshr-128.ll @@ -1008,36 +1008,16 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind { ; ; SSE41-LABEL: constant_shift_v8i16: ; SSE41: # %bb.0: -; SSE41-NEXT: movdqa %xmm0, %xmm1 -; SSE41-NEXT: psrlw $4, %xmm1 -; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; SSE41-NEXT: movdqa %xmm1, %xmm2 -; SSE41-NEXT: psrlw $2, %xmm2 -; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] -; SSE41-NEXT: movdqa %xmm2, %xmm0 -; SSE41-NEXT: psrlw $1, %xmm0 -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3],xmm2[4],xmm0[5],xmm2[6],xmm0[7] +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = <u,32768,16384,8192,4096,2048,1024,512> +; SSE41-NEXT: pmulhuw %xmm0, %xmm1 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7] ; SSE41-NEXT: retq ; -; AVX1-LABEL: constant_shift_v8i16: -; AVX1: # %bb.0: -; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm1 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] -; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; AVX1-NEXT: retq -; -; AVX2-LABEL: constant_shift_v8i16: -; AVX2: # %bb.0: -; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 -; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] -; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq +; AVX-LABEL: constant_shift_v8i16: +; AVX: # %bb.0: +; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1 +; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7] +; AVX-NEXT: retq ; ; XOP-LABEL: constant_shift_v8i16: ; XOP: # %bb.0: @@ -1046,11 +1026,8 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind { ; ; AVX512DQ-LABEL: constant_shift_v8i16: ; AVX512DQ: # %bb.0: -; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX512DQ-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 -; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 -; AVX512DQ-NEXT: vzeroupper +; AVX512DQ-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1 +; AVX512DQ-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7] ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: constant_shift_v8i16: @@ -1064,10 +1041,8 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind { ; ; AVX512DQVL-LABEL: constant_shift_v8i16: ; AVX512DQVL: # %bb.0: -; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX512DQVL-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 -; AVX512DQVL-NEXT: vpmovdw %ymm0, %xmm0 -; AVX512DQVL-NEXT: vzeroupper +; AVX512DQVL-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1 +; AVX512DQVL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7] ; AVX512DQVL-NEXT: retq ; ; AVX512BWVL-LABEL: constant_shift_v8i16: diff --git a/test/CodeGen/X86/vector-shift-lshr-256.ll b/test/CodeGen/X86/vector-shift-lshr-256.ll index f0f0bb8a8819..3ca714d7f830 100644 --- a/test/CodeGen/X86/vector-shift-lshr-256.ll +++ b/test/CodeGen/X86/vector-shift-lshr-256.ll @@ -1025,21 +1025,11 @@ define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind { define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; AVX1-LABEL: constant_shift_v16i16: ; AVX1: # %bb.0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1 -; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7] -; AVX1-NEXT: vpsrlw $2, %xmm1, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] -; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7] -; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] -; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] -; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm2 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] -; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1 +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: constant_shift_v16i16: @@ -1102,21 +1092,11 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; ; X32-AVX1-LABEL: constant_shift_v16i16: ; X32-AVX1: # %bb.0: -; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; X32-AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1 -; X32-AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2 -; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7] -; X32-AVX1-NEXT: vpsrlw $2, %xmm1, %xmm2 -; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] -; X32-AVX1-NEXT: vpsrlw $1, %xmm1, %xmm2 -; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7] -; X32-AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2 -; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] -; X32-AVX1-NEXT: vpsrlw $2, %xmm0, %xmm2 -; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] -; X32-AVX1-NEXT: vpsrlw $1, %xmm0, %xmm2 -; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] -; X32-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; X32-AVX1-NEXT: vpmulhuw {{\.LCPI.*}}, %xmm0, %xmm1 +; X32-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7] +; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; X32-AVX1-NEXT: vpmulhuw {{\.LCPI.*}}, %xmm0, %xmm0 +; X32-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X32-AVX1-NEXT: retl ; ; X32-AVX2-LABEL: constant_shift_v16i16: diff --git a/test/CodeGen/X86/win_coreclr_chkstk.ll b/test/CodeGen/X86/win_coreclr_chkstk.ll index 8934535d6f52..24f2b2be4308 100644 --- a/test/CodeGen/X86/win_coreclr_chkstk.ll +++ b/test/CodeGen/X86/win_coreclr_chkstk.ll @@ -10,8 +10,6 @@ entry: ; WIN_X64-LABEL:main4k: ; WIN_X64: # %bb.0: ; WIN_X64: movl $4096, %eax -; WIN_X64: movq %rcx, 8(%rsp) -; WIN_X64: movq %rdx, 16(%rsp) ; WIN_X64: xorq %rcx, %rcx ; WIN_X64: movq %rsp, %rdx ; WIN_X64: subq %rax, %rdx @@ -27,8 +25,6 @@ entry: ; WIN_X64: cmpq %rcx, %rdx ; WIN_X64: jne .LBB0_2 ; WIN_X64:.LBB0_3: -; WIN_X64: movq 8(%rsp), %rcx -; WIN_X64: movq 16(%rsp), %rdx ; WIN_X64: subq %rax, %rsp ; WIN_X64: xorl %eax, %eax ; WIN_X64: addq $4096, %rsp @@ -45,7 +41,6 @@ entry: define i32 @main4k_frame() nounwind "no-frame-pointer-elim"="true" { entry: ; WIN_X64-LABEL:main4k_frame: -; WIN_X64: movq %rcx, 16(%rsp) ; WIN_X64: movq %gs:16, %rcx ; LINUX-LABEL:main4k_frame: ; LINUX-NOT: movq %gs:16, %rcx @@ -58,7 +53,6 @@ entry: ; Case with INT args define i32 @main4k_intargs(i32 %x, i32 %y) nounwind { entry: -; WIN_X64: movq %rcx, 8(%rsp) ; WIN_X64: movq %gs:16, %rcx ; LINUX-NOT: movq %gs:16, %rcx ; LINUX: retq @@ -71,7 +65,6 @@ entry: ; Case with FP regs define i32 @main4k_fpargs(double %x, double %y) nounwind { entry: -; WIN_X64: movq %rcx, 8(%rsp) ; WIN_X64: movq %gs:16, %rcx ; LINUX-NOT: movq %gs:16, %rcx ; LINUX: retq diff --git a/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir b/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir new file mode 100644 index 000000000000..8da5f895063f --- /dev/null +++ b/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir @@ -0,0 +1,24 @@ +# RUN: llc -verify-machineinstrs %s -run-pass prologepilog -mtriple=x86_64-pc-win32-coreclr -o - | FileCheck %s +... +--- +name: main4k +# CHECK-LABEL: name: main4k + +alignment: 4 +tracksRegLiveness: true +frameInfo: + maxAlignment: 8 +stack: + - { id: 0, size: 4096, alignment: 1, stack-id: 0 } +body: | + bb.0.entry: + $eax = IMPLICIT_DEF + RET 0, killed $eax + + ; CHECK: bb.1.entry: + ; CHECK: liveins: $rdx + ; CHECK: bb.2.entry: + ; CHECK: liveins: $rcx, $rdx + ; CHECK: bb.3.entry: + ; CHECK: liveins: $rax +... diff --git a/test/DebugInfo/PDB/pdb-invalid-type.test b/test/DebugInfo/PDB/pdb-invalid-type.test new file mode 100644 index 000000000000..33ea8d90452f --- /dev/null +++ b/test/DebugInfo/PDB/pdb-invalid-type.test @@ -0,0 +1,15 @@ +# RUN: llvm-pdbutil yaml2pdb -pdb=%t1.pdb %p/Inputs/one-symbol.yaml +# RUN: llvm-pdbutil yaml2pdb -pdb=%t2.pdb %s +# RUN: not llvm-pdbutil merge -pdb=%t.pdb %t1.pdb %t2.pdb 2>&1 | FileCheck %s + +# CHECK: CodeView Error: The CodeView record is corrupted. + +--- +TpiStream: + Records: + # uint32_t* [Index: 0x1000] + - Kind: LF_POINTER + Pointer: + ReferentType: 4097 + Attrs: 32778 +... diff --git a/test/DebugInfo/PDB/using-namespace.test b/test/DebugInfo/PDB/using-namespace.test new file mode 100644 index 000000000000..77c37826c8fc --- /dev/null +++ b/test/DebugInfo/PDB/using-namespace.test @@ -0,0 +1,51 @@ +# RUN: yaml2obj < %s > %t.obj +# RUN: llvm-readobj -codeview %t.obj | FileCheck %s + +# CHECK: Kind: S_UNAMESPACE (0x1124) +# CHECK-NEXT: Namespace: __vc_attributes + +--- !COFF +header: + Machine: IMAGE_FILE_MACHINE_AMD64 + Characteristics: [ ] +sections: + - Name: '.debug$S' + Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_DISCARDABLE, IMAGE_SCN_MEM_READ ] + Alignment: 1 + Subsections: + - !Symbols + Records: + - Kind: S_OBJNAME + ObjNameSym: + Signature: 0 + ObjectName: 'SimpleFunction.obj' + - Kind: S_COMPILE3 + Compile3Sym: + Flags: [ SecurityChecks, HotPatch ] + Machine: X64 + FrontendMajor: 19 + FrontendMinor: 14 + FrontendBuild: 26433 + FrontendQFE: 0 + BackendMajor: 19 + BackendMinor: 14 + BackendBuild: 26433 + BackendQFE: 0 + Version: 'Microsoft (R) Optimizing Compiler' + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: __vc_attributes + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: helper_attributes + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: atl + - Kind: S_UNAMESPACE + UsingNamespaceSym: + Namespace: std + - !StringTable + Strings: + - 'SimpleFunction.c' +symbols: +... diff --git a/test/DebugInfo/RISCV/lit.local.cfg b/test/DebugInfo/RISCV/lit.local.cfg new file mode 100644 index 000000000000..c63820126f8c --- /dev/null +++ b/test/DebugInfo/RISCV/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'RISCV' in config.root.targets: + config.unsupported = True diff --git a/test/DebugInfo/RISCV/relax-debug-line.ll b/test/DebugInfo/RISCV/relax-debug-line.ll new file mode 100644 index 000000000000..814b253fadff --- /dev/null +++ b/test/DebugInfo/RISCV/relax-debug-line.ll @@ -0,0 +1,75 @@ +; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o - \ +; RUN: | llvm-readobj -r | FileCheck -check-prefix=RELAX %s +; +; RELAX: .rela.debug_line { +; RELAX: R_RISCV_ADD16 +; RELAX: R_RISCV_SUB16 +source_filename = "line.c" + +; Function Attrs: noinline nounwind optnone +define i32 @init() !dbg !7 { +entry: + ret i32 0, !dbg !11 +} + +; Function Attrs: noinline nounwind optnone +define i32 @foo(i32 signext %value) !dbg !12 { +entry: + %value.addr = alloca i32, align 4 + store i32 %value, i32* %value.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %value.addr, metadata !15, metadata !DIExpression()), !dbg !16 + %0 = load i32, i32* %value.addr, align 4, !dbg !17 + ret i32 %0, !dbg !18 +} + +; Function Attrs: nounwind readnone speculatable +declare void @llvm.dbg.declare(metadata, metadata, metadata) + +; Function Attrs: noinline nounwind optnone +define i32 @bar() !dbg !19 { +entry: + %result = alloca i32, align 4 + %v = alloca i32, align 4 + call void @llvm.dbg.declare(metadata i32* %result, metadata !20, metadata !DIExpression()), !dbg !21 + call void @llvm.dbg.declare(metadata i32* %v, metadata !22, metadata !DIExpression()), !dbg !23 + %call = call i32 @init(), !dbg !24 + store i32 %call, i32* %v, align 4, !dbg !23 + %0 = load i32, i32* %v, align 4, !dbg !25 + %call1 = call i32 @foo(i32 signext %0), !dbg !26 + store i32 %call1, i32* %result, align 4, !dbg !27 + %1 = load i32, i32* %result, align 4, !dbg !28 + ret i32 %1, !dbg !29 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "line.c", directory: "./") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!7 = distinct !DISubprogram(name: "init", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, unit: !0, retainedNodes: !2) +!8 = !DISubroutineType(types: !9) +!9 = !{!10} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = !DILocation(line: 3, column: 3, scope: !7) +!12 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 6, type: !13, isLocal: false, isDefinition: true, scopeLine: 7, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2) +!13 = !DISubroutineType(types: !14) +!14 = !{!10, !10} +!15 = !DILocalVariable(name: "value", arg: 1, scope: !12, file: !1, line: 6, type: !10) +!16 = !DILocation(line: 6, column: 13, scope: !12) +!17 = !DILocation(line: 8, column: 10, scope: !12) +!18 = !DILocation(line: 8, column: 3, scope: !12) +!19 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 11, type: !8, isLocal: false, isDefinition: true, scopeLine: 12, isOptimized: false, unit: !0, retainedNodes: !2) +!20 = !DILocalVariable(name: "result", scope: !19, file: !1, line: 13, type: !10) +!21 = !DILocation(line: 13, column: 7, scope: !19) +!22 = !DILocalVariable(name: "v", scope: !19, file: !1, line: 14, type: !10) +!23 = !DILocation(line: 14, column: 7, scope: !19) +!24 = !DILocation(line: 14, column: 11, scope: !19) +!25 = !DILocation(line: 16, column: 16, scope: !19) +!26 = !DILocation(line: 16, column: 12, scope: !19) +!27 = !DILocation(line: 16, column: 10, scope: !19) +!28 = !DILocation(line: 18, column: 10, scope: !19) +!29 = !DILocation(line: 18, column: 3, scope: !19) diff --git a/test/DebugInfo/X86/accel-tables-dwarf5.ll b/test/DebugInfo/X86/accel-tables-dwarf5.ll index 462a3bd58046..eef44e7b11c0 100644 --- a/test/DebugInfo/X86/accel-tables-dwarf5.ll +++ b/test/DebugInfo/X86/accel-tables-dwarf5.ll @@ -15,8 +15,11 @@ ; type units. Change this once DWARF v5 type units are implemented. ; RUN: llc -mtriple=x86_64-pc-linux -filetype=obj -generate-type-units -debugger-tune=lldb < %s \ ; RUN: | llvm-readobj -sections - | FileCheck --check-prefix=NONE %s + +; Debug types are ignored for non-ELF targets which means it shouldn't affect +; accelerator table generation. ; RUN: llc -mtriple=x86_64-apple-darwin12 -generate-type-units -filetype=obj < %s \ -; RUN: | llvm-readobj -sections - | FileCheck --check-prefix=NONE %s +; RUN: | llvm-readobj -sections - | FileCheck --check-prefix=DEBUG_NAMES %s ; NONE-NOT: apple_names ; NONE-NOT: debug_names diff --git a/test/DebugInfo/X86/accel-tables.ll b/test/DebugInfo/X86/accel-tables.ll index e4f1508029e2..813b66f1aeb6 100644 --- a/test/DebugInfo/X86/accel-tables.ll +++ b/test/DebugInfo/X86/accel-tables.ll @@ -12,12 +12,15 @@ ; RUN: llc -mtriple=x86_64-pc-linux -filetype=obj -debugger-tune=lldb < %s \ ; RUN: | llvm-readobj -sections - | FileCheck --check-prefix=DEBUG_NAMES %s -; Neither target has accelerator tables if type units are enabled, as DWARF v4 -; type units are not compatible with accelerator tables. +; No accelerator tables if type units are enabled, as DWARF v4 type units are +; not compatible with accelerator tables. ; RUN: llc -mtriple=x86_64-pc-linux -filetype=obj -generate-type-units -debugger-tune=lldb < %s \ ; RUN: | llvm-readobj -sections - | FileCheck --check-prefix=NONE %s + +; Debug types are ignored for non-ELF targets which means it shouldn't affect +; accelerator table generation. ; RUN: llc -mtriple=x86_64-apple-darwin12 -generate-type-units -filetype=obj < %s \ -; RUN: | llvm-readobj -sections - | FileCheck --check-prefix=NONE %s +; RUN: | llvm-readobj -sections - | FileCheck --check-prefix=APPLE %s ; APPLE-NOT: debug_names ; APPLE: apple_names diff --git a/test/DebugInfo/X86/debug_addr.ll b/test/DebugInfo/X86/debug_addr.ll new file mode 100644 index 000000000000..cf6b241b1de5 --- /dev/null +++ b/test/DebugInfo/X86/debug_addr.ll @@ -0,0 +1,79 @@ +; RUN: llc -split-dwarf-file=test.dwo -dwarf-version=4 %s -mtriple=i386-unknown-linux-gnu -filetype=obj -o - | \ +; RUN: llvm-dwarfdump -v - | FileCheck %s -check-prefix=DWARF4 + +; RUN: llc -split-dwarf-file=test.dwo -dwarf-version=5 %s -mtriple=i386-unknown-linux-gnu -filetype=obj -o - | \ +; RUN: llvm-dwarfdump -v - | FileCheck %s -check-prefix=DWARF5 + +; Source: +; void foo() { +; } +; +; void bar() { +; } + +; DWARF4: .debug_info contents: +; DWARF4: Compile Unit:{{.*}}version = 0x0004 +; DWARF4-NOT: Compile Unit +; DWARF4: DW_TAG_compile_unit +; DWARF4-NOT: DW_TAG_{{.*}} +; DWARF4: DW_AT_GNU_dwo_name{{.*}}test.dwo +; DWARF4: DW_AT_GNU_addr_base{{.*}}0x00000000 +; DWARF4: .debug_addr contents: +; DWARF4-NEXT: 0x00000000: Addr Section: length = 0x00000000, version = 0x0004, addr_size = 0x04, seg_size = 0x00 +; DWARF4-NEXT: Addrs: [ +; DWARF4-NEXT: 0x00000000 +; DWARF4-NEXT: 0x00000010 +; DWARF4-NEXT: ] + +; DWARF5: .debug_info contents: +; DWARF5: Compile Unit:{{.*}}version = 0x0005 +; DWARF5-NOT: Compile Unit +; DWARF5: DW_TAG_compile_unit +; DWARF5-NOT: DW_TAG_{{.*}} +; DWARF5: DW_AT_GNU_dwo_name{{.*}}test.dwo +; DWARF5: DW_AT_GNU_addr_base{{.*}}0x00000000 +; DWARF5: .debug_addr contents: +; DWARF5-NEXT: 0x00000000: Addr Section: length = 0x0000000c, version = 0x0005, addr_size = 0x04, seg_size = 0x00 +; DWARF5-NEXT: Addrs: [ +; DWARF5-NEXT: 0x00000000 +; DWARF5-NEXT: 0x00000010 +; DWARF5-NEXT: ] + +; ModuleID = './test.c' +source_filename = "./test.c" +target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" +target triple = "i386-unknown-linux-gnu" + +; Function Attrs: noinline nounwind optnone +define void @foo() #0 !dbg !8 { +entry: + ret void, !dbg !12 +} + +; Function Attrs: noinline nounwind optnone +define void @bar() #0 !dbg !13 { +entry: + ret void, !dbg !14 +} + +attributes #0 = { noinline nounwind optnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5, !6} +!llvm.ident = !{!7} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 6.0.1", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "test.c", directory: "/tmp") +!2 = !{} +!3 = !{i32 1, !"NumRegisterParameters", i32 0} +!4 = !{i32 2, !"Dwarf Version", i32 5} +!5 = !{i32 2, !"Debug Info Version", i32 3} +!6 = !{i32 1, !"wchar_size", i32 4} +!7 = !{!"clang version 6.0.1"} +!8 = distinct !DISubprogram(name: "foo", scope: !9, file: !9, line: 1, type: !10, isLocal: false, isDefinition: true, scopeLine: 1, isOptimized: false, unit: !0) +!9 = !DIFile(filename: "./test.c", directory: "/tmp") +!10 = !DISubroutineType(types: !11) +!11 = !{null} +!12 = !DILocation(line: 2, column: 3, scope: !8) +!13 = distinct !DISubprogram(name: "bar", scope: !9, file: !9, line: 5, type: !10, isLocal: false, isDefinition: true, scopeLine: 5, isOptimized: false, unit: !0) +!14 = !DILocation(line: 6, column: 3, scope: !13) diff --git a/test/Demangle/ms-cxx11.test b/test/Demangle/ms-cxx11.test new file mode 100644 index 000000000000..b648cc3d6e33 --- /dev/null +++ b/test/Demangle/ms-cxx11.test @@ -0,0 +1,148 @@ +; These tests are based on clang/test/CodeGenCXX/mangle-ms-cxx11.cpp + +; RUN: llvm-undname < %s | FileCheck %s + +; CHECK-NOT: Invalid mangled name + +?a@FTypeWithQuals@@3U?$S@$$A8@@BAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) const> FTypeWithQuals::a + +?b@FTypeWithQuals@@3U?$S@$$A8@@CAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) volatile> FTypeWithQuals::b + +?c@FTypeWithQuals@@3U?$S@$$A8@@IAAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) __restrict> FTypeWithQuals::c + +?d@FTypeWithQuals@@3U?$S@$$A8@@GBAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) const &> FTypeWithQuals::d + +?e@FTypeWithQuals@@3U?$S@$$A8@@GCAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) volatile &> FTypeWithQuals::e + +?f@FTypeWithQuals@@3U?$S@$$A8@@IGAAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) __restrict &> FTypeWithQuals::f + +?g@FTypeWithQuals@@3U?$S@$$A8@@HBAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) const &&> FTypeWithQuals::g + +?h@FTypeWithQuals@@3U?$S@$$A8@@HCAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) volatile &&> FTypeWithQuals::h + +?i@FTypeWithQuals@@3U?$S@$$A8@@IHAAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) __restrict &&> FTypeWithQuals::i + +?j@FTypeWithQuals@@3U?$S@$$A6AHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void)> FTypeWithQuals::j + +?k@FTypeWithQuals@@3U?$S@$$A8@@GAAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) &> FTypeWithQuals::k + +?l@FTypeWithQuals@@3U?$S@$$A8@@HAAHXZ@1@A +; CHECK: struct FTypeWithQuals::S<int __cdecl(void) &&> FTypeWithQuals::l + +?Char16Var@@3_SA +; CHECK: char16_t Char16Var + +?Char32Var@@3_UA +; CHECK: char32_t Char32Var + +?LRef@@YAXAAH@Z +; CHECK: void __cdecl LRef(int &) + +?RRef@@YAH$$QAH@Z +; CHECK: int __cdecl RRef(int &&) + +?Null@@YAX$$T@Z +; CHECK: void __cdecl Null(std::nullptr_t) + +?fun@PR18022@@YA?AU<unnamed-type-a>@1@U21@0@Z +; CHECK: struct PR18022::<unnamed-type-a> __cdecl PR18022::fun(struct PR18022::<unnamed-type-a>, struct PR18022::<unnamed-type-a>) + +; First, we have the static local variable of type "<lambda_1>" inside of "define_lambda". +; decltype(lambda), where lambda = [] { static int local=42; return 42; }; +?lambda@?1??define_lambda@@YAHXZ@4V<lambda_1>@?0??1@YAHXZ@A +; CHECK: class `int __cdecl define_lambda(void)'::`1'::<lambda_1> `int __cdecl define_lambda(void)'::`2'::lambda + +; Next, we have the "operator()" for "<lambda_1>" which is inside of "define_lambda". +??R<lambda_1>@?0??define_lambda@@YAHXZ@QBE@XZ +; CHECK: __thiscall `int __cdecl define_lambda(void)'::`1'::<lambda_1>::operator()(void) const + +; Finally, we have the local which is inside of "<lambda_1>" which is inside of "define_lambda". +?local@?2???R<lambda_1>@?0??define_lambda@@YAHXZ@QBE@XZ@4HA +; CHECK: __thiscall `int __cdecl define_lambda(void)'::`1'::<lambda_1>::operator()(void) const + +??$use_lambda_arg@V<lambda_1>@?0??call_with_lambda_arg1@@YAXXZ@@@YAXV<lambda_1>@?0??call_with_lambda_arg1@@YAXXZ@@Z +; CHECK: void __cdecl use_lambda_arg<class `void __cdecl call_with_lambda_arg1(void)'::`1'::<lambda_1>>(class `void __cdecl call_with_lambda_arg1(void)'::`1'::<lambda_1>) + +?foo@A@PR19361@@QIGAEXXZ +; CHECK: void __thiscall PR19361::A::foo(void) __restrict & + +?foo@A@PR19361@@QIHAEXXZ +; CHECK: void __thiscall PR19361::A::foo(void) __restrict && + +??__K_deg@@YAHO@Z +; CHECK: int __cdecl operator ""_deg(long double) + +??$templ_fun_with_pack@$S@@YAXXZ +; CHECK: void __cdecl templ_fun_with_pack<>(void) + +??$templ_fun_with_ty_pack@$$$V@@YAXXZ +; CHECK: void __cdecl templ_fun_with_ty_pack<>(void) +??$templ_fun_with_ty_pack@$$V@@YAXXZ +; CHECK: void __cdecl templ_fun_with_ty_pack<>(void) + +??$f@$$YAliasA@PR20047@@@PR20047@@YAXXZ +; CHECK: void __cdecl PR20047::f<PR20047::AliasA>(void) + +?f@UnnamedType@@YAXAAU<unnamed-type-TD>@A@1@@Z +; CHECK: void __cdecl UnnamedType::f(struct UnnamedType::A::<unnamed-type-TD> &) + +?f@UnnamedType@@YAXPAW4<unnamed-type-e>@?$B@H@1@@Z +; CHECK: void __cdecl UnnamedType::f(enum UnnamedType::B<int>::<unnamed-type-e> *) + +??$f@W4<unnamed-type-E>@?1??g@PR24651@@YAXXZ@@PR24651@@YAXW4<unnamed-type-E>@?1??g@0@YAXXZ@@Z +; We have a back-referencing problem here, we print `void __cdecl <unnamed-type-E>::g(void)` +; for the second occurrence of g. +; FIXME: void __cdecl PR24651::f<enum `void __cdecl PR24651::g(void)'::`2'::<unnamed-type-E>>(enum `void __cdecl PR24651::g(void)'::`2'::<unnamed-type-E>) + +??$f@T<unnamed-type-$S1>@PR18204@@@PR18204@@YAHPAT<unnamed-type-$S1>@0@@Z +; FIXME: int __cdecl PR18204::f<union PR18204::<unnamed-type-$S1>>(union PR18204::<unnamed-type-$S1> *) + +??R<lambda_0>@?0??PR26105@@YAHXZ@QBE@H@Z +; CHECK: __thiscall `int __cdecl PR26105(void)'::`1'::<lambda_0>::operator()(int) const + +??R<lambda_1>@?0???R<lambda_0>@?0??PR26105@@YAHXZ@QBE@H@Z@QBE@H@Z +; CHECK: __thiscall `__thiscall `int __cdecl PR26105(void)'::`1'::<lambda_0>::operator()(int) const'::`1'::<lambda_1>::operator()(int) const + +?unaligned_foo1@@YAPFAHXZ +; CHECK: int __unaligned * __cdecl unaligned_foo1(void) + +?unaligned_foo2@@YAPFAPFAHXZ +; CHECK: int __unaligned *__unaligned * __cdecl unaligned_foo2(void) + +?unaligned_foo3@@YAHXZ +; CHECK: int __cdecl unaligned_foo3(void) + +?unaligned_foo4@@YAXPFAH@Z +; CHECK: void __cdecl unaligned_foo4(int __unaligned *) + +?unaligned_foo5@@YAXPIFAH@Z +; CHECK: void __cdecl unaligned_foo5(int __unaligned *__restrict) + +??$unaligned_foo6@PAH@@YAPAHPAH@Z +; CHECK: int * __cdecl unaligned_foo6<int *>(int *) + +??$unaligned_foo6@PFAH@@YAPFAHPFAH@Z +; CHECK: int __unaligned * __cdecl unaligned_foo6<int __unaligned *>(int __unaligned *) + +?unaligned_foo8@unaligned_foo8_S@@QFCEXXZ +; CHECK: void __thiscall unaligned_foo8_S::unaligned_foo8(void) volatile __unaligned + +??R<lambda_1>@x@A@PR31197@@QBE@XZ +; CHECK: __thiscall PR31197::A::x::<lambda_1>::operator()(void) const + +?white@?1???R<lambda_1>@x@A@PR31197@@QBE@XZ@4HA +; CHECK: int `__thiscall PR31197::A::x::<lambda_1>::operator()(void) const'::`2'::white + +?f@@YAXW4<unnamed-enum-enumerator>@@@Z +; CHECK: void __cdecl f(enum <unnamed-enum-enumerator>) diff --git a/test/Demangle/ms-mangle.test b/test/Demangle/ms-mangle.test index a5d0c70ee314..9a2f780f9334 100644 --- a/test/Demangle/ms-mangle.test +++ b/test/Demangle/ms-mangle.test @@ -265,18 +265,18 @@ ?s6@PR13182@@3PBQBDB ; CHECK: char const *const *PR13182::s6 -; FIXME: We don't properly support static locals in functions yet. +; FIXME: We don't properly support extern "C" functions yet. ; ?local@?1??extern_c_func@@9@4HA ; FIXME: int `extern_c_func'::`2'::local ; ?local@?1??extern_c_func@@9@4HA ; FIXME: int `extern_c_func'::`2'::local -; ?v@?1??f@@YAHXZ@4U<unnamed-type-v>@?1??1@YAHXZ@A -; FIXME: struct `int __cdecl f(void)'::`2'::<unnamed-type-v> `int __cdecl f(void)'::`2'::v +?v@?1??f@@YAHXZ@4U<unnamed-type-v>@?1??1@YAHXZ@A +; CHECK: struct `int __cdecl f(void)'::`2'::<unnamed-type-v> `int __cdecl f(void)'::`2'::v -; ?v@?1???$f@H@@YAHXZ@4U<unnamed-type-v>@?1???$f@H@@YAHXZ@A -; FIXME: struct `int __cdecl f<int>(void)'::`2'::<unnamed-type-v> `int __cdecl f<int>(void)'::`2'::v +?v@?1???$f@H@@YAHXZ@4U<unnamed-type-v>@?1???$f@H@@YAHXZ@A +; CHECK: struct `int __cdecl f<int>(void)'::`2'::<unnamed-type-v> `int __cdecl f<int>(void)'::`2'::v ??2OverloadedNewDelete@@SAPAXI@Z ; CHECK: static void * __cdecl OverloadedNewDelete::operator new(unsigned int) @@ -335,8 +335,8 @@ ; ?overloaded_fn@@$$J0YAXXZ ; FIXME-EXTERNC: extern \"C\" void __cdecl overloaded_fn(void) -; ?f@UnnamedType@@YAXQAPAU<unnamed-type-T1>@S@1@@Z -; FIXME: void __cdecl UnnamedType::f(struct UnnamedType::S::<unnamed-type-T1> ** const) +?f@UnnamedType@@YAXQAPAU<unnamed-type-T1>@S@1@@Z +; CHECK: void __cdecl UnnamedType::f(struct UnnamedType::S::<unnamed-type-T1> **const) ?f@UnnamedType@@YAXUT2@S@1@@Z ; CHECK: void __cdecl UnnamedType::f(struct UnnamedType::S::T2) diff --git a/test/Demangle/ms-nested-scopes.test b/test/Demangle/ms-nested-scopes.test new file mode 100644 index 000000000000..952b138630cc --- /dev/null +++ b/test/Demangle/ms-nested-scopes.test @@ -0,0 +1,146 @@ +; RUN: llvm-undname < %s | FileCheck %s + +; CHECK-NOT: Invalid mangled name + +; Test demangling of function local scope discriminator IDs. +?M@?@??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`0'::M + +?M@?0??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`1'::M + +?M@?1??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`2'::M + +?M@?2??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`3'::M + +?M@?3??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`4'::M + +?M@?4??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`5'::M + +?M@?5??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`6'::M + +?M@?6??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`7'::M + +?M@?7??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`8'::M + +?M@?8??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`9'::M + +?M@?9??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`10'::M + +?M@?L@??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`11'::M + +?M@?M@??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`12'::M + +?M@?N@??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`13'::M + +?M@?O@??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`14'::M + +?M@?P@??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`15'::M + +?M@?BA@??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`16'::M + +?M@?BB@??L@@YAHXZ@4HA +; CHECK: int `int __cdecl L(void)'::`17'::M + +?j@?1??L@@YAHXZ@4UJ@@A +; CHECK: struct J `int __cdecl L(void)'::`2'::j + +; Test demangling of name back-references +?NN@0XX@@3HA +; CHECK: int XX::NN::NN + +?MM@0NN@XX@@3HA +; CHECK: int XX::NN::MM::MM + +?NN@MM@0XX@@3HA +; CHECK: int XX::NN::MM::NN + +?OO@0NN@01XX@@3HA +; CHECK: int XX::NN::OO::NN::OO::OO + +?NN@OO@010XX@@3HA +; CHECK: int XX::NN::OO::NN::OO::NN + +; Test demangling of name back-references combined with function local scopes. +?M@?1??0@YAHXZ@4HA +; CHECK: int `int __cdecl M(void)'::`2'::M + +?L@?2??M@0?2??0@YAHXZ@QEAAHXZ@4HA +; CHECK: int `int __cdecl `int __cdecl L(void)'::`3'::L::M(void)'::`3'::L + +?M@?2??0L@?2??1@YAHXZ@QEAAHXZ@4HA +; CHECK: int `int __cdecl `int __cdecl L(void)'::`3'::L::M(void)'::`3'::M + +; Function local scopes of template functions +?M@?1???$L@H@@YAHXZ@4HA +; CHECK: int `int __cdecl L<int>(void)'::`2'::M + +; And member functions of template classes +?SN@?$NS@H@NS@@QEAAHXZ +; CHECK: int __cdecl NS::NS<int>::SN(void) + +?NS@?1??SN@?$NS@H@0@QEAAHXZ@4HA +; CHECK: int `int __cdecl NS::NS<int>::SN(void)'::`2'::NS + +?SN@?1??0?$NS@H@NS@@QEAAHXZ@4HA +; CHECK: int `int __cdecl NS::NS<int>::SN(void)'::`2'::SN + +?NS@?1??SN@?$NS@H@10@QEAAHXZ@4HA +; CHECK: int `int __cdecl NS::SN::NS<int>::SN(void)'::`2'::NS + +?SN@?1??0?$NS@H@0NS@@QEAAHXZ@4HA +; CHECK: int `int __cdecl NS::SN::NS<int>::SN(void)'::`2'::SN + +; Make sure instantiated templates participate in back-referencing. +; In the next 3 examples there should be 3 back-references: +; 0 = X (right most name) +; 1 = C<int> (second from right) +; 2 = C (third from right) +; Make sure all 3 work as expected by having the 4th component take each value +; from 0-2 and confirming it is the right component. +?X@?$C@H@C@0@2HB +; CHECK: static int const X::C::C<int>::X + +?X@?$C@H@C@1@2HB +; CHECK: static int const C<int>::C::C<int>::X + +?X@?$C@H@C@2@2HB +; CHECK: static int const C::C::C<int>::X + +; Putting everything together. + +; namespace A { namespace B { namespace C { namespace B { namespace C { +; template<typename T> +; struct C { +; int B() { +; static C<int> C; +; static int B = 7; +; static int A = 7; +; return C.B() + B + A; +; } +; }; +; } } } } } + +?C@?1??B@?$C@H@0101A@@QEAAHXZ@4U201013@A +; CHECK: struct A::B::C::B::C::C<int> `int __cdecl A::B::C::B::C::C<int>::B(void)'::`2'::C + +?B@?1??0?$C@H@C@020A@@QEAAHXZ@4HA +; CHECK: int `int __cdecl A::B::C::B::C::C<int>::B(void)'::`2'::B + +?A@?1??B@?$C@H@C@1310@QEAAHXZ@4HA +; CHECK: int `int __cdecl A::B::C::B::C::C<int>::B(void)'::`2'::A diff --git a/test/Demangle/ms-return-qualifiers.test b/test/Demangle/ms-return-qualifiers.test new file mode 100644 index 000000000000..7fedf6c03a11 --- /dev/null +++ b/test/Demangle/ms-return-qualifiers.test @@ -0,0 +1,184 @@ +; These tests are based on clang/test/CodeGenCXX/mangle-ms-return-qualifiers.cpp + +; RUN: llvm-undname < %s | FileCheck %s + +; CHECK-NOT: Invalid mangled name + +?a1@@YAXXZ +; CHECK: void __cdecl a1(void) + +?a2@@YAHXZ +; CHECK: int __cdecl a2(void) + +?a3@@YA?BHXZ +; CHECK: int const __cdecl a3(void) + +?a4@@YA?CHXZ +; CHECK: int volatile __cdecl a4(void) + +?a5@@YA?DHXZ +; CHECK: int const volatile __cdecl a5(void) + +?a6@@YAMXZ +; CHECK: float __cdecl a6(void) + +?b1@@YAPAHXZ +; CHECK: int * __cdecl b1(void) + +?b2@@YAPBDXZ +; CHECK: char const * __cdecl b2(void) + +?b3@@YAPAMXZ +; CHECK: float * __cdecl b3(void) + +?b4@@YAPBMXZ +; CHECK: float const * __cdecl b4(void) + +?b5@@YAPCMXZ +; CHECK: float volatile * __cdecl b5(void) + +?b6@@YAPDMXZ +; CHECK: float const volatile * __cdecl b6(void) + +?b7@@YAAAMXZ +; CHECK: float & __cdecl b7(void) + +?b8@@YAABMXZ +; CHECK: float const & __cdecl b8(void) + +?b9@@YAACMXZ +; CHECK: float volatile & __cdecl b9(void) + +?b10@@YAADMXZ +; CHECK: float const volatile & __cdecl b10(void) + +?b11@@YAPAPBDXZ +; CHECK: char const ** __cdecl b11(void) + +?c1@@YA?AVA@@XZ +; CHECK: class A __cdecl c1(void) + +?c2@@YA?BVA@@XZ +; CHECK: class A const __cdecl c2(void) + +?c3@@YA?CVA@@XZ +; CHECK: class A volatile __cdecl c3(void) + +?c4@@YA?DVA@@XZ +; CHECK: class A const volatile __cdecl c4(void) + +?c5@@YAPBVA@@XZ +; CHECK: class A const * __cdecl c5(void) + +?c6@@YAPCVA@@XZ +; CHECK: class A volatile * __cdecl c6(void) + +?c7@@YAPDVA@@XZ +; CHECK: class A const volatile * __cdecl c7(void) + +?c8@@YAAAVA@@XZ +; CHECK: class A & __cdecl c8(void) + +?c9@@YAABVA@@XZ +; CHECK: class A const & __cdecl c9(void) + +?c10@@YAACVA@@XZ +; CHECK: class A volatile & __cdecl c10(void) + +?c11@@YAADVA@@XZ +; CHECK: class A const volatile & __cdecl c11(void) + +?d1@@YA?AV?$B@H@@XZ +; CHECK: class B<int> __cdecl d1(void) + +?d2@@YA?AV?$B@PBD@@XZ +; CHECK: class B<char const *> __cdecl d2(void) + +?d3@@YA?AV?$B@VA@@@@XZ +; CHECK: class B<class A> __cdecl d3(void) + +?d4@@YAPAV?$B@VA@@@@XZ +; CHECK: class B<class A> * __cdecl d4(void) + +?d5@@YAPBV?$B@VA@@@@XZ +; CHECK: class B<class A> const * __cdecl d5(void) + +?d6@@YAPCV?$B@VA@@@@XZ +; CHECK: class B<class A> volatile * __cdecl d6(void) + +?d7@@YAPDV?$B@VA@@@@XZ +; CHECK: class B<class A> const volatile * __cdecl d7(void) + +?d8@@YAAAV?$B@VA@@@@XZ +; CHECK: class B<class A> & __cdecl d8(void) + +?d9@@YAABV?$B@VA@@@@XZ +; CHECK: class B<class A> const & __cdecl d9(void) + +?d10@@YAACV?$B@VA@@@@XZ +; CHECK: class B<class A> volatile & __cdecl d10(void) + +?d11@@YAADV?$B@VA@@@@XZ +; CHECK: class B<class A> const volatile & __cdecl d11(void) + +?e1@@YA?AW4Enum@@XZ +; CHECK: Enum __cdecl e1(void) + +?e2@@YA?BW4Enum@@XZ +; CHECK: Enum const __cdecl e2(void) + +?e3@@YAPAW4Enum@@XZ +; CHECK: Enum * __cdecl e3(void) + +?e4@@YAAAW4Enum@@XZ +; CHECK: Enum & __cdecl e4(void) + +?f1@@YA?AUS@@XZ +; CHECK: struct S __cdecl f1(void) + +?f2@@YA?BUS@@XZ +; CHECK: struct S const __cdecl f2(void) + +?f3@@YAPAUS@@XZ +; CHECK: struct S * __cdecl f3(void) + +?f4@@YAPBUS@@XZ +; CHECK: struct S const * __cdecl f4(void) + +?f5@@YAPDUS@@XZ +; CHECK: struct S const volatile * __cdecl f5(void) + +?f6@@YAAAUS@@XZ +; CHECK: struct S & __cdecl f6(void) + +?f7@@YAQAUS@@XZ +; CHECK: struct S *const __cdecl f7(void) + +?f8@@YAPQS@@HXZ +; CHECK: int S::* __cdecl f8(void) + +?f9@@YAQQS@@HXZ +; CHECK: int S::*const __cdecl f9(void) + +; We print __restrict twice here. +?f10@@YAPIQS@@HXZ +; FIXME: int S::* __restrict __cdecl f10(void) + +; We print __restrict twice here. +?f11@@YAQIQS@@HXZ +; FIXME: int S::* __restrict __cdecl f11(void) + +?g1@@YAP6AHH@ZXZ +; CHECK: int (__cdecl * __cdecl g1(void))(int) + +?g2@@YAQ6AHH@ZXZ +; CHECK: int (__cdecl *const __cdecl g2(void))(int) + +?g3@@YAPAP6AHH@ZXZ +; CHECK: int (__cdecl ** __cdecl g3(void))(int) + +?g4@@YAPBQ6AHH@ZXZ +; CHECK: int (__cdecl *const * __cdecl g4(void))(int) + +?h1@@YAAIAHXZ +; CHECK: int &__restrict __cdecl h1(void) diff --git a/test/Demangle/ms-template-callback.test b/test/Demangle/ms-template-callback.test new file mode 100644 index 000000000000..88c4493d2bb6 --- /dev/null +++ b/test/Demangle/ms-template-callback.test @@ -0,0 +1,53 @@ +; These tests are based on clang/test/CodeGenCXX/mangle-ms-template-callback.cpp + +; RUN: llvm-undname < %s | FileCheck %s + +; CHECK-NOT: Invalid mangled name + +?callback_void@@3V?$C@$$A6AXXZ@@A +; CHECK: class C<void __cdecl(void)> callback_void + +?callback_void_volatile@@3V?$C@$$A6AXXZ@@C +; CHECK: class C<void __cdecl(void)> volatile callback_void_volatile + +?callback_int@@3V?$C@$$A6AHXZ@@A +; CHECK: C<int __cdecl(void)> callback_int + +?callback_Type@@3V?$C@$$A6A?AVType@@XZ@@A +; CHECK: C<class Type __cdecl(void)> callback_Type + +?callback_void_int@@3V?$C@$$A6AXH@Z@@A +; CHECK: C<void __cdecl(int)> callback_void_int + +?callback_int_int@@3V?$C@$$A6AHH@Z@@A +; CHECK: C<int __cdecl(int)> callback_int_int + +?callback_void_Type@@3V?$C@$$A6AXVType@@@Z@@A +; CHECK: C<void __cdecl(class Type)> callback_void_Type + +?foo@@YAXV?$C@$$A6AXXZ@@@Z +; CHECK: void __cdecl foo(class C<void __cdecl(void)>) + +?function@@YAXV?$C@$$A6AXXZ@@@Z +; CHECK: void __cdecl function(class C<void __cdecl(void)>) + +?function_pointer@@YAXV?$C@P6AXXZ@@@Z +; CHECK: void __cdecl function_pointer(class C<void (__cdecl *)(void)>) + +?member_pointer@@YAXV?$C@P8Z@@AEXXZ@@@Z +; CHECK: void __cdecl member_pointer(class C<void (__thiscall Z::*)(void)>) + +??$bar@P6AHH@Z@@YAXP6AHH@Z@Z +; CHECK: void __cdecl bar<int (__cdecl *)(int)>(int (__cdecl *)(int)) + +??$WrapFnPtr@$1?VoidFn@@YAXXZ@@YAXXZ +; CHECK: void __cdecl WrapFnPtr<&void __cdecl VoidFn(void)>(void) + +??$WrapFnRef@$1?VoidFn@@YAXXZ@@YAXXZ +; CHECK: void __cdecl WrapFnRef<&void __cdecl VoidFn(void)>(void) + +??$WrapFnPtr@$1?VoidStaticMethod@Thing@@SAXXZ@@YAXXZ +; CHECK: void __cdecl WrapFnPtr<&static void __cdecl Thing::VoidStaticMethod(void)>(void) + +??$WrapFnRef@$1?VoidStaticMethod@Thing@@SAXXZ@@YAXXZ +; CHECK: void __cdecl WrapFnRef<&static void __cdecl Thing::VoidStaticMethod(void)>(void) diff --git a/test/Instrumentation/InstrProfiling/linkage.ll b/test/Instrumentation/InstrProfiling/linkage.ll index 6cbc88f34519..97537579b176 100644 --- a/test/Instrumentation/InstrProfiling/linkage.ll +++ b/test/Instrumentation/InstrProfiling/linkage.ll @@ -1,13 +1,13 @@ ;; Check that runtime symbols get appropriate linkage. -; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -instrprof -S | FileCheck %s --check-prefix=OTHER --check-prefix=COMMON -; RUN: opt < %s -mtriple=x86_64-unknown-linux -instrprof -S | FileCheck %s --check-prefix=LINUX --check-prefix=COMMON -; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -passes=instrprof -S | FileCheck %s --check-prefix=OTHER --check-prefix=COMMON -; RUN: opt < %s -mtriple=x86_64-unknown-linux -passes=instrprof -S | FileCheck %s --check-prefix=LINUX --check-prefix=COMMON -; RUN: opt < %s -mtriple=x86_64-pc-win32-coff -instrprof -S | FileCheck %s --check-prefix=COFF -; RUN: opt < %s -mtriple=x86_64-pc-win32-coff -passes=instrprof -S | FileCheck %s --check-prefix=COFF +; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -instrprof -S | FileCheck %s --check-prefixes=COMMON,MACHO +; RUN: opt < %s -mtriple=x86_64-unknown-linux -instrprof -S | FileCheck %s --check-prefixes=COMMON,LINUX +; RUN: opt < %s -mtriple=x86_64-pc-win32-coff -instrprof -S | FileCheck %s --check-prefixes=COMMON,COFF +; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -passes=instrprof -S | FileCheck %s --check-prefixes=COMMON,MACHO +; RUN: opt < %s -mtriple=x86_64-unknown-linux -passes=instrprof -S | FileCheck %s --check-prefixes=COMMON,LINUX +; RUN: opt < %s -mtriple=x86_64-pc-win32-coff -passes=instrprof -S | FileCheck %s --check-prefixes=COMMON,COFF -; OTHER: @__llvm_profile_runtime = external global i32 +; MACHO: @__llvm_profile_runtime = external global i32 ; LINUX-NOT: @__llvm_profile_runtime = external global i32 @__profn_foo = hidden constant [3 x i8] c"foo" @@ -32,18 +32,15 @@ define weak void @foo_weak() { ; COMMON: @"__profc_linkage.ll:foo_internal" = internal global ; COMMON: @"__profd_linkage.ll:foo_internal" = internal global -; COFF: @"__profc_linkage.ll:foo_internal" = internal global -; COFF: @"__profd_linkage.ll:foo_internal" = internal global define internal void @foo_internal() { call void @llvm.instrprof.increment(i8* getelementptr inbounds ([23 x i8], [23 x i8]* @"__profn_linkage.ll:foo_internal", i32 0, i32 0), i64 0, i32 1, i32 0) ret void } ; COMMON: @__profc_foo_inline = linkonce_odr hidden global +; COFF-SAME: section ".lprfc", align 8 ; COMMON: @__profd_foo_inline = linkonce_odr hidden global -; FIXME: Should we put a comdat here? -; COFF: @__profc_foo_inline = linkonce_odr hidden global {{.*}}section ".lprfc", align 8 -; COFF: @__profd_foo_inline = linkonce_odr hidden global {{.*}}section ".lprfd", align 8 +; COFF-SAME: section ".lprfd", align 8 define linkonce_odr void @foo_inline() { call void @llvm.instrprof.increment(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @__profn_foo_inline, i32 0, i32 0), i64 0, i32 1, i32 0) ret void @@ -51,8 +48,8 @@ define linkonce_odr void @foo_inline() { ; LINUX: @__profc_foo_extern = linkonce_odr hidden global {{.*}}section "__llvm_prf_cnts", comdat($__profv_foo_extern), align 8 ; LINUX: @__profd_foo_extern = linkonce_odr hidden global {{.*}}section "__llvm_prf_data", comdat($__profv_foo_extern), align 8 -; OTHER: @__profc_foo_extern = linkonce_odr hidden global -; OTHER: @__profd_foo_extern = linkonce_odr hidden global +; MACHO: @__profc_foo_extern = linkonce_odr hidden global +; MACHO: @__profd_foo_extern = linkonce_odr hidden global ; COFF: @__profc_foo_extern = linkonce_odr hidden global {{.*}}section ".lprfc", comdat, align 8 ; COFF: @__profd_foo_extern = linkonce_odr hidden global {{.*}}section ".lprfd", comdat($__profc_foo_extern), align 8 define available_externally void @foo_extern() { @@ -62,10 +59,10 @@ define available_externally void @foo_extern() { declare void @llvm.instrprof.increment(i8*, i64, i32, i32) -; OTHER: define linkonce_odr hidden i32 @__llvm_profile_runtime_user() {{.*}} { -; OTHER: %[[REG:.*]] = load i32, i32* @__llvm_profile_runtime -; OTHER: ret i32 %[[REG]] -; OTHER: } +; MACHO: define linkonce_odr hidden i32 @__llvm_profile_runtime_user() {{.*}} { +; MACHO: %[[REG:.*]] = load i32, i32* @__llvm_profile_runtime +; MACHO: ret i32 %[[REG]] +; MACHO: } ; COFF: define linkonce_odr hidden i32 @__llvm_profile_runtime_user() {{.*}} comdat { ; LINUX-NOT: define linkonce_odr hidden i32 @__llvm_profile_runtime_user() {{.*}} { ; LINUX-NOT: %[[REG:.*]] = load i32, i32* @__llvm_profile_runtime diff --git a/test/Instrumentation/InstrProfiling/platform.ll b/test/Instrumentation/InstrProfiling/platform.ll index c0c711054ff1..dbdde08b8152 100644 --- a/test/Instrumentation/InstrProfiling/platform.ll +++ b/test/Instrumentation/InstrProfiling/platform.ll @@ -2,27 +2,29 @@ ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -instrprof -S | FileCheck %s -check-prefix=MACHO ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -passes=instrprof -S | FileCheck %s -check-prefix=MACHO -; RUN: opt < %s -mtriple=x86_64-unknown-linux -instrprof -S | FileCheck %s -check-prefix=LINUX -; RUN: opt < %s -mtriple=x86_64-unknown-linux -passes=instrprof -S | FileCheck %s -check-prefix=LINUX -; RUN: opt < %s -mtriple=x86_64-unknown-freebsd -instrprof -S | FileCheck %s -check-prefix=FREEBSD -; RUN: opt < %s -mtriple=x86_64-unknown-freebsd -passes=instrprof -S | FileCheck %s -check-prefix=FREEBSD -; RUN: opt < %s -mtriple=x86_64-scei-ps4 -instrprof -S | FileCheck %s -check-prefix=PS4 -; RUN: opt < %s -mtriple=x86_64-scei-ps4 -passes=instrprof -S | FileCheck %s -check-prefix=PS4 -; RUN: opt < %s -mtriple=x86_64-pc-solaris -instrprof -S | FileCheck %s -check-prefix=SOLARIS -; RUN: opt < %s -mtriple=x86_64-pc-solaris -passes=instrprof -S | FileCheck %s -check-prefix=SOLARIS +; RUN: opt < %s -mtriple=x86_64-unknown-linux -instrprof -S | FileCheck %s -check-prefixes=LINUX,ELF +; RUN: opt < %s -mtriple=x86_64-unknown-linux -passes=instrprof -S | FileCheck %s -check-prefixes=LINUX,ELF +; RUN: opt < %s -mtriple=x86_64-unknown-freebsd -instrprof -S | FileCheck %s -check-prefixes=FREEBSD,ELF +; RUN: opt < %s -mtriple=x86_64-unknown-freebsd -passes=instrprof -S | FileCheck %s -check-prefixes=FREEBSD,ELF +; RUN: opt < %s -mtriple=x86_64-scei-ps4 -instrprof -S | FileCheck %s -check-prefixes=PS4,ELF +; RUN: opt < %s -mtriple=x86_64-scei-ps4 -passes=instrprof -S | FileCheck %s -check-prefixes=PS4,ELF +; RUN: opt < %s -mtriple=x86_64-pc-solaris -instrprof -S | FileCheck %s -check-prefixes=SOLARIS,ELF +; RUN: opt < %s -mtriple=x86_64-pc-solaris -passes=instrprof -S | FileCheck %s -check-prefixes=SOLARIS,ELF +; RUN: opt < %s -mtriple=x86_64-pc-windows -instrprof -S | FileCheck %s -check-prefix=WINDOWS +; RUN: opt < %s -mtriple=x86_64-pc-windows -passes=instrprof -S | FileCheck %s -check-prefix=WINDOWS @__profn_foo = hidden constant [3 x i8] c"foo" ; MACHO-NOT: __profn_foo ; ELF-NOT: __profn_foo +; WINDOWS-NOT: __profn_foo ; MACHO: @__profc_foo = hidden global [1 x i64] zeroinitializer, section "__DATA,__llvm_prf_cnts", align 8 ; ELF: @__profc_foo = hidden global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", align 8 +; WINDOWS: @__profc_foo = hidden global [1 x i64] zeroinitializer, section ".lprfc", align 8 ; MACHO: @__profd_foo = hidden {{.*}}, section "__DATA,__llvm_prf_data,regular,live_support", align 8 -; LINUX: @__profd_foo = hidden {{.*}}, section "__llvm_prf_data", align 8 -; FREEBSD: @__profd_foo = hidden {{.*}}, section "__llvm_prf_data", align 8 -; PS4: @__profd_foo = hidden {{.*}}, section "__llvm_prf_data", align 8 -; SOLARIS: @__profd_foo = hidden {{.*}}, section "__llvm_prf_data", align 8 +; ELF: @__profd_foo = hidden {{.*}}, section "__llvm_prf_data", align 8 +; WINDOWS: @__profd_foo = hidden {{.*}}, section ".lprfd", align 8 ; ELF: @__llvm_prf_nm = private constant [{{.*}} x i8] c"{{.*}}", section "{{.*}}__llvm_prf_names" @@ -40,10 +42,21 @@ declare void @llvm.instrprof.increment(i8*, i64, i32, i32) ; LINUX-NOT: define internal void @__llvm_profile_register_functions ; FREEBSD-NOT: define internal void @__llvm_profile_register_functions ; PS4-NOT: define internal void @__llvm_profile_register_functions + +;; PR38340: When dynamic registration is used, we had a bug where we'd register +;; something that's not a __profd_* variable. + +; WINDOWS: define internal void @__llvm_profile_register_functions() +; WINDOWS-NOT: __llvm_profile_runtime_user +; WINDOWS: ret void + ; SOLARIS: define internal void @__llvm_profile_register_functions +; SOLARIS-NOT: __llvm_profile_runtime_user +; SOLARIS: ret void ; MACHO-NOT: define internal void @__llvm_profile_init ; LINUX-NOT: define internal void @__llvm_profile_init ; FREEBSD-NOT: define internal void @__llvm_profile_init ; PS4-NOT: define internal void @__llvm_profile_init ; SOLARIS: define internal void @__llvm_profile_init +; WINDOWS: define internal void @__llvm_profile_init diff --git a/test/MC/AArch64/SVE/abs.s b/test/MC/AArch64/SVE/abs.s index 6341c4f4885d..460f846cdc03 100644 --- a/test/MC/AArch64/SVE/abs.s +++ b/test/MC/AArch64/SVE/abs.s @@ -54,3 +54,31 @@ abs z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd6,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d6 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +abs z4.d, p7/m, z31.d +// CHECK-INST: abs z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d6 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +abs z4.d, p7/m, z31.d +// CHECK-INST: abs z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d6 04 <unknown> diff --git a/test/MC/AArch64/SVE/add-diagnostics.s b/test/MC/AArch64/SVE/add-diagnostics.s index 23042b6708c0..6d95a645f068 100644 --- a/test/MC/AArch64/SVE/add-diagnostics.s +++ b/test/MC/AArch64/SVE/add-diagnostics.s @@ -144,3 +144,25 @@ add z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: add z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +add z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: add z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.s, p0/z, z30.s +add z23.s, z13.s, z8.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: add z23.s, z13.s, z8.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +add z23.s, z13.s, z8.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: add z23.s, z13.s, z8.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/add.s b/test/MC/AArch64/SVE/add.s index f477eb956871..2064181d18d2 100644 --- a/test/MC/AArch64/SVE/add.s +++ b/test/MC/AArch64/SVE/add.s @@ -283,3 +283,43 @@ add z31.d, z31.d, #65280 // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e0 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.b, p7/z, z6.b +// CHECK-INST: movprfx z4.b, p7/z, z6.b +// CHECK-ENCODING: [0xc4,0x3c,0x10,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c 10 04 <unknown> + +add z4.b, p7/m, z4.b, z31.b +// CHECK-INST: add z4.b, p7/m, z4.b, z31.b +// CHECK-ENCODING: [0xe4,0x1f,0x00,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f 00 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +add z4.b, p7/m, z4.b, z31.b +// CHECK-INST: add z4.b, p7/m, z4.b, z31.b +// CHECK-ENCODING: [0xe4,0x1f,0x00,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f 00 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +add z31.d, z31.d, #65280 +// CHECK-INST: add z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe0,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e0 25 <unknown> diff --git a/test/MC/AArch64/SVE/adr-diagnostics.s b/test/MC/AArch64/SVE/adr-diagnostics.s index 99890ff79304..2bab1f7faeaa 100644 --- a/test/MC/AArch64/SVE/adr-diagnostics.s +++ b/test/MC/AArch64/SVE/adr-diagnostics.s @@ -57,3 +57,19 @@ adr z0.d, [z0.d, z0.d, sxtw #4] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' // CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #4] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +adr z0.d, [z0.d, z0.d, sxtw #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +adr z0.d, [z0.d, z0.d, sxtw #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/and-diagnostics.s b/test/MC/AArch64/SVE/and-diagnostics.s index 2ea6b3eb2721..ff7332e60e70 100644 --- a/test/MC/AArch64/SVE/and-diagnostics.s +++ b/test/MC/AArch64/SVE/and-diagnostics.s @@ -92,3 +92,25 @@ and p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: and p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +and z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: and z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +and z23.d, z13.d, z8.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: and z23.d, z13.d, z8.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +and z23.d, z13.d, z8.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: and z23.d, z13.d, z8.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/and.s b/test/MC/AArch64/SVE/and.s index 88e2439c44ed..0d0edc73e8f5 100644 --- a/test/MC/AArch64/SVE/and.s +++ b/test/MC/AArch64/SVE/and.s @@ -108,3 +108,43 @@ and p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7d 0f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +and z4.d, p7/m, z4.d, z31.d +// CHECK-INST: and z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f da 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +and z4.d, p7/m, z4.d, z31.d +// CHECK-INST: and z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f da 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +and z0.d, z0.d, #0x6 +// CHECK-INST: and z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x83,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 83 05 <unknown> diff --git a/test/MC/AArch64/SVE/andv-diagnostics.s b/test/MC/AArch64/SVE/andv-diagnostics.s index 60a42f826049..2048d77ff900 100644 --- a/test/MC/AArch64/SVE/andv-diagnostics.s +++ b/test/MC/AArch64/SVE/andv-diagnostics.s @@ -31,4 +31,19 @@ andv v0.2d, p7, z31.d andv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: andv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +andv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: andv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +andv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: andv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/asr-diagnostics.s b/test/MC/AArch64/SVE/asr-diagnostics.s index a4811324d264..9cec835dbe2f 100644 --- a/test/MC/AArch64/SVE/asr-diagnostics.s +++ b/test/MC/AArch64/SVE/asr-diagnostics.s @@ -122,3 +122,31 @@ asr z0.b, p8/m, z0.b, z1.b // CHECK-NEXT: asr z0.b, p8/m, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +asr z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: asr z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +asr z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: asr z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +asr z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: asr z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +asr z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: asr z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/asr.s b/test/MC/AArch64/SVE/asr.s index 7204a27155d4..d514eda2af13 100644 --- a/test/MC/AArch64/SVE/asr.s +++ b/test/MC/AArch64/SVE/asr.s @@ -162,3 +162,55 @@ asr z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x80,0xa2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 80 a2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 <unknown> + +asr z31.d, p0/m, z31.d, #64 +// CHECK-INST: asr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x80,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 80 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +asr z31.d, p0/m, z31.d, #64 +// CHECK-INST: asr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x80,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 80 04 <unknown> + +movprfx z0.s, p0/z, z7.s +// CHECK-INST: movprfx z0.s, p0/z, z7.s +// CHECK-ENCODING: [0xe0,0x20,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 90 04 <unknown> + +asr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: asr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x98,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 98 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +asr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: asr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x98,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 98 04 <unknown> diff --git a/test/MC/AArch64/SVE/asrd.s b/test/MC/AArch64/SVE/asrd.s index 69805517c1cb..78fbbba5b338 100644 --- a/test/MC/AArch64/SVE/asrd.s +++ b/test/MC/AArch64/SVE/asrd.s @@ -54,3 +54,31 @@ asrd z31.d, p0/m, z31.d, #64 // CHECK-ENCODING: [0x1f,0x80,0x84,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 1f 80 84 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 <unknown> + +asrd z31.d, p0/m, z31.d, #64 +// CHECK-INST: asrd z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x84,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 84 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +asrd z31.d, p0/m, z31.d, #64 +// CHECK-INST: asrd z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x84,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 84 04 <unknown> diff --git a/test/MC/AArch64/SVE/asrr.s b/test/MC/AArch64/SVE/asrr.s index e7f7cc5afa2c..f9cc7ea6f8ee 100644 --- a/test/MC/AArch64/SVE/asrr.s +++ b/test/MC/AArch64/SVE/asrr.s @@ -30,3 +30,31 @@ asrr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd4,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 d4 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +asrr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d4 04 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +asrr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: asrr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d4 04 <unknown> diff --git a/test/MC/AArch64/SVE/bic-diagnostics.s b/test/MC/AArch64/SVE/bic-diagnostics.s index 61d0231e4cf4..abdd52028d01 100644 --- a/test/MC/AArch64/SVE/bic-diagnostics.s +++ b/test/MC/AArch64/SVE/bic-diagnostics.s @@ -92,3 +92,25 @@ bic p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: bic p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +bic z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: bic z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +bic z23.d, z13.d, z8.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bic z23.d, z13.d, z8.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +bic z23.d, z13.d, z8.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bic z23.d, z13.d, z8.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/bic.s b/test/MC/AArch64/SVE/bic.s index bd19fcd9fcfd..c9e6d9b82665 100644 --- a/test/MC/AArch64/SVE/bic.s +++ b/test/MC/AArch64/SVE/bic.s @@ -102,3 +102,43 @@ bic p0.b, p0/z, p0.b, p0.b // CHECK-ENCODING: [0x10,0x40,0x00,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 10 40 00 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +bic z4.d, p7/m, z4.d, z31.d +// CHECK-INST: bic z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f db 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +bic z4.d, p7/m, z4.d, z31.d +// CHECK-INST: bic z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f db 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +bic z0.d, z0.d, #0x6 +// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x83,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 83 05 <unknown> diff --git a/test/MC/AArch64/SVE/brka-diagnostics.s b/test/MC/AArch64/SVE/brka-diagnostics.s new file mode 100644 index 000000000000..140ac004fe07 --- /dev/null +++ b/test/MC/AArch64/SVE/brka-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brka p0.s, p15/z, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brka p0.s, p15/z, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brka.s b/test/MC/AArch64/SVE/brka.s new file mode 100644 index 000000000000..d87e7632e3fd --- /dev/null +++ b/test/MC/AArch64/SVE/brka.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brka p0.b, p15/m, p15.b +// CHECK-INST: brka p0.b, p15/m, p15.b +// CHECK-ENCODING: [0xf0,0x7d,0x10,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: f0 7d 10 25 <unknown> + +brka p0.b, p15/z, p15.b +// CHECK-INST: brka p0.b, p15/z, p15.b +// CHECK-ENCODING: [0xe0,0x7d,0x10,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 7d 10 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkas-diagnostics.s b/test/MC/AArch64/SVE/brkas-diagnostics.s new file mode 100644 index 000000000000..14fe7cf6ba6d --- /dev/null +++ b/test/MC/AArch64/SVE/brkas-diagnostics.s @@ -0,0 +1,19 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkas p0.s, p15/z, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkas p0.s, p15/z, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// flag-setting variant does not have merging predication + +brkas p0.b, p15/m, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: brkas p0.b, p15/m, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkas.s b/test/MC/AArch64/SVE/brkas.s new file mode 100644 index 000000000000..f75c5bc8069d --- /dev/null +++ b/test/MC/AArch64/SVE/brkas.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkas p0.b, p15/z, p15.b +// CHECK-INST: brkas p0.b, p15/z, p15.b +// CHECK-ENCODING: [0xe0,0x7d,0x50,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 7d 50 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkb-diagnostics.s b/test/MC/AArch64/SVE/brkb-diagnostics.s new file mode 100644 index 000000000000..7f87f15d3885 --- /dev/null +++ b/test/MC/AArch64/SVE/brkb-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkb p0.s, p15/z, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkb p0.s, p15/z, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkb.s b/test/MC/AArch64/SVE/brkb.s new file mode 100644 index 000000000000..393d29449588 --- /dev/null +++ b/test/MC/AArch64/SVE/brkb.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkb p0.b, p15/m, p15.b +// CHECK-INST: brkb p0.b, p15/m, p15.b +// CHECK-ENCODING: [0xf0,0x7d,0x90,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: f0 7d 90 25 <unknown> + +brkb p0.b, p15/z, p15.b +// CHECK-INST: brkb p0.b, p15/z, p15.b +// CHECK-ENCODING: [0xe0,0x7d,0x90,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 7d 90 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkbs-diagnostics.s b/test/MC/AArch64/SVE/brkbs-diagnostics.s new file mode 100644 index 000000000000..bcb9a6464b1e --- /dev/null +++ b/test/MC/AArch64/SVE/brkbs-diagnostics.s @@ -0,0 +1,19 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkbs p0.s, p15/z, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkbs p0.s, p15/z, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// flag-setting variant does not have merging predication + +brkbs p0.b, p15/m, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: brkbs p0.b, p15/m, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkbs.s b/test/MC/AArch64/SVE/brkbs.s new file mode 100644 index 000000000000..708ec91345c3 --- /dev/null +++ b/test/MC/AArch64/SVE/brkbs.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkbs p0.b, p15/z, p15.b +// CHECK-INST: brkbs p0.b, p15/z, p15.b +// CHECK-ENCODING: [0xe0,0x7d,0xd0,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 7d d0 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkn-diagnostics.s b/test/MC/AArch64/SVE/brkn-diagnostics.s new file mode 100644 index 000000000000..87587fbe373c --- /dev/null +++ b/test/MC/AArch64/SVE/brkn-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// BRKN only supports merging predication + +brkn p0.b, p15/m, p1.b, p0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: brkn p0.b, p15/m, p1.b, p0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Check tied operand constraints + +brkn p0.b, p15/z, p1.b, p1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: brkn p0.b, p15/z, p1.b, p1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkn p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkn p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkn.s b/test/MC/AArch64/SVE/brkn.s new file mode 100644 index 000000000000..8494e547732f --- /dev/null +++ b/test/MC/AArch64/SVE/brkn.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkn p0.b, p15/z, p1.b, p0.b +// CHECK-INST: brkn p0.b, p15/z, p1.b, p0.b +// CHECK-ENCODING: [0x20,0x7c,0x18,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c 18 25 <unknown> + +brkn p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkn p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x7d,0x18,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 7d 18 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkns-diagnostics.s b/test/MC/AArch64/SVE/brkns-diagnostics.s new file mode 100644 index 000000000000..c22d4cdb0d8d --- /dev/null +++ b/test/MC/AArch64/SVE/brkns-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// BRKN only supports merging predication + +brkns p0.b, p15/m, p1.b, p0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: brkns p0.b, p15/m, p1.b, p0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Check tied operand constraints + +brkns p0.b, p15/z, p1.b, p1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: brkns p0.b, p15/z, p1.b, p1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +brkns p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkns p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkns.s b/test/MC/AArch64/SVE/brkns.s new file mode 100644 index 000000000000..6fd47f69c91f --- /dev/null +++ b/test/MC/AArch64/SVE/brkns.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkns p0.b, p15/z, p1.b, p0.b +// CHECK-INST: brkns p0.b, p15/z, p1.b, p0.b +// CHECK-ENCODING: [0x20,0x7c,0x58,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c 58 25 <unknown> + +brkns p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkns p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x7d,0x58,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 7d 58 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkpa-diagnostics.s b/test/MC/AArch64/SVE/brkpa-diagnostics.s new file mode 100644 index 000000000000..d7693c62a279 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpa-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +brkpa p15.b, p15/m, p15.b, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: brkpa p15.b, p15/m, p15.b, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +brkpa p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkpa p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkpa.s b/test/MC/AArch64/SVE/brkpa.s new file mode 100644 index 000000000000..c283ee2fdea6 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpa.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkpa p0.b, p15/z, p1.b, p2.b +// CHECK-INST: brkpa p0.b, p15/z, p1.b, p2.b +// CHECK-ENCODING: [0x20,0xfc,0x02,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc 02 25 <unknown> + +brkpa p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkpa p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xef,0xfd,0x0f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef fd 0f 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkpas-diagnostics.s b/test/MC/AArch64/SVE/brkpas-diagnostics.s new file mode 100644 index 000000000000..a88e11075c74 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpas-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +brkpas p15.b, p15/m, p15.b, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: brkpas p15.b, p15/m, p15.b, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +brkpas p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkpas p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkpas.s b/test/MC/AArch64/SVE/brkpas.s new file mode 100644 index 000000000000..81d590096681 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpas.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkpas p0.b, p15/z, p1.b, p2.b +// CHECK-INST: brkpas p0.b, p15/z, p1.b, p2.b +// CHECK-ENCODING: [0x20,0xfc,0x42,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc 42 25 <unknown> + +brkpas p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkpas p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xef,0xfd,0x4f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef fd 4f 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkpb-diagnostics.s b/test/MC/AArch64/SVE/brkpb-diagnostics.s new file mode 100644 index 000000000000..e03f0bfbf93d --- /dev/null +++ b/test/MC/AArch64/SVE/brkpb-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +brkpb p15.b, p15/m, p15.b, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: brkpb p15.b, p15/m, p15.b, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +brkpb p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkpb p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkpb.s b/test/MC/AArch64/SVE/brkpb.s new file mode 100644 index 000000000000..039e71f5e322 --- /dev/null +++ b/test/MC/AArch64/SVE/brkpb.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkpb p0.b, p15/z, p1.b, p2.b +// CHECK-INST: brkpb p0.b, p15/z, p1.b, p2.b +// CHECK-ENCODING: [0x30,0xfc,0x02,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 30 fc 02 25 <unknown> + +brkpb p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkpb p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xff,0xfd,0x0f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff fd 0f 25 <unknown> diff --git a/test/MC/AArch64/SVE/brkpbs-diagnostics.s b/test/MC/AArch64/SVE/brkpbs-diagnostics.s new file mode 100644 index 000000000000..25e230e2e63c --- /dev/null +++ b/test/MC/AArch64/SVE/brkpbs-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +brkpbs p15.b, p15/m, p15.b, p15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: brkpbs p15.b, p15/m, p15.b, p15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +brkpbs p15.s, p15/z, p15.s, p15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: brkpbs p15.s, p15/z, p15.s, p15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/brkpbs.s b/test/MC/AArch64/SVE/brkpbs.s new file mode 100644 index 000000000000..1d44178659dd --- /dev/null +++ b/test/MC/AArch64/SVE/brkpbs.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +brkpbs p0.b, p15/z, p1.b, p2.b +// CHECK-INST: brkpbs p0.b, p15/z, p1.b, p2.b +// CHECK-ENCODING: [0x30,0xfc,0x42,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 30 fc 42 25 <unknown> + +brkpbs p15.b, p15/z, p15.b, p15.b +// CHECK-INST: brkpbs p15.b, p15/z, p15.b, p15.b +// CHECK-ENCODING: [0xff,0xfd,0x4f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff fd 4f 25 <unknown> diff --git a/test/MC/AArch64/SVE/clasta-diagnostics.s b/test/MC/AArch64/SVE/clasta-diagnostics.s index cfc1db15b2cd..c0924bf689c7 100644 --- a/test/MC/AArch64/SVE/clasta-diagnostics.s +++ b/test/MC/AArch64/SVE/clasta-diagnostics.s @@ -77,3 +77,37 @@ clasta z0.d, p7, z0.d, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: clasta z0.d, p7, z0.d, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +clasta x0, p7, x0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clasta x0, p7, x0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +clasta x0, p7, x0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clasta x0, p7, x0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p7/z, z6.d +clasta d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clasta d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +clasta d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clasta d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p7/z, z7.d +clasta z0.d, p7, z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: clasta z0.d, p7, z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/clasta.s b/test/MC/AArch64/SVE/clasta.s index 3e120310298b..05f6f92afac9 100644 --- a/test/MC/AArch64/SVE/clasta.s +++ b/test/MC/AArch64/SVE/clasta.s @@ -78,3 +78,19 @@ clasta z0.d, p7, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e8 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +clasta z0.d, p7, z0.d, z31.d +// CHECK-INST: clasta z0.d, p7, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e8 05 <unknown> diff --git a/test/MC/AArch64/SVE/clastb-diagnostics.s b/test/MC/AArch64/SVE/clastb-diagnostics.s index 62f696458c3e..0f0f677ec225 100644 --- a/test/MC/AArch64/SVE/clastb-diagnostics.s +++ b/test/MC/AArch64/SVE/clastb-diagnostics.s @@ -77,3 +77,37 @@ clastb z0.d, p7, z0.d, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: clastb z0.d, p7, z0.d, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +clastb x0, p7, x0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clastb x0, p7, x0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +clastb x0, p7, x0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clastb x0, p7, x0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p7/z, z6.d +clastb d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clastb d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +clastb d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: clastb d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p7/z, z7.d +clastb z0.d, p7, z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: clastb z0.d, p7, z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/clastb.s b/test/MC/AArch64/SVE/clastb.s index 654ab1133e78..6785edb87cee 100644 --- a/test/MC/AArch64/SVE/clastb.s +++ b/test/MC/AArch64/SVE/clastb.s @@ -78,3 +78,19 @@ clastb z0.d, p7, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e9 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +clastb z0.d, p7, z0.d, z31.d +// CHECK-INST: clastb z0.d, p7, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e9 05 <unknown> diff --git a/test/MC/AArch64/SVE/cls.s b/test/MC/AArch64/SVE/cls.s index db1c0b2a7cea..e860a7b40401 100644 --- a/test/MC/AArch64/SVE/cls.s +++ b/test/MC/AArch64/SVE/cls.s @@ -30,3 +30,31 @@ cls z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd8,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d8 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +cls z4.d, p7/m, z31.d +// CHECK-INST: cls z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d8 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +cls z4.d, p7/m, z31.d +// CHECK-INST: cls z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d8 04 <unknown> diff --git a/test/MC/AArch64/SVE/clz.s b/test/MC/AArch64/SVE/clz.s index 76e9d1bf83f4..ff69f383e70c 100644 --- a/test/MC/AArch64/SVE/clz.s +++ b/test/MC/AArch64/SVE/clz.s @@ -30,3 +30,31 @@ clz z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd9,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d9 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +clz z4.d, p7/m, z31.d +// CHECK-INST: clz z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d9 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +clz z4.d, p7/m, z31.d +// CHECK-INST: clz z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d9 04 <unknown> diff --git a/test/MC/AArch64/SVE/cmpeq-diagnostics.s b/test/MC/AArch64/SVE/cmpeq-diagnostics.s index bcda4ac02821..fbf292ec8872 100644 --- a/test/MC/AArch64/SVE/cmpeq-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpeq-diagnostics.s @@ -74,3 +74,31 @@ cmpeq p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpeq p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpeq p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpeq p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpeq p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmpge-diagnostics.s b/test/MC/AArch64/SVE/cmpge-diagnostics.s index 49520ed5ecd5..44ab473808e7 100644 --- a/test/MC/AArch64/SVE/cmpge-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpge-diagnostics.s @@ -74,3 +74,31 @@ cmpge p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmpge p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpge p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpge p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpge p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpge p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpge p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpge p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmpgt-diagnostics.s b/test/MC/AArch64/SVE/cmpgt-diagnostics.s index fcc972c41011..1745aab97ea7 100644 --- a/test/MC/AArch64/SVE/cmpgt-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpgt-diagnostics.s @@ -74,3 +74,31 @@ cmpgt p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpgt p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpgt p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpgt p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpgt p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmphi-diagnostics.s b/test/MC/AArch64/SVE/cmphi-diagnostics.s index b0b3010183f3..5d7c0d82f5bf 100644 --- a/test/MC/AArch64/SVE/cmphi-diagnostics.s +++ b/test/MC/AArch64/SVE/cmphi-diagnostics.s @@ -74,3 +74,31 @@ cmphi p0.s, p0/z, z0.s, #128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK-NEXT: cmphi p0.s, p0/z, z0.s, #128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmphi p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmphi p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphi p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmphi p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmphi p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmphs-diagnostics.s b/test/MC/AArch64/SVE/cmphs-diagnostics.s index 955c1af1b8d9..5bfff46ee406 100644 --- a/test/MC/AArch64/SVE/cmphs-diagnostics.s +++ b/test/MC/AArch64/SVE/cmphs-diagnostics.s @@ -74,3 +74,31 @@ cmphs p0.s, p0/z, z0.s, #128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmphs p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphs p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmphs p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphs p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmphs p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmphs p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmple-diagnostics.s b/test/MC/AArch64/SVE/cmple-diagnostics.s index e40ab1419d5d..d03d2153fd69 100644 --- a/test/MC/AArch64/SVE/cmple-diagnostics.s +++ b/test/MC/AArch64/SVE/cmple-diagnostics.s @@ -74,3 +74,31 @@ cmple p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmple p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmple p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmple p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmple p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmple p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmple p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmple p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmple p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmple p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmplo-diagnostics.s b/test/MC/AArch64/SVE/cmplo-diagnostics.s index 825ad13b4dd7..ecbed6081ac2 100644 --- a/test/MC/AArch64/SVE/cmplo-diagnostics.s +++ b/test/MC/AArch64/SVE/cmplo-diagnostics.s @@ -74,3 +74,31 @@ cmplo p0.s, p0/z, z0.s, #128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK-NEXT: cmplo p0.s, p0/z, z0.s, #128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmplo p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplo p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmplo p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplo p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmplo p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmplo p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplo p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmpls-diagnostics.s b/test/MC/AArch64/SVE/cmpls-diagnostics.s index 349a1b3ccf68..c42ce36ae3c9 100644 --- a/test/MC/AArch64/SVE/cmpls-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpls-diagnostics.s @@ -74,3 +74,31 @@ cmpls p0.s, p0/z, z0.s, #128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 127]. // CHECK-NEXT: cmpls p0.s, p0/z, z0.s, #128 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpls p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpls p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpls p0.d, p0/z, z0.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpls p0.d, p0/z, z0.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpls p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpls p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpls p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmplt-diagnostics.s b/test/MC/AArch64/SVE/cmplt-diagnostics.s index 7878ed56d409..0f023e0f866f 100644 --- a/test/MC/AArch64/SVE/cmplt-diagnostics.s +++ b/test/MC/AArch64/SVE/cmplt-diagnostics.s @@ -74,3 +74,31 @@ cmplt p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmplt p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmplt p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplt p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmplt p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplt p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmplt p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmplt p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmplt p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cmpne-diagnostics.s b/test/MC/AArch64/SVE/cmpne-diagnostics.s index 98bd8b7857b7..74c74c7eaa7c 100644 --- a/test/MC/AArch64/SVE/cmpne-diagnostics.s +++ b/test/MC/AArch64/SVE/cmpne-diagnostics.s @@ -74,3 +74,31 @@ cmpne p0.s, p0/z, z0.s, #16 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cmpne p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpne p0.d, p0/z, z0.d, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpne p0.d, p0/z, z0.d, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmpne p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +cmpne p0.s, p0/z, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cnot.s b/test/MC/AArch64/SVE/cnot.s index 06ac6c8660df..83f21816c859 100644 --- a/test/MC/AArch64/SVE/cnot.s +++ b/test/MC/AArch64/SVE/cnot.s @@ -30,3 +30,31 @@ cnot z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdb,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf db 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +cnot z4.d, p7/m, z31.d +// CHECK-INST: cnot z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf db 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +cnot z4.d, p7/m, z31.d +// CHECK-INST: cnot z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf db 04 <unknown> diff --git a/test/MC/AArch64/SVE/cnt.s b/test/MC/AArch64/SVE/cnt.s index 4a81b1a9a9b9..86373cbe08e3 100644 --- a/test/MC/AArch64/SVE/cnt.s +++ b/test/MC/AArch64/SVE/cnt.s @@ -30,3 +30,31 @@ cnt z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xda,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf da 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +cnt z4.d, p7/m, z31.d +// CHECK-INST: cnt z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf da 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +cnt z4.d, p7/m, z31.d +// CHECK-INST: cnt z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf da 04 <unknown> diff --git a/test/MC/AArch64/SVE/compact-diagnostics.s b/test/MC/AArch64/SVE/compact-diagnostics.s index 817e97a83c5a..d252f60e55af 100644 --- a/test/MC/AArch64/SVE/compact-diagnostics.s +++ b/test/MC/AArch64/SVE/compact-diagnostics.s @@ -26,3 +26,19 @@ compact z31.h, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: compact z31.h, p7, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +compact z31.d, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: compact z31.d, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +compact z31.d, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: compact z31.d, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/cpy.s b/test/MC/AArch64/SVE/cpy.s index 7d11d9288214..968bc5ddfe8d 100644 --- a/test/MC/AArch64/SVE/cpy.s +++ b/test/MC/AArch64/SVE/cpy.s @@ -275,3 +275,79 @@ cpy z21.d, p15/m, #-128, lsl #8 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 15 70 df 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +cpy z31.d, p7/m, sp +// CHECK-INST: mov z31.d, p7/m, sp +// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf e8 05 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +cpy z31.d, p7/m, sp +// CHECK-INST: mov z31.d, p7/m, sp +// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf e8 05 <unknown> + +movprfx z21.d, p7/z, z28.d +// CHECK-INST: movprfx z21.d, p7/z, z28.d +// CHECK-ENCODING: [0x95,0x3f,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 3f d0 04 <unknown> + +cpy z21.d, p7/m, #-128, lsl #8 +// CHECK-INST: mov z21.d, p7/m, #-32768 +// CHECK-ENCODING: [0x15,0x70,0xd7,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 15 70 d7 05 <unknown> + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 <unknown> + +cpy z21.d, p15/m, #-128, lsl #8 +// CHECK-INST: mov z21.d, p15/m, #-32768 +// CHECK-ENCODING: [0x15,0x70,0xdf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 15 70 df 05 <unknown> + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +cpy z4.d, p7/m, d31 +// CHECK-INST: mov z4.d, p7/m, d31 +// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f e0 05 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +cpy z4.d, p7/m, d31 +// CHECK-INST: mov z4.d, p7/m, d31 +// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f e0 05 <unknown> diff --git a/test/MC/AArch64/SVE/ctermeq-diagnostics.s b/test/MC/AArch64/SVE/ctermeq-diagnostics.s new file mode 100644 index 000000000000..74afc10cb572 --- /dev/null +++ b/test/MC/AArch64/SVE/ctermeq-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +ctermeq w30, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermeq w30, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermeq w30, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermeq w30, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermeq wsp, w30 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermeq wsp, w30 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermeq x0, w30 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermeq x0, w30 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ctermeq.s b/test/MC/AArch64/SVE/ctermeq.s new file mode 100644 index 000000000000..3dfac002350a --- /dev/null +++ b/test/MC/AArch64/SVE/ctermeq.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ctermeq w30, wzr +// CHECK-INST: ctermeq w30, wzr +// CHECK-ENCODING: [0xc0,0x23,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c0 23 bf 25 <unknown> + +ctermeq wzr, w30 +// CHECK-INST: ctermeq wzr, w30 +// CHECK-ENCODING: [0xe0,0x23,0xbe,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 23 be 25 <unknown> + +ctermeq x30, xzr +// CHECK-INST: ctermeq x30, xzr +// CHECK-ENCODING: [0xc0,0x23,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c0 23 ff 25 <unknown> + +ctermeq xzr, x30 +// CHECK-INST: ctermeq xzr, x30 +// CHECK-ENCODING: [0xe0,0x23,0xfe,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 23 fe 25 <unknown> diff --git a/test/MC/AArch64/SVE/ctermne-diagnostics.s b/test/MC/AArch64/SVE/ctermne-diagnostics.s new file mode 100644 index 000000000000..96346f44449f --- /dev/null +++ b/test/MC/AArch64/SVE/ctermne-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +ctermne w30, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermne w30, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermne w30, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermne w30, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermne wsp, w30 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermne wsp, w30 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ctermne x0, w30 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ctermne x0, w30 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ctermne.s b/test/MC/AArch64/SVE/ctermne.s new file mode 100644 index 000000000000..54dc5e23a9c5 --- /dev/null +++ b/test/MC/AArch64/SVE/ctermne.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ctermne w30, wzr +// CHECK-INST: ctermne w30, wzr +// CHECK-ENCODING: [0xd0,0x23,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: d0 23 bf 25 <unknown> + +ctermne wzr, w30 +// CHECK-INST: ctermne wzr, w30 +// CHECK-ENCODING: [0xf0,0x23,0xbe,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: f0 23 be 25 <unknown> + +ctermne x30, xzr +// CHECK-INST: ctermne x30, xzr +// CHECK-ENCODING: [0xd0,0x23,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: d0 23 ff 25 <unknown> + +ctermne xzr, x30 +// CHECK-INST: ctermne xzr, x30 +// CHECK-ENCODING: [0xf0,0x23,0xfe,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: f0 23 fe 25 <unknown> diff --git a/test/MC/AArch64/SVE/decp-diagnostics.s b/test/MC/AArch64/SVE/decp-diagnostics.s index 2c8cc4293319..b1e4c9144cca 100644 --- a/test/MC/AArch64/SVE/decp-diagnostics.s +++ b/test/MC/AArch64/SVE/decp-diagnostics.s @@ -36,3 +36,13 @@ decp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: decp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +decp z31.d, p7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: decp z31.d, p7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/decp.s b/test/MC/AArch64/SVE/decp.s index 4866c766aaff..8bbe726a422d 100644 --- a/test/MC/AArch64/SVE/decp.s +++ b/test/MC/AArch64/SVE/decp.s @@ -72,3 +72,19 @@ decp z31.d, p15 // CHECK-ENCODING: [0xff,0x81,0xed,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 81 ed 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +decp z31.d, p15 +// CHECK-INST: decp z31.d, p15 +// CHECK-ENCODING: [0xff,0x81,0xed,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 81 ed 25 <unknown> diff --git a/test/MC/AArch64/SVE/dup-diagnostics.s b/test/MC/AArch64/SVE/dup-diagnostics.s index 6636708c457e..f97ac83aae09 100644 --- a/test/MC/AArch64/SVE/dup-diagnostics.s +++ b/test/MC/AArch64/SVE/dup-diagnostics.s @@ -215,3 +215,43 @@ dup z24.q, z21.q[4] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. // CHECK-NEXT: dup z24.q, z21.q[4] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +dup z31.b, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z31.b, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +dup z31.b, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z31.b, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21.d, p0/z, z28.d +dup z21.d, #32512 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z21.d, #32512 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +dup z21.d, #32512 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z21.d, #32512 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +dup z31.d, z31.d[7] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z31.d, z31.d[7] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +dup z31.d, z31.d[7] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dup z31.d, z31.d[7] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/dupm-diagnostics.s b/test/MC/AArch64/SVE/dupm-diagnostics.s index cb2277a1f871..f82c849437b0 100644 --- a/test/MC/AArch64/SVE/dupm-diagnostics.s +++ b/test/MC/AArch64/SVE/dupm-diagnostics.s @@ -37,3 +37,19 @@ dupm z15.d, #0xfffffffffffffffa // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate // CHECK-NEXT: dupm z15.d, #0xfffffffffffffffa // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +dupm z0.d, #0xfffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dupm z0.d, #0xfffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +dupm z0.d, #0xfffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: dupm z0.d, #0xfffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/eon-diagnostics.s b/test/MC/AArch64/SVE/eon-diagnostics.s index 5b6f59ce23de..ffdd7222cb20 100644 --- a/test/MC/AArch64/SVE/eon-diagnostics.s +++ b/test/MC/AArch64/SVE/eon-diagnostics.s @@ -50,3 +50,13 @@ eon z7.d, z8.d, #254 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK-NEXT: eon z7.d, z8.d, #254 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +eon z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: eon z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/eon.s b/test/MC/AArch64/SVE/eon.s index 9f6dd2655061..d03755d5a94e 100644 --- a/test/MC/AArch64/SVE/eon.s +++ b/test/MC/AArch64/SVE/eon.s @@ -54,3 +54,19 @@ eon z0.d, z0.d, #0x6 // CHECK-ENCODING: [0xa0,0xef,0x43,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: a0 ef 43 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +eon z0.d, z0.d, #0x6 +// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x43,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 43 05 <unknown> diff --git a/test/MC/AArch64/SVE/eor-diagnostics.s b/test/MC/AArch64/SVE/eor-diagnostics.s index dbed470e7bd4..e8d28737db22 100644 --- a/test/MC/AArch64/SVE/eor-diagnostics.s +++ b/test/MC/AArch64/SVE/eor-diagnostics.s @@ -92,3 +92,25 @@ eor p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: eor p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +eor z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: eor z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +eor z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: eor z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +eor z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: eor z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/eor.s b/test/MC/AArch64/SVE/eor.s index 8c68ec9c7835..f7b4247ad80b 100644 --- a/test/MC/AArch64/SVE/eor.s +++ b/test/MC/AArch64/SVE/eor.s @@ -108,3 +108,43 @@ eor p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7f 0f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.b, p7/z, z6.b +// CHECK-INST: movprfx z4.b, p7/z, z6.b +// CHECK-ENCODING: [0xc4,0x3c,0x10,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c 10 04 <unknown> + +eor z4.b, p7/m, z4.b, z31.b +// CHECK-INST: eor z4.b, p7/m, z4.b, z31.b +// CHECK-ENCODING: [0xe4,0x1f,0x19,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f 19 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +eor z4.b, p7/m, z4.b, z31.b +// CHECK-INST: eor z4.b, p7/m, z4.b, z31.b +// CHECK-ENCODING: [0xe4,0x1f,0x19,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f 19 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +eor z0.d, z0.d, #0x6 +// CHECK-INST: eor z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x43,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 43 05 <unknown> diff --git a/test/MC/AArch64/SVE/eorv-diagnostics.s b/test/MC/AArch64/SVE/eorv-diagnostics.s index c182615be5d6..6f231a8c6269 100644 --- a/test/MC/AArch64/SVE/eorv-diagnostics.s +++ b/test/MC/AArch64/SVE/eorv-diagnostics.s @@ -31,4 +31,19 @@ eorv v0.2d, p7, z31.d eorv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: eorv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +eorv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: eorv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +eorv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: eorv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ext-diagnostics.s b/test/MC/AArch64/SVE/ext-diagnostics.s index 8f9bee79b85c..23ae5e2ddd5c 100644 --- a/test/MC/AArch64/SVE/ext-diagnostics.s +++ b/test/MC/AArch64/SVE/ext-diagnostics.s @@ -31,3 +31,13 @@ ext z0.b, z0.b, z1.b, #256 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. // CHECK-NEXT: ext z0.b, z0.b, z1.b, #256 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +ext z31.b, z31.b, z0.b, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: ext z31.b, z31.b, z0.b, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ext.s b/test/MC/AArch64/SVE/ext.s index 2afc5f09771a..632f61eb107c 100644 --- a/test/MC/AArch64/SVE/ext.s +++ b/test/MC/AArch64/SVE/ext.s @@ -18,3 +18,19 @@ ext z31.b, z31.b, z0.b, #255 // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 1f 1c 3f 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +ext z31.b, z31.b, z0.b, #255 +// CHECK-INST: ext z31.b, z31.b, z0.b, #255 +// CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c 3f 05 <unknown> diff --git a/test/MC/AArch64/SVE/fabd.s b/test/MC/AArch64/SVE/fabd.s index 98bbc5050a37..7549f554a95f 100644 --- a/test/MC/AArch64/SVE/fabd.s +++ b/test/MC/AArch64/SVE/fabd.s @@ -24,3 +24,31 @@ fabd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c8 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fabd z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c8 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fabd z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fabd z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c8 65 <unknown> diff --git a/test/MC/AArch64/SVE/fabs.s b/test/MC/AArch64/SVE/fabs.s index c9d4d8405bef..1bd2c833d1cd 100644 --- a/test/MC/AArch64/SVE/fabs.s +++ b/test/MC/AArch64/SVE/fabs.s @@ -24,3 +24,31 @@ fabs z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdc,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf dc 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fabs z4.d, p7/m, z31.d +// CHECK-INST: fabs z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf dc 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fabs z4.d, p7/m, z31.d +// CHECK-INST: fabs z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf dc 04 <unknown> diff --git a/test/MC/AArch64/SVE/facge-diagnostics.s b/test/MC/AArch64/SVE/facge-diagnostics.s index 08710681bf4c..a33627aa68ee 100644 --- a/test/MC/AArch64/SVE/facge-diagnostics.s +++ b/test/MC/AArch64/SVE/facge-diagnostics.s @@ -9,3 +9,19 @@ facge p0.b, p0/z, z0.b, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: facge p0.b, p0/z, z0.b, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +facge p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facge p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +facge p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facge p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/facgt-diagnostics.s b/test/MC/AArch64/SVE/facgt-diagnostics.s index 12c1ed53527a..c92690bc9de8 100644 --- a/test/MC/AArch64/SVE/facgt-diagnostics.s +++ b/test/MC/AArch64/SVE/facgt-diagnostics.s @@ -9,3 +9,19 @@ facgt p0.b, p0/z, z0.b, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: facgt p0.b, p0/z, z0.b, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +facgt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facgt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +facgt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facgt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/facle-diagnostics.s b/test/MC/AArch64/SVE/facle-diagnostics.s index 6ecfccffc263..0f3b777308d9 100644 --- a/test/MC/AArch64/SVE/facle-diagnostics.s +++ b/test/MC/AArch64/SVE/facle-diagnostics.s @@ -9,3 +9,19 @@ facle p0.b, p0/z, z0.b, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: facle p0.b, p0/z, z0.b, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +facle p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facle p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +facle p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: facle p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/faclt-diagnostics.s b/test/MC/AArch64/SVE/faclt-diagnostics.s index b0ef736ffcaa..12baa18615d9 100644 --- a/test/MC/AArch64/SVE/faclt-diagnostics.s +++ b/test/MC/AArch64/SVE/faclt-diagnostics.s @@ -9,3 +9,19 @@ faclt p0.b, p0/z, z0.b, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: faclt p0.b, p0/z, z0.b, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +faclt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: faclt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +faclt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: faclt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fadd-diagnostics.s b/test/MC/AArch64/SVE/fadd-diagnostics.s index be8a85fa49b5..b809e2e72b28 100644 --- a/test/MC/AArch64/SVE/fadd-diagnostics.s +++ b/test/MC/AArch64/SVE/fadd-diagnostics.s @@ -68,3 +68,19 @@ fadd z0.h, p8/m, z0.h, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: fadd z0.h, p8/m, z0.h, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fadd z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fadd z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fadd z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fadd z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fadd.s b/test/MC/AArch64/SVE/fadd.s index 36c3171bba89..10935c37fc05 100644 --- a/test/MC/AArch64/SVE/fadd.s +++ b/test/MC/AArch64/SVE/fadd.s @@ -90,3 +90,55 @@ fadd z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x00,0xdf,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 00 df 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fadd z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c d8 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fadd z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fadd z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c d8 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fadd z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c0 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fadd z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fadd z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c0 65 <unknown> diff --git a/test/MC/AArch64/SVE/fadda-diagnostics.s b/test/MC/AArch64/SVE/fadda-diagnostics.s index bff63367b159..6386707efa5d 100644 --- a/test/MC/AArch64/SVE/fadda-diagnostics.s +++ b/test/MC/AArch64/SVE/fadda-diagnostics.s @@ -18,4 +18,19 @@ fadda h0, p8, h0, z31.h fadda v0.8h, p7, v0.8h, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fadda d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fadda d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fadda d0, p7, d0, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fadda d0, p7, d0, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/faddv-diagnostics.s b/test/MC/AArch64/SVE/faddv-diagnostics.s index 37cb19337d94..f8fa774d8bec 100644 --- a/test/MC/AArch64/SVE/faddv-diagnostics.s +++ b/test/MC/AArch64/SVE/faddv-diagnostics.s @@ -17,4 +17,19 @@ faddv h0, p8, z31.h faddv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: faddv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +faddv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: faddv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +faddv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: faddv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcadd.s b/test/MC/AArch64/SVE/fcadd.s index 5e8c8324c773..9d2398ab25a8 100644 --- a/test/MC/AArch64/SVE/fcadd.s +++ b/test/MC/AArch64/SVE/fcadd.s @@ -42,3 +42,31 @@ fcadd z31.d, p7/m, z31.d, z31.d, #270 // CHECK-ENCODING: [0xff,0x9f,0xc1,0x64] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 9f c1 64 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fcadd z4.d, p7/m, z4.d, z31.d, #270 +// CHECK-INST: fcadd z4.d, p7/m, z4.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f c1 64 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fcadd z4.d, p7/m, z4.d, z31.d, #270 +// CHECK-INST: fcadd z4.d, p7/m, z4.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f c1 64 <unknown> diff --git a/test/MC/AArch64/SVE/fcmeq-diagnostics.s b/test/MC/AArch64/SVE/fcmeq-diagnostics.s index d2e8dddda3ed..08dc7dc4010c 100644 --- a/test/MC/AArch64/SVE/fcmeq-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmeq-diagnostics.s @@ -9,3 +9,31 @@ fcmeq p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmeq p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmeq p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmeq p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmeq p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmge-diagnostics.s b/test/MC/AArch64/SVE/fcmge-diagnostics.s index d6d7b589c861..249d6fc5af12 100644 --- a/test/MC/AArch64/SVE/fcmge-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmge-diagnostics.s @@ -9,3 +9,31 @@ fcmge p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmge p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmge p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmge p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmge p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmge p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmge p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmgt-diagnostics.s b/test/MC/AArch64/SVE/fcmgt-diagnostics.s index 4ec876922bb3..d9c42217ad2d 100644 --- a/test/MC/AArch64/SVE/fcmgt-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmgt-diagnostics.s @@ -9,3 +9,31 @@ fcmgt p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmgt p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmgt p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmgt p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmgt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmgt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmgt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmla-diagnostics.s b/test/MC/AArch64/SVE/fcmla-diagnostics.s index 560b15f3de90..7ad6db4f1985 100644 --- a/test/MC/AArch64/SVE/fcmla-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmla-diagnostics.s @@ -50,3 +50,13 @@ fcmla z0.d, z1.d, z2.d[0], #0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: fcmla z0.d, z1.d, z2.d[0], #0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p0/z, z28.s +fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmla.s b/test/MC/AArch64/SVE/fcmla.s index 3a0954e7c8ef..2e4dd7f55357 100644 --- a/test/MC/AArch64/SVE/fcmla.s +++ b/test/MC/AArch64/SVE/fcmla.s @@ -102,3 +102,43 @@ fcmla z21.s, z10.s, z5.s[1], #90 // CHECK-ENCODING: [0x55,0x15,0xf5,0x64] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 15 f5 64 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fcmla z4.d, p7/m, z31.d, z31.d, #270 +// CHECK-INST: fcmla z4.d, p7/m, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 7f df 64 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fcmla z4.d, p7/m, z31.d, z31.d, #270 +// CHECK-INST: fcmla z4.d, p7/m, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 7f df 64 <unknown> + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 <unknown> + +fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90 +// CHECK-ENCODING: [0x55,0x15,0xf5,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 55 15 f5 64 <unknown> diff --git a/test/MC/AArch64/SVE/fcmle-diagnostics.s b/test/MC/AArch64/SVE/fcmle-diagnostics.s index 4ce8fb679e81..8c3dbe9c634d 100644 --- a/test/MC/AArch64/SVE/fcmle-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmle-diagnostics.s @@ -9,3 +9,31 @@ fcmle p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmle p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmle p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmle p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmle p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmle p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmle p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmlt-diagnostics.s b/test/MC/AArch64/SVE/fcmlt-diagnostics.s index 1e13a3d2e03a..44a39bb41ac2 100644 --- a/test/MC/AArch64/SVE/fcmlt-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmlt-diagnostics.s @@ -9,3 +9,31 @@ fcmlt p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmlt p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmlt p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmlt p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmlt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmlt p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmlt p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmne-diagnostics.s b/test/MC/AArch64/SVE/fcmne-diagnostics.s index d0e996b4b7bf..8e8173d4c46d 100644 --- a/test/MC/AArch64/SVE/fcmne-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmne-diagnostics.s @@ -9,3 +9,31 @@ fcmne p0.s, p0/z, z0.s, #1.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected floating-point constant #0.0 // CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #1.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmne p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmne p0.d, p0/z, z0.d, #0.0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, #0.0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +fcmne p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmne p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcmuo-diagnostics.s b/test/MC/AArch64/SVE/fcmuo-diagnostics.s index c9a33346b5f0..0905d9b240fe 100644 --- a/test/MC/AArch64/SVE/fcmuo-diagnostics.s +++ b/test/MC/AArch64/SVE/fcmuo-diagnostics.s @@ -9,3 +9,19 @@ fcmuo p0.s, p0/z, z0.s, #0.0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal // CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, #0.0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fcmuo p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcmuo p0.d, p0/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fcpy.s b/test/MC/AArch64/SVE/fcpy.s index 712f16a6affa..5510e035dd1d 100644 --- a/test/MC/AArch64/SVE/fcpy.s +++ b/test/MC/AArch64/SVE/fcpy.s @@ -1554,3 +1554,31 @@ fcpy z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 c7 d0 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p0/z, z7.d +// CHECK-INST: movprfx z0.d, p0/z, z7.d +// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 d0 04 <unknown> + +fcpy z0.d, p0/m, #31.00000000 +// CHECK-INST: fmov z0.d, p0/m, #31.00000000 +// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fcpy z0.d, p0/m, #31.00000000 +// CHECK-INST: fmov z0.d, p0/m, #31.00000000 +// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> diff --git a/test/MC/AArch64/SVE/fcvt.s b/test/MC/AArch64/SVE/fcvt.s index e0e9e7679473..3a0d52471186 100644 --- a/test/MC/AArch64/SVE/fcvt.s +++ b/test/MC/AArch64/SVE/fcvt.s @@ -42,3 +42,31 @@ fcvt z0.d, p0/m, z0.s // CHECK-ENCODING: [0x00,0xa0,0xcb,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 cb 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +fcvt z5.d, p0/m, z0.s +// CHECK-INST: fcvt z5.d, p0/m, z0.s +// CHECK-ENCODING: [0x05,0xa0,0xcb,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 cb 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +fcvt z5.d, p0/m, z0.s +// CHECK-INST: fcvt z5.d, p0/m, z0.s +// CHECK-ENCODING: [0x05,0xa0,0xcb,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 cb 65 <unknown> diff --git a/test/MC/AArch64/SVE/fcvtzs.s b/test/MC/AArch64/SVE/fcvtzs.s index 40e4c44a98d2..ecb7adc46b84 100644 --- a/test/MC/AArch64/SVE/fcvtzs.s +++ b/test/MC/AArch64/SVE/fcvtzs.s @@ -48,3 +48,31 @@ fcvtzs z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xde,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 de 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +fcvtzs z5.d, p0/m, z0.d +// CHECK-INST: fcvtzs z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xde,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 de 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +fcvtzs z5.d, p0/m, z0.d +// CHECK-INST: fcvtzs z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xde,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 de 65 <unknown> diff --git a/test/MC/AArch64/SVE/fcvtzu.s b/test/MC/AArch64/SVE/fcvtzu.s index 37505d998c5c..cd6993c0f589 100644 --- a/test/MC/AArch64/SVE/fcvtzu.s +++ b/test/MC/AArch64/SVE/fcvtzu.s @@ -48,3 +48,31 @@ fcvtzu z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xdf,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 df 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +fcvtzu z5.d, p0/m, z0.d +// CHECK-INST: fcvtzu z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 df 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +fcvtzu z5.d, p0/m, z0.d +// CHECK-INST: fcvtzu z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 df 65 <unknown> diff --git a/test/MC/AArch64/SVE/fdiv.s b/test/MC/AArch64/SVE/fdiv.s index 112d202d5abb..9f1d4ddf1b77 100644 --- a/test/MC/AArch64/SVE/fdiv.s +++ b/test/MC/AArch64/SVE/fdiv.s @@ -24,3 +24,31 @@ fdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f cd 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fdiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f cd 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fdiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fdiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f cd 65 <unknown> diff --git a/test/MC/AArch64/SVE/fdivr.s b/test/MC/AArch64/SVE/fdivr.s index 3744dd95c694..37fd871461e3 100644 --- a/test/MC/AArch64/SVE/fdivr.s +++ b/test/MC/AArch64/SVE/fdivr.s @@ -24,3 +24,31 @@ fdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f cc 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fdivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f cc 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fdivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fdivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f cc 65 <unknown> diff --git a/test/MC/AArch64/SVE/fdup-diagnostics.s b/test/MC/AArch64/SVE/fdup-diagnostics.s index 6128bbe85bba..4432393bfa26 100644 --- a/test/MC/AArch64/SVE/fdup-diagnostics.s +++ b/test/MC/AArch64/SVE/fdup-diagnostics.s @@ -62,3 +62,19 @@ fdup z0.d, #64.00000000 // r = 5, n = 32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant // CHECK-NEXT: fdup z0.d, #64.00000000 // r = 5, n = 32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fdup z0.d, #31.00000000 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fdup z0.d, #31.00000000 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fdup z0.d, #31.00000000 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fdup z0.d, #31.00000000 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fexpa-diagnostics.s b/test/MC/AArch64/SVE/fexpa-diagnostics.s index 2269ae0fdfc2..33964f24d4a6 100644 --- a/test/MC/AArch64/SVE/fexpa-diagnostics.s +++ b/test/MC/AArch64/SVE/fexpa-diagnostics.s @@ -12,4 +12,19 @@ fexpa z0.b, z31.b fexpa z0.s, z31.d // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: fexpa z0.s, z31.d -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fexpa z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fexpa z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fexpa z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fexpa z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmad.s b/test/MC/AArch64/SVE/fmad.s index dbcec437c32b..2cfb6a74156c 100644 --- a/test/MC/AArch64/SVE/fmad.s +++ b/test/MC/AArch64/SVE/fmad.s @@ -24,3 +24,31 @@ fmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x9c,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 9c ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x9c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 9c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x9c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 9c ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmax.s b/test/MC/AArch64/SVE/fmax.s index 0e4a6d4c196e..bcdc90403949 100644 --- a/test/MC/AArch64/SVE/fmax.s +++ b/test/MC/AArch64/SVE/fmax.s @@ -66,3 +66,55 @@ fmax z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c6 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p0/z, z7.d +// CHECK-INST: movprfx z0.d, p0/z, z7.d +// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 d0 04 <unknown> + +fmax z0.d, p0/m, z0.d, #0.0 +// CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0 +// CHECK-ENCODING: [0x00,0x80,0xde,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 de 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmax z0.d, p0/m, z0.d, #0.0 +// CHECK-INST: fmax z0.d, p0/m, z0.d, #0.0 +// CHECK-ENCODING: [0x00,0x80,0xde,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 de 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmax z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c6 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmax z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmax z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c6 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmaxnm.s b/test/MC/AArch64/SVE/fmaxnm.s index 3016f63154a2..5c44861ea954 100644 --- a/test/MC/AArch64/SVE/fmaxnm.s +++ b/test/MC/AArch64/SVE/fmaxnm.s @@ -72,3 +72,55 @@ fmaxnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c4 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fmaxnm z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c dc 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fmaxnm z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fmaxnm z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c dc 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmaxnm z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c4 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmaxnm z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmaxnm z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c4 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s b/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s index 2eb6191b3893..094831296559 100644 --- a/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s +++ b/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s @@ -17,4 +17,19 @@ fmaxnmv h0, p8, z31.h fmaxnmv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmaxnmv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fmaxnmv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmaxnmv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fmaxnmv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmaxnmv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmaxv-diagnostics.s b/test/MC/AArch64/SVE/fmaxv-diagnostics.s index d679734e2d62..0923dc167f8e 100644 --- a/test/MC/AArch64/SVE/fmaxv-diagnostics.s +++ b/test/MC/AArch64/SVE/fmaxv-diagnostics.s @@ -17,4 +17,19 @@ fmaxv h0, p8, z31.h fmaxv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmaxv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fmaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fmaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmin.s b/test/MC/AArch64/SVE/fmin.s index 2db4d5ca842a..1b0cb4e589c3 100644 --- a/test/MC/AArch64/SVE/fmin.s +++ b/test/MC/AArch64/SVE/fmin.s @@ -72,3 +72,55 @@ fmin z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c7 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fmin z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c df 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fmin z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fmin z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c df 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmin z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c7 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmin z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmin z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c7 65 <unknown> diff --git a/test/MC/AArch64/SVE/fminnm.s b/test/MC/AArch64/SVE/fminnm.s index 492d5898518c..482b7f561ef2 100644 --- a/test/MC/AArch64/SVE/fminnm.s +++ b/test/MC/AArch64/SVE/fminnm.s @@ -72,3 +72,55 @@ fminnm z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c5 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fminnm z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c dd 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fminnm z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fminnm z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c dd 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fminnm z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c5 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fminnm z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fminnm z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c5 65 <unknown> diff --git a/test/MC/AArch64/SVE/fminnmv-diagnostics.s b/test/MC/AArch64/SVE/fminnmv-diagnostics.s index d613d053a5f3..bf9062b5b66d 100644 --- a/test/MC/AArch64/SVE/fminnmv-diagnostics.s +++ b/test/MC/AArch64/SVE/fminnmv-diagnostics.s @@ -17,4 +17,19 @@ fminnmv h0, p8, z31.h fminnmv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fminnmv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fminnmv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fminnmv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fminnmv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fminnmv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fminv-diagnostics.s b/test/MC/AArch64/SVE/fminv-diagnostics.s index e1dc7715396c..793d7f7562b2 100644 --- a/test/MC/AArch64/SVE/fminv-diagnostics.s +++ b/test/MC/AArch64/SVE/fminv-diagnostics.s @@ -17,4 +17,19 @@ fminv h0, p8, z31.h fminv v0, p7, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fminv v0, p7, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +fminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmla-diagnostics.s b/test/MC/AArch64/SVE/fmla-diagnostics.s index 43b452f1e7be..e9892590c232 100644 --- a/test/MC/AArch64/SVE/fmla-diagnostics.s +++ b/test/MC/AArch64/SVE/fmla-diagnostics.s @@ -70,3 +70,13 @@ fmla z0.d, z1.d, z2.d[2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK-NEXT: fmla z0.d, z1.d, z2.d[2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fmla z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmla z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmla.s b/test/MC/AArch64/SVE/fmla.s index 3b1f54c37598..a28204da0a14 100644 --- a/test/MC/AArch64/SVE/fmla.s +++ b/test/MC/AArch64/SVE/fmla.s @@ -42,3 +42,43 @@ fmla z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x00,0xf7,0x64] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 00 f7 64 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x1c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x1c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmla z0.d, z1.d, z7.d[1] +// CHECK-INST: fmla z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x00,0xf7,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 f7 64 <unknown> diff --git a/test/MC/AArch64/SVE/fmls-diagnostics.s b/test/MC/AArch64/SVE/fmls-diagnostics.s index f7734f8fe9a4..8c2d175642c8 100644 --- a/test/MC/AArch64/SVE/fmls-diagnostics.s +++ b/test/MC/AArch64/SVE/fmls-diagnostics.s @@ -70,3 +70,13 @@ fmls z0.d, z1.d, z2.d[2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK-NEXT: fmls z0.d, z1.d, z2.d[2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fmls z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmls z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmls.s b/test/MC/AArch64/SVE/fmls.s index c337d8c3aec2..390a3128fc44 100644 --- a/test/MC/AArch64/SVE/fmls.s +++ b/test/MC/AArch64/SVE/fmls.s @@ -42,3 +42,43 @@ fmls z0.d, z1.d, z7.d[1] // CHECK-ENCODING: [0x20,0x04,0xf7,0x64] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 04 f7 64 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x3c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 3c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x3c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 3c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmls z0.d, z1.d, z7.d[1] +// CHECK-INST: fmls z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x04,0xf7,0x64] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 f7 64 <unknown> diff --git a/test/MC/AArch64/SVE/fmov-diagnostics.s b/test/MC/AArch64/SVE/fmov-diagnostics.s index 3225ff1b1581..fcf53644b50c 100644 --- a/test/MC/AArch64/SVE/fmov-diagnostics.s +++ b/test/MC/AArch64/SVE/fmov-diagnostics.s @@ -140,3 +140,19 @@ fmov z0.d, p0/m, #64.00000000 // r = 5, n = 32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or floating-point constant // CHECK-NEXT: fmov z0.d, p0/m, #64.00000000 // r = 5, n = 32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fmov z0.d, #31.00000000 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmov z0.d, #31.00000000 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fmov z0.d, #31.00000000 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmov z0.d, #31.00000000 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmov.s b/test/MC/AArch64/SVE/fmov.s index 72bac32ba49c..abd1044bc163 100644 --- a/test/MC/AArch64/SVE/fmov.s +++ b/test/MC/AArch64/SVE/fmov.s @@ -1596,3 +1596,31 @@ fmov z0.d, p0/m, #31.00000000 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 c7 d0 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p0/z, z7.d +// CHECK-INST: movprfx z0.d, p0/z, z7.d +// CHECK-ENCODING: [0xe0,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 d0 04 <unknown> + +fmov z0.d, p0/m, #31.00000000 +// CHECK-INST: fmov z0.d, p0/m, #31.00000000 +// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmov z0.d, p0/m, #31.00000000 +// CHECK-INST: fmov z0.d, p0/m, #31.00000000 +// CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 d0 05 <unknown> diff --git a/test/MC/AArch64/SVE/fmsb.s b/test/MC/AArch64/SVE/fmsb.s index 4e34073ff107..c1203e2f1f38 100644 --- a/test/MC/AArch64/SVE/fmsb.s +++ b/test/MC/AArch64/SVE/fmsb.s @@ -24,3 +24,31 @@ fmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xbc,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 bc ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xbc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xbc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmul-diagnostics.s b/test/MC/AArch64/SVE/fmul-diagnostics.s index 55bfbd7cef68..be91dc312f36 100644 --- a/test/MC/AArch64/SVE/fmul-diagnostics.s +++ b/test/MC/AArch64/SVE/fmul-diagnostics.s @@ -132,3 +132,31 @@ fmul z0.h, p8/m, z0.h, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: fmul z0.h, p8/m, z0.h, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fmul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fmul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +fmul z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmul z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +fmul z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fmul z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fmul.s b/test/MC/AArch64/SVE/fmul.s index fd75166319bf..3cf35f33f8ca 100644 --- a/test/MC/AArch64/SVE/fmul.s +++ b/test/MC/AArch64/SVE/fmul.s @@ -120,3 +120,55 @@ fmul z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x08,0xdf,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 08 df 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fmul z31.d, p7/m, z31.d, #2.0 +// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0 +// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c da 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fmul z31.d, p7/m, z31.d, #2.0 +// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0 +// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c da 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmul z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c2 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmul z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c2 65 <unknown> diff --git a/test/MC/AArch64/SVE/fmulx.s b/test/MC/AArch64/SVE/fmulx.s index a1c8e6b93258..0c49421fddbc 100644 --- a/test/MC/AArch64/SVE/fmulx.s +++ b/test/MC/AArch64/SVE/fmulx.s @@ -24,3 +24,31 @@ fmulx z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f ca 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fmulx z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f ca 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fmulx z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fmulx z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xca,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f ca 65 <unknown> diff --git a/test/MC/AArch64/SVE/fneg.s b/test/MC/AArch64/SVE/fneg.s index 9b9ca9041fb8..47f833e9b81c 100644 --- a/test/MC/AArch64/SVE/fneg.s +++ b/test/MC/AArch64/SVE/fneg.s @@ -24,3 +24,31 @@ fneg z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xdd,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf dd 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fneg z4.d, p7/m, z31.d +// CHECK-INST: fneg z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf dd 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fneg z4.d, p7/m, z31.d +// CHECK-INST: fneg z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf dd 04 <unknown> diff --git a/test/MC/AArch64/SVE/fnmad.s b/test/MC/AArch64/SVE/fnmad.s index 6bb736c9eb42..3bec7b6be884 100644 --- a/test/MC/AArch64/SVE/fnmad.s +++ b/test/MC/AArch64/SVE/fnmad.s @@ -24,3 +24,31 @@ fnmad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xdc,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 dc ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xdc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 dc ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xdc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 dc ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fnmla.s b/test/MC/AArch64/SVE/fnmla.s index 49d443f26103..aa3eb3be9195 100644 --- a/test/MC/AArch64/SVE/fnmla.s +++ b/test/MC/AArch64/SVE/fnmla.s @@ -24,3 +24,31 @@ fnmla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 5c ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fnmls.s b/test/MC/AArch64/SVE/fnmls.s index 438fbaeed6d0..90bde2edc4ce 100644 --- a/test/MC/AArch64/SVE/fnmls.s +++ b/test/MC/AArch64/SVE/fnmls.s @@ -24,3 +24,31 @@ fnmls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 7c ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/fnmsb.s b/test/MC/AArch64/SVE/fnmsb.s index f06de48afbf1..a1767c4091cf 100644 --- a/test/MC/AArch64/SVE/fnmsb.s +++ b/test/MC/AArch64/SVE/fnmsb.s @@ -24,3 +24,31 @@ fnmsb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0xfc,0xff,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 fc ff 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xfc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc ff 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: fnmsb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xfc,0xff,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 fc ff 65 <unknown> diff --git a/test/MC/AArch64/SVE/frecpe-diagnostics.s b/test/MC/AArch64/SVE/frecpe-diagnostics.s index 80467f26f5a3..6457ad0837bc 100644 --- a/test/MC/AArch64/SVE/frecpe-diagnostics.s +++ b/test/MC/AArch64/SVE/frecpe-diagnostics.s @@ -3,4 +3,19 @@ frecpe z0.b, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: frecpe z0.b, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +frecpe z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frecpe z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +frecpe z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frecpe z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/frecps-diagnostics.s b/test/MC/AArch64/SVE/frecps-diagnostics.s index 7de58cff80fa..ec2d6c3954c4 100644 --- a/test/MC/AArch64/SVE/frecps-diagnostics.s +++ b/test/MC/AArch64/SVE/frecps-diagnostics.s @@ -13,3 +13,19 @@ frecps z0.h, z1.s, z2.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: frecps z0.h, z1.s, z2.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +frecps z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frecps z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +frecps z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frecps z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/frecpx.s b/test/MC/AArch64/SVE/frecpx.s index 49226abc33b8..a044703ab714 100644 --- a/test/MC/AArch64/SVE/frecpx.s +++ b/test/MC/AArch64/SVE/frecpx.s @@ -24,3 +24,31 @@ frecpx z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xcc,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf cc 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frecpx z4.d, p7/m, z31.d +// CHECK-INST: frecpx z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf cc 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frecpx z4.d, p7/m, z31.d +// CHECK-INST: frecpx z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf cc 65 <unknown> diff --git a/test/MC/AArch64/SVE/frinta.s b/test/MC/AArch64/SVE/frinta.s index ea7a48a29b9b..c89e1618ae7b 100644 --- a/test/MC/AArch64/SVE/frinta.s +++ b/test/MC/AArch64/SVE/frinta.s @@ -24,3 +24,31 @@ frinta z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc4,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c4 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frinta z4.d, p7/m, z31.d +// CHECK-INST: frinta z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c4 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frinta z4.d, p7/m, z31.d +// CHECK-INST: frinta z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c4 65 <unknown> diff --git a/test/MC/AArch64/SVE/frinti.s b/test/MC/AArch64/SVE/frinti.s index 7fde35c4a184..a05cc9fe7b46 100644 --- a/test/MC/AArch64/SVE/frinti.s +++ b/test/MC/AArch64/SVE/frinti.s @@ -24,3 +24,31 @@ frinti z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc7,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c7 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frinti z4.d, p7/m, z31.d +// CHECK-INST: frinti z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c7 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frinti z4.d, p7/m, z31.d +// CHECK-INST: frinti z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c7 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintm.s b/test/MC/AArch64/SVE/frintm.s index b33e922bbd5f..e085683f9d17 100644 --- a/test/MC/AArch64/SVE/frintm.s +++ b/test/MC/AArch64/SVE/frintm.s @@ -24,3 +24,31 @@ frintm z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc2,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c2 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintm z4.d, p7/m, z31.d +// CHECK-INST: frintm z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c2 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintm z4.d, p7/m, z31.d +// CHECK-INST: frintm z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c2 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintn.s b/test/MC/AArch64/SVE/frintn.s index d19f85520644..1318c8b88318 100644 --- a/test/MC/AArch64/SVE/frintn.s +++ b/test/MC/AArch64/SVE/frintn.s @@ -24,3 +24,31 @@ frintn z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc0,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c0 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintn z4.d, p7/m, z31.d +// CHECK-INST: frintn z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c0 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintn z4.d, p7/m, z31.d +// CHECK-INST: frintn z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c0 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintp.s b/test/MC/AArch64/SVE/frintp.s index 12fce742c798..a36831ecc2dd 100644 --- a/test/MC/AArch64/SVE/frintp.s +++ b/test/MC/AArch64/SVE/frintp.s @@ -24,3 +24,31 @@ frintp z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc1,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c1 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintp z4.d, p7/m, z31.d +// CHECK-INST: frintp z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c1 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintp z4.d, p7/m, z31.d +// CHECK-INST: frintp z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c1 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintx.s b/test/MC/AArch64/SVE/frintx.s index b33f4281d3d5..60244a9cb334 100644 --- a/test/MC/AArch64/SVE/frintx.s +++ b/test/MC/AArch64/SVE/frintx.s @@ -24,3 +24,31 @@ frintx z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc6,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c6 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintx z4.d, p7/m, z31.d +// CHECK-INST: frintx z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c6 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintx z4.d, p7/m, z31.d +// CHECK-INST: frintx z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c6 65 <unknown> diff --git a/test/MC/AArch64/SVE/frintz.s b/test/MC/AArch64/SVE/frintz.s index 22e2aef98b8f..af794b79a2f2 100644 --- a/test/MC/AArch64/SVE/frintz.s +++ b/test/MC/AArch64/SVE/frintz.s @@ -24,3 +24,31 @@ frintz z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xc3,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf c3 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +frintz z4.d, p7/m, z31.d +// CHECK-INST: frintz z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c3 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +frintz z4.d, p7/m, z31.d +// CHECK-INST: frintz z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf c3 65 <unknown> diff --git a/test/MC/AArch64/SVE/frsqrte-diagnostics.s b/test/MC/AArch64/SVE/frsqrte-diagnostics.s index b7325e164aa1..b38c9370b85b 100644 --- a/test/MC/AArch64/SVE/frsqrte-diagnostics.s +++ b/test/MC/AArch64/SVE/frsqrte-diagnostics.s @@ -3,4 +3,19 @@ frsqrte z0.b, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: frsqrte z0.b, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +frsqrte z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frsqrte z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +frsqrte z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frsqrte z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/frsqrts-diagnostics.s b/test/MC/AArch64/SVE/frsqrts-diagnostics.s index 07dde46ad459..2032e74bfc28 100644 --- a/test/MC/AArch64/SVE/frsqrts-diagnostics.s +++ b/test/MC/AArch64/SVE/frsqrts-diagnostics.s @@ -13,3 +13,19 @@ frsqrts z0.h, z1.s, z2.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: frsqrts z0.h, z1.s, z2.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +frsqrts z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frsqrts z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +frsqrts z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: frsqrts z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fscale.s b/test/MC/AArch64/SVE/fscale.s index 0ce3d7ecb9a8..ab928b4c77f1 100644 --- a/test/MC/AArch64/SVE/fscale.s +++ b/test/MC/AArch64/SVE/fscale.s @@ -24,3 +24,31 @@ fscale z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c9 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fscale z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c9 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fscale z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fscale z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c9 65 <unknown> diff --git a/test/MC/AArch64/SVE/fsqrt.s b/test/MC/AArch64/SVE/fsqrt.s index 949faba227b6..b72d2438b33f 100644 --- a/test/MC/AArch64/SVE/fsqrt.s +++ b/test/MC/AArch64/SVE/fsqrt.s @@ -24,3 +24,31 @@ fsqrt z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xcd,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf cd 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +fsqrt z4.d, p7/m, z31.d +// CHECK-INST: fsqrt z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf cd 65 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +fsqrt z4.d, p7/m, z31.d +// CHECK-INST: fsqrt z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf cd 65 <unknown> diff --git a/test/MC/AArch64/SVE/fsub-diagnostics.s b/test/MC/AArch64/SVE/fsub-diagnostics.s index 27d1b3f7b918..41b36bdbea4d 100644 --- a/test/MC/AArch64/SVE/fsub-diagnostics.s +++ b/test/MC/AArch64/SVE/fsub-diagnostics.s @@ -68,3 +68,19 @@ fsub z0.h, p8/m, z0.h, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: fsub z0.h, p8/m, z0.h, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +fsub z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fsub z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fsub z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fsub z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/fsub.s b/test/MC/AArch64/SVE/fsub.s index 8e96cbb65ad0..49d7448e8574 100644 --- a/test/MC/AArch64/SVE/fsub.s +++ b/test/MC/AArch64/SVE/fsub.s @@ -90,3 +90,55 @@ fsub z0.d, z1.d, z31.d // CHECK-ENCODING: [0x20,0x04,0xdf,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 04 df 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fsub z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c d9 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fsub z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fsub z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c d9 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fsub z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c1 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fsub z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fsub z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c1 65 <unknown> diff --git a/test/MC/AArch64/SVE/fsubr.s b/test/MC/AArch64/SVE/fsubr.s index 990a0b1ac520..349871702498 100644 --- a/test/MC/AArch64/SVE/fsubr.s +++ b/test/MC/AArch64/SVE/fsubr.s @@ -72,3 +72,55 @@ fsubr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c3 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +fsubr z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c db 65 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +fsubr z31.d, p7/m, z31.d, #1.0 +// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0 +// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 3f 9c db 65 <unknown> + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +fsubr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c3 65 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +fsubr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f c3 65 <unknown> diff --git a/test/MC/AArch64/SVE/ftmad-diagnostics.s b/test/MC/AArch64/SVE/ftmad-diagnostics.s index 5b63106fb48b..ec7741810b3c 100644 --- a/test/MC/AArch64/SVE/ftmad-diagnostics.s +++ b/test/MC/AArch64/SVE/ftmad-diagnostics.s @@ -36,3 +36,13 @@ ftmad z0.h, z0.h, z1.h, #8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]. // CHECK-NEXT: ftmad z0.h, z0.h, z1.h, #8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ftmad z0.d, z0.d, z31.d, #7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: ftmad z0.d, z0.d, z31.d, #7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ftmad.s b/test/MC/AArch64/SVE/ftmad.s index c18009ec0cb6..3a59a1fb4fd7 100644 --- a/test/MC/AArch64/SVE/ftmad.s +++ b/test/MC/AArch64/SVE/ftmad.s @@ -24,3 +24,19 @@ ftmad z0.d, z0.d, z31.d, #7 // CHECK-ENCODING: [0xe0,0x83,0xd7,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 83 d7 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +ftmad z0.d, z0.d, z31.d, #7 +// CHECK-INST: ftmad z0.d, z0.d, z31.d, #7 +// CHECK-ENCODING: [0xe0,0x83,0xd7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 d7 65 <unknown> diff --git a/test/MC/AArch64/SVE/ftsmul-diagnostics.s b/test/MC/AArch64/SVE/ftsmul-diagnostics.s index 5ad0a14d798c..08b2966893fe 100644 --- a/test/MC/AArch64/SVE/ftsmul-diagnostics.s +++ b/test/MC/AArch64/SVE/ftsmul-diagnostics.s @@ -13,3 +13,19 @@ ftsmul z0.h, z1.s, z2.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ftsmul z0.h, z1.s, z2.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ftsmul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ftsmul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ftsmul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ftsmul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ftssel-diagnostics.s b/test/MC/AArch64/SVE/ftssel-diagnostics.s index 92991246163f..c0cfac061311 100644 --- a/test/MC/AArch64/SVE/ftssel-diagnostics.s +++ b/test/MC/AArch64/SVE/ftssel-diagnostics.s @@ -3,4 +3,19 @@ ftssel z0.b, z1.b, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: ftssel z0.b, z1.b, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ftssel z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ftssel z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ftssel z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ftssel z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/incd-diagnostics.s b/test/MC/AArch64/SVE/incd-diagnostics.s index ddd232062bf5..2c32eea91ef0 100644 --- a/test/MC/AArch64/SVE/incd-diagnostics.s +++ b/test/MC/AArch64/SVE/incd-diagnostics.s @@ -61,3 +61,25 @@ incd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +incd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +incd z0.d, all, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incd z0.d, all, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +incd z0.d, all +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incd z0.d, all +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/incd.s b/test/MC/AArch64/SVE/incd.s index 6d146a4612b3..9774c450ed12 100644 --- a/test/MC/AArch64/SVE/incd.s +++ b/test/MC/AArch64/SVE/incd.s @@ -164,3 +164,43 @@ incd x0, #28 // CHECK-ENCODING: [0x80,0xe3,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 e3 f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incd z0.d +// CHECK-INST: incd z0.d +// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 f0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incd z0.d, all, mul #16 +// CHECK-INST: incd z0.d, all, mul #16 +// CHECK-ENCODING: [0xe0,0xc3,0xff,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 ff 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incd z0.d, all +// CHECK-INST: incd z0.d +// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 f0 04 <unknown> diff --git a/test/MC/AArch64/SVE/inch-diagnostics.s b/test/MC/AArch64/SVE/inch-diagnostics.s index 31b71cfd49df..b25019bd9bd4 100644 --- a/test/MC/AArch64/SVE/inch-diagnostics.s +++ b/test/MC/AArch64/SVE/inch-diagnostics.s @@ -61,3 +61,25 @@ inch x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: inch x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +inch z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: inch z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +inch z0.h, all, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: inch z0.h, all, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +inch z0.h, all +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: inch z0.h, all +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/inch.s b/test/MC/AArch64/SVE/inch.s index 02519067271d..fd952cd7d3db 100644 --- a/test/MC/AArch64/SVE/inch.s +++ b/test/MC/AArch64/SVE/inch.s @@ -164,3 +164,43 @@ inch x0, #28 // CHECK-ENCODING: [0x80,0xe3,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 e3 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +inch z0.h +// CHECK-INST: inch z0.h +// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 70 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +inch z0.h, all, mul #16 +// CHECK-INST: inch z0.h, all, mul #16 +// CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 7f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +inch z0.h, all +// CHECK-INST: inch z0.h +// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 70 04 <unknown> diff --git a/test/MC/AArch64/SVE/incp-diagnostics.s b/test/MC/AArch64/SVE/incp-diagnostics.s index 71cc91f6d02d..1cc766fcd8b2 100644 --- a/test/MC/AArch64/SVE/incp-diagnostics.s +++ b/test/MC/AArch64/SVE/incp-diagnostics.s @@ -36,3 +36,13 @@ incp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: incp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +incp z31.d, p7 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incp z31.d, p7 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/incp.s b/test/MC/AArch64/SVE/incp.s index c897e846fd05..6bc2c5160925 100644 --- a/test/MC/AArch64/SVE/incp.s +++ b/test/MC/AArch64/SVE/incp.s @@ -72,3 +72,19 @@ incp z31.d, p15 // CHECK-ENCODING: [0xff,0x81,0xec,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 81 ec 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +incp z31.d, p15 +// CHECK-INST: incp z31.d, p15 +// CHECK-ENCODING: [0xff,0x81,0xec,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 81 ec 25 <unknown> diff --git a/test/MC/AArch64/SVE/incw-diagnostics.s b/test/MC/AArch64/SVE/incw-diagnostics.s index e1a85edc931c..88335e9c5d72 100644 --- a/test/MC/AArch64/SVE/incw-diagnostics.s +++ b/test/MC/AArch64/SVE/incw-diagnostics.s @@ -61,3 +61,25 @@ incw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: incw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +incw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +incw z0.s, all, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incw z0.s, all, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +incw z0.s, all +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: incw z0.s, all +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/incw.s b/test/MC/AArch64/SVE/incw.s index a9e34dad08c3..fb6a05ee6f57 100644 --- a/test/MC/AArch64/SVE/incw.s +++ b/test/MC/AArch64/SVE/incw.s @@ -165,3 +165,43 @@ incw x0, #28 // CHECK-ENCODING: [0x80,0xe3,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 e3 b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incw z0.s +// CHECK-INST: incw z0.s +// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 b0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incw z0.s, all, mul #16 +// CHECK-INST: incw z0.s, all, mul #16 +// CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 bf 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +incw z0.s, all +// CHECK-INST: incw z0.s +// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 b0 04 <unknown> diff --git a/test/MC/AArch64/SVE/index-diagnostics.s b/test/MC/AArch64/SVE/index-diagnostics.s index be42c9107233..3b2a4aa656fd 100644 --- a/test/MC/AArch64/SVE/index-diagnostics.s +++ b/test/MC/AArch64/SVE/index-diagnostics.s @@ -56,3 +56,43 @@ index z17.d, w9, w7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15]. // CHECK-NEXT: index z17.d, w9, w7 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p0/z, z28.d +index z21.d, x10, x21 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z21.d, x10, x21 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +index z21.d, x10, x21 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z21.d, x10, x21 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +index z23.d, x13, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z23.d, x13, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +index z23.d, x13, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z23.d, x13, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +index z23.d, #13, x8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z23.d, #13, x8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +index z23.d, #13, x8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: index z23.d, #13, x8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/insr-diagnostics.s b/test/MC/AArch64/SVE/insr-diagnostics.s index e0ec3e6414c8..a0afb22f8fdf 100644 --- a/test/MC/AArch64/SVE/insr-diagnostics.s +++ b/test/MC/AArch64/SVE/insr-diagnostics.s @@ -43,3 +43,19 @@ insr z31.d, b0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: insr z31.d, b0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +insr z31.d, xzr +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: insr z31.d, xzr +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z4.d, p0/z, z6.d +insr z4.d, d31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: insr z4.d, d31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/insr.s b/test/MC/AArch64/SVE/insr.s index 7e13a1b93fe5..262611300019 100644 --- a/test/MC/AArch64/SVE/insr.s +++ b/test/MC/AArch64/SVE/insr.s @@ -78,3 +78,31 @@ insr z31.d, d31 // CHECK-ENCODING: [0xff,0x3b,0xf4,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 3b f4 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +insr z31.d, xzr +// CHECK-INST: insr z31.d, xzr +// CHECK-ENCODING: [0xff,0x3b,0xe4,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 3b e4 05 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +insr z4.d, d31 +// CHECK-INST: insr z4.d, d31 +// CHECK-ENCODING: [0xe4,0x3b,0xf4,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 3b f4 05 <unknown> diff --git a/test/MC/AArch64/SVE/lasta-diagnostics.s b/test/MC/AArch64/SVE/lasta-diagnostics.s index dd8155521f5e..b153a67f35f6 100644 --- a/test/MC/AArch64/SVE/lasta-diagnostics.s +++ b/test/MC/AArch64/SVE/lasta-diagnostics.s @@ -52,3 +52,31 @@ lasta d0, p7, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: lasta d0, p7, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +lasta x0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lasta x0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lasta x0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lasta x0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p7/z, z6.d +lasta d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lasta d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lasta d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lasta d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/lastb-diagnostics.s b/test/MC/AArch64/SVE/lastb-diagnostics.s index ed92c76cadf6..b86654ffc12d 100644 --- a/test/MC/AArch64/SVE/lastb-diagnostics.s +++ b/test/MC/AArch64/SVE/lastb-diagnostics.s @@ -52,3 +52,31 @@ lastb d0, p7, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: lastb d0, p7, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +lastb x0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lastb x0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lastb x0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lastb x0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p7/z, z6.d +lastb d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lastb d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lastb d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lastb d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1b-diagnostics.s b/test/MC/AArch64/SVE/ld1b-diagnostics.s index 4d4da4021e33..70fecbf5805d 100644 --- a/test/MC/AArch64/SVE/ld1b-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1b-diagnostics.s @@ -177,3 +177,19 @@ ld1b z0.d, p0/z, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1b { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1b { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1b { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1d-diagnostics.s b/test/MC/AArch64/SVE/ld1d-diagnostics.s index cedb48b41719..2ba540699567 100644 --- a/test/MC/AArch64/SVE/ld1d-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1d-diagnostics.s @@ -132,3 +132,19 @@ ld1d z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1d { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1d { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1d { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1h-diagnostics.s b/test/MC/AArch64/SVE/ld1h-diagnostics.s index 7c8694131f86..8643a051fe9b 100644 --- a/test/MC/AArch64/SVE/ld1h-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1h-diagnostics.s @@ -192,3 +192,19 @@ ld1h z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1h { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1h { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1h { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rb-diagnostics.s b/test/MC/AArch64/SVE/ld1rb-diagnostics.s index 18532c78c87a..c862eb5cdb16 100644 --- a/test/MC/AArch64/SVE/ld1rb-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rb-diagnostics.s @@ -21,3 +21,19 @@ ld1rb z0.b, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rb z0.b, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rb { z31.d }, p7/z, [sp, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rb { z31.d }, p7/z, [sp, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rb { z31.d }, p7/z, [sp, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rb { z31.d }, p7/z, [sp, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rd-diagnostics.s b/test/MC/AArch64/SVE/ld1rd-diagnostics.s index 66eaa8b43a00..e85ffa16ef52 100644 --- a/test/MC/AArch64/SVE/ld1rd-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rd-diagnostics.s @@ -55,3 +55,19 @@ ld1rd z0.d, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rd z0.d, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rd { z31.d }, p7/z, [sp, #504] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rd { z31.d }, p7/z, [sp, #504] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rd { z31.d }, p7/z, [sp, #504] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rd { z31.d }, p7/z, [sp, #504] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rh-diagnostics.s b/test/MC/AArch64/SVE/ld1rh-diagnostics.s index bdd4b06c4f62..2665e859d81e 100644 --- a/test/MC/AArch64/SVE/ld1rh-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rh-diagnostics.s @@ -45,3 +45,19 @@ ld1rh z0.h, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rh z0.h, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rh { z31.d }, p7/z, [sp, #126] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rh { z31.d }, p7/z, [sp, #126] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rh { z31.d }, p7/z, [sp, #126] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rh { z31.d }, p7/z, [sp, #126] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rqb-diagnostics.s b/test/MC/AArch64/SVE/ld1rqb-diagnostics.s index 0a8a766d6137..94a8d5c3f5c8 100644 --- a/test/MC/AArch64/SVE/ld1rqb-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rqb-diagnostics.s @@ -79,3 +79,19 @@ ld1rqb z0.b, p0/z, [x0, w1, uxtw] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: ld1rqb z0.b, p0/z, [x0, w1, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +ld1rqb { z21.b }, p5/z, [x10, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqb { z21.b }, p5/z, [x10, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld1rqb { z21.b }, p5/z, [x10, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqb { z21.b }, p5/z, [x10, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rqd-diagnostics.s b/test/MC/AArch64/SVE/ld1rqd-diagnostics.s index 1ea8188d6074..8c4ac3ecad6d 100644 --- a/test/MC/AArch64/SVE/ld1rqd-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rqd-diagnostics.s @@ -79,3 +79,19 @@ ld1rqd z0.d, p0/z, [x0, w1, uxtw #1] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: ld1rqd z0.d, p0/z, [x0, w1, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z23.d, p3/z, z30.d +ld1rqd { z23.d }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqd { z23.d }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +ld1rqd { z23.d }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqd { z23.d }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rqh-diagnostics.s b/test/MC/AArch64/SVE/ld1rqh-diagnostics.s index aecc63e76a10..960dda35db6e 100644 --- a/test/MC/AArch64/SVE/ld1rqh-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rqh-diagnostics.s @@ -79,3 +79,19 @@ ld1rqh z0.h, p0/z, [x0, w1, uxtw #1] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld1rqh z0.h, p0/z, [x0, w1, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z23.h, p3/z, z30.h +ld1rqh { z23.h }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqh { z23.h }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +ld1rqh { z23.h }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqh { z23.h }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rqw-diagnostics.s b/test/MC/AArch64/SVE/ld1rqw-diagnostics.s index 477af4242e9a..b4d45e5ceb6d 100644 --- a/test/MC/AArch64/SVE/ld1rqw-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rqw-diagnostics.s @@ -79,3 +79,19 @@ ld1rqw z0.s, p0/z, [x0, w1, uxtw #1] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: ld1rqw z0.s, p0/z, [x0, w1, uxtw #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z23.s, p3/z, z30.s +ld1rqw { z23.s }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +ld1rqw { z23.s }, p3/z, [x13, #112] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rqw { z23.s }, p3/z, [x13, #112] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rsb-diagnostics.s b/test/MC/AArch64/SVE/ld1rsb-diagnostics.s index 7950eca94adf..28c6ecd9013d 100644 --- a/test/MC/AArch64/SVE/ld1rsb-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rsb-diagnostics.s @@ -30,3 +30,19 @@ ld1rsb z0.h, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rsb z0.h, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rsb { z31.d }, p7/z, [sp, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rsb { z31.d }, p7/z, [sp, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rsh-diagnostics.s b/test/MC/AArch64/SVE/ld1rsh-diagnostics.s index b33c7934ccb8..ae13b87b61ee 100644 --- a/test/MC/AArch64/SVE/ld1rsh-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rsh-diagnostics.s @@ -40,3 +40,19 @@ ld1rsh z0.s, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rsh z0.s, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rsh { z31.d }, p7/z, [sp, #126] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsh { z31.d }, p7/z, [sp, #126] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rsh { z31.d }, p7/z, [sp, #126] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsh { z31.d }, p7/z, [sp, #126] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rsw-diagnostics.s b/test/MC/AArch64/SVE/ld1rsw-diagnostics.s index 4d7cf63980dc..02da02d5cf5b 100644 --- a/test/MC/AArch64/SVE/ld1rsw-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rsw-diagnostics.s @@ -45,3 +45,19 @@ ld1rsw z0.d, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rsw z0.d, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rsw { z31.d }, p7/z, [sp, #252] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsw { z31.d }, p7/z, [sp, #252] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rsw { z31.d }, p7/z, [sp, #252] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rsw { z31.d }, p7/z, [sp, #252] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1rw-diagnostics.s b/test/MC/AArch64/SVE/ld1rw-diagnostics.s index e5e55c9da562..c4bc362d7d0b 100644 --- a/test/MC/AArch64/SVE/ld1rw-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1rw-diagnostics.s @@ -50,3 +50,19 @@ ld1rw z0.s, p8/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: ld1rw z0.s, p8/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +ld1rw { z31.d }, p7/z, [sp, #252] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rw { z31.d }, p7/z, [sp, #252] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ld1rw { z31.d }, p7/z, [sp, #252] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1rw { z31.d }, p7/z, [sp, #252] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1sb-diagnostics.s b/test/MC/AArch64/SVE/ld1sb-diagnostics.s index e936f576fdef..0bbccfc0c956 100644 --- a/test/MC/AArch64/SVE/ld1sb-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1sb-diagnostics.s @@ -175,3 +175,19 @@ ld1sb z0.d, p0/z, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1sb { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sb { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1sb { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sb { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1sh-diagnostics.s b/test/MC/AArch64/SVE/ld1sh-diagnostics.s index 91fc364d7dc3..d423480a2844 100644 --- a/test/MC/AArch64/SVE/ld1sh-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1sh-diagnostics.s @@ -191,3 +191,19 @@ ld1sh z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1sh { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sh { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1sh { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sh { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1sw-diagnostics.s b/test/MC/AArch64/SVE/ld1sw-diagnostics.s index 2ecf3b7fce32..1061e87301dc 100644 --- a/test/MC/AArch64/SVE/ld1sw-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1sw-diagnostics.s @@ -161,3 +161,19 @@ ld1sw z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1sw { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1sw { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld1w-diagnostics.s b/test/MC/AArch64/SVE/ld1w-diagnostics.s index d1031eac60bf..1aafc27f8585 100644 --- a/test/MC/AArch64/SVE/ld1w-diagnostics.s +++ b/test/MC/AArch64/SVE/ld1w-diagnostics.s @@ -177,3 +177,19 @@ ld1w z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ld1w { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ld1w { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld1w { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld2b-diagnostics.s b/test/MC/AArch64/SVE/ld2b-diagnostics.s index 136bf026c6ae..3eae31f363d4 100644 --- a/test/MC/AArch64/SVE/ld2b-diagnostics.s +++ b/test/MC/AArch64/SVE/ld2b-diagnostics.s @@ -89,3 +89,19 @@ ld2b { v0.2d, v1.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld2b { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld2d-diagnostics.s b/test/MC/AArch64/SVE/ld2d-diagnostics.s index 7c58ef11530c..7b64621635d8 100644 --- a/test/MC/AArch64/SVE/ld2d-diagnostics.s +++ b/test/MC/AArch64/SVE/ld2d-diagnostics.s @@ -94,3 +94,19 @@ ld2d { v0.2d, v1.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld2d { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld2h-diagnostics.s b/test/MC/AArch64/SVE/ld2h-diagnostics.s index e3d29dc2c34d..4568fe396ee1 100644 --- a/test/MC/AArch64/SVE/ld2h-diagnostics.s +++ b/test/MC/AArch64/SVE/ld2h-diagnostics.s @@ -94,3 +94,19 @@ ld2h { v0.2d, v1.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld2h { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld2w-diagnostics.s b/test/MC/AArch64/SVE/ld2w-diagnostics.s index cf09aa26d1f7..66acedab1e9f 100644 --- a/test/MC/AArch64/SVE/ld2w-diagnostics.s +++ b/test/MC/AArch64/SVE/ld2w-diagnostics.s @@ -94,3 +94,19 @@ ld2w { v0.2d, v1.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld2w { v0.2d, v1.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld3b-diagnostics.s b/test/MC/AArch64/SVE/ld3b-diagnostics.s index c93ec32ae867..388545258bc6 100644 --- a/test/MC/AArch64/SVE/ld3b-diagnostics.s +++ b/test/MC/AArch64/SVE/ld3b-diagnostics.s @@ -89,3 +89,19 @@ ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3b { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld3d-diagnostics.s b/test/MC/AArch64/SVE/ld3d-diagnostics.s index 33b063733e1b..f672fb832004 100644 --- a/test/MC/AArch64/SVE/ld3d-diagnostics.s +++ b/test/MC/AArch64/SVE/ld3d-diagnostics.s @@ -94,3 +94,19 @@ ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3d { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld3h-diagnostics.s b/test/MC/AArch64/SVE/ld3h-diagnostics.s index cf0423a128ab..c5ae5dfcda53 100644 --- a/test/MC/AArch64/SVE/ld3h-diagnostics.s +++ b/test/MC/AArch64/SVE/ld3h-diagnostics.s @@ -94,3 +94,19 @@ ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld3w-diagnostics.s b/test/MC/AArch64/SVE/ld3w-diagnostics.s index 758fc04667df..d3082c14b8fe 100644 --- a/test/MC/AArch64/SVE/ld3w-diagnostics.s +++ b/test/MC/AArch64/SVE/ld3w-diagnostics.s @@ -94,3 +94,19 @@ ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld3w { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld4b-diagnostics.s b/test/MC/AArch64/SVE/ld4b-diagnostics.s index 3120c49fb1ba..65c5bcd26fc6 100644 --- a/test/MC/AArch64/SVE/ld4b-diagnostics.s +++ b/test/MC/AArch64/SVE/ld4b-diagnostics.s @@ -89,3 +89,19 @@ ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4b { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld4d-diagnostics.s b/test/MC/AArch64/SVE/ld4d-diagnostics.s index 8b5715d2249c..ea70ea037012 100644 --- a/test/MC/AArch64/SVE/ld4d-diagnostics.s +++ b/test/MC/AArch64/SVE/ld4d-diagnostics.s @@ -94,3 +94,19 @@ ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld4h-diagnostics.s b/test/MC/AArch64/SVE/ld4h-diagnostics.s index 45f5bd5108cd..dc5485484f7b 100644 --- a/test/MC/AArch64/SVE/ld4h-diagnostics.s +++ b/test/MC/AArch64/SVE/ld4h-diagnostics.s @@ -94,3 +94,19 @@ ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4h { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ld4w-diagnostics.s b/test/MC/AArch64/SVE/ld4w-diagnostics.s index 86547c22b1a5..d4633dd4d55d 100644 --- a/test/MC/AArch64/SVE/ld4w-diagnostics.s +++ b/test/MC/AArch64/SVE/ld4w-diagnostics.s @@ -94,3 +94,19 @@ ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ld4w { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1b-diagnostics.s b/test/MC/AArch64/SVE/ldff1b-diagnostics.s index 2ce58d894fb5..8de73ef3e6f8 100644 --- a/test/MC/AArch64/SVE/ldff1b-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1b-diagnostics.s @@ -112,3 +112,19 @@ ldff1b z0.d, p0/z, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1b { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1b { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1d-diagnostics.s b/test/MC/AArch64/SVE/ldff1d-diagnostics.s index e5aec40163f2..29978c7303bc 100644 --- a/test/MC/AArch64/SVE/ldff1d-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1d-diagnostics.s @@ -111,3 +111,19 @@ ldff1d z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1d { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1d { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1d { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1d { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1h-diagnostics.s b/test/MC/AArch64/SVE/ldff1h-diagnostics.s index e568031c4791..8674d095351b 100644 --- a/test/MC/AArch64/SVE/ldff1h-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1h-diagnostics.s @@ -141,3 +141,19 @@ ldff1h z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1h { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1h { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1h { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1h { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1sb-diagnostics.s b/test/MC/AArch64/SVE/ldff1sb-diagnostics.s index b9bd9e470c34..23cca8c14545 100644 --- a/test/MC/AArch64/SVE/ldff1sb-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1sb-diagnostics.s @@ -115,3 +115,19 @@ ldff1sb z0.d, p0/z, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1sb { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sb { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1sb { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sb { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1sh-diagnostics.s b/test/MC/AArch64/SVE/ldff1sh-diagnostics.s index e58d9151b85d..4a8d329f973c 100644 --- a/test/MC/AArch64/SVE/ldff1sh-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1sh-diagnostics.s @@ -135,3 +135,19 @@ ldff1sh z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1sh { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sh { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1sh { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sh { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1sw-diagnostics.s b/test/MC/AArch64/SVE/ldff1sw-diagnostics.s index 4571ee664618..ab096f36b8c1 100644 --- a/test/MC/AArch64/SVE/ldff1sw-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1sw-diagnostics.s @@ -116,3 +116,19 @@ ldff1sw z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1sw { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sw { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1sw { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1sw { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldff1w-diagnostics.s b/test/MC/AArch64/SVE/ldff1w-diagnostics.s index 36a7eec8af56..e2cec7c77101 100644 --- a/test/MC/AArch64/SVE/ldff1w-diagnostics.s +++ b/test/MC/AArch64/SVE/ldff1w-diagnostics.s @@ -141,3 +141,19 @@ ldff1w z0.d, p0/z, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldff1w { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1w { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldff1w { z0.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldff1w { z0.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1b-diagnostics.s b/test/MC/AArch64/SVE/ldnf1b-diagnostics.s index d680595801dc..b24c15308f4c 100644 --- a/test/MC/AArch64/SVE/ldnf1b-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1b-diagnostics.s @@ -85,3 +85,19 @@ ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1b { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1d-diagnostics.s b/test/MC/AArch64/SVE/ldnf1d-diagnostics.s index c1a47ba02119..8c29bddea0c7 100644 --- a/test/MC/AArch64/SVE/ldnf1d-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1d-diagnostics.s @@ -40,3 +40,19 @@ ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1d { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1h-diagnostics.s b/test/MC/AArch64/SVE/ldnf1h-diagnostics.s index ef4d80a60a7d..6d61423f9997 100644 --- a/test/MC/AArch64/SVE/ldnf1h-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1h-diagnostics.s @@ -70,3 +70,19 @@ ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s b/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s index a4d42559d01a..23e816425c5d 100644 --- a/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s @@ -84,3 +84,19 @@ ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s b/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s index 7e62d7959576..3071cc6e4694 100644 --- a/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s @@ -69,3 +69,19 @@ ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s b/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s index 0312815614a6..5c133f7a0095 100644 --- a/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s @@ -54,3 +54,19 @@ ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnf1w-diagnostics.s b/test/MC/AArch64/SVE/ldnf1w-diagnostics.s index 688816e56da8..2fd7123b4925 100644 --- a/test/MC/AArch64/SVE/ldnf1w-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnf1w-diagnostics.s @@ -55,3 +55,19 @@ ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnf1w { z21.d }, p5/z, [x10, #5, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnt1b-diagnostics.s b/test/MC/AArch64/SVE/ldnt1b-diagnostics.s index 8fa065b13b52..b02f633f5ca1 100644 --- a/test/MC/AArch64/SVE/ldnt1b-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnt1b-diagnostics.s @@ -59,3 +59,19 @@ ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +ldnt1b { z0.b }, p0/z, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1b { z0.b }, p0/z, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnt1d-diagnostics.s b/test/MC/AArch64/SVE/ldnt1d-diagnostics.s index aff76a998623..2aba4dc2e946 100644 --- a/test/MC/AArch64/SVE/ldnt1d-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnt1d-diagnostics.s @@ -59,3 +59,19 @@ ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnt1d { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnt1h-diagnostics.s b/test/MC/AArch64/SVE/ldnt1h-diagnostics.s index 2af29bab9fe1..fce1fb5ae5b5 100644 --- a/test/MC/AArch64/SVE/ldnt1h-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnt1h-diagnostics.s @@ -59,3 +59,19 @@ ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnt1h { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ldnt1w-diagnostics.s b/test/MC/AArch64/SVE/ldnt1w-diagnostics.s index 67a9644078e6..23ba16a0315c 100644 --- a/test/MC/AArch64/SVE/ldnt1w-diagnostics.s +++ b/test/MC/AArch64/SVE/ldnt1w-diagnostics.s @@ -59,3 +59,19 @@ ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ldnt1w { v0.2d }, p0/z, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/lsl-diagnostics.s b/test/MC/AArch64/SVE/lsl-diagnostics.s index 067acf9ace6e..517384896c1c 100644 --- a/test/MC/AArch64/SVE/lsl-diagnostics.s +++ b/test/MC/AArch64/SVE/lsl-diagnostics.s @@ -120,3 +120,31 @@ lsl z0.b, p8/m, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +lsl z31.d, z31.d, #63 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsl z31.d, z31.d, #63 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lsl z31.d, z31.d, #63 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsl z31.d, z31.d, #63 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +lsl z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsl z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +lsl z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsl z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/lsl.s b/test/MC/AArch64/SVE/lsl.s index 0e8820e19865..38b895b745a6 100644 --- a/test/MC/AArch64/SVE/lsl.s +++ b/test/MC/AArch64/SVE/lsl.s @@ -162,3 +162,55 @@ lsl z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x8c,0xa2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 8c a2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 <unknown> + +lsl z31.d, p0/m, z31.d, #63 +// CHECK-INST: lsl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 83 c3 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +lsl z31.d, p0/m, z31.d, #63 +// CHECK-INST: lsl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 83 c3 04 <unknown> + +movprfx z0.s, p0/z, z7.s +// CHECK-INST: movprfx z0.s, p0/z, z7.s +// CHECK-ENCODING: [0xe0,0x20,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 90 04 <unknown> + +lsl z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x9b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 9b 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +lsl z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x9b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 9b 04 <unknown> diff --git a/test/MC/AArch64/SVE/lslr.s b/test/MC/AArch64/SVE/lslr.s index ad8941f201fe..16e19dec9562 100644 --- a/test/MC/AArch64/SVE/lslr.s +++ b/test/MC/AArch64/SVE/lslr.s @@ -30,3 +30,31 @@ lslr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd7,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 d7 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +lslr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: lslr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d7 04 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +lslr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: lslr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d7 04 <unknown> diff --git a/test/MC/AArch64/SVE/lsr-diagnostics.s b/test/MC/AArch64/SVE/lsr-diagnostics.s index 77ad88d6676f..0de5bcd522c9 100644 --- a/test/MC/AArch64/SVE/lsr-diagnostics.s +++ b/test/MC/AArch64/SVE/lsr-diagnostics.s @@ -121,3 +121,31 @@ lsr z0.b, p8/m, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +lsr z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsr z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +lsr z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsr z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +lsr z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsr z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +lsr z0.s, z1.s, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: lsr z0.s, z1.s, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/lsr.s b/test/MC/AArch64/SVE/lsr.s index 9ef662302a94..481326124930 100644 --- a/test/MC/AArch64/SVE/lsr.s +++ b/test/MC/AArch64/SVE/lsr.s @@ -162,3 +162,55 @@ lsr z0.s, z1.s, z2.d // CHECK-ENCODING: [0x20,0x84,0xa2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 84 a2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 <unknown> + +lsr z31.d, p0/m, z31.d, #64 +// CHECK-INST: lsr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x81,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 81 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +lsr z31.d, p0/m, z31.d, #64 +// CHECK-INST: lsr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x81,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 81 04 <unknown> + +movprfx z0.s, p0/z, z7.s +// CHECK-INST: movprfx z0.s, p0/z, z7.s +// CHECK-ENCODING: [0xe0,0x20,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 20 90 04 <unknown> + +lsr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x99,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 99 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +lsr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x99,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 99 04 <unknown> diff --git a/test/MC/AArch64/SVE/lsrr.s b/test/MC/AArch64/SVE/lsrr.s index a6bca70103a5..ec87a711dbfa 100644 --- a/test/MC/AArch64/SVE/lsrr.s +++ b/test/MC/AArch64/SVE/lsrr.s @@ -30,3 +30,31 @@ lsrr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd5,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 d5 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +lsrr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: lsrr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d5 04 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +lsrr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: lsrr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x80,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 80 d5 04 <unknown> diff --git a/test/MC/AArch64/SVE/mad.s b/test/MC/AArch64/SVE/mad.s index 3a5d81e32611..b9712d6ef3bb 100644 --- a/test/MC/AArch64/SVE/mad.s +++ b/test/MC/AArch64/SVE/mad.s @@ -30,3 +30,31 @@ mad z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 df c1 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +mad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 df c1 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +mad z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mad z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 df c1 04 <unknown> diff --git a/test/MC/AArch64/SVE/mla.s b/test/MC/AArch64/SVE/mla.s index 4911e6afd925..d76ee0996a8e 100644 --- a/test/MC/AArch64/SVE/mla.s +++ b/test/MC/AArch64/SVE/mla.s @@ -30,3 +30,31 @@ mla z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 5c df 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +mla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c df 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +mla z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mla z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x5c,0xdf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 5c df 04 <unknown> diff --git a/test/MC/AArch64/SVE/mls.s b/test/MC/AArch64/SVE/mls.s index 8c088fdd98b0..32d3d0e2dd8b 100644 --- a/test/MC/AArch64/SVE/mls.s +++ b/test/MC/AArch64/SVE/mls.s @@ -30,3 +30,31 @@ mls z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 7c df 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +mls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c df 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +mls z0.d, p7/m, z1.d, z31.d +// CHECK-INST: mls z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xdf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 7c df 04 <unknown> diff --git a/test/MC/AArch64/SVE/mov-diagnostics.s b/test/MC/AArch64/SVE/mov-diagnostics.s index 8f0eef0fa4d0..23b8b55be96e 100644 --- a/test/MC/AArch64/SVE/mov-diagnostics.s +++ b/test/MC/AArch64/SVE/mov-diagnostics.s @@ -412,3 +412,79 @@ mov z24.q, z21.q[4] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. // CHECK-NEXT: mov z24.q, z21.q[4] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +mov z31.b, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.b, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mov z31.b, wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.b, wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +mov z0.d, #0xe0000000000003ff +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z0.d, #0xe0000000000003ff +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +mov z0.d, #0xe0000000000003ff +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z0.d, #0xe0000000000003ff +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z4.d, p7/z, z6.d +mov z4.d, p7/m, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z4.d, p7/m, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mov z31.d, p15/m, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, p15/m, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +mov z0.d, d0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z0.d, d0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +mov z0.d, d0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z0.d, d0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +mov z31.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mov z31.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +mov z31.d, z31.d[7] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, z31.d[7] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mov z31.d, z31.d[7] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mov z31.d, z31.d[7] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/mov.s b/test/MC/AArch64/SVE/mov.s index c0a50e39c706..5704e50c941a 100644 --- a/test/MC/AArch64/SVE/mov.s +++ b/test/MC/AArch64/SVE/mov.s @@ -660,3 +660,79 @@ mov p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7d 0f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p7/z, z6.d +// CHECK-INST: movprfx z31.d, p7/z, z6.d +// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 3c d0 04 <unknown> + +mov z31.d, p7/m, sp +// CHECK-INST: mov z31.d, p7/m, sp +// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf e8 05 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +mov z31.d, p7/m, sp +// CHECK-INST: mov z31.d, p7/m, sp +// CHECK-ENCODING: [0xff,0xbf,0xe8,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf e8 05 <unknown> + +movprfx z21.d, p7/z, z28.d +// CHECK-INST: movprfx z21.d, p7/z, z28.d +// CHECK-ENCODING: [0x95,0x3f,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 3f d0 04 <unknown> + +mov z21.d, p7/m, #-128, lsl #8 +// CHECK-INST: mov z21.d, p7/m, #-32768 +// CHECK-ENCODING: [0x15,0x70,0xd7,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 15 70 d7 05 <unknown> + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 <unknown> + +mov z21.d, p15/m, #-128, lsl #8 +// CHECK-INST: mov z21.d, p15/m, #-32768 +// CHECK-ENCODING: [0x15,0x70,0xdf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 15 70 df 05 <unknown> + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +mov z4.d, p7/m, d31 +// CHECK-INST: mov z4.d, p7/m, d31 +// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f e0 05 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +mov z4.d, p7/m, d31 +// CHECK-INST: mov z4.d, p7/m, d31 +// CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f e0 05 <unknown> diff --git a/test/MC/AArch64/SVE/movprfx-diagnostics.s b/test/MC/AArch64/SVE/movprfx-diagnostics.s new file mode 100644 index 000000000000..56b1f5cfc725 --- /dev/null +++ b/test/MC/AArch64/SVE/movprfx-diagnostics.s @@ -0,0 +1,193 @@ +// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s + +// ------------------------------------------------------------------------- // +// Different destination register (unary) + +movprfx z0, z1 +abs z2.d, p0/m, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination +// CHECK-NEXT: abs z2.d, p0/m, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different destination register (binary) + +movprfx z0, z1 +add z2.d, p0/m, z2.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination +// CHECK-NEXT: add z2.d, p0/m, z2.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different destination register (wide element) + +movprfx z0, z1 +asr z2.s, p0/m, z2.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination +// CHECK-NEXT: asr z2.s, p0/m, z2.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different destination register (ternary) + +movprfx z0, z1 +mla z3.d, p0/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx writing to a different destination +// CHECK-NEXT: mla z3.d, p0/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Destination used in other operand (unary) + +movprfx z0, z1 +abs z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: abs z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z1.d +cpy z0.d, p0/m, d0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: cpy z0.d, p0/m, d0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z1.d +mov z0.d, p0/m, d0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: mov z0.d, p0/m, d0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Destination used in other operand (binary) + +movprfx z0, z1 +add z0.d, p0/m, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: add z0.d, p0/m, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Destination used in other operand (wide element) + +movprfx z0, z1 +asr z0.s, p0/m, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: asr z0.s, p0/m, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Destination used in other operand (ternary) + +movprfx z0, z1 +mla z0.d, p0/m, z0.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: mla z0.d, p0/m, z0.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different general predicate (unary) + +movprfx z0.d, p0/m, z1.d +abs z0.d, p1/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate +// CHECK-NEXT: abs z0.d, p1/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different general predicate (binary) + +movprfx z0.d, p0/m, z1.d +add z0.d, p1/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate +// CHECK-NEXT: add z0.d, p1/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different general predicate (wide element) + +movprfx z0.d, p0/m, z1.d +asr z0.s, p1/m, z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate +// CHECK-NEXT: asr z0.s, p1/m, z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different general predicate (ternary) + +movprfx z0.d, p0/m, z1.d +mla z0.d, p1/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx using a different general predicate +// CHECK-NEXT: mla z0.d, p1/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different element size (unary) + +movprfx z0.s, p0/m, z1.s +abs z0.d, p0/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: abs z0.d, p0/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different element size (binary) + +movprfx z0.s, p0/m, z1.s +add z0.d, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different element size (wide element) + +movprfx z0.d, p0/m, z1.d +asr z0.s, p0/m, z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Different element size (ternary) + +movprfx z0.s, p0/m, z1.s +mla z0.d, p0/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Predicated movprfx with non-predicated instruction. + +movprfx z0.d, p0/m, z1.d +add z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: add z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Ensure we don't try to apply a prefix to subsequent instructions (upon failure) + +movprfx z0, z1 +add z0.d, z1.d, z2.d +add z0.d, z1.d, z2.d +// CHECK: [[@LINE-2]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: add z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}: +// CHECK: add z0.d, z1.d, z2.d diff --git a/test/MC/AArch64/SVE/movprfx.s b/test/MC/AArch64/SVE/movprfx.s new file mode 100644 index 000000000000..8065967ebc3a --- /dev/null +++ b/test/MC/AArch64/SVE/movprfx.s @@ -0,0 +1,97 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +// This test file is mostly empty because most 'movprfx' tests are embedded +// with other instructions that are destructive and can be prefixed +// by the movprfx instruction. A list of destructive instructions +// is given below by their mnemonic, which have tests in corresponding +// <mnemonic>.s test files: +// +// abs decp fdivr fnmla fsubr mov sdivr sqincw umulh +// add eon fmad fnmls ftmad msb sdot sqsub uqadd +// and eor fmax fnmsb incd mul smax sub uqdecd +// asr ext fmaxnm frecpx inch neg smin subr uqdech +// asrd fabd fmin frinta incp not smulh sxtb uqdecp +// asrr fabs fminnm frinti incw orn splice sxth uqdecw +// bic fadd fmla frintm insr orr sqadd sxtw uqincd +// clasta fcadd fmls frintn lsl rbit sqdecd uabd uqinch +// clastb fcmla fmov frintp lslr revb sqdech ucvtf uqincp +// cls fcpy fmsb frintx lsr revh sqdecp udiv uqincw +// clz fcvt fmul frintz lsrr revw sqdecw udivr uqsub +// cnot fcvtzs fmulx fscale mad sabd sqincd udot uxtb +// cnt fcvtzu fneg fsqrt mla scvtf sqinch umax uxth +// cpy fdiv fnmad fsub mls sdiv sqincp umin uxtw + + +// ------------------------------------------------------------------------- // +// Test compatibility with MOVPRFX instruction with BRK and HLT. +// +// Section 7.1.2 of the SVE Architecture Reference Manual Supplement: +// "it is permitted to use MOVPRFX to prefix an A64 BRK or HLT instruction" + +movprfx z0, z1 +// CHECK-INST: movprfx z0, z1 +// CHECK-ENCODING: [0x20,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc 20 04 <unknown> + +hlt #1 +// CHECK-INST: hlt #0x1 +// CHECK-ENCODING: [0x20,0x00,0x40,0xd4] + +movprfx z0.d, p0/z, z1.d +// CHECK-INST: movprfx z0.d, p0/z, z1.d +// CHECK-ENCODING: [0x20,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 20 d0 04 <unknown> + +hlt #1 +// CHECK-INST: hlt #0x1 +// CHECK-ENCODING: [0x20,0x00,0x40,0xd4] + +movprfx z0, z1 +// CHECK-INST: movprfx z0, z1 +// CHECK-ENCODING: [0x20,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc 20 04 <unknown> + +brk #1 +// CHECK-INST: brk #0x1 +// CHECK-ENCODING: [0x20,0x00,0x20,0xd4] + +movprfx z0.d, p0/z, z1.d +// CHECK-INST: movprfx z0.d, p0/z, z1.d +// CHECK-ENCODING: [0x20,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 20 d0 04 <unknown> + +brk #1 +// CHECK-INST: brk #0x1 +// CHECK-ENCODING: [0x20,0x00,0x20,0xd4] + +// ------------------------------------------------------------------------- // +// Ensure we don't try to apply a prefix to subsequent instructions (upon success) + +movprfx z0, z1 +// CHECK-INST: movprfx z0, z1 +// CHECK-ENCODING: [0x20,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 bc 20 04 <unknown> + +add z0.d, p0/m, z0.d, z1.d +// CHECK-INST: add z0.d, p0/m, z0.d, z1.d +// CHECK-ENCODING: [0x20,0x00,0xc0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 c0 04 <unknown> + +add z0.d, p0/m, z0.d, z1.d +// CHECK-INST: add z0.d, p0/m, z0.d, z1.d +// CHECK-ENCODING: [0x20,0x00,0xc0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 c0 04 <unknown> diff --git a/test/MC/AArch64/SVE/msb.s b/test/MC/AArch64/SVE/msb.s index 048f32160e12..94715616db51 100644 --- a/test/MC/AArch64/SVE/msb.s +++ b/test/MC/AArch64/SVE/msb.s @@ -30,3 +30,31 @@ msb z0.d, p7/m, z1.d, z31.d // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 ff c1 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +msb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: msb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 ff c1 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +msb z0.d, p7/m, z1.d, z31.d +// CHECK-INST: msb z0.d, p7/m, z1.d, z31.d +// CHECK-ENCODING: [0xe0,0xff,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 ff c1 04 <unknown> diff --git a/test/MC/AArch64/SVE/mul-diagnostics.s b/test/MC/AArch64/SVE/mul-diagnostics.s index 745c35d613f8..de08aff0fd5a 100644 --- a/test/MC/AArch64/SVE/mul-diagnostics.s +++ b/test/MC/AArch64/SVE/mul-diagnostics.s @@ -36,3 +36,13 @@ mul z0.b, p8/m, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: mul z0.b, p8/m, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +mul z31.d, z31.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: mul z31.d, z31.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/mul.s b/test/MC/AArch64/SVE/mul.s index f83b88ee7125..d1a1f867847f 100644 --- a/test/MC/AArch64/SVE/mul.s +++ b/test/MC/AArch64/SVE/mul.s @@ -78,3 +78,43 @@ mul z31.d, z31.d, #127 // CHECK-ENCODING: [0xff,0xcf,0xf0,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff cf f0 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +mul z0.d, p7/m, z0.d, z31.d +// CHECK-INST: mul z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +mul z0.d, p7/m, z0.d, z31.d +// CHECK-INST: mul z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d0 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +mul z31.d, z31.d, #127 +// CHECK-INST: mul z31.d, z31.d, #127 +// CHECK-ENCODING: [0xff,0xcf,0xf0,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff cf f0 25 <unknown> diff --git a/test/MC/AArch64/SVE/neg.s b/test/MC/AArch64/SVE/neg.s index 3ad4abf463cc..437f0e959b2d 100644 --- a/test/MC/AArch64/SVE/neg.s +++ b/test/MC/AArch64/SVE/neg.s @@ -54,3 +54,31 @@ neg z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd7,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d7 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +neg z4.d, p7/m, z31.d +// CHECK-INST: neg z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d7 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +neg z4.d, p7/m, z31.d +// CHECK-INST: neg z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d7 04 <unknown> diff --git a/test/MC/AArch64/SVE/not.s b/test/MC/AArch64/SVE/not.s index 67ebce236c26..35e72bb06ac1 100644 --- a/test/MC/AArch64/SVE/not.s +++ b/test/MC/AArch64/SVE/not.s @@ -42,3 +42,31 @@ not p15.b, p15/z, p15.b // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7f 0f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +not z4.d, p7/m, z31.d +// CHECK-INST: not z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xde,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf de 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +not z4.d, p7/m, z31.d +// CHECK-INST: not z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xde,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf de 04 <unknown> diff --git a/test/MC/AArch64/SVE/orn-diagnostics.s b/test/MC/AArch64/SVE/orn-diagnostics.s index d33cf8009068..a9db36ba258c 100644 --- a/test/MC/AArch64/SVE/orn-diagnostics.s +++ b/test/MC/AArch64/SVE/orn-diagnostics.s @@ -77,3 +77,13 @@ orn p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +orn z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: orn z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/orn.s b/test/MC/AArch64/SVE/orn.s index 89b8ea5795e8..1028414070f0 100644 --- a/test/MC/AArch64/SVE/orn.s +++ b/test/MC/AArch64/SVE/orn.s @@ -66,3 +66,19 @@ orn p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xff,0x7d,0x8f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 7d 8f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +orn z0.d, z0.d, #0x6 +// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x03,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 03 05 <unknown> diff --git a/test/MC/AArch64/SVE/orr-diagnostics.s b/test/MC/AArch64/SVE/orr-diagnostics.s index bcea515cc131..7038ea41f470 100644 --- a/test/MC/AArch64/SVE/orr-diagnostics.s +++ b/test/MC/AArch64/SVE/orr-diagnostics.s @@ -92,3 +92,37 @@ orr p0.b, p0/m, p1.b, p2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: orr p0.b, p0/m, p1.b, p2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +orr z0.d, z0.d, #0x6 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: orr z0.d, z0.d, #0x6 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23.d, p0/z, z30.d +orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/orr.s b/test/MC/AArch64/SVE/orr.s index 1cf48fdd7a03..7d00cd8c6cf1 100644 --- a/test/MC/AArch64/SVE/orr.s +++ b/test/MC/AArch64/SVE/orr.s @@ -110,3 +110,43 @@ orr p15.b, p15/z, p15.b, p15.b // CHECK-ENCODING: [0xef,0x7d,0x8f,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ef 7d 8f 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +orr z4.d, p7/m, z4.d, z31.d +// CHECK-INST: orr z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f d8 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +orr z4.d, p7/m, z4.d, z31.d +// CHECK-INST: orr z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f d8 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +orr z0.d, z0.d, #0x6 +// CHECK-INST: orr z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x03,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 03 05 <unknown> diff --git a/test/MC/AArch64/SVE/orv-diagnostics.s b/test/MC/AArch64/SVE/orv-diagnostics.s index 8a64ad89c005..1892321be28b 100644 --- a/test/MC/AArch64/SVE/orv-diagnostics.s +++ b/test/MC/AArch64/SVE/orv-diagnostics.s @@ -31,4 +31,19 @@ orv v0.2d, p7, z31.d orv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: orv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +orv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +orv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: orv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pfalse-diagnostics.s b/test/MC/AArch64/SVE/pfalse-diagnostics.s new file mode 100644 index 000000000000..1a4047d8d80b --- /dev/null +++ b/test/MC/AArch64/SVE/pfalse-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +pfalse p15.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: pfalse p15.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pfalse.s b/test/MC/AArch64/SVE/pfalse.s new file mode 100644 index 000000000000..b1385d8b863f --- /dev/null +++ b/test/MC/AArch64/SVE/pfalse.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pfalse p15.b +// CHECK-INST: pfalse p15.b +// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f e4 18 25 <unknown> diff --git a/test/MC/AArch64/SVE/pfirst-diagnostics.s b/test/MC/AArch64/SVE/pfirst-diagnostics.s new file mode 100644 index 000000000000..6ed891a59f24 --- /dev/null +++ b/test/MC/AArch64/SVE/pfirst-diagnostics.s @@ -0,0 +1,19 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +pfirst p0.h, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: pfirst p0.h, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Tied operands must match + +pfirst p0.b, p15, p1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: pfirst p0.b, p15, p1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pfirst.s b/test/MC/AArch64/SVE/pfirst.s new file mode 100644 index 000000000000..8090bf72a0ef --- /dev/null +++ b/test/MC/AArch64/SVE/pfirst.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pfirst p0.b, p15, p0.b +// CHECK-INST: pfirst p0.b, p15, p0.b +// CHECK-ENCODING: [0xe0,0xc1,0x58,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c1 58 25 <unknown> + +pfirst p15.b, p15, p15.b +// CHECK-INST: pfirst p15.b, p15, p15.b +// CHECK-ENCODING: [0xef,0xc1,0x58,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef c1 58 25 <unknown> diff --git a/test/MC/AArch64/SVE/pnext-diagnostics.s b/test/MC/AArch64/SVE/pnext-diagnostics.s new file mode 100644 index 000000000000..e8ee5669dfea --- /dev/null +++ b/test/MC/AArch64/SVE/pnext-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Tied operands must match + +pnext p0.b, p15, p1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: pnext p0.b, p15, p1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pnext.s b/test/MC/AArch64/SVE/pnext.s new file mode 100644 index 000000000000..3d788deb05c4 --- /dev/null +++ b/test/MC/AArch64/SVE/pnext.s @@ -0,0 +1,38 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pnext p15.b, p15, p15.b +// CHECK-INST: pnext p15.b, p15, p15.b +// CHECK-ENCODING: [0xef,0xc5,0x19,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef c5 19 25 <unknown> + +pnext p0.b, p15, p0.b +// CHECK-INST: pnext p0.b, p15, p0.b +// CHECK-ENCODING: [0xe0,0xc5,0x19,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c5 19 25 <unknown> + +pnext p0.h, p15, p0.h +// CHECK-INST: pnext p0.h, p15, p0.h +// CHECK-ENCODING: [0xe0,0xc5,0x59,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c5 59 25 <unknown> + +pnext p0.s, p15, p0.s +// CHECK-INST: pnext p0.s, p15, p0.s +// CHECK-ENCODING: [0xe0,0xc5,0x99,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c5 99 25 <unknown> + +pnext p0.d, p15, p0.d +// CHECK-INST: pnext p0.d, p15, p0.d +// CHECK-ENCODING: [0xe0,0xc5,0xd9,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c5 d9 25 <unknown> diff --git a/test/MC/AArch64/SVE/prfb-diagnostics.s b/test/MC/AArch64/SVE/prfb-diagnostics.s index 2ffdc6ff6a00..24466ed79480 100644 --- a/test/MC/AArch64/SVE/prfb-diagnostics.s +++ b/test/MC/AArch64/SVE/prfb-diagnostics.s @@ -128,3 +128,19 @@ prfb #0, p8, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: prfb #0, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +prfb pldl1keep, p0, [x0, z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfb pldl1keep, p0, [x0, z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +prfb pldl1keep, p0, [x0, z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfb pldl1keep, p0, [x0, z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/prfd-diagnostics.s b/test/MC/AArch64/SVE/prfd-diagnostics.s index bca2f5b71218..2fb6a296576f 100644 --- a/test/MC/AArch64/SVE/prfd-diagnostics.s +++ b/test/MC/AArch64/SVE/prfd-diagnostics.s @@ -114,3 +114,19 @@ prfd #0, p8, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: prfd #0, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/prfh-diagnostics.s b/test/MC/AArch64/SVE/prfh-diagnostics.s index 0265c9f86a31..a9f8ad84c65c 100644 --- a/test/MC/AArch64/SVE/prfh-diagnostics.s +++ b/test/MC/AArch64/SVE/prfh-diagnostics.s @@ -153,3 +153,19 @@ prfh #0, p8, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: prfh #0, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/prfw-diagnostics.s b/test/MC/AArch64/SVE/prfw-diagnostics.s index 06bc54d2ed0f..510c383f535f 100644 --- a/test/MC/AArch64/SVE/prfw-diagnostics.s +++ b/test/MC/AArch64/SVE/prfw-diagnostics.s @@ -154,3 +154,31 @@ prfw #0, p8, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: prfw #0, p8, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z8.d, p3/z, z15.d +prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z8, z15 +prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21.d, p5/z, z28.d +prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ptest-diagnostics.s b/test/MC/AArch64/SVE/ptest-diagnostics.s new file mode 100644 index 000000000000..f03bf4c60f88 --- /dev/null +++ b/test/MC/AArch64/SVE/ptest-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +ptest p15, p15.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: ptest p15, p15.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ptest.s b/test/MC/AArch64/SVE/ptest.s new file mode 100644 index 000000000000..29622c08c92f --- /dev/null +++ b/test/MC/AArch64/SVE/ptest.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ptest p15, p0.b +// CHECK-INST: ptest p15, p0.b +// CHECK-ENCODING: [0x00,0xfc,0x50,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 fc 50 25 <unknown> + +ptest p15, p15.b +// CHECK-INST: ptest p15, p15.b +// CHECK-ENCODING: [0xe0,0xfd,0x50,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 fd 50 25 <unknown> diff --git a/test/MC/AArch64/SVE/rbit.s b/test/MC/AArch64/SVE/rbit.s index 9d017d9ce45b..2acba0ebc4e6 100644 --- a/test/MC/AArch64/SVE/rbit.s +++ b/test/MC/AArch64/SVE/rbit.s @@ -30,3 +30,31 @@ rbit z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e7 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +rbit z0.d, p7/m, z31.d +// CHECK-INST: rbit z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e7 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +rbit z0.d, p7/m, z31.d +// CHECK-INST: rbit z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e7 05 <unknown> diff --git a/test/MC/AArch64/SVE/rev-diagnostics.s b/test/MC/AArch64/SVE/rev-diagnostics.s new file mode 100644 index 000000000000..bad4b1655eee --- /dev/null +++ b/test/MC/AArch64/SVE/rev-diagnostics.s @@ -0,0 +1,17 @@ +// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +rev z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rev z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +rev z0.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rev z0.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/revb.s b/test/MC/AArch64/SVE/revb.s index b80f9a5d0492..1393160b80d0 100644 --- a/test/MC/AArch64/SVE/revb.s +++ b/test/MC/AArch64/SVE/revb.s @@ -24,3 +24,31 @@ revb z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e4 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +revb z0.d, p7/m, z31.d +// CHECK-INST: revb z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e4 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +revb z0.d, p7/m, z31.d +// CHECK-INST: revb z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e4 05 <unknown> diff --git a/test/MC/AArch64/SVE/revh.s b/test/MC/AArch64/SVE/revh.s index 8332461a1e69..d37b1bdec530 100644 --- a/test/MC/AArch64/SVE/revh.s +++ b/test/MC/AArch64/SVE/revh.s @@ -18,3 +18,31 @@ revh z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e5 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +revh z0.d, p7/m, z31.d +// CHECK-INST: revh z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e5 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +revh z0.d, p7/m, z31.d +// CHECK-INST: revh z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e5 05 <unknown> diff --git a/test/MC/AArch64/SVE/revw.s b/test/MC/AArch64/SVE/revw.s index 095e2aacd875..c2e419fe2542 100644 --- a/test/MC/AArch64/SVE/revw.s +++ b/test/MC/AArch64/SVE/revw.s @@ -12,3 +12,31 @@ revw z0.d, p7/m, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f e6 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +revw z0.d, p7/m, z31.d +// CHECK-INST: revw z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e6 05 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +revw z0.d, p7/m, z31.d +// CHECK-INST: revw z0.d, p7/m, z31.d +// CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 9f e6 05 <unknown> diff --git a/test/MC/AArch64/SVE/sabd.s b/test/MC/AArch64/SVE/sabd.s index 0636d3f76284..4186ff048299 100644 --- a/test/MC/AArch64/SVE/sabd.s +++ b/test/MC/AArch64/SVE/sabd.s @@ -30,3 +30,31 @@ sabd z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcc,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f cc 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +sabd z4.d, p7/m, z4.d, z31.d +// CHECK-INST: sabd z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cc 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +sabd z4.d, p7/m, z4.d, z31.d +// CHECK-INST: sabd z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cc 04 <unknown> diff --git a/test/MC/AArch64/SVE/saddv-diagnostics.s b/test/MC/AArch64/SVE/saddv-diagnostics.s index e387e07735ad..d99433222e3e 100644 --- a/test/MC/AArch64/SVE/saddv-diagnostics.s +++ b/test/MC/AArch64/SVE/saddv-diagnostics.s @@ -31,4 +31,19 @@ saddv d0, p7, z31.d saddv d0, p8, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: saddv d0, p8, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.s, p7/z, z6.s +saddv d0, p7, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddv d0, p7, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +saddv d0, p7, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddv d0, p7, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/scvtf.s b/test/MC/AArch64/SVE/scvtf.s index 31dec7e144a4..8089e4a0c21f 100644 --- a/test/MC/AArch64/SVE/scvtf.s +++ b/test/MC/AArch64/SVE/scvtf.s @@ -48,3 +48,31 @@ scvtf z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd6,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 d6 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +scvtf z5.d, p0/m, z0.d +// CHECK-INST: scvtf z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xd6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 d6 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +scvtf z5.d, p0/m, z0.d +// CHECK-INST: scvtf z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xd6,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 d6 65 <unknown> diff --git a/test/MC/AArch64/SVE/sdiv.s b/test/MC/AArch64/SVE/sdiv.s index 565e9f63cfa8..5b617eb763e5 100644 --- a/test/MC/AArch64/SVE/sdiv.s +++ b/test/MC/AArch64/SVE/sdiv.s @@ -18,3 +18,31 @@ sdiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d4 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +sdiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d4 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sdiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: sdiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d4 04 <unknown> diff --git a/test/MC/AArch64/SVE/sdivr.s b/test/MC/AArch64/SVE/sdivr.s index 02c8a3052c05..b85cecedf30d 100644 --- a/test/MC/AArch64/SVE/sdivr.s +++ b/test/MC/AArch64/SVE/sdivr.s @@ -18,3 +18,31 @@ sdivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d6 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +sdivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d6 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sdivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: sdivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d6 04 <unknown> diff --git a/test/MC/AArch64/SVE/sdot-diagnostics.s b/test/MC/AArch64/SVE/sdot-diagnostics.s index cc22f21aa24d..622e27422991 100644 --- a/test/MC/AArch64/SVE/sdot-diagnostics.s +++ b/test/MC/AArch64/SVE/sdot-diagnostics.s @@ -56,3 +56,19 @@ sdot z0.d, z1.h, z15.h[2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK-NEXT: sdot z0.d, z1.h, z15.h[2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sdot z0.d, z1.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sdot z0.d, z1.h, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sdot z0.d, z1.h, z15.h[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sdot z0.d, z1.h, z15.h[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sdot.s b/test/MC/AArch64/SVE/sdot.s index dbc6b3eabc05..a7d7e7ecb6da 100644 --- a/test/MC/AArch64/SVE/sdot.s +++ b/test/MC/AArch64/SVE/sdot.s @@ -30,3 +30,31 @@ sdot z0.d, z1.h, z15.h[1] // CHECK-ENCODING: [0x20,0x00,0xff,0x44] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 00 ff 44 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sdot z0.d, z1.h, z31.h +// CHECK-INST: sdot z0.d, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x00,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 df 44 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sdot z0.d, z1.h, z15.h[1] +// CHECK-INST: sdot z0.d, z1.h, z15.h[1] +// CHECK-ENCODING: [0x20,0x00,0xff,0x44] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 ff 44 <unknown> diff --git a/test/MC/AArch64/SVE/sel-diagnostics.s b/test/MC/AArch64/SVE/sel-diagnostics.s new file mode 100644 index 000000000000..760f2327f85a --- /dev/null +++ b/test/MC/AArch64/SVE/sel-diagnostics.s @@ -0,0 +1,17 @@ +// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z28.b, p7/z, z30.b +sel z28.b, p7, z13.b, z8.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sel z28.b, p7, z13.b, z8.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z23, z30 +sel z23.b, p11, z13.b, z8.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sel z23.b, p11, z13.b, z8.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smax-diagnostics.s b/test/MC/AArch64/SVE/smax-diagnostics.s index ac1c286f26ef..77825e013c35 100644 --- a/test/MC/AArch64/SVE/smax-diagnostics.s +++ b/test/MC/AArch64/SVE/smax-diagnostics.s @@ -14,3 +14,13 @@ smax z0.b, p8/m, z0.b, z0.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: smax z0.b, p8/m, z0.b, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +smax z31.d, z31.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smax z31.d, z31.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smax.s b/test/MC/AArch64/SVE/smax.s index de0e9e2f5247..1fbcc84110e6 100644 --- a/test/MC/AArch64/SVE/smax.s +++ b/test/MC/AArch64/SVE/smax.s @@ -78,3 +78,43 @@ smax z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xc8,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f c8 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +smax z4.d, p7/m, z4.d, z31.d +// CHECK-INST: smax z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f c8 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +smax z4.d, p7/m, z4.d, z31.d +// CHECK-INST: smax z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f c8 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +smax z31.d, z31.d, #127 +// CHECK-INST: smax z31.d, z31.d, #127 +// CHECK-ENCODING: [0xff,0xcf,0xe8,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff cf e8 25 <unknown> diff --git a/test/MC/AArch64/SVE/smaxv-diagnostics.s b/test/MC/AArch64/SVE/smaxv-diagnostics.s index 62936022f44d..7486eb67d13c 100644 --- a/test/MC/AArch64/SVE/smaxv-diagnostics.s +++ b/test/MC/AArch64/SVE/smaxv-diagnostics.s @@ -31,4 +31,19 @@ smaxv v0.2d, p7, z31.d smaxv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: smaxv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +smaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +smaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smin-diagnostics.s b/test/MC/AArch64/SVE/smin-diagnostics.s index efe7855c8315..987650901ea9 100644 --- a/test/MC/AArch64/SVE/smin-diagnostics.s +++ b/test/MC/AArch64/SVE/smin-diagnostics.s @@ -14,3 +14,13 @@ smin z0.b, p8/m, z0.b, z0.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: smin z0.b, p8/m, z0.b, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +smin z31.d, z31.d, #127 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smin z31.d, z31.d, #127 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smin.s b/test/MC/AArch64/SVE/smin.s index dd1676bf582e..da26ac04462f 100644 --- a/test/MC/AArch64/SVE/smin.s +++ b/test/MC/AArch64/SVE/smin.s @@ -78,3 +78,43 @@ smin z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xca,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f ca 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +smin z4.d, p7/m, z4.d, z31.d +// CHECK-INST: smin z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xca,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f ca 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +smin z4.d, p7/m, z4.d, z31.d +// CHECK-INST: smin z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xca,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f ca 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +smin z31.d, z31.d, #127 +// CHECK-INST: smin z31.d, z31.d, #127 +// CHECK-ENCODING: [0xff,0xcf,0xea,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff cf ea 25 <unknown> diff --git a/test/MC/AArch64/SVE/sminv-diagnostics.s b/test/MC/AArch64/SVE/sminv-diagnostics.s index 85f55772f89e..5f8a4e011e07 100644 --- a/test/MC/AArch64/SVE/sminv-diagnostics.s +++ b/test/MC/AArch64/SVE/sminv-diagnostics.s @@ -31,4 +31,19 @@ sminv v0.2d, p7, z31.d sminv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: sminv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +sminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/smulh.s b/test/MC/AArch64/SVE/smulh.s index 354dfd8c8417..7ef8d80dc786 100644 --- a/test/MC/AArch64/SVE/smulh.s +++ b/test/MC/AArch64/SVE/smulh.s @@ -30,3 +30,31 @@ smulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +smulh z0.d, p7/m, z0.d, z31.d +// CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d2 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +smulh z0.d, p7/m, z0.d, z31.d +// CHECK-INST: smulh z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d2 04 <unknown> diff --git a/test/MC/AArch64/SVE/splice-diagnostics.s b/test/MC/AArch64/SVE/splice-diagnostics.s index dbac7403c4cb..3cd659caad93 100644 --- a/test/MC/AArch64/SVE/splice-diagnostics.s +++ b/test/MC/AArch64/SVE/splice-diagnostics.s @@ -25,3 +25,13 @@ splice z0.b, p8, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: splice z0.b, p8, z0.b, z1.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z4.d, p7/z, z6.d +splice z4.d, p7, z4.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: splice z4.d, p7, z4.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/splice.s b/test/MC/AArch64/SVE/splice.s index a213b76d5091..719a761f3022 100644 --- a/test/MC/AArch64/SVE/splice.s +++ b/test/MC/AArch64/SVE/splice.s @@ -30,3 +30,19 @@ splice z31.d, p7, z31.d, z31.d // CHECK-ENCODING: [0xff,0x9f,0xec,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 9f ec 05 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +splice z4.d, p7, z4.d, z31.d +// CHECK-INST: splice z4.d, p7, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x9f,0xec,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 9f ec 05 <unknown> diff --git a/test/MC/AArch64/SVE/sqadd-diagnostics.s b/test/MC/AArch64/SVE/sqadd-diagnostics.s index 92672b648a6f..ae07bb69f9be 100644 --- a/test/MC/AArch64/SVE/sqadd-diagnostics.s +++ b/test/MC/AArch64/SVE/sqadd-diagnostics.s @@ -86,3 +86,25 @@ sqadd z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: sqadd z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqadd z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqadd z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqadd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqadd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +sqadd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqadd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqadd.s b/test/MC/AArch64/SVE/sqadd.s index 49abd41a6ade..8f722ea1da48 100644 --- a/test/MC/AArch64/SVE/sqadd.s +++ b/test/MC/AArch64/SVE/sqadd.s @@ -115,3 +115,19 @@ sqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe4,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e4 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +sqadd z31.d, z31.d, #65280 +// CHECK-INST: sqadd z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe4,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e4 25 <unknown> diff --git a/test/MC/AArch64/SVE/sqdecd-diagnostics.s b/test/MC/AArch64/SVE/sqdecd-diagnostics.s index de2270c07005..658af848c363 100644 --- a/test/MC/AArch64/SVE/sqdecd-diagnostics.s +++ b/test/MC/AArch64/SVE/sqdecd-diagnostics.s @@ -79,3 +79,25 @@ sqdecd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdecd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqdecd z0.d, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecd z0.d, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqdecd z0.d, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecd z0.d, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqdecd.s b/test/MC/AArch64/SVE/sqdecd.s index c240cc9eab88..107d630cb3e4 100644 --- a/test/MC/AArch64/SVE/sqdecd.s +++ b/test/MC/AArch64/SVE/sqdecd.s @@ -294,3 +294,43 @@ sqdecd x0, #28 // CHECK-ENCODING: [0x80,0xfb,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 fb f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecd z0.d +// CHECK-INST: sqdecd z0.d +// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cb e0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecd z0.d, pow2, mul #16 +// CHECK-INST: sqdecd z0.d, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc8,0xef,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 ef 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecd z0.d, pow2 +// CHECK-INST: sqdecd z0.d, pow2 +// CHECK-ENCODING: [0x00,0xc8,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 e0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqdech-diagnostics.s b/test/MC/AArch64/SVE/sqdech-diagnostics.s index dd68b9d08f09..af9268cb6ee2 100644 --- a/test/MC/AArch64/SVE/sqdech-diagnostics.s +++ b/test/MC/AArch64/SVE/sqdech-diagnostics.s @@ -79,3 +79,25 @@ sqdech x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdech x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +sqdech z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdech z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +sqdech z0.h, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdech z0.h, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +sqdech z0.h, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdech z0.h, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqdech.s b/test/MC/AArch64/SVE/sqdech.s index b0e8c8d39386..574316825b18 100644 --- a/test/MC/AArch64/SVE/sqdech.s +++ b/test/MC/AArch64/SVE/sqdech.s @@ -294,3 +294,43 @@ sqdech x0, #28 // CHECK-ENCODING: [0x80,0xfb,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 fb 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdech z0.h +// CHECK-INST: sqdech z0.h +// CHECK-ENCODING: [0xe0,0xcb,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cb 60 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdech z0.h, pow2, mul #16 +// CHECK-INST: sqdech z0.h, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc8,0x6f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 6f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdech z0.h, pow2 +// CHECK-INST: sqdech z0.h, pow2 +// CHECK-ENCODING: [0x00,0xc8,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 60 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqdecp-diagnostics.s b/test/MC/AArch64/SVE/sqdecp-diagnostics.s index f3fca0f17c9f..80579b824210 100644 --- a/test/MC/AArch64/SVE/sqdecp-diagnostics.s +++ b/test/MC/AArch64/SVE/sqdecp-diagnostics.s @@ -51,3 +51,13 @@ sqdecp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: sqdecp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdecp z0.d, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecp z0.d, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqdecp.s b/test/MC/AArch64/SVE/sqdecp.s index 6b6abac8621f..2a56b182f6bb 100644 --- a/test/MC/AArch64/SVE/sqdecp.s +++ b/test/MC/AArch64/SVE/sqdecp.s @@ -72,3 +72,19 @@ sqdecp z0.d, p0 // CHECK-ENCODING: [0x00,0x80,0xea,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 ea 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecp z0.d, p0 +// CHECK-INST: sqdecp z0.d, p0 +// CHECK-ENCODING: [0x00,0x80,0xea,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 ea 25 <unknown> diff --git a/test/MC/AArch64/SVE/sqdecw-diagnostics.s b/test/MC/AArch64/SVE/sqdecw-diagnostics.s index f3b11c2732c4..97adc35cf16a 100644 --- a/test/MC/AArch64/SVE/sqdecw-diagnostics.s +++ b/test/MC/AArch64/SVE/sqdecw-diagnostics.s @@ -79,3 +79,25 @@ sqdecw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqdecw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +sqdecw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqdecw z0.s, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecw z0.s, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqdecw z0.s, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdecw z0.s, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqdecw.s b/test/MC/AArch64/SVE/sqdecw.s index ac456f3f8cc0..e48d5999d409 100644 --- a/test/MC/AArch64/SVE/sqdecw.s +++ b/test/MC/AArch64/SVE/sqdecw.s @@ -294,3 +294,43 @@ sqdecw x0, #28 // CHECK-ENCODING: [0x80,0xfb,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 fb b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecw z0.s +// CHECK-INST: sqdecw z0.s +// CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cb a0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecw z0.s, pow2, mul #16 +// CHECK-INST: sqdecw z0.s, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc8,0xaf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 af 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqdecw z0.s, pow2 +// CHECK-INST: sqdecw z0.s, pow2 +// CHECK-ENCODING: [0x00,0xc8,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c8 a0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqincd-diagnostics.s b/test/MC/AArch64/SVE/sqincd-diagnostics.s index d2bad3bc6b0c..2e462e6f6dc1 100644 --- a/test/MC/AArch64/SVE/sqincd-diagnostics.s +++ b/test/MC/AArch64/SVE/sqincd-diagnostics.s @@ -79,3 +79,25 @@ sqincd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqincd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqincd z0.d, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincd z0.d, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqincd z0.d, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincd z0.d, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqincd.s b/test/MC/AArch64/SVE/sqincd.s index f6919ffdc9dd..440e4b708ffc 100644 --- a/test/MC/AArch64/SVE/sqincd.s +++ b/test/MC/AArch64/SVE/sqincd.s @@ -294,3 +294,43 @@ sqincd x0, #28 // CHECK-ENCODING: [0x80,0xf3,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f3 f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincd z0.d +// CHECK-INST: sqincd z0.d +// CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 e0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincd z0.d, pow2, mul #16 +// CHECK-INST: sqincd z0.d, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc0,0xef,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 ef 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincd z0.d, pow2 +// CHECK-INST: sqincd z0.d, pow2 +// CHECK-ENCODING: [0x00,0xc0,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 e0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqinch-diagnostics.s b/test/MC/AArch64/SVE/sqinch-diagnostics.s index 3394a814a95a..1f9cb8f8b6b2 100644 --- a/test/MC/AArch64/SVE/sqinch-diagnostics.s +++ b/test/MC/AArch64/SVE/sqinch-diagnostics.s @@ -79,3 +79,25 @@ sqinch x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqinch x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +sqinch z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqinch z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +sqinch z0.h, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqinch z0.h, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +sqinch z0.h, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqinch z0.h, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqinch.s b/test/MC/AArch64/SVE/sqinch.s index 41bdcb9f15be..6ed6dc4758e0 100644 --- a/test/MC/AArch64/SVE/sqinch.s +++ b/test/MC/AArch64/SVE/sqinch.s @@ -294,3 +294,43 @@ sqinch x0, #28 // CHECK-ENCODING: [0x80,0xf3,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f3 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqinch z0.h +// CHECK-INST: sqinch z0.h +// CHECK-ENCODING: [0xe0,0xc3,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 60 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqinch z0.h, pow2, mul #16 +// CHECK-INST: sqinch z0.h, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc0,0x6f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 6f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqinch z0.h, pow2 +// CHECK-INST: sqinch z0.h, pow2 +// CHECK-ENCODING: [0x00,0xc0,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 60 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqincp-diagnostics.s b/test/MC/AArch64/SVE/sqincp-diagnostics.s index 8b98e62e220d..9bd8587edb04 100644 --- a/test/MC/AArch64/SVE/sqincp-diagnostics.s +++ b/test/MC/AArch64/SVE/sqincp-diagnostics.s @@ -46,3 +46,13 @@ uqdecp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: uqdecp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqincp z0.d, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincp z0.d, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqincp.s b/test/MC/AArch64/SVE/sqincp.s index 6f812947df29..f7d427b0ca6e 100644 --- a/test/MC/AArch64/SVE/sqincp.s +++ b/test/MC/AArch64/SVE/sqincp.s @@ -72,3 +72,19 @@ sqincp z0.d, p0 // CHECK-ENCODING: [0x00,0x80,0xe8,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 e8 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincp z0.d, p0 +// CHECK-INST: sqincp z0.d, p0 +// CHECK-ENCODING: [0x00,0x80,0xe8,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 e8 25 <unknown> diff --git a/test/MC/AArch64/SVE/sqincw-diagnostics.s b/test/MC/AArch64/SVE/sqincw-diagnostics.s index 53b726fdacde..b0a380e16016 100644 --- a/test/MC/AArch64/SVE/sqincw-diagnostics.s +++ b/test/MC/AArch64/SVE/sqincw-diagnostics.s @@ -79,3 +79,25 @@ sqincw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: sqincw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +sqincw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqincw z0.s, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincw z0.s, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqincw z0.s, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqincw z0.s, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqincw.s b/test/MC/AArch64/SVE/sqincw.s index 1528c30a3788..7ff2bc6540a7 100644 --- a/test/MC/AArch64/SVE/sqincw.s +++ b/test/MC/AArch64/SVE/sqincw.s @@ -294,3 +294,43 @@ sqincw x0, #28 // CHECK-ENCODING: [0x80,0xf3,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f3 b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincw z0.s +// CHECK-INST: sqincw z0.s +// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c3 a0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincw z0.s, pow2, mul #16 +// CHECK-INST: sqincw z0.s, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc0,0xaf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 af 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +sqincw z0.s, pow2 +// CHECK-INST: sqincw z0.s, pow2 +// CHECK-ENCODING: [0x00,0xc0,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 a0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sqsub-diagnostics.s b/test/MC/AArch64/SVE/sqsub-diagnostics.s index 8155c366c0ab..15633050ebfd 100644 --- a/test/MC/AArch64/SVE/sqsub-diagnostics.s +++ b/test/MC/AArch64/SVE/sqsub-diagnostics.s @@ -86,3 +86,25 @@ sqsub z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: sqsub z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqsub z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqsub z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqsub z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqsub z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +sqsub z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqsub z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sqsub.s b/test/MC/AArch64/SVE/sqsub.s index ad41b5ae41b6..c91d5fe3d124 100644 --- a/test/MC/AArch64/SVE/sqsub.s +++ b/test/MC/AArch64/SVE/sqsub.s @@ -115,3 +115,19 @@ sqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe6,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e6 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +sqsub z31.d, z31.d, #65280 +// CHECK-INST: sqsub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe6,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e6 25 <unknown> diff --git a/test/MC/AArch64/SVE/st1b-diagnostics.s b/test/MC/AArch64/SVE/st1b-diagnostics.s index 99bbc55b072c..25f153c78ce9 100644 --- a/test/MC/AArch64/SVE/st1b-diagnostics.s +++ b/test/MC/AArch64/SVE/st1b-diagnostics.s @@ -175,3 +175,19 @@ st1b z0.d, p0, [z0.d, #32] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. // CHECK-NEXT: st1b z0.d, p0, [z0.d, #32] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +st1b { z31.d }, p7, [z31.d, #31] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1b { z31.d }, p7, [z31.d, #31] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +st1b { z31.d }, p7, [z31.d, #31] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1b { z31.d }, p7, [z31.d, #31] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st1d-diagnostics.s b/test/MC/AArch64/SVE/st1d-diagnostics.s index f510633983f8..82f52ce56784 100644 --- a/test/MC/AArch64/SVE/st1d-diagnostics.s +++ b/test/MC/AArch64/SVE/st1d-diagnostics.s @@ -131,3 +131,19 @@ st1d z0.d, p0, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. // CHECK-NEXT: st1d z0.d, p0, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +st1d { z31.d }, p7, [z31.d, #248] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +st1d { z31.d }, p7, [z31.d, #248] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st1h-diagnostics.s b/test/MC/AArch64/SVE/st1h-diagnostics.s index b8b8ecdebd8b..e58cd52c7858 100644 --- a/test/MC/AArch64/SVE/st1h-diagnostics.s +++ b/test/MC/AArch64/SVE/st1h-diagnostics.s @@ -189,3 +189,19 @@ st1h z0.d, p0, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. // CHECK-NEXT: st1h z0.d, p0, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +st1h { z31.d }, p7, [z31.d, #62] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1h { z31.d }, p7, [z31.d, #62] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +st1h { z31.d }, p7, [z31.d, #62] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1h { z31.d }, p7, [z31.d, #62] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st1w-diagnostics.s b/test/MC/AArch64/SVE/st1w-diagnostics.s index 2222b0677566..a5c0f0517ecf 100644 --- a/test/MC/AArch64/SVE/st1w-diagnostics.s +++ b/test/MC/AArch64/SVE/st1w-diagnostics.s @@ -178,3 +178,19 @@ st1w z0.d, p0, [z0.d, #3] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. // CHECK-NEXT: st1w z0.d, p0, [z0.d, #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +st1w { z31.d }, p7, [z31.d, #124] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1w { z31.d }, p7, [z31.d, #124] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +st1w { z31.d }, p7, [z31.d, #124] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st1w { z31.d }, p7, [z31.d, #124] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st2b-diagnostics.s b/test/MC/AArch64/SVE/st2b-diagnostics.s index 07fdd64fe15b..ac30bb47192e 100644 --- a/test/MC/AArch64/SVE/st2b-diagnostics.s +++ b/test/MC/AArch64/SVE/st2b-diagnostics.s @@ -89,3 +89,19 @@ st2b { v0.2d, v1.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st2b { v0.2d, v1.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2b { z21.b, z22.b }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st2d-diagnostics.s b/test/MC/AArch64/SVE/st2d-diagnostics.s index e5e09424484f..301849f2ee04 100644 --- a/test/MC/AArch64/SVE/st2d-diagnostics.s +++ b/test/MC/AArch64/SVE/st2d-diagnostics.s @@ -94,3 +94,19 @@ st2d { v0.2d, v1.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st2d { v0.2d, v1.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2d { z21.d, z22.d }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st2h-diagnostics.s b/test/MC/AArch64/SVE/st2h-diagnostics.s index 0854ada487e7..b22ae30c09ce 100644 --- a/test/MC/AArch64/SVE/st2h-diagnostics.s +++ b/test/MC/AArch64/SVE/st2h-diagnostics.s @@ -94,3 +94,19 @@ st2h { v0.2d, v1.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st2h { v0.2d, v1.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st2w-diagnostics.s b/test/MC/AArch64/SVE/st2w-diagnostics.s index 61ca5ec964fc..1e40d0a054cb 100644 --- a/test/MC/AArch64/SVE/st2w-diagnostics.s +++ b/test/MC/AArch64/SVE/st2w-diagnostics.s @@ -94,3 +94,19 @@ st2w { v0.2d, v1.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st2w { v0.2d, v1.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st2w { z21.s, z22.s }, p5, [x10, #10, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st3b-diagnostics.s b/test/MC/AArch64/SVE/st3b-diagnostics.s index 65201355482d..43016c0c314a 100644 --- a/test/MC/AArch64/SVE/st3b-diagnostics.s +++ b/test/MC/AArch64/SVE/st3b-diagnostics.s @@ -89,3 +89,19 @@ st3b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st3b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st3d-diagnostics.s b/test/MC/AArch64/SVE/st3d-diagnostics.s index c9e8591e446c..ad089b2ceffd 100644 --- a/test/MC/AArch64/SVE/st3d-diagnostics.s +++ b/test/MC/AArch64/SVE/st3d-diagnostics.s @@ -94,3 +94,19 @@ st3d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st3d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st3h-diagnostics.s b/test/MC/AArch64/SVE/st3h-diagnostics.s index f6874294cfcf..aba5215defeb 100644 --- a/test/MC/AArch64/SVE/st3h-diagnostics.s +++ b/test/MC/AArch64/SVE/st3h-diagnostics.s @@ -94,3 +94,19 @@ st3h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st3h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st3w-diagnostics.s b/test/MC/AArch64/SVE/st3w-diagnostics.s index 9c2bb001049f..2e89901b6e1e 100644 --- a/test/MC/AArch64/SVE/st3w-diagnostics.s +++ b/test/MC/AArch64/SVE/st3w-diagnostics.s @@ -94,3 +94,19 @@ st3w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st3w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st4b-diagnostics.s b/test/MC/AArch64/SVE/st4b-diagnostics.s index c316c81f03cc..dcd31b78a286 100644 --- a/test/MC/AArch64/SVE/st4b-diagnostics.s +++ b/test/MC/AArch64/SVE/st4b-diagnostics.s @@ -89,3 +89,19 @@ st4b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st4b { v0.16b, v1.16b, v2.16b }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.b, p5/z, z28.b +st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st4d-diagnostics.s b/test/MC/AArch64/SVE/st4d-diagnostics.s index 87f4225a87c4..e63c0c553b54 100644 --- a/test/MC/AArch64/SVE/st4d-diagnostics.s +++ b/test/MC/AArch64/SVE/st4d-diagnostics.s @@ -95,3 +95,19 @@ st4d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st4d { v0.2d, v1.2d, v2.2d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.d, p5/z, z28.d +st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st4h-diagnostics.s b/test/MC/AArch64/SVE/st4h-diagnostics.s index e3cecfef0212..8d80eb2248c8 100644 --- a/test/MC/AArch64/SVE/st4h-diagnostics.s +++ b/test/MC/AArch64/SVE/st4h-diagnostics.s @@ -94,3 +94,19 @@ st4h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st4h { v0.8h, v1.8h, v2.8h }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.h, p5/z, z28.h +st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/st4w-diagnostics.s b/test/MC/AArch64/SVE/st4w-diagnostics.s index 46bb2d7d7856..8c3816538b79 100644 --- a/test/MC/AArch64/SVE/st4w-diagnostics.s +++ b/test/MC/AArch64/SVE/st4w-diagnostics.s @@ -94,3 +94,19 @@ st4w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: st4w { v0.4s, v1.4s, v2.4s }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z21.s, p5/z, z28.s +st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z21, z28 +st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/stnt1b-diagnostics.s b/test/MC/AArch64/SVE/stnt1b-diagnostics.s index 8f5a0b222dab..4b7806e5b0e8 100644 --- a/test/MC/AArch64/SVE/stnt1b-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1b-diagnostics.s @@ -64,3 +64,19 @@ stnt1b { v0.2d }, p0, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: stnt1b { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +stnt1b { z0.b }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1b { z0.b }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1b { z0.b }, p0, [x0, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1b { z0.b }, p0, [x0, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/stnt1d-diagnostics.s b/test/MC/AArch64/SVE/stnt1d-diagnostics.s index 9761ad98cc27..a5cbfe1a9343 100644 --- a/test/MC/AArch64/SVE/stnt1d-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1d-diagnostics.s @@ -64,3 +64,19 @@ stnt1d { v0.2d }, p0, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: stnt1d { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1d { z0.d }, p0, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1d { z0.d }, p0, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1d { z0.d }, p0, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1d { z0.d }, p0, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/stnt1h-diagnostics.s b/test/MC/AArch64/SVE/stnt1h-diagnostics.s index cf009b74e493..22fe5cb7dee3 100644 --- a/test/MC/AArch64/SVE/stnt1h-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1h-diagnostics.s @@ -64,3 +64,19 @@ stnt1h { v0.2d }, p0, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: stnt1h { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +stnt1h { z0.h }, p0, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1h { z0.h }, p0, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1h { z0.h }, p0, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1h { z0.h }, p0, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/stnt1w-diagnostics.s b/test/MC/AArch64/SVE/stnt1w-diagnostics.s index eb38fcac1b4b..339ea25c4488 100644 --- a/test/MC/AArch64/SVE/stnt1w-diagnostics.s +++ b/test/MC/AArch64/SVE/stnt1w-diagnostics.s @@ -64,3 +64,19 @@ stnt1w { v0.2d }, p0, [x1, #1, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: stnt1w { v0.2d }, p0, [x1, #1, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +stnt1w { z0.s }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1w { z0.s }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1w { z0.s }, p0, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1w { z0.s }, p0, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sub-diagnostics.s b/test/MC/AArch64/SVE/sub-diagnostics.s index 4ace1ce7dabb..2bd933735bbd 100644 --- a/test/MC/AArch64/SVE/sub-diagnostics.s +++ b/test/MC/AArch64/SVE/sub-diagnostics.s @@ -144,3 +144,25 @@ sub z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: sub z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sub z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sub z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.s, p0/z, z6.s +sub z31.s, z31.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sub z31.s, z31.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sub z31.s, z31.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sub z31.s, z31.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sub.s b/test/MC/AArch64/SVE/sub.s index dcbef0bf3e5e..8e74cf8cf3f2 100644 --- a/test/MC/AArch64/SVE/sub.s +++ b/test/MC/AArch64/SVE/sub.s @@ -286,3 +286,43 @@ sub z31.d, z31.d, #65280 // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e1 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z23.b, p3/z, z30.b +// CHECK-INST: movprfx z23.b, p3/z, z30.b +// CHECK-ENCODING: [0xd7,0x2f,0x10,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: d7 2f 10 04 <unknown> + +sub z23.b, p3/m, z23.b, z13.b +// CHECK-INST: sub z23.b, p3/m, z23.b, z13.b +// CHECK-ENCODING: [0xb7,0x0d,0x01,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 0d 01 04 <unknown> + +movprfx z23, z30 +// CHECK-INST: movprfx z23, z30 +// CHECK-ENCODING: [0xd7,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: d7 bf 20 04 <unknown> + +sub z23.b, p3/m, z23.b, z13.b +// CHECK-INST: sub z23.b, p3/m, z23.b, z13.b +// CHECK-ENCODING: [0xb7,0x0d,0x01,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 0d 01 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +sub z31.d, z31.d, #65280 +// CHECK-INST: sub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe1,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e1 25 <unknown> diff --git a/test/MC/AArch64/SVE/subr-diagnostics.s b/test/MC/AArch64/SVE/subr-diagnostics.s index 847bef6dfa7d..cf259ce17ddf 100644 --- a/test/MC/AArch64/SVE/subr-diagnostics.s +++ b/test/MC/AArch64/SVE/subr-diagnostics.s @@ -138,3 +138,13 @@ subr z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: subr z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +subr z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: subr z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/subr.s b/test/MC/AArch64/SVE/subr.s index 595d275a732b..ec6fa65c9621 100644 --- a/test/MC/AArch64/SVE/subr.s +++ b/test/MC/AArch64/SVE/subr.s @@ -115,3 +115,43 @@ subr z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe3,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e3 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +subr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: subr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x00,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 00 c3 04 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +subr z5.d, p0/m, z5.d, z0.d +// CHECK-INST: subr z5.d, p0/m, z5.d, z0.d +// CHECK-ENCODING: [0x05,0x00,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 00 c3 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +subr z31.d, z31.d, #65280 +// CHECK-INST: subr z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe3,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e3 25 <unknown> diff --git a/test/MC/AArch64/SVE/sunpkhi-diagnostics.s b/test/MC/AArch64/SVE/sunpkhi-diagnostics.s index 768ef1236bf4..cbbaee25b9ca 100644 --- a/test/MC/AArch64/SVE/sunpkhi-diagnostics.s +++ b/test/MC/AArch64/SVE/sunpkhi-diagnostics.s @@ -18,3 +18,19 @@ sunpkhi z0.d, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: sunpkhi z0.d, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sunpkhi z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sunpkhi z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sunpkhi z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sunpkhi z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sunpklo-diagnostics.s b/test/MC/AArch64/SVE/sunpklo-diagnostics.s index 92de4278e23c..14a5a42e5121 100644 --- a/test/MC/AArch64/SVE/sunpklo-diagnostics.s +++ b/test/MC/AArch64/SVE/sunpklo-diagnostics.s @@ -18,3 +18,19 @@ sunpklo z0.d, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: sunpklo z0.d, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sunpklo z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sunpklo z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sunpklo z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sunpklo z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/sxtb.s b/test/MC/AArch64/SVE/sxtb.s index fe8a699e60e1..b9fa8b62c71c 100644 --- a/test/MC/AArch64/SVE/sxtb.s +++ b/test/MC/AArch64/SVE/sxtb.s @@ -42,3 +42,31 @@ sxtb z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +sxtb z4.d, p7/m, z31.d +// CHECK-INST: sxtb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d0 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +sxtb z4.d, p7/m, z31.d +// CHECK-INST: sxtb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d0 04 <unknown> diff --git a/test/MC/AArch64/SVE/sxth.s b/test/MC/AArch64/SVE/sxth.s index 138bfa43c6c9..e422de5dd6af 100644 --- a/test/MC/AArch64/SVE/sxth.s +++ b/test/MC/AArch64/SVE/sxth.s @@ -30,3 +30,31 @@ sxth z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd2,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d2 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +sxth z4.d, p7/m, z31.d +// CHECK-INST: sxth z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d2 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +sxth z4.d, p7/m, z31.d +// CHECK-INST: sxth z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d2 04 <unknown> diff --git a/test/MC/AArch64/SVE/sxtw.s b/test/MC/AArch64/SVE/sxtw.s index ef7b4e9bafba..96c66cb30472 100644 --- a/test/MC/AArch64/SVE/sxtw.s +++ b/test/MC/AArch64/SVE/sxtw.s @@ -18,3 +18,31 @@ sxtw z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd4,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d4 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +sxtw z4.d, p7/m, z31.d +// CHECK-INST: sxtw z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d4 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +sxtw z4.d, p7/m, z31.d +// CHECK-INST: sxtw z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d4 04 <unknown> diff --git a/test/MC/AArch64/SVE/tbl-diagnostics.s b/test/MC/AArch64/SVE/tbl-diagnostics.s index 8cb8575bbe81..7314fb49d1b2 100644 --- a/test/MC/AArch64/SVE/tbl-diagnostics.s +++ b/test/MC/AArch64/SVE/tbl-diagnostics.s @@ -9,3 +9,19 @@ tbl { z0.h }, z0.h, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected // CHECK-NEXT: tbl { z0.h }, z0.h, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +tbl z31.d, { z31.d }, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: tbl z31.d, { z31.d }, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +tbl z31.d, { z31.d }, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: tbl z31.d, { z31.d }, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/trn1-diagnostics.s b/test/MC/AArch64/SVE/trn1-diagnostics.s index 9e318c1eacd6..7bd0f19fa5c6 100644 --- a/test/MC/AArch64/SVE/trn1-diagnostics.s +++ b/test/MC/AArch64/SVE/trn1-diagnostics.s @@ -41,3 +41,19 @@ trn1 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: trn1 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +trn1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: trn1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +trn1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: trn1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/trn2-diagnostics.s b/test/MC/AArch64/SVE/trn2-diagnostics.s index 48b37bf3a181..4c1e29ed2dae 100644 --- a/test/MC/AArch64/SVE/trn2-diagnostics.s +++ b/test/MC/AArch64/SVE/trn2-diagnostics.s @@ -41,3 +41,19 @@ trn2 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: trn2 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +trn2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: trn2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +trn2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: trn2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uabd.s b/test/MC/AArch64/SVE/uabd.s index ae06eb8782f8..0f1a4b382518 100644 --- a/test/MC/AArch64/SVE/uabd.s +++ b/test/MC/AArch64/SVE/uabd.s @@ -30,3 +30,31 @@ uabd z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcd,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f cd 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +uabd z4.d, p7/m, z4.d, z31.d +// CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cd 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +uabd z4.d, p7/m, z4.d, z31.d +// CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cd 04 <unknown> diff --git a/test/MC/AArch64/SVE/uaddv-diagnostics.s b/test/MC/AArch64/SVE/uaddv-diagnostics.s index 11ec959913b5..55ffc6075822 100644 --- a/test/MC/AArch64/SVE/uaddv-diagnostics.s +++ b/test/MC/AArch64/SVE/uaddv-diagnostics.s @@ -26,4 +26,19 @@ uaddv s0, p7, z31.s uaddv d0, p8, z31.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: uaddv d0, p8, z31.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +uaddv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uaddv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ucvtf.s b/test/MC/AArch64/SVE/ucvtf.s index 6848448a6821..9e5f4f792b14 100644 --- a/test/MC/AArch64/SVE/ucvtf.s +++ b/test/MC/AArch64/SVE/ucvtf.s @@ -48,3 +48,31 @@ ucvtf z0.d, p0/m, z0.d // CHECK-ENCODING: [0x00,0xa0,0xd7,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 a0 d7 65 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 <unknown> + +ucvtf z5.d, p0/m, z0.d +// CHECK-INST: ucvtf z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xd7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 d7 65 <unknown> + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 <unknown> + +ucvtf z5.d, p0/m, z0.d +// CHECK-INST: ucvtf z5.d, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0xd7,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 05 a0 d7 65 <unknown> diff --git a/test/MC/AArch64/SVE/udiv.s b/test/MC/AArch64/SVE/udiv.s index 7ad8a73cb097..ca528ee6d074 100644 --- a/test/MC/AArch64/SVE/udiv.s +++ b/test/MC/AArch64/SVE/udiv.s @@ -18,3 +18,31 @@ udiv z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d5 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +udiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d5 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +udiv z0.d, p7/m, z0.d, z31.d +// CHECK-INST: udiv z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d5 04 <unknown> diff --git a/test/MC/AArch64/SVE/udivr.s b/test/MC/AArch64/SVE/udivr.s index f09b7f49b8c1..45bc391d0ef5 100644 --- a/test/MC/AArch64/SVE/udivr.s +++ b/test/MC/AArch64/SVE/udivr.s @@ -18,3 +18,31 @@ udivr z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d7 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +udivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d7 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +udivr z0.d, p7/m, z0.d, z31.d +// CHECK-INST: udivr z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d7 04 <unknown> diff --git a/test/MC/AArch64/SVE/udot-diagnostics.s b/test/MC/AArch64/SVE/udot-diagnostics.s index 08abd77592ec..ecdb036c2706 100644 --- a/test/MC/AArch64/SVE/udot-diagnostics.s +++ b/test/MC/AArch64/SVE/udot-diagnostics.s @@ -56,3 +56,19 @@ udot z0.d, z1.h, z15.h[2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. // CHECK-NEXT: udot z0.d, z1.h, z15.h[2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +udot z0.d, z1.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: udot z0.d, z1.h, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +udot z0.d, z1.h, z15.h[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: udot z0.d, z1.h, z15.h[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/udot.s b/test/MC/AArch64/SVE/udot.s index 0c3a392093c8..c9b441172de2 100644 --- a/test/MC/AArch64/SVE/udot.s +++ b/test/MC/AArch64/SVE/udot.s @@ -30,3 +30,31 @@ udot z0.d, z1.h, z15.h[1] // CHECK-ENCODING: [0x20,0x04,0xff,0x44] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 20 04 ff 44 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +udot z0.d, z1.h, z31.h +// CHECK-INST: udot z0.d, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x04,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 df 44 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +udot z0.d, z1.h, z15.h[1] +// CHECK-INST: udot z0.d, z1.h, z15.h[1] +// CHECK-ENCODING: [0x20,0x04,0xff,0x44] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 ff 44 <unknown> diff --git a/test/MC/AArch64/SVE/umax-diagnostics.s b/test/MC/AArch64/SVE/umax-diagnostics.s index f1e9e3916fba..628b8b2a7e5d 100644 --- a/test/MC/AArch64/SVE/umax-diagnostics.s +++ b/test/MC/AArch64/SVE/umax-diagnostics.s @@ -14,3 +14,13 @@ umax z0.b, p8/m, z0.b, z0.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: umax z0.b, p8/m, z0.b, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +umax z31.b, z31.b, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umax z31.b, z31.b, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/umax.s b/test/MC/AArch64/SVE/umax.s index ac774ec96b1f..bd89da13241b 100644 --- a/test/MC/AArch64/SVE/umax.s +++ b/test/MC/AArch64/SVE/umax.s @@ -78,3 +78,43 @@ umax z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xc9,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f c9 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +umax z4.d, p7/m, z4.d, z31.d +// CHECK-INST: umax z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f c9 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +umax z4.d, p7/m, z4.d, z31.d +// CHECK-INST: umax z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f c9 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +umax z31.b, z31.b, #255 +// CHECK-INST: umax z31.b, z31.b, #255 +// CHECK-ENCODING: [0xff,0xdf,0x29,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff df 29 25 <unknown> diff --git a/test/MC/AArch64/SVE/umaxv-diagnostics.s b/test/MC/AArch64/SVE/umaxv-diagnostics.s index cfcabb9a8b2c..36512f7568db 100644 --- a/test/MC/AArch64/SVE/umaxv-diagnostics.s +++ b/test/MC/AArch64/SVE/umaxv-diagnostics.s @@ -31,4 +31,19 @@ umaxv v0.2d, p7, z31.d umaxv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: umaxv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +umaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +umaxv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umaxv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/umin-diagnostics.s b/test/MC/AArch64/SVE/umin-diagnostics.s index 03c708b14620..ce60edf4557e 100644 --- a/test/MC/AArch64/SVE/umin-diagnostics.s +++ b/test/MC/AArch64/SVE/umin-diagnostics.s @@ -14,3 +14,13 @@ umin z0.b, p8/m, z0.b, z0.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: umin z0.b, p8/m, z0.b, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p0/z, z6.b +umin z31.b, z31.b, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umin z31.b, z31.b, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/umin.s b/test/MC/AArch64/SVE/umin.s index bd142c4e2c17..9aac3092df21 100644 --- a/test/MC/AArch64/SVE/umin.s +++ b/test/MC/AArch64/SVE/umin.s @@ -78,3 +78,43 @@ umin z31.d, p7/m, z31.d, z31.d // CHECK-ENCODING: [0xff,0x1f,0xcb,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 1f cb 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +umin z4.d, p7/m, z4.d, z31.d +// CHECK-INST: umin z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cb 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +umin z4.d, p7/m, z4.d, z31.d +// CHECK-INST: umin z4.d, p7/m, z4.d, z31.d +// CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 1f cb 04 <unknown> + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +umin z31.b, z31.b, #255 +// CHECK-INST: umin z31.b, z31.b, #255 +// CHECK-ENCODING: [0xff,0xdf,0x2b,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff df 2b 25 <unknown> diff --git a/test/MC/AArch64/SVE/uminv-diagnostics.s b/test/MC/AArch64/SVE/uminv-diagnostics.s index 9208dc9a11f4..f6898352a93a 100644 --- a/test/MC/AArch64/SVE/uminv-diagnostics.s +++ b/test/MC/AArch64/SVE/uminv-diagnostics.s @@ -31,4 +31,19 @@ uminv v0.2d, p7, z31.d uminv h0, p8, z31.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: uminv h0, p8, z31.h -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p7/z, z6.d +uminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uminv d0, p7, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uminv d0, p7, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/umulh.s b/test/MC/AArch64/SVE/umulh.s index 523428335edd..a5d6eb58603a 100644 --- a/test/MC/AArch64/SVE/umulh.s +++ b/test/MC/AArch64/SVE/umulh.s @@ -30,3 +30,31 @@ umulh z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 1f d3 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0.d, p7/z, z7.d +// CHECK-INST: movprfx z0.d, p7/z, z7.d +// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 3c d0 04 <unknown> + +umulh z0.d, p7/m, z0.d, z31.d +// CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d3 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +umulh z0.d, p7/m, z0.d, z31.d +// CHECK-INST: umulh z0.d, p7/m, z0.d, z31.d +// CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 1f d3 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqadd-diagnostics.s b/test/MC/AArch64/SVE/uqadd-diagnostics.s index 1a6179a14ca5..7dcdba98ccc4 100644 --- a/test/MC/AArch64/SVE/uqadd-diagnostics.s +++ b/test/MC/AArch64/SVE/uqadd-diagnostics.s @@ -86,3 +86,25 @@ uqadd z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: uqadd z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uqadd z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqadd z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqadd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqadd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +uqadd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqadd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqadd.s b/test/MC/AArch64/SVE/uqadd.s index fc152297c39c..23e213ac85f9 100644 --- a/test/MC/AArch64/SVE/uqadd.s +++ b/test/MC/AArch64/SVE/uqadd.s @@ -115,3 +115,19 @@ uqadd z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe5,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e5 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +uqadd z31.d, z31.d, #65280 +// CHECK-INST: uqadd z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe5,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e5 25 <unknown> diff --git a/test/MC/AArch64/SVE/uqdecd-diagnostics.s b/test/MC/AArch64/SVE/uqdecd-diagnostics.s index 8f3ce3e6e4fd..fcf40770cb36 100644 --- a/test/MC/AArch64/SVE/uqdecd-diagnostics.s +++ b/test/MC/AArch64/SVE/uqdecd-diagnostics.s @@ -79,3 +79,25 @@ uqdecd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uqdecd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqdecd z0.d, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecd z0.d, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqdecd z0.d, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecd z0.d, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqdecd.s b/test/MC/AArch64/SVE/uqdecd.s index 65183428ed5c..f47d0d412990 100644 --- a/test/MC/AArch64/SVE/uqdecd.s +++ b/test/MC/AArch64/SVE/uqdecd.s @@ -294,3 +294,43 @@ uqdecd x0, #28 // CHECK-ENCODING: [0x80,0xff,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 ff f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecd z0.d +// CHECK-INST: uqdecd z0.d +// CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cf e0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecd z0.d, pow2, mul #16 +// CHECK-INST: uqdecd z0.d, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xcc,0xef,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc ef 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecd z0.d, pow2 +// CHECK-INST: uqdecd z0.d, pow2 +// CHECK-ENCODING: [0x00,0xcc,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc e0 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqdech-diagnostics.s b/test/MC/AArch64/SVE/uqdech-diagnostics.s index 936c486599c4..a4e0a24c9d76 100644 --- a/test/MC/AArch64/SVE/uqdech-diagnostics.s +++ b/test/MC/AArch64/SVE/uqdech-diagnostics.s @@ -79,3 +79,25 @@ uqdech x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdech x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +uqdech z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdech z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +uqdech z0.h, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdech z0.h, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +uqdech z0.h, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdech z0.h, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqdech.s b/test/MC/AArch64/SVE/uqdech.s index 950409133e0d..9a1ff5256040 100644 --- a/test/MC/AArch64/SVE/uqdech.s +++ b/test/MC/AArch64/SVE/uqdech.s @@ -294,3 +294,43 @@ uqdech x0, #28 // CHECK-ENCODING: [0x80,0xff,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 ff 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdech z0.h +// CHECK-INST: uqdech z0.h +// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cf 60 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdech z0.h, pow2, mul #16 +// CHECK-INST: uqdech z0.h, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xcc,0x6f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc 6f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdech z0.h, pow2 +// CHECK-INST: uqdech z0.h, pow2 +// CHECK-ENCODING: [0x00,0xcc,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc 60 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqdecp-diagnostics.s b/test/MC/AArch64/SVE/uqdecp-diagnostics.s new file mode 100644 index 000000000000..8fd345b46ee5 --- /dev/null +++ b/test/MC/AArch64/SVE/uqdecp-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uqdecp z0.d, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecp z0.d, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqdecp.s b/test/MC/AArch64/SVE/uqdecp.s index 4f9a7af45d55..3c07a7da2462 100644 --- a/test/MC/AArch64/SVE/uqdecp.s +++ b/test/MC/AArch64/SVE/uqdecp.s @@ -72,3 +72,19 @@ uqdecp z0.d, p0 // CHECK-ENCODING: [0x00,0x80,0xeb,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 eb 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecp z0.d, p0 +// CHECK-INST: uqdecp z0.d, p0 +// CHECK-ENCODING: [0x00,0x80,0xeb,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 eb 25 <unknown> diff --git a/test/MC/AArch64/SVE/uqdecw-diagnostics.s b/test/MC/AArch64/SVE/uqdecw-diagnostics.s index b46373915c31..a7a955e64108 100644 --- a/test/MC/AArch64/SVE/uqdecw-diagnostics.s +++ b/test/MC/AArch64/SVE/uqdecw-diagnostics.s @@ -79,3 +79,25 @@ uqdecw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqdecw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +uqdecw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqdecw z0.s, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecw z0.s, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqdecw z0.s, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqdecw z0.s, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqdecw.s b/test/MC/AArch64/SVE/uqdecw.s index 44e96f31b98a..6ed544d5733f 100644 --- a/test/MC/AArch64/SVE/uqdecw.s +++ b/test/MC/AArch64/SVE/uqdecw.s @@ -294,3 +294,43 @@ uqdecw x0, #28 // CHECK-ENCODING: [0x80,0xff,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 ff b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecw z0.s +// CHECK-INST: uqdecw z0.s +// CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 cf a0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecw z0.s, pow2, mul #16 +// CHECK-INST: uqdecw z0.s, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xcc,0xaf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc af 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqdecw z0.s, pow2 +// CHECK-INST: uqdecw z0.s, pow2 +// CHECK-ENCODING: [0x00,0xcc,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 cc a0 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqincd-diagnostics.s b/test/MC/AArch64/SVE/uqincd-diagnostics.s index cb662cfa8f1f..1c6dfa11965f 100644 --- a/test/MC/AArch64/SVE/uqincd-diagnostics.s +++ b/test/MC/AArch64/SVE/uqincd-diagnostics.s @@ -79,3 +79,25 @@ uqincd x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincd x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uqincd z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincd z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqincd z0.d, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincd z0.d, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqincd z0.d, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincd z0.d, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqincd.s b/test/MC/AArch64/SVE/uqincd.s index 48890f965db9..d72672ced424 100644 --- a/test/MC/AArch64/SVE/uqincd.s +++ b/test/MC/AArch64/SVE/uqincd.s @@ -294,3 +294,43 @@ uqincd x0, #28 // CHECK-ENCODING: [0x80,0xf7,0xf0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f7 f0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincd z0.d +// CHECK-INST: uqincd z0.d +// CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 e0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincd z0.d, pow2, mul #16 +// CHECK-INST: uqincd z0.d, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc4,0xef,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 ef 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincd z0.d, pow2 +// CHECK-INST: uqincd z0.d, pow2 +// CHECK-ENCODING: [0x00,0xc4,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 e0 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqinch-diagnostics.s b/test/MC/AArch64/SVE/uqinch-diagnostics.s index 200d79630607..fc694c4e93de 100644 --- a/test/MC/AArch64/SVE/uqinch-diagnostics.s +++ b/test/MC/AArch64/SVE/uqinch-diagnostics.s @@ -79,3 +79,25 @@ uqinch x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqinch x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +uqinch z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqinch z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +uqinch z0.h, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqinch z0.h, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +uqinch z0.h, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqinch z0.h, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqinch.s b/test/MC/AArch64/SVE/uqinch.s index 7a471d41d49a..03c7fb7fe9a8 100644 --- a/test/MC/AArch64/SVE/uqinch.s +++ b/test/MC/AArch64/SVE/uqinch.s @@ -296,3 +296,43 @@ uqinch x0, #28 // CHECK-ENCODING: [0x80,0xf7,0x70,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f7 70 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqinch z0.h +// CHECK-INST: uqinch z0.h +// CHECK-ENCODING: [0xe0,0xc7,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 60 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqinch z0.h, pow2, mul #16 +// CHECK-INST: uqinch z0.h, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc4,0x6f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 6f 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqinch z0.h, pow2 +// CHECK-INST: uqinch z0.h, pow2 +// CHECK-ENCODING: [0x00,0xc4,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 60 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqincp-diagnostics.s b/test/MC/AArch64/SVE/uqincp-diagnostics.s index 8a4aa25ac413..d5cf76014df5 100644 --- a/test/MC/AArch64/SVE/uqincp-diagnostics.s +++ b/test/MC/AArch64/SVE/uqincp-diagnostics.s @@ -46,3 +46,13 @@ uqincp x0, p0.q // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: uqincp x0, p0.q // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uqincp z0.d, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincp z0.d, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqincp.s b/test/MC/AArch64/SVE/uqincp.s index e7c87efa4e06..a4fb8199d994 100644 --- a/test/MC/AArch64/SVE/uqincp.s +++ b/test/MC/AArch64/SVE/uqincp.s @@ -72,3 +72,19 @@ uqincp z0.d, p0 // CHECK-ENCODING: [0x00,0x80,0xe9,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 e9 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincp z0.d, p0 +// CHECK-INST: uqincp z0.d, p0 +// CHECK-ENCODING: [0x00,0x80,0xe9,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 e9 25 <unknown> diff --git a/test/MC/AArch64/SVE/uqincw-diagnostics.s b/test/MC/AArch64/SVE/uqincw-diagnostics.s index c5a632bc88cf..0ad3624230b7 100644 --- a/test/MC/AArch64/SVE/uqincw-diagnostics.s +++ b/test/MC/AArch64/SVE/uqincw-diagnostics.s @@ -79,3 +79,25 @@ uqincw x0, #32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern // CHECK-NEXT: uqincw x0, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +uqincw z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincw z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqincw z0.s, pow2, mul #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincw z0.s, pow2, mul #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqincw z0.s, pow2 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqincw z0.s, pow2 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqincw.s b/test/MC/AArch64/SVE/uqincw.s index 097b26f40afe..1944d69625e5 100644 --- a/test/MC/AArch64/SVE/uqincw.s +++ b/test/MC/AArch64/SVE/uqincw.s @@ -294,3 +294,43 @@ uqincw x0, #28 // CHECK-ENCODING: [0x80,0xf7,0xb0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 80 f7 b0 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincw z0.s +// CHECK-INST: uqincw z0.s +// CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 c7 a0 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincw z0.s, pow2, mul #16 +// CHECK-INST: uqincw z0.s, pow2, mul #16 +// CHECK-ENCODING: [0x00,0xc4,0xaf,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 af 04 <unknown> + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 <unknown> + +uqincw z0.s, pow2 +// CHECK-INST: uqincw z0.s, pow2 +// CHECK-ENCODING: [0x00,0xc4,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c4 a0 04 <unknown> diff --git a/test/MC/AArch64/SVE/uqsub-diagnostics.s b/test/MC/AArch64/SVE/uqsub-diagnostics.s index 566334ceea8d..5f8129aa773e 100644 --- a/test/MC/AArch64/SVE/uqsub-diagnostics.s +++ b/test/MC/AArch64/SVE/uqsub-diagnostics.s @@ -86,3 +86,25 @@ uqsub z0.d, z0.d, #65536 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280] // CHECK-NEXT: uqsub z0.d, z0.d, #65536 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uqsub z31.d, z31.d, #65280 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uqsub z31.d, z31.d, #65280 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +uqsub z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqsub z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +uqsub z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqsub z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uqsub.s b/test/MC/AArch64/SVE/uqsub.s index 4fb90cae9ee7..5bcc10f8b2ea 100644 --- a/test/MC/AArch64/SVE/uqsub.s +++ b/test/MC/AArch64/SVE/uqsub.s @@ -115,3 +115,19 @@ uqsub z31.d, z31.d, #65280 // CHECK-ENCODING: [0xff,0xff,0xe7,0x25] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff ff e7 25 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 <unknown> + +uqsub z31.d, z31.d, #65280 +// CHECK-INST: uqsub z31.d, z31.d, #65280 +// CHECK-ENCODING: [0xff,0xff,0xe7,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff ff e7 25 <unknown> diff --git a/test/MC/AArch64/SVE/uunpkhi-diagnostics.s b/test/MC/AArch64/SVE/uunpkhi-diagnostics.s index bdae37a32ae3..00adfb86fe42 100644 --- a/test/MC/AArch64/SVE/uunpkhi-diagnostics.s +++ b/test/MC/AArch64/SVE/uunpkhi-diagnostics.s @@ -18,3 +18,19 @@ uunpkhi z0.d, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: uunpkhi z0.d, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uunpkhi z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uunpkhi z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uunpkhi z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uunpkhi z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uunpklo-diagnostics.s b/test/MC/AArch64/SVE/uunpklo-diagnostics.s index 00f8a72fbc24..ae4a810fbea7 100644 --- a/test/MC/AArch64/SVE/uunpklo-diagnostics.s +++ b/test/MC/AArch64/SVE/uunpklo-diagnostics.s @@ -18,3 +18,19 @@ uunpklo z0.d, z0.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: uunpklo z0.d, z0.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uunpklo z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uunpklo z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uunpklo z31.d, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uunpklo z31.d, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uxtb.s b/test/MC/AArch64/SVE/uxtb.s index 5c1e01620e98..81d7dc01e02a 100644 --- a/test/MC/AArch64/SVE/uxtb.s +++ b/test/MC/AArch64/SVE/uxtb.s @@ -42,3 +42,31 @@ uxtb z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd1,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d1 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +uxtb z4.d, p7/m, z31.d +// CHECK-INST: uxtb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d1 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +uxtb z4.d, p7/m, z31.d +// CHECK-INST: uxtb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d1 04 <unknown> diff --git a/test/MC/AArch64/SVE/uxth.s b/test/MC/AArch64/SVE/uxth.s index 9244fa8c960b..10074b409429 100644 --- a/test/MC/AArch64/SVE/uxth.s +++ b/test/MC/AArch64/SVE/uxth.s @@ -30,3 +30,31 @@ uxth z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd3,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d3 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +uxth z4.d, p7/m, z31.d +// CHECK-INST: uxth z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d3 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +uxth z4.d, p7/m, z31.d +// CHECK-INST: uxth z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d3 04 <unknown> diff --git a/test/MC/AArch64/SVE/uxtw.s b/test/MC/AArch64/SVE/uxtw.s index e2dbdbcb0b3f..c72fedf31de3 100644 --- a/test/MC/AArch64/SVE/uxtw.s +++ b/test/MC/AArch64/SVE/uxtw.s @@ -18,3 +18,31 @@ uxtw z31.d, p7/m, z31.d // CHECK-ENCODING: [0xff,0xbf,0xd5,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff bf d5 04 <unknown> + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 <unknown> + +uxtw z4.d, p7/m, z31.d +// CHECK-INST: uxtw z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d5 04 <unknown> + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 <unknown> + +uxtw z4.d, p7/m, z31.d +// CHECK-INST: uxtw z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e4 bf d5 04 <unknown> diff --git a/test/MC/AArch64/SVE/uzp1-diagnostics.s b/test/MC/AArch64/SVE/uzp1-diagnostics.s index 3842d60a2916..98f0997527c1 100644 --- a/test/MC/AArch64/SVE/uzp1-diagnostics.s +++ b/test/MC/AArch64/SVE/uzp1-diagnostics.s @@ -41,3 +41,19 @@ uzp1 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: uzp1 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uzp1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uzp1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uzp1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uzp1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/uzp2-diagnostics.s b/test/MC/AArch64/SVE/uzp2-diagnostics.s index ecb8b33ccba2..a53cfe4aa87c 100644 --- a/test/MC/AArch64/SVE/uzp2-diagnostics.s +++ b/test/MC/AArch64/SVE/uzp2-diagnostics.s @@ -41,3 +41,19 @@ uzp2 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: uzp2 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uzp2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uzp2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uzp2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uzp2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilele-diagnostics.s b/test/MC/AArch64/SVE/whilele-diagnostics.s new file mode 100644 index 000000000000..94e3993645df --- /dev/null +++ b/test/MC/AArch64/SVE/whilele-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilele p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilele p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilele p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilele p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilele p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilele p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilele.s b/test/MC/AArch64/SVE/whilele.s new file mode 100644 index 000000000000..e8c48a6e926f --- /dev/null +++ b/test/MC/AArch64/SVE/whilele.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilele p15.b, xzr, x0 +// CHECK-INST: whilele p15.b, xzr, x0 +// CHECK-ENCODING: [0xff,0x17,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 17 20 25 <unknown> + +whilele p15.b, x0, xzr +// CHECK-INST: whilele p15.b, x0, xzr +// CHECK-ENCODING: [0x1f,0x14,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 14 3f 25 <unknown> + +whilele p15.b, wzr, w0 +// CHECK-INST: whilele p15.b, wzr, w0 +// CHECK-ENCODING: [0xff,0x07,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 07 20 25 <unknown> + +whilele p15.b, w0, wzr +// CHECK-INST: whilele p15.b, w0, wzr +// CHECK-ENCODING: [0x1f,0x04,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 04 3f 25 <unknown> + +whilele p15.h, x0, xzr +// CHECK-INST: whilele p15.h, x0, xzr +// CHECK-ENCODING: [0x1f,0x14,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 14 7f 25 <unknown> + +whilele p15.h, w0, wzr +// CHECK-INST: whilele p15.h, w0, wzr +// CHECK-ENCODING: [0x1f,0x04,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 04 7f 25 <unknown> + +whilele p15.s, x0, xzr +// CHECK-INST: whilele p15.s, x0, xzr +// CHECK-ENCODING: [0x1f,0x14,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 14 bf 25 <unknown> + +whilele p15.s, w0, wzr +// CHECK-INST: whilele p15.s, w0, wzr +// CHECK-ENCODING: [0x1f,0x04,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 04 bf 25 <unknown> + +whilele p15.d, w0, wzr +// CHECK-INST: whilele p15.d, w0, wzr +// CHECK-ENCODING: [0x1f,0x04,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 04 ff 25 <unknown> + +whilele p15.d, x0, xzr +// CHECK-INST: whilele p15.d, x0, xzr +// CHECK-ENCODING: [0x1f,0x14,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 14 ff 25 <unknown> diff --git a/test/MC/AArch64/SVE/whilelo-diagnostics.s b/test/MC/AArch64/SVE/whilelo-diagnostics.s new file mode 100644 index 000000000000..6237a1182d01 --- /dev/null +++ b/test/MC/AArch64/SVE/whilelo-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilelo p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelo p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilelo p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelo p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilelo p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelo p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilelo.s b/test/MC/AArch64/SVE/whilelo.s new file mode 100644 index 000000000000..30fa35dcd2cf --- /dev/null +++ b/test/MC/AArch64/SVE/whilelo.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilelo p15.b, xzr, x0 +// CHECK-INST: whilelo p15.b, xzr, x0 +// CHECK-ENCODING: [0xef,0x1f,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 1f 20 25 <unknown> + +whilelo p15.b, x0, xzr +// CHECK-INST: whilelo p15.b, x0, xzr +// CHECK-ENCODING: [0x0f,0x1c,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 1c 3f 25 <unknown> + +whilelo p15.b, wzr, w0 +// CHECK-INST: whilelo p15.b, wzr, w0 +// CHECK-ENCODING: [0xef,0x0f,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 0f 20 25 <unknown> + +whilelo p15.b, w0, wzr +// CHECK-INST: whilelo p15.b, w0, wzr +// CHECK-ENCODING: [0x0f,0x0c,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 0c 3f 25 <unknown> + +whilelo p15.h, x0, xzr +// CHECK-INST: whilelo p15.h, x0, xzr +// CHECK-ENCODING: [0x0f,0x1c,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 1c 7f 25 <unknown> + +whilelo p15.h, w0, wzr +// CHECK-INST: whilelo p15.h, w0, wzr +// CHECK-ENCODING: [0x0f,0x0c,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 0c 7f 25 <unknown> + +whilelo p15.s, x0, xzr +// CHECK-INST: whilelo p15.s, x0, xzr +// CHECK-ENCODING: [0x0f,0x1c,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 1c bf 25 <unknown> + +whilelo p15.s, w0, wzr +// CHECK-INST: whilelo p15.s, w0, wzr +// CHECK-ENCODING: [0x0f,0x0c,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 0c bf 25 <unknown> + +whilelo p15.d, w0, wzr +// CHECK-INST: whilelo p15.d, w0, wzr +// CHECK-ENCODING: [0x0f,0x0c,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 0c ff 25 <unknown> + +whilelo p15.d, x0, xzr +// CHECK-INST: whilelo p15.d, x0, xzr +// CHECK-ENCODING: [0x0f,0x1c,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 1c ff 25 <unknown> diff --git a/test/MC/AArch64/SVE/whilels-diagnostics.s b/test/MC/AArch64/SVE/whilels-diagnostics.s new file mode 100644 index 000000000000..6a422900a071 --- /dev/null +++ b/test/MC/AArch64/SVE/whilels-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilels p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilels p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilels p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilels p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilels p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilels p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilels.s b/test/MC/AArch64/SVE/whilels.s new file mode 100644 index 000000000000..3e127d3e1720 --- /dev/null +++ b/test/MC/AArch64/SVE/whilels.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilels p15.b, xzr, x0 +// CHECK-INST: whilels p15.b, xzr, x0 +// CHECK-ENCODING: [0xff,0x1f,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 20 25 <unknown> + +whilels p15.b, x0, xzr +// CHECK-INST: whilels p15.b, x0, xzr +// CHECK-ENCODING: [0x1f,0x1c,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c 3f 25 <unknown> + +whilels p15.b, wzr, w0 +// CHECK-INST: whilels p15.b, wzr, w0 +// CHECK-ENCODING: [0xff,0x0f,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 0f 20 25 <unknown> + +whilels p15.b, w0, wzr +// CHECK-INST: whilels p15.b, w0, wzr +// CHECK-ENCODING: [0x1f,0x0c,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 0c 3f 25 <unknown> + +whilels p15.h, x0, xzr +// CHECK-INST: whilels p15.h, x0, xzr +// CHECK-ENCODING: [0x1f,0x1c,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c 7f 25 <unknown> + +whilels p15.h, w0, wzr +// CHECK-INST: whilels p15.h, w0, wzr +// CHECK-ENCODING: [0x1f,0x0c,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 0c 7f 25 <unknown> + +whilels p15.s, x0, xzr +// CHECK-INST: whilels p15.s, x0, xzr +// CHECK-ENCODING: [0x1f,0x1c,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c bf 25 <unknown> + +whilels p15.s, w0, wzr +// CHECK-INST: whilels p15.s, w0, wzr +// CHECK-ENCODING: [0x1f,0x0c,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 0c bf 25 <unknown> + +whilels p15.d, w0, wzr +// CHECK-INST: whilels p15.d, w0, wzr +// CHECK-ENCODING: [0x1f,0x0c,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 0c ff 25 <unknown> + +whilels p15.d, x0, xzr +// CHECK-INST: whilels p15.d, x0, xzr +// CHECK-ENCODING: [0x1f,0x1c,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 1c ff 25 <unknown> diff --git a/test/MC/AArch64/SVE/whilelt-diagnostics.s b/test/MC/AArch64/SVE/whilelt-diagnostics.s new file mode 100644 index 000000000000..1c3a8f8f46ec --- /dev/null +++ b/test/MC/AArch64/SVE/whilelt-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilelt p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelt p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilelt p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelt p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilelt p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilelt p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/whilelt.s b/test/MC/AArch64/SVE/whilelt.s new file mode 100644 index 000000000000..9a0723cdc7c9 --- /dev/null +++ b/test/MC/AArch64/SVE/whilelt.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilelt p15.b, xzr, x0 +// CHECK-INST: whilelt p15.b, xzr, x0 +// CHECK-ENCODING: [0xef,0x17,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 17 20 25 <unknown> + +whilelt p15.b, x0, xzr +// CHECK-INST: whilelt p15.b, x0, xzr +// CHECK-ENCODING: [0x0f,0x14,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 14 3f 25 <unknown> + +whilelt p15.b, wzr, w0 +// CHECK-INST: whilelt p15.b, wzr, w0 +// CHECK-ENCODING: [0xef,0x07,0x20,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 07 20 25 <unknown> + +whilelt p15.b, w0, wzr +// CHECK-INST: whilelt p15.b, w0, wzr +// CHECK-ENCODING: [0x0f,0x04,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 04 3f 25 <unknown> + +whilelt p15.h, x0, xzr +// CHECK-INST: whilelt p15.h, x0, xzr +// CHECK-ENCODING: [0x0f,0x14,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 14 7f 25 <unknown> + +whilelt p15.h, w0, wzr +// CHECK-INST: whilelt p15.h, w0, wzr +// CHECK-ENCODING: [0x0f,0x04,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 04 7f 25 <unknown> + +whilelt p15.s, x0, xzr +// CHECK-INST: whilelt p15.s, x0, xzr +// CHECK-ENCODING: [0x0f,0x14,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 14 bf 25 <unknown> + +whilelt p15.s, w0, wzr +// CHECK-INST: whilelt p15.s, w0, wzr +// CHECK-ENCODING: [0x0f,0x04,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 04 bf 25 <unknown> + +whilelt p15.d, w0, wzr +// CHECK-INST: whilelt p15.d, w0, wzr +// CHECK-ENCODING: [0x0f,0x04,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 04 ff 25 <unknown> + +whilelt p15.d, x0, xzr +// CHECK-INST: whilelt p15.d, x0, xzr +// CHECK-ENCODING: [0x0f,0x14,0xff,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f 14 ff 25 <unknown> diff --git a/test/MC/AArch64/SVE/zip1-diagnostics.s b/test/MC/AArch64/SVE/zip1-diagnostics.s index 17670be5de22..a0652e3880fd 100644 --- a/test/MC/AArch64/SVE/zip1-diagnostics.s +++ b/test/MC/AArch64/SVE/zip1-diagnostics.s @@ -41,3 +41,19 @@ zip1 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: zip1 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +zip1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: zip1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +zip1 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: zip1 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/zip2-diagnostics.s b/test/MC/AArch64/SVE/zip2-diagnostics.s index 3a78b9432fd7..7691bafb538d 100644 --- a/test/MC/AArch64/SVE/zip2-diagnostics.s +++ b/test/MC/AArch64/SVE/zip2-diagnostics.s @@ -41,3 +41,19 @@ zip2 p1.s, p2.s, z3.s // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: zip2 p1.s, p2.s, z3.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +zip2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: zip2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +zip2 z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: zip2 z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/arm64-directive_loh.s b/test/MC/AArch64/arm64-directive_loh.s index 76d2d7f21861..654dc9e70067 100644 --- a/test/MC/AArch64/arm64-directive_loh.s +++ b/test/MC/AArch64/arm64-directive_loh.s @@ -1,5 +1,7 @@ # RUN: not llvm-mc -triple arm64-apple-darwin < %s 2> %t | FileCheck %s # RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s +# RUN: not llvm-mc -triple aarch64-linux-gnu < %s 2>&1 | FileCheck --check-prefix=UNKNOWN %s +# RUN: not llvm-mc -triple aarch64-win32-gnu < %s 2>&1 | FileCheck --check-prefix=UNKNOWN %s .globl _fct1 _fct1: @@ -15,6 +17,8 @@ _fct1: # CHECK: .loh AdrpAdrp L1, L2 # CHECK: .loh AdrpAdrp L1, L2 +# UNKNOWN: error: unknown directive +# UNKNOWN-NEXT: .loh AdrpAdrp L1, L2 .loh AdrpAdrp L1, L2 .loh 1 L1, L2 diff --git a/test/MC/AArch64/inst-directive-other.s b/test/MC/AArch64/inst-directive-other.s new file mode 100644 index 000000000000..02f21c13d295 --- /dev/null +++ b/test/MC/AArch64/inst-directive-other.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc %s -triple=arm64-apple-darwin -filetype=asm -o - \ +// RUN: | FileCheck %s --check-prefix=CHECK-ASM +// RUN: llvm-mc %s -triple=arm64-apple-darwin -filetype=obj -o - \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefixes=CHECK-OBJ,CHECK-OBJ-CODE +// RUN: llvm-mc %s -triple=aarch64-win32-gnu -filetype=asm -o - \ +// RUN: | FileCheck %s --check-prefix=CHECK-ASM +// RUN: llvm-mc %s -triple=aarch64-win32-gnu -filetype=obj -o - \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefixes=CHECK-OBJ,CHECK-OBJ-CODE +// RUN: llvm-mc %s -triple=aarch64-linux-gnu -filetype=asm -o - \ +// RUN: | FileCheck %s --check-prefix=CHECK-ASM +// RUN: llvm-mc %s -triple=aarch64-linux-gnu -filetype=obj -o - \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefixes=CHECK-OBJ,CHECK-OBJ-DATA +// RUN: llvm-mc %s -triple=aarch64_be-linux-gnu -filetype=asm -o - \ +// RUN: | FileCheck %s --check-prefix=CHECK-ASM +// RUN: llvm-mc %s -triple=aarch64_be-linux-gnu -filetype=obj -o - \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefixes=CHECK-OBJ,CHECK-OBJ-BE + + .text + + .p2align 2 + .globl _func +_func: + nop + // A .long is stored differently for big endian aarch64 targets, while + // instructions always are stored in little endian. + // ELF distinguishes between data and code when emitted this way, but + // MachO and COFF don't. + .long 0xd503201f + .inst 0xd503201f + +// CHECK-ASM: .p2align 2 +// CHECK-ASM: .globl _func +// CHECK-ASM: _func: +// CHECK-ASM: nop +// CHECK-ASM: .{{long|word}} 3573751839 +// CHECK-ASM: .inst 0xd503201f + +// CHECK-OBJ: 0: 1f 20 03 d5 nop +// CHECK-OBJ-CODE: 4: 1f 20 03 d5 nop +// CHECK-OBJ-DATA: 4: 1f 20 03 d5 .word 0xd503201f +// CHECK-OBJ-BE: 4: d5 03 20 1f .word 0xd503201f +// CHECK-OBJ: 8: 1f 20 03 d5 nop diff --git a/test/MC/ARM/directive-unsupported.s b/test/MC/ARM/directive-unsupported.s index 0b1f9bac61a1..d90db7adee61 100644 --- a/test/MC/ARM/directive-unsupported.s +++ b/test/MC/ARM/directive-unsupported.s @@ -30,24 +30,6 @@ // CHECK: .eabi_attribute 0, 0 // CHECK: ^ - .inst 0xdefe - -// CHECK: error: unknown directive -// CHECK: .inst 0xdefe -// CHECK: ^ - - .inst.n 0xdefe - -// CHECK: error: unknown directive -// CHECK: .inst.n 0xdefe -// CHECK: ^ - - .inst.w 0xdefe - -// CHECK: error: unknown directive -// CHECK: .inst.w 0xdefe -// CHECK: ^ - .object_arch armv7 // CHECK: error: unknown directive diff --git a/test/MC/ARM/inst-directive-other.s b/test/MC/ARM/inst-directive-other.s new file mode 100644 index 000000000000..f5f0cafe66eb --- /dev/null +++ b/test/MC/ARM/inst-directive-other.s @@ -0,0 +1,47 @@ +// RUN: llvm-mc %s -triple=armv7-apple-darwin -filetype=asm -o - \ +// RUN: | FileCheck %s --check-prefix=CHECK-ASM +// RUN: llvm-mc %s -triple=armv7-apple-darwin -filetype=obj -o - \ +// RUN: | llvm-objdump -triple=thumbv7 -d - | FileCheck %s --check-prefixes=CHECK-OBJ-CODE +// RUN: llvm-mc %s -triple=thumbv7-win32-gnu -filetype=asm -o - \ +// RUN: | FileCheck %s --check-prefix=CHECK-ASM +// RUN: llvm-mc %s -triple=thumbv7-win32-gnu -filetype=obj -o - \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefixes=CHECK-OBJ,CHECK-OBJ-CODE +// RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=asm -o - \ +// RUN: | FileCheck %s --check-prefix=CHECK-ASM +// RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - \ +// RUN: | llvm-objdump -d -triple=thumbv7 - | FileCheck %s --check-prefixes=CHECK-OBJ,CHECK-OBJ-DATA + + .text + + .p2align 2 + .globl _func + .thumb +_func: + // ELF distinguishes between data and code when emitted this way, but + // MachO and COFF don't. + bx lr + .short 0x4770 + .inst.n 0x4770 + mov.w r0, #42 + .short 0xf04f, 0x002a + .inst.w 0xf04f002a + +// CHECK-ASM: .p2align 2 +// CHECK-ASM: .globl _func +// CHECK-ASM: _func: +// CHECK-ASM: bx lr +// CHECK-ASM: .short 18288 +// CHECK-ASM: .inst.n 0x4770 +// CHECK-ASM: mov.w r0, #42 +// CHECK-ASM: .short 61519 +// CHECK-ASM: .short 42 +// CHECK-ASM: .inst.w 0xf04f002a + +// CHECK-OBJ: 0: 70 47 bx lr +// CHECK-OBJ-CODE: 2: 70 47 bx lr +// CHECK-OBJ-DATA: 2: 70 47 .short 0x4770 +// CHECK-OBJ: 4: 70 47 bx lr +// CHECK-OBJ: 6: 4f f0 2a 00 mov.w r0, #42 +// CHECK-OBJ-CODE: a: 4f f0 2a 00 mov.w r0, #42 +// CHECK-OBJ-DATA: a: 4f f0 2a 00 .word 0x002af04f +// CHECK-OBJ: e: 4f f0 2a 00 mov.w r0, #42 diff --git a/test/MC/ARM/inst-thumb-suffixes-auto.s b/test/MC/ARM/inst-thumb-suffixes-auto.s new file mode 100644 index 000000000000..53e3b0594505 --- /dev/null +++ b/test/MC/ARM/inst-thumb-suffixes-auto.s @@ -0,0 +1,16 @@ +@ RUN: llvm-mc %s -triple armv7-linux-gnueabi -filetype asm -o - \ +@ RUN: | FileCheck %s +@ RUN: llvm-mc %s -triple armebv7-linux-gnueabi -filetype asm -o - \ +@ RUN: | FileCheck %s + + .syntax unified + .thumb + + .align 2 + .global inst_n + .type inst_n,%function +inst_n: + @ bx lr, mov.w r0, #42 + .inst 0x4770, 0xf04f002a +@ CHECK: .inst.n 0x4770 +@ CHECK: .inst.w 0xf04f002a diff --git a/test/MC/ARM/inst-thumb-suffixes.s b/test/MC/ARM/inst-thumb-suffixes.s index 40def3c3b89e..13161472d22b 100644 --- a/test/MC/ARM/inst-thumb-suffixes.s +++ b/test/MC/ARM/inst-thumb-suffixes.s @@ -8,6 +8,6 @@ .global suffixes_required_in_thumb .type suffixes_required_in_thumb,%function suffixes_required_in_thumb: - .inst 0x0000 + .inst 0xff00 @ CHECK-ERROR: cannot determine Thumb instruction size, use inst.n/inst.w instead diff --git a/test/MC/WebAssembly/debug-info.ll b/test/MC/WebAssembly/debug-info.ll index 5173029a256b..05e339279171 100644 --- a/test/MC/WebAssembly/debug-info.ll +++ b/test/MC/WebAssembly/debug-info.ll @@ -66,68 +66,62 @@ ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) -; CHECK-NEXT: Size: 0 -; CHECK-NEXT: Offset: 504 -; CHECK-NEXT: Name: .debug_ranges -; CHECK-NEXT: } -; CHECK-NEXT: Section { -; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 1 -; CHECK-NEXT: Offset: 524 +; CHECK-NEXT: Offset: 504 ; CHECK-NEXT: Name: .debug_macinfo ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 42 -; CHECK-NEXT: Offset: 546 +; CHECK-NEXT: Offset: 526 ; CHECK-NEXT: Name: .debug_pubnames ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 26 -; CHECK-NEXT: Offset: 610 +; CHECK-NEXT: Offset: 590 ; CHECK-NEXT: Name: .debug_pubtypes ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 57 -; CHECK-NEXT: Offset: 658 +; CHECK-NEXT: Offset: 638 ; CHECK-NEXT: Name: .debug_line ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 88 -; CHECK-NEXT: Offset: 733 +; CHECK-NEXT: Offset: 713 ; CHECK-NEXT: Name: linking ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 9 -; CHECK-NEXT: Offset: 835 +; CHECK-NEXT: Offset: 815 ; CHECK-NEXT: Name: reloc.DATA ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 58 -; CHECK-NEXT: Offset: 861 +; CHECK-NEXT: Offset: 841 ; CHECK-NEXT: Name: reloc..debug_info ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 6 -; CHECK-NEXT: Offset: 943 +; CHECK-NEXT: Offset: 923 ; CHECK-NEXT: Name: reloc..debug_pubnames ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 6 -; CHECK-NEXT: Offset: 977 +; CHECK-NEXT: Offset: 957 ; CHECK-NEXT: Name: reloc..debug_pubtypes ; CHECK-NEXT: } ; CHECK-NEXT: Section { ; CHECK-NEXT: Type: CUSTOM (0x0) ; CHECK-NEXT: Size: 6 -; CHECK-NEXT: Offset: 1011 +; CHECK-NEXT: Offset: 991 ; CHECK-NEXT: Name: reloc..debug_line ; CHECK-NEXT: } ; CHECK-NEXT:] @@ -151,13 +145,13 @@ ; CHECK-NEXT: 0x5B R_WEBASSEMBLY_FUNCTION_OFFSET_I32 f2 0 ; CHECK-NEXT: 0x63 R_WEBASSEMBLY_SECTION_OFFSET_I32 .debug_str 118 ; CHECK-NEXT: } -; CHECK-NEXT: Section (12) .debug_pubnames { +; CHECK-NEXT: Section (11) .debug_pubnames { ; CHECK-NEXT: 0x6 R_WEBASSEMBLY_SECTION_OFFSET_I32 .debug_info 0 ; CHECK-NEXT: } -; CHECK-NEXT: Section (13) .debug_pubtypes { +; CHECK-NEXT: Section (12) .debug_pubtypes { ; CHECK-NEXT: 0x6 R_WEBASSEMBLY_SECTION_OFFSET_I32 .debug_info 0 ; CHECK-NEXT: } -; CHECK-NEXT: Section (14) .debug_line { +; CHECK-NEXT: Section (13) .debug_line { ; CHECK-NEXT: 0x2B R_WEBASSEMBLY_FUNCTION_OFFSET_I32 f2 0 ; CHECK-NEXT: } ; CHECK-NEXT:] diff --git a/test/Other/new-pm-defaults.ll b/test/Other/new-pm-defaults.ll index fcbfc354b920..30ee219d2ca8 100644 --- a/test/Other/new-pm-defaults.ll +++ b/test/Other/new-pm-defaults.ll @@ -170,17 +170,22 @@ ; CHECK-Os-NEXT: Running pass: MergedLoadStoreMotionPass ; CHECK-Os-NEXT: Running pass: GVN ; CHECK-Os-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-Os-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-Oz-NEXT: Running pass: MergedLoadStoreMotionPass ; CHECK-Oz-NEXT: Running pass: GVN ; CHECK-Oz-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-Oz-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O2-NEXT: Running pass: MergedLoadStoreMotionPass ; CHECK-O2-NEXT: Running pass: GVN ; CHECK-O2-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-O2-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O3-NEXT: Running pass: MergedLoadStoreMotionPass ; CHECK-O3-NEXT: Running pass: GVN ; CHECK-O3-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-O3-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O-NEXT: Running pass: MemCpyOptPass ; CHECK-O1-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-O1-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O-NEXT: Running pass: SCCPPass ; CHECK-O-NEXT: Running pass: BDCEPass ; CHECK-O-NEXT: Running analysis: DemandedBitsAnalysis diff --git a/test/Other/new-pm-lto-defaults.ll b/test/Other/new-pm-lto-defaults.ll index 5bb4d9a4eac8..26680f5edc40 100644 --- a/test/Other/new-pm-lto-defaults.ll +++ b/test/Other/new-pm-lto-defaults.ll @@ -81,6 +81,7 @@ ; CHECK-O2-NEXT: Running pass: ModuleToPostOrderCGSCCPassAdaptor<{{.*}}PostOrderFunctionAttrsPass> ; CHECK-O2-NEXT: Running pass: ModuleToFunctionPassAdaptor<{{.*}}PassManager{{.*}}> ; CHECK-O2-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-O2-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O2-NEXT: Running analysis: DemandedBitsAnalysis ; CHECK-O2-NEXT: Running pass: CrossDSOCFIPass ; CHECK-O2-NEXT: Running pass: LowerTypeTestsPass diff --git a/test/Other/new-pm-thinlto-defaults.ll b/test/Other/new-pm-thinlto-defaults.ll index 3ddae0224232..e1d3d1c0b06a 100644 --- a/test/Other/new-pm-thinlto-defaults.ll +++ b/test/Other/new-pm-thinlto-defaults.ll @@ -152,17 +152,22 @@ ; CHECK-Os-NEXT: Running pass: MergedLoadStoreMotionPass ; CHECK-Os-NEXT: Running pass: GVN ; CHECK-Os-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-Os-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-Oz-NEXT: Running pass: MergedLoadStoreMotionPass ; CHECK-Oz-NEXT: Running pass: GVN ; CHECK-Oz-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-Oz-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O2-NEXT: Running pass: MergedLoadStoreMotionPass ; CHECK-O2-NEXT: Running pass: GVN ; CHECK-O2-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-O2-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O3-NEXT: Running pass: MergedLoadStoreMotionPass ; CHECK-O3-NEXT: Running pass: GVN ; CHECK-O3-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-O3-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O-NEXT: Running pass: MemCpyOptPass ; CHECK-O1-NEXT: Running analysis: MemoryDependenceAnalysis +; CHECK-O1-NEXT: Running analysis: PhiValuesAnalysis ; CHECK-O-NEXT: Running pass: SCCPPass ; CHECK-O-NEXT: Running pass: BDCEPass ; CHECK-O-NEXT: Running analysis: DemandedBitsAnalysis diff --git a/test/Other/opt-O2-pipeline.ll b/test/Other/opt-O2-pipeline.ll index 2ebb6ed909f9..b36bd2449fd0 100644 --- a/test/Other/opt-O2-pipeline.ll +++ b/test/Other/opt-O2-pipeline.ll @@ -59,6 +59,7 @@ ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Early CSE w/ MemorySSA ; CHECK-NEXT: Speculatively execute instructions if target has divergent branches +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Value Information Analysis ; CHECK-NEXT: Jump Threading @@ -120,12 +121,15 @@ ; CHECK-NEXT: Delete dead loops ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: MergedLoadStoreMotion +; CHECK-NEXT: Phi Values Analysis +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis ; CHECK-NEXT: Lazy Block Frequency Analysis ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: Global Value Numbering +; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis @@ -133,6 +137,7 @@ ; CHECK-NEXT: Sparse Conditional Constant Propagation ; CHECK-NEXT: Demanded bits analysis ; CHECK-NEXT: Bit-Tracking Dead Code Elimination +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -144,12 +149,14 @@ ; CHECK-NEXT: Value Propagation ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results +; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Dead Store Elimination ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Canonicalize natural loops ; CHECK-NEXT: LCSSA Verifier ; CHECK-NEXT: Loop-Closed SSA Form Pass +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Scalar Evolution Analysis ; CHECK-NEXT: Loop Pass Manager diff --git a/test/Other/opt-O3-pipeline.ll b/test/Other/opt-O3-pipeline.ll index d9ffc96d4349..096982a9a8d8 100644 --- a/test/Other/opt-O3-pipeline.ll +++ b/test/Other/opt-O3-pipeline.ll @@ -62,6 +62,7 @@ ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Early CSE w/ MemorySSA ; CHECK-NEXT: Speculatively execute instructions if target has divergent branches +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Value Information Analysis ; CHECK-NEXT: Jump Threading @@ -124,12 +125,15 @@ ; CHECK-NEXT: Delete dead loops ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: MergedLoadStoreMotion +; CHECK-NEXT: Phi Values Analysis +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis ; CHECK-NEXT: Lazy Block Frequency Analysis ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: Global Value Numbering +; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis @@ -137,6 +141,7 @@ ; CHECK-NEXT: Sparse Conditional Constant Propagation ; CHECK-NEXT: Demanded bits analysis ; CHECK-NEXT: Bit-Tracking Dead Code Elimination +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -148,12 +153,14 @@ ; CHECK-NEXT: Value Propagation ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results +; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Dead Store Elimination ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Canonicalize natural loops ; CHECK-NEXT: LCSSA Verifier ; CHECK-NEXT: Loop-Closed SSA Form Pass +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Scalar Evolution Analysis ; CHECK-NEXT: Loop Pass Manager diff --git a/test/Other/opt-Os-pipeline.ll b/test/Other/opt-Os-pipeline.ll index 58bf62ffc9c0..34b8fa86537a 100644 --- a/test/Other/opt-Os-pipeline.ll +++ b/test/Other/opt-Os-pipeline.ll @@ -59,6 +59,7 @@ ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Early CSE w/ MemorySSA ; CHECK-NEXT: Speculatively execute instructions if target has divergent branches +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Value Information Analysis ; CHECK-NEXT: Jump Threading @@ -107,12 +108,15 @@ ; CHECK-NEXT: Delete dead loops ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: MergedLoadStoreMotion +; CHECK-NEXT: Phi Values Analysis +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis ; CHECK-NEXT: Lazy Block Frequency Analysis ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: Global Value Numbering +; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis @@ -120,6 +124,7 @@ ; CHECK-NEXT: Sparse Conditional Constant Propagation ; CHECK-NEXT: Demanded bits analysis ; CHECK-NEXT: Bit-Tracking Dead Code Elimination +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -131,12 +136,14 @@ ; CHECK-NEXT: Value Propagation ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results +; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Dead Store Elimination ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Canonicalize natural loops ; CHECK-NEXT: LCSSA Verifier ; CHECK-NEXT: Loop-Closed SSA Form Pass +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Scalar Evolution Analysis ; CHECK-NEXT: Loop Pass Manager diff --git a/test/Transforms/GVN/PRE/pre-after-rle.ll b/test/Transforms/GVN/PRE/pre-after-rle.ll index ff35e56a6761..879d20e891be 100644 --- a/test/Transforms/GVN/PRE/pre-after-rle.ll +++ b/test/Transforms/GVN/PRE/pre-after-rle.ll @@ -63,10 +63,12 @@ preheader: %cmp = icmp slt i32 1, %h br i1 %cmp, label %body, label %exit -; Alias analysis currently can't figure out %width doesn't alias %s, so just -; check that the redundant load has been removed. +; CHECK-LABEL: preheader.body_crit_edge: +; CHECK: load i32, i32* %width, align 8 + ; CHECK-LABEL: body: ; CHECK-NOT: load i32*, i32** %start, align 8 +; CHECK-NOT: load i32, i32* %width, align 8 body: %j = phi i32 [ 0, %preheader ], [ %j.next, %body ] %s = load i32*, i32** %start, align 8 diff --git a/test/Transforms/GlobalOpt/globalsra-multigep.ll b/test/Transforms/GlobalOpt/globalsra-multigep.ll new file mode 100644 index 000000000000..87a8486d8818 --- /dev/null +++ b/test/Transforms/GlobalOpt/globalsra-multigep.ll @@ -0,0 +1,16 @@ +; RUN: opt < %s -globalopt -S | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@g_data = internal unnamed_addr global <{ [8 x i16], [8 x i16] }> <{ [8 x i16] [i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16], [8 x i16] zeroinitializer }>, align 16 +; We cannot SRA here due to the second gep meaning the access to g_data may be to either element +; CHECK: @g_data = internal unnamed_addr constant <{ [8 x i16], [8 x i16] }> + +define i16 @test(i64 %a1) { +entry: + %g1 = getelementptr inbounds <{ [8 x i16], [8 x i16] }>, <{ [8 x i16], [8 x i16] }>* @g_data, i64 0, i32 0 + %arrayidx.i = getelementptr inbounds [8 x i16], [8 x i16]* %g1, i64 0, i64 %a1 + %r = load i16, i16* %arrayidx.i, align 2 + ret i16 %r +} diff --git a/test/Transforms/GlobalOpt/globalsra-partial.ll b/test/Transforms/GlobalOpt/globalsra-partial.ll index 6f24128c42b5..141ee1bb5a8c 100644 --- a/test/Transforms/GlobalOpt/globalsra-partial.ll +++ b/test/Transforms/GlobalOpt/globalsra-partial.ll @@ -1,11 +1,12 @@ -; In this case, the global can only be broken up by one level. +; In this case, the global cannot be merged as i may be out of range ; RUN: opt < %s -globalopt -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" @G = internal global { i32, [4 x float] } zeroinitializer ; <{ i32, [4 x float] }*> [#uses=3] -; CHECK-NOT: 12345 +; CHECK: @G = internal unnamed_addr global { i32, [4 x float] } +; CHECK: 12345 define void @onlystore() { store i32 12345, i32* getelementptr ({ i32, [4 x float] }, { i32, [4 x float] }* @G, i32 0, i32 0) ret void diff --git a/test/Transforms/Inline/attributes.ll b/test/Transforms/Inline/attributes.ll index c2808ba8c037..66a831bf8179 100644 --- a/test/Transforms/Inline/attributes.ll +++ b/test/Transforms/Inline/attributes.ll @@ -333,9 +333,10 @@ define i32 @test_no-use-jump-tables3(i32 %i) "no-jump-tables"="true" { ; CHECK-NEXT: ret i32 } -; Calle with "null-pointer-is-valid"="true" attribute should not be inlined -; into a caller without this attribute. Exception: alwaysinline callee -; can still be inlined. +; Callee with "null-pointer-is-valid"="true" attribute should not be inlined +; into a caller without this attribute. +; Exception: alwaysinline callee can still be inlined but +; "null-pointer-is-valid"="true" should get copied to caller. define i32 @null-pointer-is-valid_callee0(i32 %i) "null-pointer-is-valid"="true" { ret i32 %i @@ -355,6 +356,7 @@ define i32 @null-pointer-is-valid_callee2(i32 %i) { ; CHECK-NEXT: ret i32 } +; No inlining since caller does not have "null-pointer-is-valid"="true" attribute. define i32 @test_null-pointer-is-valid0(i32 %i) { %1 = call i32 @null-pointer-is-valid_callee0(i32 %i) ret i32 %1 @@ -363,17 +365,22 @@ define i32 @test_null-pointer-is-valid0(i32 %i) { ; CHECK-NEXT: ret i32 } -define i32 @test_null-pointer-is-valid1(i32 %i) { +; alwaysinline should force inlining even when caller does not have +; "null-pointer-is-valid"="true" attribute. However, the attribute should be +; copied to caller. +define i32 @test_null-pointer-is-valid1(i32 %i) "null-pointer-is-valid"="false" { %1 = call i32 @null-pointer-is-valid_callee1(i32 %i) ret i32 %1 -; CHECK: @test_null-pointer-is-valid1( +; CHECK: @test_null-pointer-is-valid1(i32 %i) [[NULLPOINTERISVALID:#[0-9]+]] { ; CHECK-NEXT: ret i32 } +; Can inline since both caller and callee have "null-pointer-is-valid"="true" +; attribute. define i32 @test_null-pointer-is-valid2(i32 %i) "null-pointer-is-valid"="true" { %1 = call i32 @null-pointer-is-valid_callee2(i32 %i) ret i32 %1 -; CHECK: @test_null-pointer-is-valid2( +; CHECK: @test_null-pointer-is-valid2(i32 %i) [[NULLPOINTERISVALID]] { ; CHECK-NEXT: ret i32 } @@ -381,3 +388,4 @@ define i32 @test_null-pointer-is-valid2(i32 %i) "null-pointer-is-valid"="true" { ; CHECK: attributes [[FPMAD_TRUE]] = { "less-precise-fpmad"="true" } ; CHECK: attributes [[NOIMPLICITFLOAT]] = { noimplicitfloat } ; CHECK: attributes [[NOUSEJUMPTABLES]] = { "no-jump-tables"="true" } +; CHECK: attributes [[NULLPOINTERISVALID]] = { "null-pointer-is-valid"="true" } diff --git a/test/Transforms/InstCombine/and-xor-or.ll b/test/Transforms/InstCombine/and-xor-or.ll index e4495fa5b0ae..1eb871e594cc 100644 --- a/test/Transforms/InstCombine/and-xor-or.ll +++ b/test/Transforms/InstCombine/and-xor-or.ll @@ -1,6 +1,101 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s +; a & (a ^ b) --> a & ~b + +define i32 @and_xor_common_op(i32 %pa, i32 %pb) { +; CHECK-LABEL: @and_xor_common_op( +; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[PA:%.*]] +; CHECK-NEXT: [[B:%.*]] = udiv i32 43, [[PB:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B]], -1 +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %a = udiv i32 42, %pa ; thwart complexity-based canonicalization + %b = udiv i32 43, %pb ; thwart complexity-based canonicalization + %xor = xor i32 %a, %b + %r = and i32 %a, %xor + ret i32 %r +} + +; a & (b ^ a) --> a & ~b + +define i32 @and_xor_common_op_commute1(i32 %pa, i32 %pb) { +; CHECK-LABEL: @and_xor_common_op_commute1( +; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[PA:%.*]] +; CHECK-NEXT: [[B:%.*]] = udiv i32 43, [[PB:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B]], -1 +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %a = udiv i32 42, %pa ; thwart complexity-based canonicalization + %b = udiv i32 43, %pb ; thwart complexity-based canonicalization + %xor = xor i32 %b, %a + %r = and i32 %a, %xor + ret i32 %r +} + +; (b ^ a) & a --> a & ~b + +define i32 @and_xor_common_op_commute2(i32 %pa, i32 %pb) { +; CHECK-LABEL: @and_xor_common_op_commute2( +; CHECK-NEXT: [[A:%.*]] = udiv i32 42, [[PA:%.*]] +; CHECK-NEXT: [[B:%.*]] = udiv i32 43, [[PB:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B]], -1 +; CHECK-NEXT: [[R:%.*]] = and i32 [[A]], [[TMP1]] +; CHECK-NEXT: ret i32 [[R]] +; + %a = udiv i32 42, %pa ; thwart complexity-based canonicalization + %b = udiv i32 43, %pb ; thwart complexity-based canonicalization + %xor = xor i32 %b, %a + %r = and i32 %xor, %a + ret i32 %r +} + +; (a ^ b) & a --> a & ~b + +define <2 x i32> @and_xor_common_op_commute3(<2 x i32> %pa, <2 x i32> %pb) { +; CHECK-LABEL: @and_xor_common_op_commute3( +; CHECK-NEXT: [[A:%.*]] = udiv <2 x i32> <i32 42, i32 43>, [[PA:%.*]] +; CHECK-NEXT: [[B:%.*]] = udiv <2 x i32> <i32 43, i32 42>, [[PB:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[B]], <i32 -1, i32 -1> +; CHECK-NEXT: [[R:%.*]] = and <2 x i32> [[A]], [[TMP1]] +; CHECK-NEXT: ret <2 x i32> [[R]] +; + %a = udiv <2 x i32> <i32 42, i32 43>, %pa ; thwart complexity-based canonicalization + %b = udiv <2 x i32> <i32 43, i32 42>, %pb ; thwart complexity-based canonicalization + %xor = xor <2 x i32> %a, %b + %r = and <2 x i32> %xor, %a + ret <2 x i32> %r +} + +; It's ok to match a common constant. +; TODO: The xor should be a 'not' op (-1 constant), but demanded bits shrinks it. + +define <4 x i32> @and_xor_common_op_constant(<4 x i32> %A) { +; CHECK-LABEL: @and_xor_common_op_constant( +; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i32> [[A:%.*]], <i32 7, i32 7, i32 7, i32 7> +; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4> +; CHECK-NEXT: ret <4 x i32> [[TMP2]] +; + %1 = xor <4 x i32> %A, <i32 1, i32 2, i32 3, i32 4> + %2 = and <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %1 + ret <4 x i32> %2 +} + +; a & (a ^ ~b) --> a & b + +define i32 @and_xor_not_common_op(i32 %a, i32 %b) { +; CHECK-LABEL: @and_xor_not_common_op( +; CHECK-NEXT: [[T4:%.*]] = and i32 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: ret i32 [[T4]] +; + %b2 = xor i32 %b, -1 + %t2 = xor i32 %a, %b2 + %t4 = and i32 %t2, %a + ret i32 %t4 +} + ; rdar://10770603 ; (x & y) | (x ^ y) -> x | y diff --git a/test/Transforms/InstCombine/and2.ll b/test/Transforms/InstCombine/and2.ll index dde786c9b009..ec23f61cb673 100644 --- a/test/Transforms/InstCombine/and2.ll +++ b/test/Transforms/InstCombine/and2.ll @@ -21,18 +21,6 @@ define i32 @test3(i32 %X, i32 %Y) { ret i32 %b } -; Make sure we don't go into an infinite loop with this test -define <4 x i32> @test5(<4 x i32> %A) { -; CHECK-LABEL: @test5( -; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i32> %A, <i32 1, i32 2, i32 3, i32 4> -; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4> -; CHECK-NEXT: ret <4 x i32> [[TMP2]] -; - %1 = xor <4 x i32> %A, <i32 1, i32 2, i32 3, i32 4> - %2 = and <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %1 - ret <4 x i32> %2 -} - define i1 @test7(i32 %i, i1 %b) { ; CHECK-LABEL: @test7( ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %i, 0 diff --git a/test/Transforms/InstCombine/double-float-shrink-1.ll b/test/Transforms/InstCombine/double-float-shrink-1.ll index 5d015bc99ae9..01c1087dec69 100644 --- a/test/Transforms/InstCombine/double-float-shrink-1.ll +++ b/test/Transforms/InstCombine/double-float-shrink-1.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" @@ -10,376 +11,507 @@ target triple = "x86_64-unknown-linux-gnu" ; PR17850: http://llvm.org/bugs/show_bug.cgi?id=17850 define float @acos_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @acos(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: acos_test1 -; CHECK: call fast float @acosf(float %f) +; CHECK-LABEL: @acos_test1( +; CHECK-NEXT: [[ACOSF:%.*]] = call fast float @acosf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[ACOSF]] +; + %conv = fpext float %f to double + %call = call fast double @acos(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @acos_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @acos(double %conv) - ret double %call -; CHECK-LABEL: acos_test2 -; CHECK: call fast double @acos(double %conv) +; CHECK-LABEL: @acos_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @acos(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @acos(double %conv) + ret double %call } define float @acosh_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @acosh(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: acosh_test1 -; CHECK: call fast float @acoshf(float %f) +; CHECK-LABEL: @acosh_test1( +; CHECK-NEXT: [[ACOSHF:%.*]] = call fast float @acoshf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[ACOSHF]] +; + %conv = fpext float %f to double + %call = call fast double @acosh(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @acosh_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @acosh(double %conv) - ret double %call -; CHECK-LABEL: acosh_test2 -; CHECK: call fast double @acosh(double %conv) +; CHECK-LABEL: @acosh_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @acosh(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @acosh(double %conv) + ret double %call } define float @asin_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @asin(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: asin_test1 -; CHECK: call fast float @asinf(float %f) +; CHECK-LABEL: @asin_test1( +; CHECK-NEXT: [[ASINF:%.*]] = call fast float @asinf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[ASINF]] +; + %conv = fpext float %f to double + %call = call fast double @asin(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @asin_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @asin(double %conv) - ret double %call -; CHECK-LABEL: asin_test2 -; CHECK: call fast double @asin(double %conv) +; CHECK-LABEL: @asin_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @asin(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @asin(double %conv) + ret double %call } define float @asinh_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @asinh(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: asinh_test1 -; CHECK: call fast float @asinhf(float %f) +; CHECK-LABEL: @asinh_test1( +; CHECK-NEXT: [[ASINHF:%.*]] = call fast float @asinhf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[ASINHF]] +; + %conv = fpext float %f to double + %call = call fast double @asinh(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @asinh_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @asinh(double %conv) - ret double %call -; CHECK-LABEL: asinh_test2 -; CHECK: call fast double @asinh(double %conv) +; CHECK-LABEL: @asinh_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @asinh(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @asinh(double %conv) + ret double %call } define float @atan_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @atan(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: atan_test1 -; CHECK: call fast float @atanf(float %f) +; CHECK-LABEL: @atan_test1( +; CHECK-NEXT: [[ATANF:%.*]] = call fast float @atanf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[ATANF]] +; + %conv = fpext float %f to double + %call = call fast double @atan(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @atan_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @atan(double %conv) - ret double %call -; CHECK-LABEL: atan_test2 -; CHECK: call fast double @atan(double %conv) +; CHECK-LABEL: @atan_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @atan(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @atan(double %conv) + ret double %call } define float @atanh_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @atanh(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: atanh_test1 -; CHECK: call fast float @atanhf(float %f) +; CHECK-LABEL: @atanh_test1( +; CHECK-NEXT: [[ATANHF:%.*]] = call fast float @atanhf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[ATANHF]] +; + %conv = fpext float %f to double + %call = call fast double @atanh(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @atanh_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @atanh(double %conv) - ret double %call -; CHECK-LABEL: atanh_test2 -; CHECK: call fast double @atanh(double %conv) +; CHECK-LABEL: @atanh_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @atanh(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @atanh(double %conv) + ret double %call } define float @cbrt_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @cbrt(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: cbrt_test1 -; CHECK: call fast float @cbrtf(float %f) +; CHECK-LABEL: @cbrt_test1( +; CHECK-NEXT: [[CBRTF:%.*]] = call fast float @cbrtf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[CBRTF]] +; + %conv = fpext float %f to double + %call = call fast double @cbrt(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @cbrt_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @cbrt(double %conv) - ret double %call -; CHECK-LABEL: cbrt_test2 -; CHECK: call fast double @cbrt(double %conv) +; CHECK-LABEL: @cbrt_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @cbrt(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @cbrt(double %conv) + ret double %call } define float @exp_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @exp(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: exp_test1 -; CHECK: call fast float @expf(float %f) +; CHECK-LABEL: @exp_test1( +; CHECK-NEXT: [[EXPF:%.*]] = call fast float @expf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[EXPF]] +; + %conv = fpext float %f to double + %call = call fast double @exp(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @exp_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @exp(double %conv) - ret double %call -; CHECK-LABEL: exp_test2 -; CHECK: call fast double @exp(double %conv) +; CHECK-LABEL: @exp_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @exp(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @exp(double %conv) + ret double %call } define float @expm1_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @expm1(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: expm1_test1 -; CHECK: call fast float @expm1f(float %f) +; CHECK-LABEL: @expm1_test1( +; CHECK-NEXT: [[EXPM1F:%.*]] = call fast float @expm1f(float [[F:%.*]]) +; CHECK-NEXT: ret float [[EXPM1F]] +; + %conv = fpext float %f to double + %call = call fast double @expm1(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @expm1_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @expm1(double %conv) - ret double %call -; CHECK-LABEL: expm1_test2 -; CHECK: call fast double @expm1(double %conv) +; CHECK-LABEL: @expm1_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @expm1(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @expm1(double %conv) + ret double %call } ; exp10f() doesn't exist for this triple, so it doesn't shrink. define float @exp10_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @exp10(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: exp10_test1 -; CHECK: call fast double @exp10(double %conv) +; CHECK-LABEL: @exp10_test1( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @exp10(double [[CONV]]) +; CHECK-NEXT: [[CONV1:%.*]] = fptrunc double [[CALL]] to float +; CHECK-NEXT: ret float [[CONV1]] +; + %conv = fpext float %f to double + %call = call fast double @exp10(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @exp10_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @exp10(double %conv) - ret double %call -; CHECK-LABEL: exp10_test2 -; CHECK: call fast double @exp10(double %conv) +; CHECK-LABEL: @exp10_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @exp10(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @exp10(double %conv) + ret double %call } define float @log_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @log(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: log_test1 -; CHECK: call fast float @logf(float %f) +; CHECK-LABEL: @log_test1( +; CHECK-NEXT: [[LOGF:%.*]] = call fast float @logf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[LOGF]] +; + %conv = fpext float %f to double + %call = call fast double @log(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @log_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @log(double %conv) - ret double %call -; CHECK-LABEL: log_test2 -; CHECK: call fast double @log(double %conv) +; CHECK-LABEL: @log_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @log(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @log(double %conv) + ret double %call } define float @log10_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @log10(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: log10_test1 -; CHECK: call fast float @log10f(float %f) +; CHECK-LABEL: @log10_test1( +; CHECK-NEXT: [[LOG10F:%.*]] = call fast float @log10f(float [[F:%.*]]) +; CHECK-NEXT: ret float [[LOG10F]] +; + %conv = fpext float %f to double + %call = call fast double @log10(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @log10_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @log10(double %conv) - ret double %call -; CHECK-LABEL: log10_test2 -; CHECK: call fast double @log10(double %conv) +; CHECK-LABEL: @log10_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @log10(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @log10(double %conv) + ret double %call } define float @log1p_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @log1p(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: log1p_test1 -; CHECK: call fast float @log1pf(float %f) +; CHECK-LABEL: @log1p_test1( +; CHECK-NEXT: [[LOG1PF:%.*]] = call fast float @log1pf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[LOG1PF]] +; + %conv = fpext float %f to double + %call = call fast double @log1p(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @log1p_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @log1p(double %conv) - ret double %call -; CHECK-LABEL: log1p_test2 -; CHECK: call fast double @log1p(double %conv) +; CHECK-LABEL: @log1p_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @log1p(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @log1p(double %conv) + ret double %call } define float @log2_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @log2(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: log2_test1 -; CHECK: call fast float @log2f(float %f) +; CHECK-LABEL: @log2_test1( +; CHECK-NEXT: [[LOG2F:%.*]] = call fast float @log2f(float [[F:%.*]]) +; CHECK-NEXT: ret float [[LOG2F]] +; + %conv = fpext float %f to double + %call = call fast double @log2(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @log2_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @log2(double %conv) - ret double %call -; CHECK-LABEL: log2_test2 -; CHECK: call fast double @log2(double %conv) +; CHECK-LABEL: @log2_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @log2(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @log2(double %conv) + ret double %call } define float @logb_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @logb(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: logb_test1 -; CHECK: call fast float @logbf(float %f) +; CHECK-LABEL: @logb_test1( +; CHECK-NEXT: [[LOGBF:%.*]] = call fast float @logbf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[LOGBF]] +; + %conv = fpext float %f to double + %call = call fast double @logb(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @logb_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @logb(double %conv) - ret double %call -; CHECK-LABEL: logb_test2 -; CHECK: call fast double @logb(double %conv) +; CHECK-LABEL: @logb_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @logb(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @logb(double %conv) + ret double %call +} + +; FIXME: Miscompile - we dropped the 2nd argument! + +define float @pow_test1(float %f, float %g) { +; CHECK-LABEL: @pow_test1( +; CHECK-NEXT: [[POWF:%.*]] = call fast float @powf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[POWF]] +; + %df = fpext float %f to double + %dg = fpext float %g to double + %call = call fast double @pow(double %df, double %dg) + %fr = fptrunc double %call to float + ret float %fr +} + +; TODO: This should shrink? + +define double @pow_test2(float %f, float %g) { +; CHECK-LABEL: @pow_test2( +; CHECK-NEXT: [[DF:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[DG:%.*]] = fpext float [[G:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @pow(double [[DF]], double [[DG]]) +; CHECK-NEXT: ret double [[CALL]] +; + %df = fpext float %f to double + %dg = fpext float %g to double + %call = call fast double @pow(double %df, double %dg) + ret double %call } define float @sin_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @sin(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: sin_test1 -; CHECK: call fast float @sinf(float %f) +; CHECK-LABEL: @sin_test1( +; CHECK-NEXT: [[SINF:%.*]] = call fast float @sinf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[SINF]] +; + %conv = fpext float %f to double + %call = call fast double @sin(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @sin_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @sin(double %conv) - ret double %call -; CHECK-LABEL: sin_test2 -; CHECK: call fast double @sin(double %conv) +; CHECK-LABEL: @sin_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @sin(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @sin(double %conv) + ret double %call } define float @sqrt_test1(float %f) { - %conv = fpext float %f to double - %call = call double @sqrt(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: sqrt_test1 -; CHECK: call float @sqrtf(float %f) +; CHECK-LABEL: @sqrt_test1( +; CHECK-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[SQRTF]] +; + %conv = fpext float %f to double + %call = call double @sqrt(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @sqrt_test2(float %f) { - %conv = fpext float %f to double - %call = call double @sqrt(double %conv) - ret double %call -; CHECK-LABEL: sqrt_test2 -; CHECK: call double @sqrt(double %conv) +; CHECK-LABEL: @sqrt_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call double @sqrt(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call double @sqrt(double %conv) + ret double %call } define float @sqrt_int_test1(float %f) { - %conv = fpext float %f to double - %call = call double @llvm.sqrt.f64(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: sqrt_int_test1 -; CHECK: call float @llvm.sqrt.f32(float %f) +; CHECK-LABEL: @sqrt_int_test1( +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.sqrt.f32(float [[F:%.*]]) +; CHECK-NEXT: ret float [[TMP1]] +; + %conv = fpext float %f to double + %call = call double @llvm.sqrt.f64(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @sqrt_int_test2(float %f) { - %conv = fpext float %f to double - %call = call double @llvm.sqrt.f64(double %conv) - ret double %call -; CHECK-LABEL: sqrt_int_test2 -; CHECK: call double @llvm.sqrt.f64(double %conv) +; CHECK-LABEL: @sqrt_int_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call double @llvm.sqrt.f64(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call double @llvm.sqrt.f64(double %conv) + ret double %call } define float @tan_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @tan(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: tan_test1 -; CHECK: call fast float @tanf(float %f) +; CHECK-LABEL: @tan_test1( +; CHECK-NEXT: [[TANF:%.*]] = call fast float @tanf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[TANF]] +; + %conv = fpext float %f to double + %call = call fast double @tan(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @tan_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @tan(double %conv) - ret double %call -; CHECK-LABEL: tan_test2 -; CHECK: call fast double @tan(double %conv) +; CHECK-LABEL: @tan_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @tan(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @tan(double %conv) + ret double %call } define float @tanh_test1(float %f) { - %conv = fpext float %f to double - %call = call fast double @tanh(double %conv) - %conv1 = fptrunc double %call to float - ret float %conv1 -; CHECK-LABEL: tanh_test1 -; CHECK: call fast float @tanhf(float %f) +; CHECK-LABEL: @tanh_test1( +; CHECK-NEXT: [[TANHF:%.*]] = call fast float @tanhf(float [[F:%.*]]) +; CHECK-NEXT: ret float [[TANHF]] +; + %conv = fpext float %f to double + %call = call fast double @tanh(double %conv) + %conv1 = fptrunc double %call to float + ret float %conv1 } define double @tanh_test2(float %f) { - %conv = fpext float %f to double - %call = call fast double @tanh(double %conv) - ret double %call -; CHECK-LABEL: tanh_test2 -; CHECK: call fast double @tanh(double %conv) +; CHECK-LABEL: @tanh_test2( +; CHECK-NEXT: [[CONV:%.*]] = fpext float [[F:%.*]] to double +; CHECK-NEXT: [[CALL:%.*]] = call fast double @tanh(double [[CONV]]) +; CHECK-NEXT: ret double [[CALL]] +; + %conv = fpext float %f to double + %call = call fast double @tanh(double %conv) + ret double %call } ; 'arcp' on an fmax() is meaningless. This test just proves that ; flags are propagated for shrunken *binary* double FP calls. define float @max1(float %a, float %b) { +; CHECK-LABEL: @max1( +; CHECK-NEXT: [[FMAXF:%.*]] = call arcp float @fmaxf(float [[A:%.*]], float [[B:%.*]]) +; CHECK-NEXT: ret float [[FMAXF]] +; %c = fpext float %a to double %d = fpext float %b to double %e = call arcp double @fmax(double %c, double %d) %f = fptrunc double %e to float ret float %f - -; CHECK-LABEL: max1( -; CHECK-NEXT: call arcp float @fmaxf(float %a, float %b) -; CHECK-NEXT: ret } ; A function can have a name that matches a common libcall, ; but with the wrong type(s). Let it be. define float @fake_fmin(float %a, float %b) { +; CHECK-LABEL: @fake_fmin( +; CHECK-NEXT: [[C:%.*]] = fpext float [[A:%.*]] to fp128 +; CHECK-NEXT: [[D:%.*]] = fpext float [[B:%.*]] to fp128 +; CHECK-NEXT: [[E:%.*]] = call fp128 @fmin(fp128 [[C]], fp128 [[D]]) +; CHECK-NEXT: [[F:%.*]] = fptrunc fp128 [[E]] to float +; CHECK-NEXT: ret float [[F]] +; %c = fpext float %a to fp128 %d = fpext float %b to fp128 %e = call fp128 @fmin(fp128 %c, fp128 %d) %f = fptrunc fp128 %e to float ret float %f - -; CHECK-LABEL: fake_fmin( -; CHECK-NEXT: %c = fpext float %a to fp128 -; CHECK-NEXT: %d = fpext float %b to fp128 -; CHECK-NEXT: %e = call fp128 @fmin(fp128 %c, fp128 %d) -; CHECK-NEXT: %f = fptrunc fp128 %e to float -; CHECK-NEXT: ret float %f } declare fp128 @fmin(fp128, fp128) ; This is not the 'fmin' you're looking for. @@ -389,12 +521,13 @@ declare double @fmax(double, double) declare double @tanh(double) declare double @tan(double) -; sqrt is a special case: the shrinking optimization +; sqrt is a special case: the shrinking optimization ; is valid even without unsafe-fp-math. -declare double @sqrt(double) -declare double @llvm.sqrt.f64(double) +declare double @sqrt(double) +declare double @llvm.sqrt.f64(double) declare double @sin(double) +declare double @pow(double, double) declare double @log2(double) declare double @log1p(double) declare double @log10(double) diff --git a/test/Transforms/InstCombine/gep-addrspace.ll b/test/Transforms/InstCombine/gep-addrspace.ll index 4a4951dee7fd..fadf2ae6bf68 100644 --- a/test/Transforms/InstCombine/gep-addrspace.ll +++ b/test/Transforms/InstCombine/gep-addrspace.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" @@ -7,7 +8,9 @@ target triple = "x86_64-pc-win32" ; make sure that we are not crashing when creating an illegal type define void @func(%myStruct addrspace(1)* nocapture %p) nounwind { -ST: +; CHECK-LABEL: @func( +; CHECK-NEXT: ret void +; %A = getelementptr inbounds %myStruct, %myStruct addrspace(1)* %p, i64 0 %B = addrspacecast %myStruct addrspace(1)* %A to %myStruct* %C = getelementptr inbounds %myStruct, %myStruct* %B, i32 0, i32 1 @@ -21,14 +24,19 @@ ST: @scalar = internal addrspace(3) global float 0.000000e+00, align 4 define void @keep_necessary_addrspacecast(i64 %i, float** %out0, float** %out1) { -entry: -; CHECK-LABEL: @keep_necessary_addrspacecast - %0 = getelementptr [256 x float], [256 x float]* addrspacecast ([256 x float] addrspace(3)* @array to [256 x float]*), i64 0, i64 %i -; CHECK: addrspacecast float addrspace(3)* %{{[0-9]+}} to float* - %1 = getelementptr [0 x float], [0 x float]* addrspacecast (float addrspace(3)* @scalar to [0 x float]*), i64 0, i64 %i -; CHECK: addrspacecast float addrspace(3)* %{{[0-9]+}} to float* - store float* %0, float** %out0, align 4 - store float* %1, float** %out1, align 4 +; CHECK-LABEL: @keep_necessary_addrspacecast( +; CHECK-NEXT: [[T01:%.*]] = getelementptr [256 x float], [256 x float] addrspace(3)* @array, i64 0, i64 [[I:%.*]] +; CHECK-NEXT: [[T0:%.*]] = addrspacecast float addrspace(3)* [[T01]] to float* +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, float addrspace(3)* @scalar, i64 [[I]] +; CHECK-NEXT: [[T1:%.*]] = addrspacecast float addrspace(3)* [[TMP1]] to float* +; CHECK-NEXT: store float* [[T0]], float** [[OUT0:%.*]], align 4 +; CHECK-NEXT: store float* [[T1]], float** [[OUT1:%.*]], align 4 +; CHECK-NEXT: ret void +; + %t0 = getelementptr [256 x float], [256 x float]* addrspacecast ([256 x float] addrspace(3)* @array to [256 x float]*), i64 0, i64 %i + %t1 = getelementptr [0 x float], [0 x float]* addrspacecast (float addrspace(3)* @scalar to [0 x float]*), i64 0, i64 %i + store float* %t0, float** %out0, align 4 + store float* %t1, float** %out1, align 4 ret void } @@ -37,17 +45,42 @@ declare void @escape_alloca(i16*) ; check that addrspacecast is not ignored (leading to an assertion failure) ; when trying to mark a GEP as inbounds define { i8, i8 } @inbounds_after_addrspacecast() { -top: -; CHECK-LABEL: @inbounds_after_addrspacecast - %0 = alloca i16, align 2 - call void @escape_alloca(i16* %0) - %tmpcast = bitcast i16* %0 to [2 x i8]* -; CHECK: addrspacecast [2 x i8]* %tmpcast to [2 x i8] addrspace(11)* - %1 = addrspacecast [2 x i8]* %tmpcast to [2 x i8] addrspace(11)* -; CHECK: getelementptr [2 x i8], [2 x i8] addrspace(11)* %1, i64 0, i64 1 - %2 = getelementptr [2 x i8], [2 x i8] addrspace(11)* %1, i64 0, i64 1 -; CHECK: addrspace(11) - %3 = load i8, i8 addrspace(11)* %2, align 1 - %.fca.1.insert = insertvalue { i8, i8 } zeroinitializer, i8 %3, 1 - ret { i8, i8 } %.fca.1.insert +; CHECK-LABEL: @inbounds_after_addrspacecast( +; CHECK-NEXT: [[T0:%.*]] = alloca i16, align 2 +; CHECK-NEXT: call void @escape_alloca(i16* nonnull [[T0]]) +; CHECK-NEXT: [[TMPCAST:%.*]] = bitcast i16* [[T0]] to [2 x i8]* +; CHECK-NEXT: [[T1:%.*]] = addrspacecast [2 x i8]* [[TMPCAST]] to [2 x i8] addrspace(11)* +; CHECK-NEXT: [[T2:%.*]] = getelementptr [2 x i8], [2 x i8] addrspace(11)* [[T1]], i64 0, i64 1 +; CHECK-NEXT: [[T3:%.*]] = load i8, i8 addrspace(11)* [[T2]], align 1 +; CHECK-NEXT: [[INSERT:%.*]] = insertvalue { i8, i8 } zeroinitializer, i8 [[T3]], 1 +; CHECK-NEXT: ret { i8, i8 } [[INSERT]] +; + %t0 = alloca i16, align 2 + call void @escape_alloca(i16* %t0) + %tmpcast = bitcast i16* %t0 to [2 x i8]* + %t1 = addrspacecast [2 x i8]* %tmpcast to [2 x i8] addrspace(11)* + %t2 = getelementptr [2 x i8], [2 x i8] addrspace(11)* %t1, i64 0, i64 1 + %t3 = load i8, i8 addrspace(11)* %t2, align 1 + %insert = insertvalue { i8, i8 } zeroinitializer, i8 %t3, 1 + ret { i8, i8 } %insert +} + + +declare spir_func <16 x i32> @my_extern_func() + +; check that a bitcast is not generated when we need an addrspace cast +define void @bitcast_after_gep(<16 x i32>* %t0) { +; CHECK-LABEL: @bitcast_after_gep( +; CHECK-NEXT: [[T4:%.*]] = addrspacecast <16 x i32>* [[T0:%.*]] to <16 x i32> addrspace(3)* +; CHECK-NEXT: [[CALL:%.*]] = call spir_func <16 x i32> @my_extern_func() +; CHECK-NEXT: store <16 x i32> [[CALL]], <16 x i32> addrspace(3)* [[T4]], align 64 +; CHECK-NEXT: ret void +; + %t1 = bitcast <16 x i32>* %t0 to [16 x i32]* + %t2 = addrspacecast [16 x i32]* %t1 to [16 x i32] addrspace(3)* + %t3 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* %t2, i64 0, i64 0 + %t4 = bitcast i32 addrspace(3)* %t3 to <16 x i32> addrspace(3)* + %call = call spir_func <16 x i32> @my_extern_func() + store <16 x i32> %call, <16 x i32> addrspace(3)* %t4 + ret void } diff --git a/test/Transforms/InstCombine/pow-1.ll b/test/Transforms/InstCombine/pow-1.ll index eef4f76fb84f..cf24548db3e7 100644 --- a/test/Transforms/InstCombine/pow-1.ll +++ b/test/Transforms/InstCombine/pow-1.ll @@ -15,6 +15,8 @@ declare float @powf(float, float) nounwind readonly declare double @pow(double, double) nounwind readonly +declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) nounwind readonly +declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) nounwind readonly ; Check pow(1.0, x) -> 1.0. @@ -25,6 +27,13 @@ define float @test_simplify1(float %x) { ; CHECK-NEXT: ret float 1.000000e+00 } +define <2 x float> @test_simplify1v(<2 x float> %x) { +; CHECK-LABEL: @test_simplify1v( + %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> <float 1.0, float 1.0>, <2 x float> %x) + ret <2 x float> %retval +; CHECK-NEXT: ret <2 x float> <float 1.000000e+00, float 1.000000e+00> +} + define double @test_simplify2(double %x) { ; CHECK-LABEL: @test_simplify2( %retval = call double @pow(double 1.0, double %x) @@ -32,6 +41,13 @@ define double @test_simplify2(double %x) { ; CHECK-NEXT: ret double 1.000000e+00 } +define <2 x double> @test_simplify2v(<2 x double> %x) { +; CHECK-LABEL: @test_simplify2v( + %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> <double 1.0, double 1.0>, <2 x double> %x) + ret <2 x double> %retval +; CHECK-NEXT: ret <2 x double> <double 1.000000e+00, double 1.000000e+00> +} + ; Check pow(2.0, x) -> exp2(x). define float @test_simplify3(float %x) { @@ -42,6 +58,14 @@ define float @test_simplify3(float %x) { ; CHECK-NEXT: ret float [[EXP2F]] } +define <2 x float> @test_simplify3v(<2 x float> %x) { +; CHECK-LABEL: @test_simplify3v( + %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> <float 2.0, float 2.0>, <2 x float> %x) +; CHECK-NEXT: [[EXP2F:%[a-z0-9]+]] = call <2 x float> @llvm.exp2.v2f32(<2 x float> %x) + ret <2 x float> %retval +; CHECK-NEXT: ret <2 x float> [[EXP2F]] +} + define double @test_simplify4(double %x) { ; CHECK-LABEL: @test_simplify4( %retval = call double @pow(double 2.0, double %x) @@ -50,6 +74,14 @@ define double @test_simplify4(double %x) { ; CHECK-NEXT: ret double [[EXP2]] } +define <2 x double> @test_simplify4v(<2 x double> %x) { +; CHECK-LABEL: @test_simplify4v( + %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> <double 2.0, double 2.0>, <2 x double> %x) +; CHECK-NEXT: [[EXP2:%[a-z0-9]+]] = call <2 x double> @llvm.exp2.v2f64(<2 x double> %x) + ret <2 x double> %retval +; CHECK-NEXT: ret <2 x double> [[EXP2]] +} + ; Check pow(x, 0.0) -> 1.0. define float @test_simplify5(float %x) { @@ -59,6 +91,13 @@ define float @test_simplify5(float %x) { ; CHECK-NEXT: ret float 1.000000e+00 } +define <2 x float> @test_simplify5v(<2 x float> %x) { +; CHECK-LABEL: @test_simplify5v( + %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 0.0, float 0.0>) + ret <2 x float> %retval +; CHECK-NEXT: %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> zeroinitializer) +} + define double @test_simplify6(double %x) { ; CHECK-LABEL: @test_simplify6( %retval = call double @pow(double %x, double 0.0) @@ -66,6 +105,13 @@ define double @test_simplify6(double %x) { ; CHECK-NEXT: ret double 1.000000e+00 } +define <2 x double> @test_simplify6v(<2 x double> %x) { +; CHECK-LABEL: @test_simplify6v( + %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 0.0, double 0.0>) + ret <2 x double> %retval +; CHECK-NEXT: %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> zeroinitializer) +} + ; Check pow(x, 0.5) -> fabs(sqrt(x)), where x != -infinity. define float @test_simplify7(float %x) { @@ -115,6 +161,13 @@ define float @test_simplify11(float %x) { ; CHECK-NEXT: ret float %x } +define <2 x float> @test_simplify11v(<2 x float> %x) { +; CHECK-LABEL: @test_simplify11v( + %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 1.0, float 1.0>) + ret <2 x float> %retval +; CHECK-NEXT: %retval = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 1.000000e+00, float 1.000000e+00>) +} + define double @test_simplify12(double %x) { ; CHECK-LABEL: @test_simplify12( %retval = call double @pow(double %x, double 1.0) @@ -122,6 +175,13 @@ define double @test_simplify12(double %x) { ; CHECK-NEXT: ret double %x } +define <2 x double> @test_simplify12v(<2 x double> %x) { +; CHECK-LABEL: @test_simplify12v( + %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 1.0, double 1.0>) + ret <2 x double> %retval +; CHECK-NEXT: %retval = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 1.000000e+00, double 1.000000e+00>) +} + ; Check pow(x, 2.0) -> x*x. define float @pow2_strict(float %x) { @@ -133,6 +193,15 @@ define float @pow2_strict(float %x) { ret float %r } +define <2 x float> @pow2_strictv(<2 x float> %x) { +; CHECK-LABEL: @pow2_strictv( +; CHECK-NEXT: [[POW2:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 2.000000e+00, float 2.000000e+00>) +; CHECK-NEXT: ret <2 x float> [[POW2]] +; + %r = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float 2.0, float 2.0>) + ret <2 x float> %r +} + define double @pow2_double_strict(double %x) { ; CHECK-LABEL: @pow2_double_strict( ; CHECK-NEXT: [[POW2:%.*]] = fmul double %x, %x @@ -141,6 +210,14 @@ define double @pow2_double_strict(double %x) { %r = call double @pow(double %x, double 2.0) ret double %r } +define <2 x double> @pow2_double_strictv(<2 x double> %x) { +; CHECK-LABEL: @pow2_double_strictv( +; CHECK-NEXT: [[POW2:%.*]] = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.000000e+00, double 2.000000e+00>) +; CHECK-NEXT: ret <2 x double> [[POW2]] +; + %r = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.0, double 2.0>) + ret <2 x double> %r +} ; Don't drop the FMF - PR35601 ( https://bugs.llvm.org/show_bug.cgi?id=35601 ) @@ -164,6 +241,15 @@ define float @pow_neg1_strict(float %x) { ret float %r } +define <2 x float> @pow_neg1_strictv(<2 x float> %x) { +; CHECK-LABEL: @pow_neg1_strictv( +; CHECK-NEXT: [[POWRECIP:%.*]] = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float -1.000000e+00, float -1.000000e+00>) +; CHECK-NEXT: ret <2 x float> [[POWRECIP]] +; + %r = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> <float -1.0, float -1.0>) + ret <2 x float> %r +} + define double @pow_neg1_double_fast(double %x) { ; CHECK-LABEL: @pow_neg1_double_fast( ; CHECK-NEXT: [[POWRECIP:%.*]] = fdiv fast double 1.000000e+00, %x @@ -173,6 +259,15 @@ define double @pow_neg1_double_fast(double %x) { ret double %r } +define <2 x double> @pow_neg1_double_fastv(<2 x double> %x) { +; CHECK-LABEL: @pow_neg1_double_fastv( +; CHECK-NEXT: [[POWRECIP:%.*]] = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double -1.000000e+00, double -1.000000e+00>) +; CHECK-NEXT: ret <2 x double> [[POWRECIP]] +; + %r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double -1.0, double -1.0>) + ret <2 x double> %r +} + declare double @llvm.pow.f64(double %Val, double %Power) define double @test_simplify17(double %x) { ; CHECK-LABEL: @test_simplify17( diff --git a/test/Transforms/InstCombine/pow-cbrt.ll b/test/Transforms/InstCombine/pow-cbrt.ll new file mode 100644 index 000000000000..00fa510b04e6 --- /dev/null +++ b/test/Transforms/InstCombine/pow-cbrt.ll @@ -0,0 +1,117 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +define double @pow_intrinsic_third_fast(double %x) { +; CHECK-LABEL: @pow_intrinsic_third_fast( +; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double 0x3FD5555555555555) +; CHECK-NEXT: ret double [[POW]] +; + %pow = call fast double @llvm.pow.f64(double %x, double 0x3fd5555555555555) + ret double %pow +} + +define float @powf_intrinsic_third_fast(float %x) { +; CHECK-LABEL: @powf_intrinsic_third_fast( +; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[X:%.*]], float 0x3FD5555560000000) +; CHECK-NEXT: ret float [[POW]] +; + %pow = call fast float @llvm.pow.f32(float %x, float 0x3fd5555560000000) + ret float %pow +} + +define double @pow_intrinsic_third_approx(double %x) { +; CHECK-LABEL: @pow_intrinsic_third_approx( +; CHECK-NEXT: [[POW:%.*]] = call afn double @llvm.pow.f64(double [[X:%.*]], double 0x3FD5555555555555) +; CHECK-NEXT: ret double [[POW]] +; + %pow = call afn double @llvm.pow.f64(double %x, double 0x3fd5555555555555) + ret double %pow +} + +define float @powf_intrinsic_third_approx(float %x) { +; CHECK-LABEL: @powf_intrinsic_third_approx( +; CHECK-NEXT: [[POW:%.*]] = call afn float @llvm.pow.f32(float [[X:%.*]], float 0x3FD5555560000000) +; CHECK-NEXT: ret float [[POW]] +; + %pow = call afn float @llvm.pow.f32(float %x, float 0x3fd5555560000000) + ret float %pow +} + +define double @pow_libcall_third_fast(double %x) { +; CHECK-LABEL: @pow_libcall_third_fast( +; CHECK-NEXT: [[POW:%.*]] = call fast double @pow(double [[X:%.*]], double 0x3FD5555555555555) +; CHECK-NEXT: ret double [[POW]] +; + %pow = call fast double @pow(double %x, double 0x3fd5555555555555) + ret double %pow +} + +define float @powf_libcall_third_fast(float %x) { +; CHECK-LABEL: @powf_libcall_third_fast( +; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float 0x3FD5555560000000) +; CHECK-NEXT: ret float [[POW]] +; + %pow = call fast float @powf(float %x, float 0x3fd5555560000000) + ret float %pow +} + +define double @pow_intrinsic_negthird_fast(double %x) { +; CHECK-LABEL: @pow_intrinsic_negthird_fast( +; CHECK-NEXT: [[POW:%.*]] = call fast double @llvm.pow.f64(double [[X:%.*]], double 0xBFD5555555555555) +; CHECK-NEXT: ret double [[POW]] +; + %pow = call fast double @llvm.pow.f64(double %x, double 0xbfd5555555555555) + ret double %pow +} + +define float @powf_intrinsic_negthird_fast(float %x) { +; CHECK-LABEL: @powf_intrinsic_negthird_fast( +; CHECK-NEXT: [[POW:%.*]] = call fast float @llvm.pow.f32(float [[X:%.*]], float 0xBFD5555560000000) +; CHECK-NEXT: ret float [[POW]] +; + %pow = call fast float @llvm.pow.f32(float %x, float 0xbfd5555560000000) + ret float %pow +} + +define double @pow_intrinsic_negthird_approx(double %x) { +; CHECK-LABEL: @pow_intrinsic_negthird_approx( +; CHECK-NEXT: [[POW:%.*]] = call afn double @llvm.pow.f64(double [[X:%.*]], double 0xBFD5555555555555) +; CHECK-NEXT: ret double [[POW]] +; + %pow = call afn double @llvm.pow.f64(double %x, double 0xbfd5555555555555) + ret double %pow +} + +define float @powf_intrinsic_negthird_approx(float %x) { +; CHECK-LABEL: @powf_intrinsic_negthird_approx( +; CHECK-NEXT: [[POW:%.*]] = call afn float @llvm.pow.f32(float [[X:%.*]], float 0xBFD5555560000000) +; CHECK-NEXT: ret float [[POW]] +; + %pow = call afn float @llvm.pow.f32(float %x, float 0xbfd5555560000000) + ret float %pow +} + +define double @pow_libcall_negthird_fast(double %x) { +; CHECK-LABEL: @pow_libcall_negthird_fast( +; CHECK-NEXT: [[POW:%.*]] = call fast double @pow(double [[X:%.*]], double 0xBFD5555555555555) +; CHECK-NEXT: ret double [[POW]] +; + %pow = call fast double @pow(double %x, double 0xbfd5555555555555) + ret double %pow +} + +define float @powf_libcall_negthird_fast(float %x) { +; CHECK-LABEL: @powf_libcall_negthird_fast( +; CHECK-NEXT: [[POW:%.*]] = call fast float @powf(float [[X:%.*]], float 0xBFD5555560000000) +; CHECK-NEXT: ret float [[POW]] +; + %pow = call fast float @powf(float %x, float 0xbfd5555560000000) + ret float %pow +} + +declare double @llvm.pow.f64(double, double) #0 +declare float @llvm.pow.f32(float, float) #0 +declare double @pow(double, double) +declare float @powf(float, float) + +attributes #0 = { nounwind readnone speculatable } diff --git a/test/Transforms/InstCombine/pow-sqrt.ll b/test/Transforms/InstCombine/pow-sqrt.ll index c07a82ccedda..3b885ad5bdae 100644 --- a/test/Transforms/InstCombine/pow-sqrt.ll +++ b/test/Transforms/InstCombine/pow-sqrt.ll @@ -20,9 +20,9 @@ define <2 x double> @pow_intrinsic_half_approx(<2 x double> %x) { define double @pow_libcall_half_approx(double %x) { ; CHECK-LABEL: @pow_libcall_half_approx( -; CHECK-NEXT: [[SQRT:%.*]] = call double @sqrt(double %x) -; CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.fabs.f64(double [[SQRT]]) -; CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq double %x, 0xFFF0000000000000 +; CHECK-NEXT: [[SQRT:%.*]] = call afn double @sqrt(double %x) +; CHECK-NEXT: [[TMP1:%.*]] = call afn double @llvm.fabs.f64(double [[SQRT]]) +; CHECK-NEXT: [[TMP2:%.*]] = fcmp afn oeq double %x, 0xFFF0000000000000 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], double 0x7FF0000000000000, double [[TMP1]] ; CHECK-NEXT: ret double [[TMP3]] ; diff --git a/test/Transforms/InstCombine/select-binop-icmp.ll b/test/Transforms/InstCombine/select-binop-icmp.ll new file mode 100644 index 000000000000..a2ac68fa21e3 --- /dev/null +++ b/test/Transforms/InstCombine/select-binop-icmp.ll @@ -0,0 +1,391 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +declare void @use(<2 x i1>) + +define i32 @select_xor_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_xor_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = xor i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_xor_icmp2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_xor_icmp2( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp ne i32 %x, 0 + %B = xor i32 %x, %z + %C = select i1 %A, i32 %y, i32 %B + ret i32 %C +} + +define i32 @select_xor_icmp_meta(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_xor_icmp_meta( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]], !prof !0 +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = xor i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y, !prof !0 + ret i32 %C +} + +define i32 @select_mul_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_mul_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 1 + %B = mul i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_add_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_add_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = add i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_or_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = or i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_and_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], -1 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, -1 + %B = and i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define <2 x i8> @select_xor_icmp_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { +; CHECK-LABEL: @select_xor_icmp_vec( +; CHECK-NEXT: [[A:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer +; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[Z:%.*]], <2 x i8> [[Y:%.*]] +; CHECK-NEXT: ret <2 x i8> [[C]] +; + %A = icmp eq <2 x i8> %x, <i8 0, i8 0> + %B = xor <2 x i8> %x, %z + %C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y + ret <2 x i8> %C +} + +define <2 x i8> @select_xor_icmp_vec_use(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { +; CHECK-LABEL: @select_xor_icmp_vec_use( +; CHECK-NEXT: [[A:%.*]] = icmp ne <2 x i8> [[X:%.*]], zeroinitializer +; CHECK-NEXT: call void @use(<2 x i1> [[A]]) +; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[Y:%.*]], <2 x i8> [[Z:%.*]] +; CHECK-NEXT: ret <2 x i8> [[C]] +; + %A = icmp ne <2 x i8> %x, <i8 0, i8 0> + call void @use(<2 x i1> %A) + %B = xor <2 x i8> %x, %z + %C = select <2 x i1> %A, <2 x i8> %y, <2 x i8> %B + ret <2 x i8> %C +} + +define i32 @select_xor_inv_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_xor_inv_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = xor i32 %z, %x + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_xor_inv_icmp2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_xor_inv_icmp2( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Z:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp ne i32 %x, 0 + %B = xor i32 %x, %z + %C = select i1 %A, i32 %y, i32 %B + ret i32 %C +} + +; Negative tests +define i32 @select_xor_icmp_bad_1(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_xor_icmp_bad_1( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[K:%.*]] +; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, %k + %B = xor i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_xor_icmp_bad_2(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_xor_icmp_bad_2( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[B:%.*]] = xor i32 [[K:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = xor i32 %k, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_xor_icmp_bad_3(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_xor_icmp_bad_3( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 3 +; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 3 + %B = xor i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_xor_icmp_bad_4(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_xor_icmp_bad_4( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[K:%.*]] +; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, %k + %B = xor i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_xor_icmp_bad_5(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_xor_icmp_bad_5( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[Y:%.*]], i32 [[B]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp ne i32 %x, 0 + %B = xor i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_xor_icmp_bad_6(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_xor_icmp_bad_6( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1 +; CHECK-NEXT: [[B:%.*]] = xor i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp ne i32 %x, 1 + %B = xor i32 %x, %z + %C = select i1 %A, i32 %y, i32 %B + ret i32 %C +} + +define <2 x i8> @select_xor_icmp_vec_bad(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { +; CHECK-LABEL: @select_xor_icmp_vec_bad( +; CHECK-NEXT: [[A:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 5, i8 3> +; CHECK-NEXT: [[B:%.*]] = xor <2 x i8> [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[B]], <2 x i8> [[Y:%.*]] +; CHECK-NEXT: ret <2 x i8> [[C]] +; + %A = icmp eq <2 x i8> %x, <i8 5, i8 3> + %B = xor <2 x i8> %x, %z + %C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y + ret <2 x i8> %C +} + +; TODO: support for undefs, check for an identity constant does not handle them yet +define <2 x i8> @select_xor_icmp_vec_bad_2(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { +; CHECK-LABEL: @select_xor_icmp_vec_bad_2( +; CHECK-NEXT: [[A:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 0, i8 undef> +; CHECK-NEXT: [[B:%.*]] = xor <2 x i8> [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select <2 x i1> [[A]], <2 x i8> [[B]], <2 x i8> [[Y:%.*]] +; CHECK-NEXT: ret <2 x i8> [[C]] +; + %A = icmp eq <2 x i8> %x, <i8 0, i8 undef> + %B = xor <2 x i8> %x, %z + %C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y + ret <2 x i8> %C +} + +define i32 @select_mul_icmp_bad(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_mul_icmp_bad( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 3 +; CHECK-NEXT: [[B:%.*]] = mul i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 3 + %B = mul i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_add_icmp_bad(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_add_icmp_bad( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 1 +; CHECK-NEXT: [[B:%.*]] = add i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 1 + %B = add i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_and_icmp_bad(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_bad( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[B:%.*]] = and i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = and i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_or_icmp_bad(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_bad( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 3 +; CHECK-NEXT: [[B:%.*]] = or i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 3 + %B = or i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +; TODO: Support for non-commutative opcodes +define i32 @select_sub_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_sub_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[B:%.*]] = sub i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = sub i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_shl_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_shl_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[B:%.*]] = shl i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = shl i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_lshr_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_lshr_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[B:%.*]] = lshr i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = lshr i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +define i32 @select_ashr_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_ashr_icmp( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: [[B:%.*]] = ashr i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i32 [[B]], i32 [[Y:%.*]] +; CHECK-NEXT: ret i32 [[C]] +; + %A = icmp eq i32 %x, 0 + %B = ashr i32 %x, %z + %C = select i1 %A, i32 %B, i32 %y + ret i32 %C +} + +; TODO: Support for FP opcodes +define float @select_fadd_icmp(float %x, float %y, float %z) { +; CHECK-LABEL: @select_fadd_icmp( +; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], -0.000000e+00 +; CHECK-NEXT: [[B:%.*]] = fadd float [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]] +; CHECK-NEXT: ret float [[C]] +; + %A = fcmp oeq float %x, -0.0 + %B = fadd float %x, %z + %C = select i1 %A, float %B, float %y + ret float %C +} + +define float @select_fadd_icmp2(float %x, float %y, float %z) { +; CHECK-LABEL: @select_fadd_icmp2( +; CHECK-NEXT: [[A:%.*]] = fcmp ueq float [[X:%.*]], -0.000000e+00 +; CHECK-NEXT: [[B:%.*]] = fadd float [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]] +; CHECK-NEXT: ret float [[C]] +; + %A = fcmp ueq float %x, -0.0 + %B = fadd float %x, %z + %C = select i1 %A, float %B, float %y + ret float %C +} + +define float @select_fmul_icmp(float %x, float %y, float %z) { +; CHECK-LABEL: @select_fmul_icmp( +; CHECK-NEXT: [[A:%.*]] = fcmp oeq float [[X:%.*]], 1.000000e+00 +; CHECK-NEXT: [[B:%.*]] = fmul float [[X]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], float [[B]], float [[Y:%.*]] +; CHECK-NEXT: ret float [[C]] +; + %A = fcmp oeq float %x, 1.0 + %B = fmul float %x, %z + %C = select i1 %A, float %B, float %y + ret float %C +} + +!0 = !{!"branch_weights", i32 2, i32 10} diff --git a/test/Transforms/InstCombine/sub-not.ll b/test/Transforms/InstCombine/sub-not.ll index 5fc42367dad4..cd1f8f3bd52d 100644 --- a/test/Transforms/InstCombine/sub-not.ll +++ b/test/Transforms/InstCombine/sub-not.ll @@ -40,8 +40,8 @@ define <2 x i8> @sub_not_vec(<2 x i8> %x, <2 x i8> %y) { define i8 @dec_sub(i8 %x, i8 %y) { ; CHECK-LABEL: @dec_sub( -; CHECK-NEXT: [[S:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[R:%.*]] = add i8 [[S]], -1 +; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1 +; CHECK-NEXT: [[R:%.*]] = add i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: ret i8 [[R]] ; %s = sub i8 %x, %y @@ -64,8 +64,8 @@ define i8 @dec_sub_extra_use(i8 %x, i8 %y) { define <2 x i8> @dec_sub_vec(<2 x i8> %x, <2 x i8> %y) { ; CHECK-LABEL: @dec_sub_vec( -; CHECK-NEXT: [[S:%.*]] = sub <2 x i8> [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[S]], <i8 -1, i8 undef> +; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i8> [[Y:%.*]], <i8 -1, i8 -1> +; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[TMP1]], [[X:%.*]] ; CHECK-NEXT: ret <2 x i8> [[R]] ; %s = sub <2 x i8> %x, %y @@ -75,8 +75,8 @@ define <2 x i8> @dec_sub_vec(<2 x i8> %x, <2 x i8> %y) { define i8 @sub_inc(i8 %x, i8 %y) { ; CHECK-LABEL: @sub_inc( -; CHECK-NEXT: [[S:%.*]] = add i8 [[X:%.*]], 1 -; CHECK-NEXT: [[R:%.*]] = sub i8 [[Y:%.*]], [[S]] +; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[X:%.*]], -1 +; CHECK-NEXT: [[R:%.*]] = add i8 [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: ret i8 [[R]] ; %s = add i8 %x, 1 @@ -99,8 +99,8 @@ define i8 @sub_inc_extra_use(i8 %x, i8 %y) { define <2 x i8> @sub_inc_vec(<2 x i8> %x, <2 x i8> %y) { ; CHECK-LABEL: @sub_inc_vec( -; CHECK-NEXT: [[S:%.*]] = add <2 x i8> [[X:%.*]], <i8 undef, i8 1> -; CHECK-NEXT: [[R:%.*]] = sub <2 x i8> [[Y:%.*]], [[S]] +; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i8> [[X:%.*]], <i8 -1, i8 -1> +; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[TMP1]], [[Y:%.*]] ; CHECK-NEXT: ret <2 x i8> [[R]] ; %s = add <2 x i8> %x, <i8 undef, i8 1> @@ -108,3 +108,38 @@ define <2 x i8> @sub_inc_vec(<2 x i8> %x, <2 x i8> %y) { ret <2 x i8> %r } +define i8 @sub_dec(i8 %x, i8 %y) { +; CHECK-LABEL: @sub_dec( +; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[Y:%.*]], -1 +; CHECK-NEXT: [[R:%.*]] = add i8 [[TMP1]], [[X:%.*]] +; CHECK-NEXT: ret i8 [[R]] +; + %s = add i8 %x, -1 + %r = sub i8 %s, %y + ret i8 %r +} + +define i8 @sub_dec_extra_use(i8 %x, i8 %y) { +; CHECK-LABEL: @sub_dec_extra_use( +; CHECK-NEXT: [[S:%.*]] = add i8 [[X:%.*]], -1 +; CHECK-NEXT: [[R:%.*]] = sub i8 [[S]], [[Y:%.*]] +; CHECK-NEXT: call void @use(i8 [[S]]) +; CHECK-NEXT: ret i8 [[R]] +; + %s = add i8 %x, -1 + %r = sub i8 %s, %y + call void @use(i8 %s) + ret i8 %r +} + +define <2 x i8> @sub_dec_vec(<2 x i8> %x, <2 x i8> %y) { +; CHECK-LABEL: @sub_dec_vec( +; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i8> [[Y:%.*]], <i8 -1, i8 -1> +; CHECK-NEXT: [[R:%.*]] = add <2 x i8> [[TMP1]], [[X:%.*]] +; CHECK-NEXT: ret <2 x i8> [[R]] +; + %s = add <2 x i8> %x, <i8 undef, i8 -1> + %r = sub <2 x i8> %s, %y + ret <2 x i8> %r +} + diff --git a/test/Transforms/InstCombine/xor.ll b/test/Transforms/InstCombine/xor.ll index 0724af1f4221..2fc5270587fc 100644 --- a/test/Transforms/InstCombine/xor.ll +++ b/test/Transforms/InstCombine/xor.ll @@ -328,17 +328,6 @@ define i32 @test25(i32 %g, i32 %h) { ret i32 %t4 } -define i32 @test26(i32 %a, i32 %b) { -; CHECK-LABEL: @test26( -; CHECK-NEXT: [[T4:%.*]] = and i32 %b, %a -; CHECK-NEXT: ret i32 [[T4]] -; - %b2 = xor i32 %b, -1 - %t2 = xor i32 %a, %b2 - %t4 = and i32 %t2, %a - ret i32 %t4 -} - define i32 @test27(i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: @test27( ; CHECK-NEXT: [[T6:%.*]] = icmp eq i32 %b, %c diff --git a/test/Transforms/InstSimplify/AndOrXor.ll b/test/Transforms/InstSimplify/AndOrXor.ll index 251b4dea63b5..ed68f1121278 100644 --- a/test/Transforms/InstSimplify/AndOrXor.ll +++ b/test/Transforms/InstSimplify/AndOrXor.ll @@ -999,28 +999,26 @@ define i64 @shl_or_and2(i32 %a, i1 %b) { ret i64 %tmp5 } -define i32 @shl_or_and3(i32 %a, i32 %b) { ; concatinate two 32-bit integers and extract lower 32-bit +define i64 @shl_or_and3(i32 %a, i32 %b) { ; CHECK-LABEL: @shl_or_and3( ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967295 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -; CHECK-NEXT: ret i32 [[TMP6]] +; CHECK-NEXT: ret i64 [[TMP5]] ; %tmp1 = zext i32 %a to i64 %tmp2 = zext i32 %b to i64 %tmp3 = shl nuw i64 %tmp1, 32 %tmp4 = or i64 %tmp2, %tmp3 %tmp5 = and i64 %tmp4, 4294967295 - %tmp6 = trunc i64 %tmp5 to i32 - ret i32 %tmp6 + ret i64 %tmp5 } -define i32 @shl_or_and4(i16 %a, i16 %b) { ; concatinate two 16-bit integers and extract higher 16-bit +define i32 @shl_or_and4(i16 %a, i16 %b) { ; CHECK-LABEL: @shl_or_and4( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 @@ -1037,27 +1035,25 @@ define i32 @shl_or_and4(i16 %a, i16 %b) { ret i32 %tmp5 } -define i64 @shl_or_and5(i64 %a, i1 %b) { +define i128 @shl_or_and5(i64 %a, i1 %b) { ; CHECK-LABEL: @shl_or_and5( ; CHECK-NEXT: [[TMP1:%.*]] = zext i64 [[A:%.*]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i128 [[TMP1]], 64 ; CHECK-NEXT: [[TMP4:%.*]] = or i128 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = and i128 [[TMP4]], 1 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i64 -; CHECK-NEXT: ret i64 [[TMP6]] +; CHECK-NEXT: ret i128 [[TMP5]] ; %tmp1 = zext i64 %a to i128 %tmp2 = zext i1 %b to i128 %tmp3 = shl nuw i128 %tmp1, 64 %tmp4 = or i128 %tmp2, %tmp3 %tmp5 = and i128 %tmp4, 1 - %tmp6 = trunc i128 %tmp5 to i64 - ret i64 %tmp6 + ret i128 %tmp5 } +; A variation of above test cases; it fails due to the mask value define i32 @shl_or_and6(i16 %a, i16 %b) { -; A variation of above test case, but fails due to the mask value ; CHECK-LABEL: @shl_or_and6( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 @@ -1074,8 +1070,8 @@ define i32 @shl_or_and6(i16 %a, i16 %b) { ret i32 %tmp5 } +; A variation of above test cases; it fails due to the mask value define i32 @shl_or_and7(i16 %a, i16 %b) { -; A variation of above test case, but fails due to the mask value ; CHECK-LABEL: @shl_or_and7( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 @@ -1092,8 +1088,8 @@ define i32 @shl_or_and7(i16 %a, i16 %b) { ret i32 %tmp5 } +; A variation of above test cases; it fails due to the mask value define i32 @shl_or_and8(i16 %a, i16 %b) { -; A variation of above test case, but fails due to the mask value ; CHECK-LABEL: @shl_or_and8( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 @@ -1109,3 +1105,55 @@ define i32 @shl_or_and8(i16 %a, i16 %b) { %tmp5 = and i32 %tmp4, 131071 ; mask with 0x1FFFF ret i32 %tmp5 } + +define <2 x i64> @shl_or_and1v(<2 x i32> %a, <2 x i1> %b) { +; CHECK-LABEL: @shl_or_and1v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32> +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], <i64 1, i64 1> +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i32> %a to <2 x i64> + %tmp2 = zext <2 x i1> %b to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32> + %tmp4 = or <2 x i64> %tmp3, %tmp2 + %tmp5 = and <2 x i64> %tmp4, <i64 1, i64 1> + ret <2 x i64> %tmp5 +} + +define <2 x i64> @shl_or_and2v(<2 x i32> %a, <2 x i1> %b) { +; CHECK-LABEL: @shl_or_and2v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32> +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP4]], <i64 4294967296, i64 4294967296> +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i1> %b to <2 x i64> + %tmp2 = zext <2 x i32> %a to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32> + %tmp4 = or <2 x i64> %tmp2, %tmp3 + %tmp5 = and <2 x i64> %tmp4, <i64 4294967296, i64 4294967296> + ret <2 x i64> %tmp5 +} + +define <2 x i32> @shl_or_and3v(<2 x i16> %a, <2 x i16> %b) { +; A variation of above test case, but fails due to the mask value +; CHECK-LABEL: @shl_or_and3v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[A:%.*]] to <2 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[B:%.*]] to <2 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i32> [[TMP1]], <i32 16, i32 16> +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i32> [[TMP4]], <i32 -65535, i32 -65535> +; CHECK-NEXT: ret <2 x i32> [[TMP5]] +; + %tmp1 = zext <2 x i16> %a to <2 x i32> + %tmp2 = zext <2 x i16> %b to <2 x i32> + %tmp3 = shl nuw <2 x i32> %tmp1, <i32 16, i32 16> + %tmp4 = or <2 x i32> %tmp2, %tmp3 + %tmp5 = and <2 x i32> %tmp4, <i32 4294901761, i32 4294901761> ; mask with 0xFFFF0001 + ret <2 x i32> %tmp5 +} diff --git a/test/Transforms/InstSimplify/call.ll b/test/Transforms/InstSimplify/call.ll index 080d3ed22219..1e581dd4d7c7 100644 --- a/test/Transforms/InstSimplify/call.ll +++ b/test/Transforms/InstSimplify/call.ll @@ -431,22 +431,72 @@ declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 declare double @llvm.powi.f64(double, i32) declare <2 x double> @llvm.powi.v2f64(<2 x double>, i32) -define double @constant_fold_powi() nounwind uwtable ssp { +define double @constant_fold_powi() { ; CHECK-LABEL: @constant_fold_powi( -; CHECK-NEXT: entry: ; CHECK-NEXT: ret double 9.000000e+00 ; -entry: - %0 = call double @llvm.powi.f64(double 3.00000e+00, i32 2) - ret double %0 + %t0 = call double @llvm.powi.f64(double 3.00000e+00, i32 2) + ret double %t0 } -define <2 x double> @constant_fold_powi_vec() nounwind uwtable ssp { +define <2 x double> @constant_fold_powi_vec() { ; CHECK-LABEL: @constant_fold_powi_vec( -; CHECK-NEXT: entry: ; CHECK-NEXT: ret <2 x double> <double 9.000000e+00, double 2.500000e+01> ; -entry: - %0 = call <2 x double> @llvm.powi.v2f64(<2 x double> <double 3.00000e+00, double 5.00000e+00>, i32 2) - ret <2 x double> %0 + %t0 = call <2 x double> @llvm.powi.v2f64(<2 x double> <double 3.00000e+00, double 5.00000e+00>, i32 2) + ret <2 x double> %t0 +} + +declare i8 @llvm.fshl.i8(i8, i8, i8) +declare i9 @llvm.fshr.i9(i9, i9, i9) +declare <2 x i7> @llvm.fshl.v2i7(<2 x i7>, <2 x i7>, <2 x i7>) +declare <2 x i8> @llvm.fshr.v2i8(<2 x i8>, <2 x i8>, <2 x i8>) + +define i8 @fshl_no_shift(i8 %x, i8 %y) { +; CHECK-LABEL: @fshl_no_shift( +; CHECK-NEXT: ret i8 [[X:%.*]] +; + %z = call i8 @llvm.fshl.i8(i8 %x, i8 %y, i8 0) + ret i8 %z +} + +define i9 @fshr_no_shift(i9 %x, i9 %y) { +; CHECK-LABEL: @fshr_no_shift( +; CHECK-NEXT: ret i9 [[Y:%.*]] +; + %z = call i9 @llvm.fshr.i9(i9 %x, i9 %y, i9 0) + ret i9 %z +} + +define i8 @fshl_no_shift_modulo_bitwidth(i8 %x, i8 %y) { +; CHECK-LABEL: @fshl_no_shift_modulo_bitwidth( +; CHECK-NEXT: ret i8 [[X:%.*]] +; + %z = call i8 @llvm.fshl.i8(i8 %x, i8 %y, i8 40) + ret i8 %z +} + +define i9 @fshr_no_shift_modulo_bitwidth(i9 %x, i9 %y) { +; CHECK-LABEL: @fshr_no_shift_modulo_bitwidth( +; CHECK-NEXT: ret i9 [[Y:%.*]] +; + %z = call i9 @llvm.fshr.i9(i9 %x, i9 %y, i9 189) + ret i9 %z +} + +define <2 x i7> @fshl_no_shift_modulo_bitwidth_splat(<2 x i7> %x, <2 x i7> %y) { +; CHECK-LABEL: @fshl_no_shift_modulo_bitwidth_splat( +; CHECK-NEXT: ret <2 x i7> [[X:%.*]] +; + %z = call <2 x i7> @llvm.fshl.v2i7(<2 x i7> %x, <2 x i7> %y, <2 x i7> <i7 21, i7 21>) + ret <2 x i7> %z +} + +define <2 x i8> @fshr_no_shift_modulo_bitwidth_splat(<2 x i8> %x, <2 x i8> %y) { +; CHECK-LABEL: @fshr_no_shift_modulo_bitwidth_splat( +; CHECK-NEXT: ret <2 x i8> [[Y:%.*]] +; + %z = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> <i8 72, i8 72>) + ret <2 x i8> %z } + diff --git a/test/Transforms/InstSimplify/select-and-cmp.ll b/test/Transforms/InstSimplify/select-and-cmp.ll new file mode 100644 index 000000000000..7153972c79c8 --- /dev/null +++ b/test/Transforms/InstSimplify/select-and-cmp.ll @@ -0,0 +1,339 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instsimplify -S | FileCheck %s + +define i32 @select_and_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp( +; CHECK-NEXT: ret i32 [[X:%.*]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define <2 x i8> @select_and_icmp_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { +; CHECK-LABEL: @select_and_icmp_vec( +; CHECK-NEXT: ret <2 x i8> [[X:%.*]] +; + %A = icmp eq <2 x i8> %x, %z + %B = icmp eq <2 x i8> %y, %z + %C = and <2 x i1> %A, %B + %D = select <2 x i1> %C, <2 x i8> %z, <2 x i8> %x + ret <2 x i8> %D +} + +define i32 @select_and_icmp2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp2( +; CHECK-NEXT: ret i32 [[Y:%.*]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %y + ret i32 %D +} + +define i32 @select_and_icmp_alt(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_alt( +; CHECK-NEXT: ret i32 [[Z:%.*]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_and_icmp_alt2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_alt2( +; CHECK-NEXT: ret i32 [[Z:%.*]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %y, i32 %z + ret i32 %D +} + +define i32 @select_and_icmp_inv_alt(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_inv_alt( +; CHECK-NEXT: ret i32 [[Z:%.*]] +; + %A = icmp eq i32 %z, %x + %B = icmp eq i32 %z, %y + %C = and i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_and_inv_icmp_alt(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_inv_icmp_alt( +; CHECK-NEXT: ret i32 [[Z:%.*]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %B, %A + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_and_inv_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_inv_icmp( +; CHECK-NEXT: ret i32 [[X:%.*]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %B , %A + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define <2 x i8> @select_and_icmp_alt_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { +; CHECK-LABEL: @select_and_icmp_alt_vec( +; CHECK-NEXT: ret <2 x i8> [[Z:%.*]] +; + %A = icmp eq <2 x i8> %x, %z + %B = icmp eq <2 x i8> %y, %z + %C = and <2 x i1> %A, %B + %D = select <2 x i1> %C, <2 x i8> %x, <2 x i8> %z + ret <2 x i8> %D +} + + +define i32 @select_and_icmp_inv(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_inv( +; CHECK-NEXT: ret i32 [[X:%.*]] +; + %A = icmp eq i32 %z, %x + %B = icmp eq i32 %z, %y + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +; Negative tests +define i32 @select_and_icmp_pred_bad_1(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_pred_bad_1( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp ne i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_pred_bad_2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_pred_bad_2( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_pred_bad_3(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_pred_bad_3( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_pred_bad_4(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_pred_bad_4( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_bad_true_val(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_and_icmp_bad_true_val( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[K:%.*]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %k, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_bad_false_val(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_and_icmp_bad_false_val( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[K:%.*]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %k + ret i32 %D +} + +define i32 @select_and_icmp_bad_op(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_and_icmp_bad_op( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[K:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X:%.*]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %k, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_bad_op_2(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_and_icmp_bad_op_2( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[K:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %k + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_alt_bad_1(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_alt_bad_1( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp ne i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_and_icmp_alt_bad_2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_alt_bad_2( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_and_icmp_alt_bad_3(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_alt_bad_3( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_and_icmp_alt_bad_4(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_alt_bad_4( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_and_icmp_alt_bad_5(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_and_icmp_alt_bad_5( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[K:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %k + %B = icmp eq i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_and_icmp_alt_bad_true_val(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_and_icmp_alt_bad_true_val( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[K:%.*]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %k, i32 %z + ret i32 %D +} + +define i32 @select_and_icmp_alt_bad_false_val(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_and_icmp_alt_bad_false_val( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[K:%.*]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %x, i32 %k + ret i32 %D +} diff --git a/test/Transforms/InstSimplify/select-or-cmp.ll b/test/Transforms/InstSimplify/select-or-cmp.ll new file mode 100644 index 000000000000..ea29bff7d1c4 --- /dev/null +++ b/test/Transforms/InstSimplify/select-or-cmp.ll @@ -0,0 +1,339 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instsimplify -S | FileCheck %s + +define i32 @select_or_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp( +; CHECK-NEXT: ret i32 [[Z:%.*]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define <2 x i8> @select_or_icmp_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { +; CHECK-LABEL: @select_or_icmp_vec( +; CHECK-NEXT: ret <2 x i8> [[Z:%.*]] +; + %A = icmp ne <2 x i8> %x, %z + %B = icmp ne <2 x i8> %y, %z + %C = or <2 x i1> %A, %B + %D = select <2 x i1> %C, <2 x i8> %z, <2 x i8> %x + ret <2 x i8> %D +} + +define i32 @select_or_icmp2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp2( +; CHECK-NEXT: ret i32 [[Z:%.*]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %y + ret i32 %D +} + +define i32 @select_or_icmp_alt(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_alt( +; CHECK-NEXT: ret i32 [[X:%.*]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_or_icmp_alt2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_alt2( +; CHECK-NEXT: ret i32 [[Y:%.*]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %y, i32 %z + ret i32 %D +} + +define i32 @select_or_icmp_inv_alt(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_inv_alt( +; CHECK-NEXT: ret i32 [[X:%.*]] +; + %A = icmp ne i32 %z, %x + %B = icmp ne i32 %z, %y + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_or_inv_icmp_alt(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_inv_icmp_alt( +; CHECK-NEXT: ret i32 [[X:%.*]] +; + %A = icmp ne i32 %z, %x + %B = icmp ne i32 %z, %y + %C = or i1 %B, %A + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define <2 x i8> @select_or_icmp_alt_vec(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { +; CHECK-LABEL: @select_or_icmp_alt_vec( +; CHECK-NEXT: ret <2 x i8> [[X:%.*]] +; + %A = icmp ne <2 x i8> %x, %z + %B = icmp ne <2 x i8> %y, %z + %C = or <2 x i1> %A, %B + %D = select <2 x i1> %C, <2 x i8> %x, <2 x i8> %z + ret <2 x i8> %D +} + +define i32 @select_or_inv_icmp(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_inv_icmp( +; CHECK-NEXT: ret i32 [[Z:%.*]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %B , %A + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_or_icmp_inv(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_inv( +; CHECK-NEXT: ret i32 [[Z:%.*]] +; + %A = icmp ne i32 %z, %x + %B = icmp ne i32 %z, %y + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +; Negative tests +define i32 @select_and_icmp_pred_bad_1(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_pred_bad_1( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_pred_bad_2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_pred_bad_2( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp eq i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_pred_bad_3(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_pred_bad_3( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_and_icmp_pred_bad_4(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_and_icmp_pred_bad_4( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_or_icmp_bad_true_val(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_or_icmp_bad_true_val( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[K:%.*]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %k, i32 %x + ret i32 %D +} + +define i32 @select_or_icmp_bad_false_val(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_or_icmp_bad_false_val( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[K:%.*]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %k + ret i32 %D +} + +define i32 @select_or_icmp_bad_op(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_or_icmp_bad_op( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[K:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X:%.*]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %k, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + + +define i32 @select_or_icmp_bad_op_2(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_or_icmp_bad_op_2( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[K:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[Z]], i32 [[X]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %k + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %z, i32 %x + ret i32 %D +} + +define i32 @select_or_icmp_alt_bad_1(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_alt_bad_1( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_or_icmp_alt_bad_2(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_alt_bad_2( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp eq i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_or_icmp_alt_bad_3(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_alt_bad_3( +; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp eq i32 %x, %z + %B = icmp eq i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_or_icmp_alt_bad_4(i32 %x, i32 %y, i32 %z) { +; CHECK-LABEL: @select_or_icmp_alt_bad_4( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = and i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_or_icmp_alt_bad_5(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_or_icmp_alt_bad_5( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[K:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %k + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %z + ret i32 %D +} + +define i32 @select_or_icmp_alt_bad_true_val(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_or_icmp_alt_bad_true_val( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[K:%.*]], i32 [[Z]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %k, i32 %z + ret i32 %D +} + +define i32 @select_or_icmp_alt_bad_false_val(i32 %x, i32 %y, i32 %z, i32 %k) { +; CHECK-LABEL: @select_or_icmp_alt_bad_false_val( +; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[C:%.*]] = or i1 [[A]], [[B]] +; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[K:%.*]] +; CHECK-NEXT: ret i32 [[D]] +; + %A = icmp ne i32 %x, %z + %B = icmp ne i32 %y, %z + %C = or i1 %A, %B + %D = select i1 %C, i32 %x, i32 %k + ret i32 %D +} diff --git a/test/Transforms/InstSimplify/shift.ll b/test/Transforms/InstSimplify/shift.ll index 7a09ef971514..cbffd371853b 100644 --- a/test/Transforms/InstSimplify/shift.ll +++ b/test/Transforms/InstSimplify/shift.ll @@ -175,41 +175,65 @@ define <2 x i8> @shl_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) { ret <2 x i8> %r } -define i32 @shl_or_shr(i32 %a, i32 %b) { +define i64 @shl_or_shr(i32 %a, i32 %b) { ; CHECK-LABEL: @shl_or_shr( ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64 -; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 32 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -; CHECK-NEXT: ret i32 [[TMP6]] +; CHECK-NEXT: ret i64 [[TMP1]] ; %tmp1 = zext i32 %a to i64 %tmp2 = zext i32 %b to i64 %tmp3 = shl nuw i64 %tmp1, 32 %tmp4 = or i64 %tmp2, %tmp3 %tmp5 = lshr i64 %tmp4, 32 - %tmp6 = trunc i64 %tmp5 to i32 - ret i32 %tmp6 + ret i64 %tmp5 } -define i32 @shl_or_shr2(i32 %a, i32 %b) { ; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated. +define i64 @shl_or_shr2(i32 %a, i32 %b) { ; CHECK-LABEL: @shl_or_shr2( ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 31 ; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 31 -; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 -; CHECK-NEXT: ret i32 [[TMP6]] +; CHECK-NEXT: ret i64 [[TMP5]] ; %tmp1 = zext i32 %a to i64 %tmp2 = zext i32 %b to i64 %tmp3 = shl nuw i64 %tmp1, 31 %tmp4 = or i64 %tmp2, %tmp3 %tmp5 = lshr i64 %tmp4, 31 - %tmp6 = trunc i64 %tmp5 to i32 - ret i32 %tmp6 + ret i64 %tmp5 +} + +; Unit test for vector integer +define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) { +; CHECK-LABEL: @shl_or_shr1v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: ret <2 x i64> [[TMP1]] +; + %tmp1 = zext <2 x i32> %a to <2 x i64> + %tmp2 = zext <2 x i32> %b to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32> + %tmp4 = or <2 x i64> %tmp3, %tmp2 + %tmp5 = lshr <2 x i64> %tmp4, <i64 32, i64 32> + ret <2 x i64> %tmp5 +} + +; Negative unit test for vector integer +define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) { +; CHECK-LABEL: @shl_or_shr2v( +; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 31, i64 31> +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], <i64 31, i64 31> +; CHECK-NEXT: ret <2 x i64> [[TMP5]] +; + %tmp1 = zext <2 x i32> %a to <2 x i64> + %tmp2 = zext <2 x i32> %b to <2 x i64> + %tmp3 = shl nuw <2 x i64> %tmp1, <i64 31, i64 31> + %tmp4 = or <2 x i64> %tmp2, %tmp3 + %tmp5 = lshr <2 x i64> %tmp4, <i64 31, i64 31> + ret <2 x i64> %tmp5 } diff --git a/test/Transforms/LCSSA/basictest.ll b/test/Transforms/LCSSA/basictest.ll index 910e6f8f607d..7ca552039b63 100644 --- a/test/Transforms/LCSSA/basictest.ll +++ b/test/Transforms/LCSSA/basictest.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -lcssa -S | FileCheck %s ; RUN: opt < %s -passes=lcssa -S | FileCheck %s -; RUN: opt < %s -debugify -lcssa -S | FileCheck -check-prefix=CHECK2 %s +; RUN: opt < %s -debugify -lcssa -S | FileCheck -check-prefix=DEBUGIFY %s define void @lcssa(i1 %S2) { ; CHECK-LABEL: @lcssa @@ -19,9 +19,12 @@ post.if: ; preds = %if.false, %if.true br i1 %S2, label %loop.exit, label %loop.interior loop.exit: ; preds = %post.if ; CHECK: %X3.lcssa = phi i32 -; CHECK2: call void @llvm.dbg.value(metadata i32 %X3.lcssa +; DEBUGIFY: %X3.lcssa = phi i32 {{.*}}, !dbg ![[DbgLoc:[0-9]+]] +; DEBUGIFY-NEXT: call void @llvm.dbg.value(metadata i32 %X3.lcssa ; CHECK: %X4 = add i32 3, %X3.lcssa %X4 = add i32 3, %X3 ; <i32> [#uses=0] ret void } +; Make sure the lcssa phi has %X3's debug location +; DEBUGIFY: ![[DbgLoc]] = !DILocation(line: 7 diff --git a/test/Transforms/SCCP/preserve-analysis.ll b/test/Transforms/SCCP/preserve-analysis.ll index 52d2941d81ba..8d34e7195b95 100644 --- a/test/Transforms/SCCP/preserve-analysis.ll +++ b/test/Transforms/SCCP/preserve-analysis.ll @@ -7,11 +7,9 @@ ; CHECK: Globals Alias Analysis ; CHECK: Dominator Tree Construction ; CHECK: Natural Loop Information -; CHECK: Basic Alias Analysis (stateless AA impl) ; CHECK: Sparse Conditional Constant Propagation ; CHECK-NOT: Dominator Tree Construction ; CHECK-NOT: Natural Loop Information -; CHECK-NOT: Basic Alias Analysis (stateless AA impl) ; CHECK-NOT: Globals Alias Analysis ; CHECK: Loop Vectorization diff --git a/test/Transforms/SLPVectorizer/AArch64/PR38339.ll b/test/Transforms/SLPVectorizer/AArch64/PR38339.ll new file mode 100644 index 000000000000..1ab4a13260ed --- /dev/null +++ b/test/Transforms/SLPVectorizer/AArch64/PR38339.ll @@ -0,0 +1,29 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -slp-vectorizer -S -mtriple=aarch64-apple-ios -mcpu=cyclone -o - %s | FileCheck %s + +define void @f1(<2 x i16> %x, i16* %a) { +; CHECK-LABEL: @f1( +; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i16> [[X:%.*]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0> +; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 0 +; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 1 +; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 2 +; CHECK-NEXT: [[PTR3:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 3 +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[SHUFFLE]], i32 0 +; CHECK-NEXT: store i16 [[TMP1]], i16* [[A:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[PTR0]] to <4 x i16>* +; CHECK-NEXT: store <4 x i16> [[SHUFFLE]], <4 x i16>* [[TMP2]], align 2 +; CHECK-NEXT: ret void +; + %t2 = extractelement <2 x i16> %x, i32 0 + %t3 = extractelement <2 x i16> %x, i32 1 + %ptr0 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 0 + %ptr1 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 1 + %ptr2 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 2 + %ptr3 = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 3 + store i16 %t2, i16* %a + store i16 %t2, i16* %ptr0 + store i16 %t3, i16* %ptr1 + store i16 %t3, i16* %ptr2 + store i16 %t2, i16* %ptr3 + ret void +} diff --git a/test/Transforms/SimplifyCFG/merge-cond-stores.ll b/test/Transforms/SimplifyCFG/merge-cond-stores.ll index f730ef2aed3c..613eedde96bb 100644 --- a/test/Transforms/SimplifyCFG/merge-cond-stores.ll +++ b/test/Transforms/SimplifyCFG/merge-cond-stores.ll @@ -5,15 +5,15 @@ define void @test_simple(i32* %p, i32 %a, i32 %b) { ; CHECK-LABEL: @test_simple( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp ne i32 [[A:%.*]], 0 +; CHECK-NEXT: [[X1:%.*]] = icmp ne i32 [[A:%.*]], 0 ; CHECK-NEXT: [[X2:%.*]] = icmp eq i32 [[B:%.*]], 0 -; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[X2]], true -; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]] -; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[X2]], true +; CHECK-NEXT: [[TMP1:%.*]] = or i1 [[X1]], [[TMP0]] +; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP3:%.*]] ; CHECK: [[NOT_X2:%.*]] = xor i1 [[X2]], true -; CHECK-NEXT: [[DOT:%.*]] = zext i1 [[NOT_X2]] to i32 -; CHECK-NEXT: store i32 [[DOT]], i32* [[P:%.*]], align 4 -; CHECK-NEXT: br label [[TMP4]] +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = zext i1 [[NOT_X2]] to i32 +; CHECK-NEXT: store i32 [[SPEC_SELECT]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: br label [[TMP3]] ; CHECK: ret void ; entry: @@ -44,8 +44,8 @@ define void @test_simple_commuted(i32* %p, i32 %a, i32 %b) { ; CHECK-NEXT: [[X2:%.*]] = icmp eq i32 [[B:%.*]], 0 ; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[X1]], [[X2]] ; CHECK-NEXT: br i1 [[TMP0]], label [[TMP1:%.*]], label [[TMP2:%.*]] -; CHECK: [[DOT:%.*]] = zext i1 [[X2]] to i32 -; CHECK-NEXT: store i32 [[DOT]], i32* [[P:%.*]], align 4 +; CHECK: [[SPEC_SELECT:%.*]] = zext i1 [[X2]] to i32 +; CHECK-NEXT: store i32 [[SPEC_SELECT]], i32* [[P:%.*]], align 4 ; CHECK-NEXT: br label [[TMP2]] ; CHECK: ret void ; @@ -76,16 +76,16 @@ define void @test_recursive(i32* %p, i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-NEXT: [[TMP0:%.*]] = or i32 [[B:%.*]], [[A:%.*]] ; CHECK-NEXT: [[X4:%.*]] = icmp eq i32 [[D:%.*]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP0]], [[C:%.*]] -; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP1]], 0 -; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[X4]], true -; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[X4]], true +; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]] ; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP6:%.*]] ; CHECK: [[X3:%.*]] = icmp eq i32 [[C]], 0 -; CHECK-NEXT: [[NOT_X2:%.*]] = icmp ne i32 [[B]], 0 -; CHECK-NEXT: [[DOT:%.*]] = zext i1 [[NOT_X2]] to i32 -; CHECK-NEXT: [[DOT_:%.*]] = select i1 [[X3]], i32 [[DOT]], i32 2 -; CHECK-NEXT: [[DOT__:%.*]] = select i1 [[X4]], i32 [[DOT_]], i32 3 -; CHECK-NEXT: store i32 [[DOT__]], i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[X2:%.*]] = icmp ne i32 [[B]], 0 +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = zext i1 [[X2]] to i32 +; CHECK-NEXT: [[SPEC_SELECT1:%.*]] = select i1 [[X3]], i32 [[SPEC_SELECT]], i32 2 +; CHECK-NEXT: [[SPEC_SELECT2:%.*]] = select i1 [[X4]], i32 [[SPEC_SELECT1]], i32 3 +; CHECK-NEXT: store i32 [[SPEC_SELECT2]], i32* [[P:%.*]], align 4 ; CHECK-NEXT: br label [[TMP6]] ; CHECK: ret void ; @@ -265,8 +265,7 @@ define i32 @test_diamond_simple(i32* %p, i32* %q, i32 %a, i32 %b) { ; CHECK-LABEL: @test_diamond_simple( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[X1:%.*]] = icmp eq i32 [[A:%.*]], 0 -; CHECK-NEXT: [[Z1:%.*]] = add i32 [[A]], [[B:%.*]] -; CHECK-NEXT: [[Z2:%.*]] = select i1 [[X1]], i32 [[Z1]], i32 0 +; CHECK-NEXT: [[Z2:%.*]] = select i1 [[X1]], i32 [[B:%.*]], i32 0 ; CHECK-NEXT: [[X2:%.*]] = icmp eq i32 [[B]], 0 ; CHECK-NEXT: [[Z3:%.*]] = sub i32 [[Z2]], [[B]] ; CHECK-NEXT: [[Z4:%.*]] = select i1 [[X2]], i32 [[Z3]], i32 3 diff --git a/test/tools/dsymutil/X86/accelerator.test b/test/tools/dsymutil/X86/accelerator.test index 906b0e645cf4..96fc58ee5683 100644 --- a/test/tools/dsymutil/X86/accelerator.test +++ b/test/tools/dsymutil/X86/accelerator.test @@ -1,7 +1,3 @@ -UNSUPPORTED: system-windows -Windows does not like renaming files that have open handles to them. We -need to use TempFile::keep to move them in a portable way. - RUN: dsymutil -accelerator=Dwarf -oso-prepend-path=%p/.. %p/../Inputs/basic.macho.x86_64 -o %t.dwarf.dSYM RUN: dsymutil -accelerator=Apple -oso-prepend-path=%p/.. %p/../Inputs/basic.macho.x86_64 -o %t.apple.dSYM diff --git a/test/tools/dsymutil/X86/update-one-CU.test b/test/tools/dsymutil/X86/update-one-CU.test index 5d36ce7135f2..09f49ca89c48 100644 --- a/test/tools/dsymutil/X86/update-one-CU.test +++ b/test/tools/dsymutil/X86/update-one-CU.test @@ -1,7 +1,3 @@ -UNSUPPORTED: system-windows -Windows does not like renaming files that have open handles to them. We -need to use TempFile::keep to move them in a portable way. - RUN: dsymutil -oso-prepend-path=%p/.. %p/../Inputs/objc.macho.x86_64 -o %t.dSYM RUN: dsymutil -update %t.dSYM RUN: llvm-dwarfdump -apple-types -apple-objc %t.dSYM | FileCheck %s diff --git a/test/tools/dsymutil/X86/update.test b/test/tools/dsymutil/X86/update.test index cbfff63d6a87..804091ab2943 100644 --- a/test/tools/dsymutil/X86/update.test +++ b/test/tools/dsymutil/X86/update.test @@ -1,7 +1,3 @@ -UNSUPPORTED: system-windows -Windows does not like renaming files that have open handles to them. We -need to use TempFile::keep to move them in a portable way. - RUN: rm -rf %t.dir RUN: mkdir -p %t.dir RUN: cat %p/../Inputs/basic.macho.x86_64 > %t.dir/basic diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr.s b/test/tools/llvm-dwarfdump/X86/debug_addr.s new file mode 100644 index 000000000000..b0ee8be29544 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o %t.o +# RUN: llvm-dwarfdump -debug-addr %t.o | FileCheck %s + +# CHECK: .debug_addr contents + +# CHECK-NEXT: length = 0x0000000c, version = 0x0005, addr_size = 0x04, seg_size = 0x00 +# CHECK-NEXT: Addrs: [ +# CHECK-NEXT: 0x00000000 +# CHECK-NEXT: 0x00000001 +# CHECK-NEXT: ] +# CHECK-NEXT: length = 0x00000004, version = 0x0005, addr_size = 0x04, seg_size = 0x00 +# CHECK-NOT: {{.}} + + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .section .debug_info,"",@progbits +.Lcu_begin0: + .long 8 # Length of Unit + .short 5 # DWARF version number + .byte 1 # DWARF unit type + .byte 4 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 5 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 + + .section .debug_addr,"",@progbits +.Ldebug_addr1: + .long 4 # unit_length = .short + .byte + .byte + .short 5 # version + .byte 4 # address_size + .byte 0 # segment_selector_size diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_64bit_address.s b/test/tools/llvm-dwarfdump/X86/debug_addr_64bit_address.s new file mode 100644 index 000000000000..616d726d6575 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_64bit_address.s @@ -0,0 +1,29 @@ +# RUN: llvm-mc %s -filetype obj -triple x86_64-pc-linux -o %t.o +# RUN: llvm-dwarfdump -debug-addr %t.o | FileCheck %s + +# CHECK: .debug_addr contents +# CHECK-NEXT: length = 0x00000014, version = 0x0005, addr_size = 0x08, seg_size = 0x00 +# CHECK-NEXT: Addrs: [ +# CHECK-NEXT: 0x0000000100000000 +# CHECK-NEXT: 0x0000000100000001 +# CHECK-NEXT: ] +# CHECK-NOT: {{.}} + + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .section .debug_info,"",@progbits +.Lcu_begin0: + .long 8 # Length of Unit + .short 5 # DWARF version number + .byte 1 # DWARF unit type + .byte 8 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 20 # unit_length = .short + .byte + .byte + .quad + .quad + .short 5 # version + .byte 8 # address_size + .byte 0 # segment_selector_size + .quad 0x0000000100000000 + .quad 0x0000000100000001 diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_absent.s b/test/tools/llvm-dwarfdump/X86/debug_addr_absent.s new file mode 100644 index 000000000000..1965fef91cda --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_absent.s @@ -0,0 +1,4 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2>&1 | FileCheck %s +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_mismatch.s b/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_mismatch.s new file mode 100644 index 000000000000..49e694a9f1cc --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_mismatch.s @@ -0,0 +1,42 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# ERR: .debug_addr table at offset 0x0 has address size 8 which is different from CU address size 4 +# ERR-NOT: {{.}} + +# CHECK: .debug_addr contents +# CHECK-NEXT: length = 0x0000000c, version = 0x0005, addr_size = 0x04, seg_size = 0x00 +# CHECK-NEXT: Addrs: [ +# CHECK-NEXT: 0x00000000 +# CHECK-NEXT: 0x00000001 +# CHECK-NEXT: ] +# CHECK-NOT: {{.}} + + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .section .debug_info,"",@progbits +.Lcu_begin0: + .long 8 # Length of Unit + .short 5 # DWARF version number + .byte 1 # DWARF unit type + .byte 4 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 5 # version + .byte 8 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 + + .section .debug_addr,"",@progbits +.Ldebug_addr1: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 5 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s b/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s new file mode 100644 index 000000000000..e8835e087962 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} +# ERR: .debug_addr table at offset 0x0 contains data of size 7 which is not a multiple of addr size 4 +# ERR-NOT: {{.}} + +# data size is not multiple of address_size + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 11 # unit_length = .short + .byte + .byte + .long + .long - 1 + .short 5 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s b/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s new file mode 100644 index 000000000000..57e9dd3c5193 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o %t.o +# RUN: llvm-dwarfdump --debug-addr %t.o | FileCheck %s + +# CHECK: .debug_addr contents +# CHECK-NEXT: length = 0x00000000, version = 0x0004, addr_size = 0x04, seg_size = 0x00 +# CHECK-NEXT: Addrs: [ +# CHECK-NEXT: 0x00000000 +# CHECK-NEXT: 0x00000001 + + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .section .debug_info,"",@progbits +.Lcu_begin0: + .long 7 # Length of Unit + .short 4 # DWARF version number + .long .debug_abbrev # Offset Into Abbrev. Section + .byte 4 # Address Size (in bytes) + .section .debug_addr,"",@progbits + .long 0x00000000 + .long 0x00000001 diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf64.s b/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf64.s new file mode 100644 index 000000000000..bed41952df05 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf64.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} +# ERR: DWARF64 is not supported in .debug_addr at offset 0x0 +# ERR-NOT: {{.}} + +# DWARF64 table + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 0xffffffff # unit_length DWARF64 mark + .quad 12 # unit_length + .short 5 # version + .byte 3 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_empty.s b/test/tools/llvm-dwarfdump/X86/debug_addr_empty.s new file mode 100644 index 000000000000..e80cf8f280a9 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_empty.s @@ -0,0 +1,7 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - | FileCheck %s +# CHECK: .debug_addr contents: +# CHECK-NOT: Addr +# CHECK-NOT: error: + +.section .debug_addr,"",@progbits diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_invalid_addr_size.s b/test/tools/llvm-dwarfdump/X86/debug_addr_invalid_addr_size.s new file mode 100644 index 000000000000..1ba1afebf5da --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_invalid_addr_size.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} +# ERR: unsupported address size 3 +# ERR-NOT: {{.}} + +# invalid addr size + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 5 # version + .byte 3 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_segment_selector.s b/test/tools/llvm-dwarfdump/X86/debug_addr_segment_selector.s new file mode 100644 index 000000000000..21f0322fd2ec --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_segment_selector.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} +# ERR: .debug_addr table at offset 0x0 has unsupported segment selector size 1 +# ERR-NOT: {{.}} + +# non-zero segment_selector_size +# TODO: make this valid + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 4 # unit_length = .short + .byte + .byte + .short 5 # version + .byte 4 # address_size + .byte 1 # segment_selector_size diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s b/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s new file mode 100644 index 000000000000..cbecb98e6bec --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s @@ -0,0 +1,18 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} +# ERR: .debug_addr table at offset 0x0 has too small length (0x5) to contain a complete header +# ERR-NOT: {{.}} + +# too small length value + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 1 # unit_length + .short 5 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_length_field.s b/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_length_field.s new file mode 100644 index 000000000000..c26bfcb02e0a --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_length_field.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} +# ERR: section is not large enough to contain a .debug_addr table length at offset 0x0 +# ERR-NOT: {{.}} + +# too small section to contain length field + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .short 1 # unit_length diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s b/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s new file mode 100644 index 000000000000..facffee69fb6 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s @@ -0,0 +1,16 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} +# ERR: section is not large enough to contain a .debug_addr table of length 0x10 at offset 0x0 +# ERR-NOT: {{.}} + +# too small section to contain section of given length + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 12 # unit_length + .short 5 # version + .byte 4 # address_size + .byte 0 # segment_selector_size diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s b/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s new file mode 100644 index 000000000000..f30dd8f0b979 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s @@ -0,0 +1,42 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# ERR: version 6 of .debug_addr section at offset 0x0 is not supported +# ERR-NOT: {{.}} + +# CHECK: .debug_addr contents +# CHECK-NEXT: length = 0x0000000c, version = 0x0005, addr_size = 0x04, seg_size = 0x00 +# CHECK-NEXT: Addrs: [ +# CHECK-NEXT: 0x00000002 +# CHECK-NEXT: 0x00000003 +# CHECK-NEXT: ] +# CHECK-NOT: {{.}} + + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .section .debug_info,"",@progbits +.Lcu_begin0: + .long 8 # Length of Unit + .short 5 # DWARF version number + .byte 1 # DWARF unit type + .byte 4 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 6 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 + + .section .debug_addr,"",@progbits +.Ldebug_addr1: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 5 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000002 + .long 0x00000003 diff --git a/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s b/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s new file mode 100644 index 000000000000..e349f3386a6c --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s @@ -0,0 +1,42 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# ERR: .debug_addr table at offset 0x0 has version 4 which is different from the version suggested by the DWARF unit header: 5 +# ERR-NOT: {{.}} + +# CHECK: .debug_addr contents +# CHECK-NEXT: length = 0x0000000c, version = 0x0005, addr_size = 0x04, seg_size = 0x00 +# CHECK-NEXT: Addrs: [ +# CHECK-NEXT: 0x00000000 +# CHECK-NEXT: 0x00000001 +# CHECK-NEXT: ] +# CHECK-NOT: {{.}} + + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .section .debug_info,"",@progbits +.Lcu_begin0: + .long 8 # Length of Unit + .short 5 # DWARF version number + .byte 1 # DWARF unit type + .byte 4 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + + .section .debug_addr,"",@progbits +.Ldebug_addr0: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 4 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 + + .section .debug_addr,"",@progbits +.Ldebug_addr1: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 5 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 diff --git a/test/tools/llvm-mca/X86/Atom/resources-x86_32.s b/test/tools/llvm-mca/X86/Atom/resources-x86_32.s new file mode 100644 index 000000000000..f913a2f3082f --- /dev/null +++ b/test/tools/llvm-mca/X86/Atom/resources-x86_32.s @@ -0,0 +1,72 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=atom -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 13 6.50 aaa +# CHECK-NEXT: 1 7 3.50 aad +# CHECK-NEXT: 1 7 3.50 aad $7 +# CHECK-NEXT: 1 21 10.50 aam +# CHECK-NEXT: 1 21 10.50 aam $7 +# CHECK-NEXT: 1 13 6.50 aas +# CHECK-NEXT: 1 11 5.50 U bound %bx, (%eax) +# CHECK-NEXT: 1 11 5.50 U bound %ebx, (%eax) +# CHECK-NEXT: 1 18 9.00 daa +# CHECK-NEXT: 1 20 10.00 das +# CHECK-NEXT: 1 6 3.00 U into +# CHECK-NEXT: 1 2 1.00 * leave +# CHECK-NEXT: 1 1 0.50 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - AtomPort0 +# CHECK-NEXT: [1] - AtomPort1 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] +# CHECK-NEXT: 75.50 75.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] Instructions: +# CHECK-NEXT: 6.50 6.50 aaa +# CHECK-NEXT: 3.50 3.50 aad +# CHECK-NEXT: 3.50 3.50 aad $7 +# CHECK-NEXT: 10.50 10.50 aam +# CHECK-NEXT: 10.50 10.50 aam $7 +# CHECK-NEXT: 6.50 6.50 aas +# CHECK-NEXT: 5.50 5.50 bound %bx, (%eax) +# CHECK-NEXT: 5.50 5.50 bound %ebx, (%eax) +# CHECK-NEXT: 9.00 9.00 daa +# CHECK-NEXT: 10.00 10.00 das +# CHECK-NEXT: 3.00 3.00 into +# CHECK-NEXT: 1.00 1.00 leave +# CHECK-NEXT: 0.50 0.50 salc diff --git a/test/tools/llvm-mca/X86/Atom/resources-x86_64.s b/test/tools/llvm-mca/X86/Atom/resources-x86_64.s index 32823eff8471..bd8578bf8e1a 100644 --- a/test/tools/llvm-mca/X86/Atom/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/Atom/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.50 cmpq %rsi, %rdi # CHECK-NEXT: 1 1 1.00 * cmpq %rsi, (%rax) # CHECK-NEXT: 1 1 1.00 * cmpq (%rax), %rdi +# CHECK-NEXT: 1 3 1.50 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 3 1.50 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 3 1.50 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 3 1.50 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.50 decb %dil # CHECK-NEXT: 1 1 1.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.50 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.50 incq %rdi # CHECK-NEXT: 1 1 1.00 * * incq (%rax) # CHECK-NEXT: 1 2 1.00 lahf +# CHECK-NEXT: 1 2 1.00 U lodsb (%rsi), %al +# CHECK-NEXT: 1 2 1.00 U lodsw (%rsi), %ax +# CHECK-NEXT: 1 2 1.00 U lodsl (%rsi), %eax +# CHECK-NEXT: 1 2 1.00 U lodsq (%rsi), %rax +# CHECK-NEXT: 1 3 1.50 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 3 1.50 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 3 1.50 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 3 1.50 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 2 1.00 movsbw %al, %di # CHECK-NEXT: 1 2 1.00 movzbw %al, %di # CHECK-NEXT: 1 3 1.50 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 9 4.50 shrdq $7, %rsi, %rdi # CHECK-NEXT: 1 9 4.50 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 1 9 4.50 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.50 U stc +# CHECK-NEXT: 1 21 10.50 U std +# CHECK-NEXT: 1 1 0.50 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 1 1 0.50 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 1 1 0.50 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 1 1 0.50 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.50 subb $7, %al # CHECK-NEXT: 1 1 0.50 subb $7, %dil # CHECK-NEXT: 1 1 1.00 * * subb $7, (%rax) @@ -1322,7 +1363,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] -# CHECK-NEXT: 1418.00 1088.00 +# CHECK-NEXT: 1447.00 1117.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] Instructions: @@ -1517,6 +1558,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 0.50 0.50 cmpq %rsi, %rdi # CHECK-NEXT: 1.00 - cmpq %rsi, (%rax) # CHECK-NEXT: 1.00 - cmpq (%rax), %rdi +# CHECK-NEXT: 1.50 1.50 cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 1.50 1.50 cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 1.50 1.50 cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 1.50 1.50 cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 0.50 0.50 decb %dil # CHECK-NEXT: 1.00 - decb (%rax) # CHECK-NEXT: 0.50 0.50 decw %di @@ -1576,6 +1621,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 0.50 0.50 incq %rdi # CHECK-NEXT: 1.00 - incq (%rax) # CHECK-NEXT: 1.00 1.00 lahf +# CHECK-NEXT: 1.00 1.00 lodsb (%rsi), %al +# CHECK-NEXT: 1.00 1.00 lodsw (%rsi), %ax +# CHECK-NEXT: 1.00 1.00 lodsl (%rsi), %eax +# CHECK-NEXT: 1.00 1.00 lodsq (%rsi), %rax +# CHECK-NEXT: 1.50 1.50 movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 1.50 1.50 movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 1.50 1.50 movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 1.50 1.50 movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1.00 1.00 movsbw %al, %di # CHECK-NEXT: 1.00 1.00 movzbw %al, %di # CHECK-NEXT: 1.50 1.50 movsbw (%rax), %di @@ -1882,6 +1935,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 4.50 4.50 shrdq $7, %rsi, %rdi # CHECK-NEXT: 4.50 4.50 shldq $7, %rsi, (%rax) # CHECK-NEXT: 4.50 4.50 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 0.50 0.50 stc +# CHECK-NEXT: 10.50 10.50 std +# CHECK-NEXT: 0.50 0.50 stosb %al, %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 stosw %ax, %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 stosl %eax, %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 stosq %rax, %es:(%rdi) # CHECK-NEXT: 0.50 0.50 subb $7, %al # CHECK-NEXT: 0.50 0.50 subb $7, %dil # CHECK-NEXT: 1.00 - subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/Broadwell/resources-x86_32.s b/test/tools/llvm-mca/X86/Broadwell/resources-x86_32.s new file mode 100644 index 000000000000..b880fe5b8103 --- /dev/null +++ b/test/tools/llvm-mca/X86/Broadwell/resources-x86_32.s @@ -0,0 +1,80 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=broadwell -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.25 aaa +# CHECK-NEXT: 1 100 0.25 aad +# CHECK-NEXT: 1 100 0.25 aad $7 +# CHECK-NEXT: 1 100 0.25 aam +# CHECK-NEXT: 1 100 0.25 aam $7 +# CHECK-NEXT: 1 100 0.25 aas +# CHECK-NEXT: 1 100 0.25 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.25 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.25 daa +# CHECK-NEXT: 1 100 0.25 das +# CHECK-NEXT: 1 100 0.25 U into +# CHECK-NEXT: 3 7 0.50 * leave +# CHECK-NEXT: 1 1 0.25 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - BWDivider +# CHECK-NEXT: [1] - BWFPDivider +# CHECK-NEXT: [2] - BWPort0 +# CHECK-NEXT: [3] - BWPort1 +# CHECK-NEXT: [4] - BWPort2 +# CHECK-NEXT: [5] - BWPort3 +# CHECK-NEXT: [6] - BWPort4 +# CHECK-NEXT: [7] - BWPort5 +# CHECK-NEXT: [8] - BWPort6 +# CHECK-NEXT: [9] - BWPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 3.50 3.50 0.50 0.50 - 3.50 3.50 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aaa +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aad +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aad $7 +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aam +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aam $7 +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aas +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - bound %bx, (%eax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - bound %ebx, (%eax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - daa +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - das +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - into +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - leave +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - salc diff --git a/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s b/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s index ea6d7c6052b0..1083227070ce 100644 --- a/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 cmpq %rsi, %rdi # CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) # CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 1 100 0.25 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.25 decb %dil # CHECK-NEXT: 3 7 1.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.25 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 incq %rdi # CHECK-NEXT: 3 7 1.00 * * incq (%rax) # CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 1 100 0.25 U lodsb (%rsi), %al +# CHECK-NEXT: 1 100 0.25 U lodsw (%rsi), %ax +# CHECK-NEXT: 1 100 0.25 U lodsl (%rsi), %eax +# CHECK-NEXT: 1 100 0.25 U lodsq (%rsi), %rax +# CHECK-NEXT: 1 100 0.25 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.25 movsbw %al, %di # CHECK-NEXT: 1 1 0.25 movzbw %al, %di # CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 3 1.00 shrdq $7, %rsi, %rdi # CHECK-NEXT: 4 9 1.00 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 4 9 1.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.25 U stc +# CHECK-NEXT: 6 6 1.50 U std +# CHECK-NEXT: 3 2 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.25 subb $7, %al # CHECK-NEXT: 1 1 0.25 subb $7, %dil # CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) @@ -1330,7 +1371,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] -# CHECK-NEXT: 50.00 - 377.00 267.50 218.00 218.00 167.00 161.00 343.50 69.00 +# CHECK-NEXT: 50.00 - 382.50 273.00 219.33 219.33 171.00 166.50 350.00 70.33 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: @@ -1525,6 +1566,10 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpq %rsi, %rdi # CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - cmpq %rsi, (%rax) # CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - cmpq (%rax), %rdi +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - decb %dil # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 decb (%rax) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - decw %di @@ -1584,6 +1629,14 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - incq %rdi # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 incq (%rax) # CHECK-NEXT: - - 0.50 - - - - - 0.50 - lahf +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsb (%rsi), %al +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsw (%rsi), %ax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsl (%rsi), %eax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsq (%rsi), %rax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsq (%rsi), %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsbw %al, %di # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movzbw %al, %di # CHECK-NEXT: - - - - 0.50 0.50 - - - - movsbw (%rax), %di @@ -1890,6 +1943,12 @@ xorq (%rax), %rdi # CHECK-NEXT: - - - 1.00 - - - - - - shrdq $7, %rsi, %rdi # CHECK-NEXT: - - 0.25 1.25 0.83 0.83 - 0.25 0.25 0.33 shldq $7, %rsi, (%rax) # CHECK-NEXT: - - 0.25 1.25 0.83 0.83 - 0.25 0.25 0.33 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - stc +# CHECK-NEXT: - - 1.25 1.25 - - - 1.25 2.25 - std +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosb %al, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosq %rax, %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - subb $7, %al # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - subb $7, %dil # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-cmp.s b/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-cmp.s index bc5ceb5b72e7..001fb8ed6612 100644 --- a/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-cmp.s +++ b/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-cmp.s @@ -11,9 +11,9 @@ cmovae %ebx, %eax # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 3000 -# CHECK-NEXT: Total Cycles: 3003 +# CHECK-NEXT: Total Cycles: 1504 # CHECK-NEXT: Dispatch Width: 2 -# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: IPC: 1.99 # CHECK-NEXT: Block RThroughput: 1.0 # CHECK: Instruction Info: @@ -54,14 +54,14 @@ cmovae %ebx, %eax # CHECK-NEXT: 1.00 - - - - - - - - - - - - - cmovael %ebx, %eax # CHECK: Timeline view: -# CHECK-NEXT: Index 012345678 +# CHECK-NEXT: Index 0123456 -# CHECK: [0,0] DeER . . cmpl %eax, %eax -# CHECK-NEXT: [0,1] D=eER. . cmovael %ebx, %eax -# CHECK-NEXT: [1,0] .D=eER . cmpl %eax, %eax -# CHECK-NEXT: [1,1] .D==eER . cmovael %ebx, %eax -# CHECK-NEXT: [2,0] . D==eER. cmpl %eax, %eax -# CHECK-NEXT: [2,1] . D===eER cmovael %ebx, %eax +# CHECK: [0,0] DeER .. cmpl %eax, %eax +# CHECK-NEXT: [0,1] D=eER.. cmovael %ebx, %eax +# CHECK-NEXT: [1,0] .DeER.. cmpl %eax, %eax +# CHECK-NEXT: [1,1] .D=eER. cmovael %ebx, %eax +# CHECK-NEXT: [2,0] . DeER. cmpl %eax, %eax +# CHECK-NEXT: [2,1] . D=eER cmovael %ebx, %eax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -70,5 +70,5 @@ cmovae %ebx, %eax # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 2.0 0.3 0.0 cmpl %eax, %eax -# CHECK-NEXT: 1. 3 3.0 0.0 0.0 cmovael %ebx, %eax +# CHECK-NEXT: 0. 3 1.0 1.0 0.0 cmpl %eax, %eax +# CHECK-NEXT: 1. 3 2.0 0.0 0.0 cmovael %ebx, %eax diff --git a/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-pcmpeq.s b/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-pcmpeq.s index 97bf501e577a..04007f24e42b 100644 --- a/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-pcmpeq.s +++ b/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-pcmpeq.s @@ -14,9 +14,9 @@ vpcmpeqq %xmm3, %xmm3, %xmm0 # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 6000 -# CHECK-NEXT: Total Cycles: 6003 +# CHECK-NEXT: Total Cycles: 3003 # CHECK-NEXT: Dispatch Width: 2 -# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: IPC: 2.00 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -61,21 +61,20 @@ vpcmpeqq %xmm3, %xmm3, %xmm0 # CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - - vpcmpeqq %xmm3, %xmm3, %xmm0 # CHECK: Timeline view: -# CHECK-NEXT: 01234 -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: Index 012345678 -# CHECK: [0,0] DeER . . . vpcmpeqb %xmm0, %xmm0, %xmm1 -# CHECK-NEXT: [0,1] D=eER. . . vpcmpeqw %xmm1, %xmm1, %xmm2 -# CHECK-NEXT: [0,2] .D=eER . . vpcmpeqd %xmm2, %xmm2, %xmm3 -# CHECK-NEXT: [0,3] .D==eER . . vpcmpeqq %xmm3, %xmm3, %xmm0 -# CHECK-NEXT: [1,0] . D==eER . . vpcmpeqb %xmm0, %xmm0, %xmm1 -# CHECK-NEXT: [1,1] . D===eER . . vpcmpeqw %xmm1, %xmm1, %xmm2 -# CHECK-NEXT: [1,2] . D===eER. . vpcmpeqd %xmm2, %xmm2, %xmm3 -# CHECK-NEXT: [1,3] . D====eER . vpcmpeqq %xmm3, %xmm3, %xmm0 -# CHECK-NEXT: [2,0] . D====eER . vpcmpeqb %xmm0, %xmm0, %xmm1 -# CHECK-NEXT: [2,1] . D=====eER . vpcmpeqw %xmm1, %xmm1, %xmm2 -# CHECK-NEXT: [2,2] . D=====eER. vpcmpeqd %xmm2, %xmm2, %xmm3 -# CHECK-NEXT: [2,3] . D======eER vpcmpeqq %xmm3, %xmm3, %xmm0 +# CHECK: [0,0] DeER . . vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [0,1] DeER . . vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [0,2] .DeER. . vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [0,3] .DeER. . vpcmpeqq %xmm3, %xmm3, %xmm0 +# CHECK-NEXT: [1,0] . DeER . vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [1,1] . DeER . vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [1,2] . DeER . vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [1,3] . DeER . vpcmpeqq %xmm3, %xmm3, %xmm0 +# CHECK-NEXT: [2,0] . DeER. vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [2,1] . DeER. vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [2,2] . DeER vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [2,3] . DeER vpcmpeqq %xmm3, %xmm3, %xmm0 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -84,7 +83,7 @@ vpcmpeqq %xmm3, %xmm3, %xmm0 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 3.0 0.3 0.0 vpcmpeqb %xmm0, %xmm0, %xmm1 -# CHECK-NEXT: 1. 3 4.0 0.0 0.0 vpcmpeqw %xmm1, %xmm1, %xmm2 -# CHECK-NEXT: 2. 3 4.0 0.0 0.0 vpcmpeqd %xmm2, %xmm2, %xmm3 -# CHECK-NEXT: 3. 3 5.0 0.0 0.0 vpcmpeqq %xmm3, %xmm3, %xmm0 +# CHECK-NEXT: 0. 3 1.0 1.0 0.0 vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1. 3 1.0 1.0 0.0 vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: 2. 3 1.0 1.0 0.0 vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: 3. 3 1.0 1.0 0.0 vpcmpeqq %xmm3, %xmm3, %xmm0 diff --git a/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s b/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s index 00b88954e489..da94624fd551 100644 --- a/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s +++ b/test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s @@ -13,9 +13,9 @@ sbb %eax, %eax # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 4500 -# CHECK-NEXT: Total Cycles: 6745 +# CHECK-NEXT: Total Cycles: 3007 # CHECK-NEXT: Dispatch Width: 2 -# CHECK-NEXT: IPC: 0.67 +# CHECK-NEXT: IPC: 1.50 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -49,27 +49,27 @@ sbb %eax, %eax # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] -# CHECK-NEXT: 2.01 1.99 - - - - - - 1.00 - - - - - +# CHECK-NEXT: 2.00 2.00 - - - - - - 1.00 - - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: # CHECK-NEXT: - 1.00 - - - - - - 1.00 - - - - - imull %edx, %eax -# CHECK-NEXT: 0.99 0.01 - - - - - - - - - - - - addl %edx, %edx -# CHECK-NEXT: 1.01 0.99 - - - - - - - - - - - - sbbl %eax, %eax +# CHECK-NEXT: - 1.00 - - - - - - - - - - - - addl %edx, %edx +# CHECK-NEXT: 2.00 - - - - - - - - - - - - - sbbl %eax, %eax # CHECK: Timeline view: -# CHECK-NEXT: 012345 +# CHECK-NEXT: 01 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeER . . imull %edx, %eax -# CHECK-NEXT: [0,1] .DeE-R . . addl %edx, %edx -# CHECK-NEXT: [0,2] .D==eER . . sbbl %eax, %eax -# CHECK-NEXT: [1,0] . D===eeeER . imull %edx, %eax -# CHECK-NEXT: [1,1] . DeE----R . addl %edx, %edx -# CHECK-NEXT: [1,2] . D=====eER . sbbl %eax, %eax -# CHECK-NEXT: [2,0] . D=====eeeER. imull %edx, %eax -# CHECK-NEXT: [2,1] . DeE------R. addl %edx, %edx -# CHECK-NEXT: [2,2] . D=======eER sbbl %eax, %eax +# CHECK: [0,0] DeeeER .. imull %edx, %eax +# CHECK-NEXT: [0,1] .DeE-R .. addl %edx, %edx +# CHECK-NEXT: [0,2] .D=eE-R .. sbbl %eax, %eax +# CHECK-NEXT: [1,0] . D==eeeER.. imull %edx, %eax +# CHECK-NEXT: [1,1] . DeE---R.. addl %edx, %edx +# CHECK-NEXT: [1,2] . D=eE---R. sbbl %eax, %eax +# CHECK-NEXT: [2,0] . D=eeeER. imull %edx, %eax +# CHECK-NEXT: [2,1] . D=eE--R addl %edx, %edx +# CHECK-NEXT: [2,2] . D==eE-R sbbl %eax, %eax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -78,6 +78,6 @@ sbb %eax, %eax # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 3.7 0.7 0.0 imull %edx, %eax -# CHECK-NEXT: 1. 3 1.0 1.0 3.7 addl %edx, %edx -# CHECK-NEXT: 2. 3 5.7 0.0 0.0 sbbl %eax, %eax +# CHECK-NEXT: 0. 3 2.0 0.7 0.0 imull %edx, %eax +# CHECK-NEXT: 1. 3 1.3 1.3 2.0 addl %edx, %edx +# CHECK-NEXT: 2. 3 2.3 0.0 1.7 sbbl %eax, %eax diff --git a/test/tools/llvm-mca/X86/BtVer2/one-idioms.s b/test/tools/llvm-mca/X86/BtVer2/one-idioms.s index 3beaf829c1a4..3c20002d9c8c 100644 --- a/test/tools/llvm-mca/X86/BtVer2/one-idioms.s +++ b/test/tools/llvm-mca/X86/BtVer2/one-idioms.s @@ -1,9 +1,11 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -timeline -register-file-stats -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -timeline -timeline-max-iterations=1 -register-file-stats < %s | FileCheck %s # These are dependency-breaking one-idioms. # Much like zero-idioms, but they produce ones, and do consume resources. +# perf stats reports a throughput of 2.00 IPC. + pcmpeqb %mm2, %mm2 pcmpeqd %mm2, %mm2 pcmpeqw %mm2, %mm2 @@ -25,11 +27,11 @@ vpcmpeqw %xmm3, %xmm3, %xmm5 # FIXME: their handling is broken in llvm-mca. -# CHECK: Iterations: 1 -# CHECK-NEXT: Instructions: 15 -# CHECK-NEXT: Total Cycles: 12 +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 1500 +# CHECK-NEXT: Total Cycles: 753 # CHECK-NEXT: Dispatch Width: 2 -# CHECK-NEXT: IPC: 1.25 +# CHECK-NEXT: IPC: 1.99 # CHECK-NEXT: Block RThroughput: 7.5 # CHECK: Instruction Info: @@ -58,13 +60,13 @@ vpcmpeqw %xmm3, %xmm3, %xmm5 # CHECK-NEXT: 1 1 0.50 vpcmpeqw %xmm3, %xmm3, %xmm5 # CHECK: Register File statistics: -# CHECK-NEXT: Total number of mappings created: 15 -# CHECK-NEXT: Max number of mappings used: 8 +# CHECK-NEXT: Total number of mappings created: 1500 +# CHECK-NEXT: Max number of mappings used: 6 # CHECK: * Register File #1 -- JFpuPRF: # CHECK-NEXT: Number of physical registers: 72 -# CHECK-NEXT: Total number of mappings created: 15 -# CHECK-NEXT: Max number of mappings used: 8 +# CHECK-NEXT: Total number of mappings created: 1500 +# CHECK-NEXT: Max number of mappings used: 6 # CHECK: * Register File #2 -- JIntegerPRF: # CHECK-NEXT: Number of physical registers: 64 @@ -89,45 +91,45 @@ vpcmpeqw %xmm3, %xmm3, %xmm5 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] -# CHECK-NEXT: - - - - - 7.00 8.00 - - - - 7.00 8.00 - +# CHECK-NEXT: - - - - - 7.50 7.50 - - - - 7.50 7.50 - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: -# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 - pcmpeqb %mm2, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - - pcmpeqd %mm2, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - - pcmpeqw %mm2, %mm2 -# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 - pcmpeqb %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 - pcmpeqd %xmm2, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - - pcmpeqq %xmm2, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - - pcmpeqw %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 - vpcmpeqb %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 - vpcmpeqd %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - - vpcmpeqq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 - vpcmpeqw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - - vpcmpeqb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 - vpcmpeqd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - - vpcmpeqq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 - vpcmpeqw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pcmpeqb %mm2, %mm2 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pcmpeqd %mm2, %mm2 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pcmpeqw %mm2, %mm2 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vpcmpeqb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vpcmpeqd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vpcmpeqq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vpcmpeqw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vpcmpeqb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vpcmpeqd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vpcmpeqq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - 0.50 0.50 - - - - 0.50 0.50 - vpcmpeqw %xmm3, %xmm3, %xmm5 # CHECK: Timeline view: -# CHECK-NEXT: 01 +# CHECK-NEXT: 0 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER . .. pcmpeqb %mm2, %mm2 -# CHECK-NEXT: [0,1] D=eER. .. pcmpeqd %mm2, %mm2 -# CHECK-NEXT: [0,2] .D=eER .. pcmpeqw %mm2, %mm2 -# CHECK-NEXT: [0,3] .DeE-R .. pcmpeqb %xmm2, %xmm2 -# CHECK-NEXT: [0,4] . DeE-R .. pcmpeqd %xmm2, %xmm2 -# CHECK-NEXT: [0,5] . D=eER .. pcmpeqq %xmm2, %xmm2 -# CHECK-NEXT: [0,6] . D=eER .. pcmpeqw %xmm2, %xmm2 -# CHECK-NEXT: [0,7] . DeE-R .. vpcmpeqb %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,8] . DeE-R .. vpcmpeqd %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,9] . D=eER .. vpcmpeqq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,10] . D=eER.. vpcmpeqw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: [0,11] . D==eER. vpcmpeqb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,12] . .D=eER. vpcmpeqd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,13] . .D==eER vpcmpeqq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: [0,14] . . D=eER vpcmpeqw %xmm3, %xmm3, %xmm5 +# CHECK: [0,0] DeER . . pcmpeqb %mm2, %mm2 +# CHECK-NEXT: [0,1] DeER . . pcmpeqd %mm2, %mm2 +# CHECK-NEXT: [0,2] .DeER. . pcmpeqw %mm2, %mm2 +# CHECK-NEXT: [0,3] .DeER. . pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: [0,4] . DeER . pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: [0,5] . DeER . pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: [0,6] . DeER . pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: [0,7] . DeER . vpcmpeqb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,8] . DeER . vpcmpeqd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,9] . DeER . vpcmpeqq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,10] . DeER . vpcmpeqw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,11] . DeER . vpcmpeqb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,12] . .DeER. vpcmpeqd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,13] . .DeER. vpcmpeqq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,14] . . DeER vpcmpeqw %xmm3, %xmm3, %xmm5 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -137,17 +139,17 @@ vpcmpeqw %xmm3, %xmm3, %xmm5 # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 pcmpeqb %mm2, %mm2 -# CHECK-NEXT: 1. 1 2.0 0.0 0.0 pcmpeqd %mm2, %mm2 -# CHECK-NEXT: 2. 1 2.0 0.0 0.0 pcmpeqw %mm2, %mm2 -# CHECK-NEXT: 3. 1 1.0 1.0 1.0 pcmpeqb %xmm2, %xmm2 -# CHECK-NEXT: 4. 1 1.0 0.0 1.0 pcmpeqd %xmm2, %xmm2 -# CHECK-NEXT: 5. 1 2.0 0.0 0.0 pcmpeqq %xmm2, %xmm2 -# CHECK-NEXT: 6. 1 2.0 0.0 0.0 pcmpeqw %xmm2, %xmm2 -# CHECK-NEXT: 7. 1 1.0 1.0 1.0 vpcmpeqb %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 8. 1 1.0 0.0 1.0 vpcmpeqd %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 9. 1 2.0 0.0 0.0 vpcmpeqq %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 10. 1 2.0 0.0 0.0 vpcmpeqw %xmm3, %xmm3, %xmm3 -# CHECK-NEXT: 11. 1 3.0 0.0 0.0 vpcmpeqb %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 12. 1 2.0 0.0 0.0 vpcmpeqd %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 13. 1 3.0 1.0 0.0 vpcmpeqq %xmm3, %xmm3, %xmm5 -# CHECK-NEXT: 14. 1 2.0 1.0 0.0 vpcmpeqw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1. 1 1.0 1.0 0.0 pcmpeqd %mm2, %mm2 +# CHECK-NEXT: 2. 1 1.0 1.0 0.0 pcmpeqw %mm2, %mm2 +# CHECK-NEXT: 3. 1 1.0 1.0 0.0 pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: 4. 1 1.0 1.0 0.0 pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: 5. 1 1.0 1.0 0.0 pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: 6. 1 1.0 1.0 0.0 pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: 7. 1 1.0 1.0 0.0 vpcmpeqb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 8. 1 1.0 1.0 0.0 vpcmpeqd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 9. 1 1.0 1.0 0.0 vpcmpeqq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 10. 1 1.0 1.0 0.0 vpcmpeqw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 11. 1 1.0 1.0 0.0 vpcmpeqb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 12. 1 1.0 1.0 0.0 vpcmpeqd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 13. 1 1.0 1.0 0.0 vpcmpeqq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 14. 1 1.0 1.0 0.0 vpcmpeqw %xmm3, %xmm3, %xmm5 diff --git a/test/tools/llvm-mca/X86/BtVer2/resources-x86_32.s b/test/tools/llvm-mca/X86/BtVer2/resources-x86_32.s new file mode 100644 index 000000000000..5556e78a0155 --- /dev/null +++ b/test/tools/llvm-mca/X86/BtVer2/resources-x86_32.s @@ -0,0 +1,84 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=btver2 -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.50 aaa +# CHECK-NEXT: 1 100 0.50 aad +# CHECK-NEXT: 1 100 0.50 aad $7 +# CHECK-NEXT: 1 100 0.50 aam +# CHECK-NEXT: 1 100 0.50 aam $7 +# CHECK-NEXT: 1 100 0.50 aas +# CHECK-NEXT: 1 100 0.50 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.50 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.50 daa +# CHECK-NEXT: 1 100 0.50 das +# CHECK-NEXT: 1 100 0.50 U into +# CHECK-NEXT: 1 1 0.50 * leave +# CHECK-NEXT: 1 1 0.50 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - JALU0 +# CHECK-NEXT: [1] - JALU1 +# CHECK-NEXT: [2] - JDiv +# CHECK-NEXT: [3] - JFPA +# CHECK-NEXT: [4] - JFPM +# CHECK-NEXT: [5] - JFPU0 +# CHECK-NEXT: [6] - JFPU1 +# CHECK-NEXT: [7] - JLAGU +# CHECK-NEXT: [8] - JMul +# CHECK-NEXT: [9] - JSAGU +# CHECK-NEXT: [10] - JSTC +# CHECK-NEXT: [11] - JVALU0 +# CHECK-NEXT: [12] - JVALU1 +# CHECK-NEXT: [13] - JVIMUL + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] +# CHECK-NEXT: 6.50 6.50 - - - - - - - - - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - aaa +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - aad +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - aad $7 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - aam +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - aam $7 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - aas +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bound %bx, (%eax) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bound %ebx, (%eax) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - daa +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - das +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - into +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - leave +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - salc diff --git a/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s b/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s index 8a99598a5762..c5ffa6ced328 100644 --- a/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.50 cmpq %rsi, %rdi # CHECK-NEXT: 1 4 1.00 * cmpq %rsi, (%rax) # CHECK-NEXT: 1 4 1.00 * cmpq (%rax), %rdi +# CHECK-NEXT: 1 100 0.50 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.50 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.50 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.50 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.50 decb %dil # CHECK-NEXT: 2 5 1.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.50 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.50 incq %rdi # CHECK-NEXT: 2 5 1.00 * * incq (%rax) # CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 1 100 0.50 U lodsb (%rsi), %al +# CHECK-NEXT: 1 100 0.50 U lodsw (%rsi), %ax +# CHECK-NEXT: 1 100 0.50 U lodsl (%rsi), %eax +# CHECK-NEXT: 1 100 0.50 U lodsq (%rsi), %rax +# CHECK-NEXT: 1 100 0.50 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.50 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.50 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.50 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.50 movsbw %al, %di # CHECK-NEXT: 1 1 0.50 movzbw %al, %di # CHECK-NEXT: 1 4 1.00 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 6 3 3.00 shrdq $7, %rsi, %rdi # CHECK-NEXT: 8 9 11.00 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 8 9 11.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.50 U stc +# CHECK-NEXT: 1 1 0.50 U std +# CHECK-NEXT: 1 100 0.50 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 1 100 0.50 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 1 100 0.50 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 1 100 0.50 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.50 subb $7, %al # CHECK-NEXT: 1 1 0.50 subb $7, %dil # CHECK-NEXT: 2 5 1.00 * * subb $7, (%rax) @@ -1334,7 +1375,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] -# CHECK-NEXT: 493.00 543.00 380.00 - - - - 295.00 64.00 195.00 - - - - +# CHECK-NEXT: 502.00 552.00 380.00 - - - - 295.00 64.00 195.00 - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: @@ -1529,6 +1570,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - cmpq %rsi, %rdi # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - cmpq %rsi, (%rax) # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - cmpq (%rax), %rdi +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - decb %dil # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - 1.00 - - - - decb (%rax) # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - decw %di @@ -1588,6 +1633,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - incq %rdi # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - 1.00 - - - - incq (%rax) # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - lahf +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - lodsb (%rsi), %al +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - lodsw (%rsi), %ax +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - lodsl (%rsi), %eax +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - lodsq (%rsi), %rax +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movsbw %al, %di # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movzbw %al, %di # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - movsbw (%rax), %di @@ -1894,6 +1947,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 3.00 3.00 - - - - - - - - - - - - shrdq $7, %rsi, %rdi # CHECK-NEXT: 11.00 11.00 - - - - - 1.00 - - - - - - shldq $7, %rsi, (%rax) # CHECK-NEXT: 11.00 11.00 - - - - - 1.00 - - - - - - shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - stc +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - std +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - stosb %al, %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - stosw %ax, %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - stosl %eax, %es:(%rdi) +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - stosq %rax, %es:(%rdi) # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - subb $7, %al # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - subb $7, %dil # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - 1.00 - - - - subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/Generic/resources-x86_32.s b/test/tools/llvm-mca/X86/Generic/resources-x86_32.s new file mode 100644 index 000000000000..b4672620cf43 --- /dev/null +++ b/test/tools/llvm-mca/X86/Generic/resources-x86_32.s @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.33 aaa +# CHECK-NEXT: 1 100 0.33 aad +# CHECK-NEXT: 1 100 0.33 aad $7 +# CHECK-NEXT: 1 100 0.33 aam +# CHECK-NEXT: 1 100 0.33 aam $7 +# CHECK-NEXT: 1 100 0.33 aas +# CHECK-NEXT: 1 100 0.33 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.33 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.33 daa +# CHECK-NEXT: 1 100 0.33 das +# CHECK-NEXT: 1 100 0.33 U into +# CHECK-NEXT: 3 7 0.67 * leave +# CHECK-NEXT: 1 1 0.33 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 4.67 4.67 - 4.67 0.50 0.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aaa +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aas +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %bx, (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %ebx, (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - daa +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - das +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - into +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 leave +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - salc diff --git a/test/tools/llvm-mca/X86/Generic/resources-x86_64.s b/test/tools/llvm-mca/X86/Generic/resources-x86_64.s index e27b322fa9b1..c04a56673db9 100644 --- a/test/tools/llvm-mca/X86/Generic/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/Generic/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.33 cmpq %rsi, %rdi # CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) # CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 5 8 1.00 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.33 decb %dil # CHECK-NEXT: 3 7 1.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.33 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.33 incq %rdi # CHECK-NEXT: 3 7 1.00 * * incq (%rax) # CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 3 7 0.67 U lodsb (%rsi), %al +# CHECK-NEXT: 3 7 0.67 U lodsw (%rsi), %ax +# CHECK-NEXT: 2 6 0.50 U lodsl (%rsi), %eax +# CHECK-NEXT: 2 6 0.50 U lodsq (%rsi), %rax +# CHECK-NEXT: 5 8 1.00 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.33 movsbw %al, %di # CHECK-NEXT: 1 1 0.33 movzbw %al, %di # CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 2 2 0.67 shrdq $7, %rsi, %rdi # CHECK-NEXT: 5 8 1.00 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 5 8 1.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.33 U stc +# CHECK-NEXT: 1 1 0.33 U std +# CHECK-NEXT: 3 5 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.33 subb $7, %al # CHECK-NEXT: 1 1 0.33 subb $7, %dil # CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) @@ -1328,7 +1369,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: 160.00 - 365.50 171.00 210.00 356.50 254.00 254.00 +# CHECK-NEXT: 160.00 - 376.17 181.67 218.00 367.17 266.00 266.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: @@ -1523,6 +1564,10 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq %rsi, %rdi # CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq %rsi, (%rax) # CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq (%rax), %rdi +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decw %di @@ -1582,6 +1627,14 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incq %rdi # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incq (%rax) # CHECK-NEXT: - - 0.50 - - 0.50 - - lahf +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsb (%rsi), %al +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsw (%rsi), %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsl (%rsi), %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsq (%rsi), %rax +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsq (%rsi), %es:(%rdi) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbw %al, %di # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbw %al, %di # CHECK-NEXT: - - - - - - 0.50 0.50 movsbw (%rax), %di @@ -1888,6 +1941,12 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdq $7, %rsi, %rdi # CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldq $7, %rsi, (%rax) # CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - stc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - std +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosb %al, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosq %rax, %es:(%rdi) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %al # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %dil # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/Haswell/resources-x86_32.s b/test/tools/llvm-mca/X86/Haswell/resources-x86_32.s new file mode 100644 index 000000000000..2a2db69888ce --- /dev/null +++ b/test/tools/llvm-mca/X86/Haswell/resources-x86_32.s @@ -0,0 +1,80 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=haswell -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.25 aaa +# CHECK-NEXT: 1 100 0.25 aad +# CHECK-NEXT: 1 100 0.25 aad $7 +# CHECK-NEXT: 1 100 0.25 aam +# CHECK-NEXT: 1 100 0.25 aam $7 +# CHECK-NEXT: 1 100 0.25 aas +# CHECK-NEXT: 15 1 3.75 U bound %bx, (%eax) +# CHECK-NEXT: 15 1 3.75 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.25 daa +# CHECK-NEXT: 1 100 0.25 das +# CHECK-NEXT: 4 1 1.00 U into +# CHECK-NEXT: 3 7 0.50 * leave +# CHECK-NEXT: 1 1 0.25 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - HWDivider +# CHECK-NEXT: [1] - HWFPDivider +# CHECK-NEXT: [2] - HWPort0 +# CHECK-NEXT: [3] - HWPort1 +# CHECK-NEXT: [4] - HWPort2 +# CHECK-NEXT: [5] - HWPort3 +# CHECK-NEXT: [6] - HWPort4 +# CHECK-NEXT: [7] - HWPort5 +# CHECK-NEXT: [8] - HWPort6 +# CHECK-NEXT: [9] - HWPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 2.75 2.75 0.50 0.50 - 2.75 2.75 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aaa +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aad +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aad $7 +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aam +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aam $7 +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aas +# CHECK-NEXT: - - - - - - - - - - bound %bx, (%eax) +# CHECK-NEXT: - - - - - - - - - - bound %ebx, (%eax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - daa +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - das +# CHECK-NEXT: - - - - - - - - - - into +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - leave +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - salc diff --git a/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s b/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s index 7a48e799abc2..9d6083a6c853 100644 --- a/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 cmpq %rsi, %rdi # CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) # CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 5 4 1.00 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 4 1.00 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 4 1.00 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 4 1.00 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.25 decb %dil # CHECK-NEXT: 3 7 1.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.25 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 incq %rdi # CHECK-NEXT: 3 7 1.00 * * incq (%rax) # CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 3 1 0.50 U lodsb (%rsi), %al +# CHECK-NEXT: 3 1 0.50 U lodsw (%rsi), %ax +# CHECK-NEXT: 2 1 0.50 U lodsl (%rsi), %eax +# CHECK-NEXT: 2 1 0.50 U lodsq (%rsi), %rax +# CHECK-NEXT: 5 4 1.00 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 4 1.00 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 4 1.00 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 4 1.00 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.25 movsbw %al, %di # CHECK-NEXT: 1 1 0.25 movzbw %al, %di # CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 3 1.00 shrdq $7, %rsi, %rdi # CHECK-NEXT: 4 10 1.00 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 4 10 1.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.25 U stc +# CHECK-NEXT: 6 6 1.50 U std +# CHECK-NEXT: 3 2 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.25 subb $7, %al # CHECK-NEXT: 1 1 0.25 subb $7, %dil # CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) @@ -1330,7 +1371,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] -# CHECK-NEXT: 80.00 - 428.00 288.50 209.00 209.00 158.00 184.00 423.50 66.00 +# CHECK-NEXT: 80.00 - 437.00 297.50 220.33 220.33 166.00 193.00 433.50 67.33 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: @@ -1525,6 +1566,10 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpq %rsi, %rdi # CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - cmpq %rsi, (%rax) # CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - cmpq (%rax), %rdi +# CHECK-NEXT: - - 0.75 0.75 1.00 1.00 - 0.75 0.75 - cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.75 0.75 1.00 1.00 - 0.75 0.75 - cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.75 0.75 1.00 1.00 - 0.75 0.75 - cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.75 0.75 1.00 1.00 - 0.75 0.75 - cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - decb %dil # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 decb (%rax) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - decw %di @@ -1584,6 +1629,14 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - incq %rdi # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 incq (%rax) # CHECK-NEXT: - - 0.50 - - - - - 0.50 - lahf +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - lodsb (%rsi), %al +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - lodsw (%rsi), %ax +# CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - lodsl (%rsi), %eax +# CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - lodsq (%rsi), %rax +# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 1.00 0.50 0.50 - movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 1.00 0.50 0.50 - movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 1.00 0.50 0.50 - movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 1.00 0.50 0.50 - movsq (%rsi), %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsbw %al, %di # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movzbw %al, %di # CHECK-NEXT: - - - - 0.50 0.50 - - - - movsbw (%rax), %di @@ -1890,6 +1943,12 @@ xorq (%rax), %rdi # CHECK-NEXT: - - - 1.00 - - - - - - shrdq $7, %rsi, %rdi # CHECK-NEXT: - - 0.25 1.25 0.83 0.83 - 0.25 0.25 0.33 shldq $7, %rsi, (%rax) # CHECK-NEXT: - - 0.25 1.25 0.83 0.83 - 0.25 0.25 0.33 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - stc +# CHECK-NEXT: - - 1.25 1.25 - - - 1.25 2.25 - std +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosb %al, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosq %rax, %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - subb $7, %al # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - subb $7, %dil # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/SLM/resources-x86_32.s b/test/tools/llvm-mca/X86/SLM/resources-x86_32.s new file mode 100644 index 000000000000..bc194ed6237b --- /dev/null +++ b/test/tools/llvm-mca/X86/SLM/resources-x86_32.s @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=slm -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 1.00 aaa +# CHECK-NEXT: 1 100 1.00 aad +# CHECK-NEXT: 1 100 1.00 aad $7 +# CHECK-NEXT: 1 100 1.00 aam +# CHECK-NEXT: 1 100 1.00 aam $7 +# CHECK-NEXT: 1 100 1.00 aas +# CHECK-NEXT: 1 100 1.00 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 1.00 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 1.00 daa +# CHECK-NEXT: 1 100 1.00 das +# CHECK-NEXT: 1 100 1.00 U into +# CHECK-NEXT: 1 1 0.50 * leave +# CHECK-NEXT: 1 1 0.50 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - SLMDivider +# CHECK-NEXT: [1] - SLMFPDivider +# CHECK-NEXT: [2] - SLMFPMultiplier +# CHECK-NEXT: [3] - SLM_FPC_RSV0 +# CHECK-NEXT: [4] - SLM_FPC_RSV1 +# CHECK-NEXT: [5] - SLM_IEC_RSV0 +# CHECK-NEXT: [6] - SLM_IEC_RSV1 +# CHECK-NEXT: [7] - SLM_MEC_RSV + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] +# CHECK-NEXT: - - - 11.00 - 1.00 1.00 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - aaa +# CHECK-NEXT: - - - 1.00 - - - - aad +# CHECK-NEXT: - - - 1.00 - - - - aad $7 +# CHECK-NEXT: - - - 1.00 - - - - aam +# CHECK-NEXT: - - - 1.00 - - - - aam $7 +# CHECK-NEXT: - - - 1.00 - - - - aas +# CHECK-NEXT: - - - 1.00 - - - - bound %bx, (%eax) +# CHECK-NEXT: - - - 1.00 - - - - bound %ebx, (%eax) +# CHECK-NEXT: - - - 1.00 - - - - daa +# CHECK-NEXT: - - - 1.00 - - - - das +# CHECK-NEXT: - - - 1.00 - - - - into +# CHECK-NEXT: - - - - - 0.50 0.50 - leave +# CHECK-NEXT: - - - - - 0.50 0.50 - salc diff --git a/test/tools/llvm-mca/X86/SLM/resources-x86_64.s b/test/tools/llvm-mca/X86/SLM/resources-x86_64.s index 0c50dd08bc23..c272cf69004f 100644 --- a/test/tools/llvm-mca/X86/SLM/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/SLM/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.50 cmpq %rsi, %rdi # CHECK-NEXT: 1 4 1.00 * cmpq %rsi, (%rax) # CHECK-NEXT: 1 4 1.00 * cmpq (%rax), %rdi +# CHECK-NEXT: 1 100 1.00 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 1.00 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 1.00 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 1.00 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.50 decb %dil # CHECK-NEXT: 2 5 2.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.50 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.50 incq %rdi # CHECK-NEXT: 2 5 2.00 * * incq (%rax) # CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 1 100 1.00 U lodsb (%rsi), %al +# CHECK-NEXT: 1 100 1.00 U lodsw (%rsi), %ax +# CHECK-NEXT: 1 100 1.00 U lodsl (%rsi), %eax +# CHECK-NEXT: 1 100 1.00 U lodsq (%rsi), %rax +# CHECK-NEXT: 1 100 1.00 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 1.00 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 1.00 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 1.00 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.50 movsbw %al, %di # CHECK-NEXT: 1 1 0.50 movzbw %al, %di # CHECK-NEXT: 1 4 1.00 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 1.00 shrdq $7, %rsi, %rdi # CHECK-NEXT: 2 4 2.00 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 2 4 2.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.50 U stc +# CHECK-NEXT: 1 1 0.50 U std +# CHECK-NEXT: 1 100 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 1 100 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 1 100 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 1 100 1.00 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.50 subb $7, %al # CHECK-NEXT: 1 1 0.50 subb $7, %dil # CHECK-NEXT: 2 5 2.00 * * subb $7, (%rax) @@ -1328,7 +1369,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: 400.00 - - - - 544.00 386.00 502.00 +# CHECK-NEXT: 400.00 - - 16.00 - 545.00 387.00 502.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: @@ -1523,6 +1564,10 @@ xorq (%rax), %rdi # CHECK-NEXT: - - - - - 0.50 0.50 - cmpq %rsi, %rdi # CHECK-NEXT: - - - - - 0.50 0.50 1.00 cmpq %rsi, (%rax) # CHECK-NEXT: - - - - - 0.50 0.50 1.00 cmpq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - 1.00 - - - - cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - 1.00 - - - - cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - 1.00 - - - - cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - - - - 0.50 0.50 - decb %dil # CHECK-NEXT: - - - - - 1.00 1.00 2.00 decb (%rax) # CHECK-NEXT: - - - - - 0.50 0.50 - decw %di @@ -1582,6 +1627,14 @@ xorq (%rax), %rdi # CHECK-NEXT: - - - - - 0.50 0.50 - incq %rdi # CHECK-NEXT: - - - - - 1.00 1.00 2.00 incq (%rax) # CHECK-NEXT: - - - - - 0.50 0.50 - lahf +# CHECK-NEXT: - - - 1.00 - - - - lodsb (%rsi), %al +# CHECK-NEXT: - - - 1.00 - - - - lodsw (%rsi), %ax +# CHECK-NEXT: - - - 1.00 - - - - lodsl (%rsi), %eax +# CHECK-NEXT: - - - 1.00 - - - - lodsq (%rsi), %rax +# CHECK-NEXT: - - - 1.00 - - - - movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - 1.00 - - - - movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - 1.00 - - - - movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - 1.00 - - - - movsq (%rsi), %es:(%rdi) # CHECK-NEXT: - - - - - 0.50 0.50 - movsbw %al, %di # CHECK-NEXT: - - - - - 0.50 0.50 - movzbw %al, %di # CHECK-NEXT: - - - - - 0.50 0.50 1.00 movsbw (%rax), %di @@ -1888,6 +1941,12 @@ xorq (%rax), %rdi # CHECK-NEXT: - - - - - 1.00 - - shrdq $7, %rsi, %rdi # CHECK-NEXT: - - - - - 1.00 - 2.00 shldq $7, %rsi, (%rax) # CHECK-NEXT: - - - - - 1.00 - 2.00 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - - - - 0.50 0.50 - stc +# CHECK-NEXT: - - - - - 0.50 0.50 - std +# CHECK-NEXT: - - - 1.00 - - - - stosb %al, %es:(%rdi) +# CHECK-NEXT: - - - 1.00 - - - - stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - - 1.00 - - - - stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - - 1.00 - - - - stosq %rax, %es:(%rdi) # CHECK-NEXT: - - - - - 0.50 0.50 - subb $7, %al # CHECK-NEXT: - - - - - 0.50 0.50 - subb $7, %dil # CHECK-NEXT: - - - - - 1.00 1.00 2.00 subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/SandyBridge/resources-x86_32.s b/test/tools/llvm-mca/X86/SandyBridge/resources-x86_32.s new file mode 100644 index 000000000000..4441391fd9bb --- /dev/null +++ b/test/tools/llvm-mca/X86/SandyBridge/resources-x86_32.s @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=sandybridge -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.33 aaa +# CHECK-NEXT: 1 100 0.33 aad +# CHECK-NEXT: 1 100 0.33 aad $7 +# CHECK-NEXT: 1 100 0.33 aam +# CHECK-NEXT: 1 100 0.33 aam $7 +# CHECK-NEXT: 1 100 0.33 aas +# CHECK-NEXT: 1 100 0.33 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.33 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.33 daa +# CHECK-NEXT: 1 100 0.33 das +# CHECK-NEXT: 1 100 0.33 U into +# CHECK-NEXT: 3 7 0.67 * leave +# CHECK-NEXT: 1 1 0.33 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 4.67 4.67 - 4.67 0.50 0.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aaa +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aas +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %bx, (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %ebx, (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - daa +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - das +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - into +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 leave +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - salc diff --git a/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s b/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s index a9627e85b60f..cda2e7e6b5aa 100644 --- a/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.33 cmpq %rsi, %rdi # CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) # CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 5 8 1.00 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.33 decb %dil # CHECK-NEXT: 3 7 1.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.33 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.33 incq %rdi # CHECK-NEXT: 3 7 1.00 * * incq (%rax) # CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 3 7 0.67 U lodsb (%rsi), %al +# CHECK-NEXT: 3 7 0.67 U lodsw (%rsi), %ax +# CHECK-NEXT: 2 6 0.50 U lodsl (%rsi), %eax +# CHECK-NEXT: 2 6 0.50 U lodsq (%rsi), %rax +# CHECK-NEXT: 5 8 1.00 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.33 movsbw %al, %di # CHECK-NEXT: 1 1 0.33 movzbw %al, %di # CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 2 2 0.67 shrdq $7, %rsi, %rdi # CHECK-NEXT: 5 8 1.00 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 5 8 1.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.33 U stc +# CHECK-NEXT: 1 1 0.33 U std +# CHECK-NEXT: 3 5 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.33 subb $7, %al # CHECK-NEXT: 1 1 0.33 subb $7, %dil # CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) @@ -1328,7 +1369,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: 160.00 - 365.50 171.00 210.00 356.50 254.00 254.00 +# CHECK-NEXT: 160.00 - 376.17 181.67 218.00 367.17 266.00 266.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: @@ -1523,6 +1564,10 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq %rsi, %rdi # CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq %rsi, (%rax) # CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq (%rax), %rdi +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decw %di @@ -1582,6 +1627,14 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incq %rdi # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incq (%rax) # CHECK-NEXT: - - 0.50 - - 0.50 - - lahf +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsb (%rsi), %al +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsw (%rsi), %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsl (%rsi), %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsq (%rsi), %rax +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsq (%rsi), %es:(%rdi) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbw %al, %di # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbw %al, %di # CHECK-NEXT: - - - - - - 0.50 0.50 movsbw (%rax), %di @@ -1888,6 +1941,12 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdq $7, %rsi, %rdi # CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldq $7, %rsi, (%rax) # CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - stc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - std +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosb %al, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosq %rax, %es:(%rdi) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %al # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %dil # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_32.s b/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_32.s new file mode 100644 index 000000000000..103cc3ced847 --- /dev/null +++ b/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_32.s @@ -0,0 +1,80 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=skylake -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.25 aaa +# CHECK-NEXT: 1 100 0.25 aad +# CHECK-NEXT: 1 100 0.25 aad $7 +# CHECK-NEXT: 1 100 0.25 aam +# CHECK-NEXT: 1 100 0.25 aam $7 +# CHECK-NEXT: 1 100 0.25 aas +# CHECK-NEXT: 1 100 0.25 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.25 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.25 daa +# CHECK-NEXT: 1 100 0.25 das +# CHECK-NEXT: 1 100 0.25 U into +# CHECK-NEXT: 3 7 0.50 * leave +# CHECK-NEXT: 1 1 0.25 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - SKLDivider +# CHECK-NEXT: [1] - SKLFPDivider +# CHECK-NEXT: [2] - SKLPort0 +# CHECK-NEXT: [3] - SKLPort1 +# CHECK-NEXT: [4] - SKLPort2 +# CHECK-NEXT: [5] - SKLPort3 +# CHECK-NEXT: [6] - SKLPort4 +# CHECK-NEXT: [7] - SKLPort5 +# CHECK-NEXT: [8] - SKLPort6 +# CHECK-NEXT: [9] - SKLPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 3.50 3.50 0.50 0.50 - 3.50 3.50 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aaa +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aad +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aad $7 +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aam +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aam $7 +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aas +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - bound %bx, (%eax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - bound %ebx, (%eax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - daa +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - das +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - into +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - leave +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - salc diff --git a/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s b/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s index e21c4085aad2..5f88e2cf7dc8 100644 --- a/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 cmpq %rsi, %rdi # CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) # CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 1 100 0.25 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.25 decb %dil # CHECK-NEXT: 3 7 1.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.25 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 incq %rdi # CHECK-NEXT: 3 7 1.00 * * incq (%rax) # CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 1 100 0.25 U lodsb (%rsi), %al +# CHECK-NEXT: 1 100 0.25 U lodsw (%rsi), %ax +# CHECK-NEXT: 1 100 0.25 U lodsl (%rsi), %eax +# CHECK-NEXT: 1 100 0.25 U lodsq (%rsi), %rax +# CHECK-NEXT: 1 100 0.25 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.25 movsbw %al, %di # CHECK-NEXT: 1 1 0.25 movzbw %al, %di # CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 3 1.00 shrdq $7, %rsi, %rdi # CHECK-NEXT: 4 9 1.00 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 4 9 1.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.25 U stc +# CHECK-NEXT: 6 6 1.50 U std +# CHECK-NEXT: 3 2 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.25 subb $7, %al # CHECK-NEXT: 1 1 0.25 subb $7, %dil # CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) @@ -1330,7 +1371,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] -# CHECK-NEXT: 60.00 - 444.50 248.50 218.00 218.00 167.00 197.00 430.00 69.00 +# CHECK-NEXT: 60.00 - 450.00 254.00 219.33 219.33 171.00 202.50 436.50 70.33 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: @@ -1525,6 +1566,10 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpq %rsi, %rdi # CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - cmpq %rsi, (%rax) # CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - cmpq (%rax), %rdi +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - decb %dil # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 decb (%rax) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - decw %di @@ -1584,6 +1629,14 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - incq %rdi # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 incq (%rax) # CHECK-NEXT: - - 0.50 - - - - - 0.50 - lahf +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsb (%rsi), %al +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsw (%rsi), %ax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsl (%rsi), %eax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsq (%rsi), %rax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsq (%rsi), %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsbw %al, %di # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movzbw %al, %di # CHECK-NEXT: - - - - 0.50 0.50 - - - - movsbw (%rax), %di @@ -1890,6 +1943,12 @@ xorq (%rax), %rdi # CHECK-NEXT: - - - 1.00 - - - - - - shrdq $7, %rsi, %rdi # CHECK-NEXT: - - 0.25 1.25 0.83 0.83 - 0.25 0.25 0.33 shldq $7, %rsi, (%rax) # CHECK-NEXT: - - 0.25 1.25 0.83 0.83 - 0.25 0.25 0.33 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - stc +# CHECK-NEXT: - - 1.25 1.25 - - - 1.25 2.25 - std +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosb %al, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosq %rax, %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - subb $7, %al # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - subb $7, %dil # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_32.s b/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_32.s new file mode 100644 index 000000000000..ebb503cdf379 --- /dev/null +++ b/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_32.s @@ -0,0 +1,80 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=skylake-avx512 -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.25 aaa +# CHECK-NEXT: 1 100 0.25 aad +# CHECK-NEXT: 1 100 0.25 aad $7 +# CHECK-NEXT: 1 100 0.25 aam +# CHECK-NEXT: 1 100 0.25 aam $7 +# CHECK-NEXT: 1 100 0.25 aas +# CHECK-NEXT: 1 100 0.25 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.25 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.25 daa +# CHECK-NEXT: 1 100 0.25 das +# CHECK-NEXT: 1 100 0.25 U into +# CHECK-NEXT: 3 7 0.50 * leave +# CHECK-NEXT: 1 1 0.25 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - SKXDivider +# CHECK-NEXT: [1] - SKXFPDivider +# CHECK-NEXT: [2] - SKXPort0 +# CHECK-NEXT: [3] - SKXPort1 +# CHECK-NEXT: [4] - SKXPort2 +# CHECK-NEXT: [5] - SKXPort3 +# CHECK-NEXT: [6] - SKXPort4 +# CHECK-NEXT: [7] - SKXPort5 +# CHECK-NEXT: [8] - SKXPort6 +# CHECK-NEXT: [9] - SKXPort7 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] +# CHECK-NEXT: - - 3.50 3.50 0.50 0.50 - 3.50 3.50 - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aaa +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aad +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aad $7 +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aam +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aam $7 +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - aas +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - bound %bx, (%eax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - bound %ebx, (%eax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - daa +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - das +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - into +# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - 0.50 0.50 - leave +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - salc diff --git a/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s b/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s index 7671bb0e21ea..6cd2ae1198e8 100644 --- a/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 cmpq %rsi, %rdi # CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) # CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 1 100 0.25 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.25 decb %dil # CHECK-NEXT: 3 7 1.00 * * decb (%rax) # CHECK-NEXT: 1 1 0.25 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 incq %rdi # CHECK-NEXT: 3 7 1.00 * * incq (%rax) # CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 1 100 0.25 U lodsb (%rsi), %al +# CHECK-NEXT: 1 100 0.25 U lodsw (%rsi), %ax +# CHECK-NEXT: 1 100 0.25 U lodsl (%rsi), %eax +# CHECK-NEXT: 1 100 0.25 U lodsq (%rsi), %rax +# CHECK-NEXT: 1 100 0.25 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.25 movsbw %al, %di # CHECK-NEXT: 1 1 0.25 movzbw %al, %di # CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 3 1.00 shrdq $7, %rsi, %rdi # CHECK-NEXT: 4 9 1.00 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 4 9 1.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.25 U stc +# CHECK-NEXT: 6 6 1.50 U std +# CHECK-NEXT: 3 2 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 3 2 1.00 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.25 subb $7, %al # CHECK-NEXT: 1 1 0.25 subb $7, %dil # CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) @@ -1330,7 +1371,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] -# CHECK-NEXT: 60.00 - 444.75 248.75 218.00 218.00 167.00 197.25 430.25 69.00 +# CHECK-NEXT: 60.00 - 450.25 254.25 219.33 219.33 171.00 202.75 436.75 70.33 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: @@ -1525,6 +1566,10 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpq %rsi, %rdi # CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - cmpq %rsi, (%rax) # CHECK-NEXT: - - 0.25 0.25 0.50 0.50 - 0.25 0.25 - cmpq (%rax), %rdi +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - decb %dil # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 decb (%rax) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - decw %di @@ -1584,6 +1629,14 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - incq %rdi # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 incq (%rax) # CHECK-NEXT: - - 0.50 - - - - - 0.50 - lahf +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsb (%rsi), %al +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsw (%rsi), %ax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsl (%rsi), %eax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - lodsq (%rsi), %rax +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsq (%rsi), %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movsbw %al, %di # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - movzbw %al, %di # CHECK-NEXT: - - - - 0.50 0.50 - - - - movsbw (%rax), %di @@ -1890,6 +1943,12 @@ xorq (%rax), %rdi # CHECK-NEXT: - - - 1.00 - - - - - - shrdq $7, %rsi, %rdi # CHECK-NEXT: - - 0.25 1.25 0.83 0.83 - 0.25 0.25 0.33 shldq $7, %rsi, (%rax) # CHECK-NEXT: - - 0.25 1.25 0.83 0.83 - 0.25 0.25 0.33 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - stc +# CHECK-NEXT: - - 1.25 1.25 - - - 1.25 2.25 - std +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosb %al, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - 0.25 0.25 0.33 0.33 1.00 0.25 0.25 0.33 stosq %rax, %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - subb $7, %al # CHECK-NEXT: - - 0.25 0.25 - - - 0.25 0.25 - subb $7, %dil # CHECK-NEXT: - - 0.25 0.25 0.83 0.83 1.00 0.25 0.25 0.33 subb $7, (%rax) diff --git a/test/tools/llvm-mca/X86/Znver1/resources-x86_32.s b/test/tools/llvm-mca/X86/Znver1/resources-x86_32.s new file mode 100644 index 000000000000..85bd0dc9de4b --- /dev/null +++ b/test/tools/llvm-mca/X86/Znver1/resources-x86_32.s @@ -0,0 +1,82 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=znver1 -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.25 aaa +# CHECK-NEXT: 1 100 0.25 aad +# CHECK-NEXT: 1 100 0.25 aad $7 +# CHECK-NEXT: 1 100 0.25 aam +# CHECK-NEXT: 1 100 0.25 aam $7 +# CHECK-NEXT: 1 100 0.25 aas +# CHECK-NEXT: 1 100 0.25 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.25 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.25 daa +# CHECK-NEXT: 1 100 0.25 das +# CHECK-NEXT: 1 100 0.25 U into +# CHECK-NEXT: 2 8 0.50 * leave +# CHECK-NEXT: 1 1 0.25 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - ZnAGU0 +# CHECK-NEXT: [1] - ZnAGU1 +# CHECK-NEXT: [2] - ZnALU0 +# CHECK-NEXT: [3] - ZnALU1 +# CHECK-NEXT: [4] - ZnALU2 +# CHECK-NEXT: [5] - ZnALU3 +# CHECK-NEXT: [6] - ZnDivider +# CHECK-NEXT: [7] - ZnFPU0 +# CHECK-NEXT: [8] - ZnFPU1 +# CHECK-NEXT: [9] - ZnFPU2 +# CHECK-NEXT: [10] - ZnFPU3 +# CHECK-NEXT: [11] - ZnMultiplier + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] +# CHECK-NEXT: 0.50 0.50 0.50 0.50 0.50 0.50 - - - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions: +# CHECK-NEXT: - - - - - - - - - - - - aaa +# CHECK-NEXT: - - - - - - - - - - - - aad +# CHECK-NEXT: - - - - - - - - - - - - aad $7 +# CHECK-NEXT: - - - - - - - - - - - - aam +# CHECK-NEXT: - - - - - - - - - - - - aam $7 +# CHECK-NEXT: - - - - - - - - - - - - aas +# CHECK-NEXT: - - - - - - - - - - - - bound %bx, (%eax) +# CHECK-NEXT: - - - - - - - - - - - - bound %ebx, (%eax) +# CHECK-NEXT: - - - - - - - - - - - - daa +# CHECK-NEXT: - - - - - - - - - - - - das +# CHECK-NEXT: - - - - - - - - - - - - into +# CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - leave +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - salc diff --git a/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s b/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s index 261328b15dc5..c2b6cf785601 100644 --- a/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s +++ b/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s @@ -217,6 +217,11 @@ cmpq %rsi, %rdi cmpq %rsi, (%rax) cmpq (%rax), %rdi +cmpsb +cmpsw +cmpsl +cmpsq + decb %dil decb (%rax) decw %di @@ -285,6 +290,16 @@ incq (%rax) lahf +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + movsbw %al, %di movzbw %al, %di movsbw (%rax), %di @@ -622,6 +637,14 @@ shrdq $7, %rsi, %rdi shldq $7, %rsi, (%rax) shrdq $7, %rsi, (%rax) +stc +std + +stosb +stosw +stosl +stosq + subb $7, %al subb $7, %dil subb $7, (%rax) @@ -890,6 +913,10 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 cmpq %rsi, %rdi # CHECK-NEXT: 2 5 0.50 * cmpq %rsi, (%rax) # CHECK-NEXT: 2 5 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 1 100 0.25 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 1 100 0.25 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 1 1 0.25 decb %dil # CHECK-NEXT: 2 5 0.50 * * decb (%rax) # CHECK-NEXT: 1 1 0.25 decw %di @@ -949,6 +976,14 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 incq %rdi # CHECK-NEXT: 2 5 0.50 * * incq (%rax) # CHECK-NEXT: 1 100 0.25 lahf +# CHECK-NEXT: 1 100 0.25 U lodsb (%rsi), %al +# CHECK-NEXT: 1 100 0.25 U lodsw (%rsi), %ax +# CHECK-NEXT: 1 100 0.25 U lodsl (%rsi), %eax +# CHECK-NEXT: 1 100 0.25 U lodsq (%rsi), %rax +# CHECK-NEXT: 1 100 0.25 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U movsq (%rsi), %es:(%rdi) # CHECK-NEXT: 1 1 0.25 movsbw %al, %di # CHECK-NEXT: 1 1 0.25 movzbw %al, %di # CHECK-NEXT: 2 5 0.50 * movsbw (%rax), %di @@ -1255,6 +1290,12 @@ xorq (%rax), %rdi # CHECK-NEXT: 1 1 0.25 shrdq $7, %rsi, %rdi # CHECK-NEXT: 2 5 0.50 * * shldq $7, %rsi, (%rax) # CHECK-NEXT: 2 5 0.50 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.25 U stc +# CHECK-NEXT: 1 1 0.25 U std +# CHECK-NEXT: 1 100 0.25 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 1 100 0.25 U stosq %rax, %es:(%rdi) # CHECK-NEXT: 1 1 0.25 subb $7, %al # CHECK-NEXT: 1 1 0.25 subb $7, %dil # CHECK-NEXT: 2 5 0.50 * * subb $7, (%rax) @@ -1332,7 +1373,7 @@ xorq (%rax), %rdi # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] -# CHECK-NEXT: 147.50 147.50 131.00 165.00 147.00 131.00 392.00 - - - - 34.00 +# CHECK-NEXT: 147.50 147.50 131.50 165.50 147.50 131.50 392.00 - - - - 34.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions: @@ -1527,6 +1568,10 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - cmpq %rsi, %rdi # CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - cmpq %rsi, (%rax) # CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - cmpq (%rax), %rdi +# CHECK-NEXT: - - - - - - - - - - - - cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - - - - - - - - - - cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - - - - - - - - - - cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - - - - - - - - - - cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - decb %dil # CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - decb (%rax) # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - decw %di @@ -1586,6 +1631,14 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - incq %rdi # CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - incq (%rax) # CHECK-NEXT: - - - - - - - - - - - - lahf +# CHECK-NEXT: - - - - - - - - - - - - lodsb (%rsi), %al +# CHECK-NEXT: - - - - - - - - - - - - lodsw (%rsi), %ax +# CHECK-NEXT: - - - - - - - - - - - - lodsl (%rsi), %eax +# CHECK-NEXT: - - - - - - - - - - - - lodsq (%rsi), %rax +# CHECK-NEXT: - - - - - - - - - - - - movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - - - - - - - - - - movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - - - - - - - - - - movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - - - - - - - - - - movsq (%rsi), %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - movsbw %al, %di # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - movzbw %al, %di # CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - movsbw (%rax), %di @@ -1892,6 +1945,12 @@ xorq (%rax), %rdi # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - shrdq $7, %rsi, %rdi # CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - shldq $7, %rsi, (%rax) # CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - stc +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - std +# CHECK-NEXT: - - - - - - - - - - - - stosb %al, %es:(%rdi) +# CHECK-NEXT: - - - - - - - - - - - - stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - - - - - - - - - - - stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - - - - - - - - - - - stosq %rax, %es:(%rdi) # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - subb $7, %al # CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - subb $7, %dil # CHECK-NEXT: 0.50 0.50 0.25 0.25 0.25 0.25 - - - - - - subb $7, (%rax) diff --git a/test/tools/llvm-objcopy/strip-debug.test b/test/tools/llvm-objcopy/strip-debug.test index c8f90d9ca19e..6c833f301c7f 100644 --- a/test/tools/llvm-objcopy/strip-debug.test +++ b/test/tools/llvm-objcopy/strip-debug.test @@ -67,7 +67,7 @@ # RUN: llvm-objcopy --strip-debug %t.thin.a %t2.thin.a # RUN: cat %t.thin.a | FileCheck %s --check-prefix=VERIFY-THIN-ARCHIVE # RUN: cat %t2.thin.a | FileCheck %s --check-prefix=VERIFY-THIN-ARCHIVE - + # VERIFY-THIN-ARCHIVE: !<thin> # Verify that the member of a thin archive was properly modified. @@ -94,6 +94,12 @@ Sections: - Name: .debugfoo Type: SHT_PROGBITS Content: "00000000" + - Name: .zdebugfoo + Type: SHT_PROGBITS + Content: "00000000" + - Name: .gdb_index + Type: SHT_PROGBITS + Content: "00000000" - Name: .text Type: SHT_PROGBITS Flags: [ SHF_ALLOC, SHF_EXECINSTR ] |