diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2018-07-28 10:51:19 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-07-28 10:51:19 +0000 |
| commit | eb11fae6d08f479c0799db45860a98af528fa6e7 (patch) | |
| tree | 44d492a50c8c1a7eb8e2d17ea3360ec4d066f042 /utils/TableGen/TableGen.cpp | |
| parent | b8a2042aa938069e862750553db0e4d82d25822c (diff) | |
Notes
Diffstat (limited to 'utils/TableGen/TableGen.cpp')
| -rw-r--r-- | utils/TableGen/TableGen.cpp | 40 |
1 files changed, 32 insertions, 8 deletions
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp index b0e0385a45c7..b78260625cb2 100644 --- a/utils/TableGen/TableGen.cpp +++ b/utils/TableGen/TableGen.cpp @@ -24,6 +24,7 @@ using namespace llvm; enum ActionType { PrintRecords, + DumpJSON, GenEmitter, GenRegisterInfo, GenInstrInfo, @@ -32,13 +33,16 @@ enum ActionType { GenAsmMatcher, GenDisassembler, GenPseudoLowering, + GenCompressInst, GenCallingConv, GenDAGISel, GenDFAPacketizer, GenFastISel, GenSubtarget, - GenIntrinsic, - GenTgtIntrinsic, + GenIntrinsicEnums, + GenIntrinsicImpl, + GenTgtIntrinsicEnums, + GenTgtIntrinsicImpl, PrintEnums, PrintSets, GenOptParserDefs, @@ -56,6 +60,8 @@ namespace { Action(cl::desc("Action to perform:"), cl::values(clEnumValN(PrintRecords, "print-records", "Print all records to stdout (default)"), + clEnumValN(DumpJSON, "dump-json", + "Dump all records as machine-readable JSON"), clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"), clEnumValN(GenRegisterInfo, "gen-register-info", @@ -72,6 +78,8 @@ namespace { "Generate disassembler"), clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", "Generate pseudo instruction lowering"), + clEnumValN(GenCompressInst, "gen-compress-inst-emitter", + "Generate RISCV compressed instructions."), clEnumValN(GenAsmMatcher, "gen-asm-matcher", "Generate assembly instruction matcher"), clEnumValN(GenDAGISel, "gen-dag-isel", @@ -82,9 +90,13 @@ namespace { "Generate a \"fast\" instruction selector"), clEnumValN(GenSubtarget, "gen-subtarget", "Generate subtarget enumerations"), - clEnumValN(GenIntrinsic, "gen-intrinsic", + clEnumValN(GenIntrinsicEnums, "gen-intrinsic-enums", + "Generate intrinsic enums"), + clEnumValN(GenIntrinsicImpl, "gen-intrinsic-impl", "Generate intrinsic information"), - clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", + clEnumValN(GenTgtIntrinsicEnums, "gen-tgt-intrinsic-enums", + "Generate target intrinsic enums"), + clEnumValN(GenTgtIntrinsicImpl, "gen-tgt-intrinsic-impl", "Generate target intrinsic information"), clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"), @@ -117,6 +129,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case PrintRecords: OS << Records; // No argument, dump all contents break; + case DumpJSON: + EmitJSON(Records, OS); + break; case GenEmitter: EmitCodeEmitter(Records, OS); break; @@ -144,6 +159,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenPseudoLowering: EmitPseudoLowering(Records, OS); break; + case GenCompressInst: + EmitCompressInst(Records, OS); + break; case GenDAGISel: EmitDAGISel(Records, OS); break; @@ -156,11 +174,17 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenSubtarget: EmitSubtarget(Records, OS); break; - case GenIntrinsic: - EmitIntrinsics(Records, OS); + case GenIntrinsicEnums: + EmitIntrinsicEnums(Records, OS); + break; + case GenIntrinsicImpl: + EmitIntrinsicImpl(Records, OS); + break; + case GenTgtIntrinsicEnums: + EmitIntrinsicEnums(Records, OS, true); break; - case GenTgtIntrinsic: - EmitIntrinsics(Records, OS, true); + case GenTgtIntrinsicImpl: + EmitIntrinsicImpl(Records, OS, true); break; case GenOptParserDefs: EmitOptParser(Records, OS); |