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-rw-r--r--ELF/Arch/AArch64.cpp374
-rw-r--r--ELF/Arch/AMDGPU.cpp82
-rw-r--r--ELF/Arch/ARM.cpp432
-rw-r--r--ELF/Arch/AVR.cpp78
-rw-r--r--ELF/Arch/Mips.cpp422
-rw-r--r--ELF/Arch/PPC.cpp63
-rw-r--r--ELF/Arch/PPC64.cpp215
-rw-r--r--ELF/Arch/X86.cpp363
-rw-r--r--ELF/Arch/X86_64.cpp468
-rw-r--r--ELF/CMakeLists.txt9
-rw-r--r--ELF/Driver.cpp82
-rw-r--r--ELF/ICF.cpp84
-rw-r--r--ELF/InputFiles.cpp37
-rw-r--r--ELF/InputFiles.h7
-rw-r--r--ELF/InputSection.cpp38
-rw-r--r--ELF/LinkerScript.cpp136
-rw-r--r--ELF/LinkerScript.h6
-rw-r--r--ELF/MarkLive.cpp2
-rw-r--r--ELF/OutputSections.cpp3
-rw-r--r--ELF/OutputSections.h2
-rw-r--r--ELF/Relocations.cpp26
-rw-r--r--ELF/Relocations.h17
-rw-r--r--ELF/Strings.h4
-rw-r--r--ELF/SyntheticSections.cpp63
-rw-r--r--ELF/SyntheticSections.h2
-rw-r--r--ELF/Target.cpp2344
-rw-r--r--ELF/Target.h47
-rw-r--r--ELF/Writer.cpp263
28 files changed, 3017 insertions, 2652 deletions
diff --git a/ELF/Arch/AArch64.cpp b/ELF/Arch/AArch64.cpp
new file mode 100644
index 000000000000..113d0960d5f5
--- /dev/null
+++ b/ELF/Arch/AArch64.cpp
@@ -0,0 +1,374 @@
+//===- AArch64.cpp --------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+#include "Thunks.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+// Page(Expr) is the page address of the expression Expr, defined
+// as (Expr & ~0xFFF). (This applies even if the machine page size
+// supported by the platform has a different value.)
+uint64_t elf::getAArch64Page(uint64_t Expr) {
+ return Expr & ~static_cast<uint64_t>(0xFFF);
+}
+
+namespace {
+class AArch64 final : public TargetInfo {
+public:
+ AArch64();
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+ bool isPicRel(uint32_t Type) const override;
+ void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+ void writePltHeader(uint8_t *Buf) const override;
+ void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+ int32_t Index, unsigned RelOff) const override;
+ bool usesOnlyLowPageBits(uint32_t Type) const override;
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
+ RelExpr Expr) const override;
+ void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+};
+} // namespace
+
+AArch64::AArch64() {
+ CopyRel = R_AARCH64_COPY;
+ RelativeRel = R_AARCH64_RELATIVE;
+ IRelativeRel = R_AARCH64_IRELATIVE;
+ GotRel = R_AARCH64_GLOB_DAT;
+ PltRel = R_AARCH64_JUMP_SLOT;
+ TlsDescRel = R_AARCH64_TLSDESC;
+ TlsGotRel = R_AARCH64_TLS_TPREL64;
+ GotEntrySize = 8;
+ GotPltEntrySize = 8;
+ PltEntrySize = 16;
+ PltHeaderSize = 32;
+ DefaultMaxPageSize = 65536;
+
+ // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
+ // 1 of the tls structures and the tcb size is 16.
+ TcbSize = 16;
+}
+
+RelExpr AArch64::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ switch (Type) {
+ default:
+ return R_ABS;
+ case R_AARCH64_TLSDESC_ADR_PAGE21:
+ return R_TLSDESC_PAGE;
+ case R_AARCH64_TLSDESC_LD64_LO12:
+ case R_AARCH64_TLSDESC_ADD_LO12:
+ return R_TLSDESC;
+ case R_AARCH64_TLSDESC_CALL:
+ return R_TLSDESC_CALL;
+ case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ return R_TLS;
+ case R_AARCH64_CALL26:
+ case R_AARCH64_CONDBR19:
+ case R_AARCH64_JUMP26:
+ case R_AARCH64_TSTBR14:
+ return R_PLT_PC;
+ case R_AARCH64_PREL16:
+ case R_AARCH64_PREL32:
+ case R_AARCH64_PREL64:
+ case R_AARCH64_ADR_PREL_LO21:
+ return R_PC;
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ return R_PAGE_PC;
+ case R_AARCH64_LD64_GOT_LO12_NC:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ return R_GOT;
+ case R_AARCH64_ADR_GOT_PAGE:
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ return R_GOT_PAGE_PC;
+ case R_AARCH64_NONE:
+ return R_NONE;
+ }
+}
+
+RelExpr AArch64::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
+ RelExpr Expr) const {
+ if (Expr == R_RELAX_TLS_GD_TO_IE) {
+ if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
+ return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
+ return R_RELAX_TLS_GD_TO_IE_ABS;
+ }
+ return Expr;
+}
+
+bool AArch64::usesOnlyLowPageBits(uint32_t Type) const {
+ switch (Type) {
+ default:
+ return false;
+ case R_AARCH64_ADD_ABS_LO12_NC:
+ case R_AARCH64_LD64_GOT_LO12_NC:
+ case R_AARCH64_LDST128_ABS_LO12_NC:
+ case R_AARCH64_LDST16_ABS_LO12_NC:
+ case R_AARCH64_LDST32_ABS_LO12_NC:
+ case R_AARCH64_LDST64_ABS_LO12_NC:
+ case R_AARCH64_LDST8_ABS_LO12_NC:
+ case R_AARCH64_TLSDESC_ADD_LO12:
+ case R_AARCH64_TLSDESC_LD64_LO12:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ return true;
+ }
+}
+
+bool AArch64::isPicRel(uint32_t Type) const {
+ return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64;
+}
+
+void AArch64::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
+ write64le(Buf, InX::Plt->getVA());
+}
+
+void AArch64::writePltHeader(uint8_t *Buf) const {
+ const uint8_t PltData[] = {
+ 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
+ 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2]))
+ 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))]
+ 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2]))
+ 0x20, 0x02, 0x1f, 0xd6, // br x17
+ 0x1f, 0x20, 0x03, 0xd5, // nop
+ 0x1f, 0x20, 0x03, 0xd5, // nop
+ 0x1f, 0x20, 0x03, 0xd5 // nop
+ };
+ memcpy(Buf, PltData, sizeof(PltData));
+
+ uint64_t Got = InX::GotPlt->getVA();
+ uint64_t Plt = InX::Plt->getVA();
+ relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
+ getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
+ relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
+ relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
+}
+
+void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+ uint64_t PltEntryAddr, int32_t Index,
+ unsigned RelOff) const {
+ const uint8_t Inst[] = {
+ 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
+ 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))]
+ 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n]))
+ 0x20, 0x02, 0x1f, 0xd6 // br x17
+ };
+ memcpy(Buf, Inst, sizeof(Inst));
+
+ relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
+ getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
+ relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
+ relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
+}
+
+static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
+ uint32_t ImmLo = (Imm & 0x3) << 29;
+ uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
+ uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
+ write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
+}
+
+// Return the bits [Start, End] from Val shifted Start bits.
+// For instance, getBits(0xF0, 4, 8) returns 0xF.
+static uint64_t getBits(uint64_t Val, int Start, int End) {
+ uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
+ return (Val >> Start) & Mask;
+}
+
+static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
+
+// Update the immediate field in a AARCH64 ldr, str, and add instruction.
+static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
+ or32le(L, (Imm & 0xFFF) << 10);
+}
+
+void AArch64::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ switch (Type) {
+ case R_AARCH64_ABS16:
+ case R_AARCH64_PREL16:
+ checkIntUInt<16>(Loc, Val, Type);
+ write16le(Loc, Val);
+ break;
+ case R_AARCH64_ABS32:
+ case R_AARCH64_PREL32:
+ checkIntUInt<32>(Loc, Val, Type);
+ write32le(Loc, Val);
+ break;
+ case R_AARCH64_ABS64:
+ case R_AARCH64_GLOB_DAT:
+ case R_AARCH64_PREL64:
+ write64le(Loc, Val);
+ break;
+ case R_AARCH64_ADD_ABS_LO12_NC:
+ or32AArch64Imm(Loc, Val);
+ break;
+ case R_AARCH64_ADR_GOT_PAGE:
+ case R_AARCH64_ADR_PREL_PG_HI21:
+ case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+ case R_AARCH64_TLSDESC_ADR_PAGE21:
+ checkInt<33>(Loc, Val, Type);
+ write32AArch64Addr(Loc, Val >> 12);
+ break;
+ case R_AARCH64_ADR_PREL_LO21:
+ checkInt<21>(Loc, Val, Type);
+ write32AArch64Addr(Loc, Val);
+ break;
+ case R_AARCH64_CALL26:
+ case R_AARCH64_JUMP26:
+ checkInt<28>(Loc, Val, Type);
+ or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
+ break;
+ case R_AARCH64_CONDBR19:
+ checkInt<21>(Loc, Val, Type);
+ or32le(Loc, (Val & 0x1FFFFC) << 3);
+ break;
+ case R_AARCH64_LD64_GOT_LO12_NC:
+ case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+ case R_AARCH64_TLSDESC_LD64_LO12:
+ checkAlignment<8>(Loc, Val, Type);
+ or32le(Loc, (Val & 0xFF8) << 7);
+ break;
+ case R_AARCH64_LDST8_ABS_LO12_NC:
+ or32AArch64Imm(Loc, getBits(Val, 0, 11));
+ break;
+ case R_AARCH64_LDST16_ABS_LO12_NC:
+ or32AArch64Imm(Loc, getBits(Val, 1, 11));
+ break;
+ case R_AARCH64_LDST32_ABS_LO12_NC:
+ or32AArch64Imm(Loc, getBits(Val, 2, 11));
+ break;
+ case R_AARCH64_LDST64_ABS_LO12_NC:
+ or32AArch64Imm(Loc, getBits(Val, 3, 11));
+ break;
+ case R_AARCH64_LDST128_ABS_LO12_NC:
+ or32AArch64Imm(Loc, getBits(Val, 4, 11));
+ break;
+ case R_AARCH64_MOVW_UABS_G0_NC:
+ or32le(Loc, (Val & 0xFFFF) << 5);
+ break;
+ case R_AARCH64_MOVW_UABS_G1_NC:
+ or32le(Loc, (Val & 0xFFFF0000) >> 11);
+ break;
+ case R_AARCH64_MOVW_UABS_G2_NC:
+ or32le(Loc, (Val & 0xFFFF00000000) >> 27);
+ break;
+ case R_AARCH64_MOVW_UABS_G3:
+ or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
+ break;
+ case R_AARCH64_TSTBR14:
+ checkInt<16>(Loc, Val, Type);
+ or32le(Loc, (Val & 0xFFFC) << 3);
+ break;
+ case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+ checkInt<24>(Loc, Val, Type);
+ or32AArch64Imm(Loc, Val >> 12);
+ break;
+ case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+ case R_AARCH64_TLSDESC_ADD_LO12:
+ or32AArch64Imm(Loc, Val);
+ break;
+ default:
+ error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+ }
+}
+
+void AArch64::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ // TLSDESC Global-Dynamic relocation are in the form:
+ // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
+ // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
+ // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
+ // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
+ // blr x1
+ // And it can optimized to:
+ // movz x0, #0x0, lsl #16
+ // movk x0, #0x10
+ // nop
+ // nop
+ checkUInt<32>(Loc, Val, Type);
+
+ switch (Type) {
+ case R_AARCH64_TLSDESC_ADD_LO12:
+ case R_AARCH64_TLSDESC_CALL:
+ write32le(Loc, 0xd503201f); // nop
+ return;
+ case R_AARCH64_TLSDESC_ADR_PAGE21:
+ write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
+ return;
+ case R_AARCH64_TLSDESC_LD64_LO12:
+ write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
+ return;
+ default:
+ llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
+ }
+}
+
+void AArch64::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ // TLSDESC Global-Dynamic relocation are in the form:
+ // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
+ // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
+ // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
+ // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
+ // blr x1
+ // And it can optimized to:
+ // adrp x0, :gottprel:v
+ // ldr x0, [x0, :gottprel_lo12:v]
+ // nop
+ // nop
+
+ switch (Type) {
+ case R_AARCH64_TLSDESC_ADD_LO12:
+ case R_AARCH64_TLSDESC_CALL:
+ write32le(Loc, 0xd503201f); // nop
+ break;
+ case R_AARCH64_TLSDESC_ADR_PAGE21:
+ write32le(Loc, 0x90000000); // adrp
+ relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
+ break;
+ case R_AARCH64_TLSDESC_LD64_LO12:
+ write32le(Loc, 0xf9400000); // ldr
+ relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
+ break;
+ default:
+ llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
+ }
+}
+
+void AArch64::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ checkUInt<32>(Loc, Val, Type);
+
+ if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
+ // Generate MOVZ.
+ uint32_t RegNo = read32le(Loc) & 0x1f;
+ write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
+ return;
+ }
+ if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
+ // Generate MOVK.
+ uint32_t RegNo = read32le(Loc) & 0x1f;
+ write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
+ return;
+ }
+ llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
+}
+
+TargetInfo *elf::createAArch64TargetInfo() { return make<AArch64>(); }
diff --git a/ELF/Arch/AMDGPU.cpp b/ELF/Arch/AMDGPU.cpp
new file mode 100644
index 000000000000..68e516f9e6cf
--- /dev/null
+++ b/ELF/Arch/AMDGPU.cpp
@@ -0,0 +1,82 @@
+//===- AMDGPU.cpp ---------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "InputFiles.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "Target.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class AMDGPU final : public TargetInfo {
+public:
+ AMDGPU();
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+};
+} // namespace
+
+AMDGPU::AMDGPU() {
+ RelativeRel = R_AMDGPU_REL64;
+ GotRel = R_AMDGPU_ABS64;
+ GotEntrySize = 8;
+}
+
+void AMDGPU::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ switch (Type) {
+ case R_AMDGPU_ABS32:
+ case R_AMDGPU_GOTPCREL:
+ case R_AMDGPU_GOTPCREL32_LO:
+ case R_AMDGPU_REL32:
+ case R_AMDGPU_REL32_LO:
+ write32le(Loc, Val);
+ break;
+ case R_AMDGPU_ABS64:
+ write64le(Loc, Val);
+ break;
+ case R_AMDGPU_GOTPCREL32_HI:
+ case R_AMDGPU_REL32_HI:
+ write32le(Loc, Val >> 32);
+ break;
+ default:
+ error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+ }
+}
+
+RelExpr AMDGPU::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ switch (Type) {
+ case R_AMDGPU_ABS32:
+ case R_AMDGPU_ABS64:
+ return R_ABS;
+ case R_AMDGPU_REL32:
+ case R_AMDGPU_REL32_LO:
+ case R_AMDGPU_REL32_HI:
+ return R_PC;
+ case R_AMDGPU_GOTPCREL:
+ case R_AMDGPU_GOTPCREL32_LO:
+ case R_AMDGPU_GOTPCREL32_HI:
+ return R_GOT_PC;
+ default:
+ error(toString(S.File) + ": unknown relocation type: " + toString(Type));
+ return R_HINT;
+ }
+}
+
+TargetInfo *elf::createAMDGPUTargetInfo() { return make<AMDGPU>(); }
diff --git a/ELF/Arch/ARM.cpp b/ELF/Arch/ARM.cpp
new file mode 100644
index 000000000000..b245cbd7005a
--- /dev/null
+++ b/ELF/Arch/ARM.cpp
@@ -0,0 +1,432 @@
+//===- ARM.cpp ------------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "InputFiles.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+#include "Thunks.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class ARM final : public TargetInfo {
+public:
+ ARM();
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+ bool isPicRel(uint32_t Type) const override;
+ uint32_t getDynRel(uint32_t Type) const override;
+ int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
+ void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+ void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+ void writePltHeader(uint8_t *Buf) const override;
+ void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+ int32_t Index, unsigned RelOff) const override;
+ void addPltSymbols(InputSectionBase *IS, uint64_t Off) const override;
+ void addPltHeaderSymbols(InputSectionBase *ISD) const override;
+ bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
+ const SymbolBody &S) const override;
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+};
+} // namespace
+
+ARM::ARM() {
+ CopyRel = R_ARM_COPY;
+ RelativeRel = R_ARM_RELATIVE;
+ IRelativeRel = R_ARM_IRELATIVE;
+ GotRel = R_ARM_GLOB_DAT;
+ PltRel = R_ARM_JUMP_SLOT;
+ TlsGotRel = R_ARM_TLS_TPOFF32;
+ TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
+ TlsOffsetRel = R_ARM_TLS_DTPOFF32;
+ GotEntrySize = 4;
+ GotPltEntrySize = 4;
+ PltEntrySize = 16;
+ PltHeaderSize = 20;
+ // ARM uses Variant 1 TLS
+ TcbSize = 8;
+ NeedsThunks = true;
+}
+
+RelExpr ARM::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ switch (Type) {
+ default:
+ return R_ABS;
+ case R_ARM_THM_JUMP11:
+ return R_PC;
+ case R_ARM_CALL:
+ case R_ARM_JUMP24:
+ case R_ARM_PC24:
+ case R_ARM_PLT32:
+ case R_ARM_PREL31:
+ case R_ARM_THM_JUMP19:
+ case R_ARM_THM_JUMP24:
+ case R_ARM_THM_CALL:
+ return R_PLT_PC;
+ case R_ARM_GOTOFF32:
+ // (S + A) - GOT_ORG
+ return R_GOTREL;
+ case R_ARM_GOT_BREL:
+ // GOT(S) + A - GOT_ORG
+ return R_GOT_OFF;
+ case R_ARM_GOT_PREL:
+ case R_ARM_TLS_IE32:
+ // GOT(S) + A - P
+ return R_GOT_PC;
+ case R_ARM_SBREL32:
+ return R_ARM_SBREL;
+ case R_ARM_TARGET1:
+ return Config->Target1Rel ? R_PC : R_ABS;
+ case R_ARM_TARGET2:
+ if (Config->Target2 == Target2Policy::Rel)
+ return R_PC;
+ if (Config->Target2 == Target2Policy::Abs)
+ return R_ABS;
+ return R_GOT_PC;
+ case R_ARM_TLS_GD32:
+ return R_TLSGD_PC;
+ case R_ARM_TLS_LDM32:
+ return R_TLSLD_PC;
+ case R_ARM_BASE_PREL:
+ // B(S) + A - P
+ // FIXME: currently B(S) assumed to be .got, this may not hold for all
+ // platforms.
+ return R_GOTONLY_PC;
+ case R_ARM_MOVW_PREL_NC:
+ case R_ARM_MOVT_PREL:
+ case R_ARM_REL32:
+ case R_ARM_THM_MOVW_PREL_NC:
+ case R_ARM_THM_MOVT_PREL:
+ return R_PC;
+ case R_ARM_NONE:
+ return R_NONE;
+ case R_ARM_TLS_LE32:
+ return R_TLS;
+ }
+}
+
+bool ARM::isPicRel(uint32_t Type) const {
+ return (Type == R_ARM_TARGET1 && !Config->Target1Rel) ||
+ (Type == R_ARM_ABS32);
+}
+
+uint32_t ARM::getDynRel(uint32_t Type) const {
+ if (Type == R_ARM_TARGET1 && !Config->Target1Rel)
+ return R_ARM_ABS32;
+ if (Type == R_ARM_ABS32)
+ return Type;
+ // Keep it going with a dummy value so that we can find more reloc errors.
+ return R_ARM_ABS32;
+}
+
+void ARM::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
+ write32le(Buf, InX::Plt->getVA());
+}
+
+void ARM::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const {
+ // An ARM entry is the address of the ifunc resolver function.
+ write32le(Buf, S.getVA());
+}
+
+void ARM::writePltHeader(uint8_t *Buf) const {
+ const uint8_t PltData[] = {
+ 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]!
+ 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2
+ 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
+ 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8]
+ 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8
+ };
+ memcpy(Buf, PltData, sizeof(PltData));
+ uint64_t GotPlt = InX::GotPlt->getVA();
+ uint64_t L1 = InX::Plt->getVA() + 8;
+ write32le(Buf + 16, GotPlt - L1 - 8);
+}
+
+void ARM::addPltHeaderSymbols(InputSectionBase *ISD) const {
+ auto *IS = cast<InputSection>(ISD);
+ addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS);
+ addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS);
+}
+
+void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+ uint64_t PltEntryAddr, int32_t Index,
+ unsigned RelOff) const {
+ // FIXME: Using simple code sequence with simple relocations.
+ // There is a more optimal sequence but it requires support for the group
+ // relocations. See ELF for the ARM Architecture Appendix A.3
+ const uint8_t PltData[] = {
+ 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2
+ 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
+ 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip]
+ 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8
+ };
+ memcpy(Buf, PltData, sizeof(PltData));
+ uint64_t L1 = PltEntryAddr + 4;
+ write32le(Buf + 12, GotPltEntryAddr - L1 - 8);
+}
+
+void ARM::addPltSymbols(InputSectionBase *ISD, uint64_t Off) const {
+ auto *IS = cast<InputSection>(ISD);
+ addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
+ addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
+}
+
+bool ARM::needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
+ const SymbolBody &S) const {
+ // If S is an undefined weak symbol in an executable we don't need a Thunk.
+ // In a DSO calls to undefined symbols, including weak ones get PLT entries
+ // which may need a thunk.
+ if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() &&
+ !Config->Shared)
+ return false;
+ // A state change from ARM to Thumb and vice versa must go through an
+ // interworking thunk if the relocation type is not R_ARM_CALL or
+ // R_ARM_THM_CALL.
+ switch (RelocType) {
+ case R_ARM_PC24:
+ case R_ARM_PLT32:
+ case R_ARM_JUMP24:
+ // Source is ARM, all PLT entries are ARM so no interworking required.
+ // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
+ if (Expr == R_PC && ((S.getVA() & 1) == 1))
+ return true;
+ break;
+ case R_ARM_THM_JUMP19:
+ case R_ARM_THM_JUMP24:
+ // Source is Thumb, all PLT entries are ARM so interworking is required.
+ // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
+ if (Expr == R_PLT_PC || ((S.getVA() & 1) == 0))
+ return true;
+ break;
+ }
+ return false;
+}
+
+void ARM::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ switch (Type) {
+ case R_ARM_ABS32:
+ case R_ARM_BASE_PREL:
+ case R_ARM_GLOB_DAT:
+ case R_ARM_GOTOFF32:
+ case R_ARM_GOT_BREL:
+ case R_ARM_GOT_PREL:
+ case R_ARM_REL32:
+ case R_ARM_RELATIVE:
+ case R_ARM_SBREL32:
+ case R_ARM_TARGET1:
+ case R_ARM_TARGET2:
+ case R_ARM_TLS_GD32:
+ case R_ARM_TLS_IE32:
+ case R_ARM_TLS_LDM32:
+ case R_ARM_TLS_LDO32:
+ case R_ARM_TLS_LE32:
+ case R_ARM_TLS_TPOFF32:
+ case R_ARM_TLS_DTPOFF32:
+ write32le(Loc, Val);
+ break;
+ case R_ARM_TLS_DTPMOD32:
+ write32le(Loc, 1);
+ break;
+ case R_ARM_PREL31:
+ checkInt<31>(Loc, Val, Type);
+ write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
+ break;
+ case R_ARM_CALL:
+ // R_ARM_CALL is used for BL and BLX instructions, depending on the
+ // value of bit 0 of Val, we must select a BL or BLX instruction
+ if (Val & 1) {
+ // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
+ // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
+ checkInt<26>(Loc, Val, Type);
+ write32le(Loc, 0xfa000000 | // opcode
+ ((Val & 2) << 23) | // H
+ ((Val >> 2) & 0x00ffffff)); // imm24
+ break;
+ }
+ if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
+ // BLX (always unconditional) instruction to an ARM Target, select an
+ // unconditional BL.
+ write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
+ // fall through as BL encoding is shared with B
+ LLVM_FALLTHROUGH;
+ case R_ARM_JUMP24:
+ case R_ARM_PC24:
+ case R_ARM_PLT32:
+ checkInt<26>(Loc, Val, Type);
+ write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
+ break;
+ case R_ARM_THM_JUMP11:
+ checkInt<12>(Loc, Val, Type);
+ write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
+ break;
+ case R_ARM_THM_JUMP19:
+ // Encoding T3: Val = S:J2:J1:imm6:imm11:0
+ checkInt<21>(Loc, Val, Type);
+ write16le(Loc,
+ (read16le(Loc) & 0xfbc0) | // opcode cond
+ ((Val >> 10) & 0x0400) | // S
+ ((Val >> 12) & 0x003f)); // imm6
+ write16le(Loc + 2,
+ 0x8000 | // opcode
+ ((Val >> 8) & 0x0800) | // J2
+ ((Val >> 5) & 0x2000) | // J1
+ ((Val >> 1) & 0x07ff)); // imm11
+ break;
+ case R_ARM_THM_CALL:
+ // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
+ // value of bit 0 of Val, we must select a BL or BLX instruction
+ if ((Val & 1) == 0) {
+ // Ensure BLX destination is 4-byte aligned. As BLX instruction may
+ // only be two byte aligned. This must be done before overflow check
+ Val = alignTo(Val, 4);
+ }
+ // Bit 12 is 0 for BLX, 1 for BL
+ write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
+ // Fall through as rest of encoding is the same as B.W
+ LLVM_FALLTHROUGH;
+ case R_ARM_THM_JUMP24:
+ // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
+ // FIXME: Use of I1 and I2 require v6T2ops
+ checkInt<25>(Loc, Val, Type);
+ write16le(Loc,
+ 0xf000 | // opcode
+ ((Val >> 14) & 0x0400) | // S
+ ((Val >> 12) & 0x03ff)); // imm10
+ write16le(Loc + 2,
+ (read16le(Loc + 2) & 0xd000) | // opcode
+ (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
+ (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
+ ((Val >> 1) & 0x07ff)); // imm11
+ break;
+ case R_ARM_MOVW_ABS_NC:
+ case R_ARM_MOVW_PREL_NC:
+ write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
+ (Val & 0x0fff));
+ break;
+ case R_ARM_MOVT_ABS:
+ case R_ARM_MOVT_PREL:
+ checkInt<32>(Loc, Val, Type);
+ write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
+ (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
+ break;
+ case R_ARM_THM_MOVT_ABS:
+ case R_ARM_THM_MOVT_PREL:
+ // Encoding T1: A = imm4:i:imm3:imm8
+ checkInt<32>(Loc, Val, Type);
+ write16le(Loc,
+ 0xf2c0 | // opcode
+ ((Val >> 17) & 0x0400) | // i
+ ((Val >> 28) & 0x000f)); // imm4
+ write16le(Loc + 2,
+ (read16le(Loc + 2) & 0x8f00) | // opcode
+ ((Val >> 12) & 0x7000) | // imm3
+ ((Val >> 16) & 0x00ff)); // imm8
+ break;
+ case R_ARM_THM_MOVW_ABS_NC:
+ case R_ARM_THM_MOVW_PREL_NC:
+ // Encoding T3: A = imm4:i:imm3:imm8
+ write16le(Loc,
+ 0xf240 | // opcode
+ ((Val >> 1) & 0x0400) | // i
+ ((Val >> 12) & 0x000f)); // imm4
+ write16le(Loc + 2,
+ (read16le(Loc + 2) & 0x8f00) | // opcode
+ ((Val << 4) & 0x7000) | // imm3
+ (Val & 0x00ff)); // imm8
+ break;
+ default:
+ error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+ }
+}
+
+int64_t ARM::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
+ switch (Type) {
+ default:
+ return 0;
+ case R_ARM_ABS32:
+ case R_ARM_BASE_PREL:
+ case R_ARM_GOTOFF32:
+ case R_ARM_GOT_BREL:
+ case R_ARM_GOT_PREL:
+ case R_ARM_REL32:
+ case R_ARM_TARGET1:
+ case R_ARM_TARGET2:
+ case R_ARM_TLS_GD32:
+ case R_ARM_TLS_LDM32:
+ case R_ARM_TLS_LDO32:
+ case R_ARM_TLS_IE32:
+ case R_ARM_TLS_LE32:
+ return SignExtend64<32>(read32le(Buf));
+ case R_ARM_PREL31:
+ return SignExtend64<31>(read32le(Buf));
+ case R_ARM_CALL:
+ case R_ARM_JUMP24:
+ case R_ARM_PC24:
+ case R_ARM_PLT32:
+ return SignExtend64<26>(read32le(Buf) << 2);
+ case R_ARM_THM_JUMP11:
+ return SignExtend64<12>(read16le(Buf) << 1);
+ case R_ARM_THM_JUMP19: {
+ // Encoding T3: A = S:J2:J1:imm10:imm6:0
+ uint16_t Hi = read16le(Buf);
+ uint16_t Lo = read16le(Buf + 2);
+ return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
+ ((Lo & 0x0800) << 8) | // J2
+ ((Lo & 0x2000) << 5) | // J1
+ ((Hi & 0x003f) << 12) | // imm6
+ ((Lo & 0x07ff) << 1)); // imm11:0
+ }
+ case R_ARM_THM_CALL:
+ case R_ARM_THM_JUMP24: {
+ // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
+ // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
+ // FIXME: I1 and I2 require v6T2ops
+ uint16_t Hi = read16le(Buf);
+ uint16_t Lo = read16le(Buf + 2);
+ return SignExtend64<24>(((Hi & 0x0400) << 14) | // S
+ (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
+ (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
+ ((Hi & 0x003ff) << 12) | // imm0
+ ((Lo & 0x007ff) << 1)); // imm11:0
+ }
+ // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
+ // MOVT is in the range -32768 <= A < 32768
+ case R_ARM_MOVW_ABS_NC:
+ case R_ARM_MOVT_ABS:
+ case R_ARM_MOVW_PREL_NC:
+ case R_ARM_MOVT_PREL: {
+ uint64_t Val = read32le(Buf) & 0x000f0fff;
+ return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
+ }
+ case R_ARM_THM_MOVW_ABS_NC:
+ case R_ARM_THM_MOVT_ABS:
+ case R_ARM_THM_MOVW_PREL_NC:
+ case R_ARM_THM_MOVT_PREL: {
+ // Encoding T3: A = imm4:i:imm3:imm8
+ uint16_t Hi = read16le(Buf);
+ uint16_t Lo = read16le(Buf + 2);
+ return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
+ ((Hi & 0x0400) << 1) | // i
+ ((Lo & 0x7000) >> 4) | // imm3
+ (Lo & 0x00ff)); // imm8
+ }
+ }
+}
+
+TargetInfo *elf::createARMTargetInfo() { return make<ARM>(); }
diff --git a/ELF/Arch/AVR.cpp b/ELF/Arch/AVR.cpp
new file mode 100644
index 000000000000..86343a6faa16
--- /dev/null
+++ b/ELF/Arch/AVR.cpp
@@ -0,0 +1,78 @@
+//===- AVR.cpp ------------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// AVR is a Harvard-architecture 8-bit micrcontroller designed for small
+// baremetal programs. All AVR-family processors have 32 8-bit registers.
+// The tiniest AVR has 32 byte RAM and 1 KiB program memory, and the largest
+// one supports up to 2^24 data address space and 2^22 code address space.
+//
+// Since it is a baremetal programming, there's usually no loader to load
+// ELF files on AVRs. You are expected to link your program against address
+// 0 and pull out a .text section from the result using objcopy, so that you
+// can write the linked code to on-chip flush memory. You can do that with
+// the following commands:
+//
+// ld.lld -Ttext=0 -o foo foo.o
+// objcopy -O binary --only-section=.text foo output.bin
+//
+// Note that the current AVR support is very preliminary so you can't
+// link any useful program yet, though.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "InputFiles.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "Target.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class AVR final : public TargetInfo {
+public:
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+};
+} // namespace
+
+RelExpr AVR::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ switch (Type) {
+ case R_AVR_CALL:
+ return R_ABS;
+ default:
+ error(toString(S.File) + ": unknown relocation type: " + toString(Type));
+ return R_HINT;
+ }
+}
+
+void AVR::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ switch (Type) {
+ case R_AVR_CALL: {
+ uint16_t Hi = Val >> 17;
+ uint16_t Lo = Val >> 1;
+ write16le(Loc, read16le(Loc) | ((Hi >> 1) << 4) | (Hi & 1));
+ write16le(Loc + 2, Lo);
+ break;
+ }
+ default:
+ error(getErrorLocation(Loc) + "unrecognized reloc " + toString(Type));
+ }
+}
+
+TargetInfo *elf::createAVRTargetInfo() { return make<AVR>(); }
diff --git a/ELF/Arch/Mips.cpp b/ELF/Arch/Mips.cpp
new file mode 100644
index 000000000000..79642df8a885
--- /dev/null
+++ b/ELF/Arch/Mips.cpp
@@ -0,0 +1,422 @@
+//===- MIPS.cpp -----------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "InputFiles.h"
+#include "Memory.h"
+#include "OutputSections.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+#include "Thunks.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+template <class ELFT> class MIPS final : public TargetInfo {
+public:
+ MIPS();
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+ int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
+ bool isPicRel(uint32_t Type) const override;
+ uint32_t getDynRel(uint32_t Type) const override;
+ void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+ void writePltHeader(uint8_t *Buf) const override;
+ void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+ int32_t Index, unsigned RelOff) const override;
+ bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
+ const SymbolBody &S) const override;
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ bool usesOnlyLowPageBits(uint32_t Type) const override;
+};
+} // namespace
+
+template <class ELFT> MIPS<ELFT>::MIPS() {
+ GotPltHeaderEntriesNum = 2;
+ DefaultMaxPageSize = 65536;
+ GotEntrySize = sizeof(typename ELFT::uint);
+ GotPltEntrySize = sizeof(typename ELFT::uint);
+ PltEntrySize = 16;
+ PltHeaderSize = 32;
+ CopyRel = R_MIPS_COPY;
+ PltRel = R_MIPS_JUMP_SLOT;
+ NeedsThunks = true;
+
+ if (ELFT::Is64Bits) {
+ RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
+ TlsGotRel = R_MIPS_TLS_TPREL64;
+ TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
+ TlsOffsetRel = R_MIPS_TLS_DTPREL64;
+ } else {
+ RelativeRel = R_MIPS_REL32;
+ TlsGotRel = R_MIPS_TLS_TPREL32;
+ TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
+ TlsOffsetRel = R_MIPS_TLS_DTPREL32;
+ }
+}
+
+template <class ELFT>
+RelExpr MIPS<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ // See comment in the calculateMipsRelChain.
+ if (ELFT::Is64Bits || Config->MipsN32Abi)
+ Type &= 0xff;
+ switch (Type) {
+ default:
+ return R_ABS;
+ case R_MIPS_JALR:
+ return R_HINT;
+ case R_MIPS_GPREL16:
+ case R_MIPS_GPREL32:
+ return R_MIPS_GOTREL;
+ case R_MIPS_26:
+ return R_PLT;
+ case R_MIPS_HI16:
+ case R_MIPS_LO16:
+ // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
+ // offset between start of function and 'gp' value which by default
+ // equal to the start of .got section. In that case we consider these
+ // relocations as relative.
+ if (&S == ElfSym::MipsGpDisp)
+ return R_MIPS_GOT_GP_PC;
+ if (&S == ElfSym::MipsLocalGp)
+ return R_MIPS_GOT_GP;
+ LLVM_FALLTHROUGH;
+ case R_MIPS_GOT_OFST:
+ return R_ABS;
+ case R_MIPS_PC32:
+ case R_MIPS_PC16:
+ case R_MIPS_PC19_S2:
+ case R_MIPS_PC21_S2:
+ case R_MIPS_PC26_S2:
+ case R_MIPS_PCHI16:
+ case R_MIPS_PCLO16:
+ return R_PC;
+ case R_MIPS_GOT16:
+ if (S.isLocal())
+ return R_MIPS_GOT_LOCAL_PAGE;
+ LLVM_FALLTHROUGH;
+ case R_MIPS_CALL16:
+ case R_MIPS_GOT_DISP:
+ case R_MIPS_TLS_GOTTPREL:
+ return R_MIPS_GOT_OFF;
+ case R_MIPS_CALL_HI16:
+ case R_MIPS_CALL_LO16:
+ case R_MIPS_GOT_HI16:
+ case R_MIPS_GOT_LO16:
+ return R_MIPS_GOT_OFF32;
+ case R_MIPS_GOT_PAGE:
+ return R_MIPS_GOT_LOCAL_PAGE;
+ case R_MIPS_TLS_GD:
+ return R_MIPS_TLSGD;
+ case R_MIPS_TLS_LDM:
+ return R_MIPS_TLSLD;
+ }
+}
+
+template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const {
+ return Type == R_MIPS_32 || Type == R_MIPS_64;
+}
+
+template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const {
+ return RelativeRel;
+}
+
+template <class ELFT>
+void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
+ write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
+}
+
+template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
+static int64_t getPcRelocAddend(const uint8_t *Loc) {
+ uint32_t Instr = read32<E>(Loc);
+ uint32_t Mask = 0xffffffff >> (32 - BSIZE);
+ return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT);
+}
+
+template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
+static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) {
+ uint32_t Mask = 0xffffffff >> (32 - BSIZE);
+ uint32_t Instr = read32<E>(Loc);
+ if (SHIFT > 0)
+ checkAlignment<(1 << SHIFT)>(Loc, V, Type);
+ checkInt<BSIZE + SHIFT>(Loc, V, Type);
+ write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask));
+}
+
+template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) {
+ uint32_t Instr = read32<E>(Loc);
+ uint16_t Res = ((V + 0x8000) >> 16) & 0xffff;
+ write32<E>(Loc, (Instr & 0xffff0000) | Res);
+}
+
+template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) {
+ uint32_t Instr = read32<E>(Loc);
+ uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff;
+ write32<E>(Loc, (Instr & 0xffff0000) | Res);
+}
+
+template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) {
+ uint32_t Instr = read32<E>(Loc);
+ uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff;
+ write32<E>(Loc, (Instr & 0xffff0000) | Res);
+}
+
+template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) {
+ uint32_t Instr = read32<E>(Loc);
+ write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff));
+}
+
+template <class ELFT> static bool isMipsR6() {
+ const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
+ uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
+ return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
+}
+
+template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
+ const endianness E = ELFT::TargetEndianness;
+ if (Config->MipsN32Abi) {
+ write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0])
+ write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14)
+ write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0])
+ write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14
+ } else {
+ write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0])
+ write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28)
+ write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0])
+ write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28
+ }
+
+ write32<E>(Buf + 16, 0x03e07825); // move $15, $31
+ write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2
+ write32<E>(Buf + 24, 0x0320f809); // jalr $25
+ write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2
+
+ uint64_t GotPlt = InX::GotPlt->getVA();
+ writeMipsHi16<E>(Buf, GotPlt);
+ writeMipsLo16<E>(Buf + 4, GotPlt);
+ writeMipsLo16<E>(Buf + 8, GotPlt);
+}
+
+template <class ELFT>
+void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+ uint64_t PltEntryAddr, int32_t Index,
+ unsigned RelOff) const {
+ const endianness E = ELFT::TargetEndianness;
+ write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry)
+ write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
+ // jr $25
+ write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008);
+ write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
+ writeMipsHi16<E>(Buf, GotPltEntryAddr);
+ writeMipsLo16<E>(Buf + 4, GotPltEntryAddr);
+ writeMipsLo16<E>(Buf + 12, GotPltEntryAddr);
+}
+
+template <class ELFT>
+bool MIPS<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, const InputFile *File,
+ const SymbolBody &S) const {
+ // Any MIPS PIC code function is invoked with its address in register $t9.
+ // So if we have a branch instruction from non-PIC code to the PIC one
+ // we cannot make the jump directly and need to create a small stubs
+ // to save the target function address.
+ // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
+ if (Type != R_MIPS_26)
+ return false;
+ auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
+ if (!F)
+ return false;
+ // If current file has PIC code, LA25 stub is not required.
+ if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
+ return false;
+ auto *D = dyn_cast<DefinedRegular>(&S);
+ // LA25 is required if target file has PIC code
+ // or target symbol is a PIC symbol.
+ return D && D->isMipsPIC<ELFT>();
+}
+
+template <class ELFT>
+int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
+ const endianness E = ELFT::TargetEndianness;
+ switch (Type) {
+ default:
+ return 0;
+ case R_MIPS_32:
+ case R_MIPS_GPREL32:
+ case R_MIPS_TLS_DTPREL32:
+ case R_MIPS_TLS_TPREL32:
+ return SignExtend64<32>(read32<E>(Buf));
+ case R_MIPS_26:
+ // FIXME (simon): If the relocation target symbol is not a PLT entry
+ // we should use another expression for calculation:
+ // ((A << 2) | (P & 0xf0000000)) >> 2
+ return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2);
+ case R_MIPS_GPREL16:
+ case R_MIPS_LO16:
+ case R_MIPS_PCLO16:
+ case R_MIPS_TLS_DTPREL_HI16:
+ case R_MIPS_TLS_DTPREL_LO16:
+ case R_MIPS_TLS_TPREL_HI16:
+ case R_MIPS_TLS_TPREL_LO16:
+ return SignExtend64<16>(read32<E>(Buf));
+ case R_MIPS_PC16:
+ return getPcRelocAddend<E, 16, 2>(Buf);
+ case R_MIPS_PC19_S2:
+ return getPcRelocAddend<E, 19, 2>(Buf);
+ case R_MIPS_PC21_S2:
+ return getPcRelocAddend<E, 21, 2>(Buf);
+ case R_MIPS_PC26_S2:
+ return getPcRelocAddend<E, 26, 2>(Buf);
+ case R_MIPS_PC32:
+ return getPcRelocAddend<E, 32, 0>(Buf);
+ }
+}
+
+static std::pair<uint32_t, uint64_t>
+calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) {
+ // MIPS N64 ABI packs multiple relocations into the single relocation
+ // record. In general, all up to three relocations can have arbitrary
+ // types. In fact, Clang and GCC uses only a few combinations. For now,
+ // we support two of them. That is allow to pass at least all LLVM
+ // test suite cases.
+ // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
+ // <any relocation> / R_MIPS_64 / R_MIPS_NONE
+ // The first relocation is a 'real' relocation which is calculated
+ // using the corresponding symbol's value. The second and the third
+ // relocations used to modify result of the first one: extend it to
+ // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
+ // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
+ uint32_t Type2 = (Type >> 8) & 0xff;
+ uint32_t Type3 = (Type >> 16) & 0xff;
+ if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE)
+ return std::make_pair(Type, Val);
+ if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE)
+ return std::make_pair(Type2, Val);
+ if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16))
+ return std::make_pair(Type3, -Val);
+ error(getErrorLocation(Loc) + "unsupported relocations combination " +
+ Twine(Type));
+ return std::make_pair(Type & 0xff, Val);
+}
+
+template <class ELFT>
+void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ const endianness E = ELFT::TargetEndianness;
+ // Thread pointer and DRP offsets from the start of TLS data area.
+ // https://www.linux-mips.org/wiki/NPTL
+ if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
+ Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64)
+ Val -= 0x8000;
+ else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
+ Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64)
+ Val -= 0x7000;
+ if (ELFT::Is64Bits || Config->MipsN32Abi)
+ std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
+ switch (Type) {
+ case R_MIPS_32:
+ case R_MIPS_GPREL32:
+ case R_MIPS_TLS_DTPREL32:
+ case R_MIPS_TLS_TPREL32:
+ write32<E>(Loc, Val);
+ break;
+ case R_MIPS_64:
+ case R_MIPS_TLS_DTPREL64:
+ case R_MIPS_TLS_TPREL64:
+ write64<E>(Loc, Val);
+ break;
+ case R_MIPS_26:
+ write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff));
+ break;
+ case R_MIPS_GOT16:
+ // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
+ // is updated addend (not a GOT index). In that case write high 16 bits
+ // to store a correct addend value.
+ if (Config->Relocatable)
+ writeMipsHi16<E>(Loc, Val);
+ else {
+ checkInt<16>(Loc, Val, Type);
+ writeMipsLo16<E>(Loc, Val);
+ }
+ break;
+ case R_MIPS_GOT_DISP:
+ case R_MIPS_GOT_PAGE:
+ case R_MIPS_GPREL16:
+ case R_MIPS_TLS_GD:
+ case R_MIPS_TLS_LDM:
+ checkInt<16>(Loc, Val, Type);
+ LLVM_FALLTHROUGH;
+ case R_MIPS_CALL16:
+ case R_MIPS_CALL_LO16:
+ case R_MIPS_GOT_LO16:
+ case R_MIPS_GOT_OFST:
+ case R_MIPS_LO16:
+ case R_MIPS_PCLO16:
+ case R_MIPS_TLS_DTPREL_LO16:
+ case R_MIPS_TLS_GOTTPREL:
+ case R_MIPS_TLS_TPREL_LO16:
+ writeMipsLo16<E>(Loc, Val);
+ break;
+ case R_MIPS_CALL_HI16:
+ case R_MIPS_GOT_HI16:
+ case R_MIPS_HI16:
+ case R_MIPS_PCHI16:
+ case R_MIPS_TLS_DTPREL_HI16:
+ case R_MIPS_TLS_TPREL_HI16:
+ writeMipsHi16<E>(Loc, Val);
+ break;
+ case R_MIPS_HIGHER:
+ writeMipsHigher<E>(Loc, Val);
+ break;
+ case R_MIPS_HIGHEST:
+ writeMipsHighest<E>(Loc, Val);
+ break;
+ case R_MIPS_JALR:
+ // Ignore this optimization relocation for now
+ break;
+ case R_MIPS_PC16:
+ applyMipsPcReloc<E, 16, 2>(Loc, Type, Val);
+ break;
+ case R_MIPS_PC19_S2:
+ applyMipsPcReloc<E, 19, 2>(Loc, Type, Val);
+ break;
+ case R_MIPS_PC21_S2:
+ applyMipsPcReloc<E, 21, 2>(Loc, Type, Val);
+ break;
+ case R_MIPS_PC26_S2:
+ applyMipsPcReloc<E, 26, 2>(Loc, Type, Val);
+ break;
+ case R_MIPS_PC32:
+ applyMipsPcReloc<E, 32, 0>(Loc, Type, Val);
+ break;
+ default:
+ error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+ }
+}
+
+template <class ELFT>
+bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
+ return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST;
+}
+
+template <class ELFT> TargetInfo *elf::createMipsTargetInfo() {
+ return make<MIPS<ELFT>>();
+}
+
+template TargetInfo *elf::createMipsTargetInfo<ELF32LE>();
+template TargetInfo *elf::createMipsTargetInfo<ELF32BE>();
+template TargetInfo *elf::createMipsTargetInfo<ELF64LE>();
+template TargetInfo *elf::createMipsTargetInfo<ELF64BE>();
diff --git a/ELF/Arch/PPC.cpp b/ELF/Arch/PPC.cpp
new file mode 100644
index 000000000000..b5f0d5b4c687
--- /dev/null
+++ b/ELF/Arch/PPC.cpp
@@ -0,0 +1,63 @@
+//===- PPC.cpp ------------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "Target.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class PPC final : public TargetInfo {
+public:
+ PPC() {}
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+};
+} // namespace
+
+void PPC::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ switch (Type) {
+ case R_PPC_ADDR16_HA:
+ write16be(Loc, (Val + 0x8000) >> 16);
+ break;
+ case R_PPC_ADDR16_LO:
+ write16be(Loc, Val);
+ break;
+ case R_PPC_ADDR32:
+ case R_PPC_REL32:
+ write32be(Loc, Val);
+ break;
+ case R_PPC_REL24:
+ write32be(Loc, read32be(Loc) | (Val & 0x3FFFFFC));
+ break;
+ default:
+ error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+ }
+}
+
+RelExpr PPC::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ switch (Type) {
+ case R_PPC_REL24:
+ case R_PPC_REL32:
+ return R_PC;
+ default:
+ return R_ABS;
+ }
+}
+
+TargetInfo *elf::createPPCTargetInfo() { return make<PPC>(); }
diff --git a/ELF/Arch/PPC64.cpp b/ELF/Arch/PPC64.cpp
new file mode 100644
index 000000000000..eb1e917d5790
--- /dev/null
+++ b/ELF/Arch/PPC64.cpp
@@ -0,0 +1,215 @@
+//===- PPC64.cpp ----------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+static uint64_t PPC64TocOffset = 0x8000;
+
+uint64_t elf::getPPC64TocBase() {
+ // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
+ // TOC starts where the first of these sections starts. We always create a
+ // .got when we see a relocation that uses it, so for us the start is always
+ // the .got.
+ uint64_t TocVA = InX::Got->getVA();
+
+ // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
+ // thus permitting a full 64 Kbytes segment. Note that the glibc startup
+ // code (crt1.o) assumes that you can get from the TOC base to the
+ // start of the .toc section with only a single (signed) 16-bit relocation.
+ return TocVA + PPC64TocOffset;
+}
+
+namespace {
+class PPC64 final : public TargetInfo {
+public:
+ PPC64();
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+ void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+ int32_t Index, unsigned RelOff) const override;
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+};
+} // namespace
+
+// Relocation masks following the #lo(value), #hi(value), #ha(value),
+// #higher(value), #highera(value), #highest(value), and #highesta(value)
+// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
+// document.
+static uint16_t applyPPCLo(uint64_t V) { return V; }
+static uint16_t applyPPCHi(uint64_t V) { return V >> 16; }
+static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; }
+static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; }
+static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; }
+static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; }
+static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; }
+
+PPC64::PPC64() {
+ PltRel = GotRel = R_PPC64_GLOB_DAT;
+ RelativeRel = R_PPC64_RELATIVE;
+ GotEntrySize = 8;
+ GotPltEntrySize = 8;
+ PltEntrySize = 32;
+ PltHeaderSize = 0;
+
+ // We need 64K pages (at least under glibc/Linux, the loader won't
+ // set different permissions on a finer granularity than that).
+ DefaultMaxPageSize = 65536;
+
+ // The PPC64 ELF ABI v1 spec, says:
+ //
+ // It is normally desirable to put segments with different characteristics
+ // in separate 256 Mbyte portions of the address space, to give the
+ // operating system full paging flexibility in the 64-bit address space.
+ //
+ // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
+ // use 0x10000000 as the starting address.
+ DefaultImageBase = 0x10000000;
+}
+
+RelExpr PPC64::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ switch (Type) {
+ default:
+ return R_ABS;
+ case R_PPC64_TOC16:
+ case R_PPC64_TOC16_DS:
+ case R_PPC64_TOC16_HA:
+ case R_PPC64_TOC16_HI:
+ case R_PPC64_TOC16_LO:
+ case R_PPC64_TOC16_LO_DS:
+ return R_GOTREL;
+ case R_PPC64_TOC:
+ return R_PPC_TOC;
+ case R_PPC64_REL24:
+ return R_PPC_PLT_OPD;
+ }
+}
+
+void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+ uint64_t PltEntryAddr, int32_t Index,
+ unsigned RelOff) const {
+ uint64_t Off = GotPltEntryAddr - getPPC64TocBase();
+
+ // FIXME: What we should do, in theory, is get the offset of the function
+ // descriptor in the .opd section, and use that as the offset from %r2 (the
+ // TOC-base pointer). Instead, we have the GOT-entry offset, and that will
+ // be a pointer to the function descriptor in the .opd section. Using
+ // this scheme is simpler, but requires an extra indirection per PLT dispatch.
+
+ write32be(Buf, 0xf8410028); // std %r2, 40(%r1)
+ write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha
+ write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11)
+ write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12)
+ write32be(Buf + 16, 0x7d6903a6); // mtctr %r11
+ write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12)
+ write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12)
+ write32be(Buf + 28, 0x4e800420); // bctr
+}
+
+static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) {
+ uint64_t V = Val - PPC64TocOffset;
+ switch (Type) {
+ case R_PPC64_TOC16:
+ return {R_PPC64_ADDR16, V};
+ case R_PPC64_TOC16_DS:
+ return {R_PPC64_ADDR16_DS, V};
+ case R_PPC64_TOC16_HA:
+ return {R_PPC64_ADDR16_HA, V};
+ case R_PPC64_TOC16_HI:
+ return {R_PPC64_ADDR16_HI, V};
+ case R_PPC64_TOC16_LO:
+ return {R_PPC64_ADDR16_LO, V};
+ case R_PPC64_TOC16_LO_DS:
+ return {R_PPC64_ADDR16_LO_DS, V};
+ default:
+ return {Type, Val};
+ }
+}
+
+void PPC64::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ // For a TOC-relative relocation, proceed in terms of the corresponding
+ // ADDR16 relocation type.
+ std::tie(Type, Val) = toAddr16Rel(Type, Val);
+
+ switch (Type) {
+ case R_PPC64_ADDR14: {
+ checkAlignment<4>(Loc, Val, Type);
+ // Preserve the AA/LK bits in the branch instruction
+ uint8_t AALK = Loc[3];
+ write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc));
+ break;
+ }
+ case R_PPC64_ADDR16:
+ checkInt<16>(Loc, Val, Type);
+ write16be(Loc, Val);
+ break;
+ case R_PPC64_ADDR16_DS:
+ checkInt<16>(Loc, Val, Type);
+ write16be(Loc, (read16be(Loc) & 3) | (Val & ~3));
+ break;
+ case R_PPC64_ADDR16_HA:
+ case R_PPC64_REL16_HA:
+ write16be(Loc, applyPPCHa(Val));
+ break;
+ case R_PPC64_ADDR16_HI:
+ case R_PPC64_REL16_HI:
+ write16be(Loc, applyPPCHi(Val));
+ break;
+ case R_PPC64_ADDR16_HIGHER:
+ write16be(Loc, applyPPCHigher(Val));
+ break;
+ case R_PPC64_ADDR16_HIGHERA:
+ write16be(Loc, applyPPCHighera(Val));
+ break;
+ case R_PPC64_ADDR16_HIGHEST:
+ write16be(Loc, applyPPCHighest(Val));
+ break;
+ case R_PPC64_ADDR16_HIGHESTA:
+ write16be(Loc, applyPPCHighesta(Val));
+ break;
+ case R_PPC64_ADDR16_LO:
+ write16be(Loc, applyPPCLo(Val));
+ break;
+ case R_PPC64_ADDR16_LO_DS:
+ case R_PPC64_REL16_LO:
+ write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3));
+ break;
+ case R_PPC64_ADDR32:
+ case R_PPC64_REL32:
+ checkInt<32>(Loc, Val, Type);
+ write32be(Loc, Val);
+ break;
+ case R_PPC64_ADDR64:
+ case R_PPC64_REL64:
+ case R_PPC64_TOC:
+ write64be(Loc, Val);
+ break;
+ case R_PPC64_REL24: {
+ uint32_t Mask = 0x03FFFFFC;
+ checkInt<24>(Loc, Val, Type);
+ write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask));
+ break;
+ }
+ default:
+ error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+ }
+}
+
+TargetInfo *elf::createPPC64TargetInfo() { return make<PPC64>(); }
diff --git a/ELF/Arch/X86.cpp b/ELF/Arch/X86.cpp
new file mode 100644
index 000000000000..bc0d2b81a613
--- /dev/null
+++ b/ELF/Arch/X86.cpp
@@ -0,0 +1,363 @@
+//===- X86.cpp ------------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "InputFiles.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class X86 final : public TargetInfo {
+public:
+ X86();
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+ int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
+ void writeGotPltHeader(uint8_t *Buf) const override;
+ uint32_t getDynRel(uint32_t Type) const override;
+ void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+ void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+ void writePltHeader(uint8_t *Buf) const override;
+ void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+ int32_t Index, unsigned RelOff) const override;
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+
+ RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
+ RelExpr Expr) const override;
+ void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+};
+} // namespace
+
+X86::X86() {
+ CopyRel = R_386_COPY;
+ GotRel = R_386_GLOB_DAT;
+ PltRel = R_386_JUMP_SLOT;
+ IRelativeRel = R_386_IRELATIVE;
+ RelativeRel = R_386_RELATIVE;
+ TlsGotRel = R_386_TLS_TPOFF;
+ TlsModuleIndexRel = R_386_TLS_DTPMOD32;
+ TlsOffsetRel = R_386_TLS_DTPOFF32;
+ GotEntrySize = 4;
+ GotPltEntrySize = 4;
+ PltEntrySize = 16;
+ PltHeaderSize = 16;
+ TlsGdRelaxSkip = 2;
+
+ // 0xCC is the "int3" (call debug exception handler) instruction.
+ TrapInstr = 0xcccccccc;
+}
+
+RelExpr X86::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ switch (Type) {
+ case R_386_8:
+ case R_386_16:
+ case R_386_32:
+ case R_386_TLS_LDO_32:
+ return R_ABS;
+ case R_386_TLS_GD:
+ return R_TLSGD;
+ case R_386_TLS_LDM:
+ return R_TLSLD;
+ case R_386_PLT32:
+ return R_PLT_PC;
+ case R_386_PC8:
+ case R_386_PC16:
+ case R_386_PC32:
+ return R_PC;
+ case R_386_GOTPC:
+ return R_GOTONLY_PC_FROM_END;
+ case R_386_TLS_IE:
+ return R_GOT;
+ case R_386_GOT32:
+ case R_386_GOT32X:
+ // These relocations can be calculated in two different ways.
+ // Usual calculation is G + A - GOT what means an offset in GOT table
+ // (R_GOT_FROM_END). When instruction pointed by relocation has no base
+ // register, then relocations can be used when PIC code is disabled. In that
+ // case calculation is G + A, it resolves to an address of entry in GOT
+ // (R_GOT) and not an offset.
+ //
+ // To check that instruction has no base register we scan ModR/M byte.
+ // See "Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte"
+ // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/
+ // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf)
+ if ((Loc[-1] & 0xc7) != 0x5)
+ return R_GOT_FROM_END;
+ if (Config->Pic)
+ error(toString(S.File) + ": relocation " + toString(Type) + " against '" +
+ S.getName() +
+ "' without base register can not be used when PIC enabled");
+ return R_GOT;
+ case R_386_TLS_GOTIE:
+ return R_GOT_FROM_END;
+ case R_386_GOTOFF:
+ return R_GOTREL_FROM_END;
+ case R_386_TLS_LE:
+ return R_TLS;
+ case R_386_TLS_LE_32:
+ return R_NEG_TLS;
+ case R_386_NONE:
+ return R_NONE;
+ default:
+ error(toString(S.File) + ": unknown relocation type: " + toString(Type));
+ return R_HINT;
+ }
+}
+
+RelExpr X86::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
+ RelExpr Expr) const {
+ switch (Expr) {
+ default:
+ return Expr;
+ case R_RELAX_TLS_GD_TO_IE:
+ return R_RELAX_TLS_GD_TO_IE_END;
+ case R_RELAX_TLS_GD_TO_LE:
+ return R_RELAX_TLS_GD_TO_LE_NEG;
+ }
+}
+
+void X86::writeGotPltHeader(uint8_t *Buf) const {
+ write32le(Buf, InX::Dynamic->getVA());
+}
+
+void X86::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {
+ // Entries in .got.plt initially points back to the corresponding
+ // PLT entries with a fixed offset to skip the first instruction.
+ write32le(Buf, S.getPltVA() + 6);
+}
+
+void X86::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const {
+ // An x86 entry is the address of the ifunc resolver function.
+ write32le(Buf, S.getVA());
+}
+
+uint32_t X86::getDynRel(uint32_t Type) const {
+ if (Type == R_386_TLS_LE)
+ return R_386_TLS_TPOFF;
+ if (Type == R_386_TLS_LE_32)
+ return R_386_TLS_TPOFF32;
+ return Type;
+}
+
+void X86::writePltHeader(uint8_t *Buf) const {
+ if (Config->Pic) {
+ const uint8_t V[] = {
+ 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl GOTPLT+4(%ebx)
+ 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *GOTPLT+8(%ebx)
+ 0x90, 0x90, 0x90, 0x90 // nop
+ };
+ memcpy(Buf, V, sizeof(V));
+
+ uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
+ uint32_t GotPlt = InX::GotPlt->getVA() - Ebx;
+ write32le(Buf + 2, GotPlt + 4);
+ write32le(Buf + 8, GotPlt + 8);
+ return;
+ }
+
+ const uint8_t PltData[] = {
+ 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOTPLT+4)
+ 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOTPLT+8)
+ 0x90, 0x90, 0x90, 0x90 // nop
+ };
+ memcpy(Buf, PltData, sizeof(PltData));
+ uint32_t GotPlt = InX::GotPlt->getVA();
+ write32le(Buf + 2, GotPlt + 4);
+ write32le(Buf + 8, GotPlt + 8);
+}
+
+void X86::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+ uint64_t PltEntryAddr, int32_t Index,
+ unsigned RelOff) const {
+ const uint8_t Inst[] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx)
+ 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset
+ 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC
+ };
+ memcpy(Buf, Inst, sizeof(Inst));
+
+ if (Config->Pic) {
+ // jmp *foo@GOT(%ebx)
+ uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
+ Buf[1] = 0xa3;
+ write32le(Buf + 2, GotPltEntryAddr - Ebx);
+ } else {
+ // jmp *foo_in_GOT
+ Buf[1] = 0x25;
+ write32le(Buf + 2, GotPltEntryAddr);
+ }
+
+ write32le(Buf + 7, RelOff);
+ write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
+}
+
+int64_t X86::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
+ switch (Type) {
+ default:
+ return 0;
+ case R_386_8:
+ case R_386_PC8:
+ return SignExtend64<8>(*Buf);
+ case R_386_16:
+ case R_386_PC16:
+ return SignExtend64<16>(read16le(Buf));
+ case R_386_32:
+ case R_386_GOT32:
+ case R_386_GOT32X:
+ case R_386_GOTOFF:
+ case R_386_GOTPC:
+ case R_386_PC32:
+ case R_386_PLT32:
+ case R_386_TLS_LDO_32:
+ case R_386_TLS_LE:
+ return SignExtend64<32>(read32le(Buf));
+ }
+}
+
+void X86::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ // R_386_{PC,}{8,16} are not part of the i386 psABI, but they are
+ // being used for some 16-bit programs such as boot loaders, so
+ // we want to support them.
+ switch (Type) {
+ case R_386_8:
+ checkUInt<8>(Loc, Val, Type);
+ *Loc = Val;
+ break;
+ case R_386_PC8:
+ checkInt<8>(Loc, Val, Type);
+ *Loc = Val;
+ break;
+ case R_386_16:
+ checkUInt<16>(Loc, Val, Type);
+ write16le(Loc, Val);
+ break;
+ case R_386_PC16:
+ // R_386_PC16 is normally used with 16 bit code. In that situation
+ // the PC is 16 bits, just like the addend. This means that it can
+ // point from any 16 bit address to any other if the possibility
+ // of wrapping is included.
+ // The only restriction we have to check then is that the destination
+ // address fits in 16 bits. That is impossible to do here. The problem is
+ // that we are passed the final value, which already had the
+ // current location subtracted from it.
+ // We just check that Val fits in 17 bits. This misses some cases, but
+ // should have no false positives.
+ checkInt<17>(Loc, Val, Type);
+ write16le(Loc, Val);
+ break;
+ default:
+ checkInt<32>(Loc, Val, Type);
+ write32le(Loc, Val);
+ }
+}
+
+void X86::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ // Convert
+ // leal x@tlsgd(, %ebx, 1),
+ // call __tls_get_addr@plt
+ // to
+ // movl %gs:0,%eax
+ // subl $x@ntpoff,%eax
+ const uint8_t Inst[] = {
+ 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
+ 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax
+ };
+ memcpy(Loc - 3, Inst, sizeof(Inst));
+ write32le(Loc + 5, Val);
+}
+
+void X86::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ // Convert
+ // leal x@tlsgd(, %ebx, 1),
+ // call __tls_get_addr@plt
+ // to
+ // movl %gs:0, %eax
+ // addl x@gotntpoff(%ebx), %eax
+ const uint8_t Inst[] = {
+ 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
+ 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax
+ };
+ memcpy(Loc - 3, Inst, sizeof(Inst));
+ write32le(Loc + 5, Val);
+}
+
+// In some conditions, relocations can be optimized to avoid using GOT.
+// This function does that for Initial Exec to Local Exec case.
+void X86::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ // Ulrich's document section 6.2 says that @gotntpoff can
+ // be used with MOVL or ADDL instructions.
+ // @indntpoff is similar to @gotntpoff, but for use in
+ // position dependent code.
+ uint8_t Reg = (Loc[-1] >> 3) & 7;
+
+ if (Type == R_386_TLS_IE) {
+ if (Loc[-1] == 0xa1) {
+ // "movl foo@indntpoff,%eax" -> "movl $foo,%eax"
+ // This case is different from the generic case below because
+ // this is a 5 byte instruction while below is 6 bytes.
+ Loc[-1] = 0xb8;
+ } else if (Loc[-2] == 0x8b) {
+ // "movl foo@indntpoff,%reg" -> "movl $foo,%reg"
+ Loc[-2] = 0xc7;
+ Loc[-1] = 0xc0 | Reg;
+ } else {
+ // "addl foo@indntpoff,%reg" -> "addl $foo,%reg"
+ Loc[-2] = 0x81;
+ Loc[-1] = 0xc0 | Reg;
+ }
+ } else {
+ assert(Type == R_386_TLS_GOTIE);
+ if (Loc[-2] == 0x8b) {
+ // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg"
+ Loc[-2] = 0xc7;
+ Loc[-1] = 0xc0 | Reg;
+ } else {
+ // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg"
+ Loc[-2] = 0x8d;
+ Loc[-1] = 0x80 | (Reg << 3) | Reg;
+ }
+ }
+ write32le(Loc, Val);
+}
+
+void X86::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+ if (Type == R_386_TLS_LDO_32) {
+ write32le(Loc, Val);
+ return;
+ }
+
+ // Convert
+ // leal foo(%reg),%eax
+ // call ___tls_get_addr
+ // to
+ // movl %gs:0,%eax
+ // nop
+ // leal 0(%esi,1),%esi
+ const uint8_t Inst[] = {
+ 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax
+ 0x90, // nop
+ 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi
+ };
+ memcpy(Loc - 2, Inst, sizeof(Inst));
+}
+
+TargetInfo *elf::createX86TargetInfo() { return make<X86>(); }
diff --git a/ELF/Arch/X86_64.cpp b/ELF/Arch/X86_64.cpp
new file mode 100644
index 000000000000..b790868c7125
--- /dev/null
+++ b/ELF/Arch/X86_64.cpp
@@ -0,0 +1,468 @@
+//===- X86_64.cpp ---------------------------------------------------------===//
+//
+// The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "InputFiles.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+template <class ELFT> class X86_64 final : public TargetInfo {
+public:
+ X86_64();
+ RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const override;
+ bool isPicRel(uint32_t Type) const override;
+ void writeGotPltHeader(uint8_t *Buf) const override;
+ void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+ void writePltHeader(uint8_t *Buf) const override;
+ void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+ int32_t Index, unsigned RelOff) const override;
+ void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+
+ RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
+ RelExpr Expr) const override;
+ void relaxGot(uint8_t *Loc, uint64_t Val) const override;
+ void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+ void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+
+private:
+ void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
+ uint8_t ModRm) const;
+};
+} // namespace
+
+template <class ELFT> X86_64<ELFT>::X86_64() {
+ CopyRel = R_X86_64_COPY;
+ GotRel = R_X86_64_GLOB_DAT;
+ PltRel = R_X86_64_JUMP_SLOT;
+ RelativeRel = R_X86_64_RELATIVE;
+ IRelativeRel = R_X86_64_IRELATIVE;
+ TlsGotRel = R_X86_64_TPOFF64;
+ TlsModuleIndexRel = R_X86_64_DTPMOD64;
+ TlsOffsetRel = R_X86_64_DTPOFF64;
+ GotEntrySize = 8;
+ GotPltEntrySize = 8;
+ PltEntrySize = 16;
+ PltHeaderSize = 16;
+ TlsGdRelaxSkip = 2;
+
+ // Align to the large page size (known as a superpage or huge page).
+ // FreeBSD automatically promotes large, superpage-aligned allocations.
+ DefaultImageBase = 0x200000;
+
+ // 0xCC is the "int3" (call debug exception handler) instruction.
+ TrapInstr = 0xcccccccc;
+}
+
+template <class ELFT>
+RelExpr X86_64<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S,
+ const uint8_t *Loc) const {
+ switch (Type) {
+ case R_X86_64_8:
+ case R_X86_64_16:
+ case R_X86_64_32:
+ case R_X86_64_32S:
+ case R_X86_64_64:
+ case R_X86_64_DTPOFF32:
+ case R_X86_64_DTPOFF64:
+ return R_ABS;
+ case R_X86_64_TPOFF32:
+ return R_TLS;
+ case R_X86_64_TLSLD:
+ return R_TLSLD_PC;
+ case R_X86_64_TLSGD:
+ return R_TLSGD_PC;
+ case R_X86_64_SIZE32:
+ case R_X86_64_SIZE64:
+ return R_SIZE;
+ case R_X86_64_PLT32:
+ return R_PLT_PC;
+ case R_X86_64_PC32:
+ case R_X86_64_PC64:
+ return R_PC;
+ case R_X86_64_GOT32:
+ case R_X86_64_GOT64:
+ return R_GOT_FROM_END;
+ case R_X86_64_GOTPCREL:
+ case R_X86_64_GOTPCRELX:
+ case R_X86_64_REX_GOTPCRELX:
+ case R_X86_64_GOTTPOFF:
+ return R_GOT_PC;
+ case R_X86_64_NONE:
+ return R_NONE;
+ default:
+ error(toString(S.File) + ": unknown relocation type: " + toString(Type));
+ return R_HINT;
+ }
+}
+
+template <class ELFT> void X86_64<ELFT>::writeGotPltHeader(uint8_t *Buf) const {
+ // The first entry holds the value of _DYNAMIC. It is not clear why that is
+ // required, but it is documented in the psabi and the glibc dynamic linker
+ // seems to use it (note that this is relevant for linking ld.so, not any
+ // other program).
+ write64le(Buf, InX::Dynamic->getVA());
+}
+
+template <class ELFT>
+void X86_64<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {
+ // See comments in X86TargetInfo::writeGotPlt.
+ write32le(Buf, S.getPltVA() + 6);
+}
+
+template <class ELFT> void X86_64<ELFT>::writePltHeader(uint8_t *Buf) const {
+ const uint8_t PltData[] = {
+ 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOTPLT+8(%rip)
+ 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOTPLT+16(%rip)
+ 0x0f, 0x1f, 0x40, 0x00 // nop
+ };
+ memcpy(Buf, PltData, sizeof(PltData));
+ uint64_t GotPlt = InX::GotPlt->getVA();
+ uint64_t Plt = InX::Plt->getVA();
+ write32le(Buf + 2, GotPlt - Plt + 2); // GOTPLT+8
+ write32le(Buf + 8, GotPlt - Plt + 4); // GOTPLT+16
+}
+
+template <class ELFT>
+void X86_64<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+ uint64_t PltEntryAddr, int32_t Index,
+ unsigned RelOff) const {
+ const uint8_t Inst[] = {
+ 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip)
+ 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index>
+ 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0]
+ };
+ memcpy(Buf, Inst, sizeof(Inst));
+
+ write32le(Buf + 2, GotPltEntryAddr - PltEntryAddr - 6);
+ write32le(Buf + 7, Index);
+ write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
+}
+
+template <class ELFT> bool X86_64<ELFT>::isPicRel(uint32_t Type) const {
+ return Type != R_X86_64_PC32 && Type != R_X86_64_32 &&
+ Type != R_X86_64_TPOFF32;
+}
+
+template <class ELFT>
+void X86_64<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
+ uint64_t Val) const {
+ // Convert
+ // .byte 0x66
+ // leaq x@tlsgd(%rip), %rdi
+ // .word 0x6666
+ // rex64
+ // call __tls_get_addr@plt
+ // to
+ // mov %fs:0x0,%rax
+ // lea x@tpoff,%rax
+ const uint8_t Inst[] = {
+ 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
+ 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax
+ };
+ memcpy(Loc - 4, Inst, sizeof(Inst));
+
+ // The original code used a pc relative relocation and so we have to
+ // compensate for the -4 in had in the addend.
+ write32le(Loc + 8, Val + 4);
+}
+
+template <class ELFT>
+void X86_64<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
+ uint64_t Val) const {
+ // Convert
+ // .byte 0x66
+ // leaq x@tlsgd(%rip), %rdi
+ // .word 0x6666
+ // rex64
+ // call __tls_get_addr@plt
+ // to
+ // mov %fs:0x0,%rax
+ // addq x@tpoff,%rax
+ const uint8_t Inst[] = {
+ 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
+ 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax
+ };
+ memcpy(Loc - 4, Inst, sizeof(Inst));
+
+ // Both code sequences are PC relatives, but since we are moving the constant
+ // forward by 8 bytes we have to subtract the value by 8.
+ write32le(Loc + 8, Val - 8);
+}
+
+// In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to
+// R_X86_64_TPOFF32 so that it does not use GOT.
+template <class ELFT>
+void X86_64<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
+ uint64_t Val) const {
+ uint8_t *Inst = Loc - 3;
+ uint8_t Reg = Loc[-1] >> 3;
+ uint8_t *RegSlot = Loc - 1;
+
+ // Note that ADD with RSP or R12 is converted to ADD instead of LEA
+ // because LEA with these registers needs 4 bytes to encode and thus
+ // wouldn't fit the space.
+
+ if (memcmp(Inst, "\x48\x03\x25", 3) == 0) {
+ // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp"
+ memcpy(Inst, "\x48\x81\xc4", 3);
+ } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) {
+ // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12"
+ memcpy(Inst, "\x49\x81\xc4", 3);
+ } else if (memcmp(Inst, "\x4c\x03", 2) == 0) {
+ // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]"
+ memcpy(Inst, "\x4d\x8d", 2);
+ *RegSlot = 0x80 | (Reg << 3) | Reg;
+ } else if (memcmp(Inst, "\x48\x03", 2) == 0) {
+ // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg"
+ memcpy(Inst, "\x48\x8d", 2);
+ *RegSlot = 0x80 | (Reg << 3) | Reg;
+ } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) {
+ // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
+ memcpy(Inst, "\x49\xc7", 2);
+ *RegSlot = 0xc0 | Reg;
+ } else if (memcmp(Inst, "\x48\x8b", 2) == 0) {
+ // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
+ memcpy(Inst, "\x48\xc7", 2);
+ *RegSlot = 0xc0 | Reg;
+ } else {
+ error(getErrorLocation(Loc - 3) +
+ "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only");
+ }
+
+ // The original code used a PC relative relocation.
+ // Need to compensate for the -4 it had in the addend.
+ write32le(Loc, Val + 4);
+}
+
+template <class ELFT>
+void X86_64<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
+ uint64_t Val) const {
+ // Convert
+ // leaq bar@tlsld(%rip), %rdi
+ // callq __tls_get_addr@PLT
+ // leaq bar@dtpoff(%rax), %rcx
+ // to
+ // .word 0x6666
+ // .byte 0x66
+ // mov %fs:0,%rax
+ // leaq bar@tpoff(%rax), %rcx
+ if (Type == R_X86_64_DTPOFF64) {
+ write64le(Loc, Val);
+ return;
+ }
+ if (Type == R_X86_64_DTPOFF32) {
+ write32le(Loc, Val);
+ return;
+ }
+
+ const uint8_t Inst[] = {
+ 0x66, 0x66, // .word 0x6666
+ 0x66, // .byte 0x66
+ 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax
+ };
+ memcpy(Loc - 3, Inst, sizeof(Inst));
+}
+
+template <class ELFT>
+void X86_64<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
+ uint64_t Val) const {
+ switch (Type) {
+ case R_X86_64_8:
+ checkUInt<8>(Loc, Val, Type);
+ *Loc = Val;
+ break;
+ case R_X86_64_16:
+ checkUInt<16>(Loc, Val, Type);
+ write16le(Loc, Val);
+ break;
+ case R_X86_64_32:
+ checkUInt<32>(Loc, Val, Type);
+ write32le(Loc, Val);
+ break;
+ case R_X86_64_32S:
+ case R_X86_64_TPOFF32:
+ case R_X86_64_GOT32:
+ case R_X86_64_GOTPCREL:
+ case R_X86_64_GOTPCRELX:
+ case R_X86_64_REX_GOTPCRELX:
+ case R_X86_64_PC32:
+ case R_X86_64_GOTTPOFF:
+ case R_X86_64_PLT32:
+ case R_X86_64_TLSGD:
+ case R_X86_64_TLSLD:
+ case R_X86_64_DTPOFF32:
+ case R_X86_64_SIZE32:
+ checkInt<32>(Loc, Val, Type);
+ write32le(Loc, Val);
+ break;
+ case R_X86_64_64:
+ case R_X86_64_DTPOFF64:
+ case R_X86_64_GLOB_DAT:
+ case R_X86_64_PC64:
+ case R_X86_64_SIZE64:
+ case R_X86_64_GOT64:
+ write64le(Loc, Val);
+ break;
+ default:
+ llvm_unreachable("unexpected relocation");
+ }
+}
+
+template <class ELFT>
+RelExpr X86_64<ELFT>::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
+ RelExpr RelExpr) const {
+ if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX)
+ return RelExpr;
+ const uint8_t Op = Data[-2];
+ const uint8_t ModRm = Data[-1];
+
+ // FIXME: When PIC is disabled and foo is defined locally in the
+ // lower 32 bit address space, memory operand in mov can be converted into
+ // immediate operand. Otherwise, mov must be changed to lea. We support only
+ // latter relaxation at this moment.
+ if (Op == 0x8b)
+ return R_RELAX_GOT_PC;
+
+ // Relax call and jmp.
+ if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25))
+ return R_RELAX_GOT_PC;
+
+ // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor.
+ // If PIC then no relaxation is available.
+ // We also don't relax test/binop instructions without REX byte,
+ // they are 32bit operations and not common to have.
+ assert(Type == R_X86_64_REX_GOTPCRELX);
+ return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC;
+}
+
+// A subset of relaxations can only be applied for no-PIC. This method
+// handles such relaxations. Instructions encoding information was taken from:
+// "Intel 64 and IA-32 Architectures Software Developer's Manual V2"
+// (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/
+// 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf)
+template <class ELFT>
+void X86_64<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
+ uint8_t ModRm) const {
+ const uint8_t Rex = Loc[-3];
+ // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg".
+ if (Op == 0x85) {
+ // See "TEST-Logical Compare" (4-428 Vol. 2B),
+ // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension).
+
+ // ModR/M byte has form XX YYY ZZZ, where
+ // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1).
+ // XX has different meanings:
+ // 00: The operand's memory address is in reg1.
+ // 01: The operand's memory address is reg1 + a byte-sized displacement.
+ // 10: The operand's memory address is reg1 + a word-sized displacement.
+ // 11: The operand is reg1 itself.
+ // If an instruction requires only one operand, the unused reg2 field
+ // holds extra opcode bits rather than a register code
+ // 0xC0 == 11 000 000 binary.
+ // 0x38 == 00 111 000 binary.
+ // We transfer reg2 to reg1 here as operand.
+ // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3).
+ Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte.
+
+ // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32
+ // See "TEST-Logical Compare" (4-428 Vol. 2B).
+ Loc[-2] = 0xf7;
+
+ // Move R bit to the B bit in REX byte.
+ // REX byte is encoded as 0100WRXB, where
+ // 0100 is 4bit fixed pattern.
+ // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the
+ // default operand size is used (which is 32-bit for most but not all
+ // instructions).
+ // REX.R This 1-bit value is an extension to the MODRM.reg field.
+ // REX.X This 1-bit value is an extension to the SIB.index field.
+ // REX.B This 1-bit value is an extension to the MODRM.rm field or the
+ // SIB.base field.
+ // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A).
+ Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
+ write32le(Loc, Val);
+ return;
+ }
+
+ // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub
+ // or xor operations.
+
+ // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg".
+ // Logic is close to one for test instruction above, but we also
+ // write opcode extension here, see below for details.
+ Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte.
+
+ // Primary opcode is 0x81, opcode extension is one of:
+ // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB,
+ // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP.
+ // This value was wrote to MODRM.reg in a line above.
+ // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15),
+ // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for
+ // descriptions about each operation.
+ Loc[-2] = 0x81;
+ Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
+ write32le(Loc, Val);
+}
+
+template <class ELFT>
+void X86_64<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const {
+ const uint8_t Op = Loc[-2];
+ const uint8_t ModRm = Loc[-1];
+
+ // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg".
+ if (Op == 0x8b) {
+ Loc[-2] = 0x8d;
+ write32le(Loc, Val);
+ return;
+ }
+
+ if (Op != 0xff) {
+ // We are relaxing a rip relative to an absolute, so compensate
+ // for the old -4 addend.
+ assert(!Config->Pic);
+ relaxGotNoPic(Loc, Val + 4, Op, ModRm);
+ return;
+ }
+
+ // Convert call/jmp instructions.
+ if (ModRm == 0x15) {
+ // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo".
+ // Instead we convert to "addr32 call foo" where addr32 is an instruction
+ // prefix. That makes result expression to be a single instruction.
+ Loc[-2] = 0x67; // addr32 prefix
+ Loc[-1] = 0xe8; // call
+ write32le(Loc, Val);
+ return;
+ }
+
+ // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop".
+ // jmp doesn't return, so it is fine to use nop here, it is just a stub.
+ assert(ModRm == 0x25);
+ Loc[-2] = 0xe9; // jmp
+ Loc[3] = 0x90; // nop
+ write32le(Loc - 1, Val + 1);
+}
+
+TargetInfo *elf::createX32TargetInfo() { return make<X86_64<ELF32LE>>(); }
+TargetInfo *elf::createX86_64TargetInfo() { return make<X86_64<ELF64LE>>(); }
diff --git a/ELF/CMakeLists.txt b/ELF/CMakeLists.txt
index c852198bb240..09a19fee14b2 100644
--- a/ELF/CMakeLists.txt
+++ b/ELF/CMakeLists.txt
@@ -7,6 +7,15 @@ if(NOT LLD_BUILT_STANDALONE)
endif()
add_lld_library(lldELF
+ Arch/AArch64.cpp
+ Arch/AMDGPU.cpp
+ Arch/ARM.cpp
+ Arch/AVR.cpp
+ Arch/Mips.cpp
+ Arch/PPC.cpp
+ Arch/PPC64.cpp
+ Arch/X86.cpp
+ Arch/X86_64.cpp
Driver.cpp
DriverUtils.cpp
EhFrame.cpp
diff --git a/ELF/Driver.cpp b/ELF/Driver.cpp
index f3943b5cf655..f24c941fe773 100644
--- a/ELF/Driver.cpp
+++ b/ELF/Driver.cpp
@@ -36,6 +36,7 @@
#include "ScriptParser.h"
#include "Strings.h"
#include "SymbolTable.h"
+#include "SyntheticSections.h"
#include "Target.h"
#include "Threads.h"
#include "Writer.h"
@@ -43,7 +44,6 @@
#include "lld/Driver/Driver.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
-#include "llvm/Object/Decompressor.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compression.h"
#include "llvm/Support/Path.h"
@@ -99,7 +99,7 @@ static std::tuple<ELFKind, uint16_t, uint8_t> parseEmulation(StringRef Emul) {
std::pair<ELFKind, uint16_t> Ret =
StringSwitch<std::pair<ELFKind, uint16_t>>(S)
.Cases("aarch64elf", "aarch64linux", {ELF64LEKind, EM_AARCH64})
- .Case("armelf_linux_eabi", {ELF32LEKind, EM_ARM})
+ .Cases("armelf", "armelf_linux_eabi", {ELF32LEKind, EM_ARM})
.Case("elf32_x86_64", {ELF32LEKind, EM_X86_64})
.Cases("elf32btsmip", "elf32btsmipn32", {ELF32BEKind, EM_MIPS})
.Cases("elf32ltsmip", "elf32ltsmipn32", {ELF32LEKind, EM_MIPS})
@@ -273,13 +273,6 @@ static void checkOptions(opt::InputArgList &Args) {
}
}
-static StringRef getString(opt::InputArgList &Args, unsigned Key,
- StringRef Default = "") {
- if (auto *Arg = Args.getLastArg(Key))
- return Arg->getValue();
- return Default;
-}
-
static int getInteger(opt::InputArgList &Args, unsigned Key, int Default) {
int V = Default;
if (auto *Arg = Args.getLastArg(Key)) {
@@ -306,13 +299,11 @@ static bool hasZOption(opt::InputArgList &Args, StringRef Key) {
static uint64_t getZOptionValue(opt::InputArgList &Args, StringRef Key,
uint64_t Default) {
for (auto *Arg : Args.filtered(OPT_z)) {
- StringRef Value = Arg->getValue();
- size_t Pos = Value.find("=");
- if (Pos != StringRef::npos && Key == Value.substr(0, Pos)) {
- Value = Value.substr(Pos + 1);
+ std::pair<StringRef, StringRef> KV = StringRef(Arg->getValue()).split('=');
+ if (KV.first == Key) {
uint64_t Result;
- if (!to_integer(Value, Result))
- error("invalid " + Key + ": " + Value);
+ if (!to_integer(KV.second, Result))
+ error("invalid " + Key + ": " + KV.second);
return Result;
}
}
@@ -463,7 +454,7 @@ static UnresolvedPolicy getUnresolvedSymbolPolicy(opt::InputArgList &Args) {
}
static Target2Policy getTarget2(opt::InputArgList &Args) {
- StringRef S = getString(Args, OPT_target2, "got-rel");
+ StringRef S = Args.getLastArgValue(OPT_target2, "got-rel");
if (S == "rel")
return Target2Policy::Rel;
if (S == "abs")
@@ -546,7 +537,7 @@ static StringMap<uint64_t> getSectionStartMap(opt::InputArgList &Args) {
}
static SortSectionPolicy getSortSection(opt::InputArgList &Args) {
- StringRef S = getString(Args, OPT_sort_section);
+ StringRef S = Args.getLastArgValue(OPT_sort_section);
if (S == "alignment")
return SortSectionPolicy::Alignment;
if (S == "name")
@@ -557,7 +548,7 @@ static SortSectionPolicy getSortSection(opt::InputArgList &Args) {
}
static std::pair<bool, bool> getHashStyle(opt::InputArgList &Args) {
- StringRef S = getString(Args, OPT_hash_style, "sysv");
+ StringRef S = Args.getLastArgValue(OPT_hash_style, "sysv");
if (S == "sysv")
return {true, false};
if (S == "gnu")
@@ -608,7 +599,7 @@ static std::vector<StringRef> getLines(MemoryBufferRef MB) {
}
static bool getCompressDebugSections(opt::InputArgList &Args) {
- StringRef S = getString(Args, OPT_compress_debug_sections, "none");
+ StringRef S = Args.getLastArgValue(OPT_compress_debug_sections, "none");
if (S == "none")
return false;
if (S != "zlib")
@@ -634,30 +625,30 @@ void LinkerDriver::readConfigs(opt::InputArgList &Args) {
Config->EhFrameHdr = Args.hasArg(OPT_eh_frame_hdr);
Config->EmitRelocs = Args.hasArg(OPT_emit_relocs);
Config->EnableNewDtags = !Args.hasArg(OPT_disable_new_dtags);
- Config->Entry = getString(Args, OPT_entry);
+ Config->Entry = Args.getLastArgValue(OPT_entry);
Config->ExportDynamic =
getArg(Args, OPT_export_dynamic, OPT_no_export_dynamic, false);
Config->FatalWarnings =
getArg(Args, OPT_fatal_warnings, OPT_no_fatal_warnings, false);
- Config->Fini = getString(Args, OPT_fini, "_fini");
+ Config->Fini = Args.getLastArgValue(OPT_fini, "_fini");
Config->GcSections = getArg(Args, OPT_gc_sections, OPT_no_gc_sections, false);
Config->GdbIndex = Args.hasArg(OPT_gdb_index);
Config->ICF = Args.hasArg(OPT_icf);
- Config->Init = getString(Args, OPT_init, "_init");
- Config->LTOAAPipeline = getString(Args, OPT_lto_aa_pipeline);
- Config->LTONewPmPasses = getString(Args, OPT_lto_newpm_passes);
+ Config->Init = Args.getLastArgValue(OPT_init, "_init");
+ Config->LTOAAPipeline = Args.getLastArgValue(OPT_lto_aa_pipeline);
+ Config->LTONewPmPasses = Args.getLastArgValue(OPT_lto_newpm_passes);
Config->LTOO = getInteger(Args, OPT_lto_O, 2);
Config->LTOPartitions = getInteger(Args, OPT_lto_partitions, 1);
- Config->MapFile = getString(Args, OPT_Map);
+ Config->MapFile = Args.getLastArgValue(OPT_Map);
Config->NoGnuUnique = Args.hasArg(OPT_no_gnu_unique);
Config->NoUndefinedVersion = Args.hasArg(OPT_no_undefined_version);
Config->Nostdlib = Args.hasArg(OPT_nostdlib);
Config->OFormatBinary = isOutputFormatBinary(Args);
Config->Omagic = Args.hasArg(OPT_omagic);
- Config->OptRemarksFilename = getString(Args, OPT_opt_remarks_filename);
+ Config->OptRemarksFilename = Args.getLastArgValue(OPT_opt_remarks_filename);
Config->OptRemarksWithHotness = Args.hasArg(OPT_opt_remarks_with_hotness);
Config->Optimize = getInteger(Args, OPT_O, 1);
- Config->OutputFile = getString(Args, OPT_o);
+ Config->OutputFile = Args.getLastArgValue(OPT_o);
Config->Pie = getArg(Args, OPT_pie, OPT_nopie, false);
Config->PrintGcSections = Args.hasArg(OPT_print_gc_sections);
Config->Rpath = getRpath(Args);
@@ -667,16 +658,16 @@ void LinkerDriver::readConfigs(opt::InputArgList &Args) {
Config->SectionStartMap = getSectionStartMap(Args);
Config->Shared = Args.hasArg(OPT_shared);
Config->SingleRoRx = Args.hasArg(OPT_no_rosegment);
- Config->SoName = getString(Args, OPT_soname);
+ Config->SoName = Args.getLastArgValue(OPT_soname);
Config->SortSection = getSortSection(Args);
Config->Strip = getStrip(Args);
- Config->Sysroot = getString(Args, OPT_sysroot);
+ Config->Sysroot = Args.getLastArgValue(OPT_sysroot);
Config->Target1Rel = getArg(Args, OPT_target1_rel, OPT_target1_abs, false);
Config->Target2 = getTarget2(Args);
- Config->ThinLTOCacheDir = getString(Args, OPT_thinlto_cache_dir);
- Config->ThinLTOCachePolicy =
- check(parseCachePruningPolicy(getString(Args, OPT_thinlto_cache_policy)),
- "--thinlto-cache-policy: invalid cache policy");
+ Config->ThinLTOCacheDir = Args.getLastArgValue(OPT_thinlto_cache_dir);
+ Config->ThinLTOCachePolicy = check(
+ parseCachePruningPolicy(Args.getLastArgValue(OPT_thinlto_cache_policy)),
+ "--thinlto-cache-policy: invalid cache policy");
Config->ThinLTOJobs = getInteger(Args, OPT_thinlto_jobs, -1u);
Config->Threads = getArg(Args, OPT_threads, OPT_no_threads, true);
Config->Trace = Args.hasArg(OPT_trace);
@@ -698,7 +689,8 @@ void LinkerDriver::readConfigs(opt::InputArgList &Args) {
Config->ZWxneeded = hasZOption(Args, "wxneeded");
if (Config->LTOO > 3)
- error("invalid optimization level for LTO: " + getString(Args, OPT_lto_O));
+ error("invalid optimization level for LTO: " +
+ Args.getLastArgValue(OPT_lto_O));
if (Config->LTOPartitions == 0)
error("--lto-partitions: number of threads must be > 0");
if (Config->ThinLTOJobs == 0)
@@ -1001,24 +993,20 @@ template <class ELFT> void LinkerDriver::link(opt::InputArgList &Args) {
for (InputSectionBase *S : F->getSections())
InputSections.push_back(cast<InputSection>(S));
- // Do size optimizations: garbage collection and identical code folding.
+ // This adds a .comment section containing a version string. We have to add it
+ // before decompressAndMergeSections because the .comment section is a
+ // mergeable section.
+ if (!Config->Relocatable)
+ InputSections.push_back(createCommentSection<ELFT>());
+
+ // Do size optimizations: garbage collection, merging of SHF_MERGE sections
+ // and identical code folding.
if (Config->GcSections)
markLive<ELFT>();
+ decompressAndMergeSections();
if (Config->ICF)
doIcf<ELFT>();
- // MergeInputSection::splitIntoPieces needs to be called before
- // any call of MergeInputSection::getOffset. Do that.
- parallelForEach(InputSections.begin(), InputSections.end(),
- [](InputSectionBase *S) {
- if (!S->Live)
- return;
- if (Decompressor::isCompressedELFSection(S->Flags, S->Name))
- S->uncompress();
- if (auto *MS = dyn_cast<MergeInputSection>(S))
- MS->splitIntoPieces();
- });
-
// Write the result to the file.
writeResult<ELFT>();
}
diff --git a/ELF/ICF.cpp b/ELF/ICF.cpp
index 536032bdc3a8..09512a8b09d9 100644
--- a/ELF/ICF.cpp
+++ b/ELF/ICF.cpp
@@ -98,7 +98,8 @@ private:
void segregate(size_t Begin, size_t End, bool Constant);
template <class RelTy>
- bool constantEq(ArrayRef<RelTy> RelsA, ArrayRef<RelTy> RelsB);
+ bool constantEq(const InputSection *A, ArrayRef<RelTy> RelsA,
+ const InputSection *B, ArrayRef<RelTy> RelsB);
template <class RelTy>
bool variableEq(const InputSection *A, ArrayRef<RelTy> RelsA,
@@ -206,11 +207,53 @@ void ICF<ELFT>::segregate(size_t Begin, size_t End, bool Constant) {
// Compare two lists of relocations.
template <class ELFT>
template <class RelTy>
-bool ICF<ELFT>::constantEq(ArrayRef<RelTy> RelsA, ArrayRef<RelTy> RelsB) {
- auto Eq = [](const RelTy &A, const RelTy &B) {
- return A.r_offset == B.r_offset &&
- A.getType(Config->IsMips64EL) == B.getType(Config->IsMips64EL) &&
- getAddend<ELFT>(A) == getAddend<ELFT>(B);
+bool ICF<ELFT>::constantEq(const InputSection *A, ArrayRef<RelTy> RelsA,
+ const InputSection *B, ArrayRef<RelTy> RelsB) {
+ auto Eq = [&](const RelTy &RA, const RelTy &RB) {
+ if (RA.r_offset != RB.r_offset ||
+ RA.getType(Config->IsMips64EL) != RB.getType(Config->IsMips64EL))
+ return false;
+ uint64_t AddA = getAddend<ELFT>(RA);
+ uint64_t AddB = getAddend<ELFT>(RB);
+
+ SymbolBody &SA = A->template getFile<ELFT>()->getRelocTargetSym(RA);
+ SymbolBody &SB = B->template getFile<ELFT>()->getRelocTargetSym(RB);
+ if (&SA == &SB)
+ return AddA == AddB;
+
+ auto *DA = dyn_cast<DefinedRegular>(&SA);
+ auto *DB = dyn_cast<DefinedRegular>(&SB);
+ if (!DA || !DB)
+ return false;
+
+ // Relocations referring to absolute symbols are constant-equal if their
+ // values are equal.
+ if (!DA->Section || !DB->Section)
+ return !DA->Section && !DB->Section &&
+ DA->Value + AddA == DB->Value + AddB;
+
+ if (DA->Section->kind() != DB->Section->kind())
+ return false;
+
+ // Relocations referring to InputSections are constant-equal if their
+ // section offsets are equal.
+ if (isa<InputSection>(DA->Section))
+ return DA->Value + AddA == DB->Value + AddB;
+
+ // Relocations referring to MergeInputSections are constant-equal if their
+ // offsets in the output section are equal.
+ auto *X = dyn_cast<MergeInputSection>(DA->Section);
+ if (!X)
+ return false;
+ auto *Y = cast<MergeInputSection>(DB->Section);
+ if (X->getParent() != Y->getParent())
+ return false;
+
+ uint64_t OffsetA =
+ SA.isSection() ? X->getOffset(AddA) : X->getOffset(DA->Value) + AddA;
+ uint64_t OffsetB =
+ SB.isSection() ? Y->getOffset(AddB) : Y->getOffset(DB->Value) + AddB;
+ return OffsetA == OffsetB;
};
return RelsA.size() == RelsB.size() &&
@@ -226,8 +269,9 @@ bool ICF<ELFT>::equalsConstant(const InputSection *A, const InputSection *B) {
return false;
if (A->AreRelocsRela)
- return constantEq(A->template relas<ELFT>(), B->template relas<ELFT>());
- return constantEq(A->template rels<ELFT>(), B->template rels<ELFT>());
+ return constantEq(A, A->template relas<ELFT>(), B,
+ B->template relas<ELFT>());
+ return constantEq(A, A->template rels<ELFT>(), B, B->template rels<ELFT>());
}
// Compare two lists of relocations. Returns true if all pairs of
@@ -243,22 +287,18 @@ bool ICF<ELFT>::variableEq(const InputSection *A, ArrayRef<RelTy> RelsA,
if (&SA == &SB)
return true;
- auto *DA = dyn_cast<DefinedRegular>(&SA);
- auto *DB = dyn_cast<DefinedRegular>(&SB);
- if (!DA || !DB)
- return false;
- if (DA->Value != DB->Value)
- return false;
-
- // Either both symbols must be absolute...
- if (!DA->Section || !DB->Section)
- return !DA->Section && !DB->Section;
+ auto *DA = cast<DefinedRegular>(&SA);
+ auto *DB = cast<DefinedRegular>(&SB);
- // Or the two sections must be in the same equivalence class.
+ // We already dealt with absolute and non-InputSection symbols in
+ // constantEq, and for InputSections we have already checked everything
+ // except the equivalence class.
+ if (!DA->Section)
+ return true;
auto *X = dyn_cast<InputSection>(DA->Section);
- auto *Y = dyn_cast<InputSection>(DB->Section);
- if (!X || !Y)
- return false;
+ if (!X)
+ return true;
+ auto *Y = cast<InputSection>(DB->Section);
// Ineligible sections are in the special equivalence class 0.
// They can never be the same in terms of the equivalence class.
diff --git a/ELF/InputFiles.cpp b/ELF/InputFiles.cpp
index 524246ed1d17..3d11239bf88f 100644
--- a/ELF/InputFiles.cpp
+++ b/ELF/InputFiles.cpp
@@ -205,13 +205,27 @@ template <class ELFT>
StringRef
elf::ObjectFile<ELFT>::getShtGroupSignature(ArrayRef<Elf_Shdr> Sections,
const Elf_Shdr &Sec) {
+ // Group signatures are stored as symbol names in object files.
+ // sh_info contains a symbol index, so we fetch a symbol and read its name.
if (this->Symbols.empty())
this->initSymtab(
Sections,
check(object::getSection<ELFT>(Sections, Sec.sh_link), toString(this)));
+
const Elf_Sym *Sym = check(
object::getSymbol<ELFT>(this->Symbols, Sec.sh_info), toString(this));
- return check(Sym->getName(this->StringTable), toString(this));
+ StringRef Signature = check(Sym->getName(this->StringTable), toString(this));
+
+ // As a special case, if a symbol is a section symbol and has no name,
+ // we use a section name as a signature.
+ //
+ // Such SHT_GROUP sections are invalid from the perspective of the ELF
+ // standard, but GNU gold 1.14 (the neweset version as of July 2017) or
+ // older produce such sections as outputs for the -r option, so we need
+ // a bug-compatibility.
+ if (Signature.empty() && Sym->getType() == STT_SECTION)
+ return getSectionName(Sec);
+ return Signature;
}
template <class ELFT>
@@ -287,8 +301,7 @@ void elf::ObjectFile<ELFT>::initializeSections(
check(this->getObj().sections(), toString(this));
uint64_t Size = ObjSections.size();
this->Sections.resize(Size);
-
- StringRef SectionStringTable =
+ this->SectionStringTable =
check(Obj.getSectionStringTable(ObjSections), toString(this));
for (size_t I = 0, E = ObjSections.size(); I < E; I++) {
@@ -318,7 +331,7 @@ void elf::ObjectFile<ELFT>::initializeSections(
// object files, we want to pass through basically everything.
if (IsNew) {
if (Config->Relocatable)
- this->Sections[I] = createInputSection(Sec, SectionStringTable);
+ this->Sections[I] = createInputSection(Sec);
continue;
}
@@ -342,7 +355,7 @@ void elf::ObjectFile<ELFT>::initializeSections(
case SHT_NULL:
break;
default:
- this->Sections[I] = createInputSection(Sec, SectionStringTable);
+ this->Sections[I] = createInputSection(Sec);
}
// .ARM.exidx sections have a reverse dependency on the InputSection they
@@ -386,10 +399,8 @@ InputSectionBase *toRegularSection(MergeInputSection *Sec) {
template <class ELFT>
InputSectionBase *
-elf::ObjectFile<ELFT>::createInputSection(const Elf_Shdr &Sec,
- StringRef SectionStringTable) {
- StringRef Name = check(
- this->getObj().getSectionName(&Sec, SectionStringTable), toString(this));
+elf::ObjectFile<ELFT>::createInputSection(const Elf_Shdr &Sec) {
+ StringRef Name = getSectionName(Sec);
switch (Sec.sh_type) {
case SHT_ARM_ATTRIBUTES:
@@ -521,6 +532,12 @@ elf::ObjectFile<ELFT>::createInputSection(const Elf_Shdr &Sec,
return make<InputSection>(this, &Sec, Name);
}
+template <class ELFT>
+StringRef elf::ObjectFile<ELFT>::getSectionName(const Elf_Shdr &Sec) {
+ return check(this->getObj().getSectionName(&Sec, SectionStringTable),
+ toString(this));
+}
+
template <class ELFT> void elf::ObjectFile<ELFT>::initializeSymbols() {
SymbolBodies.reserve(this->Symbols.size());
for (const Elf_Sym &Sym : this->Symbols)
@@ -804,6 +821,8 @@ static uint8_t getBitcodeMachineKind(StringRef Path, const Triple &T) {
case Triple::arm:
case Triple::thumb:
return EM_ARM;
+ case Triple::avr:
+ return EM_AVR;
case Triple::mips:
case Triple::mipsel:
case Triple::mips64:
diff --git a/ELF/InputFiles.h b/ELF/InputFiles.h
index 6daf26649859..2eec78444837 100644
--- a/ELF/InputFiles.h
+++ b/ELF/InputFiles.h
@@ -194,8 +194,8 @@ private:
void initializeSymbols();
void initializeDwarfLine();
InputSectionBase *getRelocTarget(const Elf_Shdr &Sec);
- InputSectionBase *createInputSection(const Elf_Shdr &Sec,
- StringRef SectionStringTable);
+ InputSectionBase *createInputSection(const Elf_Shdr &Sec);
+ StringRef getSectionName(const Elf_Shdr &Sec);
bool shouldMerge(const Elf_Shdr &Sec);
SymbolBody *createSymbolBody(const Elf_Sym *Sym);
@@ -203,6 +203,9 @@ private:
// List of all symbols referenced or defined by this file.
std::vector<SymbolBody *> SymbolBodies;
+ // .shstrtab contents.
+ StringRef SectionStringTable;
+
// Debugging information to retrieve source file and line for error
// reporting. Linker may find reasonable number of errors in a
// single object file, so we cache debugging information in order to
diff --git a/ELF/InputSection.cpp b/ELF/InputSection.cpp
index e82f8c3016fa..9aae82bc2992 100644
--- a/ELF/InputSection.cpp
+++ b/ELF/InputSection.cpp
@@ -403,7 +403,7 @@ static uint32_t getARMUndefinedRelativeWeakVA(uint32_t Type, uint32_t A,
uint32_t P) {
switch (Type) {
case R_ARM_THM_JUMP11:
- return P + 2;
+ return P + 2 + A;
case R_ARM_CALL:
case R_ARM_JUMP24:
case R_ARM_PC24:
@@ -411,12 +411,12 @@ static uint32_t getARMUndefinedRelativeWeakVA(uint32_t Type, uint32_t A,
case R_ARM_PREL31:
case R_ARM_THM_JUMP19:
case R_ARM_THM_JUMP24:
- return P + 4;
+ return P + 4 + A;
case R_ARM_THM_CALL:
// We don't want an interworking BLX to ARM
- return P + 5;
+ return P + 5 + A;
default:
- return A;
+ return P + A;
}
}
@@ -427,9 +427,9 @@ static uint64_t getAArch64UndefinedRelativeWeakVA(uint64_t Type, uint64_t A,
case R_AARCH64_CONDBR19:
case R_AARCH64_JUMP26:
case R_AARCH64_TSTBR14:
- return P + 4;
+ return P + 4 + A;
default:
- return A;
+ return P + A;
}
}
@@ -515,20 +515,30 @@ static uint64_t getRelocTargetVA(uint32_t Type, int64_t A, uint64_t P,
return InX::MipsGot->getVA() + InX::MipsGot->getTlsOffset() +
InX::MipsGot->getTlsIndexOff() - InX::MipsGot->getGp();
case R_PAGE_PC:
- case R_PLT_PAGE_PC:
+ case R_PLT_PAGE_PC: {
+ uint64_t Dest;
if (Body.isUndefined() && !Body.isLocal() && Body.symbol()->isWeak())
- return getAArch64Page(A);
- return getAArch64Page(Body.getVA(A)) - getAArch64Page(P);
- case R_PC:
+ Dest = getAArch64Page(A);
+ else
+ Dest = getAArch64Page(Body.getVA(A));
+ return Dest - getAArch64Page(P);
+ }
+ case R_PC: {
+ uint64_t Dest;
if (Body.isUndefined() && !Body.isLocal() && Body.symbol()->isWeak()) {
// On ARM and AArch64 a branch to an undefined weak resolves to the
// next instruction, otherwise the place.
if (Config->EMachine == EM_ARM)
- return getARMUndefinedRelativeWeakVA(Type, A, P);
- if (Config->EMachine == EM_AARCH64)
- return getAArch64UndefinedRelativeWeakVA(Type, A, P);
+ Dest = getARMUndefinedRelativeWeakVA(Type, A, P);
+ else if (Config->EMachine == EM_AARCH64)
+ Dest = getAArch64UndefinedRelativeWeakVA(Type, A, P);
+ else
+ Dest = Body.getVA(A);
+ } else {
+ Dest = Body.getVA(A);
}
- return Body.getVA(A) - P;
+ return Dest - P;
+ }
case R_PLT:
return Body.getPltVA() + A;
case R_PLT_PC:
diff --git a/ELF/LinkerScript.cpp b/ELF/LinkerScript.cpp
index 9dd7ba52be19..f5a59f0c8c4d 100644
--- a/ELF/LinkerScript.cpp
+++ b/ELF/LinkerScript.cpp
@@ -142,10 +142,7 @@ void LinkerScript::assignSymbol(SymbolAssignment *Cmd, bool InSec) {
Sym->Value = V.getValue();
} else {
Sym->Section = V.Sec;
- if (Sym->Section->Flags & SHF_ALLOC)
- Sym->Value = alignTo(V.Val, V.Alignment);
- else
- Sym->Value = V.getValue();
+ Sym->Value = alignTo(V.Val, V.Alignment);
}
}
@@ -461,7 +458,7 @@ void LinkerScript::fabricateDefaultCommands() {
// For each OutputSection that needs a VA fabricate an OutputSectionCommand
// with an InputSectionDescription describing the InputSections
- for (OutputSection *Sec : *OutputSections) {
+ for (OutputSection *Sec : OutputSections) {
auto *OSCmd = createOutputSectionCommand(Sec->Name, "<internal>");
OSCmd->Sec = Sec;
SecToCommand[Sec] = OSCmd;
@@ -649,7 +646,9 @@ void LinkerScript::assignOffsets(OutputSectionCommand *Cmd) {
if (!Sec)
return;
- if (Cmd->AddrExpr && (Sec->Flags & SHF_ALLOC))
+ if (!(Sec->Flags & SHF_ALLOC))
+ Dot = 0;
+ else if (Cmd->AddrExpr)
setDot(Cmd->AddrExpr, Cmd->Location, false);
if (Cmd->LMAExpr) {
@@ -681,8 +680,7 @@ void LinkerScript::removeEmptyCommands() {
auto Pos = std::remove_if(
Opt.Commands.begin(), Opt.Commands.end(), [&](BaseCommand *Base) {
if (auto *Cmd = dyn_cast<OutputSectionCommand>(Base))
- return std::find(OutputSections->begin(), OutputSections->end(),
- Cmd->Sec) == OutputSections->end();
+ return Cmd->Sec == nullptr;
return false;
});
Opt.Commands.erase(Pos, Opt.Commands.end());
@@ -716,15 +714,12 @@ void LinkerScript::adjustSectionsBeforeSorting() {
auto *OutSec = make<OutputSection>(Cmd->Name, SHT_PROGBITS, Flags);
OutSec->SectionIndex = I;
- OutputSections->push_back(OutSec);
Cmd->Sec = OutSec;
SecToCommand[OutSec] = Cmd;
}
}
void LinkerScript::adjustSectionsAfterSorting() {
- placeOrphanSections();
-
// Try and find an appropriate memory region to assign offsets in.
for (BaseCommand *Base : Opt.Commands) {
if (auto *Cmd = dyn_cast<OutputSectionCommand>(Base)) {
@@ -764,106 +759,18 @@ void LinkerScript::adjustSectionsAfterSorting() {
removeEmptyCommands();
}
-// When placing orphan sections, we want to place them after symbol assignments
-// so that an orphan after
-// begin_foo = .;
-// foo : { *(foo) }
-// end_foo = .;
-// doesn't break the intended meaning of the begin/end symbols.
-// We don't want to go over sections since Writer<ELFT>::sortSections is the
-// one in charge of deciding the order of the sections.
-// We don't want to go over alignments, since doing so in
-// rx_sec : { *(rx_sec) }
-// . = ALIGN(0x1000);
-// /* The RW PT_LOAD starts here*/
-// rw_sec : { *(rw_sec) }
-// would mean that the RW PT_LOAD would become unaligned.
-static bool shouldSkip(BaseCommand *Cmd) {
- if (isa<OutputSectionCommand>(Cmd))
- return false;
- if (auto *Assign = dyn_cast<SymbolAssignment>(Cmd))
- return Assign->Name != ".";
- return true;
-}
-
-// Orphan sections are sections present in the input files which are
-// not explicitly placed into the output file by the linker script.
-//
-// When the control reaches this function, Opt.Commands contains
-// output section commands for non-orphan sections only. This function
-// adds new elements for orphan sections so that all sections are
-// explicitly handled by Opt.Commands.
-//
-// Writer<ELFT>::sortSections has already sorted output sections.
-// What we need to do is to scan OutputSections vector and
-// Opt.Commands in parallel to find orphan sections. If there is an
-// output section that doesn't have a corresponding entry in
-// Opt.Commands, we will insert a new entry to Opt.Commands.
-//
-// There is some ambiguity as to where exactly a new entry should be
-// inserted, because Opt.Commands contains not only output section
-// commands but also other types of commands such as symbol assignment
-// expressions. There's no correct answer here due to the lack of the
-// formal specification of the linker script. We use heuristics to
-// determine whether a new output command should be added before or
-// after another commands. For the details, look at shouldSkip
-// function.
-void LinkerScript::placeOrphanSections() {
- // The OutputSections are already in the correct order.
- // This loops creates or moves commands as needed so that they are in the
- // correct order.
- int CmdIndex = 0;
-
- // As a horrible special case, skip the first . assignment if it is before any
- // section. We do this because it is common to set a load address by starting
- // the script with ". = 0xabcd" and the expectation is that every section is
- // after that.
- auto FirstSectionOrDotAssignment =
- std::find_if(Opt.Commands.begin(), Opt.Commands.end(),
- [](BaseCommand *Cmd) { return !shouldSkip(Cmd); });
- if (FirstSectionOrDotAssignment != Opt.Commands.end()) {
- CmdIndex = FirstSectionOrDotAssignment - Opt.Commands.begin();
- if (isa<SymbolAssignment>(**FirstSectionOrDotAssignment))
- ++CmdIndex;
- }
-
- for (OutputSection *Sec : *OutputSections) {
- StringRef Name = Sec->Name;
-
- // Find the last spot where we can insert a command and still get the
- // correct result.
- auto CmdIter = Opt.Commands.begin() + CmdIndex;
- auto E = Opt.Commands.end();
- while (CmdIter != E && shouldSkip(*CmdIter)) {
- ++CmdIter;
- ++CmdIndex;
- }
-
- // If there is no command corresponding to this output section,
- // create one and put a InputSectionDescription in it so that both
- // representations agree on which input sections to use.
- OutputSectionCommand *Cmd = getCmd(Sec);
- if (!Cmd) {
- Cmd = createOutputSectionCommand(Name, "<internal>");
- Opt.Commands.insert(CmdIter, Cmd);
- ++CmdIndex;
-
- Cmd->Sec = Sec;
- SecToCommand[Sec] = Cmd;
- auto *ISD = make<InputSectionDescription>("");
- for (InputSection *IS : Sec->Sections)
- ISD->Sections.push_back(IS);
- Cmd->Commands.push_back(ISD);
-
+void LinkerScript::createOrphanCommands() {
+ for (OutputSection *Sec : OutputSections) {
+ if (Sec->SectionIndex != INT_MAX)
continue;
- }
-
- // Continue from where we found it.
- while (*CmdIter != Cmd) {
- ++CmdIter;
- ++CmdIndex;
- }
- ++CmdIndex;
+ OutputSectionCommand *Cmd =
+ createOutputSectionCommand(Sec->Name, "<internal>");
+ Cmd->Sec = Sec;
+ SecToCommand[Sec] = Cmd;
+ auto *ISD = make<InputSectionDescription>("");
+ ISD->Sections = Sec->Sections;
+ Cmd->Commands.push_back(ISD);
+ Opt.Commands.push_back(Cmd);
}
}
@@ -922,9 +829,7 @@ allocateHeaders(std::vector<PhdrEntry> &Phdrs,
return false;
}
-void LinkerScript::assignAddresses(
- std::vector<PhdrEntry> &Phdrs,
- ArrayRef<OutputSectionCommand *> OutputSectionCommands) {
+void LinkerScript::assignAddresses(std::vector<PhdrEntry> &Phdrs) {
// Assign addresses as instructed by linker script SECTIONS sub-commands.
Dot = 0;
ErrorOnMissingSection = true;
@@ -950,8 +855,6 @@ void LinkerScript::assignAddresses(
OutputSection *Sec = Cmd->Sec;
if (Sec->Flags & SHF_ALLOC)
MinVA = std::min<uint64_t>(MinVA, Sec->Addr);
- else
- Sec->Addr = 0;
}
allocateHeaders(Phdrs, OutputSectionCommands, MinVA);
@@ -979,7 +882,8 @@ std::vector<PhdrEntry> LinkerScript::createPhdrs() {
}
// Add output sections to program headers.
- for (OutputSection *Sec : *OutputSections) {
+ for (OutputSectionCommand *Cmd : OutputSectionCommands) {
+ OutputSection *Sec = Cmd->Sec;
if (!(Sec->Flags & SHF_ALLOC))
break;
diff --git a/ELF/LinkerScript.h b/ELF/LinkerScript.h
index 1d4c736763fb..f8a34a1e97dd 100644
--- a/ELF/LinkerScript.h
+++ b/ELF/LinkerScript.h
@@ -267,7 +267,6 @@ public:
ExprValue getSymbolValue(const Twine &Loc, StringRef S);
bool isDefined(StringRef S);
- std::vector<OutputSection *> *OutputSections;
void fabricateDefaultCommands();
void addOrphanSections(OutputSectionFactory &Factory);
void removeEmptyCommands();
@@ -280,10 +279,9 @@ public:
bool hasLMA(OutputSection *Sec);
bool shouldKeep(InputSectionBase *S);
void assignOffsets(OutputSectionCommand *Cmd);
- void placeOrphanSections();
+ void createOrphanCommands();
void processNonSectionCommands();
- void assignAddresses(std::vector<PhdrEntry> &Phdrs,
- ArrayRef<OutputSectionCommand *> OutputSectionCommands);
+ void assignAddresses(std::vector<PhdrEntry> &Phdrs);
void addSymbol(SymbolAssignment *Cmd);
void processCommands(OutputSectionFactory &Factory);
diff --git a/ELF/MarkLive.cpp b/ELF/MarkLive.cpp
index b77c84ff75a0..0b4a78f8da6b 100644
--- a/ELF/MarkLive.cpp
+++ b/ELF/MarkLive.cpp
@@ -230,6 +230,8 @@ template <class ELFT> void elf::markLive() {
MarkSymbol(Symtab<ELFT>::X->find(Config->Fini));
for (StringRef S : Config->Undefined)
MarkSymbol(Symtab<ELFT>::X->find(S));
+ for (StringRef S : Script->Opt.ReferencedSymbols)
+ MarkSymbol(Symtab<ELFT>::X->find(S));
// Preserve externally-visible symbols if the symbols defined by this
// file can interrupt other ELF file's symbols at runtime.
diff --git a/ELF/OutputSections.cpp b/ELF/OutputSections.cpp
index 008871fd3889..6f04a04be8d0 100644
--- a/ELF/OutputSections.cpp
+++ b/ELF/OutputSections.cpp
@@ -41,6 +41,9 @@ OutputSection *Out::PreinitArray;
OutputSection *Out::InitArray;
OutputSection *Out::FiniArray;
+std::vector<OutputSection *> elf::OutputSections;
+std::vector<OutputSectionCommand *> elf::OutputSectionCommands;
+
uint32_t OutputSection::getPhdrFlags() const {
uint32_t Ret = PF_R;
if (Flags & SHF_WRITE)
diff --git a/ELF/OutputSections.h b/ELF/OutputSections.h
index 7b093fb9dee7..d5f77838d530 100644
--- a/ELF/OutputSections.h
+++ b/ELF/OutputSections.h
@@ -150,6 +150,8 @@ private:
uint64_t getHeaderSize();
void reportDiscarded(InputSectionBase *IS);
+extern std::vector<OutputSection *> OutputSections;
+extern std::vector<OutputSectionCommand *> OutputSectionCommands;
} // namespace elf
} // namespace lld
diff --git a/ELF/Relocations.cpp b/ELF/Relocations.cpp
index 98c1349a2f0d..1ac3bce769ee 100644
--- a/ELF/Relocations.cpp
+++ b/ELF/Relocations.cpp
@@ -1009,8 +1009,7 @@ ThunkSection *ThunkCreator::getOSThunkSec(OutputSection *OS,
if ((IS->Flags & SHF_EXECINSTR) == 0)
break;
}
- CurTS = make<ThunkSection>(OS, Off);
- ThunkSections[ISR].push_back(CurTS);
+ CurTS = addThunkSection(OS, ISR, Off);
}
return CurTS;
}
@@ -1020,7 +1019,6 @@ ThunkSection *ThunkCreator::getISThunkSec(InputSection *IS, OutputSection *OS) {
if (TS)
return TS;
auto *TOS = IS->getParent();
- TS = make<ThunkSection>(TOS, IS->OutSecOff);
// Find InputSectionRange within TOS that IS is in
OutputSectionCommand *C = Script->getCmd(TOS);
@@ -1035,11 +1033,20 @@ ThunkSection *ThunkCreator::getISThunkSec(InputSection *IS, OutputSection *OS) {
break;
}
}
- ThunkSections[Range].push_back(TS);
+ TS = addThunkSection(TOS, Range, IS->OutSecOff);
ThunkedSections[IS] = TS;
return TS;
}
+ThunkSection *ThunkCreator::addThunkSection(OutputSection *OS,
+ std::vector<InputSection *> *ISR,
+ uint64_t Off) {
+ auto *TS = make<ThunkSection>(OS, Off);
+ ThunkSections[ISR].push_back(TS);
+ return TS;
+}
+
+
std::pair<Thunk *, bool> ThunkCreator::getThunk(SymbolBody &Body,
uint32_t Type) {
auto res = ThunkedSymbols.insert({&Body, nullptr});
@@ -1081,6 +1088,9 @@ void ThunkCreator::forEachExecInputSection(
// extension Thunks are not yet supported.
bool ThunkCreator::createThunks(
ArrayRef<OutputSectionCommand *> OutputSections) {
+ if (Pass > 0)
+ ThunkSections.clear();
+
// Create all the Thunks and insert them into synthetic ThunkSections. The
// ThunkSections are later inserted back into the OutputSection.
@@ -1088,11 +1098,12 @@ bool ThunkCreator::createThunks(
// ThunkSections back into the OutputSection as ThunkSections are not always
// inserted into the same OutputSection as the caller.
forEachExecInputSection(
- OutputSections, [=](OutputSection *OS, std::vector<InputSection*> *ISR,
+ OutputSections, [&](OutputSection *OS, std::vector<InputSection*> *ISR,
InputSection *IS) {
for (Relocation &Rel : IS->Relocations) {
SymbolBody &Body = *Rel.Sym;
- if (!Target->needsThunk(Rel.Expr, Rel.Type, IS->File, Body))
+ if (Thunks.find(&Body) != Thunks.end() ||
+ !Target->needsThunk(Rel.Expr, Rel.Type, IS->File, Body))
continue;
Thunk *T;
bool IsNew;
@@ -1105,15 +1116,16 @@ bool ThunkCreator::createThunks(
else
TS = getOSThunkSec(OS, ISR);
TS->addThunk(T);
+ Thunks[T->ThunkSym] = T;
}
// Redirect relocation to Thunk, we never go via the PLT to a Thunk
Rel.Sym = T->ThunkSym;
Rel.Expr = fromPlt(Rel.Expr);
}
});
-
// Merge all created synthetic ThunkSections back into OutputSection
mergeThunks();
+ ++Pass;
return !ThunkSections.empty();
}
diff --git a/ELF/Relocations.h b/ELF/Relocations.h
index dcbf545cde53..445308b27cec 100644
--- a/ELF/Relocations.h
+++ b/ELF/Relocations.h
@@ -126,6 +126,11 @@ public:
// Return true if Thunks have been added to OutputSections
bool createThunks(ArrayRef<OutputSectionCommand *> OutputSections);
+ // The number of completed passes of createThunks this permits us
+ // to do one time initialization on Pass 0 and put a limit on the
+ // number of times it can be called to prevent infinite loops.
+ uint32_t Pass = 0;
+
private:
void mergeThunks();
ThunkSection *getOSThunkSec(OutputSection *OS,
@@ -137,14 +142,22 @@ private:
InputSection *)>
Fn);
std::pair<Thunk *, bool> getThunk(SymbolBody &Body, uint32_t Type);
-
+ ThunkSection *addThunkSection(OutputSection *OS,
+ std::vector<InputSection *> *, uint64_t Off);
// Track Symbols that already have a Thunk
llvm::DenseMap<SymbolBody *, Thunk *> ThunkedSymbols;
+ // Find a Thunk from the Thunks symbol definition, we can use this to find
+ // the Thunk from a relocation to the Thunks symbol definition.
+ llvm::DenseMap<SymbolBody *, Thunk *> Thunks;
+
// Track InputSections that have a ThunkSection placed in front
llvm::DenseMap<InputSection *, ThunkSection *> ThunkedSections;
- // Track the ThunksSections that need to be inserted into an OutputSection
+ // All the ThunkSections that we have created, organised by OutputSection
+ // will contain a mix of ThunkSections that have been created this pass, and
+ // ThunkSections that have been merged into the OutputSection on previous
+ // passes
std::map<std::vector<InputSection *> *, std::vector<ThunkSection *>>
ThunkSections;
diff --git a/ELF/Strings.h b/ELF/Strings.h
index bcfa28144989..fd1aa40539d2 100644
--- a/ELF/Strings.h
+++ b/ELF/Strings.h
@@ -73,10 +73,6 @@ private:
// name, it returns Optional::None.
llvm::Optional<std::string> demangle(StringRef Name);
-inline StringRef toStringRef(ArrayRef<uint8_t> Arr) {
- return {(const char *)Arr.data(), Arr.size()};
-}
-
inline ArrayRef<uint8_t> toArrayRef(StringRef S) {
return {(const uint8_t *)S.data(), S.size()};
}
diff --git a/ELF/SyntheticSections.cpp b/ELF/SyntheticSections.cpp
index 5cd6c5f2b914..cb1494d427a0 100644
--- a/ELF/SyntheticSections.cpp
+++ b/ELF/SyntheticSections.cpp
@@ -29,6 +29,7 @@
#include "lld/Config/Version.h"
#include "llvm/BinaryFormat/Dwarf.h"
#include "llvm/DebugInfo/DWARF/DWARFDebugPubTable.h"
+#include "llvm/Object/Decompressor.h"
#include "llvm/Object/ELFObjectFile.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/MD5.h"
@@ -2133,7 +2134,6 @@ MergeSyntheticSection::MergeSyntheticSection(StringRef Name, uint32_t Type,
Builder(StringTableBuilder::RAW, Alignment) {}
void MergeSyntheticSection::addSection(MergeInputSection *MS) {
- assert(!Finalized);
MS->Parent = this;
Sections.push_back(MS);
}
@@ -2178,9 +2178,6 @@ void MergeSyntheticSection::finalizeNoTailMerge() {
}
void MergeSyntheticSection::finalizeContents() {
- if (Finalized)
- return;
- Finalized = true;
if (shouldTailMerge())
finalizeTailMerge();
else
@@ -2188,11 +2185,65 @@ void MergeSyntheticSection::finalizeContents() {
}
size_t MergeSyntheticSection::getSize() const {
- // We should finalize string builder to know the size.
- const_cast<MergeSyntheticSection *>(this)->finalizeContents();
return Builder.getSize();
}
+// This function decompresses compressed sections and scans over the input
+// sections to create mergeable synthetic sections. It removes
+// MergeInputSections from the input section array and adds new synthetic
+// sections at the location of the first input section that it replaces. It then
+// finalizes each synthetic section in order to compute an output offset for
+// each piece of each input section.
+void elf::decompressAndMergeSections() {
+ // splitIntoPieces needs to be called on each MergeInputSection before calling
+ // finalizeContents(). Do that first.
+ parallelForEach(InputSections.begin(), InputSections.end(),
+ [](InputSectionBase *S) {
+ if (!S->Live)
+ return;
+ if (Decompressor::isCompressedELFSection(S->Flags, S->Name))
+ S->uncompress();
+ if (auto *MS = dyn_cast<MergeInputSection>(S))
+ MS->splitIntoPieces();
+ });
+
+ std::vector<MergeSyntheticSection *> MergeSections;
+ for (InputSectionBase *&S : InputSections) {
+ MergeInputSection *MS = dyn_cast<MergeInputSection>(S);
+ if (!MS)
+ continue;
+
+ // We do not want to handle sections that are not alive, so just remove
+ // them instead of trying to merge.
+ if (!MS->Live)
+ continue;
+
+ StringRef OutsecName = getOutputSectionName(MS->Name);
+ uint64_t Flags = MS->Flags & ~(uint64_t)SHF_GROUP;
+ uint32_t Alignment = std::max<uint32_t>(MS->Alignment, MS->Entsize);
+
+ auto I = llvm::find_if(MergeSections, [=](MergeSyntheticSection *Sec) {
+ return Sec->Name == OutsecName && Sec->Flags == Flags &&
+ Sec->Alignment == Alignment;
+ });
+ if (I == MergeSections.end()) {
+ MergeSyntheticSection *Syn =
+ make<MergeSyntheticSection>(OutsecName, MS->Type, Flags, Alignment);
+ MergeSections.push_back(Syn);
+ I = std::prev(MergeSections.end());
+ S = Syn;
+ } else {
+ S = nullptr;
+ }
+ (*I)->addSection(MS);
+ }
+ for (auto *MS : MergeSections)
+ MS->finalizeContents();
+
+ std::vector<InputSectionBase *> &V = InputSections;
+ V.erase(std::remove(V.begin(), V.end(), nullptr), V.end());
+}
+
MipsRldMapSection::MipsRldMapSection()
: SyntheticSection(SHF_ALLOC | SHF_WRITE, SHT_PROGBITS, Config->Wordsize,
".rld_map") {}
diff --git a/ELF/SyntheticSections.h b/ELF/SyntheticSections.h
index c807043c9dc2..be9a43c8155b 100644
--- a/ELF/SyntheticSections.h
+++ b/ELF/SyntheticSections.h
@@ -651,7 +651,6 @@ private:
void finalizeTailMerge();
void finalizeNoTailMerge();
- bool Finalized = false;
llvm::StringTableBuilder Builder;
std::vector<MergeInputSection *> Sections;
};
@@ -748,6 +747,7 @@ private:
template <class ELFT> InputSection *createCommonSection();
InputSection *createInterpSection();
template <class ELFT> MergeInputSection *createCommentSection();
+void decompressAndMergeSections();
SymbolBody *addSyntheticLocal(StringRef Name, uint8_t Type, uint64_t Value,
uint64_t Size, InputSectionBase *Section);
diff --git a/ELF/Target.cpp b/ELF/Target.cpp
index ee5a7690fc64..df3f4d6773f0 100644
--- a/ELF/Target.cpp
+++ b/ELF/Target.cpp
@@ -27,22 +27,18 @@
#include "Target.h"
#include "Error.h"
#include "InputFiles.h"
-#include "Memory.h"
#include "OutputSections.h"
#include "SymbolTable.h"
#include "Symbols.h"
-#include "SyntheticSections.h"
-#include "Thunks.h"
-#include "Writer.h"
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/BinaryFormat/ELF.h"
#include "llvm/Object/ELF.h"
-#include "llvm/Support/Endian.h"
using namespace llvm;
using namespace llvm::object;
-using namespace llvm::support::endian;
using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+TargetInfo *elf::Target;
std::string lld::toString(uint32_t Type) {
StringRef S = getELFRelocationTypeName(elf::Config->EMachine, Type);
@@ -51,13 +47,43 @@ std::string lld::toString(uint32_t Type) {
return S;
}
-namespace lld {
-namespace elf {
-
-TargetInfo *Target;
-
-static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
-static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); }
+TargetInfo *elf::createTarget() {
+ switch (Config->EMachine) {
+ case EM_386:
+ case EM_IAMCU:
+ return createX86TargetInfo();
+ case EM_AARCH64:
+ return createAArch64TargetInfo();
+ case EM_AMDGPU:
+ return createAMDGPUTargetInfo();
+ case EM_ARM:
+ return createARMTargetInfo();
+ case EM_AVR:
+ return createAVRTargetInfo();
+ case EM_MIPS:
+ switch (Config->EKind) {
+ case ELF32LEKind:
+ return createMipsTargetInfo<ELF32LE>();
+ case ELF32BEKind:
+ return createMipsTargetInfo<ELF32BE>();
+ case ELF64LEKind:
+ return createMipsTargetInfo<ELF64LE>();
+ case ELF64BEKind:
+ return createMipsTargetInfo<ELF64BE>();
+ default:
+ fatal("unsupported MIPS target");
+ }
+ case EM_PPC:
+ return createPPCTargetInfo();
+ case EM_PPC64:
+ return createPPC64TargetInfo();
+ case EM_X86_64:
+ if (Config->EKind == ELF32LEKind)
+ return createX32TargetInfo();
+ return createX86_64TargetInfo();
+ }
+ fatal("unknown target machine");
+}
template <class ELFT> static std::string getErrorLoc(const uint8_t *Loc) {
for (InputSectionBase *D : InputSections) {
@@ -72,7 +98,7 @@ template <class ELFT> static std::string getErrorLoc(const uint8_t *Loc) {
return "";
}
-static std::string getErrorLocation(const uint8_t *Loc) {
+std::string elf::getErrorLocation(const uint8_t *Loc) {
switch (Config->EKind) {
case ELF32LEKind:
return getErrorLoc<ELF32LE>(Loc);
@@ -87,204 +113,6 @@ static std::string getErrorLocation(const uint8_t *Loc) {
}
}
-template <unsigned N>
-static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) {
- if (!isInt<N>(V))
- error(getErrorLocation(Loc) + "relocation " + toString(Type) +
- " out of range");
-}
-
-template <unsigned N>
-static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) {
- if (!isUInt<N>(V))
- error(getErrorLocation(Loc) + "relocation " + toString(Type) +
- " out of range");
-}
-
-template <unsigned N>
-static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) {
- if (!isInt<N>(V) && !isUInt<N>(V))
- error(getErrorLocation(Loc) + "relocation " + toString(Type) +
- " out of range");
-}
-
-template <unsigned N>
-static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) {
- if ((V & (N - 1)) != 0)
- error(getErrorLocation(Loc) + "improper alignment for relocation " +
- toString(Type));
-}
-
-namespace {
-class X86TargetInfo final : public TargetInfo {
-public:
- X86TargetInfo();
- RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const override;
- int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
- void writeGotPltHeader(uint8_t *Buf) const override;
- uint32_t getDynRel(uint32_t Type) const override;
- void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
- void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
- void writePltHeader(uint8_t *Buf) const override;
- void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
- int32_t Index, unsigned RelOff) const override;
- void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
-
- RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
- RelExpr Expr) const override;
- void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
-};
-
-template <class ELFT> class X86_64TargetInfo final : public TargetInfo {
-public:
- X86_64TargetInfo();
- RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const override;
- bool isPicRel(uint32_t Type) const override;
- void writeGotPltHeader(uint8_t *Buf) const override;
- void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
- void writePltHeader(uint8_t *Buf) const override;
- void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
- int32_t Index, unsigned RelOff) const override;
- void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
-
- RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
- RelExpr Expr) const override;
- void relaxGot(uint8_t *Loc, uint64_t Val) const override;
- void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
-
-private:
- void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
- uint8_t ModRm) const;
-};
-
-class PPCTargetInfo final : public TargetInfo {
-public:
- PPCTargetInfo();
- void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const override;
-};
-
-class PPC64TargetInfo final : public TargetInfo {
-public:
- PPC64TargetInfo();
- RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const override;
- void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
- int32_t Index, unsigned RelOff) const override;
- void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
-};
-
-class AArch64TargetInfo final : public TargetInfo {
-public:
- AArch64TargetInfo();
- RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const override;
- bool isPicRel(uint32_t Type) const override;
- void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
- void writePltHeader(uint8_t *Buf) const override;
- void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
- int32_t Index, unsigned RelOff) const override;
- bool usesOnlyLowPageBits(uint32_t Type) const override;
- void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
- RelExpr Expr) const override;
- void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
-};
-
-class AMDGPUTargetInfo final : public TargetInfo {
-public:
- AMDGPUTargetInfo();
- void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const override;
-};
-
-class ARMTargetInfo final : public TargetInfo {
-public:
- ARMTargetInfo();
- RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const override;
- bool isPicRel(uint32_t Type) const override;
- uint32_t getDynRel(uint32_t Type) const override;
- int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
- void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
- void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
- void writePltHeader(uint8_t *Buf) const override;
- void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
- int32_t Index, unsigned RelOff) const override;
- void addPltSymbols(InputSectionBase *IS, uint64_t Off) const override;
- void addPltHeaderSymbols(InputSectionBase *ISD) const override;
- bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
- const SymbolBody &S) const override;
- void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
-};
-
-template <class ELFT> class MipsTargetInfo final : public TargetInfo {
-public:
- MipsTargetInfo();
- RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const override;
- int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
- bool isPicRel(uint32_t Type) const override;
- uint32_t getDynRel(uint32_t Type) const override;
- void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
- void writePltHeader(uint8_t *Buf) const override;
- void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
- int32_t Index, unsigned RelOff) const override;
- bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
- const SymbolBody &S) const override;
- void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
- bool usesOnlyLowPageBits(uint32_t Type) const override;
-};
-} // anonymous namespace
-
-TargetInfo *createTarget() {
- switch (Config->EMachine) {
- case EM_386:
- case EM_IAMCU:
- return make<X86TargetInfo>();
- case EM_AARCH64:
- return make<AArch64TargetInfo>();
- case EM_AMDGPU:
- return make<AMDGPUTargetInfo>();
- case EM_ARM:
- return make<ARMTargetInfo>();
- case EM_MIPS:
- switch (Config->EKind) {
- case ELF32LEKind:
- return make<MipsTargetInfo<ELF32LE>>();
- case ELF32BEKind:
- return make<MipsTargetInfo<ELF32BE>>();
- case ELF64LEKind:
- return make<MipsTargetInfo<ELF64LE>>();
- case ELF64BEKind:
- return make<MipsTargetInfo<ELF64BE>>();
- default:
- fatal("unsupported MIPS target");
- }
- case EM_PPC:
- return make<PPCTargetInfo>();
- case EM_PPC64:
- return make<PPC64TargetInfo>();
- case EM_X86_64:
- if (Config->EKind == ELF32LEKind)
- return make<X86_64TargetInfo<ELF32LE>>();
- return make<X86_64TargetInfo<ELF64LE>>();
- }
- fatal("unknown target machine");
-}
-
TargetInfo::~TargetInfo() {}
int64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
@@ -330,2091 +158,3 @@ void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
uint64_t Val) const {
llvm_unreachable("Should not have claimed to be relaxable");
}
-
-X86TargetInfo::X86TargetInfo() {
- CopyRel = R_386_COPY;
- GotRel = R_386_GLOB_DAT;
- PltRel = R_386_JUMP_SLOT;
- IRelativeRel = R_386_IRELATIVE;
- RelativeRel = R_386_RELATIVE;
- TlsGotRel = R_386_TLS_TPOFF;
- TlsModuleIndexRel = R_386_TLS_DTPMOD32;
- TlsOffsetRel = R_386_TLS_DTPOFF32;
- GotEntrySize = 4;
- GotPltEntrySize = 4;
- PltEntrySize = 16;
- PltHeaderSize = 16;
- TlsGdRelaxSkip = 2;
- // 0xCC is the "int3" (call debug exception handler) instruction.
- TrapInstr = 0xcccccccc;
-}
-
-RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const {
- switch (Type) {
- case R_386_8:
- case R_386_16:
- case R_386_32:
- case R_386_TLS_LDO_32:
- return R_ABS;
- case R_386_TLS_GD:
- return R_TLSGD;
- case R_386_TLS_LDM:
- return R_TLSLD;
- case R_386_PLT32:
- return R_PLT_PC;
- case R_386_PC8:
- case R_386_PC16:
- case R_386_PC32:
- return R_PC;
- case R_386_GOTPC:
- return R_GOTONLY_PC_FROM_END;
- case R_386_TLS_IE:
- return R_GOT;
- case R_386_GOT32:
- case R_386_GOT32X:
- // These relocations can be calculated in two different ways.
- // Usual calculation is G + A - GOT what means an offset in GOT table
- // (R_GOT_FROM_END). When instruction pointed by relocation has no base
- // register, then relocations can be used when PIC code is disabled. In that
- // case calculation is G + A, it resolves to an address of entry in GOT
- // (R_GOT) and not an offset.
- //
- // To check that instruction has no base register we scan ModR/M byte.
- // See "Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte"
- // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/
- // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf)
- if ((Loc[-1] & 0xc7) != 0x5)
- return R_GOT_FROM_END;
- if (Config->Pic)
- error(toString(S.File) + ": relocation " + toString(Type) + " against '" +
- S.getName() +
- "' without base register can not be used when PIC enabled");
- return R_GOT;
- case R_386_TLS_GOTIE:
- return R_GOT_FROM_END;
- case R_386_GOTOFF:
- return R_GOTREL_FROM_END;
- case R_386_TLS_LE:
- return R_TLS;
- case R_386_TLS_LE_32:
- return R_NEG_TLS;
- case R_386_NONE:
- return R_NONE;
- default:
- error(toString(S.File) + ": unknown relocation type: " + toString(Type));
- return R_HINT;
- }
-}
-
-RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
- RelExpr Expr) const {
- switch (Expr) {
- default:
- return Expr;
- case R_RELAX_TLS_GD_TO_IE:
- return R_RELAX_TLS_GD_TO_IE_END;
- case R_RELAX_TLS_GD_TO_LE:
- return R_RELAX_TLS_GD_TO_LE_NEG;
- }
-}
-
-void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const {
- write32le(Buf, InX::Dynamic->getVA());
-}
-
-void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {
- // Entries in .got.plt initially points back to the corresponding
- // PLT entries with a fixed offset to skip the first instruction.
- write32le(Buf, S.getPltVA() + 6);
-}
-
-void X86TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const {
- // An x86 entry is the address of the ifunc resolver function.
- write32le(Buf, S.getVA());
-}
-
-uint32_t X86TargetInfo::getDynRel(uint32_t Type) const {
- if (Type == R_386_TLS_LE)
- return R_386_TLS_TPOFF;
- if (Type == R_386_TLS_LE_32)
- return R_386_TLS_TPOFF32;
- return Type;
-}
-
-void X86TargetInfo::writePltHeader(uint8_t *Buf) const {
- if (Config->Pic) {
- const uint8_t V[] = {
- 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl GOTPLT+4(%ebx)
- 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *GOTPLT+8(%ebx)
- 0x90, 0x90, 0x90, 0x90 // nop
- };
- memcpy(Buf, V, sizeof(V));
-
- uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
- uint32_t GotPlt = InX::GotPlt->getVA() - Ebx;
- write32le(Buf + 2, GotPlt + 4);
- write32le(Buf + 8, GotPlt + 8);
- return;
- }
-
- const uint8_t PltData[] = {
- 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOTPLT+4)
- 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOTPLT+8)
- 0x90, 0x90, 0x90, 0x90 // nop
- };
- memcpy(Buf, PltData, sizeof(PltData));
- uint32_t GotPlt = InX::GotPlt->getVA();
- write32le(Buf + 2, GotPlt + 4);
- write32le(Buf + 8, GotPlt + 8);
-}
-
-void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
- uint64_t PltEntryAddr, int32_t Index,
- unsigned RelOff) const {
- const uint8_t Inst[] = {
- 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx)
- 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset
- 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC
- };
- memcpy(Buf, Inst, sizeof(Inst));
-
- if (Config->Pic) {
- // jmp *foo@GOT(%ebx)
- uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
- Buf[1] = 0xa3;
- write32le(Buf + 2, GotPltEntryAddr - Ebx);
- } else {
- // jmp *foo_in_GOT
- Buf[1] = 0x25;
- write32le(Buf + 2, GotPltEntryAddr);
- }
-
- write32le(Buf + 7, RelOff);
- write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
-}
-
-int64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf,
- uint32_t Type) const {
- switch (Type) {
- default:
- return 0;
- case R_386_8:
- case R_386_PC8:
- return SignExtend64<8>(*Buf);
- case R_386_16:
- case R_386_PC16:
- return SignExtend64<16>(read16le(Buf));
- case R_386_32:
- case R_386_GOT32:
- case R_386_GOT32X:
- case R_386_GOTOFF:
- case R_386_GOTPC:
- case R_386_PC32:
- case R_386_PLT32:
- case R_386_TLS_LDO_32:
- case R_386_TLS_LE:
- return SignExtend64<32>(read32le(Buf));
- }
-}
-
-void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // R_386_{PC,}{8,16} are not part of the i386 psABI, but they are
- // being used for some 16-bit programs such as boot loaders, so
- // we want to support them.
- switch (Type) {
- case R_386_8:
- checkUInt<8>(Loc, Val, Type);
- *Loc = Val;
- break;
- case R_386_PC8:
- checkInt<8>(Loc, Val, Type);
- *Loc = Val;
- break;
- case R_386_16:
- checkUInt<16>(Loc, Val, Type);
- write16le(Loc, Val);
- break;
- case R_386_PC16:
- // R_386_PC16 is normally used with 16 bit code. In that situation
- // the PC is 16 bits, just like the addend. This means that it can
- // point from any 16 bit address to any other if the possibility
- // of wrapping is included.
- // The only restriction we have to check then is that the destination
- // address fits in 16 bits. That is impossible to do here. The problem is
- // that we are passed the final value, which already had the
- // current location subtracted from it.
- // We just check that Val fits in 17 bits. This misses some cases, but
- // should have no false positives.
- checkInt<17>(Loc, Val, Type);
- write16le(Loc, Val);
- break;
- default:
- checkInt<32>(Loc, Val, Type);
- write32le(Loc, Val);
- }
-}
-
-void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // Convert
- // leal x@tlsgd(, %ebx, 1),
- // call __tls_get_addr@plt
- // to
- // movl %gs:0,%eax
- // subl $x@ntpoff,%eax
- const uint8_t Inst[] = {
- 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
- 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax
- };
- memcpy(Loc - 3, Inst, sizeof(Inst));
- write32le(Loc + 5, Val);
-}
-
-void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // Convert
- // leal x@tlsgd(, %ebx, 1),
- // call __tls_get_addr@plt
- // to
- // movl %gs:0, %eax
- // addl x@gotntpoff(%ebx), %eax
- const uint8_t Inst[] = {
- 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax
- 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax
- };
- memcpy(Loc - 3, Inst, sizeof(Inst));
- write32le(Loc + 5, Val);
-}
-
-// In some conditions, relocations can be optimized to avoid using GOT.
-// This function does that for Initial Exec to Local Exec case.
-void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // Ulrich's document section 6.2 says that @gotntpoff can
- // be used with MOVL or ADDL instructions.
- // @indntpoff is similar to @gotntpoff, but for use in
- // position dependent code.
- uint8_t Reg = (Loc[-1] >> 3) & 7;
-
- if (Type == R_386_TLS_IE) {
- if (Loc[-1] == 0xa1) {
- // "movl foo@indntpoff,%eax" -> "movl $foo,%eax"
- // This case is different from the generic case below because
- // this is a 5 byte instruction while below is 6 bytes.
- Loc[-1] = 0xb8;
- } else if (Loc[-2] == 0x8b) {
- // "movl foo@indntpoff,%reg" -> "movl $foo,%reg"
- Loc[-2] = 0xc7;
- Loc[-1] = 0xc0 | Reg;
- } else {
- // "addl foo@indntpoff,%reg" -> "addl $foo,%reg"
- Loc[-2] = 0x81;
- Loc[-1] = 0xc0 | Reg;
- }
- } else {
- assert(Type == R_386_TLS_GOTIE);
- if (Loc[-2] == 0x8b) {
- // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg"
- Loc[-2] = 0xc7;
- Loc[-1] = 0xc0 | Reg;
- } else {
- // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg"
- Loc[-2] = 0x8d;
- Loc[-1] = 0x80 | (Reg << 3) | Reg;
- }
- }
- write32le(Loc, Val);
-}
-
-void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- if (Type == R_386_TLS_LDO_32) {
- write32le(Loc, Val);
- return;
- }
-
- // Convert
- // leal foo(%reg),%eax
- // call ___tls_get_addr
- // to
- // movl %gs:0,%eax
- // nop
- // leal 0(%esi,1),%esi
- const uint8_t Inst[] = {
- 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax
- 0x90, // nop
- 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi
- };
- memcpy(Loc - 2, Inst, sizeof(Inst));
-}
-
-template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() {
- CopyRel = R_X86_64_COPY;
- GotRel = R_X86_64_GLOB_DAT;
- PltRel = R_X86_64_JUMP_SLOT;
- RelativeRel = R_X86_64_RELATIVE;
- IRelativeRel = R_X86_64_IRELATIVE;
- TlsGotRel = R_X86_64_TPOFF64;
- TlsModuleIndexRel = R_X86_64_DTPMOD64;
- TlsOffsetRel = R_X86_64_DTPOFF64;
- GotEntrySize = 8;
- GotPltEntrySize = 8;
- PltEntrySize = 16;
- PltHeaderSize = 16;
- TlsGdRelaxSkip = 2;
- // Align to the large page size (known as a superpage or huge page).
- // FreeBSD automatically promotes large, superpage-aligned allocations.
- DefaultImageBase = 0x200000;
- // 0xCC is the "int3" (call debug exception handler) instruction.
- TrapInstr = 0xcccccccc;
-}
-
-template <class ELFT>
-RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const {
- switch (Type) {
- case R_X86_64_8:
- case R_X86_64_16:
- case R_X86_64_32:
- case R_X86_64_32S:
- case R_X86_64_64:
- case R_X86_64_DTPOFF32:
- case R_X86_64_DTPOFF64:
- return R_ABS;
- case R_X86_64_TPOFF32:
- return R_TLS;
- case R_X86_64_TLSLD:
- return R_TLSLD_PC;
- case R_X86_64_TLSGD:
- return R_TLSGD_PC;
- case R_X86_64_SIZE32:
- case R_X86_64_SIZE64:
- return R_SIZE;
- case R_X86_64_PLT32:
- return R_PLT_PC;
- case R_X86_64_PC32:
- case R_X86_64_PC64:
- return R_PC;
- case R_X86_64_GOT32:
- case R_X86_64_GOT64:
- return R_GOT_FROM_END;
- case R_X86_64_GOTPCREL:
- case R_X86_64_GOTPCRELX:
- case R_X86_64_REX_GOTPCRELX:
- case R_X86_64_GOTTPOFF:
- return R_GOT_PC;
- case R_X86_64_NONE:
- return R_NONE;
- default:
- error(toString(S.File) + ": unknown relocation type: " + toString(Type));
- return R_HINT;
- }
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const {
- // The first entry holds the value of _DYNAMIC. It is not clear why that is
- // required, but it is documented in the psabi and the glibc dynamic linker
- // seems to use it (note that this is relevant for linking ld.so, not any
- // other program).
- write64le(Buf, InX::Dynamic->getVA());
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf,
- const SymbolBody &S) const {
- // See comments in X86TargetInfo::writeGotPlt.
- write32le(Buf, S.getPltVA() + 6);
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const {
- const uint8_t PltData[] = {
- 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOTPLT+8(%rip)
- 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOTPLT+16(%rip)
- 0x0f, 0x1f, 0x40, 0x00 // nop
- };
- memcpy(Buf, PltData, sizeof(PltData));
- uint64_t GotPlt = InX::GotPlt->getVA();
- uint64_t Plt = InX::Plt->getVA();
- write32le(Buf + 2, GotPlt - Plt + 2); // GOTPLT+8
- write32le(Buf + 8, GotPlt - Plt + 4); // GOTPLT+16
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
- uint64_t PltEntryAddr, int32_t Index,
- unsigned RelOff) const {
- const uint8_t Inst[] = {
- 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip)
- 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index>
- 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0]
- };
- memcpy(Buf, Inst, sizeof(Inst));
-
- write32le(Buf + 2, GotPltEntryAddr - PltEntryAddr - 6);
- write32le(Buf + 7, Index);
- write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
-}
-
-template <class ELFT>
-bool X86_64TargetInfo<ELFT>::isPicRel(uint32_t Type) const {
- return Type != R_X86_64_PC32 && Type != R_X86_64_32 &&
- Type != R_X86_64_TPOFF32;
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // Convert
- // .byte 0x66
- // leaq x@tlsgd(%rip), %rdi
- // .word 0x6666
- // rex64
- // call __tls_get_addr@plt
- // to
- // mov %fs:0x0,%rax
- // lea x@tpoff,%rax
- const uint8_t Inst[] = {
- 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
- 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax
- };
- memcpy(Loc - 4, Inst, sizeof(Inst));
-
- // The original code used a pc relative relocation and so we have to
- // compensate for the -4 in had in the addend.
- write32le(Loc + 8, Val + 4);
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // Convert
- // .byte 0x66
- // leaq x@tlsgd(%rip), %rdi
- // .word 0x6666
- // rex64
- // call __tls_get_addr@plt
- // to
- // mov %fs:0x0,%rax
- // addq x@tpoff,%rax
- const uint8_t Inst[] = {
- 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
- 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax
- };
- memcpy(Loc - 4, Inst, sizeof(Inst));
-
- // Both code sequences are PC relatives, but since we are moving the constant
- // forward by 8 bytes we have to subtract the value by 8.
- write32le(Loc + 8, Val - 8);
-}
-
-// In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to
-// R_X86_64_TPOFF32 so that it does not use GOT.
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- uint8_t *Inst = Loc - 3;
- uint8_t Reg = Loc[-1] >> 3;
- uint8_t *RegSlot = Loc - 1;
-
- // Note that ADD with RSP or R12 is converted to ADD instead of LEA
- // because LEA with these registers needs 4 bytes to encode and thus
- // wouldn't fit the space.
-
- if (memcmp(Inst, "\x48\x03\x25", 3) == 0) {
- // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp"
- memcpy(Inst, "\x48\x81\xc4", 3);
- } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) {
- // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12"
- memcpy(Inst, "\x49\x81\xc4", 3);
- } else if (memcmp(Inst, "\x4c\x03", 2) == 0) {
- // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]"
- memcpy(Inst, "\x4d\x8d", 2);
- *RegSlot = 0x80 | (Reg << 3) | Reg;
- } else if (memcmp(Inst, "\x48\x03", 2) == 0) {
- // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg"
- memcpy(Inst, "\x48\x8d", 2);
- *RegSlot = 0x80 | (Reg << 3) | Reg;
- } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) {
- // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
- memcpy(Inst, "\x49\xc7", 2);
- *RegSlot = 0xc0 | Reg;
- } else if (memcmp(Inst, "\x48\x8b", 2) == 0) {
- // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
- memcpy(Inst, "\x48\xc7", 2);
- *RegSlot = 0xc0 | Reg;
- } else {
- error(getErrorLocation(Loc - 3) +
- "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only");
- }
-
- // The original code used a PC relative relocation.
- // Need to compensate for the -4 it had in the addend.
- write32le(Loc, Val + 4);
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // Convert
- // leaq bar@tlsld(%rip), %rdi
- // callq __tls_get_addr@PLT
- // leaq bar@dtpoff(%rax), %rcx
- // to
- // .word 0x6666
- // .byte 0x66
- // mov %fs:0,%rax
- // leaq bar@tpoff(%rax), %rcx
- if (Type == R_X86_64_DTPOFF64) {
- write64le(Loc, Val);
- return;
- }
- if (Type == R_X86_64_DTPOFF32) {
- write32le(Loc, Val);
- return;
- }
-
- const uint8_t Inst[] = {
- 0x66, 0x66, // .word 0x6666
- 0x66, // .byte 0x66
- 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax
- };
- memcpy(Loc - 3, Inst, sizeof(Inst));
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- switch (Type) {
- case R_X86_64_8:
- checkUInt<8>(Loc, Val, Type);
- *Loc = Val;
- break;
- case R_X86_64_16:
- checkUInt<16>(Loc, Val, Type);
- write16le(Loc, Val);
- break;
- case R_X86_64_32:
- checkUInt<32>(Loc, Val, Type);
- write32le(Loc, Val);
- break;
- case R_X86_64_32S:
- case R_X86_64_TPOFF32:
- case R_X86_64_GOT32:
- case R_X86_64_GOTPCREL:
- case R_X86_64_GOTPCRELX:
- case R_X86_64_REX_GOTPCRELX:
- case R_X86_64_PC32:
- case R_X86_64_GOTTPOFF:
- case R_X86_64_PLT32:
- case R_X86_64_TLSGD:
- case R_X86_64_TLSLD:
- case R_X86_64_DTPOFF32:
- case R_X86_64_SIZE32:
- checkInt<32>(Loc, Val, Type);
- write32le(Loc, Val);
- break;
- case R_X86_64_64:
- case R_X86_64_DTPOFF64:
- case R_X86_64_GLOB_DAT:
- case R_X86_64_PC64:
- case R_X86_64_SIZE64:
- case R_X86_64_GOT64:
- write64le(Loc, Val);
- break;
- default:
- llvm_unreachable("unexpected relocation");
- }
-}
-
-template <class ELFT>
-RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type,
- const uint8_t *Data,
- RelExpr RelExpr) const {
- if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX)
- return RelExpr;
- const uint8_t Op = Data[-2];
- const uint8_t ModRm = Data[-1];
-
- // FIXME: When PIC is disabled and foo is defined locally in the
- // lower 32 bit address space, memory operand in mov can be converted into
- // immediate operand. Otherwise, mov must be changed to lea. We support only
- // latter relaxation at this moment.
- if (Op == 0x8b)
- return R_RELAX_GOT_PC;
-
- // Relax call and jmp.
- if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25))
- return R_RELAX_GOT_PC;
-
- // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor.
- // If PIC then no relaxation is available.
- // We also don't relax test/binop instructions without REX byte,
- // they are 32bit operations and not common to have.
- assert(Type == R_X86_64_REX_GOTPCRELX);
- return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC;
-}
-
-// A subset of relaxations can only be applied for no-PIC. This method
-// handles such relaxations. Instructions encoding information was taken from:
-// "Intel 64 and IA-32 Architectures Software Developer's Manual V2"
-// (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/
-// 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf)
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val,
- uint8_t Op, uint8_t ModRm) const {
- const uint8_t Rex = Loc[-3];
- // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg".
- if (Op == 0x85) {
- // See "TEST-Logical Compare" (4-428 Vol. 2B),
- // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension).
-
- // ModR/M byte has form XX YYY ZZZ, where
- // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1).
- // XX has different meanings:
- // 00: The operand's memory address is in reg1.
- // 01: The operand's memory address is reg1 + a byte-sized displacement.
- // 10: The operand's memory address is reg1 + a word-sized displacement.
- // 11: The operand is reg1 itself.
- // If an instruction requires only one operand, the unused reg2 field
- // holds extra opcode bits rather than a register code
- // 0xC0 == 11 000 000 binary.
- // 0x38 == 00 111 000 binary.
- // We transfer reg2 to reg1 here as operand.
- // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3).
- Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte.
-
- // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32
- // See "TEST-Logical Compare" (4-428 Vol. 2B).
- Loc[-2] = 0xf7;
-
- // Move R bit to the B bit in REX byte.
- // REX byte is encoded as 0100WRXB, where
- // 0100 is 4bit fixed pattern.
- // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the
- // default operand size is used (which is 32-bit for most but not all
- // instructions).
- // REX.R This 1-bit value is an extension to the MODRM.reg field.
- // REX.X This 1-bit value is an extension to the SIB.index field.
- // REX.B This 1-bit value is an extension to the MODRM.rm field or the
- // SIB.base field.
- // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A).
- Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
- write32le(Loc, Val);
- return;
- }
-
- // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub
- // or xor operations.
-
- // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg".
- // Logic is close to one for test instruction above, but we also
- // write opcode extension here, see below for details.
- Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte.
-
- // Primary opcode is 0x81, opcode extension is one of:
- // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB,
- // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP.
- // This value was wrote to MODRM.reg in a line above.
- // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15),
- // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for
- // descriptions about each operation.
- Loc[-2] = 0x81;
- Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
- write32le(Loc, Val);
-}
-
-template <class ELFT>
-void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const {
- const uint8_t Op = Loc[-2];
- const uint8_t ModRm = Loc[-1];
-
- // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg".
- if (Op == 0x8b) {
- Loc[-2] = 0x8d;
- write32le(Loc, Val);
- return;
- }
-
- if (Op != 0xff) {
- // We are relaxing a rip relative to an absolute, so compensate
- // for the old -4 addend.
- assert(!Config->Pic);
- relaxGotNoPic(Loc, Val + 4, Op, ModRm);
- return;
- }
-
- // Convert call/jmp instructions.
- if (ModRm == 0x15) {
- // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo".
- // Instead we convert to "addr32 call foo" where addr32 is an instruction
- // prefix. That makes result expression to be a single instruction.
- Loc[-2] = 0x67; // addr32 prefix
- Loc[-1] = 0xe8; // call
- write32le(Loc, Val);
- return;
- }
-
- // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop".
- // jmp doesn't return, so it is fine to use nop here, it is just a stub.
- assert(ModRm == 0x25);
- Loc[-2] = 0xe9; // jmp
- Loc[3] = 0x90; // nop
- write32le(Loc - 1, Val + 1);
-}
-
-// Relocation masks following the #lo(value), #hi(value), #ha(value),
-// #higher(value), #highera(value), #highest(value), and #highesta(value)
-// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
-// document.
-static uint16_t applyPPCLo(uint64_t V) { return V; }
-static uint16_t applyPPCHi(uint64_t V) { return V >> 16; }
-static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; }
-static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; }
-static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; }
-static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; }
-static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; }
-
-PPCTargetInfo::PPCTargetInfo() {}
-
-void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- switch (Type) {
- case R_PPC_ADDR16_HA:
- write16be(Loc, applyPPCHa(Val));
- break;
- case R_PPC_ADDR16_LO:
- write16be(Loc, applyPPCLo(Val));
- break;
- case R_PPC_ADDR32:
- case R_PPC_REL32:
- write32be(Loc, Val);
- break;
- case R_PPC_REL24:
- or32be(Loc, Val & 0x3FFFFFC);
- break;
- default:
- error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
- }
-}
-
-RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const {
- switch (Type) {
- case R_PPC_REL24:
- case R_PPC_REL32:
- return R_PC;
- default:
- return R_ABS;
- }
-}
-
-PPC64TargetInfo::PPC64TargetInfo() {
- PltRel = GotRel = R_PPC64_GLOB_DAT;
- RelativeRel = R_PPC64_RELATIVE;
- GotEntrySize = 8;
- GotPltEntrySize = 8;
- PltEntrySize = 32;
- PltHeaderSize = 0;
-
- // We need 64K pages (at least under glibc/Linux, the loader won't
- // set different permissions on a finer granularity than that).
- DefaultMaxPageSize = 65536;
-
- // The PPC64 ELF ABI v1 spec, says:
- //
- // It is normally desirable to put segments with different characteristics
- // in separate 256 Mbyte portions of the address space, to give the
- // operating system full paging flexibility in the 64-bit address space.
- //
- // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
- // use 0x10000000 as the starting address.
- DefaultImageBase = 0x10000000;
-}
-
-static uint64_t PPC64TocOffset = 0x8000;
-
-uint64_t getPPC64TocBase() {
- // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
- // TOC starts where the first of these sections starts. We always create a
- // .got when we see a relocation that uses it, so for us the start is always
- // the .got.
- uint64_t TocVA = InX::Got->getVA();
-
- // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
- // thus permitting a full 64 Kbytes segment. Note that the glibc startup
- // code (crt1.o) assumes that you can get from the TOC base to the
- // start of the .toc section with only a single (signed) 16-bit relocation.
- return TocVA + PPC64TocOffset;
-}
-
-RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const {
- switch (Type) {
- default:
- return R_ABS;
- case R_PPC64_TOC16:
- case R_PPC64_TOC16_DS:
- case R_PPC64_TOC16_HA:
- case R_PPC64_TOC16_HI:
- case R_PPC64_TOC16_LO:
- case R_PPC64_TOC16_LO_DS:
- return R_GOTREL;
- case R_PPC64_TOC:
- return R_PPC_TOC;
- case R_PPC64_REL24:
- return R_PPC_PLT_OPD;
- }
-}
-
-void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
- uint64_t PltEntryAddr, int32_t Index,
- unsigned RelOff) const {
- uint64_t Off = GotPltEntryAddr - getPPC64TocBase();
-
- // FIXME: What we should do, in theory, is get the offset of the function
- // descriptor in the .opd section, and use that as the offset from %r2 (the
- // TOC-base pointer). Instead, we have the GOT-entry offset, and that will
- // be a pointer to the function descriptor in the .opd section. Using
- // this scheme is simpler, but requires an extra indirection per PLT dispatch.
-
- write32be(Buf, 0xf8410028); // std %r2, 40(%r1)
- write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha
- write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11)
- write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12)
- write32be(Buf + 16, 0x7d6903a6); // mtctr %r11
- write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12)
- write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12)
- write32be(Buf + 28, 0x4e800420); // bctr
-}
-
-static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) {
- uint64_t V = Val - PPC64TocOffset;
- switch (Type) {
- case R_PPC64_TOC16:
- return {R_PPC64_ADDR16, V};
- case R_PPC64_TOC16_DS:
- return {R_PPC64_ADDR16_DS, V};
- case R_PPC64_TOC16_HA:
- return {R_PPC64_ADDR16_HA, V};
- case R_PPC64_TOC16_HI:
- return {R_PPC64_ADDR16_HI, V};
- case R_PPC64_TOC16_LO:
- return {R_PPC64_ADDR16_LO, V};
- case R_PPC64_TOC16_LO_DS:
- return {R_PPC64_ADDR16_LO_DS, V};
- default:
- return {Type, Val};
- }
-}
-
-void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // For a TOC-relative relocation, proceed in terms of the corresponding
- // ADDR16 relocation type.
- std::tie(Type, Val) = toAddr16Rel(Type, Val);
-
- switch (Type) {
- case R_PPC64_ADDR14: {
- checkAlignment<4>(Loc, Val, Type);
- // Preserve the AA/LK bits in the branch instruction
- uint8_t AALK = Loc[3];
- write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc));
- break;
- }
- case R_PPC64_ADDR16:
- checkInt<16>(Loc, Val, Type);
- write16be(Loc, Val);
- break;
- case R_PPC64_ADDR16_DS:
- checkInt<16>(Loc, Val, Type);
- write16be(Loc, (read16be(Loc) & 3) | (Val & ~3));
- break;
- case R_PPC64_ADDR16_HA:
- case R_PPC64_REL16_HA:
- write16be(Loc, applyPPCHa(Val));
- break;
- case R_PPC64_ADDR16_HI:
- case R_PPC64_REL16_HI:
- write16be(Loc, applyPPCHi(Val));
- break;
- case R_PPC64_ADDR16_HIGHER:
- write16be(Loc, applyPPCHigher(Val));
- break;
- case R_PPC64_ADDR16_HIGHERA:
- write16be(Loc, applyPPCHighera(Val));
- break;
- case R_PPC64_ADDR16_HIGHEST:
- write16be(Loc, applyPPCHighest(Val));
- break;
- case R_PPC64_ADDR16_HIGHESTA:
- write16be(Loc, applyPPCHighesta(Val));
- break;
- case R_PPC64_ADDR16_LO:
- write16be(Loc, applyPPCLo(Val));
- break;
- case R_PPC64_ADDR16_LO_DS:
- case R_PPC64_REL16_LO:
- write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3));
- break;
- case R_PPC64_ADDR32:
- case R_PPC64_REL32:
- checkInt<32>(Loc, Val, Type);
- write32be(Loc, Val);
- break;
- case R_PPC64_ADDR64:
- case R_PPC64_REL64:
- case R_PPC64_TOC:
- write64be(Loc, Val);
- break;
- case R_PPC64_REL24: {
- uint32_t Mask = 0x03FFFFFC;
- checkInt<24>(Loc, Val, Type);
- write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask));
- break;
- }
- default:
- error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
- }
-}
-
-AArch64TargetInfo::AArch64TargetInfo() {
- CopyRel = R_AARCH64_COPY;
- RelativeRel = R_AARCH64_RELATIVE;
- IRelativeRel = R_AARCH64_IRELATIVE;
- GotRel = R_AARCH64_GLOB_DAT;
- PltRel = R_AARCH64_JUMP_SLOT;
- TlsDescRel = R_AARCH64_TLSDESC;
- TlsGotRel = R_AARCH64_TLS_TPREL64;
- GotEntrySize = 8;
- GotPltEntrySize = 8;
- PltEntrySize = 16;
- PltHeaderSize = 32;
- DefaultMaxPageSize = 65536;
-
- // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
- // 1 of the tls structures and the tcb size is 16.
- TcbSize = 16;
-}
-
-RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const {
- switch (Type) {
- default:
- return R_ABS;
- case R_AARCH64_TLSDESC_ADR_PAGE21:
- return R_TLSDESC_PAGE;
- case R_AARCH64_TLSDESC_LD64_LO12:
- case R_AARCH64_TLSDESC_ADD_LO12:
- return R_TLSDESC;
- case R_AARCH64_TLSDESC_CALL:
- return R_TLSDESC_CALL;
- case R_AARCH64_TLSLE_ADD_TPREL_HI12:
- case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
- return R_TLS;
- case R_AARCH64_CALL26:
- case R_AARCH64_CONDBR19:
- case R_AARCH64_JUMP26:
- case R_AARCH64_TSTBR14:
- return R_PLT_PC;
- case R_AARCH64_PREL16:
- case R_AARCH64_PREL32:
- case R_AARCH64_PREL64:
- case R_AARCH64_ADR_PREL_LO21:
- return R_PC;
- case R_AARCH64_ADR_PREL_PG_HI21:
- return R_PAGE_PC;
- case R_AARCH64_LD64_GOT_LO12_NC:
- case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
- return R_GOT;
- case R_AARCH64_ADR_GOT_PAGE:
- case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
- return R_GOT_PAGE_PC;
- case R_AARCH64_NONE:
- return R_NONE;
- }
-}
-
-RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
- RelExpr Expr) const {
- if (Expr == R_RELAX_TLS_GD_TO_IE) {
- if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
- return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
- return R_RELAX_TLS_GD_TO_IE_ABS;
- }
- return Expr;
-}
-
-bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const {
- switch (Type) {
- default:
- return false;
- case R_AARCH64_ADD_ABS_LO12_NC:
- case R_AARCH64_LD64_GOT_LO12_NC:
- case R_AARCH64_LDST128_ABS_LO12_NC:
- case R_AARCH64_LDST16_ABS_LO12_NC:
- case R_AARCH64_LDST32_ABS_LO12_NC:
- case R_AARCH64_LDST64_ABS_LO12_NC:
- case R_AARCH64_LDST8_ABS_LO12_NC:
- case R_AARCH64_TLSDESC_ADD_LO12:
- case R_AARCH64_TLSDESC_LD64_LO12:
- case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
- return true;
- }
-}
-
-bool AArch64TargetInfo::isPicRel(uint32_t Type) const {
- return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64;
-}
-
-void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
- write64le(Buf, InX::Plt->getVA());
-}
-
-// Page(Expr) is the page address of the expression Expr, defined
-// as (Expr & ~0xFFF). (This applies even if the machine page size
-// supported by the platform has a different value.)
-uint64_t getAArch64Page(uint64_t Expr) {
- return Expr & (~static_cast<uint64_t>(0xFFF));
-}
-
-void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const {
- const uint8_t PltData[] = {
- 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]!
- 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2]))
- 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))]
- 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2]))
- 0x20, 0x02, 0x1f, 0xd6, // br x17
- 0x1f, 0x20, 0x03, 0xd5, // nop
- 0x1f, 0x20, 0x03, 0xd5, // nop
- 0x1f, 0x20, 0x03, 0xd5 // nop
- };
- memcpy(Buf, PltData, sizeof(PltData));
-
- uint64_t Got = InX::GotPlt->getVA();
- uint64_t Plt = InX::Plt->getVA();
- relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
- getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
- relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
- relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
-}
-
-void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
- uint64_t PltEntryAddr, int32_t Index,
- unsigned RelOff) const {
- const uint8_t Inst[] = {
- 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
- 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))]
- 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n]))
- 0x20, 0x02, 0x1f, 0xd6 // br x17
- };
- memcpy(Buf, Inst, sizeof(Inst));
-
- relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
- getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
- relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
- relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
-}
-
-static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
- uint32_t ImmLo = (Imm & 0x3) << 29;
- uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
- uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
- write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
-}
-
-// Return the bits [Start, End] from Val shifted Start bits.
-// For instance, getBits(0xF0, 4, 8) returns 0xF.
-static uint64_t getBits(uint64_t Val, int Start, int End) {
- uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
- return (Val >> Start) & Mask;
-}
-
-// Update the immediate field in a AARCH64 ldr, str, and add instruction.
-static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
- or32le(L, (Imm & 0xFFF) << 10);
-}
-
-void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- switch (Type) {
- case R_AARCH64_ABS16:
- case R_AARCH64_PREL16:
- checkIntUInt<16>(Loc, Val, Type);
- write16le(Loc, Val);
- break;
- case R_AARCH64_ABS32:
- case R_AARCH64_PREL32:
- checkIntUInt<32>(Loc, Val, Type);
- write32le(Loc, Val);
- break;
- case R_AARCH64_ABS64:
- case R_AARCH64_GLOB_DAT:
- case R_AARCH64_PREL64:
- write64le(Loc, Val);
- break;
- case R_AARCH64_ADD_ABS_LO12_NC:
- or32AArch64Imm(Loc, Val);
- break;
- case R_AARCH64_ADR_GOT_PAGE:
- case R_AARCH64_ADR_PREL_PG_HI21:
- case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
- case R_AARCH64_TLSDESC_ADR_PAGE21:
- checkInt<33>(Loc, Val, Type);
- write32AArch64Addr(Loc, Val >> 12);
- break;
- case R_AARCH64_ADR_PREL_LO21:
- checkInt<21>(Loc, Val, Type);
- write32AArch64Addr(Loc, Val);
- break;
- case R_AARCH64_CALL26:
- case R_AARCH64_JUMP26:
- checkInt<28>(Loc, Val, Type);
- or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
- break;
- case R_AARCH64_CONDBR19:
- checkInt<21>(Loc, Val, Type);
- or32le(Loc, (Val & 0x1FFFFC) << 3);
- break;
- case R_AARCH64_LD64_GOT_LO12_NC:
- case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
- case R_AARCH64_TLSDESC_LD64_LO12:
- checkAlignment<8>(Loc, Val, Type);
- or32le(Loc, (Val & 0xFF8) << 7);
- break;
- case R_AARCH64_LDST8_ABS_LO12_NC:
- or32AArch64Imm(Loc, getBits(Val, 0, 11));
- break;
- case R_AARCH64_LDST16_ABS_LO12_NC:
- or32AArch64Imm(Loc, getBits(Val, 1, 11));
- break;
- case R_AARCH64_LDST32_ABS_LO12_NC:
- or32AArch64Imm(Loc, getBits(Val, 2, 11));
- break;
- case R_AARCH64_LDST64_ABS_LO12_NC:
- or32AArch64Imm(Loc, getBits(Val, 3, 11));
- break;
- case R_AARCH64_LDST128_ABS_LO12_NC:
- or32AArch64Imm(Loc, getBits(Val, 4, 11));
- break;
- case R_AARCH64_MOVW_UABS_G0_NC:
- or32le(Loc, (Val & 0xFFFF) << 5);
- break;
- case R_AARCH64_MOVW_UABS_G1_NC:
- or32le(Loc, (Val & 0xFFFF0000) >> 11);
- break;
- case R_AARCH64_MOVW_UABS_G2_NC:
- or32le(Loc, (Val & 0xFFFF00000000) >> 27);
- break;
- case R_AARCH64_MOVW_UABS_G3:
- or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
- break;
- case R_AARCH64_TSTBR14:
- checkInt<16>(Loc, Val, Type);
- or32le(Loc, (Val & 0xFFFC) << 3);
- break;
- case R_AARCH64_TLSLE_ADD_TPREL_HI12:
- checkInt<24>(Loc, Val, Type);
- or32AArch64Imm(Loc, Val >> 12);
- break;
- case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
- case R_AARCH64_TLSDESC_ADD_LO12:
- or32AArch64Imm(Loc, Val);
- break;
- default:
- error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
- }
-}
-
-void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // TLSDESC Global-Dynamic relocation are in the form:
- // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
- // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
- // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
- // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
- // blr x1
- // And it can optimized to:
- // movz x0, #0x0, lsl #16
- // movk x0, #0x10
- // nop
- // nop
- checkUInt<32>(Loc, Val, Type);
-
- switch (Type) {
- case R_AARCH64_TLSDESC_ADD_LO12:
- case R_AARCH64_TLSDESC_CALL:
- write32le(Loc, 0xd503201f); // nop
- return;
- case R_AARCH64_TLSDESC_ADR_PAGE21:
- write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
- return;
- case R_AARCH64_TLSDESC_LD64_LO12:
- write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
- return;
- default:
- llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
- }
-}
-
-void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- // TLSDESC Global-Dynamic relocation are in the form:
- // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21]
- // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12]
- // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12]
- // .tlsdesccall [R_AARCH64_TLSDESC_CALL]
- // blr x1
- // And it can optimized to:
- // adrp x0, :gottprel:v
- // ldr x0, [x0, :gottprel_lo12:v]
- // nop
- // nop
-
- switch (Type) {
- case R_AARCH64_TLSDESC_ADD_LO12:
- case R_AARCH64_TLSDESC_CALL:
- write32le(Loc, 0xd503201f); // nop
- break;
- case R_AARCH64_TLSDESC_ADR_PAGE21:
- write32le(Loc, 0x90000000); // adrp
- relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
- break;
- case R_AARCH64_TLSDESC_LD64_LO12:
- write32le(Loc, 0xf9400000); // ldr
- relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
- break;
- default:
- llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
- }
-}
-
-void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- checkUInt<32>(Loc, Val, Type);
-
- if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
- // Generate MOVZ.
- uint32_t RegNo = read32le(Loc) & 0x1f;
- write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
- return;
- }
- if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
- // Generate MOVK.
- uint32_t RegNo = read32le(Loc) & 0x1f;
- write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
- return;
- }
- llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
-}
-
-AMDGPUTargetInfo::AMDGPUTargetInfo() {
- RelativeRel = R_AMDGPU_REL64;
- GotRel = R_AMDGPU_ABS64;
- GotEntrySize = 8;
-}
-
-void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- switch (Type) {
- case R_AMDGPU_ABS32:
- case R_AMDGPU_GOTPCREL:
- case R_AMDGPU_GOTPCREL32_LO:
- case R_AMDGPU_REL32:
- case R_AMDGPU_REL32_LO:
- write32le(Loc, Val);
- break;
- case R_AMDGPU_ABS64:
- write64le(Loc, Val);
- break;
- case R_AMDGPU_GOTPCREL32_HI:
- case R_AMDGPU_REL32_HI:
- write32le(Loc, Val >> 32);
- break;
- default:
- error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
- }
-}
-
-RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const {
- switch (Type) {
- case R_AMDGPU_ABS32:
- case R_AMDGPU_ABS64:
- return R_ABS;
- case R_AMDGPU_REL32:
- case R_AMDGPU_REL32_LO:
- case R_AMDGPU_REL32_HI:
- return R_PC;
- case R_AMDGPU_GOTPCREL:
- case R_AMDGPU_GOTPCREL32_LO:
- case R_AMDGPU_GOTPCREL32_HI:
- return R_GOT_PC;
- default:
- error(toString(S.File) + ": unknown relocation type: " + toString(Type));
- return R_HINT;
- }
-}
-
-ARMTargetInfo::ARMTargetInfo() {
- CopyRel = R_ARM_COPY;
- RelativeRel = R_ARM_RELATIVE;
- IRelativeRel = R_ARM_IRELATIVE;
- GotRel = R_ARM_GLOB_DAT;
- PltRel = R_ARM_JUMP_SLOT;
- TlsGotRel = R_ARM_TLS_TPOFF32;
- TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
- TlsOffsetRel = R_ARM_TLS_DTPOFF32;
- GotEntrySize = 4;
- GotPltEntrySize = 4;
- PltEntrySize = 16;
- PltHeaderSize = 20;
- // ARM uses Variant 1 TLS
- TcbSize = 8;
- NeedsThunks = true;
-}
-
-RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const {
- switch (Type) {
- default:
- return R_ABS;
- case R_ARM_THM_JUMP11:
- return R_PC;
- case R_ARM_CALL:
- case R_ARM_JUMP24:
- case R_ARM_PC24:
- case R_ARM_PLT32:
- case R_ARM_PREL31:
- case R_ARM_THM_JUMP19:
- case R_ARM_THM_JUMP24:
- case R_ARM_THM_CALL:
- return R_PLT_PC;
- case R_ARM_GOTOFF32:
- // (S + A) - GOT_ORG
- return R_GOTREL;
- case R_ARM_GOT_BREL:
- // GOT(S) + A - GOT_ORG
- return R_GOT_OFF;
- case R_ARM_GOT_PREL:
- case R_ARM_TLS_IE32:
- // GOT(S) + A - P
- return R_GOT_PC;
- case R_ARM_SBREL32:
- return R_ARM_SBREL;
- case R_ARM_TARGET1:
- return Config->Target1Rel ? R_PC : R_ABS;
- case R_ARM_TARGET2:
- if (Config->Target2 == Target2Policy::Rel)
- return R_PC;
- if (Config->Target2 == Target2Policy::Abs)
- return R_ABS;
- return R_GOT_PC;
- case R_ARM_TLS_GD32:
- return R_TLSGD_PC;
- case R_ARM_TLS_LDM32:
- return R_TLSLD_PC;
- case R_ARM_BASE_PREL:
- // B(S) + A - P
- // FIXME: currently B(S) assumed to be .got, this may not hold for all
- // platforms.
- return R_GOTONLY_PC;
- case R_ARM_MOVW_PREL_NC:
- case R_ARM_MOVT_PREL:
- case R_ARM_REL32:
- case R_ARM_THM_MOVW_PREL_NC:
- case R_ARM_THM_MOVT_PREL:
- return R_PC;
- case R_ARM_NONE:
- return R_NONE;
- case R_ARM_TLS_LE32:
- return R_TLS;
- }
-}
-
-bool ARMTargetInfo::isPicRel(uint32_t Type) const {
- return (Type == R_ARM_TARGET1 && !Config->Target1Rel) ||
- (Type == R_ARM_ABS32);
-}
-
-uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const {
- if (Type == R_ARM_TARGET1 && !Config->Target1Rel)
- return R_ARM_ABS32;
- if (Type == R_ARM_ABS32)
- return Type;
- // Keep it going with a dummy value so that we can find more reloc errors.
- return R_ARM_ABS32;
-}
-
-void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
- write32le(Buf, InX::Plt->getVA());
-}
-
-void ARMTargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const {
- // An ARM entry is the address of the ifunc resolver function.
- write32le(Buf, S.getVA());
-}
-
-void ARMTargetInfo::writePltHeader(uint8_t *Buf) const {
- const uint8_t PltData[] = {
- 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]!
- 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2
- 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
- 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8]
- 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8
- };
- memcpy(Buf, PltData, sizeof(PltData));
- uint64_t GotPlt = InX::GotPlt->getVA();
- uint64_t L1 = InX::Plt->getVA() + 8;
- write32le(Buf + 16, GotPlt - L1 - 8);
-}
-
-void ARMTargetInfo::addPltHeaderSymbols(InputSectionBase *ISD) const {
- auto *IS = cast<InputSection>(ISD);
- addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS);
- addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS);
-}
-
-void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
- uint64_t PltEntryAddr, int32_t Index,
- unsigned RelOff) const {
- // FIXME: Using simple code sequence with simple relocations.
- // There is a more optimal sequence but it requires support for the group
- // relocations. See ELF for the ARM Architecture Appendix A.3
- const uint8_t PltData[] = {
- 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2
- 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
- 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip]
- 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8
- };
- memcpy(Buf, PltData, sizeof(PltData));
- uint64_t L1 = PltEntryAddr + 4;
- write32le(Buf + 12, GotPltEntryAddr - L1 - 8);
-}
-
-void ARMTargetInfo::addPltSymbols(InputSectionBase *ISD, uint64_t Off) const {
- auto *IS = cast<InputSection>(ISD);
- addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
- addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
-}
-
-bool ARMTargetInfo::needsThunk(RelExpr Expr, uint32_t RelocType,
- const InputFile *File,
- const SymbolBody &S) const {
- // If S is an undefined weak symbol in an executable we don't need a Thunk.
- // In a DSO calls to undefined symbols, including weak ones get PLT entries
- // which may need a thunk.
- if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() &&
- !Config->Shared)
- return false;
- // A state change from ARM to Thumb and vice versa must go through an
- // interworking thunk if the relocation type is not R_ARM_CALL or
- // R_ARM_THM_CALL.
- switch (RelocType) {
- case R_ARM_PC24:
- case R_ARM_PLT32:
- case R_ARM_JUMP24:
- // Source is ARM, all PLT entries are ARM so no interworking required.
- // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
- if (Expr == R_PC && ((S.getVA() & 1) == 1))
- return true;
- break;
- case R_ARM_THM_JUMP19:
- case R_ARM_THM_JUMP24:
- // Source is Thumb, all PLT entries are ARM so interworking is required.
- // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
- if (Expr == R_PLT_PC || ((S.getVA() & 1) == 0))
- return true;
- break;
- }
- return false;
-}
-
-void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- switch (Type) {
- case R_ARM_ABS32:
- case R_ARM_BASE_PREL:
- case R_ARM_GLOB_DAT:
- case R_ARM_GOTOFF32:
- case R_ARM_GOT_BREL:
- case R_ARM_GOT_PREL:
- case R_ARM_REL32:
- case R_ARM_RELATIVE:
- case R_ARM_SBREL32:
- case R_ARM_TARGET1:
- case R_ARM_TARGET2:
- case R_ARM_TLS_GD32:
- case R_ARM_TLS_IE32:
- case R_ARM_TLS_LDM32:
- case R_ARM_TLS_LDO32:
- case R_ARM_TLS_LE32:
- case R_ARM_TLS_TPOFF32:
- case R_ARM_TLS_DTPOFF32:
- write32le(Loc, Val);
- break;
- case R_ARM_TLS_DTPMOD32:
- write32le(Loc, 1);
- break;
- case R_ARM_PREL31:
- checkInt<31>(Loc, Val, Type);
- write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
- break;
- case R_ARM_CALL:
- // R_ARM_CALL is used for BL and BLX instructions, depending on the
- // value of bit 0 of Val, we must select a BL or BLX instruction
- if (Val & 1) {
- // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
- // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
- checkInt<26>(Loc, Val, Type);
- write32le(Loc, 0xfa000000 | // opcode
- ((Val & 2) << 23) | // H
- ((Val >> 2) & 0x00ffffff)); // imm24
- break;
- }
- if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
- // BLX (always unconditional) instruction to an ARM Target, select an
- // unconditional BL.
- write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
- // fall through as BL encoding is shared with B
- LLVM_FALLTHROUGH;
- case R_ARM_JUMP24:
- case R_ARM_PC24:
- case R_ARM_PLT32:
- checkInt<26>(Loc, Val, Type);
- write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
- break;
- case R_ARM_THM_JUMP11:
- checkInt<12>(Loc, Val, Type);
- write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
- break;
- case R_ARM_THM_JUMP19:
- // Encoding T3: Val = S:J2:J1:imm6:imm11:0
- checkInt<21>(Loc, Val, Type);
- write16le(Loc,
- (read16le(Loc) & 0xfbc0) | // opcode cond
- ((Val >> 10) & 0x0400) | // S
- ((Val >> 12) & 0x003f)); // imm6
- write16le(Loc + 2,
- 0x8000 | // opcode
- ((Val >> 8) & 0x0800) | // J2
- ((Val >> 5) & 0x2000) | // J1
- ((Val >> 1) & 0x07ff)); // imm11
- break;
- case R_ARM_THM_CALL:
- // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
- // value of bit 0 of Val, we must select a BL or BLX instruction
- if ((Val & 1) == 0) {
- // Ensure BLX destination is 4-byte aligned. As BLX instruction may
- // only be two byte aligned. This must be done before overflow check
- Val = alignTo(Val, 4);
- }
- // Bit 12 is 0 for BLX, 1 for BL
- write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
- // Fall through as rest of encoding is the same as B.W
- LLVM_FALLTHROUGH;
- case R_ARM_THM_JUMP24:
- // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
- // FIXME: Use of I1 and I2 require v6T2ops
- checkInt<25>(Loc, Val, Type);
- write16le(Loc,
- 0xf000 | // opcode
- ((Val >> 14) & 0x0400) | // S
- ((Val >> 12) & 0x03ff)); // imm10
- write16le(Loc + 2,
- (read16le(Loc + 2) & 0xd000) | // opcode
- (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
- (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
- ((Val >> 1) & 0x07ff)); // imm11
- break;
- case R_ARM_MOVW_ABS_NC:
- case R_ARM_MOVW_PREL_NC:
- write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
- (Val & 0x0fff));
- break;
- case R_ARM_MOVT_ABS:
- case R_ARM_MOVT_PREL:
- checkInt<32>(Loc, Val, Type);
- write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
- (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
- break;
- case R_ARM_THM_MOVT_ABS:
- case R_ARM_THM_MOVT_PREL:
- // Encoding T1: A = imm4:i:imm3:imm8
- checkInt<32>(Loc, Val, Type);
- write16le(Loc,
- 0xf2c0 | // opcode
- ((Val >> 17) & 0x0400) | // i
- ((Val >> 28) & 0x000f)); // imm4
- write16le(Loc + 2,
- (read16le(Loc + 2) & 0x8f00) | // opcode
- ((Val >> 12) & 0x7000) | // imm3
- ((Val >> 16) & 0x00ff)); // imm8
- break;
- case R_ARM_THM_MOVW_ABS_NC:
- case R_ARM_THM_MOVW_PREL_NC:
- // Encoding T3: A = imm4:i:imm3:imm8
- write16le(Loc,
- 0xf240 | // opcode
- ((Val >> 1) & 0x0400) | // i
- ((Val >> 12) & 0x000f)); // imm4
- write16le(Loc + 2,
- (read16le(Loc + 2) & 0x8f00) | // opcode
- ((Val << 4) & 0x7000) | // imm3
- (Val & 0x00ff)); // imm8
- break;
- default:
- error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
- }
-}
-
-int64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf,
- uint32_t Type) const {
- switch (Type) {
- default:
- return 0;
- case R_ARM_ABS32:
- case R_ARM_BASE_PREL:
- case R_ARM_GOTOFF32:
- case R_ARM_GOT_BREL:
- case R_ARM_GOT_PREL:
- case R_ARM_REL32:
- case R_ARM_TARGET1:
- case R_ARM_TARGET2:
- case R_ARM_TLS_GD32:
- case R_ARM_TLS_LDM32:
- case R_ARM_TLS_LDO32:
- case R_ARM_TLS_IE32:
- case R_ARM_TLS_LE32:
- return SignExtend64<32>(read32le(Buf));
- case R_ARM_PREL31:
- return SignExtend64<31>(read32le(Buf));
- case R_ARM_CALL:
- case R_ARM_JUMP24:
- case R_ARM_PC24:
- case R_ARM_PLT32:
- return SignExtend64<26>(read32le(Buf) << 2);
- case R_ARM_THM_JUMP11:
- return SignExtend64<12>(read16le(Buf) << 1);
- case R_ARM_THM_JUMP19: {
- // Encoding T3: A = S:J2:J1:imm10:imm6:0
- uint16_t Hi = read16le(Buf);
- uint16_t Lo = read16le(Buf + 2);
- return SignExtend64<20>(((Hi & 0x0400) << 10) | // S
- ((Lo & 0x0800) << 8) | // J2
- ((Lo & 0x2000) << 5) | // J1
- ((Hi & 0x003f) << 12) | // imm6
- ((Lo & 0x07ff) << 1)); // imm11:0
- }
- case R_ARM_THM_CALL:
- case R_ARM_THM_JUMP24: {
- // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
- // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
- // FIXME: I1 and I2 require v6T2ops
- uint16_t Hi = read16le(Buf);
- uint16_t Lo = read16le(Buf + 2);
- return SignExtend64<24>(((Hi & 0x0400) << 14) | // S
- (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1
- (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2
- ((Hi & 0x003ff) << 12) | // imm0
- ((Lo & 0x007ff) << 1)); // imm11:0
- }
- // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
- // MOVT is in the range -32768 <= A < 32768
- case R_ARM_MOVW_ABS_NC:
- case R_ARM_MOVT_ABS:
- case R_ARM_MOVW_PREL_NC:
- case R_ARM_MOVT_PREL: {
- uint64_t Val = read32le(Buf) & 0x000f0fff;
- return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff));
- }
- case R_ARM_THM_MOVW_ABS_NC:
- case R_ARM_THM_MOVT_ABS:
- case R_ARM_THM_MOVW_PREL_NC:
- case R_ARM_THM_MOVT_PREL: {
- // Encoding T3: A = imm4:i:imm3:imm8
- uint16_t Hi = read16le(Buf);
- uint16_t Lo = read16le(Buf + 2);
- return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4
- ((Hi & 0x0400) << 1) | // i
- ((Lo & 0x7000) >> 4) | // imm3
- (Lo & 0x00ff)); // imm8
- }
- }
-}
-
-template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() {
- GotPltHeaderEntriesNum = 2;
- DefaultMaxPageSize = 65536;
- GotEntrySize = sizeof(typename ELFT::uint);
- GotPltEntrySize = sizeof(typename ELFT::uint);
- PltEntrySize = 16;
- PltHeaderSize = 32;
- CopyRel = R_MIPS_COPY;
- PltRel = R_MIPS_JUMP_SLOT;
- NeedsThunks = true;
- if (ELFT::Is64Bits) {
- RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
- TlsGotRel = R_MIPS_TLS_TPREL64;
- TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64;
- TlsOffsetRel = R_MIPS_TLS_DTPREL64;
- } else {
- RelativeRel = R_MIPS_REL32;
- TlsGotRel = R_MIPS_TLS_TPREL32;
- TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32;
- TlsOffsetRel = R_MIPS_TLS_DTPREL32;
- }
-}
-
-template <class ELFT>
-RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S,
- const uint8_t *Loc) const {
- // See comment in the calculateMipsRelChain.
- if (ELFT::Is64Bits || Config->MipsN32Abi)
- Type &= 0xff;
- switch (Type) {
- default:
- return R_ABS;
- case R_MIPS_JALR:
- return R_HINT;
- case R_MIPS_GPREL16:
- case R_MIPS_GPREL32:
- return R_MIPS_GOTREL;
- case R_MIPS_26:
- return R_PLT;
- case R_MIPS_HI16:
- case R_MIPS_LO16:
- // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate
- // offset between start of function and 'gp' value which by default
- // equal to the start of .got section. In that case we consider these
- // relocations as relative.
- if (&S == ElfSym::MipsGpDisp)
- return R_MIPS_GOT_GP_PC;
- if (&S == ElfSym::MipsLocalGp)
- return R_MIPS_GOT_GP;
- LLVM_FALLTHROUGH;
- case R_MIPS_GOT_OFST:
- return R_ABS;
- case R_MIPS_PC32:
- case R_MIPS_PC16:
- case R_MIPS_PC19_S2:
- case R_MIPS_PC21_S2:
- case R_MIPS_PC26_S2:
- case R_MIPS_PCHI16:
- case R_MIPS_PCLO16:
- return R_PC;
- case R_MIPS_GOT16:
- if (S.isLocal())
- return R_MIPS_GOT_LOCAL_PAGE;
- LLVM_FALLTHROUGH;
- case R_MIPS_CALL16:
- case R_MIPS_GOT_DISP:
- case R_MIPS_TLS_GOTTPREL:
- return R_MIPS_GOT_OFF;
- case R_MIPS_CALL_HI16:
- case R_MIPS_CALL_LO16:
- case R_MIPS_GOT_HI16:
- case R_MIPS_GOT_LO16:
- return R_MIPS_GOT_OFF32;
- case R_MIPS_GOT_PAGE:
- return R_MIPS_GOT_LOCAL_PAGE;
- case R_MIPS_TLS_GD:
- return R_MIPS_TLSGD;
- case R_MIPS_TLS_LDM:
- return R_MIPS_TLSLD;
- }
-}
-
-template <class ELFT> bool MipsTargetInfo<ELFT>::isPicRel(uint32_t Type) const {
- return Type == R_MIPS_32 || Type == R_MIPS_64;
-}
-
-template <class ELFT>
-uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const {
- return RelativeRel;
-}
-
-template <class ELFT>
-void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
- write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA());
-}
-
-template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
-static int64_t getPcRelocAddend(const uint8_t *Loc) {
- uint32_t Instr = read32<E>(Loc);
- uint32_t Mask = 0xffffffff >> (32 - BSIZE);
- return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT);
-}
-
-template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
-static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) {
- uint32_t Mask = 0xffffffff >> (32 - BSIZE);
- uint32_t Instr = read32<E>(Loc);
- if (SHIFT > 0)
- checkAlignment<(1 << SHIFT)>(Loc, V, Type);
- checkInt<BSIZE + SHIFT>(Loc, V, Type);
- write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask));
-}
-
-template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) {
- uint32_t Instr = read32<E>(Loc);
- uint16_t Res = ((V + 0x8000) >> 16) & 0xffff;
- write32<E>(Loc, (Instr & 0xffff0000) | Res);
-}
-
-template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) {
- uint32_t Instr = read32<E>(Loc);
- uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff;
- write32<E>(Loc, (Instr & 0xffff0000) | Res);
-}
-
-template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) {
- uint32_t Instr = read32<E>(Loc);
- uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff;
- write32<E>(Loc, (Instr & 0xffff0000) | Res);
-}
-
-template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) {
- uint32_t Instr = read32<E>(Loc);
- write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff));
-}
-
-template <class ELFT> static bool isMipsR6() {
- const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf);
- uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH;
- return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6;
-}
-
-template <class ELFT>
-void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const {
- const endianness E = ELFT::TargetEndianness;
- if (Config->MipsN32Abi) {
- write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0])
- write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14)
- write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0])
- write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14
- } else {
- write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0])
- write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28)
- write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0])
- write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28
- }
-
- write32<E>(Buf + 16, 0x03e07825); // move $15, $31
- write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2
- write32<E>(Buf + 24, 0x0320f809); // jalr $25
- write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2
-
- uint64_t GotPlt = InX::GotPlt->getVA();
- writeMipsHi16<E>(Buf, GotPlt);
- writeMipsLo16<E>(Buf + 4, GotPlt);
- writeMipsLo16<E>(Buf + 8, GotPlt);
-}
-
-template <class ELFT>
-void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
- uint64_t PltEntryAddr, int32_t Index,
- unsigned RelOff) const {
- const endianness E = ELFT::TargetEndianness;
- write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry)
- write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15)
- // jr $25
- write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008);
- write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry)
- writeMipsHi16<E>(Buf, GotPltEntryAddr);
- writeMipsLo16<E>(Buf + 4, GotPltEntryAddr);
- writeMipsLo16<E>(Buf + 12, GotPltEntryAddr);
-}
-
-template <class ELFT>
-bool MipsTargetInfo<ELFT>::needsThunk(RelExpr Expr, uint32_t Type,
- const InputFile *File,
- const SymbolBody &S) const {
- // Any MIPS PIC code function is invoked with its address in register $t9.
- // So if we have a branch instruction from non-PIC code to the PIC one
- // we cannot make the jump directly and need to create a small stubs
- // to save the target function address.
- // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
- if (Type != R_MIPS_26)
- return false;
- auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File);
- if (!F)
- return false;
- // If current file has PIC code, LA25 stub is not required.
- if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
- return false;
- auto *D = dyn_cast<DefinedRegular>(&S);
- // LA25 is required if target file has PIC code
- // or target symbol is a PIC symbol.
- return D && D->isMipsPIC<ELFT>();
-}
-
-template <class ELFT>
-int64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf,
- uint32_t Type) const {
- const endianness E = ELFT::TargetEndianness;
- switch (Type) {
- default:
- return 0;
- case R_MIPS_32:
- case R_MIPS_GPREL32:
- case R_MIPS_TLS_DTPREL32:
- case R_MIPS_TLS_TPREL32:
- return SignExtend64<32>(read32<E>(Buf));
- case R_MIPS_26:
- // FIXME (simon): If the relocation target symbol is not a PLT entry
- // we should use another expression for calculation:
- // ((A << 2) | (P & 0xf0000000)) >> 2
- return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2);
- case R_MIPS_GPREL16:
- case R_MIPS_LO16:
- case R_MIPS_PCLO16:
- case R_MIPS_TLS_DTPREL_HI16:
- case R_MIPS_TLS_DTPREL_LO16:
- case R_MIPS_TLS_TPREL_HI16:
- case R_MIPS_TLS_TPREL_LO16:
- return SignExtend64<16>(read32<E>(Buf));
- case R_MIPS_PC16:
- return getPcRelocAddend<E, 16, 2>(Buf);
- case R_MIPS_PC19_S2:
- return getPcRelocAddend<E, 19, 2>(Buf);
- case R_MIPS_PC21_S2:
- return getPcRelocAddend<E, 21, 2>(Buf);
- case R_MIPS_PC26_S2:
- return getPcRelocAddend<E, 26, 2>(Buf);
- case R_MIPS_PC32:
- return getPcRelocAddend<E, 32, 0>(Buf);
- }
-}
-
-static std::pair<uint32_t, uint64_t>
-calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) {
- // MIPS N64 ABI packs multiple relocations into the single relocation
- // record. In general, all up to three relocations can have arbitrary
- // types. In fact, Clang and GCC uses only a few combinations. For now,
- // we support two of them. That is allow to pass at least all LLVM
- // test suite cases.
- // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
- // <any relocation> / R_MIPS_64 / R_MIPS_NONE
- // The first relocation is a 'real' relocation which is calculated
- // using the corresponding symbol's value. The second and the third
- // relocations used to modify result of the first one: extend it to
- // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
- // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
- uint32_t Type2 = (Type >> 8) & 0xff;
- uint32_t Type3 = (Type >> 16) & 0xff;
- if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE)
- return std::make_pair(Type, Val);
- if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE)
- return std::make_pair(Type2, Val);
- if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16))
- return std::make_pair(Type3, -Val);
- error(getErrorLocation(Loc) + "unsupported relocations combination " +
- Twine(Type));
- return std::make_pair(Type & 0xff, Val);
-}
-
-template <class ELFT>
-void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
- uint64_t Val) const {
- const endianness E = ELFT::TargetEndianness;
- // Thread pointer and DRP offsets from the start of TLS data area.
- // https://www.linux-mips.org/wiki/NPTL
- if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
- Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64)
- Val -= 0x8000;
- else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
- Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64)
- Val -= 0x7000;
- if (ELFT::Is64Bits || Config->MipsN32Abi)
- std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
- switch (Type) {
- case R_MIPS_32:
- case R_MIPS_GPREL32:
- case R_MIPS_TLS_DTPREL32:
- case R_MIPS_TLS_TPREL32:
- write32<E>(Loc, Val);
- break;
- case R_MIPS_64:
- case R_MIPS_TLS_DTPREL64:
- case R_MIPS_TLS_TPREL64:
- write64<E>(Loc, Val);
- break;
- case R_MIPS_26:
- write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff));
- break;
- case R_MIPS_GOT16:
- // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
- // is updated addend (not a GOT index). In that case write high 16 bits
- // to store a correct addend value.
- if (Config->Relocatable)
- writeMipsHi16<E>(Loc, Val);
- else {
- checkInt<16>(Loc, Val, Type);
- writeMipsLo16<E>(Loc, Val);
- }
- break;
- case R_MIPS_GOT_DISP:
- case R_MIPS_GOT_PAGE:
- case R_MIPS_GPREL16:
- case R_MIPS_TLS_GD:
- case R_MIPS_TLS_LDM:
- checkInt<16>(Loc, Val, Type);
- LLVM_FALLTHROUGH;
- case R_MIPS_CALL16:
- case R_MIPS_CALL_LO16:
- case R_MIPS_GOT_LO16:
- case R_MIPS_GOT_OFST:
- case R_MIPS_LO16:
- case R_MIPS_PCLO16:
- case R_MIPS_TLS_DTPREL_LO16:
- case R_MIPS_TLS_GOTTPREL:
- case R_MIPS_TLS_TPREL_LO16:
- writeMipsLo16<E>(Loc, Val);
- break;
- case R_MIPS_CALL_HI16:
- case R_MIPS_GOT_HI16:
- case R_MIPS_HI16:
- case R_MIPS_PCHI16:
- case R_MIPS_TLS_DTPREL_HI16:
- case R_MIPS_TLS_TPREL_HI16:
- writeMipsHi16<E>(Loc, Val);
- break;
- case R_MIPS_HIGHER:
- writeMipsHigher<E>(Loc, Val);
- break;
- case R_MIPS_HIGHEST:
- writeMipsHighest<E>(Loc, Val);
- break;
- case R_MIPS_JALR:
- // Ignore this optimization relocation for now
- break;
- case R_MIPS_PC16:
- applyMipsPcReloc<E, 16, 2>(Loc, Type, Val);
- break;
- case R_MIPS_PC19_S2:
- applyMipsPcReloc<E, 19, 2>(Loc, Type, Val);
- break;
- case R_MIPS_PC21_S2:
- applyMipsPcReloc<E, 21, 2>(Loc, Type, Val);
- break;
- case R_MIPS_PC26_S2:
- applyMipsPcReloc<E, 26, 2>(Loc, Type, Val);
- break;
- case R_MIPS_PC32:
- applyMipsPcReloc<E, 32, 0>(Loc, Type, Val);
- break;
- default:
- error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
- }
-}
-
-template <class ELFT>
-bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
- return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST;
-}
-}
-}
diff --git a/ELF/Target.h b/ELF/Target.h
index f4f366219d86..79b03f876d0d 100644
--- a/ELF/Target.h
+++ b/ELF/Target.h
@@ -10,13 +10,13 @@
#ifndef LLD_ELF_TARGET_H
#define LLD_ELF_TARGET_H
+#include "Error.h"
#include "InputSection.h"
-#include "llvm/ADT/StringRef.h"
#include "llvm/Object/ELF.h"
-#include <memory>
-
namespace lld {
+std::string toString(uint32_t RelType);
+
namespace elf {
class InputFile;
class SymbolBody;
@@ -102,14 +102,53 @@ public:
virtual void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
};
+TargetInfo *createAArch64TargetInfo();
+TargetInfo *createAMDGPUTargetInfo();
+TargetInfo *createARMTargetInfo();
+TargetInfo *createAVRTargetInfo();
+TargetInfo *createPPC64TargetInfo();
+TargetInfo *createPPCTargetInfo();
+TargetInfo *createX32TargetInfo();
+TargetInfo *createX86TargetInfo();
+TargetInfo *createX86_64TargetInfo();
+template <class ELFT> TargetInfo *createMipsTargetInfo();
+
+std::string getErrorLocation(const uint8_t *Loc);
+
uint64_t getPPC64TocBase();
uint64_t getAArch64Page(uint64_t Expr);
extern TargetInfo *Target;
TargetInfo *createTarget();
+
+template <unsigned N>
+static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) {
+ if (!llvm::isInt<N>(V))
+ error(getErrorLocation(Loc) + "relocation " + lld::toString(Type) +
+ " out of range");
}
-std::string toString(uint32_t RelType);
+template <unsigned N>
+static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) {
+ if (!llvm::isUInt<N>(V))
+ error(getErrorLocation(Loc) + "relocation " + lld::toString(Type) +
+ " out of range");
+}
+
+template <unsigned N>
+static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) {
+ if (!llvm::isInt<N>(V) && !llvm::isUInt<N>(V))
+ error(getErrorLocation(Loc) + "relocation " + lld::toString(Type) +
+ " out of range");
+}
+
+template <unsigned N>
+static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) {
+ if ((V & (N - 1)) != 0)
+ error(getErrorLocation(Loc) + "improper alignment for relocation " +
+ lld::toString(Type));
+}
+} // namespace elf
}
#endif
diff --git a/ELF/Writer.cpp b/ELF/Writer.cpp
index ad95a8acced4..4ff06388ec78 100644
--- a/ELF/Writer.cpp
+++ b/ELF/Writer.cpp
@@ -73,8 +73,6 @@ private:
std::unique_ptr<FileOutputBuffer> Buffer;
- std::vector<OutputSection *> OutputSections;
- std::vector<OutputSectionCommand *> OutputSectionCommands;
OutputSectionFactory Factory{OutputSections};
void addRelIpltSymbols();
@@ -137,46 +135,6 @@ template <class ELFT> void Writer<ELFT>::removeEmptyPTLoad() {
Phdrs.erase(I, Phdrs.end());
}
-// This function scans over the input sections and creates mergeable
-// synthetic sections. It removes MergeInputSections from array and
-// adds new synthetic ones. Each synthetic section is added to the
-// location of the first input section it replaces.
-static void combineMergableSections() {
- std::vector<MergeSyntheticSection *> MergeSections;
- for (InputSectionBase *&S : InputSections) {
- MergeInputSection *MS = dyn_cast<MergeInputSection>(S);
- if (!MS)
- continue;
-
- // We do not want to handle sections that are not alive, so just remove
- // them instead of trying to merge.
- if (!MS->Live)
- continue;
-
- StringRef OutsecName = getOutputSectionName(MS->Name);
- uint64_t Flags = MS->Flags & ~(uint64_t)SHF_GROUP;
- uint32_t Alignment = std::max<uint32_t>(MS->Alignment, MS->Entsize);
-
- auto I = llvm::find_if(MergeSections, [=](MergeSyntheticSection *Sec) {
- return Sec->Name == OutsecName && Sec->Flags == Flags &&
- Sec->Alignment == Alignment;
- });
- if (I == MergeSections.end()) {
- MergeSyntheticSection *Syn =
- make<MergeSyntheticSection>(OutsecName, MS->Type, Flags, Alignment);
- MergeSections.push_back(Syn);
- I = std::prev(MergeSections.end());
- S = Syn;
- } else {
- S = nullptr;
- }
- (*I)->addSection(MS);
- }
-
- std::vector<InputSectionBase *> &V = InputSections;
- V.erase(std::remove(V.begin(), V.end(), nullptr), V.end());
-}
-
template <class ELFT> static void combineEhFrameSections() {
for (InputSectionBase *&S : InputSections) {
EhInputSection *ES = dyn_cast<EhInputSection>(S);
@@ -192,6 +150,10 @@ template <class ELFT> static void combineEhFrameSections() {
}
template <class ELFT> void Writer<ELFT>::clearOutputSections() {
+ if (Script->Opt.HasSections)
+ Script->createOrphanCommands();
+ else
+ Script->fabricateDefaultCommands();
// Clear the OutputSections to make sure it is not used anymore. Any
// code from this point on should be using the linker script
// commands.
@@ -205,7 +167,6 @@ template <class ELFT> void Writer<ELFT>::run() {
// Create linker-synthesized sections such as .got or .plt.
// Such sections are of type input section.
createSyntheticSections();
- combineMergableSections();
if (!Config->Relocatable)
combineEhFrameSections<ELFT>();
@@ -215,7 +176,6 @@ template <class ELFT> void Writer<ELFT>::run() {
addReservedSymbols();
// Create output sections.
- Script->OutputSections = &OutputSections;
if (Script->Opt.HasSections) {
// If linker script contains SECTIONS commands, let it create sections.
Script->processCommands(Factory);
@@ -256,7 +216,7 @@ template <class ELFT> void Writer<ELFT>::run() {
OutputSectionCommands.begin(), OutputSectionCommands.end(),
[](OutputSectionCommand *Cmd) { Cmd->maybeCompress<ELFT>(); });
- Script->assignAddresses(Phdrs, OutputSectionCommands);
+ Script->assignAddresses(Phdrs);
// Remove empty PT_LOAD to avoid causing the dynamic linker to try to mmap a
// 0 sized region. This has to be done late since only after assignAddresses
@@ -340,9 +300,6 @@ template <class ELFT> void Writer<ELFT>::createSyntheticSections() {
InX::Interp = nullptr;
}
- if (!Config->Relocatable)
- Add(createCommentSection<ELFT>());
-
if (Config->Strip != StripPolicy::All) {
InX::StrTab = make<StringTableSection>(".strtab", false);
InX::SymTab = make<SymbolTableSection<ELFT>>(*InX::StrTab);
@@ -772,8 +729,9 @@ static unsigned getSectionRank(const OutputSection *Sec) {
return Rank;
}
-static bool compareSectionsNonScript(const OutputSection *A,
- const OutputSection *B) {
+static bool compareSections(const BaseCommand *ACmd, const BaseCommand *BCmd) {
+ const OutputSection *A = cast<OutputSectionCommand>(ACmd)->Sec;
+ const OutputSection *B = cast<OutputSectionCommand>(BCmd)->Sec;
if (A->SortRank != B->SortRank)
return A->SortRank < B->SortRank;
if (!(A->SortRank & RF_NOT_ADDR_SET))
@@ -782,19 +740,6 @@ static bool compareSectionsNonScript(const OutputSection *A,
return false;
}
-// Output section ordering is determined by this function.
-static bool compareSections(const OutputSection *A, const OutputSection *B) {
- // For now, put sections mentioned in a linker script
- // first. Sections not on linker script will have a SectionIndex of
- // INT_MAX.
- int AIndex = A->SectionIndex;
- int BIndex = B->SectionIndex;
- if (AIndex != BIndex)
- return AIndex < BIndex;
-
- return compareSectionsNonScript(A, B);
-}
-
void PhdrEntry::add(OutputSection *Sec) {
Last = Sec;
if (!First)
@@ -1004,30 +949,70 @@ template <class ELFT> void Writer<ELFT>::createSections() {
// The more branches in getSectionRank that match, the more similar they are.
// Since each branch corresponds to a bit flag, we can just use
// countLeadingZeros.
-static unsigned getRankProximity(OutputSection *A, OutputSection *B) {
+static int getRankProximity(OutputSection *A, OutputSection *B) {
return countLeadingZeros(A->SortRank ^ B->SortRank);
}
+static int getRankProximity(OutputSection *A, BaseCommand *B) {
+ if (auto *Cmd = dyn_cast<OutputSectionCommand>(B))
+ if (Cmd->Sec)
+ return getRankProximity(A, Cmd->Sec);
+ return -1;
+}
+
+// When placing orphan sections, we want to place them after symbol assignments
+// so that an orphan after
+// begin_foo = .;
+// foo : { *(foo) }
+// end_foo = .;
+// doesn't break the intended meaning of the begin/end symbols.
+// We don't want to go over sections since findOrphanPos is the
+// one in charge of deciding the order of the sections.
+// We don't want to go over changes to '.', since doing so in
+// rx_sec : { *(rx_sec) }
+// . = ALIGN(0x1000);
+// /* The RW PT_LOAD starts here*/
+// rw_sec : { *(rw_sec) }
+// would mean that the RW PT_LOAD would become unaligned.
+static bool shouldSkip(BaseCommand *Cmd) {
+ if (isa<OutputSectionCommand>(Cmd))
+ return false;
+ if (auto *Assign = dyn_cast<SymbolAssignment>(Cmd))
+ return Assign->Name != ".";
+ return true;
+}
+
// We want to place orphan sections so that they share as much
// characteristics with their neighbors as possible. For example, if
// both are rw, or both are tls.
template <typename ELFT>
-static std::vector<OutputSection *>::iterator
-findOrphanPos(std::vector<OutputSection *>::iterator B,
- std::vector<OutputSection *>::iterator E) {
- OutputSection *Sec = *E;
+static std::vector<BaseCommand *>::iterator
+findOrphanPos(std::vector<BaseCommand *>::iterator B,
+ std::vector<BaseCommand *>::iterator E) {
+ OutputSection *Sec = cast<OutputSectionCommand>(*E)->Sec;
// Find the first element that has as close a rank as possible.
- auto I = std::max_element(B, E, [=](OutputSection *A, OutputSection *B) {
+ auto I = std::max_element(B, E, [=](BaseCommand *A, BaseCommand *B) {
return getRankProximity(Sec, A) < getRankProximity(Sec, B);
});
if (I == E)
return E;
// Consider all existing sections with the same proximity.
- unsigned Proximity = getRankProximity(Sec, *I);
- while (I != E && getRankProximity(Sec, *I) == Proximity &&
- Sec->SortRank >= (*I)->SortRank)
+ int Proximity = getRankProximity(Sec, *I);
+ for (; I != E; ++I) {
+ auto *Cmd = dyn_cast<OutputSectionCommand>(*I);
+ if (!Cmd || !Cmd->Sec)
+ continue;
+ if (getRankProximity(Sec, Cmd->Sec) != Proximity ||
+ Sec->SortRank < Cmd->Sec->SortRank)
+ break;
+ }
+ auto J = std::find_if(
+ llvm::make_reverse_iterator(I), llvm::make_reverse_iterator(B),
+ [](BaseCommand *Cmd) { return isa<OutputSectionCommand>(Cmd); });
+ I = J.base();
+ while (I != E && shouldSkip(*I))
++I;
return I;
}
@@ -1041,19 +1026,38 @@ template <class ELFT> void Writer<ELFT>::sortSections() {
if (Script->Opt.HasSections)
Script->adjustSectionsBeforeSorting();
- for (OutputSection *Sec : OutputSections)
- Sec->SortRank = getSectionRank(Sec);
+ for (BaseCommand *Base : Script->Opt.Commands)
+ if (auto *Cmd = dyn_cast<OutputSectionCommand>(Base))
+ if (OutputSection *Sec = Cmd->Sec)
+ Sec->SortRank = getSectionRank(Sec);
if (!Script->Opt.HasSections) {
- std::stable_sort(OutputSections.begin(), OutputSections.end(),
- compareSectionsNonScript);
+ // We know that all the OutputSectionCommands are contiguous in
+ // this case.
+ auto E = Script->Opt.Commands.end();
+ auto I = Script->Opt.Commands.begin();
+ auto IsSection = [](BaseCommand *Base) {
+ return isa<OutputSectionCommand>(Base);
+ };
+ I = std::find_if(I, E, IsSection);
+ E = std::find_if(llvm::make_reverse_iterator(E),
+ llvm::make_reverse_iterator(I), IsSection)
+ .base();
+ std::stable_sort(I, E, compareSections);
return;
}
+ // Orphan sections are sections present in the input files which are
+ // not explicitly placed into the output file by the linker script.
+ //
+ // The sections in the linker script are already in the correct
+ // order. We have to figuere out where to insert the orphan
+ // sections.
+ //
// The order of the sections in the script is arbitrary and may not agree with
- // compareSectionsNonScript. This means that we cannot easily define a
- // strict weak ordering. To see why, consider a comparison of a section in the
- // script and one not in the script. We have a two simple options:
+ // compareSections. This means that we cannot easily define a strict weak
+ // ordering. To see why, consider a comparison of a section in the script and
+ // one not in the script. We have a two simple options:
// * Make them equivalent (a is not less than b, and b is not less than a).
// The problem is then that equivalence has to be transitive and we can
// have sections a, b and c with only b in a script and a less than c
@@ -1068,27 +1072,51 @@ template <class ELFT> void Writer<ELFT>::sortSections() {
// .d (ro) # not in script
//
// The way we define an order then is:
- // * First put script sections at the start and sort the script sections.
- // * Move each non-script section to its preferred position. We try
+ // * Sort only the orphan sections. They are in the end right now.
+ // * Move each orphan section to its preferred position. We try
// to put each section in the last position where it it can share
// a PT_LOAD.
+ //
+ // There is some ambiguity as to where exactly a new entry should be
+ // inserted, because Opt.Commands contains not only output section
+ // commands but also other types of commands such as symbol assignment
+ // expressions. There's no correct answer here due to the lack of the
+ // formal specification of the linker script. We use heuristics to
+ // determine whether a new output command should be added before or
+ // after another commands. For the details, look at shouldSkip
+ // function.
+
+ auto I = Script->Opt.Commands.begin();
+ auto E = Script->Opt.Commands.end();
+ auto NonScriptI = std::find_if(I, E, [](BaseCommand *Base) {
+ if (auto *Cmd = dyn_cast<OutputSectionCommand>(Base))
+ return Cmd->Sec && Cmd->Sec->SectionIndex == INT_MAX;
+ return false;
+ });
+
+ // Sort the orphan sections.
+ std::stable_sort(NonScriptI, E, compareSections);
- std::stable_sort(OutputSections.begin(), OutputSections.end(),
- compareSections);
+ // As a horrible special case, skip the first . assignment if it is before any
+ // section. We do this because it is common to set a load address by starting
+ // the script with ". = 0xabcd" and the expectation is that every section is
+ // after that.
+ auto FirstSectionOrDotAssignment =
+ std::find_if(I, E, [](BaseCommand *Cmd) { return !shouldSkip(Cmd); });
+ if (FirstSectionOrDotAssignment != E &&
+ isa<SymbolAssignment>(**FirstSectionOrDotAssignment))
+ ++FirstSectionOrDotAssignment;
+ I = FirstSectionOrDotAssignment;
- auto I = OutputSections.begin();
- auto E = OutputSections.end();
- auto NonScriptI =
- std::find_if(OutputSections.begin(), E,
- [](OutputSection *S) { return S->SectionIndex == INT_MAX; });
while (NonScriptI != E) {
auto Pos = findOrphanPos<ELFT>(I, NonScriptI);
+ OutputSection *Orphan = cast<OutputSectionCommand>(*NonScriptI)->Sec;
// As an optimization, find all sections with the same sort rank
// and insert them with one rotate.
- unsigned Rank = (*NonScriptI)->SortRank;
- auto End = std::find_if(NonScriptI + 1, E, [=](OutputSection *Sec) {
- return Sec->SortRank != Rank;
+ unsigned Rank = Orphan->SortRank;
+ auto End = std::find_if(NonScriptI + 1, E, [=](BaseCommand *Cmd) {
+ return cast<OutputSectionCommand>(Cmd)->Sec->SortRank != Rank;
});
std::rotate(Pos, NonScriptI, End);
NonScriptI = End;
@@ -1194,25 +1222,27 @@ template <class ELFT> void Writer<ELFT>::finalizeSections() {
addPredefinedSections();
removeUnusedSyntheticSections(OutputSections);
+ clearOutputSections();
sortSections();
+ // Now that we have the final list, create a list of all the
+ // OutputSectionCommands for convenience.
+ for (BaseCommand *Base : Script->Opt.Commands)
+ if (auto *Cmd = dyn_cast<OutputSectionCommand>(Base))
+ OutputSectionCommands.push_back(Cmd);
+
// This is a bit of a hack. A value of 0 means undef, so we set it
// to 1 t make __ehdr_start defined. The section number is not
// particularly relevant.
Out::ElfHeader->SectionIndex = 1;
unsigned I = 1;
- for (OutputSection *Sec : OutputSections) {
+ for (OutputSectionCommand *Cmd : OutputSectionCommands) {
+ OutputSection *Sec = Cmd->Sec;
Sec->SectionIndex = I++;
Sec->ShName = InX::ShStrTab->addString(Sec->Name);
}
- if (!Script->Opt.HasSections)
- Script->fabricateDefaultCommands();
- for (BaseCommand *Base : Script->Opt.Commands)
- if (auto *Cmd = dyn_cast<OutputSectionCommand>(Base))
- OutputSectionCommands.push_back(Cmd);
-
// Binary and relocatable output does not have PHDRS.
// The headers have to be created before finalize as that can influence the
// image base and the dynamic section on mips includes the image base.
@@ -1222,8 +1252,6 @@ template <class ELFT> void Writer<ELFT>::finalizeSections() {
Out::ProgramHeaders->Size = sizeof(Elf_Phdr) * Phdrs.size();
}
- clearOutputSections();
-
// Compute the size of .rela.dyn and .rela.plt early since we need
// them to populate .dynamic.
for (SyntheticSection *SS : {In<ELFT>::RelaDyn, In<ELFT>::RelaPlt})
@@ -1253,9 +1281,12 @@ template <class ELFT> void Writer<ELFT>::finalizeSections() {
// are out of range. This will need to turn into a loop that converges
// when no more Thunks are added
ThunkCreator TC;
- if (TC.createThunks(OutputSectionCommands))
+ if (TC.createThunks(OutputSectionCommands)) {
applySynthetic({InX::MipsGot},
[](SyntheticSection *SS) { SS->updateAllocSize(); });
+ if (TC.createThunks(OutputSectionCommands))
+ fatal("All non-range thunks should be created in first call");
+ }
}
// Fill other section headers. The dynamic table is finalized
@@ -1386,7 +1417,7 @@ template <class ELFT> std::vector<PhdrEntry> Writer<ELFT>::createPhdrs() {
AddHdr(PT_PHDR, PF_R)->add(Out::ProgramHeaders);
// PT_INTERP must be the second entry if exists.
- if (OutputSection *Sec = findSection(".interp"))
+ if (OutputSection *Sec = findSectionInScript(".interp"))
AddHdr(PT_INTERP, Sec->getPhdrFlags())->add(Sec);
// Add the first PT_LOAD segment for regular output sections.
@@ -1397,7 +1428,8 @@ template <class ELFT> std::vector<PhdrEntry> Writer<ELFT>::createPhdrs() {
Load->add(Out::ElfHeader);
Load->add(Out::ProgramHeaders);
- for (OutputSection *Sec : OutputSections) {
+ for (OutputSectionCommand *Cmd : OutputSectionCommands) {
+ OutputSection *Sec = Cmd->Sec;
if (!(Sec->Flags & SHF_ALLOC))
break;
if (!needsPtLoad(Sec))
@@ -1419,9 +1451,11 @@ template <class ELFT> std::vector<PhdrEntry> Writer<ELFT>::createPhdrs() {
// Add a TLS segment if any.
PhdrEntry TlsHdr(PT_TLS, PF_R);
- for (OutputSection *Sec : OutputSections)
+ for (OutputSectionCommand *Cmd : OutputSectionCommands) {
+ OutputSection *Sec = Cmd->Sec;
if (Sec->Flags & SHF_TLS)
TlsHdr.add(Sec);
+ }
if (TlsHdr.First)
Ret.push_back(std::move(TlsHdr));
@@ -1433,9 +1467,11 @@ template <class ELFT> std::vector<PhdrEntry> Writer<ELFT>::createPhdrs() {
// PT_GNU_RELRO includes all sections that should be marked as
// read-only by dynamic linker after proccessing relocations.
PhdrEntry RelRo(PT_GNU_RELRO, PF_R);
- for (OutputSection *Sec : OutputSections)
+ for (OutputSectionCommand *Cmd : OutputSectionCommands) {
+ OutputSection *Sec = Cmd->Sec;
if (needsPtLoad(Sec) && isRelroSection(Sec))
RelRo.add(Sec);
+ }
if (RelRo.First)
Ret.push_back(std::move(RelRo));
@@ -1447,7 +1483,7 @@ template <class ELFT> std::vector<PhdrEntry> Writer<ELFT>::createPhdrs() {
// PT_OPENBSD_RANDOMIZE is an OpenBSD-specific feature. That makes
// the dynamic linker fill the segment with random data.
- if (OutputSection *Sec = findSection(".openbsd.randomdata"))
+ if (OutputSection *Sec = findSectionInScript(".openbsd.randomdata"))
AddHdr(PT_OPENBSD_RANDOMIZE, Sec->getPhdrFlags())->add(Sec);
// PT_GNU_STACK is a special section to tell the loader to make the
@@ -1470,7 +1506,8 @@ template <class ELFT> std::vector<PhdrEntry> Writer<ELFT>::createPhdrs() {
// Create one PT_NOTE per a group of contiguous .note sections.
PhdrEntry *Note = nullptr;
- for (OutputSection *Sec : OutputSections) {
+ for (OutputSectionCommand *Cmd : OutputSectionCommands) {
+ OutputSection *Sec = Cmd->Sec;
if (Sec->Type == SHT_NOTE) {
if (!Note || Script->hasLMA(Sec))
Note = AddHdr(PT_NOTE, PF_R);
@@ -1486,15 +1523,17 @@ template <class ELFT>
void Writer<ELFT>::addPtArmExid(std::vector<PhdrEntry> &Phdrs) {
if (Config->EMachine != EM_ARM)
return;
- auto I = std::find_if(
- OutputSections.begin(), OutputSections.end(),
- [](OutputSection *Sec) { return Sec->Type == SHT_ARM_EXIDX; });
- if (I == OutputSections.end())
+ auto I =
+ std::find_if(OutputSectionCommands.begin(), OutputSectionCommands.end(),
+ [](OutputSectionCommand *Cmd) {
+ return Cmd->Sec->Type == SHT_ARM_EXIDX;
+ });
+ if (I == OutputSectionCommands.end())
return;
// PT_ARM_EXIDX is the ARM EHABI equivalent of PT_GNU_EH_FRAME
PhdrEntry ARMExidx(PT_ARM_EXIDX, PF_R);
- ARMExidx.add(*I);
+ ARMExidx.add((*I)->Sec);
Phdrs.push_back(ARMExidx);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 15:26:51 +0000