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Diffstat (limited to 'contrib/gcc')
258 files changed, 76516 insertions, 727 deletions
diff --git a/contrib/gcc/INSTALL b/contrib/gcc/INSTALL new file mode 100644 index 000000000000..a7c63d57de89 --- /dev/null +++ b/contrib/gcc/INSTALL @@ -0,0 +1,2188 @@ +This is Info file INSTALL, produced by Makeinfo version 1.68 from the +input file install1.texi. + + This file documents the installation of the GNU compiler. Copyright +(C) 1988, 1989, 1992, 1994, 1995 Free Software Foundation, Inc. You +may copy, distribute, and modify it freely as long as you preserve this +copyright notice and permission notice. + + +File: INSTALL, Node: Installation, Up: (dir) + +Installing GNU CC +***************** + + Note most of this information is out of date and superceded by the +EGCS install procedures. It is provided for historical reference only. + +* Menu: + +* Configurations:: Configurations Supported by GNU CC. +* Other Dir:: Compiling in a separate directory (not where the source is). +* Cross-Compiler:: Building and installing a cross-compiler. +* Sun Install:: See below for installation on the Sun. +* VMS Install:: See below for installation on VMS. +* Collect2:: How `collect2' works; how it finds `ld'. +* Header Dirs:: Understanding the standard header file directories. + + Here is the procedure for installing GNU CC on a Unix system. See +*Note VMS Install::, for VMS systems. In this section we assume you +compile in the same directory that contains the source files; see *Note +Other Dir::, to find out how to compile in a separate directory on Unix +systems. + + You cannot install GNU C by itself on MSDOS; it will not compile +under any MSDOS compiler except itself. You need to get the complete +compilation package DJGPP, which includes binaries as well as sources, +and includes all the necessary compilation tools and libraries. + + 1. If you have built GNU CC previously in the same directory for a + different target machine, do `make distclean' to delete all files + that might be invalid. One of the files this deletes is + `Makefile'; if `make distclean' complains that `Makefile' does not + exist, it probably means that the directory is already suitably + clean. + + 2. On a System V release 4 system, make sure `/usr/bin' precedes + `/usr/ucb' in `PATH'. The `cc' command in `/usr/ucb' uses + libraries which have bugs. + + 3. Specify the host, build and target machine configurations. You do + this by running the file `configure'. + + The "build" machine is the system which you are using, the "host" + machine is the system where you want to run the resulting compiler + (normally the build machine), and the "target" machine is the + system for which you want the compiler to generate code. + + If you are building a compiler to produce code for the machine it + runs on (a native compiler), you normally do not need to specify + any operands to `configure'; it will try to guess the type of + machine you are on and use that as the build, host and target + machines. So you don't need to specify a configuration when + building a native compiler unless `configure' cannot figure out + what your configuration is or guesses wrong. + + In those cases, specify the build machine's "configuration name" + with the `--host' option; the host and target will default to be + the same as the host machine. (If you are building a + cross-compiler, see *Note Cross-Compiler::.) + + Here is an example: + + ./configure --host=sparc-sun-sunos4.1 + + A configuration name may be canonical or it may be more or less + abbreviated. + + A canonical configuration name has three parts, separated by + dashes. It looks like this: `CPU-COMPANY-SYSTEM'. (The three + parts may themselves contain dashes; `configure' can figure out + which dashes serve which purpose.) For example, + `m68k-sun-sunos4.1' specifies a Sun 3. + + You can also replace parts of the configuration by nicknames or + aliases. For example, `sun3' stands for `m68k-sun', so + `sun3-sunos4.1' is another way to specify a Sun 3. You can also + use simply `sun3-sunos', since the version of SunOS is assumed by + default to be version 4. + + You can specify a version number after any of the system types, + and some of the CPU types. In most cases, the version is + irrelevant, and will be ignored. So you might as well specify the + version if you know it. + + See *Note Configurations::, for a list of supported configuration + names and notes on many of the configurations. You should check + the notes in that section before proceeding any further with the + installation of GNU CC. + + There are four additional options you can specify independently to + describe variant hardware and software configurations. These are + `--with-gnu-as', `--with-gnu-ld', `--with-stabs' and `--nfp'. + + `--with-gnu-as' + If you will use GNU CC with the GNU assembler (GAS), you + should declare this by using the `--with-gnu-as' option when + you run `configure'. + + Using this option does not install GAS. It only modifies the + output of GNU CC to work with GAS. Building and installing + GAS is up to you. + + Conversely, if you *do not* wish to use GAS and do not specify + `--with-gnu-as' when building GNU CC, it is up to you to make + sure that GAS is not installed. GNU CC searches for a + program named `as' in various directories; if the program it + finds is GAS, then it runs GAS. If you are not sure where + GNU CC finds the assembler it is using, try specifying `-v' + when you run it. + + The systems where it makes a difference whether you use GAS + are + `hppa1.0-ANY-ANY', `hppa1.1-ANY-ANY', `i386-ANY-sysv', + `i386-ANY-isc', + `i860-ANY-bsd', `m68k-bull-sysv', + `m68k-hp-hpux', `m68k-sony-bsd', + `m68k-altos-sysv', `m68000-hp-hpux', + `m68000-att-sysv', `ANY-lynx-lynxos', and `mips-ANY'). On + any other system, `--with-gnu-as' has no effect. + + On the systems listed above (except for the HP-PA, for ISC on + the 386, and for `mips-sgi-irix5.*'), if you use GAS, you + should also use the GNU linker (and specify `--with-gnu-ld'). + + `--with-gnu-ld' + Specify the option `--with-gnu-ld' if you plan to use the GNU + linker with GNU CC. + + This option does not cause the GNU linker to be installed; it + just modifies the behavior of GNU CC to work with the GNU + linker. + + `--with-stabs' + On MIPS based systems and on Alphas, you must specify whether + you want GNU CC to create the normal ECOFF debugging format, + or to use BSD-style stabs passed through the ECOFF symbol + table. The normal ECOFF debug format cannot fully handle + languages other than C. BSD stabs format can handle other + languages, but it only works with the GNU debugger GDB. + + Normally, GNU CC uses the ECOFF debugging format by default; + if you prefer BSD stabs, specify `--with-stabs' when you + configure GNU CC. + + No matter which default you choose when you configure GNU CC, + the user can use the `-gcoff' and `-gstabs+' options to + specify explicitly the debug format for a particular + compilation. + + `--with-stabs' is meaningful on the ISC system on the 386, + also, if `--with-gas' is used. It selects use of stabs + debugging information embedded in COFF output. This kind of + debugging information supports C++ well; ordinary COFF + debugging information does not. + + `--with-stabs' is also meaningful on 386 systems running + SVR4. It selects use of stabs debugging information embedded + in ELF output. The C++ compiler currently (2.6.0) does not + support the DWARF debugging information normally used on 386 + SVR4 platforms; stabs provide a workable alternative. This + requires gas and gdb, as the normal SVR4 tools can not + generate or interpret stabs. + + `--nfp' + On certain systems, you must specify whether the machine has + a floating point unit. These systems include + `m68k-sun-sunosN' and `m68k-isi-bsd'. On any other system, + `--nfp' currently has no effect, though perhaps there are + other systems where it could usefully make a difference. + + `--enable-haifa' + `--disable-haifa' + Use `--enable-haifa' to enable use of an experimental + instruction scheduler (from IBM Haifa). This may or may not + produce better code. Some targets on which it is known to be + a win enable it by default; use `--disable-haifa' to disable + it in these cases. `configure' will print out whether the + Haifa scheduler is enabled when it is run. + + `--enable-threads=TYPE' + Certain systems, notably Linux-based GNU systems, can't be + relied on to supply a threads facility for the Objective C + runtime and so will default to single-threaded runtime. They + may, however, have a library threads implementation + available, in which case threads can be enabled with this + option by supplying a suitable TYPE, probably `posix'. The + possibilities for TYPE are `single', `posix', `win32', + `solaris', `irix' and `mach'. + + `--enable-checking' + When you specify this option, the compiler is built to + perform checking of tree node types when referencing fields + of that node. This does not change the generated code, but + adds error checking within the compiler. This will slow down + the compiler and may only work properly if you are building + the compiler with GNU C. + + The `configure' script searches subdirectories of the source + directory for other compilers that are to be integrated into GNU + CC. The GNU compiler for C++, called G++ is in a subdirectory + named `cp'. `configure' inserts rules into `Makefile' to build + all of those compilers. + + Here we spell out what files will be set up by `configure'. + Normally you need not be concerned with these files. + + * A file named `config.h' is created that contains a `#include' + of the top-level config file for the machine you will run the + compiler on (*note The Configuration File: + (gcc.info)Config.). This file is responsible for defining + information about the host machine. It includes `tm.h'. + + The top-level config file is located in the subdirectory + `config'. Its name is always `xm-SOMETHING.h'; usually + `xm-MACHINE.h', but there are some exceptions. + + If your system does not support symbolic links, you might + want to set up `config.h' to contain a `#include' command + which refers to the appropriate file. + + * A file named `tconfig.h' is created which includes the + top-level config file for your target machine. This is used + for compiling certain programs to run on that machine. + + * A file named `tm.h' is created which includes the + machine-description macro file for your target machine. It + should be in the subdirectory `config' and its name is often + `MACHINE.h'. + + * The command file `configure' also constructs the file + `Makefile' by adding some text to the template file + `Makefile.in'. The additional text comes from files in the + `config' directory, named `t-TARGET' and `x-HOST'. If these + files do not exist, it means nothing needs to be added for a + given target or host. + + 4. The standard directory for installing GNU CC is `/usr/local/lib'. + If you want to install its files somewhere else, specify + `--prefix=DIR' when you run `configure'. Here DIR is a directory + name to use instead of `/usr/local' for all purposes with one + exception: the directory `/usr/local/include' is searched for + header files no matter where you install the compiler. To override + this name, use the `--with-local-prefix' option below. The + directory you specify need not exist, but its parent directory + must exist. + + 5. Specify `--with-local-prefix=DIR' if you want the compiler to + search directory `DIR/include' for locally installed header files + *instead* of `/usr/local/include'. + + You should specify `--with-local-prefix' *only* if your site has a + different convention (not `/usr/local') for where to put + site-specific files. + + The default value for `--with-local-prefix' is `/usr/local' + regardless of the value of `--prefix'. Specifying `--prefix' has + no effect on which directory GNU CC searches for local header + files. This may seem counterintuitive, but actually it is logical. + + The purpose of `--prefix' is to specify where to *install GNU CC*. + The local header files in `/usr/local/include'--if you put any in + that directory--are not part of GNU CC. They are part of other + programs--perhaps many others. (GNU CC installs its own header + files in another directory which is based on the `--prefix' value.) + + *Do not* specify `/usr' as the `--with-local-prefix'! The + directory you use for `--with-local-prefix' *must not* contain any + of the system's standard header files. If it did contain them, + certain programs would be miscompiled (including GNU Emacs, on + certain targets), because this would override and nullify the + header file corrections made by the `fixincludes' script. + + Indications are that people who use this option use it based on + mistaken ideas of what it is for. People use it as if it specified + where to install part of GNU CC. Perhaps they make this assumption + because installing GNU CC creates the directory. + + 6. Make sure the Bison parser generator is installed. (This is + unnecessary if the Bison output files `c-parse.c' and `cexp.c' are + more recent than `c-parse.y' and `cexp.y' and you do not plan to + change the `.y' files.) + + Bison versions older than Sept 8, 1988 will produce incorrect + output for `c-parse.c'. + + 7. If you have chosen a configuration for GNU CC which requires other + GNU tools (such as GAS or the GNU linker) instead of the standard + system tools, install the required tools in the build directory + under the names `as', `ld' or whatever is appropriate. This will + enable the compiler to find the proper tools for compilation of + the program `enquire'. + + Alternatively, you can do subsequent compilation using a value of + the `PATH' environment variable such that the necessary GNU tools + come before the standard system tools. + + 8. Build the compiler. Just type `make LANGUAGES=c' in the compiler + directory. + + `LANGUAGES=c' specifies that only the C compiler should be + compiled. The makefile normally builds compilers for all the + supported languages; currently, C, C++ and Objective C. However, + C is the only language that is sure to work when you build with + other non-GNU C compilers. In addition, building anything but C + at this stage is a waste of time. + + In general, you can specify the languages to build by typing the + argument `LANGUAGES="LIST"', where LIST is one or more words from + the list `c', `c++', and `objective-c'. If you have any + additional GNU compilers as subdirectories of the GNU CC source + directory, you may also specify their names in this list. + + Ignore any warnings you may see about "statement not reached" in + `insn-emit.c'; they are normal. Also, warnings about "unknown + escape sequence" are normal in `genopinit.c' and perhaps some + other files. Likewise, you should ignore warnings about "constant + is so large that it is unsigned" in `insn-emit.c' and + `insn-recog.c', a warning about a comparison always being zero in + `enquire.o', and warnings about shift counts exceeding type widths + in `cexp.y'. Any other compilation errors may represent bugs in + the port to your machine or operating system, and should be + investigated and reported. + + Some commercial compilers fail to compile GNU CC because they have + bugs or limitations. For example, the Microsoft compiler is said + to run out of macro space. Some Ultrix compilers run out of + expression space; then you need to break up the statement where + the problem happens. + + 9. If you are building a cross-compiler, stop here. *Note + Cross-Compiler::. + + 10. Move the first-stage object files and executables into a + subdirectory with this command: + + make stage1 + + The files are moved into a subdirectory named `stage1'. Once + installation is complete, you may wish to delete these files with + `rm -r stage1'. + + 11. If you have chosen a configuration for GNU CC which requires other + GNU tools (such as GAS or the GNU linker) instead of the standard + system tools, install the required tools in the `stage1' + subdirectory under the names `as', `ld' or whatever is + appropriate. This will enable the stage 1 compiler to find the + proper tools in the following stage. + + Alternatively, you can do subsequent compilation using a value of + the `PATH' environment variable such that the necessary GNU tools + come before the standard system tools. + + 12. Recompile the compiler with itself, with this command: + + make CC="stage1/xgcc -Bstage1/" CFLAGS="-g -O2" + + This is called making the stage 2 compiler. + + The command shown above builds compilers for all the supported + languages. If you don't want them all, you can specify the + languages to build by typing the argument `LANGUAGES="LIST"'. LIST + should contain one or more words from the list `c', `c++', + `objective-c', and `proto'. Separate the words with spaces. + `proto' stands for the programs `protoize' and `unprotoize'; they + are not a separate language, but you use `LANGUAGES' to enable or + disable their installation. + + If you are going to build the stage 3 compiler, then you might + want to build only the C language in stage 2. + + Once you have built the stage 2 compiler, if you are short of disk + space, you can delete the subdirectory `stage1'. + + On a 68000 or 68020 system lacking floating point hardware, unless + you have selected a `tm.h' file that expects by default that there + is no such hardware, do this instead: + + make CC="stage1/xgcc -Bstage1/" CFLAGS="-g -O2 -msoft-float" + + 13. If you wish to test the compiler by compiling it with itself one + more time, install any other necessary GNU tools (such as GAS or + the GNU linker) in the `stage2' subdirectory as you did in the + `stage1' subdirectory, then do this: + + make stage2 + make CC="stage2/xgcc -Bstage2/" CFLAGS="-g -O2" + + This is called making the stage 3 compiler. Aside from the `-B' + option, the compiler options should be the same as when you made + the stage 2 compiler. But the `LANGUAGES' option need not be the + same. The command shown above builds compilers for all the + supported languages; if you don't want them all, you can specify + the languages to build by typing the argument `LANGUAGES="LIST"', + as described above. + + If you do not have to install any additional GNU tools, you may + use the command + + make bootstrap LANGUAGES=LANGUAGE-LIST BOOT_CFLAGS=OPTION-LIST + + instead of making `stage1', `stage2', and performing the two + compiler builds. + + 14. Then compare the latest object files with the stage 2 object + files--they ought to be identical, aside from time stamps (if any). + + On some systems, meaningful comparison of object files is + impossible; they always appear "different." This is currently + true on Solaris and some systems that use ELF object file format. + On some versions of Irix on SGI machines and DEC Unix (OSF/1) on + Alpha systems, you will not be able to compare the files without + specifying `-save-temps'; see the description of individual + systems above to see if you get comparison failures. You may have + similar problems on other systems. + + Use this command to compare the files: + + make compare + + This will mention any object files that differ between stage 2 and + stage 3. Any difference, no matter how innocuous, indicates that + the stage 2 compiler has compiled GNU CC incorrectly, and is + therefore a potentially serious bug which you should investigate + and report. + + If your system does not put time stamps in the object files, then + this is a faster way to compare them (using the Bourne shell): + + for file in *.o; do + cmp $file stage2/$file + done + + If you have built the compiler with the `-mno-mips-tfile' option on + MIPS machines, you will not be able to compare the files. + + 15. Install the compiler driver, the compiler's passes and run-time + support with `make install'. Use the same value for `CC', + `CFLAGS' and `LANGUAGES' that you used when compiling the files + that are being installed. One reason this is necessary is that + some versions of Make have bugs and recompile files gratuitously + when you do this step. If you use the same variable values, those + files will be recompiled properly. + + For example, if you have built the stage 2 compiler, you can use + the following command: + + make install CC="stage2/xgcc -Bstage2/" CFLAGS="-g -O" LANGUAGES="LIST" + + This copies the files `cc1', `cpp' and `libgcc.a' to files `cc1', + `cpp' and `libgcc.a' in the directory + `/usr/local/lib/gcc-lib/TARGET/VERSION', which is where the + compiler driver program looks for them. Here TARGET is the + canonicalized form of target machine type specified when you ran + `configure', and VERSION is the version number of GNU CC. This + naming scheme permits various versions and/or cross-compilers to + coexist. It also copies the executables for compilers for other + languages (e.g., `cc1plus' for C++) to the same directory. + + This also copies the driver program `xgcc' into + `/usr/local/bin/gcc', so that it appears in typical execution + search paths. It also copies `gcc.1' into `/usr/local/man/man1' + and info pages into `/usr/local/info'. + + On some systems, this command causes recompilation of some files. + This is usually due to bugs in `make'. You should either ignore + this problem, or use GNU Make. + + *Warning: there is a bug in `alloca' in the Sun library. To avoid + this bug, be sure to install the executables of GNU CC that were + compiled by GNU CC. (That is, the executables from stage 2 or 3, + not stage 1.) They use `alloca' as a built-in function and never + the one in the library.* + + (It is usually better to install GNU CC executables from stage 2 + or 3, since they usually run faster than the ones compiled with + some other compiler.) + + 16. If you're going to use C++, it's likely that you need to also + install a C++ runtime library. Just as GNU C does not distribute + a C runtime library, it also does not include a C++ runtime + library. All I/O functionality, special class libraries, etc., are + provided by the C++ runtime library. + + The standard C++ runtime library for GNU CC is called `libstdc++'. + An obsolescent library `libg++' may also be available, but it's + necessary only for older software that hasn't been converted yet; + if you don't know whether you need `libg++' then you probably don't + need it. + + Here's one way to build and install `libstdc++' for GNU CC: + + * Build and install GNU CC, so that invoking `gcc' obtains the + GNU CC that was just built. + + * Obtain a copy of a compatible `libstdc++' distribution. For + example, the `libstdc++-2.8.0.tar.gz' distribution should be + compatible with GCC 2.8.0. GCC distributors normally + distribute `libstdc++' as well. + + * Set the `CXX' environment variable to `gcc' while running the + `libstdc++' distribution's `configure' command. Use the same + `configure' options that you used when you invoked GCC's + `configure' command. + + * Invoke `make' to build the C++ runtime. + + * Invoke `make install' to install the C++ runtime. + + To summarize, after building and installing GNU CC, invoke the + following shell commands in the topmost directory of the C++ + library distribution. For CONFIGURE-OPTIONS, use the same options + that you used to configure GNU CC. + + $ CXX=gcc ./configure CONFIGURE-OPTIONS + $ make + $ make install + + 17. GNU CC includes a runtime library for Objective-C because it is an + integral part of the language. You can find the files associated + with the library in the subdirectory `objc'. The GNU Objective-C + Runtime Library requires header files for the target's C library in + order to be compiled,and also requires the header files for the + target's thread library if you want thread support. *Note + Cross-Compilers and Header Files: Cross Headers, for discussion + about header files issues for cross-compilation. + + When you run `configure', it picks the appropriate Objective-C + thread implementation file for the target platform. In some + situations, you may wish to choose a different back-end as some + platforms support multiple thread implementations or you may wish + to disable thread support completely. You do this by specifying a + value for the OBJC_THREAD_FILE makefile variable on the command + line when you run make, for example: + + make CC="stage2/xgcc -Bstage2/" CFLAGS="-g -O2" OBJC_THREAD_FILE=thr-single + + Below is a list of the currently available back-ends. + + * thr-single Disable thread support, should work for all + platforms. + + * thr-decosf1 DEC OSF/1 thread support. + + * thr-irix SGI IRIX thread support. + + * thr-mach Generic MACH thread support, known to work on + NEXTSTEP. + + * thr-os2 IBM OS/2 thread support. + + * thr-posix Generix POSIX thread support. + + * thr-pthreads PCThreads on Linux-based GNU systems. + + * thr-solaris SUN Solaris thread support. + + * thr-win32 Microsoft Win32 API thread support. + + +File: INSTALL, Node: Configurations, Next: Other Dir, Up: Installation + +Configurations Supported by GNU CC +================================== + + Here are the possible CPU types: + + 1750a, a29k, alpha, arm, cN, clipper, dsp16xx, elxsi, h8300, + hppa1.0, hppa1.1, i370, i386, i486, i586, i860, i960, m32r, + m68000, m68k, m88k, mips, mipsel, mips64, mips64el, ns32k, + powerpc, powerpcle, pyramid, romp, rs6000, sh, sparc, sparclite, + sparc64, vax, we32k. + + Here are the recognized company names. As you can see, customary +abbreviations are used rather than the longer official names. + + acorn, alliant, altos, apollo, apple, att, bull, cbm, convergent, + convex, crds, dec, dg, dolphin, elxsi, encore, harris, hitachi, + hp, ibm, intergraph, isi, mips, motorola, ncr, next, ns, omron, + plexus, sequent, sgi, sony, sun, tti, unicom, wrs. + + The company name is meaningful only to disambiguate when the rest of +the information supplied is insufficient. You can omit it, writing +just `CPU-SYSTEM', if it is not needed. For example, `vax-ultrix4.2' +is equivalent to `vax-dec-ultrix4.2'. + + Here is a list of system types: + + 386bsd, aix, acis, amigaos, aos, aout, aux, bosx, bsd, clix, coff, + ctix, cxux, dgux, dynix, ebmon, ecoff, elf, esix, freebsd, hms, + genix, gnu, linux-gnu, hiux, hpux, iris, irix, isc, luna, lynxos, + mach, minix, msdos, mvs, netbsd, newsos, nindy, ns, osf, osfrose, + ptx, riscix, riscos, rtu, sco, sim, solaris, sunos, sym, sysv, + udi, ultrix, unicos, uniplus, unos, vms, vsta, vxworks, winnt, + xenix. + +You can omit the system type; then `configure' guesses the operating +system from the CPU and company. + + You can add a version number to the system type; this may or may not +make a difference. For example, you can write `bsd4.3' or `bsd4.4' to +distinguish versions of BSD. In practice, the version number is most +needed for `sysv3' and `sysv4', which are often treated differently. + + If you specify an impossible combination such as `i860-dg-vms', then +you may get an error message from `configure', or it may ignore part of +the information and do the best it can with the rest. `configure' +always prints the canonical name for the alternative that it used. GNU +CC does not support all possible alternatives. + + Often a particular model of machine has a name. Many machine names +are recognized as aliases for CPU/company combinations. Thus, the +machine name `sun3', mentioned above, is an alias for `m68k-sun'. +Sometimes we accept a company name as a machine name, when the name is +popularly used for a particular machine. Here is a table of the known +machine names: + + 3300, 3b1, 3bN, 7300, altos3068, altos, apollo68, att-7300, + balance, convex-cN, crds, decstation-3100, decstation, delta, + encore, fx2800, gmicro, hp7NN, hp8NN, hp9k2NN, hp9k3NN, hp9k7NN, + hp9k8NN, iris4d, iris, isi68, m3230, magnum, merlin, miniframe, + mmax, news-3600, news800, news, next, pbd, pc532, pmax, powerpc, + powerpcle, ps2, risc-news, rtpc, sun2, sun386i, sun386, sun3, + sun4, symmetry, tower-32, tower. + +Remember that a machine name specifies both the cpu type and the company +name. If you want to install your own homemade configuration files, +you can use `local' as the company name to access them. If you use +configuration `CPU-local', the configuration name without the cpu prefix +is used to form the configuration file names. + + Thus, if you specify `m68k-local', configuration uses files +`m68k.md', `local.h', `m68k.c', `xm-local.h', `t-local', and `x-local', +all in the directory `config/m68k'. + + Here is a list of configurations that have special treatment or +special things you must know: + +`1750a-*-*' + MIL-STD-1750A processors. + + The MIL-STD-1750A cross configuration produces output for + `as1750', an assembler/linker available under the GNU Public + License for the 1750A. `as1750' can be obtained at + *ftp://ftp.fta-berlin.de/pub/crossgcc/1750gals/*. A similarly + licensed simulator for the 1750A is available from same address. + + You should ignore a fatal error during the building of libgcc + (libgcc is not yet implemented for the 1750A.) + + The `as1750' assembler requires the file `ms1750.inc', which is + found in the directory `config/1750a'. + + GNU CC produced the same sections as the Fairchild F9450 C + Compiler, namely: + + `Normal' + The program code section. + + `Static' + The read/write (RAM) data section. + + `Konst' + The read-only (ROM) constants section. + + `Init' + Initialization section (code to copy KREL to SREL). + + The smallest addressable unit is 16 bits (BITS_PER_UNIT is 16). + This means that type `char' is represented with a 16-bit word per + character. The 1750A's "Load/Store Upper/Lower Byte" instructions + are not used by GNU CC. + +`alpha-*-osf1' + Systems using processors that implement the DEC Alpha architecture + and are running the DEC Unix (OSF/1) operating system, for example + the DEC Alpha AXP systems.CC.) + + GNU CC writes a `.verstamp' directive to the assembler output file + unless it is built as a cross-compiler. It gets the version to + use from the system header file `/usr/include/stamp.h'. If you + install a new version of DEC Unix, you should rebuild GCC to pick + up the new version stamp. + + Note that since the Alpha is a 64-bit architecture, + cross-compilers from 32-bit machines will not generate code as + efficient as that generated when the compiler is running on a + 64-bit machine because many optimizations that depend on being + able to represent a word on the target in an integral value on the + host cannot be performed. Building cross-compilers on the Alpha + for 32-bit machines has only been tested in a few cases and may + not work properly. + + `make compare' may fail on old versions of DEC Unix unless you add + `-save-temps' to `CFLAGS'. On these systems, the name of the + assembler input file is stored in the object file, and that makes + comparison fail if it differs between the `stage1' and `stage2' + compilations. The option `-save-temps' forces a fixed name to be + used for the assembler input file, instead of a randomly chosen + name in `/tmp'. Do not add `-save-temps' unless the comparisons + fail without that option. If you add `-save-temps', you will have + to manually delete the `.i' and `.s' files after each series of + compilations. + + GNU CC now supports both the native (ECOFF) debugging format used + by DBX and GDB and an encapsulated STABS format for use only with + GDB. See the discussion of the `--with-stabs' option of + `configure' above for more information on these formats and how to + select them. + + There is a bug in DEC's assembler that produces incorrect line + numbers for ECOFF format when the `.align' directive is used. To + work around this problem, GNU CC will not emit such alignment + directives while writing ECOFF format debugging information even + if optimization is being performed. Unfortunately, this has the + very undesirable side-effect that code addresses when `-O' is + specified are different depending on whether or not `-g' is also + specified. + + To avoid this behavior, specify `-gstabs+' and use GDB instead of + DBX. DEC is now aware of this problem with the assembler and + hopes to provide a fix shortly. + +`arc-*-elf' + Argonaut ARC processor. This configuration is intended for + embedded systems. + +`arm-*-aout' + Advanced RISC Machines ARM-family processors. These are often + used in embedded applications. There are no standard Unix + configurations. This configuration corresponds to the basic + instruction sequences and will produce `a.out' format object + modules. + + You may need to make a variant of the file `arm.h' for your + particular configuration. + +`arm-*-linuxaout' + Any of the ARM family processors running the Linux-based GNU + system with the `a.out' binary format (ELF is not yet supported). + You must use version 2.8.1.0.7 or later of the GNU/Linux binutils, + which you can download from `sunsite.unc.edu:/pub/Linux/GCC' and + other mirror sites for Linux-based GNU systems. + +`arm-*-riscix' + The ARM2 or ARM3 processor running RISC iX, Acorn's port of BSD + Unix. If you are running a version of RISC iX prior to 1.2 then + you must specify the version number during configuration. Note + that the assembler shipped with RISC iX does not support stabs + debugging information; a new version of the assembler, with stabs + support included, is now available from Acorn and via ftp + `ftp.acorn.com:/pub/riscix/as+xterm.tar.Z'. To enable stabs + debugging, pass `--with-gnu-as' to configure. + + You will need to install GNU `sed' before you can run configure. + +`a29k' + AMD Am29k-family processors. These are normally used in embedded + applications. There are no standard Unix configurations. This + configuration corresponds to AMD's standard calling sequence and + binary interface and is compatible with other 29k tools. + + You may need to make a variant of the file `a29k.h' for your + particular configuration. + +`a29k-*-bsd' + AMD Am29050 used in a system running a variant of BSD Unix. + +`decstation-*' + MIPS-based DECstations can support three different personalities: + Ultrix, DEC OSF/1, and OSF/rose. (Alpha-based DECstation products + have a configuration name beginning with `alpha-dec'.) To + configure GCC for these platforms use the following configurations: + + `decstation-ultrix' + Ultrix configuration. + + `decstation-osf1' + Dec's version of OSF/1. + + `decstation-osfrose' + Open Software Foundation reference port of OSF/1 which uses + the OSF/rose object file format instead of ECOFF. Normally, + you would not select this configuration. + + The MIPS C compiler needs to be told to increase its table size + for switch statements with the `-Wf,-XNg1500' option in order to + compile `cp/parse.c'. If you use the `-O2' optimization option, + you also need to use `-Olimit 3000'. Both of these options are + automatically generated in the `Makefile' that the shell script + `configure' builds. If you override the `CC' make variable and + use the MIPS compilers, you may need to add `-Wf,-XNg1500 -Olimit + 3000'. + +`elxsi-elxsi-bsd' + The Elxsi's C compiler has known limitations that prevent it from + compiling GNU C. Please contact `mrs@cygnus.com' for more details. + +`dsp16xx' + A port to the AT&T DSP1610 family of processors. + +`h8300-*-*' + Hitachi H8/300 series of processors. + + The calling convention and structure layout has changed in release + 2.6. All code must be recompiled. The calling convention now + passes the first three arguments in function calls in registers. + Structures are no longer a multiple of 2 bytes. + +`hppa*-*-*' + There are several variants of the HP-PA processor which run a + variety of operating systems. GNU CC must be configured to use + the correct processor type and operating system, or GNU CC will + not function correctly. The easiest way to handle this problem is + to *not* specify a target when configuring GNU CC, the `configure' + script will try to automatically determine the right processor + type and operating system. + + `-g' does not work on HP-UX, since that system uses a peculiar + debugging format which GNU CC does not know about. However, `-g' + will work if you also use GAS and GDB in conjunction with GCC. We + highly recommend using GAS for all HP-PA configurations. + + You should be using GAS-2.6 (or later) along with GDB-4.16 (or + later). These can be retrieved from all the traditional GNU ftp + archive sites. + + On some versions of HP-UX, you will need to install GNU `sed'. + + You will need to be install GAS into a directory before `/bin', + `/usr/bin', and `/usr/ccs/bin' in your search path. You should + install GAS before you build GNU CC. + + To enable debugging, you must configure GNU CC with the + `--with-gnu-as' option before building. + +`i370-*-*' + This port is very preliminary and has many known bugs. We hope to + have a higher-quality port for this machine soon. + +`i386-*-linux-gnuoldld' + Use this configuration to generate `a.out' binaries on Linux-based + GNU systems if you do not have gas/binutils version 2.5.2 or later + installed. This is an obsolete configuration. + +`i386-*-linux-gnuaout' + Use this configuration to generate `a.out' binaries on Linux-based + GNU systems. This configuration is being superseded. You must use + gas/binutils version 2.5.2 or later. + +`i386-*-linux-gnu' + Use this configuration to generate ELF binaries on Linux-based GNU + systems. You must use gas/binutils version 2.5.2 or later. + +`i386-*-sco' + Compilation with RCC is recommended. Also, it may be a good idea + to link with GNU malloc instead of the malloc that comes with the + system. + +`i386-*-sco3.2v4' + Use this configuration for SCO release 3.2 version 4. + +`i386-*-sco3.2v5*' + Use this for the SCO OpenServer Release family including 5.0.0, + 5.0.2, 5.0.4, 5.0.5, Internet FastStart 1.0, and Internet + FastStart 1.1. + + GNU CC can generate COFF binaries if you specify `-mcoff' or ELF + binaries, the default. A full `make bootstrap' is recommended + so that an ELF compiler that builds ELF is generated. + + You must have TLS597 from `ftp://ftp.sco.com/TLS' installed for ELF + C++ binaries to work correctly on releases before 5.0.4. + + The native SCO assembler that is provided with the OS at no charge + is normally required. If, however, you must be able to use the GNU + assembler (perhaps you have complex asms) you must configure this + package `--with-gnu-as'. To do this, install (cp or symlink) + gcc/as to your copy of the GNU assembler. You must use a recent + version of GNU binutils; version 2.9.1 seems to work well. If you + select this option, you will be unable to build COFF images. + Trying to do so will result in non-obvious failures. In general, + the "-with-gnu-as" option isn't as well tested as the native + assembler. + + *NOTE:* If you are building C++, you must follow the instructions + about invoking `make bootstrap' because the native OpenServer + compiler may build a `cc1plus' that will not correctly parse many + valid C++ programs. You must do a `make bootstrap' if you are + building with the native compiler. + +`i386-*-isc' + It may be a good idea to link with GNU malloc instead of the + malloc that comes with the system. + + In ISC version 4.1, `sed' core dumps when building `deduced.h'. + Use the version of `sed' from version 4.0. + +`i386-*-esix' + It may be good idea to link with GNU malloc instead of the malloc + that comes with the system. + +`i386-ibm-aix' + You need to use GAS version 2.1 or later, and LD from GNU binutils + version 2.2 or later. + +`i386-sequent-bsd' + Go to the Berkeley universe before compiling. + +`i386-sequent-ptx1*' +`i386-sequent-ptx2*' + You must install GNU `sed' before running `configure'. + +`i386-sun-sunos4' + You may find that you need another version of GNU CC to begin + bootstrapping with, since the current version when built with the + system's own compiler seems to get an infinite loop compiling part + of `libgcc2.c'. GNU CC version 2 compiled with GNU CC (any + version) seems not to have this problem. + + See *Note Sun Install::, for information on installing GNU CC on + Sun systems. + +`i[345]86-*-winnt3.5' + This version requires a GAS that has not yet been released. Until + it is, you can get a prebuilt binary version via anonymous ftp from + `cs.washington.edu:pub/gnat' or `cs.nyu.edu:pub/gnat'. You must + also use the Microsoft header files from the Windows NT 3.5 SDK. + Find these on the CDROM in the `/mstools/h' directory dated + 9/4/94. You must use a fixed version of Microsoft linker made + especially for NT 3.5, which is also is available on the NT 3.5 + SDK CDROM. If you do not have this linker, can you also use the + linker from Visual C/C++ 1.0 or 2.0. + + Installing GNU CC for NT builds a wrapper linker, called `ld.exe', + which mimics the behaviour of Unix `ld' in the specification of + libraries (`-L' and `-l'). `ld.exe' looks for both Unix and + Microsoft named libraries. For example, if you specify `-lfoo', + `ld.exe' will look first for `libfoo.a' and then for `foo.lib'. + + You may install GNU CC for Windows NT in one of two ways, + depending on whether or not you have a Unix-like shell and various + Unix-like utilities. + + 1. If you do not have a Unix-like shell and few Unix-like + utilities, you will use a DOS style batch script called + `configure.bat'. Invoke it as `configure winnt' from an + MSDOS console window or from the program manager dialog box. + `configure.bat' assumes you have already installed and have + in your path a Unix-like `sed' program which is used to + create a working `Makefile' from `Makefile.in'. + + `Makefile' uses the Microsoft Nmake program maintenance + utility and the Visual C/C++ V8.00 compiler to build GNU CC. + You need only have the utilities `sed' and `touch' to use + this installation method, which only automatically builds the + compiler itself. You must then examine what `fixinc.winnt' + does, edit the header files by hand and build `libgcc.a' + manually. + + 2. The second type of installation assumes you are running a + Unix-like shell, have a complete suite of Unix-like utilities + in your path, and have a previous version of GNU CC already + installed, either through building it via the above + installation method or acquiring a pre-built binary. In this + case, use the `configure' script in the normal fashion. + +`i860-intel-osf1' + This is the Paragon. If you have version 1.0 of the operating + system, you need to take special steps to build GNU CC due to + peculiarities of the system. Newer system versions have no + problem. See the section `Installation Problems' in the GNU CC + Manual. + +`*-lynx-lynxos' + LynxOS 2.2 and earlier comes with GNU CC 1.x already installed as + `/bin/gcc'. You should compile with this instead of `/bin/cc'. + You can tell GNU CC to use the GNU assembler and linker, by + specifying `--with-gnu-as --with-gnu-ld' when configuring. These + will produce COFF format object files and executables; otherwise + GNU CC will use the installed tools, which produce `a.out' format + executables. + +`m32r-*-elf' + Mitsubishi M32R processor. This configuration is intended for + embedded systems. + +`m68000-hp-bsd' + HP 9000 series 200 running BSD. Note that the C compiler that + comes with this system cannot compile GNU CC; contact + `law@cygnus.com' to get binaries of GNU CC for bootstrapping. + +`m68k-altos' + Altos 3068. You must use the GNU assembler, linker and debugger. + Also, you must fix a kernel bug. Details in the file + `README.ALTOS'. + +`m68k-apple-aux' + Apple Macintosh running A/UX. You may configure GCC to use + either the system assembler and linker or the GNU assembler and + linker. You should use the GNU configuration if you can, + especially if you also want to use GNU C++. You enabled that + configuration with + the `--with-gnu-as' and `--with-gnu-ld' + options to `configure'. + + Note the C compiler that comes with this system cannot compile GNU + CC. You can find binaries of GNU CC for bootstrapping on + `jagubox.gsfc.nasa.gov'. You will also a patched version of + `/bin/ld' there that raises some of the arbitrary limits found in + the original. + +`m68k-att-sysv' + AT&T 3b1, a.k.a. 7300 PC. Special procedures are needed to + compile GNU CC with this machine's standard C compiler, due to + bugs in that compiler. You can bootstrap it more easily with + previous versions of GNU CC if you have them. + + Installing GNU CC on the 3b1 is difficult if you do not already + have GNU CC running, due to bugs in the installed C compiler. + However, the following procedure might work. We are unable to + test it. + + 1. Comment out the `#include "config.h"' line near the start of + `cccp.c' and do `make cpp'. This makes a preliminary version + of GNU cpp. + + 2. Save the old `/lib/cpp' and copy the preliminary GNU cpp to + that file name. + + 3. Undo your change in `cccp.c', or reinstall the original + version, and do `make cpp' again. + + 4. Copy this final version of GNU cpp into `/lib/cpp'. + + 5. Replace every occurrence of `obstack_free' in the file + `tree.c' with `_obstack_free'. + + 6. Run `make' to get the first-stage GNU CC. + + 7. Reinstall the original version of `/lib/cpp'. + + 8. Now you can compile GNU CC with itself and install it in the + normal fashion. + +`m68k-bull-sysv' + Bull DPX/2 series 200 and 300 with BOS-2.00.45 up to BOS-2.01. GNU + CC works either with native assembler or GNU assembler. You can use + GNU assembler with native coff generation by providing + `--with-gnu-as' to the configure script or use GNU assembler with + dbx-in-coff encapsulation by providing `--with-gnu-as --stabs'. + For any problem with native assembler or for availability of the + DPX/2 port of GAS, contact `F.Pierresteguy@frcl.bull.fr'. + +`m68k-crds-unox' + Use `configure unos' for building on Unos. + + The Unos assembler is named `casm' instead of `as'. For some + strange reason linking `/bin/as' to `/bin/casm' changes the + behavior, and does not work. So, when installing GNU CC, you + should install the following script as `as' in the subdirectory + where the passes of GCC are installed: + + #!/bin/sh + casm $* + + The default Unos library is named `libunos.a' instead of `libc.a'. + To allow GNU CC to function, either change all references to + `-lc' in `gcc.c' to `-lunos' or link `/lib/libc.a' to + `/lib/libunos.a'. + + When compiling GNU CC with the standard compiler, to overcome bugs + in the support of `alloca', do not use `-O' when making stage 2. + Then use the stage 2 compiler with `-O' to make the stage 3 + compiler. This compiler will have the same characteristics as the + usual stage 2 compiler on other systems. Use it to make a stage 4 + compiler and compare that with stage 3 to verify proper + compilation. + + (Perhaps simply defining `ALLOCA' in `x-crds' as described in the + comments there will make the above paragraph superfluous. Please + inform us of whether this works.) + + Unos uses memory segmentation instead of demand paging, so you + will need a lot of memory. 5 Mb is barely enough if no other + tasks are running. If linking `cc1' fails, try putting the object + files into a library and linking from that library. + +`m68k-hp-hpux' + HP 9000 series 300 or 400 running HP-UX. HP-UX version 8.0 has a + bug in the assembler that prevents compilation of GNU CC. To fix + it, get patch PHCO_4484 from HP. + + In addition, if you wish to use gas `--with-gnu-as' you must use + gas version 2.1 or later, and you must use the GNU linker version + 2.1 or later. Earlier versions of gas relied upon a program which + converted the gas output into the native HP-UX format, but that + program has not been kept up to date. gdb does not understand + that native HP-UX format, so you must use gas if you wish to use + gdb. + +`m68k-sun' + Sun 3. We do not provide a configuration file to use the Sun FPA + by default, because programs that establish signal handlers for + floating point traps inherently cannot work with the FPA. + + See *Note Sun Install::, for information on installing GNU CC on + Sun systems. + +`m88k-*-svr3' + Motorola m88k running the AT&T/Unisoft/Motorola V.3 reference port. + These systems tend to use the Green Hills C, revision 1.8.5, as the + standard C compiler. There are apparently bugs in this compiler + that result in object files differences between stage 2 and stage + 3. If this happens, make the stage 4 compiler and compare it to + the stage 3 compiler. If the stage 3 and stage 4 object files are + identical, this suggests you encountered a problem with the + standard C compiler; the stage 3 and 4 compilers may be usable. + + It is best, however, to use an older version of GNU CC for + bootstrapping if you have one. + +`m88k-*-dgux' + Motorola m88k running DG/UX. To build 88open BCS native or cross + compilers on DG/UX, specify the configuration name as + `m88k-*-dguxbcs' and build in the 88open BCS software development + environment. To build ELF native or cross compilers on DG/UX, + specify `m88k-*-dgux' and build in the DG/UX ELF development + environment. You set the software development environment by + issuing `sde-target' command and specifying either `m88kbcs' or + `m88kdguxelf' as the operand. + + If you do not specify a configuration name, `configure' guesses the + configuration based on the current software development + environment. + +`m88k-tektronix-sysv3' + Tektronix XD88 running UTekV 3.2e. Do not turn on optimization + while building stage1 if you bootstrap with the buggy Green Hills + compiler. Also, The bundled LAI System V NFS is buggy so if you + build in an NFS mounted directory, start from a fresh reboot, or + avoid NFS all together. Otherwise you may have trouble getting + clean comparisons between stages. + +`mips-mips-bsd' + MIPS machines running the MIPS operating system in BSD mode. It's + possible that some old versions of the system lack the functions + `memcpy', `memcmp', and `memset'. If your system lacks these, you + must remove or undo the definition of `TARGET_MEM_FUNCTIONS' in + `mips-bsd.h'. + + The MIPS C compiler needs to be told to increase its table size + for switch statements with the `-Wf,-XNg1500' option in order to + compile `cp/parse.c'. If you use the `-O2' optimization option, + you also need to use `-Olimit 3000'. Both of these options are + automatically generated in the `Makefile' that the shell script + `configure' builds. If you override the `CC' make variable and + use the MIPS compilers, you may need to add `-Wf,-XNg1500 -Olimit + 3000'. + +`mips-mips-riscos*' + The MIPS C compiler needs to be told to increase its table size + for switch statements with the `-Wf,-XNg1500' option in order to + compile `cp/parse.c'. If you use the `-O2' optimization option, + you also need to use `-Olimit 3000'. Both of these options are + automatically generated in the `Makefile' that the shell script + `configure' builds. If you override the `CC' make variable and + use the MIPS compilers, you may need to add `-Wf,-XNg1500 -Olimit + 3000'. + + MIPS computers running RISC-OS can support four different + personalities: default, BSD 4.3, System V.3, and System V.4 (older + versions of RISC-OS don't support V.4). To configure GCC for + these platforms use the following configurations: + + `mips-mips-riscos`rev'' + Default configuration for RISC-OS, revision `rev'. + + `mips-mips-riscos`rev'bsd' + BSD 4.3 configuration for RISC-OS, revision `rev'. + + `mips-mips-riscos`rev'sysv4' + System V.4 configuration for RISC-OS, revision `rev'. + + `mips-mips-riscos`rev'sysv' + System V.3 configuration for RISC-OS, revision `rev'. + + The revision `rev' mentioned above is the revision of RISC-OS to + use. You must reconfigure GCC when going from a RISC-OS revision + 4 to RISC-OS revision 5. This has the effect of avoiding a linker + bug. + +`mips-sgi-*' + In order to compile GCC on an SGI running IRIX 4, the "c.hdr.lib" + option must be installed from the CD-ROM supplied from Silicon + Graphics. This is found on the 2nd CD in release 4.0.1. + + In order to compile GCC on an SGI running IRIX 5, the + "compiler_dev.hdr" subsystem must be installed from the IDO CD-ROM + supplied by Silicon Graphics. + + `make compare' may fail on version 5 of IRIX unless you add + `-save-temps' to `CFLAGS'. On these systems, the name of the + assembler input file is stored in the object file, and that makes + comparison fail if it differs between the `stage1' and `stage2' + compilations. The option `-save-temps' forces a fixed name to be + used for the assembler input file, instead of a randomly chosen + name in `/tmp'. Do not add `-save-temps' unless the comparisons + fail without that option. If you do you `-save-temps', you will + have to manually delete the `.i' and `.s' files after each series + of compilations. + + The MIPS C compiler needs to be told to increase its table size + for switch statements with the `-Wf,-XNg1500' option in order to + compile `cp/parse.c'. If you use the `-O2' optimization option, + you also need to use `-Olimit 3000'. Both of these options are + automatically generated in the `Makefile' that the shell script + `configure' builds. If you override the `CC' make variable and + use the MIPS compilers, you may need to add `-Wf,-XNg1500 -Olimit + 3000'. + + On Irix version 4.0.5F, and perhaps on some other versions as well, + there is an assembler bug that reorders instructions incorrectly. + To work around it, specify the target configuration + `mips-sgi-irix4loser'. This configuration inhibits assembler + optimization. + + In a compiler configured with target `mips-sgi-irix4', you can turn + off assembler optimization by using the `-noasmopt' option. This + compiler option passes the option `-O0' to the assembler, to + inhibit reordering. + + The `-noasmopt' option can be useful for testing whether a problem + is due to erroneous assembler reordering. Even if a problem does + not go away with `-noasmopt', it may still be due to assembler + reordering--perhaps GNU CC itself was miscompiled as a result. + + To enable debugging under Irix 5, you must use GNU as 2.5 or later, + and use the `--with-gnu-as' configure option when configuring gcc. + GNU as is distributed as part of the binutils package. + +`mips-sony-sysv' + Sony MIPS NEWS. This works in NEWSOS 5.0.1, but not in 5.0.2 + (which uses ELF instead of COFF). Support for 5.0.2 will probably + be provided soon by volunteers. In particular, the linker does + not like the code generated by GCC when shared libraries are + linked in. + +`ns32k-encore' + Encore ns32000 system. Encore systems are supported only under + BSD. + +`ns32k-*-genix' + National Semiconductor ns32000 system. Genix has bugs in `alloca' + and `malloc'; you must get the compiled versions of these from GNU + Emacs. + +`ns32k-sequent' + Go to the Berkeley universe before compiling. + +`ns32k-utek' + UTEK ns32000 system ("merlin"). The C compiler that comes with + this system cannot compile GNU CC; contact `tektronix!reed!mason' + to get binaries of GNU CC for bootstrapping. + +`romp-*-aos' +`romp-*-mach' + The only operating systems supported for the IBM RT PC are AOS and + MACH. GNU CC does not support AIX running on the RT. We + recommend you compile GNU CC with an earlier version of itself; if + you compile GNU CC with `hc', the Metaware compiler, it will work, + but you will get mismatches between the stage 2 and stage 3 + compilers in various files. These errors are minor differences in + some floating-point constants and can be safely ignored; the stage + 3 compiler is correct. + +`rs6000-*-aix' +`powerpc-*-aix' + Various early versions of each release of the IBM XLC compiler + will not bootstrap GNU CC. Symptoms include differences between + the stage2 and stage3 object files, and errors when compiling + `libgcc.a' or `enquire'. Known problematic releases include: + xlc-1.2.1.8, xlc-1.3.0.0 (distributed with AIX 3.2.5), and + xlc-1.3.0.19. Both xlc-1.2.1.28 and xlc-1.3.0.24 (PTF 432238) are + known to produce working versions of GNU CC, but most other recent + releases correctly bootstrap GNU CC. + + Release 4.3.0 of AIX and ones prior to AIX 3.2.4 include a version + of the IBM assembler which does not accept debugging directives: + assembler updates are available as PTFs. Also, if you are using + AIX 3.2.5 or greater and the GNU assembler, you must have a + version modified after October 16th, 1995 in order for the GNU C + compiler to build. See the file `README.RS6000' for more details + on any of these problems. + + GNU CC does not yet support the 64-bit PowerPC instructions. + + Objective C does not work on this architecture because it makes + assumptions that are incompatible with the calling conventions. + + AIX on the RS/6000 provides support (NLS) for environments outside + of the United States. Compilers and assemblers use NLS to support + locale-specific representations of various objects including + floating-point numbers ("." vs "," for separating decimal + fractions). There have been problems reported where the library + linked with GNU CC does not produce the same floating-point + formats that the assembler accepts. If you have this problem, set + the LANG environment variable to "C" or "En_US". + + Due to changes in the way that GNU CC invokes the binder (linker) + for AIX 4.1, you may now receive warnings of duplicate symbols + from the link step that were not reported before. The assembly + files generated by GNU CC for AIX have always included multiple + symbol definitions for certain global variable and function + declarations in the original program. The warnings should not + prevent the linker from producing a correct library or runnable + executable. + + By default, AIX 4.1 produces code that can be used on either Power + or PowerPC processors. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-elf' +`powerpc-*-sysv4' + PowerPC system in big endian mode, running System V.4. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-linux-gnu' + PowerPC system in big endian mode, running the Linux-based GNU + system. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-eabiaix' + Embedded PowerPC system in big endian mode with -mcall-aix + selected as the default. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-eabisim' + Embedded PowerPC system in big endian mode for use in running + under the PSIM simulator. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpc-*-eabi' + Embedded PowerPC system in big endian mode. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpcle-*-elf' +`powerpcle-*-sysv4' + PowerPC system in little endian mode, running System V.4. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpcle-*-solaris2*' + PowerPC system in little endian mode, running Solaris 2.5.1 or + higher. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. Beta + versions of the Sun 4.0 compiler do not seem to be able to build + GNU CC correctly. There are also problems with the host assembler + and linker that are fixed by using the GNU versions of these tools. + +`powerpcle-*-eabisim' + Embedded PowerPC system in little endian mode for use in running + under the PSIM simulator. + +`powerpcle-*-eabi' + Embedded PowerPC system in little endian mode. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`powerpcle-*-winnt' +`powerpcle-*-pe' + PowerPC system in little endian mode running Windows NT. + + You can specify a default version for the `-mcpu='CPU_TYPE switch + by using the configure option `--with-cpu-'CPU_TYPE. + +`vax-dec-ultrix' + Don't try compiling with Vax C (`vcc'). It produces incorrect code + in some cases (for example, when `alloca' is used). + + Meanwhile, compiling `cp/parse.c' with pcc does not work because of + an internal table size limitation in that compiler. To avoid this + problem, compile just the GNU C compiler first, and use it to + recompile building all the languages that you want to run. + +`sparc-sun-*' + See *Note Sun Install::, for information on installing GNU CC on + Sun systems. + +`vax-dec-vms' + See *Note VMS Install::, for details on how to install GNU CC on + VMS. + +`we32k-*-*' + These computers are also known as the 3b2, 3b5, 3b20 and other + similar names. (However, the 3b1 is actually a 68000; see *Note + Configurations::.) + + Don't use `-g' when compiling with the system's compiler. The + system's linker seems to be unable to handle such a large program + with debugging information. + + The system's compiler runs out of capacity when compiling `stmt.c' + in GNU CC. You can work around this by building `cpp' in GNU CC + first, then use that instead of the system's preprocessor with the + system's C compiler to compile `stmt.c'. Here is how: + + mv /lib/cpp /lib/cpp.att + cp cpp /lib/cpp.gnu + echo '/lib/cpp.gnu -traditional ${1+"$@"}' > /lib/cpp + chmod +x /lib/cpp + + The system's compiler produces bad code for some of the GNU CC + optimization files. So you must build the stage 2 compiler without + optimization. Then build a stage 3 compiler with optimization. + That executable should work. Here are the necessary commands: + + make LANGUAGES=c CC=stage1/xgcc CFLAGS="-Bstage1/ -g" + make stage2 + make CC=stage2/xgcc CFLAGS="-Bstage2/ -g -O" + + You may need to raise the ULIMIT setting to build a C++ compiler, + as the file `cc1plus' is larger than one megabyte. + + +File: INSTALL, Node: Other Dir, Next: Cross-Compiler, Prev: Configurations, Up: Installation + +Compilation in a Separate Directory +=================================== + + If you wish to build the object files and executables in a directory +other than the one containing the source files, here is what you must +do differently: + + 1. Make sure you have a version of Make that supports the `VPATH' + feature. (GNU Make supports it, as do Make versions on most BSD + systems.) + + 2. If you have ever run `configure' in the source directory, you must + undo the configuration. Do this by running: + + make distclean + + 3. Go to the directory in which you want to build the compiler before + running `configure': + + mkdir gcc-sun3 + cd gcc-sun3 + + On systems that do not support symbolic links, this directory must + be on the same file system as the source code directory. + + 4. Specify where to find `configure' when you run it: + + ../gcc/configure ... + + This also tells `configure' where to find the compiler sources; + `configure' takes the directory from the file name that was used to + invoke it. But if you want to be sure, you can specify the source + directory with the `--srcdir' option, like this: + + ../gcc/configure --srcdir=../gcc OTHER OPTIONS + + The directory you specify with `--srcdir' need not be the same as + the one that `configure' is found in. + + Now, you can run `make' in that directory. You need not repeat the +configuration steps shown above, when ordinary source files change. You +must, however, run `configure' again when the configuration files +change, if your system does not support symbolic links. + + +File: INSTALL, Node: Cross-Compiler, Next: Sun Install, Prev: Other Dir, Up: Installation + +Building and Installing a Cross-Compiler +======================================== + + GNU CC can function as a cross-compiler for many machines, but not +all. + + * Cross-compilers for the Mips as target using the Mips assembler + currently do not work, because the auxiliary programs + `mips-tdump.c' and `mips-tfile.c' can't be compiled on anything + but a Mips. It does work to cross compile for a Mips if you use + the GNU assembler and linker. + + * Cross-compilers between machines with different floating point + formats have not all been made to work. GNU CC now has a floating + point emulator with which these can work, but each target machine + description needs to be updated to take advantage of it. + + * Cross-compilation between machines of different word sizes is + somewhat problematic and sometimes does not work. + + Since GNU CC generates assembler code, you probably need a +cross-assembler that GNU CC can run, in order to produce object files. +If you want to link on other than the target machine, you need a +cross-linker as well. You also need header files and libraries suitable +for the target machine that you can install on the host machine. + +* Menu: + +* Steps of Cross:: Using a cross-compiler involves several steps + that may be carried out on different machines. +* Configure Cross:: Configuring a cross-compiler. +* Tools and Libraries:: Where to put the linker and assembler, and the C library. +* Cross Headers:: Finding and installing header files + for a cross-compiler. +* Cross Runtime:: Supplying arithmetic runtime routines (`libgcc1.a'). +* Build Cross:: Actually compiling the cross-compiler. + + +File: INSTALL, Node: Steps of Cross, Next: Configure Cross, Up: Cross-Compiler + +Steps of Cross-Compilation +-------------------------- + + To compile and run a program using a cross-compiler involves several +steps: + + * Run the cross-compiler on the host machine to produce assembler + files for the target machine. This requires header files for the + target machine. + + * Assemble the files produced by the cross-compiler. You can do this + either with an assembler on the target machine, or with a + cross-assembler on the host machine. + + * Link those files to make an executable. You can do this either + with a linker on the target machine, or with a cross-linker on the + host machine. Whichever machine you use, you need libraries and + certain startup files (typically `crt....o') for the target + machine. + + It is most convenient to do all of these steps on the same host +machine, since then you can do it all with a single invocation of GNU +CC. This requires a suitable cross-assembler and cross-linker. For +some targets, the GNU assembler and linker are available. + + +File: INSTALL, Node: Configure Cross, Next: Tools and Libraries, Prev: Steps of Cross, Up: Cross-Compiler + +Configuring a Cross-Compiler +---------------------------- + + To build GNU CC as a cross-compiler, you start out by running +`configure'. Use the `--target=TARGET' to specify the target type. If +`configure' was unable to correctly identify the system you are running +on, also specify the `--build=BUILD' option. For example, here is how +to configure for a cross-compiler that produces code for an HP 68030 +system running BSD on a system that `configure' can correctly identify: + + ./configure --target=m68k-hp-bsd4.3 + + +File: INSTALL, Node: Tools and Libraries, Next: Cross Headers, Prev: Configure Cross, Up: Cross-Compiler + +Tools and Libraries for a Cross-Compiler +---------------------------------------- + + If you have a cross-assembler and cross-linker available, you should +install them now. Put them in the directory `/usr/local/TARGET/bin'. +Here is a table of the tools you should put in this directory: + +`as' + This should be the cross-assembler. + +`ld' + This should be the cross-linker. + +`ar' + This should be the cross-archiver: a program which can manipulate + archive files (linker libraries) in the target machine's format. + +`ranlib' + This should be a program to construct a symbol table in an archive + file. + + The installation of GNU CC will find these programs in that +directory, and copy or link them to the proper place to for the +cross-compiler to find them when run later. + + The easiest way to provide these files is to build the Binutils +package and GAS. Configure them with the same `--host' and `--target' +options that you use for configuring GNU CC, then build and install +them. They install their executables automatically into the proper +directory. Alas, they do not support all the targets that GNU CC +supports. + + If you want to install libraries to use with the cross-compiler, +such as a standard C library, put them in the directory +`/usr/local/TARGET/lib'; installation of GNU CC copies all the files in +that subdirectory into the proper place for GNU CC to find them and +link with them. Here's an example of copying some libraries from a +target machine: + + ftp TARGET-MACHINE + lcd /usr/local/TARGET/lib + cd /lib + get libc.a + cd /usr/lib + get libg.a + get libm.a + quit + +The precise set of libraries you'll need, and their locations on the +target machine, vary depending on its operating system. + + Many targets require "start files" such as `crt0.o' and `crtn.o' +which are linked into each executable; these too should be placed in +`/usr/local/TARGET/lib'. There may be several alternatives for +`crt0.o', for use with profiling or other compilation options. Check +your target's definition of `STARTFILE_SPEC' to find out what start +files it uses. Here's an example of copying these files from a target +machine: + + ftp TARGET-MACHINE + lcd /usr/local/TARGET/lib + prompt + cd /lib + mget *crt*.o + cd /usr/lib + mget *crt*.o + quit + + +File: INSTALL, Node: Cross Runtime, Next: Build Cross, Prev: Cross Headers, Up: Cross-Compiler + +`libgcc.a' and Cross-Compilers +------------------------------ + + Code compiled by GNU CC uses certain runtime support functions +implicitly. Some of these functions can be compiled successfully with +GNU CC itself, but a few cannot be. These problem functions are in the +source file `libgcc1.c'; the library made from them is called +`libgcc1.a'. + + When you build a native compiler, these functions are compiled with +some other compiler-the one that you use for bootstrapping GNU CC. +Presumably it knows how to open code these operations, or else knows how +to call the run-time emulation facilities that the machine comes with. +But this approach doesn't work for building a cross-compiler. The +compiler that you use for building knows about the host system, not the +target system. + + So, when you build a cross-compiler you have to supply a suitable +library `libgcc1.a' that does the job it is expected to do. + + To compile `libgcc1.c' with the cross-compiler itself does not work. +The functions in this file are supposed to implement arithmetic +operations that GNU CC does not know how to open code for your target +machine. If these functions are compiled with GNU CC itself, they will +compile into infinite recursion. + + On any given target, most of these functions are not needed. If GNU +CC can open code an arithmetic operation, it will not call these +functions to perform the operation. It is possible that on your target +machine, none of these functions is needed. If so, you can supply an +empty library as `libgcc1.a'. + + Many targets need library support only for multiplication and +division. If you are linking with a library that contains functions for +multiplication and division, you can tell GNU CC to call them directly +by defining the macros `MULSI3_LIBCALL', and the like. These macros +need to be defined in the target description macro file. For some +targets, they are defined already. This may be sufficient to avoid the +need for libgcc1.a; if so, you can supply an empty library. + + Some targets do not have floating point instructions; they need other +functions in `libgcc1.a', which do floating arithmetic. Recent +versions of GNU CC have a file which emulates floating point. With a +certain amount of work, you should be able to construct a floating +point emulator that can be used as `libgcc1.a'. Perhaps future +versions will contain code to do this automatically and conveniently. +That depends on whether someone wants to implement it. + + Some embedded targets come with all the necessary `libgcc1.a' +routines written in C or assembler. These targets build `libgcc1.a' +automatically and you do not need to do anything special for them. +Other embedded targets do not need any `libgcc1.a' routines since all +the necessary operations are supported by the hardware. + + If your target system has another C compiler, you can configure GNU +CC as a native compiler on that machine, build just `libgcc1.a' with +`make libgcc1.a' on that machine, and use the resulting file with the +cross-compiler. To do this, execute the following on the target +machine: + + cd TARGET-BUILD-DIR + ./configure --host=sparc --target=sun3 + make libgcc1.a + +And then this on the host machine: + + ftp TARGET-MACHINE + binary + cd TARGET-BUILD-DIR + get libgcc1.a + quit + + Another way to provide the functions you need in `libgcc1.a' is to +define the appropriate `perform_...' macros for those functions. If +these definitions do not use the C arithmetic operators that they are +meant to implement, you should be able to compile them with the +cross-compiler you are building. (If these definitions already exist +for your target file, then you are all set.) + + To build `libgcc1.a' using the perform macros, use +`LIBGCC1=libgcc1.a OLDCC=./xgcc' when building the compiler. +Otherwise, you should place your replacement library under the name +`libgcc1.a' in the directory in which you will build the +cross-compiler, before you run `make'. + + +File: INSTALL, Node: Cross Headers, Next: Cross Runtime, Prev: Tools and Libraries, Up: Cross-Compiler + +Cross-Compilers and Header Files +-------------------------------- + + If you are cross-compiling a standalone program or a program for an +embedded system, then you may not need any header files except the few +that are part of GNU CC (and those of your program). However, if you +intend to link your program with a standard C library such as `libc.a', +then you probably need to compile with the header files that go with +the library you use. + + The GNU C compiler does not come with these files, because (1) they +are system-specific, and (2) they belong in a C library, not in a +compiler. + + If the GNU C library supports your target machine, then you can get +the header files from there (assuming you actually use the GNU library +when you link your program). + + If your target machine comes with a C compiler, it probably comes +with suitable header files also. If you make these files accessible +from the host machine, the cross-compiler can use them also. + + Otherwise, you're on your own in finding header files to use when +cross-compiling. + + When you have found suitable header files, put them in the directory +`/usr/local/TARGET/include', before building the cross compiler. Then +installation will run fixincludes properly and install the corrected +versions of the header files where the compiler will use them. + + Provide the header files before you build the cross-compiler, because +the build stage actually runs the cross-compiler to produce parts of +`libgcc.a'. (These are the parts that *can* be compiled with GNU CC.) +Some of them need suitable header files. + + Here's an example showing how to copy the header files from a target +machine. On the target machine, do this: + + (cd /usr/include; tar cf - .) > tarfile + + Then, on the host machine, do this: + + ftp TARGET-MACHINE + lcd /usr/local/TARGET/include + get tarfile + quit + tar xf tarfile + + +File: INSTALL, Node: Build Cross, Prev: Cross Runtime, Up: Cross-Compiler + +Actually Building the Cross-Compiler +------------------------------------ + + Now you can proceed just as for compiling a single-machine compiler +through the step of building stage 1. If you have not provided some +sort of `libgcc1.a', then compilation will give up at the point where +it needs that file, printing a suitable error message. If you do +provide `libgcc1.a', then building the compiler will automatically +compile and link a test program called `libgcc1-test'; if you get +errors in the linking, it means that not all of the necessary routines +in `libgcc1.a' are available. + + You must provide the header file `float.h'. One way to do this is +to compile `enquire' and run it on your target machine. The job of +`enquire' is to run on the target machine and figure out by experiment +the nature of its floating point representation. `enquire' records its +findings in the header file `float.h'. If you can't produce this file +by running `enquire' on the target machine, then you will need to come +up with a suitable `float.h' in some other way (or else, avoid using it +in your programs). + + Do not try to build stage 2 for a cross-compiler. It doesn't work to +rebuild GNU CC as a cross-compiler using the cross-compiler, because +that would produce a program that runs on the target machine, not on the +host. For example, if you compile a 386-to-68030 cross-compiler with +itself, the result will not be right either for the 386 (because it was +compiled into 68030 code) or for the 68030 (because it was configured +for a 386 as the host). If you want to compile GNU CC into 68030 code, +whether you compile it on a 68030 or with a cross-compiler on a 386, you +must specify a 68030 as the host when you configure it. + + To install the cross-compiler, use `make install', as usual. + + +File: INSTALL, Node: Sun Install, Next: VMS Install, Prev: Cross-Compiler, Up: Installation + +Installing GNU CC on the Sun +============================ + + On Solaris, do not use the linker or other tools in `/usr/ucb' to +build GNU CC. Use `/usr/ccs/bin'. + + If the assembler reports `Error: misaligned data' when bootstrapping, +you are probably using an obsolete version of the GNU assembler. +Upgrade to the latest version of GNU `binutils', or use the Solaris +assembler. + + Make sure the environment variable `FLOAT_OPTION' is not set when +you compile `libgcc.a'. If this option were set to `f68881' when +`libgcc.a' is compiled, the resulting code would demand to be linked +with a special startup file and would not link properly without special +pains. + + There is a bug in `alloca' in certain versions of the Sun library. +To avoid this bug, install the binaries of GNU CC that were compiled by +GNU CC. They use `alloca' as a built-in function and never the one in +the library. + + Some versions of the Sun compiler crash when compiling GNU CC. The +problem is a segmentation fault in cpp. This problem seems to be due to +the bulk of data in the environment variables. You may be able to avoid +it by using the following command to compile GNU CC with Sun CC: + + make CC="TERMCAP=x OBJS=x LIBFUNCS=x STAGESTUFF=x cc" + + SunOS 4.1.3 and 4.1.3_U1 have bugs that can cause intermittent core +dumps when compiling GNU CC. A common symptom is an internal compiler +error which does not recur if you run it again. To fix the problem, +install Sun recommended patch 100726 (for SunOS 4.1.3) or 101508 (for +SunOS 4.1.3_U1), or upgrade to a later SunOS release. + + +File: INSTALL, Node: VMS Install, Next: Collect2, Prev: Sun Install, Up: Installation + +Installing GNU CC on VMS +======================== + + The VMS version of GNU CC is distributed in a backup saveset +containing both source code and precompiled binaries. + + To install the `gcc' command so you can use the compiler easily, in +the same manner as you use the VMS C compiler, you must install the VMS +CLD file for GNU CC as follows: + + 1. Define the VMS logical names `GNU_CC' and `GNU_CC_INCLUDE' to + point to the directories where the GNU CC executables + (`gcc-cpp.exe', `gcc-cc1.exe', etc.) and the C include files are + kept respectively. This should be done with the commands: + + $ assign /system /translation=concealed - + disk:[gcc.] gnu_cc + $ assign /system /translation=concealed - + disk:[gcc.include.] gnu_cc_include + + with the appropriate disk and directory names. These commands can + be placed in your system startup file so they will be executed + whenever the machine is rebooted. You may, if you choose, do this + via the `GCC_INSTALL.COM' script in the `[GCC]' directory. + + 2. Install the `GCC' command with the command line: + + $ set command /table=sys$common:[syslib]dcltables - + /output=sys$common:[syslib]dcltables gnu_cc:[000000]gcc + $ install replace sys$common:[syslib]dcltables + + 3. To install the help file, do the following: + + $ library/help sys$library:helplib.hlb gcc.hlp + + Now you can invoke the compiler with a command like `gcc /verbose + file.c', which is equivalent to the command `gcc -v -c file.c' in + Unix. + + If you wish to use GNU C++ you must first install GNU CC, and then +perform the following steps: + + 1. Define the VMS logical name `GNU_GXX_INCLUDE' to point to the + directory where the preprocessor will search for the C++ header + files. This can be done with the command: + + $ assign /system /translation=concealed - + disk:[gcc.gxx_include.] gnu_gxx_include + + with the appropriate disk and directory name. If you are going to + be using a C++ runtime library, this is where its install + procedure will install its header files. + + 2. Obtain the file `gcc-cc1plus.exe', and place this in the same + directory that `gcc-cc1.exe' is kept. + + The GNU C++ compiler can be invoked with a command like `gcc /plus + /verbose file.cc', which is equivalent to the command `g++ -v -c + file.cc' in Unix. + + We try to put corresponding binaries and sources on the VMS +distribution tape. But sometimes the binaries will be from an older +version than the sources, because we don't always have time to update +them. (Use the `/version' option to determine the version number of +the binaries and compare it with the source file `version.c' to tell +whether this is so.) In this case, you should use the binaries you get +to recompile the sources. If you must recompile, here is how: + + 1. Execute the command procedure `vmsconfig.com' to set up the files + `tm.h', `config.h', `aux-output.c', and `md.', and to create files + `tconfig.h' and `hconfig.h'. This procedure also creates several + linker option files used by `make-cc1.com' and a data file used by + `make-l2.com'. + + $ @vmsconfig.com + + 2. Setup the logical names and command tables as defined above. In + addition, define the VMS logical name `GNU_BISON' to point at the + to the directories where the Bison executable is kept. This + should be done with the command: + + $ assign /system /translation=concealed - + disk:[bison.] gnu_bison + + You may, if you choose, use the `INSTALL_BISON.COM' script in the + `[BISON]' directory. + + 3. Install the `BISON' command with the command line: + + $ set command /table=sys$common:[syslib]dcltables - + /output=sys$common:[syslib]dcltables - + gnu_bison:[000000]bison + $ install replace sys$common:[syslib]dcltables + + 4. Type `@make-gcc' to recompile everything (alternatively, submit + the file `make-gcc.com' to a batch queue). If you wish to build + the GNU C++ compiler as well as the GNU CC compiler, you must + first edit `make-gcc.com' and follow the instructions that appear + in the comments. + + 5. In order to use GCC, you need a library of functions which GCC + compiled code will call to perform certain tasks, and these + functions are defined in the file `libgcc2.c'. To compile this + you should use the command procedure `make-l2.com', which will + generate the library `libgcc2.olb'. `libgcc2.olb' should be built + using the compiler built from the same distribution that + `libgcc2.c' came from, and `make-gcc.com' will automatically do + all of this for you. + + To install the library, use the following commands: + + $ library gnu_cc:[000000]gcclib/delete=(new,eprintf) + $ library gnu_cc:[000000]gcclib/delete=L_* + $ library libgcc2/extract=*/output=libgcc2.obj + $ library gnu_cc:[000000]gcclib libgcc2.obj + + The first command simply removes old modules that will be replaced + with modules from `libgcc2' under different module names. The + modules `new' and `eprintf' may not actually be present in your + `gcclib.olb'--if the VMS librarian complains about those modules + not being present, simply ignore the message and continue on with + the next command. The second command removes the modules that + came from the previous version of the library `libgcc2.c'. + + Whenever you update the compiler on your system, you should also + update the library with the above procedure. + + 6. You may wish to build GCC in such a way that no files are written + to the directory where the source files reside. An example would + be the when the source files are on a read-only disk. In these + cases, execute the following DCL commands (substituting your + actual path names): + + $ assign dua0:[gcc.build_dir.]/translation=concealed, - + dua1:[gcc.source_dir.]/translation=concealed gcc_build + $ set default gcc_build:[000000] + + where the directory `dua1:[gcc.source_dir]' contains the source + code, and the directory `dua0:[gcc.build_dir]' is meant to contain + all of the generated object files and executables. Once you have + done this, you can proceed building GCC as described above. (Keep + in mind that `gcc_build' is a rooted logical name, and thus the + device names in each element of the search list must be an actual + physical device name rather than another rooted logical name). + + 7. *If you are building GNU CC with a previous version of GNU CC, you + also should check to see that you have the newest version of the + assembler*. In particular, GNU CC version 2 treats global constant + variables slightly differently from GNU CC version 1, and GAS + version 1.38.1 does not have the patches required to work with GCC + version 2. If you use GAS 1.38.1, then `extern const' variables + will not have the read-only bit set, and the linker will generate + warning messages about mismatched psect attributes for these + variables. These warning messages are merely a nuisance, and can + safely be ignored. + + If you are compiling with a version of GNU CC older than 1.33, + specify `/DEFINE=("inline=")' as an option in all the + compilations. This requires editing all the `gcc' commands in + `make-cc1.com'. (The older versions had problems supporting + `inline'.) Once you have a working 1.33 or newer GNU CC, you can + change this file back. + + 8. If you want to build GNU CC with the VAX C compiler, you will need + to make minor changes in `make-cccp.com' and `make-cc1.com' to + choose alternate definitions of `CC', `CFLAGS', and `LIBS'. See + comments in those files. However, you must also have a working + version of the GNU assembler (GNU as, aka GAS) as it is used as + the back-end for GNU CC to produce binary object modules and is + not included in the GNU CC sources. GAS is also needed to compile + `libgcc2' in order to build `gcclib' (see above); `make-l2.com' + expects to be able to find it operational in + `gnu_cc:[000000]gnu-as.exe'. + + To use GNU CC on VMS, you need the VMS driver programs `gcc.exe', + `gcc.com', and `gcc.cld'. They are distributed with the VMS + binaries (`gcc-vms') rather than the GNU CC sources. GAS is also + included in `gcc-vms', as is Bison. + + Once you have successfully built GNU CC with VAX C, you should use + the resulting compiler to rebuild itself. Before doing this, be + sure to restore the `CC', `CFLAGS', and `LIBS' definitions in + `make-cccp.com' and `make-cc1.com'. The second generation + compiler will be able to take advantage of many optimizations that + must be suppressed when building with other compilers. + + Under previous versions of GNU CC, the generated code would +occasionally give strange results when linked with the sharable +`VAXCRTL' library. Now this should work. + + Even with this version, however, GNU CC itself should not be linked +with the sharable `VAXCRTL'. The version of `qsort' in `VAXCRTL' has a +bug (known to be present in VMS versions V4.6 through V5.5) which +causes the compiler to fail. + + The executables are generated by `make-cc1.com' and `make-cccp.com' +use the object library version of `VAXCRTL' in order to make use of the +`qsort' routine in `gcclib.olb'. If you wish to link the compiler +executables with the shareable image version of `VAXCRTL', you should +edit the file `tm.h' (created by `vmsconfig.com') to define the macro +`QSORT_WORKAROUND'. + + `QSORT_WORKAROUND' is always defined when GNU CC is compiled with +VAX C, to avoid a problem in case `gcclib.olb' is not yet available. + + +File: INSTALL, Node: Collect2, Next: Header Dirs, Prev: VMS Install, Up: Installation + +`collect2' +========== + + GNU CC uses a utility called `collect2' on nearly all systems to +arrange to call various initialization functions at start time. + + The program `collect2' works by linking the program once and looking +through the linker output file for symbols with particular names +indicating they are constructor functions. If it finds any, it creates +a new temporary `.c' file containing a table of them, compiles it, and +links the program a second time including that file. + + The actual calls to the constructors are carried out by a subroutine +called `__main', which is called (automatically) at the beginning of +the body of `main' (provided `main' was compiled with GNU CC). Calling +`__main' is necessary, even when compiling C code, to allow linking C +and C++ object code together. (If you use `-nostdlib', you get an +unresolved reference to `__main', since it's defined in the standard +GCC library. Include `-lgcc' at the end of your compiler command line +to resolve this reference.) + + The program `collect2' is installed as `ld' in the directory where +the passes of the compiler are installed. When `collect2' needs to +find the *real* `ld', it tries the following file names: + + * `real-ld' in the directories listed in the compiler's search + directories. + + * `real-ld' in the directories listed in the environment variable + `PATH'. + + * The file specified in the `REAL_LD_FILE_NAME' configuration macro, + if specified. + + * `ld' in the compiler's search directories, except that `collect2' + will not execute itself recursively. + + * `ld' in `PATH'. + + "The compiler's search directories" means all the directories where +`gcc' searches for passes of the compiler. This includes directories +that you specify with `-B'. + + Cross-compilers search a little differently: + + * `real-ld' in the compiler's search directories. + + * `TARGET-real-ld' in `PATH'. + + * The file specified in the `REAL_LD_FILE_NAME' configuration macro, + if specified. + + * `ld' in the compiler's search directories. + + * `TARGET-ld' in `PATH'. + + `collect2' explicitly avoids running `ld' using the file name under +which `collect2' itself was invoked. In fact, it remembers up a list +of such names--in case one copy of `collect2' finds another copy (or +version) of `collect2' installed as `ld' in a second place in the +search path. + + `collect2' searches for the utilities `nm' and `strip' using the +same algorithm as above for `ld'. + + +File: INSTALL, Node: Header Dirs, Prev: Collect2, Up: Installation + +Standard Header File Directories +================================ + + `GCC_INCLUDE_DIR' means the same thing for native and cross. It is +where GNU CC stores its private include files, and also where GNU CC +stores the fixed include files. A cross compiled GNU CC runs +`fixincludes' on the header files in `$(tooldir)/include'. (If the +cross compilation header files need to be fixed, they must be installed +before GNU CC is built. If the cross compilation header files are +already suitable for ANSI C and GNU CC, nothing special need be done). + + `GPLUS_INCLUDE_DIR' means the same thing for native and cross. It +is where `g++' looks first for header files. The C++ library installs +only target independent header files in that directory. + + `LOCAL_INCLUDE_DIR' is used only for a native compiler. It is +normally `/usr/local/include'. GNU CC searches this directory so that +users can install header files in `/usr/local/include'. + + `CROSS_INCLUDE_DIR' is used only for a cross compiler. GNU CC +doesn't install anything there. + + `TOOL_INCLUDE_DIR' is used for both native and cross compilers. It +is the place for other packages to install header files that GNU CC will +use. For a cross-compiler, this is the equivalent of `/usr/include'. +When you build a cross-compiler, `fixincludes' processes any header +files in this directory. + + + +Tag Table: +Node: Installation351 +Node: Configurations26618 +Node: Other Dir65739 +Node: Cross-Compiler67454 +Node: Steps of Cross69284 +Node: Configure Cross70401 +Node: Tools and Libraries71037 +Node: Cross Runtime73475 +Node: Cross Headers77555 +Node: Build Cross79553 +Node: Sun Install81428 +Node: VMS Install83099 +Node: Collect293028 +Node: Header Dirs95592 + +End Tag Table diff --git a/contrib/gcc/LITERATURE b/contrib/gcc/LITERATURE new file mode 100644 index 000000000000..2cbe780df846 --- /dev/null +++ b/contrib/gcc/LITERATURE @@ -0,0 +1,99 @@ +Collected papers/sites on standards, compilers, optimization, etc. + +- Massively Scalar Compiler Project + + ftp://cs.rice.edu/public/preston/optimizer + +- http://www.lpac.ac.uk/SEL-HPC/Articles/CompilersArchive.html + +- David M Keaton's site + + http://www.dmk.com, ftp://ftp.dmk.com + c9x stuff is in ftp://ftp.dmk.com/DMK/sc22wg14/c9x + +- Some information about optimizing for x86 processors, links to + x86 manuals and documentation. + + http://www.goof.com/pcg/docs.html + + +- AMD site with optimization guide for x86 + + http://www.amd.com/K6/k6docs/pdf/21828a.pdf + +- Links related to many compiler topics + + http://www.nullstone.com/htmls/connections.htm + +- HPPA information: + + http://www.hp.com/computing/framed/technology/micropro + +- New compiler book. Online appendix includes some compiler links + + http://www.mkp.com/books_catalog/1-55860-320-4.asp + +- Various MIPS stuff: + + http://www.sgi.com/MIPS/arch/mips4docs/mipsiv_3_2.pdf (*) + http://www.sgi.com/MIPS/arch/MIPS16/MIPS16.whitepaper.pdf + http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf + http://www.sgi.com/MIPS/arch/ISA5/isa5_tech_brf.pdf + http://www.sgi.com/MIPS/arch/ISA5/MDMXspec.pdf + http://www.sgi.com/MIPS/arch/ISA5/MIPSVspec.pdf + + +- IBM Journal of Research and Development + + http://www.almaden.ibm.com/journal/ + + +- System V PowerPC ABI + + http://www.esofta.com/softspecs.html + +- C9X draft + + http://www.dkuug.dk/JTC1/SC22/WG14/www/docs/n794.htm + +- DWARF v2 spec and sample implementation + + ftp://sgigate.sgi.com/pub/dwarf/ + + +- Various m68k info (including user guides in pdf format) + + http://www.mot.com/SPS/HPESD/prod/0X0 + + +- Modula 3 Stuff + + http://www.cmass.com + http://www.cl.cam.ac.uk/m3doc/linux/cambridge.html + ftp://ftp.freebsd.org/pub/FreeBSD/distfiles/LOCAL_PORTS/m3-fbsd-m3cc-3.6.tar.gz + http://www.m3.org + +- Comp.compilers archive + + http://www.iecc.com/compilers + +- Intel Pentium design info: + + http://developer.intel.com/design/litcentr/index.htm + +- comp.std.c++ FAQ: + + http://reality.sgi.com/employees/austern_mti/std-c++/faq.html + +- EG3 maintains a list of compiler Internet resources, including FAQ's, +papers, hot list pages, potential software/shareware, all known companies, etc. + + http://www.eg3.com/ulc/compulc.htm + http://www.eg3.com/softd/compiler.htm + http://www.eg3.com/softdv/compiler.htm + + These resource pages are published as part of EG3's + Free Electronic Engineers' Toolbox at: + + http://www.eg3.com/ebox.htm + diff --git a/contrib/gcc/Makefile.in b/contrib/gcc/Makefile.in index b1f7b0808c75..1a140c4ec2bd 100644 --- a/contrib/gcc/Makefile.in +++ b/contrib/gcc/Makefile.in @@ -18,7 +18,7 @@ #the Free Software Foundation, 59 Temple Place - Suite 330, #Boston MA 02111-1307, USA. -# $FreeBSD$ +# $FreeBSD: src/contrib/gcc/Makefile.in,v 1.4 1999/10/16 08:21:54 obrien Exp $ # The targets for external use include: # all, doc, proto, install, install-cross, install-cross-rest, diff --git a/contrib/gcc/c-common.c b/contrib/gcc/c-common.c index aeb08fd742c3..6396c2da7f06 100644 --- a/contrib/gcc/c-common.c +++ b/contrib/gcc/c-common.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/c-common.c,v 1.8.2.2 2000/04/18 21:09:03 obrien Exp $ */ #include "config.h" #include "system.h" diff --git a/contrib/gcc/c-tree.h b/contrib/gcc/c-tree.h index 40c2f2dbac5b..d8cec4751657 100644 --- a/contrib/gcc/c-tree.h +++ b/contrib/gcc/c-tree.h @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/c-tree.h,v 1.4 1999/10/16 08:34:33 obrien Exp $ */ #ifndef _C_TREE_H #define _C_TREE_H diff --git a/contrib/gcc/cccp.1 b/contrib/gcc/cccp.1 index 442f0ab748e9..a056a7e10f64 100644 --- a/contrib/gcc/cccp.1 +++ b/contrib/gcc/cccp.1 @@ -1,4 +1,4 @@ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/gcc/cccp.1,v 1.3 1999/09/19 08:18:18 obrien Exp $ .\" Copyright (c) 1991, 1992, 1993 Free Software Foundation \-*-Text-*- .\" See section COPYING for conditions for redistribution .TH cpp 1 "April 30, 1993" "FreeBSD" "GNU Tools" diff --git a/contrib/gcc/cccp.c b/contrib/gcc/cccp.c index 69cd93d3e88b..a26e6bcdb1be 100644 --- a/contrib/gcc/cccp.c +++ b/contrib/gcc/cccp.c @@ -18,7 +18,7 @@ along with this program; if not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/cccp.c,v 1.6 2000/03/09 10:11:07 obrien Exp $ */ #include "config.h" diff --git a/contrib/gcc/choose-temp.c b/contrib/gcc/choose-temp.c index 018f7d92a89f..22678f19cce1 100644 --- a/contrib/gcc/choose-temp.c +++ b/contrib/gcc/choose-temp.c @@ -22,7 +22,7 @@ Boston, MA 02111-1307, USA. */ /* This file lives in at least two places: libiberty and gcc. Don't change one without the other. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/choose-temp.c,v 1.3 1999/11/04 10:23:25 obrien Exp $ */ #ifdef HAVE_CONFIG_H #include "config.h" diff --git a/contrib/gcc/config.sub b/contrib/gcc/config.sub new file mode 100755 index 000000000000..b491c9f5ce05 --- /dev/null +++ b/contrib/gcc/config.sub @@ -0,0 +1,976 @@ +#! /bin/sh +# Configuration validation subroutine script, version 1.1. +# Copyright (C) 1991, 92-97, 1998 Free Software Foundation, Inc. +# This file is (in principle) common to ALL GNU software. +# The presence of a machine in this file suggests that SOME GNU software +# can handle that machine. It does not imply ALL GNU software can. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# Configuration subroutine to validate and canonicalize a configuration type. +# Supply the specified configuration type as an argument. +# If it is invalid, we print an error message on stderr and exit with code 1. +# Otherwise, we print the canonical config type on stdout and succeed. + +# This file is supposed to be the same for all GNU packages +# and recognize all the CPU types, system types and aliases +# that are meaningful with *any* GNU software. +# Each package is responsible for reporting which valid configurations +# it does not support. The user should be able to distinguish +# a failure to support a valid configuration from a meaningless +# configuration. + +# The goal of this file is to map all the various variations of a given +# machine specification into a single specification in the form: +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or in some cases, the newer four-part form: +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# It is wrong to echo any other type of specification. + +if [ x$1 = x ] +then + echo Configuration name missing. 1>&2 + echo "Usage: $0 CPU-MFR-OPSYS" 1>&2 + echo "or $0 ALIAS" 1>&2 + echo where ALIAS is a recognized configuration type. 1>&2 + exit 1 +fi + +# First pass through any local machine types. +case $1 in + *local*) + echo $1 + exit 0 + ;; + *) + ;; +esac + +# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). +# Here we must recognize all the valid KERNEL-OS combinations. +maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` +case $maybe_os in + linux-gnu*) + os=-$maybe_os + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` + ;; + *) + basic_machine=`echo $1 | sed 's/-[^-]*$//'` + if [ $basic_machine != $1 ] + then os=`echo $1 | sed 's/.*-/-/'` + else os=; fi + ;; +esac + +### Let's recognize common machines as not being operating systems so +### that things like config.sub decstation-3100 work. We also +### recognize some manufacturers as not being operating systems, so we +### can provide default operating systems below. +case $os in + -sun*os*) + # Prevent following clause from handling this invalid input. + ;; + -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ + -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ + -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ + -apple) + os= + basic_machine=$1 + ;; + -hiux*) + os=-hiuxwe2 + ;; + -sco5) + os=-sco3.2v5 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco4) + os=-sco3.2v4 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2.[4-9]*) + os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2v[4-9]*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco*) + os=-sco3.2v2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -isc) + os=-isc2.2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -clix*) + basic_machine=clipper-intergraph + ;; + -isc*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -lynx*) + os=-lynxos + ;; + -ptx*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` + ;; + -windowsnt*) + os=`echo $os | sed -e 's/windowsnt/winnt/'` + ;; + -psos*) + os=-psos + ;; +esac + +# Decode aliases for certain CPU-COMPANY combinations. +case $basic_machine in + # Recognize the basic CPU types without company name. + # Some are omitted here because they have special meanings below. + tahoe | i860 | m32r | m68k | m68000 | m88k | ns32k | arc | arm \ + | arme[lb] | pyramid | mn10200 | mn10300 \ + | tron | a29k | 580 | i960 | h8300 | hppa | hppa1.0 | hppa1.1 \ + | alpha | alphaev5 | alphaev56 | we32k | ns16k | clipper \ + | i370 | sh | powerpc | powerpcle | 1750a | dsp16xx | pdp11 \ + | mips64 | mipsel | mips64el | mips64orion | mips64orionel \ + | mipstx39 | mipstx39el \ + | sparc | sparclet | sparclite | sparc64 | v850) + basic_machine=$basic_machine-unknown + ;; + thumb | thumbel) + basic_machine=$basic_machine-unknown + ;; + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. + i[34567]86) + basic_machine=$basic_machine-pc + ;; + # Object if more than one company name word. + *-*-*) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; + # Recognize the basic CPU types with company name. + vax-* | tahoe-* | i[34567]86-* | i860-* | m32r-* | m68k-* | m68000-* \ + | m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | arm-* | c[123]* \ + | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \ + | power-* | none-* | 580-* | cray2-* | h8300-* | i960-* \ + | xmp-* | ymp-* | hppa-* | hppa1.0-* | hppa1.1-* \ + | alpha-* | alphaev5-* | alphaev56-* | we32k-* | cydra-* \ + | ns16k-* | pn-* | np1-* | xps100-* | clipper-* | orion-* \ + | sparclite-* | pdp11-* | sh-* | powerpc-* | powerpcle-* \ + | sparc64-* | mips64-* | mipsel-* \ + | mips64el-* | mips64orion-* | mips64orionel-* \ + | mipstx39-* | mipstx39el-* \ + | f301-*) + ;; + # Recognize the various machine names and aliases which stand + # for a CPU type and a company and sometimes even an OS. + 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) + basic_machine=m68000-att + ;; + 3b*) + basic_machine=we32k-att + ;; + alliant | fx80) + basic_machine=fx80-alliant + ;; + altos | altos3068) + basic_machine=m68k-altos + ;; + am29k) + basic_machine=a29k-none + os=-bsd + ;; + amdahl) + basic_machine=580-amdahl + os=-sysv + ;; + amiga | amiga-*) + basic_machine=m68k-cbm + ;; + amigaos | amigados) + basic_machine=m68k-cbm + os=-amigaos + ;; + amigaunix | amix) + basic_machine=m68k-cbm + os=-sysv4 + ;; + apollo68) + basic_machine=m68k-apollo + os=-sysv + ;; + aux) + basic_machine=m68k-apple + os=-aux + ;; + balance) + basic_machine=ns32k-sequent + os=-dynix + ;; + convex-c1) + basic_machine=c1-convex + os=-bsd + ;; + convex-c2) + basic_machine=c2-convex + os=-bsd + ;; + convex-c32) + basic_machine=c32-convex + os=-bsd + ;; + convex-c34) + basic_machine=c34-convex + os=-bsd + ;; + convex-c38) + basic_machine=c38-convex + os=-bsd + ;; + cray | ymp) + basic_machine=ymp-cray + os=-unicos + ;; + cray2) + basic_machine=cray2-cray + os=-unicos + ;; + [ctj]90-cray) + basic_machine=c90-cray + os=-unicos + ;; + crds | unos) + basic_machine=m68k-crds + ;; + da30 | da30-*) + basic_machine=m68k-da30 + ;; + decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) + basic_machine=mips-dec + ;; + delta | 3300 | motorola-3300 | motorola-delta \ + | 3300-motorola | delta-motorola) + basic_machine=m68k-motorola + ;; + delta88) + basic_machine=m88k-motorola + os=-sysv3 + ;; + dpx20 | dpx20-*) + basic_machine=rs6000-bull + os=-bosx + ;; + dpx2* | dpx2*-bull) + basic_machine=m68k-bull + os=-sysv3 + ;; + ebmon29k) + basic_machine=a29k-amd + os=-ebmon + ;; + elxsi) + basic_machine=elxsi-elxsi + os=-bsd + ;; + encore | umax | mmax) + basic_machine=ns32k-encore + ;; + fx2800) + basic_machine=i860-alliant + ;; + genix) + basic_machine=ns32k-ns + ;; + gmicro) + basic_machine=tron-gmicro + os=-sysv + ;; + h3050r* | hiux*) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + h8300hms) + basic_machine=h8300-hitachi + os=-hms + ;; + harris) + basic_machine=m88k-harris + os=-sysv3 + ;; + hp300-*) + basic_machine=m68k-hp + ;; + hp300bsd) + basic_machine=m68k-hp + os=-bsd + ;; + hp300hpux) + basic_machine=m68k-hp + os=-hpux + ;; + hp9k2[0-9][0-9] | hp9k31[0-9]) + basic_machine=m68000-hp + ;; + hp9k3[2-9][0-9]) + basic_machine=m68k-hp + ;; + hp9k6[0-9][0-9] | hp6[0-9][0-9] ) + basic_machine=hppa1.0-hp + ;; + hp9k7[0-79][0-9] | hp7[0-79][0-9] ) + basic_machine=hppa1.1-hp + ;; + hp9k78[0-9] | hp78[0-9] ) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | \ + hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893 ) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][13679] | hp8[0-9][13679] ) + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][0-9] | hp8[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hppa-next) + os=-nextstep3 + ;; + i370-ibm* | ibm*) + basic_machine=i370-ibm + os=-mvs + ;; +# I'm not sure what "Sysv32" means. Should this be sysv3.2? + i[34567]86v32) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv32 + ;; + i[34567]86v4*) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv4 + ;; + i[34567]86v) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv + ;; + i[34567]86sol2) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-solaris2 + ;; + iris | iris4d) + basic_machine=mips-sgi + case $os in + -irix*) + ;; + *) + os=-irix4 + ;; + esac + ;; + isi68 | isi) + basic_machine=m68k-isi + os=-sysv + ;; + m88k-omron*) + basic_machine=m88k-omron + ;; + magnum | m3230) + basic_machine=mips-mips + os=-sysv + ;; + merlin) + basic_machine=ns32k-utek + os=-sysv + ;; + miniframe) + basic_machine=m68000-convergent + ;; + mipsel*-linux*) + basic_machine=mipsel-unknown + os=-linux-gnu + ;; + mips*-linux*) + basic_machine=mips-unknown + os=-linux-gnu + ;; + mips3*-*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` + ;; + mips3*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown + ;; + ncr3000) + basic_machine=i486-ncr + os=-sysv4 + ;; + news | news700 | news800 | news900) + basic_machine=m68k-sony + os=-newsos + ;; + news1000) + basic_machine=m68030-sony + os=-newsos + ;; + news-3600 | risc-news) + basic_machine=mips-sony + os=-newsos + ;; + next | m*-next ) + basic_machine=m68k-next + case $os in + -nextstep* ) + ;; + -ns2*) + os=-nextstep2 + ;; + *) + os=-nextstep3 + ;; + esac + ;; + nh3000) + basic_machine=m68k-harris + os=-cxux + ;; + nh[45]000) + basic_machine=m88k-harris + os=-cxux + ;; + nindy960) + basic_machine=i960-intel + os=-nindy + ;; + np1) + basic_machine=np1-gould + ;; + pa-hitachi) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + paragon) + basic_machine=i860-intel + os=-osf + ;; + pbd) + basic_machine=sparc-tti + ;; + pbb) + basic_machine=m68k-tti + ;; + pc532 | pc532-*) + basic_machine=ns32k-pc532 + ;; + pentium | p5 | k5 | nexen) + basic_machine=i586-pc + ;; + pentiumpro | p6 | k6 | 6x86) + basic_machine=i686-pc + ;; + pentiumii | pentium2) + basic_machine=i786-pc + ;; + pentium-* | p5-* | k5-* | nexen-*) + basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumpro-* | p6-* | k6-* | 6x86-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumii-* | pentium2-*) + basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pn) + basic_machine=pn-gould + ;; + power) basic_machine=rs6000-ibm + ;; + ppc) basic_machine=powerpc-unknown + ;; + ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppcle | powerpclittle | ppc-le | powerpc-little) + basic_machine=powerpcle-unknown + ;; + ppcle-* | powerpclittle-*) + basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ps2) + basic_machine=i386-ibm + ;; + rm[46]00) + basic_machine=mips-siemens + ;; + rtpc | rtpc-*) + basic_machine=romp-ibm + ;; + sequent) + basic_machine=i386-sequent + ;; + sh) + basic_machine=sh-hitachi + os=-hms + ;; + sps7) + basic_machine=m68k-bull + os=-sysv2 + ;; + spur) + basic_machine=spur-unknown + ;; + sun2) + basic_machine=m68000-sun + ;; + sun2os3) + basic_machine=m68000-sun + os=-sunos3 + ;; + sun2os4) + basic_machine=m68000-sun + os=-sunos4 + ;; + sun3os3) + basic_machine=m68k-sun + os=-sunos3 + ;; + sun3os4) + basic_machine=m68k-sun + os=-sunos4 + ;; + sun4os3) + basic_machine=sparc-sun + os=-sunos3 + ;; + sun4os4) + basic_machine=sparc-sun + os=-sunos4 + ;; + sun4sol2) + basic_machine=sparc-sun + os=-solaris2 + ;; + sun3 | sun3-*) + basic_machine=m68k-sun + ;; + sun4) + basic_machine=sparc-sun + ;; + sun386 | sun386i | roadrunner) + basic_machine=i386-sun + ;; + symmetry) + basic_machine=i386-sequent + os=-dynix + ;; + tx39) + basic_machine=mipstx39-unknown + ;; + tx39el) + basic_machine=mipstx39el-unknown + ;; + tower | tower-32) + basic_machine=m68k-ncr + ;; + udi29k) + basic_machine=a29k-amd + os=-udi + ;; + ultra3) + basic_machine=a29k-nyu + os=-sym1 + ;; + vaxv) + basic_machine=vax-dec + os=-sysv + ;; + vms) + basic_machine=vax-dec + os=-vms + ;; + vpp*|vx|vx-*) + basic_machine=f301-fujitsu + ;; + vxworks960) + basic_machine=i960-wrs + os=-vxworks + ;; + vxworks68) + basic_machine=m68k-wrs + os=-vxworks + ;; + vxworks29k) + basic_machine=a29k-wrs + os=-vxworks + ;; + xmp) + basic_machine=xmp-cray + os=-unicos + ;; + xps | xps100) + basic_machine=xps100-honeywell + ;; + none) + basic_machine=none-none + os=-none + ;; + +# Here we handle the default manufacturer of certain CPU types. It is in +# some cases the only manufacturer, in others, it is the most popular. + mips) + if [ x$os = x-linux-gnu ]; then + basic_machine=mips-unknown + else + basic_machine=mips-mips + fi + ;; + romp) + basic_machine=romp-ibm + ;; + rs6000) + basic_machine=rs6000-ibm + ;; + vax) + basic_machine=vax-dec + ;; + pdp11) + basic_machine=pdp11-dec + ;; + we32k) + basic_machine=we32k-att + ;; + sparc) + basic_machine=sparc-sun + ;; + cydra) + basic_machine=cydra-cydrome + ;; + orion) + basic_machine=orion-highlevel + ;; + orion105) + basic_machine=clipper-highlevel + ;; + *) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; +esac + +# Here we canonicalize certain aliases for manufacturers. +case $basic_machine in + *-digital*) + basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` + ;; + *-commodore*) + basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` + ;; + *) + ;; +esac + +# Decode manufacturer-specific aliases for certain operating systems. + +if [ x"$os" != x"" ] +then +case $os in + # First match some system type aliases + # that might get confused with valid system types. + # -solaris* is a basic system type, with this one exception. + -solaris1 | -solaris1.*) + os=`echo $os | sed -e 's|solaris1|sunos4|'` + ;; + -solaris) + os=-solaris2 + ;; + -svr4*) + os=-sysv4 + ;; + -unixware*) + os=-sysv4.2uw + ;; + -gnu/linux*) + os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` + ;; + # First accept the basic system types. + # The portable systems comes first. + # Each alternative MUST END IN A *, to match a version number. + # -sysv* is not here because it comes later, after sysvr4. + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ + | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ + | -aos* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -netbsd* | -openbsd* | -freebsd* | -riscix* \ + | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -cygwin32* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ + | -mingw32* | -linux-gnu* | -uxpv* | -beos* ) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -linux*) + os=`echo $os | sed -e 's|linux|linux-gnu|'` + ;; + -sunos5*) + os=`echo $os | sed -e 's|sunos5|solaris2|'` + ;; + -sunos6*) + os=`echo $os | sed -e 's|sunos6|solaris3|'` + ;; + -osfrose*) + os=-osfrose + ;; + -osf*) + os=-osf + ;; + -utek*) + os=-bsd + ;; + -dynix*) + os=-bsd + ;; + -acis*) + os=-aos + ;; + -ctix* | -uts*) + os=-sysv + ;; + -ns2 ) + os=-nextstep2 + ;; + # Preserve the version number of sinix5. + -sinix5.*) + os=`echo $os | sed -e 's|sinix|sysv|'` + ;; + -sinix*) + os=-sysv4 + ;; + -triton*) + os=-sysv3 + ;; + -oss*) + os=-sysv3 + ;; + -svr4) + os=-sysv4 + ;; + -svr3) + os=-sysv3 + ;; + -sysvr4) + os=-sysv4 + ;; + # This must come after -sysvr4. + -sysv*) + ;; + -xenix) + os=-xenix + ;; + -none) + ;; + *) + # Get rid of the `-' at the beginning of $os. + os=`echo $os | sed 's/[^-]*-//'` + echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 + exit 1 + ;; +esac +else + +# Here we handle the default operating systems that come with various machines. +# The value should be what the vendor currently ships out the door with their +# machine or put another way, the most popular os provided with the machine. + +# Note that if you're going to try to match "-MANUFACTURER" here (say, +# "-sun"), then you have to tell the case statement up towards the top +# that MANUFACTURER isn't an operating system. Otherwise, code above +# will signal an error saying that MANUFACTURER isn't an operating +# system, and we'll never get to this point. + +case $basic_machine in + *-acorn) + os=-riscix1.2 + ;; + arm*-semi) + os=-aout + ;; + pdp11-*) + os=-none + ;; + *-dec | vax-*) + os=-ultrix4.2 + ;; + m68*-apollo) + os=-domain + ;; + i386-sun) + os=-sunos4.0.2 + ;; + m68000-sun) + os=-sunos3 + # This also exists in the configure program, but was not the + # default. + # os=-sunos4 + ;; + *-tti) # must be before sparc entry or we get the wrong os. + os=-sysv3 + ;; + sparc-* | *-sun) + os=-sunos4.1.1 + ;; + *-ibm) + os=-aix + ;; + *-hp) + os=-hpux + ;; + *-hitachi) + os=-hiux + ;; + i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) + os=-sysv + ;; + *-cbm) + os=-amigaos + ;; + *-dg) + os=-dgux + ;; + *-dolphin) + os=-sysv3 + ;; + m68k-ccur) + os=-rtu + ;; + m88k-omron*) + os=-luna + ;; + *-next ) + os=-nextstep + ;; + *-sequent) + os=-ptx + ;; + *-crds) + os=-unos + ;; + *-ns) + os=-genix + ;; + i370-*) + os=-mvs + ;; + *-next) + os=-nextstep3 + ;; + *-gould) + os=-sysv + ;; + *-highlevel) + os=-bsd + ;; + *-encore) + os=-bsd + ;; + *-sgi) + os=-irix + ;; + *-siemens) + os=-sysv4 + ;; + *-masscomp) + os=-rtu + ;; + f301-fujitsu) + os=-uxpv + ;; + *-be) + os=-beos + ;; + *) + os=-none + ;; +esac +fi + +# Here we handle the case where we know the os, and the CPU type, but not the +# manufacturer. We pick the logical manufacturer. +vendor=unknown +case $basic_machine in + *-unknown) + case $os in + -riscix*) + vendor=acorn + ;; + -sunos*) + vendor=sun + ;; + -aix*) + vendor=ibm + ;; + -hpux*) + vendor=hp + ;; + -hiux*) + vendor=hitachi + ;; + -unos*) + vendor=crds + ;; + -dgux*) + vendor=dg + ;; + -luna*) + vendor=omron + ;; + -genix*) + vendor=ns + ;; + -mvs*) + vendor=ibm + ;; + -ptx*) + vendor=sequent + ;; + -vxsim* | -vxworks*) + vendor=wrs + ;; + -aux*) + vendor=apple + ;; + -beos*) + vendor=be + ;; + esac + basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` + ;; +esac + +echo $basic_machine$os diff --git a/contrib/gcc/config/alpha/elf.h b/contrib/gcc/config/alpha/elf.h index 24af9d3d0313..a226a6a460f5 100644 --- a/contrib/gcc/config/alpha/elf.h +++ b/contrib/gcc/config/alpha/elf.h @@ -19,7 +19,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/alpha/elf.h,v 1.3 1999/10/16 08:13:35 obrien Exp $ */ #undef OBJECT_FORMAT_COFF #undef EXTENDED_COFF diff --git a/contrib/gcc/config/alpha/freebsd.h b/contrib/gcc/config/alpha/freebsd.h index da88be23c7fe..2d977f07fb43 100644 --- a/contrib/gcc/config/alpha/freebsd.h +++ b/contrib/gcc/config/alpha/freebsd.h @@ -22,7 +22,7 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ This was taken from the NetBSD configuration, and modified for FreeBSD/Alpha by Hidetoshi Shimokawa <simokawa@FreeBSD.ORG> */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/alpha/freebsd.h,v 1.9.2.1 2000/07/04 05:51:04 obrien Exp $ */ /* Names to predefine in the preprocessor for this target machine. diff --git a/contrib/gcc/config/alpha/gdb-osf12.h b/contrib/gcc/config/alpha/gdb-osf12.h new file mode 100644 index 000000000000..98c289714017 --- /dev/null +++ b/contrib/gcc/config/alpha/gdb-osf12.h @@ -0,0 +1,26 @@ +/* Definitions of target machine for GNU compiler, for DEC Alpha, using + encapsulated stabs and OSF V1.2. + Copyright (C) 1994 Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "alpha/osf12.h" + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG diff --git a/contrib/gcc/config/alpha/gdb-osf2.h b/contrib/gcc/config/alpha/gdb-osf2.h new file mode 100644 index 000000000000..5ddb7981b34d --- /dev/null +++ b/contrib/gcc/config/alpha/gdb-osf2.h @@ -0,0 +1,26 @@ +/* Definitions of target machine for GNU compiler, for DEC Alpha, using + encapsulated stabs. + Copyright (C) 1992, 1993 Free Software Foundation, Inc. + Contributed by Peter Schauer (pes@regent.e-technik.tu-muenchen.de). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "alpha/osf2.h" + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG diff --git a/contrib/gcc/config/alpha/gdb.h b/contrib/gcc/config/alpha/gdb.h new file mode 100644 index 000000000000..ecdbe40a9a45 --- /dev/null +++ b/contrib/gcc/config/alpha/gdb.h @@ -0,0 +1,26 @@ +/* Definitions of target machine for GNU compiler, for DEC Alpha, using + encapsulated stabs. + Copyright (C) 1992, 1993 Free Software Foundation, Inc. + Contributed by Peter Schauer (pes@regent.e-technik.tu-muenchen.de). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "alpha/alpha.h" + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG diff --git a/contrib/gcc/config/alpha/osf2.h b/contrib/gcc/config/alpha/osf2.h new file mode 100644 index 000000000000..169af5a01c97 --- /dev/null +++ b/contrib/gcc/config/alpha/osf2.h @@ -0,0 +1,32 @@ +/* Definitions of target machine for GNU compiler, for DEC Alpha. + Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +#include "alpha/alpha.h" + +/* In OSF 2.0, the size of wchar_t was changed from short unsigned + to unsigned int. */ + +#undef WCHAR_TYPE +#define WCHAR_TYPE "unsigned int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 32 diff --git a/contrib/gcc/config/freebsd.h b/contrib/gcc/config/freebsd.h index 07bfb7f558c6..8328fd44507c 100644 --- a/contrib/gcc/config/freebsd.h +++ b/contrib/gcc/config/freebsd.h @@ -25,7 +25,7 @@ Boston, MA 02111-1307, USA. */ /usr/src/contrib/gcc/config/svr4.h & egcs/gcc/config/i386/freebsd-elf.h version by David O'Brien */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/freebsd.h,v 1.25.2.3 2000/07/19 00:30:53 obrien Exp $ */ /* Cpp, assembler, linker, library, and startfile spec's. */ diff --git a/contrib/gcc/config/i386/cygwin32.asm b/contrib/gcc/config/i386/cygwin32.asm new file mode 100644 index 000000000000..4ac4c91a3b18 --- /dev/null +++ b/contrib/gcc/config/i386/cygwin32.asm @@ -0,0 +1,32 @@ +/* stuff needed for libgcc1 on win32. */ + +#ifdef L_chkstk + + .global ___chkstk + .global __alloca +___chkstk: +__alloca: + pushl %ecx /* save temp */ + movl %esp,%ecx /* get sp */ + addl $0x8,%ecx /* and point to return addr */ + +probe: cmpl $0x1000,%eax /* > 4k ?*/ + jb done + + subl $0x1000,%ecx /* yes, move pointer down 4k*/ + orl $0x0,(%ecx) /* probe there */ + subl $0x1000,%eax /* decrement count */ + jmp probe /* and do it again */ + +done: subl %eax,%ecx + orl $0x0,(%ecx) /* less that 4k, just peek here */ + + movl %esp,%eax + movl %ecx,%esp /* decrement stack */ + + movl (%eax),%ecx /* recover saved temp */ + movl 4(%eax),%eax /* get return address */ + jmp *%eax + + +#endif diff --git a/contrib/gcc/config/i386/cygwin32.h b/contrib/gcc/config/i386/cygwin32.h new file mode 100644 index 000000000000..3fe7df9f1536 --- /dev/null +++ b/contrib/gcc/config/i386/cygwin32.h @@ -0,0 +1,453 @@ +/* Operating system specific defines to be used when targeting GCC for + hosting on Windows NT 3.x, using a Unix style C library and tools, + as distinct from winnt.h, which is used to build GCC for use with a + windows style library and tool set and uses the Microsoft tools. + Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define YES_UNDERSCORES + +#define DBX_DEBUGGING_INFO +#define SDB_DEBUGGING_INFO +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "i386/gas.h" +#include "dbxcoff.h" + +/* Support the __declspec keyword by turning them into attributes. + We currently only support: dllimport and dllexport. + Note that the current way we do this may result in a collision with + predefined attributes later on. This can be solved by using one attribute, + say __declspec__, and passing args to it. The problem with that approach + is that args are not accumulated: each new appearance would clobber any + existing args. */ + +#ifdef CPP_PREDEFINES +#undef CPP_PREDEFINES +#endif + +#define CPP_PREDEFINES "-Di386 -D_WIN32 \ + -D__CYGWIN32__ -DWINNT -D_X86_=1 -D__STDC__=1\ + -D__stdcall=__attribute__((__stdcall__)) \ + -D__cdecl=__attribute__((__cdecl__)) \ + -D__declspec(x)=__attribute__((x)) \ + -Asystem(winnt) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC "-remap %(cpp_cpu) %{posix:-D_POSIX_SOURCE}" + +/* We have to dynamic link to get to the system DLLs. All of libc, libm and + the Unix stuff is in cygwin.dll. The import library is called + 'libcygwin.a'. For Windows applications, include more libraries, but + always include kernel32. We'd like to specific subsystem windows to + ld, but that doesn't work just yet. */ + +#undef LIB_SPEC +#define LIB_SPEC "-lcygwin %{mwindows:-luser32 -lgdi32 -lcomdlg32} -lkernel32 \ + -ladvapi32 -lshell32" + +#define LINK_SPEC "%{mwindows:--subsystem windows}" + +/* Normally, -lgcc is not needed since everything in it is in the DLL, but we + want to allow things to be added to it when installing new versions of + GCC without making a new CYGWIN.DLL, so we leave it. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "crt0%O%s" + +#define SIZE_TYPE "unsigned int" +#define PTRDIFF_TYPE "int" +#define WCHAR_UNSIGNED 1 +#define WCHAR_TYPE_SIZE 16 +#define WCHAR_TYPE "short unsigned int" +#define HAVE_ATEXIT 1 + + +/* Ignore dllimport for functions. */ +#define TARGET_NOP_FUN_DLLIMPORT (target_flags & 0x20000) + +#undef SUBTARGET_SWITCHES +#define SUBTARGET_SWITCHES \ + { "nop-fun-dllimport", 0x20000 }, \ + { "no-nop-fun-dllimport", -0x20000 }, \ + { "windows", 0x0 }, + +/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS + is a valid machine specific attribute for DECL. + The attributes in ATTRIBUTES have previously been assigned to DECL. */ +extern int i386_pe_valid_decl_attribute_p (); + +#undef VALID_MACHINE_DECL_ATTRIBUTE +#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \ + i386_pe_valid_decl_attribute_p (DECL, ATTRIBUTES, IDENTIFIER, ARGS) + +/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS + is a valid machine specific attribute for TYPE. + The attributes in ATTRIBUTES have previously been assigned to TYPE. */ + +#undef VALID_MACHINE_TYPE_ATTRIBUTE +#define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, IDENTIFIER, ARGS) \ + i386_pe_valid_type_attribute_p (TYPE, ATTRIBUTES, IDENTIFIER, ARGS) +extern int i386_pe_valid_type_attribute_p (); + +extern union tree_node *i386_pe_merge_decl_attributes (); +#define MERGE_MACHINE_DECL_ATTRIBUTES(OLD, NEW) \ + i386_pe_merge_decl_attributes ((OLD), (NEW)) + +/* Used to implement dllexport overriding dllimport semantics. It's also used + to handle vtables - the first pass won't do anything because + DECL_CONTEXT (DECL) will be 0 so i386_pe_dll{ex,im}port_p will return 0. + It's also used to handle dllimport override semantics. */ +#if 0 +#define REDO_SECTION_INFO_P(DECL) \ + ((DECL_MACHINE_ATTRIBUTES (DECL) != NULL_TREE) \ + || (TREE_CODE (DECL) == VAR_DECL && DECL_VIRTUAL_P (DECL))) +#else +#define REDO_SECTION_INFO_P(DECL) 1 +#endif + + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_ctor, in_dtor, in_drectve + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CTOR_SECTION_FUNCTION \ + DTOR_SECTION_FUNCTION \ + DRECTVE_SECTION_FUNCTION \ + SWITCH_TO_SECTION_FUNCTION + +#define CTOR_SECTION_FUNCTION \ +void \ +ctor_section () \ +{ \ + if (in_section != in_ctor) \ + { \ + fprintf (asm_out_file, "\t.section .ctor\n"); \ + in_section = in_ctor; \ + } \ +} + +#define DTOR_SECTION_FUNCTION \ +void \ +dtor_section () \ +{ \ + if (in_section != in_dtor) \ + { \ + fprintf (asm_out_file, "\t.section .dtor\n"); \ + in_section = in_dtor; \ + } \ +} + +#define DRECTVE_SECTION_FUNCTION \ +void \ +drectve_section () \ +{ \ + if (in_section != in_drectve) \ + { \ + fprintf (asm_out_file, "%s\n", "\t.section .drectve\n"); \ + in_section = in_drectve; \ + } \ +} + +/* Switch to SECTION (an `enum in_section'). + + ??? This facility should be provided by GCC proper. + The problem is that we want to temporarily switch sections in + ASM_DECLARE_OBJECT_NAME and then switch back to the original section + afterwards. */ +#define SWITCH_TO_SECTION_FUNCTION \ +void \ +switch_to_section (section, decl) \ + enum in_section section; \ + tree decl; \ +{ \ + switch (section) \ + { \ + case in_text: text_section (); break; \ + case in_data: data_section (); break; \ + case in_named: named_section (decl, NULL, 0); break; \ + case in_ctor: ctor_section (); break; \ + case in_dtor: dtor_section (); break; \ + case in_drectve: drectve_section (); break; \ + default: abort (); break; \ + } \ +} + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + On i386 running Windows NT, modify the assembler name with a suffix + consisting of an atsign (@) followed by string of digits that represents + the number of bytes of arguments passed to the function, if it has the + attribute STDCALL. + + In addition, we must mark dll symbols specially. Definitions of + dllexport'd objects install some info in the .drectve section. + References to dllimport'd objects are fetched indirectly via + _imp__. If both are declared, dllexport overrides. This is also + needed to implement one-only vtables: they go into their own + section and we need to set DECL_SECTION_NAME so we do that here. + Note that we can be called twice on the same decl. */ + +extern void i386_pe_encode_section_info (); + +#ifdef ENCODE_SECTION_INFO +#undef ENCODE_SECTION_INFO +#endif +#define ENCODE_SECTION_INFO(DECL) i386_pe_encode_section_info (DECL) + +/* Utility used only in this file. */ +#define I386_PE_STRIP_ENCODING(SYM_NAME) \ + ((SYM_NAME) + ((SYM_NAME)[0] == '@' ? 3 : 0)) + +/* This macro gets just the user-specified name + out of the string in a SYMBOL_REF. Discard + trailing @[NUM] encoded by ENCODE_SECTION_INFO. */ +#undef STRIP_NAME_ENCODING +#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \ +do { \ + char *_p; \ + char *_name = I386_PE_STRIP_ENCODING (SYMBOL_NAME); \ + for (_p = _name; *_p && *_p != '@'; ++_p) \ + ; \ + if (*_p == '@') \ + { \ + int _len = _p - _name; \ + (VAR) = (char *) alloca (_len + 1); \ + strncpy ((VAR), _name, _len); \ + (VAR)[_len] = '\0'; \ + } \ + else \ + (VAR) = _name; \ +} while (0) + + +/* Output a reference to a label. */ +#undef ASM_OUTPUT_LABELREF +#define ASM_OUTPUT_LABELREF(STREAM, NAME) \ + fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, \ + I386_PE_STRIP_ENCODING (NAME)) \ + +/* Output a common block. */ +#undef ASM_OUTPUT_COMMON +#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ +do { \ + if (i386_pe_dllexport_name_p (NAME)) \ + { \ + drectve_section (); \ + fprintf ((STREAM), "\t.ascii \" -export:%s\"\n", \ + I386_PE_STRIP_ENCODING (NAME)); \ + } \ + if (! i386_pe_dllimport_name_p (NAME)) \ + { \ + fprintf ((STREAM), "\t.comm\t"); \ + assemble_name ((STREAM), (NAME)); \ + fprintf ((STREAM), ", %d\t%s %d\n", \ + (ROUNDED), ASM_COMMENT_START, (SIZE)); \ + } \ +} while (0) + +/* Output the label for an initialized variable. */ +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ +do { \ + if (i386_pe_dllexport_name_p (NAME)) \ + { \ + enum in_section save_section = in_section; \ + drectve_section (); \ + fprintf ((STREAM), "\t.ascii \" -export:%s\"\n", \ + I386_PE_STRIP_ENCODING (NAME)); \ + switch_to_section (save_section, (DECL)); \ + } \ + ASM_OUTPUT_LABEL ((STREAM), (NAME)); \ +} while (0) + + +/* Emit code to check the stack when allocating more that 4000 + bytes in one go. */ + +#define CHECK_STACK_LIMIT 4000 + +/* By default, target has a 80387, uses IEEE compatible arithmetic, + and returns float values in the 387 and needs stack probes */ +#undef TARGET_DEFAULT + +#define TARGET_DEFAULT \ + (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_STACK_PROBE) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#undef ASM_OUTPUT_ALIGN +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) + +/* Define this macro if in some cases global symbols from one translation + unit may not be bound to undefined symbols in another translation unit + without user intervention. For instance, under Microsoft Windows + symbols must be explicitly imported from shared libraries (DLLs). */ +#define MULTIPLE_SYMBOL_SPACES + +#define UNIQUE_SECTION_P(DECL) DECL_ONE_ONLY (DECL) +extern void i386_pe_unique_section (); +#define UNIQUE_SECTION(DECL,RELOC) i386_pe_unique_section (DECL, RELOC) + +#define SUPPORTS_ONE_ONLY 1 + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. Some target formats do not support arbitrary sections. Do not + define this macro in such cases. */ +#undef ASM_OUTPUT_SECTION_NAME +#define ASM_OUTPUT_SECTION_NAME(STREAM, DECL, NAME, RELOC) \ +do { \ + static struct section_info \ + { \ + struct section_info *next; \ + char *name; \ + enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type; \ + } *sections; \ + struct section_info *s; \ + char *mode; \ + enum sect_enum type; \ + \ + for (s = sections; s; s = s->next) \ + if (!strcmp (NAME, s->name)) \ + break; \ + \ + if (DECL && TREE_CODE (DECL) == FUNCTION_DECL) \ + type = SECT_EXEC, mode = "x"; \ + else if (DECL && DECL_READONLY_SECTION (DECL, RELOC)) \ + type = SECT_RO, mode = ""; \ + else \ + type = SECT_RW, mode = "w"; \ + \ + if (s == 0) \ + { \ + s = (struct section_info *) xmalloc (sizeof (struct section_info)); \ + s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME)); \ + strcpy (s->name, NAME); \ + s->type = type; \ + s->next = sections; \ + sections = s; \ + fprintf (STREAM, ".section\t%s,\"%s\"\n", NAME, mode); \ + /* Functions may have been compiled at various levels of \ + optimization so we can't use `same_size' here. Instead, \ + have the linker pick one. */ \ + if ((DECL) && DECL_ONE_ONLY (DECL)) \ + fprintf (STREAM, "\t.linkonce %s\n", \ + TREE_CODE (DECL) == FUNCTION_DECL \ + ? "discard" : "same_size"); \ + } \ + else \ + { \ + fprintf (STREAM, ".section\t%s,\"%s\"\n", NAME, mode); \ + } \ +} while (0) + +/* Write the extra assembler code needed to declare a function + properly. If we are generating SDB debugging information, this + will happen automatically, so we only need to handle other cases. */ +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ + do \ + { \ + if (i386_pe_dllexport_name_p (NAME)) \ + { \ + drectve_section (); \ + fprintf ((FILE), "\t.ascii \" -export:%s\"\n", \ + I386_PE_STRIP_ENCODING (NAME)); \ + function_section (DECL); \ + } \ + if (write_symbols != SDB_DEBUG) \ + i386_pe_declare_function_type (FILE, NAME, TREE_PUBLIC (DECL)); \ + ASM_OUTPUT_LABEL (FILE, NAME); \ + } \ + while (0) + +/* Add an external function to the list of functions to be declared at + the end of the file. */ +#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ + do \ + { \ + if (TREE_CODE (DECL) == FUNCTION_DECL) \ + i386_pe_record_external_function (NAME); \ + } \ + while (0) + +/* Declare the type properly for any external libcall. */ +#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ + i386_pe_declare_function_type (FILE, XSTR (FUN, 0), 1) + +/* Output function declarations at the end of the file. */ +#define ASM_FILE_END(FILE) \ + i386_pe_asm_file_end (FILE) + +#undef ASM_COMMENT_START +#define ASM_COMMENT_START " #" + +/* DWARF2 Unwinding doesn't work with exception handling yet. */ +#define DWARF2_UNWIND_INFO 0 + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +/* External function declarations. */ + +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif + +#ifdef BUFSIZ /* stdio.h has been included, ok to use FILE * */ +#define STDIO_PROTO(ARGS) PROTO(ARGS) +#else +#define STDIO_PROTO(ARGS) () +#endif + +extern void i386_pe_record_external_function PROTO((char *)); +extern void i386_pe_declare_function_type STDIO_PROTO((FILE *, char *, int)); +extern void i386_pe_asm_file_end STDIO_PROTO((FILE *)); + +/* For Win32 ABI compatibility */ +#undef DEFAULT_PCC_STRUCT_RETURN +#define DEFAULT_PCC_STRUCT_RETURN 0 + diff --git a/contrib/gcc/config/i386/freebsd.h b/contrib/gcc/config/i386/freebsd.h index d4a03586532f..b538465e8326 100644 --- a/contrib/gcc/config/i386/freebsd.h +++ b/contrib/gcc/config/i386/freebsd.h @@ -23,7 +23,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/i386/freebsd.h,v 1.34.2.1 2000/07/04 05:51:05 obrien Exp $ */ #undef CPP_PREDEFINES #define CPP_PREDEFINES \ diff --git a/contrib/gcc/config/i386/freebsd.h.fixed b/contrib/gcc/config/i386/freebsd.h.fixed deleted file mode 100644 index d4a03586532f..000000000000 --- a/contrib/gcc/config/i386/freebsd.h.fixed +++ /dev/null @@ -1,692 +0,0 @@ -/* Definitions for Intel 386 running FreeBSD with either a.out or ELF format - Copyright (C) 1996-2000 Free Software Foundation, Inc. - Contributed by Eric Youngdale. - Modified for stabs-in-ELF by H.J. Lu. - Adapted from GNU/Linux version by John Polstra. - Added support for generating "old a.out gas" on the fly by Peter Wemm. - Continued development by David O'Brien <obrien@freebsd.org> - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* $FreeBSD$ */ - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-Di386 -Acpu(i386) -Amachine(i386)" \ - FBSD_CPP_PREDEFINES - -#undef CC1_SPEC -#define CC1_SPEC "\ - %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ - %{maout: %{!mno-underscores: %{!munderscores: -munderscores }}}" - -#undef ASM_SPEC -#define ASM_SPEC "%{v*: -v} %{maout: %{fpic:-k} %{fPIC:-k}}" - -#undef ASM_FINAL_SPEC -#define ASM_FINAL_SPEC "%|" - -/* Provide a LINK_SPEC appropriate for FreeBSD. Here we provide support - for the special GCC options -static and -shared, which allow us to - link things in one of these three modes by applying the appropriate - combinations of options at link-time. We like to support here for - as many of the other GNU linker options as possible. But I don't - have the time to search for those flags. I am sure how to add - support for -soname shared_object_name. H.J. - - I took out %{v:%{!V:-V}}. It is too much :-(. They can use - -Wl,-V. - - When the -shared link option is used a final link is not being - done. */ - -#undef LINK_SPEC -#define LINK_SPEC "\ - %{p:%e`-p' not supported; use `-pg' and gprof(1)} \ - %{maout: %{shared:-Bshareable} \ - %{!shared:%{!nostdlib:%{!r:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} \ - %{pg:-Bstatic} %{Z}} \ - %{assert*} %{R*}} \ - %{!maout: \ - -m elf_i386 \ - %{Wl,*:%*} \ - %{assert*} %{R*} %{rpath*} %{defsym*} \ - %{shared:-Bshareable %{h*} %{soname*}} \ - %{symbolic:-Bsymbolic} \ - %{!shared: \ - %{!static: \ - %{rdynamic: -export-dynamic} \ - %{!dynamic-linker: -dynamic-linker /usr/libexec/ld-elf.so.1}} \ - %{static:-Bstatic}}}" - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "\ - %{maout: %{shared:c++rt0.o%s} \ - %{!shared: \ - %{pg:gcrt0.o%s}%{!pg: \ - %{static:scrt0.o%s} \ - %{!static:crt0.o%s}}}} \ - %{!maout: \ - %{!shared: \ - %{pg:gcrt1.o%s} \ - %{!pg: \ - %{p:gcrt1.o%s} \ - %{!p:crt1.o%s}}} \ - crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" - -/* Provide an ENDFILE_SPEC appropriate for FreeBSD/i386. Here we tack on our - own magical crtend.o file (compare w/crtstuff.c) which provides part of the - support for getting C++ file-scope static object constructed before - entering `main', followed by the normal "finalizer" file, `crtn.o'. */ - -#undef ENDFILE_SPEC -#define ENDFILE_SPEC "\ - %{!maout: \ - %{!shared:crtend.o%s} \ - %{shared:crtendS.o%s} crtn.o%s}" - - -/************************[ Target stuff ]***********************************/ - -/* Define the actual types of some ANSI-mandated types. - Needs to agree with <machine/ansi.h>. GCC defaults come from c-decl.c, - c-common.c, and config/<arch>/<arch>.h. */ - -#undef SIZE_TYPE -#define SIZE_TYPE "unsigned int" - -#undef PTRDIFF_TYPE -#define PTRDIFF_TYPE "int" - -/* This is the pseudo-op used to generate a 32-bit word of data with a - specific value in some section. */ - -#undef INT_ASM_OP -#define INT_ASM_OP ".long" - -/* Biggest alignment supported by the object file format of this - machine. Use this macro to limit the alignment which can be - specified using the `__attribute__ ((aligned (N)))' construct. If - not defined, the default value is `BIGGEST_ALIGNMENT'. */ - -#define MAX_OFILE_ALIGNMENT (32768*8) - -#undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (i386 FreeBSD/ELF)"); - -#define MASK_PROFILER_EPILOGUE 010000000000 -#define MASK_AOUT 004000000000 /* a.out not elf */ -#define MASK_UNDERSCORES 002000000000 /* use leading _ */ - -#define TARGET_PROFILER_EPILOGUE (target_flags & MASK_PROFILER_EPILOGUE) -#define TARGET_AOUT (target_flags & MASK_AOUT) -#define TARGET_ELF ((target_flags & MASK_AOUT) == 0) -#define TARGET_UNDERSCORES ((target_flags & MASK_UNDERSCORES) != 0) - -#undef SUBTARGET_SWITCHES -#define SUBTARGET_SWITCHES \ - { "profiler-epilogue", MASK_PROFILER_EPILOGUE}, \ - { "no-profiler-epilogue", -MASK_PROFILER_EPILOGUE}, \ - { "aout", MASK_AOUT}, \ - { "no-aout", -MASK_AOUT}, \ - { "underscores", MASK_UNDERSCORES}, \ - { "no-underscores", -MASK_UNDERSCORES}, - -/* This goes away when the math emulator is fixed. */ -#undef TARGET_DEFAULT -#define TARGET_DEFAULT \ - (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS | MASK_NO_FANCY_MATH_387) - -/* Prefix for internally generated assembler labels. If we aren't using - underscores, we are using prefix `.'s to identify labels that should - be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ -#undef LPREFIX -#define LPREFIX ((TARGET_UNDERSCORES) ? "L" : ".L") - -/* The a.out tools do not support "linkonce" sections. */ -#undef SUPPORTS_ONE_ONLY -#define SUPPORTS_ONE_ONLY TARGET_ELF - -/* Enable alias attribute support. */ -#undef SET_ASM_OP -#define SET_ASM_OP ".set" - -/* The a.out tools do not support "Lscope" .stabs symbols. */ -#undef NO_DBX_FUNCTION_END -#define NO_DBX_FUNCTION_END TARGET_AOUT - -/* In ELF, the function stabs come first, before the relative offsets. */ -#undef DBX_FUNCTION_FIRST -#define DBX_CHECK_FUNCTION_FIRST TARGET_ELF - -/* supply our own hook for calling __main() from main() */ -#undef INVOKE__main -#define INVOKE__main -#undef GEN_CALL__MAIN -#define GEN_CALL__MAIN \ - do { \ - if (!(TARGET_ELF)) \ - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, NAME__MAIN), 0, \ - VOIDmode, 0); \ - } while (0) - -/* Indicate that jump tables go in the text section. This is - necessary when compiling PIC code. */ -#undef JUMP_TABLES_IN_TEXT_SECTION -#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) - -/* override the exception table positioning */ -#undef EXCEPTION_SECTION -#define EXCEPTION_SECTION() \ - do { \ - if (TARGET_ELF) \ - { \ - named_section (NULL_TREE, ".gcc_except_table", 0); \ - } \ - else \ - { \ - if (flag_pic) \ - data_section (); \ - else \ - readonly_data_section (); \ - } \ - } while (0); - -/* Tell final.c that we don't need a label passed to mcount. */ -#undef NO_PROFILE_DATA -#define NO_PROFILE_DATA - -/* Output assembler code to FILE to begin profiling of the current function. - LABELNO is an optional label. */ - -#undef FUNCTION_PROFILER -#define FUNCTION_PROFILER(FILE, LABELNO) \ - do { \ - char *_name = TARGET_AOUT ? "mcount" : ".mcount"; \ - if (flag_pic) \ - fprintf ((FILE), "\tcall *%s@GOT(%%ebx)\n", _name); \ - else \ - fprintf ((FILE), "\tcall %s\n", _name); \ - } while (0) - -/* Output assembler code to FILE to end profiling of the current function. */ - -#undef FUNCTION_PROFILER_EPILOGUE -#define FUNCTION_PROFILER_EPILOGUE(FILE, DO_RTL) \ - do { \ - if (TARGET_PROFILER_EPILOGUE) \ - { \ - if (DO_RTL) \ - { \ - /* ".mexitcount" is specially handled in \ - ASM_HACK_SYMBOLREF () so that we don't need to handle \ - flag_pic or TARGET_AOUT here. */ \ - rtx xop; \ - xop = gen_rtx_MEM (FUNCTION_MODE, \ - gen_rtx_SYMBOL_REF (Pmode, ".mexitcount")); \ - emit_call_insn (gen_rtx (CALL, VOIDmode, xop, const0_rtx)); \ - } \ - else \ - { \ - /* XXX this !DO_RTL case is broken but not actually used. */ \ - char *_name = TARGET_AOUT ? "mcount" : ".mcount"; \ - if (flag_pic) \ - fprintf (FILE, "\tcall *%s@GOT(%%ebx)\n", _name); \ - else \ - fprintf (FILE, "\tcall %s\n", _name); \ - } \ - } \ - } while (0) - - -/************************[ Assembler stuff ]********************************/ - -#undef ASM_APP_ON -#define ASM_APP_ON "#APP\n" - -#undef ASM_APP_OFF -#define ASM_APP_OFF "#NO_APP\n" - -/* This is how to begin an assembly language file. - The .file command should always begin the output. - ELF also needs a .version. */ - -#undef ASM_FILE_START -#define ASM_FILE_START(FILE) \ - do { \ - output_file_directive ((FILE), main_input_filename); \ - if (TARGET_ELF) \ - fprintf ((FILE), "\t.version\t\"01.01\"\n"); \ - } while (0) - -/* This is how to store into the string BUF - the symbol_ref name of an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - This is suitable for output with `assemble_name'. */ -#undef ASM_GENERATE_INTERNAL_LABEL -#define ASM_GENERATE_INTERNAL_LABEL(BUF, PREFIX, NUMBER) \ - sprintf ((BUF), "*%s%s%d", (TARGET_UNDERSCORES) ? "" : ".", \ - (PREFIX), (NUMBER)) - -/* This is how to output an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - For most svr4/ELF systems, the convention is that any symbol which begins - with a period is not put into the linker symbol table by the assembler. */ -#undef ASM_OUTPUT_INTERNAL_LABEL -#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ - fprintf ((FILE), "%s%s%d:\n", (TARGET_UNDERSCORES) ? "" : ".", \ - (PREFIX), (NUM)) - -/* This is how to output a reference to a user-level label named NAME. */ -#undef ASM_OUTPUT_LABELREF -#define ASM_OUTPUT_LABELREF(FILE, NAME) \ - do { \ - char *_name = (NAME); \ - /* Hack to avoid writing lots of rtl in \ - FUNCTION_PROFILER_EPILOGUE (). */ \ - if (*_name == '.' && strcmp(_name + 1, "mexitcount") == 0) \ - { \ - if (TARGET_AOUT) \ - _name++; \ - if (flag_pic) \ - fprintf ((FILE), "*%s@GOT(%%ebx)", _name); \ - else \ - fprintf ((FILE), "%s", _name); \ - } \ - else \ - fprintf (FILE, "%s%s", TARGET_UNDERSCORES ? "_" : "", _name); \ -} while (0) - -/* This is how to hack on the symbol code of certain relcalcitrant - symbols to modify their output in output_pic_addr_const (). */ - -#undef ASM_HACK_SYMBOLREF_CODE -#define ASM_HACK_SYMBOLREF_CODE(NAME, CODE) \ - do { \ - /* Part of hack to avoid writing lots of rtl in \ - FUNCTION_PROFILER_EPILOGUE (). */ \ - char *_name = (NAME); \ - if (*_name == '.' && strcmp(_name + 1, "mexitcount") == 0) \ - (CODE) = 'X'; \ - } while (0) - -/* This is how to output an element of a case-vector that is relative. - This is only used for PIC code. See comments by the `casesi' insn in - i386.md for an explanation of the expression this outputs. */ -#undef ASM_OUTPUT_ADDR_DIFF_ELT -#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ - fprintf ((FILE), "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, (VALUE)) - -#undef ASM_OUTPUT_ALIGN -#define ASM_OUTPUT_ALIGN(FILE, LOG) \ - if ((LOG)!=0) { \ - if (in_text_section()) \ - fprintf ((FILE), "\t.p2align %d,0x90\n", (LOG)); \ - else \ - fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ - } - -#undef ASM_OUTPUT_SOURCE_LINE -#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ - do { \ - static int sym_lineno = 1; \ - if (TARGET_ELF) \ - { \ - fprintf ((FILE), ".stabn 68,0,%d,.LM%d-", (LINE), sym_lineno); \ - assemble_name ((FILE), \ - XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ - fprintf ((FILE), "\n.LM%d:\n", sym_lineno); \ - sym_lineno += 1; \ - } \ - else \ - { \ - fprintf ((FILE), "\t%s %d,0,%d\n", ASM_STABD_OP, N_SLINE, \ - lineno); \ - } \ - } while (0) - -/* These macros generate the special .type and .size directives which - are used to set the corresponding fields of the linker symbol table - entries in an ELF object file under SVR4. These macros also output - the starting labels for the relevant functions/objects. */ - -/* Write the extra assembler code needed to declare a function properly. - Some svr4 assemblers need to also have something extra said about the - function's return value. We allow for that here. */ - -#undef ASM_DECLARE_FUNCTION_NAME -#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ - do { \ - fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ - assemble_name (FILE, NAME); \ - putc (',', FILE); \ - fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ - putc ('\n', FILE); \ - ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ - ASM_OUTPUT_LABEL(FILE, NAME); \ - } while (0) - -/* This is how to declare the size of a function. */ - -#undef ASM_DECLARE_FUNCTION_SIZE -#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ - do { \ - if (!flag_inhibit_size_directive) \ - { \ - char label[256]; \ - static int labelno; \ - labelno++; \ - ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ - ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \ - fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ - assemble_name (FILE, (FNAME)); \ - fprintf (FILE, ","); \ - assemble_name (FILE, label); \ - fprintf (FILE, "-"); \ - assemble_name (FILE, (FNAME)); \ - putc ('\n', FILE); \ - } \ - } while (0) - - -/* The routine used to output NUL terminated strings. We use a special - version of this for most svr4 targets because doing so makes the - generated assembly code more compact (and thus faster to assemble) - as well as more readable, especially for targets like the i386 - (where the only alternative is to output character sequences as - comma separated lists of numbers). */ - -#undef ASM_OUTPUT_LIMITED_STRING -#define ASM_OUTPUT_LIMITED_STRING(FILE, STR) \ - do { \ - register unsigned char *_limited_str = (unsigned char *) (STR); \ - register unsigned ch; \ - fprintf ((FILE), "\t%s\t\"", STRING_ASM_OP); \ - for (; (ch = *_limited_str); _limited_str++) \ - { \ - register int escape; \ - switch (escape = ESCAPES[ch]) \ - { \ - case 0: \ - putc (ch, (FILE)); \ - break; \ - case 1: \ - fprintf ((FILE), "\\%03o", ch); \ - break; \ - default: \ - putc ('\\', (FILE)); \ - putc (escape, (FILE)); \ - break; \ - } \ - } \ - fprintf ((FILE), "\"\n"); \ - } while (0) - -/* Switch into a generic section. - - We make the section read-only and executable for a function decl, - read-only for a const data decl, and writable for a non-const data decl. - - If the section has already been defined, we must not - emit the attributes here. The SVR4 assembler does not - recognize section redefinitions. - If DECL is NULL, no attributes are emitted. */ - -#undef ASM_OUTPUT_SECTION_NAME -#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \ - do { \ - static struct section_info \ - { \ - struct section_info *next; \ - char *name; \ - enum sect_enum {SECT_RW, SECT_RO, SECT_EXEC} type; \ - } *sections; \ - struct section_info *s; \ - char *mode; \ - enum sect_enum type; \ - \ - for (s = sections; s; s = s->next) \ - if (!strcmp (NAME, s->name)) \ - break; \ - \ - if (DECL && TREE_CODE (DECL) == FUNCTION_DECL) \ - type = SECT_EXEC, mode = "ax"; \ - else if (DECL && DECL_READONLY_SECTION (DECL, RELOC)) \ - type = SECT_RO, mode = "a"; \ - else \ - type = SECT_RW, mode = "aw"; \ - \ - if (s == 0) \ - { \ - s = (struct section_info *) xmalloc (sizeof (struct section_info)); \ - s->name = xmalloc ((strlen (NAME) + 1) * sizeof (*NAME)); \ - strcpy (s->name, NAME); \ - s->type = type; \ - s->next = sections; \ - sections = s; \ - fprintf (FILE, ".section\t%s,\"%s\",@progbits\n", NAME, mode); \ - } \ - else \ - { \ - if (DECL && s->type != type) \ - error_with_decl (DECL, "%s causes a section type conflict"); \ - \ - fprintf (FILE, ".section\t%s\n", NAME); \ - } \ - } while (0) - -#undef MAKE_DECL_ONE_ONLY -#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) -#undef UNIQUE_SECTION_P -#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL)) -#undef UNIQUE_SECTION -#define UNIQUE_SECTION(DECL,RELOC) \ - do { \ - int len; \ - char *name, *string, *prefix; \ - \ - name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL)); \ - \ - if (! DECL_ONE_ONLY (DECL)) \ - { \ - prefix = "."; \ - if (TREE_CODE (DECL) == FUNCTION_DECL) \ - prefix = ".text."; \ - else if (DECL_READONLY_SECTION (DECL, RELOC)) \ - prefix = ".rodata."; \ - else \ - prefix = ".data."; \ - } \ - else if (TREE_CODE (DECL) == FUNCTION_DECL) \ - prefix = ".gnu.linkonce.t."; \ - else if (DECL_READONLY_SECTION (DECL, RELOC)) \ - prefix = ".gnu.linkonce.r."; \ - else \ - prefix = ".gnu.linkonce.d."; \ - \ - len = strlen (name) + strlen (prefix); \ - string = alloca (len + 1); \ - sprintf (string, "%s%s", prefix, name); \ - \ - DECL_SECTION_NAME (DECL) = build_string (len, string); \ - } while (0) - -/* A C statement or statements to switch to the appropriate - section for output of DECL. DECL is either a `VAR_DECL' node - or a constant of some sort. RELOC indicates whether forming - the initial value of DECL requires link-time relocations. */ - -#undef SELECT_SECTION -#define SELECT_SECTION(DECL,RELOC) \ - { \ - if (flag_pic && RELOC) \ - data_section (); \ - else if (TREE_CODE (DECL) == STRING_CST) \ - { \ - if (! flag_writable_strings) \ - const_section (); \ - else \ - data_section (); \ - } \ - else if (TREE_CODE (DECL) == VAR_DECL) \ - { \ - if (! DECL_READONLY_SECTION (DECL, RELOC)) \ - data_section (); \ - else \ - const_section (); \ - } \ - else \ - const_section (); \ - } - -/* Define macro used to output shift-double opcodes when the shift - count is in %cl. Some assemblers require %cl as an argument; - some don't. - - *OLD* GAS requires the %cl argument, so override i386/unix.h. */ - -#undef AS3_SHIFT_DOUBLE -#define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) - - -/************************[ Debugger stuff ]*********************************/ - -/* Copy this from the svr4 specifications... */ -/* Define the register numbers to be used in Dwarf debugging information. - The SVR4 reference port C compiler uses the following register numbers - in its Dwarf output code: - 0 for %eax (gnu regno = 0) - 1 for %ecx (gnu regno = 2) - 2 for %edx (gnu regno = 1) - 3 for %ebx (gnu regno = 3) - 4 for %esp (gnu regno = 7) - 5 for %ebp (gnu regno = 6) - 6 for %esi (gnu regno = 4) - 7 for %edi (gnu regno = 5) - The following three DWARF register numbers are never generated by - the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4 - believes these numbers have these meanings. - 8 for %eip (no gnu equivalent) - 9 for %eflags (no gnu equivalent) - 10 for %trapno (no gnu equivalent) - It is not at all clear how we should number the FP stack registers - for the x86 architecture. If the version of SDB on x86/svr4 were - a bit less brain dead with respect to floating-point then we would - have a precedent to follow with respect to DWARF register numbers - for x86 FP registers, but the SDB on x86/svr4 is so completely - broken with respect to FP registers that it is hardly worth thinking - of it as something to strive for compatibility with. - The version of x86/svr4 SDB I have at the moment does (partially) - seem to believe that DWARF register number 11 is associated with - the x86 register %st(0), but that's about all. Higher DWARF - register numbers don't seem to be associated with anything in - particular, and even for DWARF regno 11, SDB only seems to under- - stand that it should say that a variable lives in %st(0) (when - asked via an `=' command) if we said it was in DWARF regno 11, - but SDB still prints garbage when asked for the value of the - variable in question (via a `/' command). - (Also note that the labels SDB prints for various FP stack regs - when doing an `x' command are all wrong.) - Note that these problems generally don't affect the native SVR4 - C compiler because it doesn't allow the use of -O with -g and - because when it is *not* optimizing, it allocates a memory - location for each floating-point variable, and the memory - location is what gets described in the DWARF AT_location - attribute for the variable in question. - Regardless of the severe mental illness of the x86/svr4 SDB, we - do something sensible here and we use the following DWARF - register numbers. Note that these are all stack-top-relative - numbers. - 11 for %st(0) (gnu regno = 8) - 12 for %st(1) (gnu regno = 9) - 13 for %st(2) (gnu regno = 10) - 14 for %st(3) (gnu regno = 11) - 15 for %st(4) (gnu regno = 12) - 16 for %st(5) (gnu regno = 13) - 17 for %st(6) (gnu regno = 14) - 18 for %st(7) (gnu regno = 15) -*/ -#undef DWARF_DBX_REGISTER_NUMBER -#define DWARF_DBX_REGISTER_NUMBER(n) \ -((n) == 0 ? 0 \ - : (n) == 1 ? 2 \ - : (n) == 2 ? 1 \ - : (n) == 3 ? 3 \ - : (n) == 4 ? 6 \ - : (n) == 5 ? 7 \ - : (n) == 6 ? 5 \ - : (n) == 7 ? 4 \ - : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ - : (-1)) - -/* Now what stabs expects in the register. */ -#undef STABS_DBX_REGISTER_NUMBER -#define STABS_DBX_REGISTER_NUMBER(n) \ -((n) == 0 ? 0 : \ - (n) == 1 ? 2 : \ - (n) == 2 ? 1 : \ - (n) == 3 ? 3 : \ - (n) == 4 ? 6 : \ - (n) == 5 ? 7 : \ - (n) == 6 ? 4 : \ - (n) == 7 ? 5 : \ - (n) + 4) - -#undef DBX_REGISTER_NUMBER -#define DBX_REGISTER_NUMBER(n) ((write_symbols == DWARF_DEBUG) \ - ? DWARF_DBX_REGISTER_NUMBER(n) \ - : STABS_DBX_REGISTER_NUMBER(n)) - -/* tag end of file in elf mode */ -#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END -#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME) \ - do { \ - if (TARGET_ELF) { \ - fprintf ((FILE), "\t.text\n\t.stabs \"\",%d,0,0,.Letext\n.Letext:\n", \ - N_SO); \ - } \ - } while (0) - -/* stabs-in-elf has offsets relative to function beginning */ -#undef DBX_OUTPUT_LBRAC -#define DBX_OUTPUT_LBRAC(FILE, NAME) \ - do { \ - fprintf (asmfile, "%s %d,0,0,", ASM_STABN_OP, N_LBRAC); \ - assemble_name (asmfile, buf); \ - if (TARGET_ELF) \ - { \ - fputc ('-', asmfile); \ - assemble_name (asmfile, \ - XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ - } \ - fprintf (asmfile, "\n"); \ - } while (0) - -#undef DBX_OUTPUT_RBRAC -#define DBX_OUTPUT_RBRAC(FILE, NAME) \ - do { \ - fprintf (asmfile, "%s %d,0,0,", ASM_STABN_OP, N_RBRAC); \ - assemble_name (asmfile, buf); \ - if (TARGET_ELF) \ - { \ - fputc ('-', asmfile); \ - assemble_name (asmfile, \ - XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ - } \ - fprintf (asmfile, "\n"); \ - } while (0) diff --git a/contrib/gcc/config/i386/go32-rtems.h b/contrib/gcc/config/i386/go32-rtems.h new file mode 100644 index 000000000000..9ae1998db51d --- /dev/null +++ b/contrib/gcc/config/i386/go32-rtems.h @@ -0,0 +1,40 @@ +/* Configuration for an i386 running RTEMS on top of MS-DOS with + djgpp/go32 v1.x. + + Copyright (C) 1996 Free Software Foundation, Inc. + Contributed by Joel Sherrill (joel@OARcorp.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "i386/go32.h" + +/* Specify predefined symbols in preprocessor. */ + +#ifdef CPP_PREDEFINES +#undef CPP_PREDEFINES +#endif +#define CPP_PREDEFINES "-Dunix -Di386 -DGO32 -DMSDOS -Drtems -D__rtems__ \ + -Asystem(unix) -Asystem(msdos) -Acpu(i386) -Amachine(i386) -Asystem(rtems)" + +/* Generate calls to memcpy, memcmp and memset. */ +#ifndef TARGET_MEM_FUNCTIONS +#define TARGET_MEM_FUNCTIONS +#endif + +/* end of i386/go32-rtems.h */ + diff --git a/contrib/gcc/config/i386/go32.h b/contrib/gcc/config/i386/go32.h new file mode 100644 index 000000000000..dd03cc8a75d1 --- /dev/null +++ b/contrib/gcc/config/i386/go32.h @@ -0,0 +1,96 @@ +/* Configuration for an i386 running MS-DOS with djgpp/go32. */ + +#include "dbxcoff.h" + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +#define HANDLE_SYSV_PRAGMA + +#define YES_UNDERSCORES + +#include "i386/gas.h" + +#ifdef CPP_PREDEFINES +#undef CPP_PREDEFINES +#endif +#define CPP_PREDEFINES "-Dunix -Di386 -DGO32 -DMSDOS \ + -Asystem(unix) -Asystem(msdos) -Acpu(i386) -Amachine(i386)" + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_ctor, in_dtor + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CTOR_SECTION_FUNCTION \ + DTOR_SECTION_FUNCTION + +#define CTOR_SECTION_FUNCTION \ +void \ +ctor_section () \ +{ \ + if (in_section != in_ctor) \ + { \ + fprintf (asm_out_file, "\t.section .ctor\n"); \ + in_section = in_ctor; \ + } \ +} + +#define DTOR_SECTION_FUNCTION \ +void \ +dtor_section () \ +{ \ + if (in_section != in_dtor) \ + { \ + fprintf (asm_out_file, "\t.section .dtor\n"); \ + in_section = in_dtor; \ + } \ +} + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* Allow (eg) __attribute__((section "locked")) to work */ +#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC)\ + do { \ + fprintf (FILE, "\t.section %s\n", NAME); \ + } while (0) + +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* Output at beginning of assembler file. */ +/* The .file command should always begin the output. */ +/* Use the main_input_filename instead of dump_base_name */ + +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + output_file_directive (FILE, main_input_filename); \ + } while (0) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#undef ASM_OUTPUT_ALIGN +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG) != 0) fprintf ((FILE), "\t.p2align %d\n", LOG) + +/* djgpp has atexit (). */ +#undef HAVE_ATEXIT +#define HAVE_ATEXIT + +/* djgpp automatically calls its own version of __main, so don't define one + in libgcc, nor call one in main(). */ +#define HAS_INIT_SECTION diff --git a/contrib/gcc/config/i386/i386.c b/contrib/gcc/config/i386/i386.c index 9eb9582553c4..458e1760a4a0 100644 --- a/contrib/gcc/config/i386/i386.c +++ b/contrib/gcc/config/i386/i386.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/i386/i386.c,v 1.7 2000/01/29 13:06:33 obrien Exp $ */ #include <setjmp.h> #include "config.h" diff --git a/contrib/gcc/config/i386/i386.h b/contrib/gcc/config/i386/i386.h index e492e04101ee..92f2f92aacec 100644 --- a/contrib/gcc/config/i386/i386.h +++ b/contrib/gcc/config/i386/i386.h @@ -34,7 +34,7 @@ Boston, MA 02111-1307, USA. */ PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/config/i386/i386.h,v 1.5 1999/10/16 08:10:36 obrien Exp $ */ /* Names to predefine in the preprocessor for this target machine. */ diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md index 27df88774449..3c7b0eae5b18 100644 --- a/contrib/gcc/config/i386/i386.md +++ b/contrib/gcc/config/i386/i386.md @@ -71,7 +71,7 @@ ;; This shadows the processor_type enumeration, so changes must be made ;; to i386.h at the same time. -;; $FreeBSD$ +;; $FreeBSD: src/contrib/gcc/config/i386/i386.md,v 1.7.2.1 2000/08/07 10:06:43 obrien Exp $ (define_attr "type" "integer,binary,memory,test,compare,fcompare,idiv,imul,lea,fld,fpop,fpdiv,fpmul" diff --git a/contrib/gcc/config/i386/i386iscgas.h b/contrib/gcc/config/i386/i386iscgas.h new file mode 100644 index 000000000000..526fe374e481 --- /dev/null +++ b/contrib/gcc/config/i386/i386iscgas.h @@ -0,0 +1,67 @@ +/* Definitions for Intel 386 running Interactive Unix System V, + producing stabs-in-coff output (using a slightly modified gas). + Specifically, this is for recent versions that support POSIX; + for version 2.0.2, use configuration option i386-sysv instead. */ + +/* Underscores are not used on ISC systems (probably not on any COFF + system), despite the comments in i386/gas.h. If this is not defined, + enquire (for example) will fail to link. --karl@cs.umb.edu */ +#define NO_UNDERSCORES + +/* Mostly like other gas-using systems. */ +#include "i386/gas.h" + +/* But with ISC-specific additions. */ +#include "i386/isc.h" + +/* We do not want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO + + +/* The function `dbxout_init' in dbxout.c omits the first character of + `ltext_label_name' when outputting the main source directory and main + source filename. I don't understand why, but rather than making a + system-independent change there, I override dbxout.c's defaults. + Perhaps it would be better to use ".Ltext0" instead of + `ltext_label_name', but we've already generated the label, so we just + use it here. --karl@cs.umb.edu */ +#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(asmfile, cwd) \ + do { fprintf (asmfile, "%s ", ASM_STABS_OP); \ + output_quoted_string (asmfile, cwd); \ + fprintf (asmfile, ",%d,0,0,%s\n", N_SO, ltext_label_name); \ + } while (0) +#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(asmfile, input_file_name) \ + fprintf (asmfile, "%s ", ASM_STABS_OP); \ + output_quoted_string (input_file_name); \ + fprintf (asmfile, ",%d,0,0,%s\n", N_SO, ltext_label_name); \ + text_section (); \ + ASM_OUTPUT_INTERNAL_LABEL (asmfile, "Ltext", 0) + + +/* Because we don't include `svr3.h', we haven't yet defined SIZE_TYPE + and PTRDIFF_TYPE. ISC's definitions don't match GCC's defaults, so: */ + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + + +/* But we can't use crtbegin.o and crtend.o, because gas 1.38.1 doesn't + grok .section. The definitions here are otherwise identical to those + in i386/isc.h. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ + %{!posix:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}\ + %{p:-L/lib/libp} %{pg:-L/lib/libp}}}\ + %{shlib:%{posix:crtp1.o%s}%{!posix:crt1.o%s}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtn.o%s" diff --git a/contrib/gcc/config/i386/next.c b/contrib/gcc/config/i386/next.c new file mode 100644 index 000000000000..f249647ab595 --- /dev/null +++ b/contrib/gcc/config/i386/next.c @@ -0,0 +1,7 @@ +/* next.c: Functions for NeXT as target machine for GNU C compiler. */ + +/* Note that the include below means that we can't debug routines in + i386.c when running on a COFF system. */ + +#include "i386/i386.c" +#include "nextstep.c" diff --git a/contrib/gcc/config/i386/sol2dbg.h b/contrib/gcc/config/i386/sol2dbg.h new file mode 100644 index 000000000000..9f95333b4b99 --- /dev/null +++ b/contrib/gcc/config/i386/sol2dbg.h @@ -0,0 +1,27 @@ +/* Target definitions for GNU compiler for Intel 80386 running Solaris + with gas and gdb. + This file is added into the directory .../gcc-2.../config/i386 + Workability without "#undef DWARF_DEBUGGING_INFO" is not tested. */ + +/* Use stabs instead of DWARF debug format. */ +#ifdef PREFERRED_DEBUGGING_TYPE +#undef PREFERRED_DEBUGGING_TYPE +#endif +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "i386/sol2.h" + +#ifdef DWARF_DEBUGGING_INFO +#undef DWARF_DEBUGGING_INFO +#endif + +/* + Changed from config/svr4.h in the following ways: + + - Added "%{V}". + - Modified "{%v:-V}" to take into account "%{V}". + - Added "-s" so that stabs are saved in the final executable. */ + +#undef ASM_SPEC +#define ASM_SPEC \ + "%{V} %{v:%{!V:-V}} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} -s" diff --git a/contrib/gcc/config/i386/sysv4gdb.h b/contrib/gcc/config/i386/sysv4gdb.h new file mode 100644 index 000000000000..dd1e8f256f35 --- /dev/null +++ b/contrib/gcc/config/i386/sysv4gdb.h @@ -0,0 +1,7 @@ +/* Target definitions for GNU compiler for Intel 80386 running System V.4 + with gas and gdb. */ + +/* Use stabs instead of DWARF debug format. */ +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "i386/sysv4.h" diff --git a/contrib/gcc/config/i386/t-cygwin32 b/contrib/gcc/config/i386/t-cygwin32 new file mode 100644 index 000000000000..20bc9803b1ec --- /dev/null +++ b/contrib/gcc/config/i386/t-cygwin32 @@ -0,0 +1,16 @@ +LIBGCC1 = libgcc1-asm.a +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = i386/cygwin32.asm +LIB1ASMFUNCS = _chkstk + +# cygwin32 always has a limits.h, but, depending upon how we are doing +# the build, it may not be installed yet. +LIMITS_H_TEST = true + +# If we are building next to winsup, this will let us find the real +# limits.h when building libgcc2. Otherwise, winsup must be installed +# first. +LIBGCC2_INCLUDES = -I$(srcdir)/../winsup/include + +winnt.o: $(srcdir)/config/i386/winnt.c + $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/i386/winnt.c diff --git a/contrib/gcc/config/i386/t-go32 b/contrib/gcc/config/i386/t-go32 new file mode 100644 index 000000000000..6160b7ec945d --- /dev/null +++ b/contrib/gcc/config/i386/t-go32 @@ -0,0 +1,2 @@ +LIBGCC1 = libgcc1.null +CROSS_LIBGCC1 = libgcc1.null diff --git a/contrib/gcc/config/i386/t-iscscodbx b/contrib/gcc/config/i386/t-iscscodbx new file mode 100644 index 000000000000..928a7589f8c9 --- /dev/null +++ b/contrib/gcc/config/i386/t-iscscodbx @@ -0,0 +1,2 @@ +# The one that comes with the system is POSIX-compliant. +LIMITS_H = diff --git a/contrib/gcc/config/i386/x-cygwin32 b/contrib/gcc/config/i386/x-cygwin32 new file mode 100644 index 000000000000..f251835bd332 --- /dev/null +++ b/contrib/gcc/config/i386/x-cygwin32 @@ -0,0 +1,4 @@ +# Don't run fixproto +STMP_FIXPROTO = +# prefix.c wants to poke around the Registry +CLIB = -ladvapi32 diff --git a/contrib/gcc/config/i386/x-freebsd b/contrib/gcc/config/i386/x-freebsd new file mode 100644 index 000000000000..47640c0a2c0d --- /dev/null +++ b/contrib/gcc/config/i386/x-freebsd @@ -0,0 +1,4 @@ +# Don't run fixproto +STMP_FIXPROTO = +# Use only native include files +USER_H = diff --git a/contrib/gcc/config/i386/xm-cygwin32.h b/contrib/gcc/config/i386/xm-cygwin32.h new file mode 100644 index 000000000000..521a65309912 --- /dev/null +++ b/contrib/gcc/config/i386/xm-cygwin32.h @@ -0,0 +1,55 @@ +/* Configuration for GNU C-compiler for hosting on Windows NT. + using a unix style C library. + Copyright (C) 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define EXECUTABLE_SUFFIX ".exe" +#define NO_SYS_SIGLIST 1 +#define HAVE_BCOPY 1 +#define HAVE_BZERO 1 +#define HAVE_BCMP 1 +#define HAVE_RINDEX 1 +#define HAVE_INDEX 1 + +/* Even though we support "/", allow "\" since everybody tests both. */ +#define DIR_SEPARATOR '\\' + +/* If we allow both '/' and '\' as dir separators, then + allow both unix and win32 PATH syntax */ +#undef GET_ENVIRONMENT +#define GET_ENVIRONMENT(ENV_VALUE,ENV_NAME) \ +{ \ + char *epath; \ + char *win32epath; \ + \ + epath = win32epath = getenv (ENV_NAME); \ + /* if we have a posix path list, convert to win32 path list */ \ + if (epath != NULL && *epath != 0 && cygwin32_posix_path_list_p (epath)) \ + { \ + win32epath = (char *) xmalloc \ + (cygwin32_posix_to_win32_path_list_buf_size (epath)); \ + cygwin32_posix_to_win32_path_list (epath, win32epath); \ + } \ + ENV_VALUE = win32epath; \ +} + +#define PATH_SEPARATOR ';' + +/* This is needed so that protoize will compile. */ +#define POSIX diff --git a/contrib/gcc/config/i386/xm-go32.h b/contrib/gcc/config/i386/xm-go32.h new file mode 100644 index 000000000000..c44e73ea4211 --- /dev/null +++ b/contrib/gcc/config/i386/xm-go32.h @@ -0,0 +1,33 @@ +/* Configuration for GNU C-compiler for Intel 80386 running GO32. + Copyright (C) 1988, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define __MSDOS__ 1 + +#include "i386/xm-i386.h" + +/* Use semicolons to separate elements of a path. */ +#define PATH_SEPARATOR ';' + +#define EXECUTABLE_SUFFIX ".exe" + +/* Even though we support "/", allow "\" since everybody tests both. */ +#define DIR_SEPARATOR '\\' + +#define NO_SYS_SIGLIST 1 diff --git a/contrib/gcc/config/i386/xm-netbsd.h b/contrib/gcc/config/i386/xm-netbsd.h new file mode 100644 index 000000000000..3a9f32419907 --- /dev/null +++ b/contrib/gcc/config/i386/xm-netbsd.h @@ -0,0 +1,4 @@ +/* Configuration for GCC for Intel i386 running NetBSD as host. */ + +#include <i386/xm-i386.h> +#include <xm-netbsd.h> diff --git a/contrib/gcc/config/mips/abi64.h b/contrib/gcc/config/mips/abi64.h new file mode 100644 index 000000000000..ce1e5fe3831f --- /dev/null +++ b/contrib/gcc/config/mips/abi64.h @@ -0,0 +1,250 @@ +/* Definitions of target machine for GNU compiler. 64 bit ABI support. + Copyright (C) 1994, 1995, 1996, 1998, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Macros to implement the 64 bit ABI. This file is meant to be included + after mips.h. */ + +#undef SUBTARGET_TARGET_OPTIONS +#define SUBTARGET_TARGET_OPTIONS \ + { "abi=", &mips_abi_string, \ + "Speciy ABI to use"}, + +#undef STACK_BOUNDARY +#define STACK_BOUNDARY \ + ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \ + ? 64 : 128) + +#undef MIPS_STACK_ALIGN +#define MIPS_STACK_ALIGN(LOC) \ + ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \ + ? ((LOC) + 7) & ~7 \ + : ((LOC) + 15) & ~15) + +#undef GP_ARG_LAST +#define GP_ARG_LAST ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? GP_REG_FIRST + 7 : GP_REG_FIRST + 11) +#undef FP_ARG_LAST +#define FP_ARG_LAST ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? FP_REG_FIRST + 15 : FP_REG_FIRST + 19) + +#undef SUBTARGET_CONDITIONAL_REGISTER_USAGE +#define SUBTARGET_CONDITIONAL_REGISTER_USAGE \ +{ \ + /* fp20-23 are now caller saved. */ \ + if (mips_abi == ABI_64) \ + { \ + int regno; \ + for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) \ + call_used_regs[regno] = 1; \ + } \ + /* odd registers from fp21 to fp31 are now caller saved. */ \ + if (mips_abi == ABI_N32) \ + { \ + int regno; \ + for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) \ + call_used_regs[regno] = 1; \ + } \ +} + +#undef MAX_ARGS_IN_REGISTERS +#define MAX_ARGS_IN_REGISTERS ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? 4 : 8) + +#undef REG_PARM_STACK_SPACE +#define REG_PARM_STACK_SPACE(FNDECL) \ + ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? (MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \ + : 0) + +#define FUNCTION_ARG_PADDING(MODE, TYPE) \ + (! BYTES_BIG_ENDIAN \ + ? upward \ + : (((MODE) == BLKmode \ + ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ + && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\ + : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \ + && (mips_abi == ABI_32 \ + || mips_abi == ABI_O64 \ + || mips_abi == ABI_EABI \ + || GET_MODE_CLASS (MODE) == MODE_INT))) \ + ? downward : upward)) + +#undef RETURN_IN_MEMORY +#define RETURN_IN_MEMORY(TYPE) \ + ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? TYPE_MODE (TYPE) == BLKmode \ + : (int_size_in_bytes (TYPE) \ + > (mips_abi == ABI_EABI ? 2 * UNITS_PER_WORD : 16))) + +extern struct rtx_def *mips_function_value (); +#undef FUNCTION_VALUE +#define FUNCTION_VALUE(VALTYPE, FUNC) mips_function_value (VALTYPE, FUNC) + +/* For varargs, we must save the current argument, because it is the fake + argument va_alist, and will need to be converted to the real argument. + For stdarg, we do not need to save the current argument, because it + is a real argument. */ +#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ +{ int mips_off = (! current_function_varargs) && (! (CUM).last_arg_fp); \ + int mips_fp_off = (! current_function_varargs) && ((CUM).last_arg_fp); \ + if (((mips_abi != ABI_32 && mips_abi != ABI_O64) \ + && (CUM).arg_words < MAX_ARGS_IN_REGISTERS - mips_off) \ + || (mips_abi == ABI_EABI \ + && ! TARGET_SOFT_FLOAT \ + && (CUM).fp_arg_words < MAX_ARGS_IN_REGISTERS - mips_fp_off)) \ + { \ + int mips_save_gp_regs = \ + MAX_ARGS_IN_REGISTERS - (CUM).arg_words - mips_off; \ + int mips_save_fp_regs = \ + (mips_abi != ABI_EABI ? 0 \ + : MAX_ARGS_IN_REGISTERS - (CUM).fp_arg_words - mips_fp_off); \ + \ + if (mips_save_gp_regs < 0) \ + mips_save_gp_regs = 0; \ + if (mips_save_fp_regs < 0) \ + mips_save_fp_regs = 0; \ + PRETEND_SIZE = ((mips_save_gp_regs * UNITS_PER_WORD) \ + + (mips_save_fp_regs * UNITS_PER_FPREG)); \ + \ + if (! (NO_RTL)) \ + { \ + if ((CUM).arg_words < MAX_ARGS_IN_REGISTERS - mips_off) \ + { \ + rtx ptr, mem; \ + if (mips_abi != ABI_EABI) \ + ptr = virtual_incoming_args_rtx; \ + else \ + ptr = plus_constant (virtual_incoming_args_rtx, \ + - (mips_save_gp_regs \ + * UNITS_PER_WORD)); \ + mem = gen_rtx (MEM, BLKmode, ptr); \ + /* va_arg is an array access in this case, which causes \ + it to get MEM_IN_STRUCT_P set. We must set it here \ + so that the insn scheduler won't assume that these \ + stores can't possibly overlap with the va_arg loads. */ \ + if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN) \ + MEM_SET_IN_STRUCT_P (mem, 1); \ + move_block_from_reg \ + ((CUM).arg_words + GP_ARG_FIRST + mips_off, \ + mem, \ + mips_save_gp_regs, \ + mips_save_gp_regs * UNITS_PER_WORD); \ + } \ + if (mips_abi == ABI_EABI \ + && ! TARGET_SOFT_FLOAT \ + && (CUM).fp_arg_words < MAX_ARGS_IN_REGISTERS - mips_fp_off) \ + { \ + enum machine_mode mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; \ + int size = GET_MODE_SIZE (mode); \ + int off; \ + int i; \ + /* We can't use move_block_from_reg, because it will use \ + the wrong mode. */ \ + off = - (mips_save_gp_regs * UNITS_PER_WORD); \ + if (! TARGET_SINGLE_FLOAT) \ + off &= ~ 7; \ + if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) \ + off -= (mips_save_fp_regs / 2) * size; \ + else \ + off -= mips_save_fp_regs * size; \ + for (i = 0; i < mips_save_fp_regs; i++) \ + { \ + rtx tem = \ + gen_rtx (MEM, mode, \ + plus_constant (virtual_incoming_args_rtx, \ + off)); \ + emit_move_insn (tem, \ + gen_rtx (REG, mode, \ + ((CUM).fp_arg_words \ + + FP_ARG_FIRST \ + + i \ + + mips_fp_off))); \ + off += size; \ + if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) \ + ++i; \ + } \ + } \ + } \ + } \ +} + +#define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64) + +/* A C expression that indicates when an argument must be passed by + reference. If nonzero for an argument, a copy of that argument is + made in memory and a pointer to the argument is passed instead of the + argument itself. The pointer is passed in whatever way is appropriate + for passing a pointer to that type. */ +#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ + (mips_abi == ABI_EABI \ + && function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)) + +/* A C expression that indicates when it is the called function's + responsibility to make a copy of arguments passed by invisible + reference. Normally, the caller makes a copy and passes the + address of the copy to the routine being called. When + FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller + does not make a copy. Instead, it passes a pointer to the "live" + value. The called function must not modify this value. If it can + be determined that the value won't be modified, it need not make a + copy; otherwise a copy must be made. + + ??? The MIPS EABI says that the caller should copy in ``K&R mode.'' + I don't know how to detect that here, since flag_traditional is not + a back end flag. */ +#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ + (mips_abi == ABI_EABI && (NAMED) \ + && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED)) + +/* Define LONG_MAX correctly for all users. We need to handle 32 bit EABI, + 64 bit EABI, N32, and N64 as possible defaults. The checks performed here + are the same as the checks in override_options in mips.c that determines + whether MASK_LONG64 will be set. + + This does not handle inappropriate options or ununusal option + combinations. */ + +#undef LONG_MAX_SPEC +#if ((MIPS_ABI_DEFAULT == ABI_64) || ((MIPS_ABI_DEFAULT == ABI_EABI) && ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_64BIT))) +#define LONG_MAX_SPEC \ + "%{!mabi=32:%{!mabi=n32:%{!mlong32:%{!mgp32:%{!mips1:%{!mips2:-D__LONG_MAX__=9223372036854775807L}}}}}}" +#else +#define LONG_MAX_SPEC \ + "%{mabi=64:-D__LONG_MAX__=9223372036854775807L} \ + %{mlong64:-D__LONG_MAX__=9223372036854775807L} \ + %{mgp64:-D__LONG_MAX__=9223372036854775807L}" +#endif + +/* ??? Unimplemented stuff follows. */ + +/* ??? Add support for 16 byte/128 bit long doubles here when + mips_abi != ABI32. */ + +/* ??? Make main return zero if user did not specify return value. */ + +/* ??? Add support for .interfaces section, so as to get linker warnings + when stdarg functions called without prototype in scope? */ + +/* ??? Could optimize structure passing by putting the right register rtx + into the field decl, so that if we use the field, we can take the value from + a register instead of from memory. */ + + + diff --git a/contrib/gcc/config/mips/bsd-4.h b/contrib/gcc/config/mips/bsd-4.h new file mode 100644 index 000000000000..c2aee83df7b5 --- /dev/null +++ b/contrib/gcc/config/mips/bsd-4.h @@ -0,0 +1,46 @@ +/* Definitions of target machine for GNU compiler. MIPS RISC-OS BSD version. + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_BSD43 + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \ +-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)" + +#define STANDARD_INCLUDE_DIR "/bsd43/usr/include" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +-systype /bsd43/" + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" + +#define MACHINE_TYPE "RISC-OS BSD Mips" + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* Override defaults for finding the MIPS tools. */ +#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/" diff --git a/contrib/gcc/config/mips/bsd-5.h b/contrib/gcc/config/mips/bsd-5.h new file mode 100644 index 000000000000..f97af5e1f80d --- /dev/null +++ b/contrib/gcc/config/mips/bsd-5.h @@ -0,0 +1,67 @@ +/* Definitions of target machine for GNU compiler. + MIPS RISC-OS, 5.0 BSD version. + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_BSD43 + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \ +-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)" + +#define STANDARD_INCLUDE_DIR "/bsd43/usr/include" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \ +-systype /bsd43/" + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" + +#define MACHINE_TYPE "RISC-OS BSD Mips" + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* Override defaults for finding the MIPS tools. */ +#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/" + +#include "mips/mips.h" + +/* Some assemblers have a bug that causes backslash escaped chars in .ascii + to be misassembled, so we just completely avoid it. */ +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) diff --git a/contrib/gcc/config/mips/cross64.h b/contrib/gcc/config/mips/cross64.h new file mode 100644 index 000000000000..4462e5ecc55c --- /dev/null +++ b/contrib/gcc/config/mips/cross64.h @@ -0,0 +1,34 @@ +/* Configuration for an Irix 5 host and Irix 6 target using SGI's cross64 + package. */ + +#define STANDARD_INCLUDE_DIR "/usr/cross64/usr/include" +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/cross64/usr/bin/" +#undef MD_STARTFILE_PREFIX +#define MD_STARTFILE_PREFIX "/usr/cross64/usr/lib/lib64/" + +/* Must add TOOLROOT to the environment, or else the assembler will not + work. */ +#define INIT_ENVIRONMENT \ + "TOOLROOT=/usr/cross64" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{mips1:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \ + %{mips2:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \ + %{!mips1:%{!mips2:%{pg:/usr/cross64/usr/lib64/mips4/gcrt1.o} \ + %{!pg:%{p:/usr/cross64/usr/lib64/mips4/mcrt1.o \ + /usr/cross64/usr/lib64/mips4/libprof1.a} \ + %{!p:/usr/cross64/usr/lib64/mips4/crt1.o}}}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "%{mips1:crtn.o%s}%{mips2:crtn.o%s}%{!mips1:%{!mips2:/usr/cross64/usr/lib64/mips4/crtn.o}}" + +#undef LINK_SPEC +#define LINK_SPEC "\ +-64 -_SYSTYPE_SVR4 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}} \ +%{!mips1:%{!mips2:-L/usr/cross64/usr/lib64/mips4 -L/usr/cross64/usr/lib64}}" diff --git a/contrib/gcc/config/mips/dec-bsd.h b/contrib/gcc/config/mips/dec-bsd.h new file mode 100644 index 000000000000..126353b25dd7 --- /dev/null +++ b/contrib/gcc/config/mips/dec-bsd.h @@ -0,0 +1,53 @@ +/* Definitions for DECstation running BSD as target machine for GNU compiler. + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define DECSTATION + +#ifndef CPP_PREDEFINES +#define CPP_PREDEFINES "-D__ANSI_COMPAT \ +-DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -Dbsd4_4 -Dhost_mips -Dmips \ +-Dunix -D_mips -D_unix -D_host_mips -D_MIPSEL -D_R3000 \ +-Asystem(unix) -Asystem(bsd) -Amachine(mips)" +#endif + +/* Always uses GNU ld. */ +#ifndef LINK_SPEC +#define LINK_SPEC "%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3}" +#endif + +#define LIB_SPEC "" +#define STARTFILE_SPEC "" + +#ifndef MACHINE_TYPE +#define MACHINE_TYPE "DECstation running BSD 4.4" +#endif + +#define TARGET_DEFAULT MASK_GAS +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "mips/mips.h" + +/* Since gas and gld are standard on 4.4 BSD, we don't need these */ +#undef MD_EXEC_PREFIX +#undef MD_STARTFILE_PREFIX +#undef ASM_FINAL_SPEC +#undef LIB_SPEC +#undef STARTFILE_SPEC + diff --git a/contrib/gcc/config/mips/dec-osf1.h b/contrib/gcc/config/mips/dec-osf1.h new file mode 100644 index 000000000000..ee7e787353c4 --- /dev/null +++ b/contrib/gcc/config/mips/dec-osf1.h @@ -0,0 +1,55 @@ +/* Definitions of target machine for GNU compiler. DECstation (OSF/1) version. + Copyright (C) 1992, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define DEC_OSF1 + +#define CPP_PREDEFINES "\ +-D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \ +-Dbsd4_2 -Dhost_mips -Dmips -Dosf -Dunix \ +-Asystem(unix) -Asystem(xpg4) -Acpu(mips) -Amachine(mips)" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}" + +#include "mips/ultrix.h" +#include "mips/mips.h" + +/* Specify size_t and wchar_t types. */ +#undef SIZE_TYPE +#undef WCHAR_TYPE +#undef WCHAR_TYPE_SIZE + +#define SIZE_TYPE "long unsigned int" +#define WCHAR_TYPE "short unsigned int" +#define WCHAR_TYPE_SIZE SHORT_TYPE_SIZE + +#undef SUBTARGET_CPP_SIZE_SPEC +#define SUBTARGET_CPP_SIZE_SPEC "\ +%{mlong64:-D__PTRDIFF_TYPE__=long\\ int} \ +%{!mlong64:-D__PTRDIFF_TYPE__=int}" + +/* turn off collect2 COFF support, since ldfcn now has elf declaration */ +#undef OBJECT_FORMAT_COFF + +#undef MACHINE_TYPE +#define MACHINE_TYPE "DECstation running DEC OSF/1" diff --git a/contrib/gcc/config/mips/ecoff.h b/contrib/gcc/config/mips/ecoff.h new file mode 100644 index 000000000000..dcc00a4b4b84 --- /dev/null +++ b/contrib/gcc/config/mips/ecoff.h @@ -0,0 +1,35 @@ +/* Definitions of target machine for GNU compiler. MIPS version with + GOFAST floating point library. + Copyright (C) 1994, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* US Software GOFAST library support. */ +#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS + +#include "mips/mips.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR3000 -D_mips -D_MIPSEB -D_R3000" + +/* Use memcpy, et. al., rather than bcopy. */ +#define TARGET_MEM_FUNCTIONS + +/* Don't assume anything about startfiles. The linker script will load the + appropriate startfiles. */ +#define STARTFILE_SPEC "" diff --git a/contrib/gcc/config/mips/ecoffl.h b/contrib/gcc/config/mips/ecoffl.h new file mode 100644 index 000000000000..9fe90e848480 --- /dev/null +++ b/contrib/gcc/config/mips/ecoffl.h @@ -0,0 +1,30 @@ +/* Definitions of target machine for GNU compiler. Little endian MIPS + version with GOFAST floating point library. + Copyright (C) 1994, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is a little endian version of ecoff.h. */ + +#define TARGET_ENDIAN_DEFAULT 0 + +#include "gofast.h" +#include "mips/ecoff.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000" diff --git a/contrib/gcc/config/mips/elf.h b/contrib/gcc/config/mips/elf.h new file mode 100644 index 000000000000..53af04690760 --- /dev/null +++ b/contrib/gcc/config/mips/elf.h @@ -0,0 +1,329 @@ +/* Definitions of target machine for GNU compiler. MIPS R3000 version with + GOFAST floating point library. + Copyright (C) 1994, 1997, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Use ELF. */ +#define OBJECT_FORMAT_ELF + +/* Until we figure out what MIPS ELF targets normally use, just do + stabs in ELF. */ +#ifndef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG +#endif + +/* Mostly like ECOFF. */ +#include "gofast.h" +#include "mips/ecoff.h" + +/* We need to use .esize and .etype instead of .size and .type to + avoid conflicting with ELF directives. */ +#undef PUT_SDB_SIZE +#define PUT_SDB_SIZE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.esize\t%d;", (a)); \ +} while (0) + +#undef PUT_SDB_TYPE +#define PUT_SDB_TYPE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a)); \ +} while (0) + +/* Biggest alignment supported by the object file format of this + machine. Use this macro to limit the alignment which can be + specified using the `__attribute__ ((aligned (N)))' construct. If + not defined, the default value is `BIGGEST_ALIGNMENT'. */ + +#define MAX_OFILE_ALIGNMENT (32768*8) + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. Some target formats do not support arbitrary sections. Do not + define this macro in such cases. */ + +#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \ +do { \ + extern FILE *asm_out_text_file; \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \ + fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \ + else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \ + fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME)); \ + else \ + fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME)); \ +} while (0) + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#define TYPE_OPERAND_FMT "@%s" + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#undef TYPE_ASM_OP +#undef SIZE_ASM_OP +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" + +/* These macros generate the special .type and .size directives which + are used to set the corresponding fields of the linker symbol table + entries in an ELF object file under SVR4. These macros also output + the starting labels for the relevant functions/objects. */ + +/* Write the extra assembler code needed to declare an object properly. */ + +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + mips_declare_object (FILE, NAME, "", ":\n", 0); \ + } while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#undef ASM_FINISH_DECLARE_OBJECT +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fputc ( '\t', FILE); \ + assemble_name (FILE, LABEL1); \ + fputs ( " = ", FILE); \ + assemble_name (FILE, LABEL2); \ + fputc ( '\n', FILE); \ + } while (0) + +/* Note about .weak vs. .weakext + The mips native assemblers support .weakext, but not .weak. + mips-elf gas supports .weak, but not .weakext. + mips-elf gas has been changed to support both .weak and .weakext, + but until that support is generally available, the 'if' below + should serve. */ + +#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0) +#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE) \ + do { \ + if (TARGET_GAS) \ + fputs ("\t.weak\t", FILE); \ + else \ + fputs ("\t.weakext\t", FILE); \ + assemble_name (FILE, NAME); \ + if (VALUE) \ + { \ + fputc (' ', FILE); \ + assemble_name (FILE, VALUE); \ + } \ + fputc ('\n', FILE); \ + } while (0) + +#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) +#undef UNIQUE_SECTION_P +#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL)) +#define UNIQUE_SECTION(DECL,RELOC) \ +do { \ + int len, size, sec; \ + char *name, *string, *prefix; \ + static char *prefixes[4][2] = { \ + { ".text.", ".gnu.linkonce.t." }, \ + { ".rodata.", ".gnu.linkonce.r." }, \ + { ".data.", ".gnu.linkonce.d." }, \ + { ".sdata.", ".gnu.linkonce.s." } \ + }; \ + \ + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL)); \ + size = int_size_in_bytes (TREE_TYPE (decl)); \ + \ + /* Determine the base section we are interested in: \ + 0=text, 1=rodata, 2=data, 3=sdata. */ \ + if (TREE_CODE (DECL) == FUNCTION_DECL) \ + sec = 0; \ + else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16) \ + && TREE_CODE (decl) == STRING_CST \ + && !flag_writable_strings) \ + { \ + /* For embedded position independent code, put constant strings \ + in the text section, because the data section is limited to \ + 64K in size. For mips16 code, put strings in the text \ + section so that a PC relative load instruction can be used to \ + get their address. */ \ + sec = 0; \ + } \ + else if (TARGET_EMBEDDED_DATA) \ + { \ + /* For embedded applications, always put an object in read-only data \ + if possible, in order to reduce RAM usage. */ \ + \ + if (DECL_READONLY_SECTION (DECL, RELOC)) \ + sec = 1; \ + else if (size > 0 && size <= mips_section_threshold) \ + sec = 3; \ + else \ + sec = 2; \ + } \ + else \ + { \ + /* For hosted applications, always put an object in small data if \ + possible, as this gives the best performance. */ \ + \ + if (size > 0 && size <= mips_section_threshold) \ + sec = 3; \ + else if (DECL_READONLY_SECTION (DECL, RELOC)) \ + sec = 1; \ + else \ + sec = 2; \ + } \ + \ + prefix = prefixes[sec][DECL_ONE_ONLY (DECL)]; \ + len = strlen (name) + strlen (prefix); \ + string = alloca (len + 1); \ + sprintf (string, "%s%s", prefix, name); \ + \ + DECL_SECTION_NAME (DECL) = build_string (len, string); \ +} while (0) + +/* Support the ctors/dtors and other sections. */ + +/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. + + Note that we want to give these sections the SHF_WRITE attribute + because these sections will actually contain data (i.e. tables of + addresses of functions in the current root executable or shared library + file) and, in the case of a shared library, the relocatable addresses + will have to be properly resolved/relocated (and then written into) by + the dynamic linker when it actually attaches the given shared library + to the executing process. (Note that on SVR4, you may wish to use the + `-z text' option to the ELF linker, when building a shared library, as + an additional check that you are doing everything right. But if you do + use the `-z text' option when building a shared library, you will get + errors unless the .ctors and .dtors sections are marked as writable + via the SHF_WRITE attribute.) */ + +#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\"" +#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\"" + +/* A list of other sections which the compiler might be "in" at any + given time. */ +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata, in_ctors, in_dtors + +#define INVOKE__main +#define NAME__MAIN "__gccmain" +#define SYMBOL__MAIN __gccmain + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP) + +#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP) \ +void FN () \ +{ \ + if (in_section != ENUM) \ + { \ + fprintf (asm_out_file, "%s\n", OP); \ + in_section = ENUM; \ + } \ +} + + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define CTOR_LIST_BEGIN \ +asm (CTORS_SECTION_ASM_OP); \ +func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) } + +#define CTOR_LIST_END \ +asm (CTORS_SECTION_ASM_OP); \ +func_ptr __CTOR_END__[1] = { (func_ptr) 0 }; + +#define DTOR_LIST_BEGIN \ +asm (DTORS_SECTION_ASM_OP); \ +func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) } + +#define DTOR_LIST_END \ +asm (DTORS_SECTION_ASM_OP); \ +func_ptr __DTOR_END__[1] = { (func_ptr) 0 }; + +/* Don't set the target flags, this is done by the linker script */ +#undef LIB_SPEC +#define LIB_SPEC "" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "crtbegin%O%s crt0%O%s" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend%O%s" diff --git a/contrib/gcc/config/mips/elf64.h b/contrib/gcc/config/mips/elf64.h new file mode 100644 index 000000000000..91c83103b975 --- /dev/null +++ b/contrib/gcc/config/mips/elf64.h @@ -0,0 +1,355 @@ +/* Definitions of target machine for GNU compiler. MIPS R4000 version with + GOFAST floating point library. + Copyright (C) 1994, 1995, 1996, 1997, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define OBJECT_FORMAT_ELF + +/* Default to -mips3. */ +#define TARGET_DEFAULT MASK_FLOAT64|MASK_64BIT +#define MIPS_ISA_DEFAULT 3 + +/* Until we figure out what MIPS ELF targets normally use, just do + stabs in ELF. */ +#ifndef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG +#endif + +/* US Software GOFAST library support. */ +#include "gofast.h" +#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS + +#include "mips/mips.h" + +/* This must be done after mips.h, because mips.h defines + TARGET_ENDIAN_DEFAULT. */ +#undef MULTILIB_DEFAULTS +#if TARGET_ENDIAN_DEFAULT == 0 +#define MULTILIB_DEFAULTS { "EL", "mips3" } +#else +#define MULTILIB_DEFAULTS { "EB", "mips3" } +#endif + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000" + +/* I would rather put this in CPP_PREDEFINES, but the gcc driver + doesn't handle -U options in CPP_PREDEFINES. */ +#undef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "\ +%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}" + +/* Use memcpy, et. al., rather than bcopy. */ +#define TARGET_MEM_FUNCTIONS + +/* Biggest alignment supported by the object file format of this + machine. Use this macro to limit the alignment which can be + specified using the `__attribute__ ((aligned (N)))' construct. If + not defined, the default value is `BIGGEST_ALIGNMENT'. */ + +#define MAX_OFILE_ALIGNMENT (32768*8) + +/* We need to use .esize and .etype instead of .size and .type to + avoid conflicting with ELF directives. */ +#undef PUT_SDB_SIZE +#define PUT_SDB_SIZE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.esize\t%d;", (a)); \ +} while (0) + +#undef PUT_SDB_TYPE +#define PUT_SDB_TYPE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a)); \ +} while (0) + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. Some target formats do not support arbitrary sections. Do not + define this macro in such cases. */ + +#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \ +do { \ + extern FILE *asm_out_text_file; \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \ + fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \ + else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \ + fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME)); \ + else \ + fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME)); \ +} while (0) + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#define TYPE_OPERAND_FMT "@%s" + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#undef TYPE_ASM_OP +#undef SIZE_ASM_OP +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" + +/* These macros generate the special .type and .size directives which + are used to set the corresponding fields of the linker symbol table + entries in an ELF object file under SVR4. These macros also output + the starting labels for the relevant functions/objects. */ + +/* Write the extra assembler code needed to declare an object properly. */ + +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + mips_declare_object (FILE, NAME, "", ":\n", 0); \ + } while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#undef ASM_FINISH_DECLARE_OBJECT +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fputc ( '\t', FILE); \ + assemble_name (FILE, LABEL1); \ + fputs ( " = ", FILE); \ + assemble_name (FILE, LABEL2); \ + fputc ( '\n', FILE); \ + } while (0) + +/* Note about .weak vs. .weakext + The mips native assemblers support .weakext, but not .weak. + mips-elf gas supports .weak, but not .weakext. + mips-elf gas has been changed to support both .weak and .weakext, + but until that support is generally available, the 'if' below + should serve. */ + +#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0) +#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE) \ + do { \ + if (TARGET_GAS) \ + fputs ("\t.weak\t", FILE); \ + else \ + fputs ("\t.weakext\t", FILE); \ + assemble_name (FILE, NAME); \ + if (VALUE) \ + { \ + fputc (' ', FILE); \ + assemble_name (FILE, VALUE); \ + } \ + fputc ('\n', FILE); \ + } while (0) + +#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) +#undef UNIQUE_SECTION_P +#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL)) +#define UNIQUE_SECTION(DECL,RELOC) \ +do { \ + int len, size, sec; \ + char *name, *string, *prefix; \ + static char *prefixes[4][2] = { \ + { ".text.", ".gnu.linkonce.t." }, \ + { ".rodata.", ".gnu.linkonce.r." }, \ + { ".data.", ".gnu.linkonce.d." }, \ + { ".sdata.", ".gnu.linkonce.s." } \ + }; \ + \ + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL)); \ + size = int_size_in_bytes (TREE_TYPE (decl)); \ + \ + /* Determine the base section we are interested in: \ + 0=text, 1=rodata, 2=data, 3=sdata. */ \ + if (TREE_CODE (DECL) == FUNCTION_DECL) \ + sec = 0; \ + else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16) \ + && TREE_CODE (decl) == STRING_CST \ + && !flag_writable_strings) \ + { \ + /* For embedded position independent code, put constant strings \ + in the text section, because the data section is limited to \ + 64K in size. For mips16 code, put strings in the text \ + section so that a PC relative load instruction can be used to \ + get their address. */ \ + sec = 0; \ + } \ + else if (TARGET_EMBEDDED_DATA) \ + { \ + /* For embedded applications, always put an object in read-only data \ + if possible, in order to reduce RAM usage. */ \ + \ + if (DECL_READONLY_SECTION (DECL, RELOC)) \ + sec = 1; \ + else if (size > 0 && size <= mips_section_threshold) \ + sec = 3; \ + else \ + sec = 2; \ + } \ + else \ + { \ + /* For hosted applications, always put an object in small data if \ + possible, as this gives the best performance. */ \ + \ + if (size > 0 && size <= mips_section_threshold) \ + sec = 3; \ + else if (DECL_READONLY_SECTION (DECL, RELOC)) \ + sec = 1; \ + else \ + sec = 2; \ + } \ + \ + prefix = prefixes[sec][DECL_ONE_ONLY (DECL)]; \ + len = strlen (name) + strlen (prefix); \ + string = alloca (len + 1); \ + sprintf (string, "%s%s", prefix, name); \ + \ + DECL_SECTION_NAME (DECL) = build_string (len, string); \ +} while (0) + +/* Support the ctors/dtors and other sections. */ + +/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. + + Note that we want to give these sections the SHF_WRITE attribute + because these sections will actually contain data (i.e. tables of + addresses of functions in the current root executable or shared library + file) and, in the case of a shared library, the relocatable addresses + will have to be properly resolved/relocated (and then written into) by + the dynamic linker when it actually attaches the given shared library + to the executing process. (Note that on SVR4, you may wish to use the + `-z text' option to the ELF linker, when building a shared library, as + an additional check that you are doing everything right. But if you do + use the `-z text' option when building a shared library, you will get + errors unless the .ctors and .dtors sections are marked as writable + via the SHF_WRITE attribute.) */ + +#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\"" +#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\"" + +/* A list of other sections which the compiler might be "in" at any + given time. */ +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata, in_ctors, in_dtors + +#define INVOKE__main +#define NAME__MAIN "__gccmain" +#define SYMBOL__MAIN __gccmain + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP) + +#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP) \ +void FN () \ +{ \ + if (in_section != ENUM) \ + { \ + fprintf (asm_out_file, "%s\n", OP); \ + in_section = ENUM; \ + } \ +} + + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define CTOR_LIST_BEGIN \ +asm (CTORS_SECTION_ASM_OP); \ +func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) } + +#define CTOR_LIST_END \ +asm (CTORS_SECTION_ASM_OP); \ +func_ptr __CTOR_END__[1] = { (func_ptr) 0 }; + +#define DTOR_LIST_BEGIN \ +asm (DTORS_SECTION_ASM_OP); \ +func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) } + +#define DTOR_LIST_END \ +asm (DTORS_SECTION_ASM_OP); \ +func_ptr __DTOR_END__[1] = { (func_ptr) 0 }; + +/* Don't set the target flags, this is done by the linker script */ +#undef LIB_SPEC +#define LIB_SPEC "" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "crtbegin%O%s crt0%O%s" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend%O%s" diff --git a/contrib/gcc/config/mips/elfl.h b/contrib/gcc/config/mips/elfl.h new file mode 100644 index 000000000000..7575e3da5d8d --- /dev/null +++ b/contrib/gcc/config/mips/elfl.h @@ -0,0 +1,29 @@ +/* Definitions of target machine for GNU compiler. Little endian MIPS + R3000 version with GOFAST floating point library. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is a little endian version of elf.h. */ + +#define TARGET_ENDIAN_DEFAULT 0 + +#include "mips/elf.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000" diff --git a/contrib/gcc/config/mips/elfl64.h b/contrib/gcc/config/mips/elfl64.h new file mode 100644 index 000000000000..5e18c0932086 --- /dev/null +++ b/contrib/gcc/config/mips/elfl64.h @@ -0,0 +1,29 @@ +/* Definitions of target machine for GNU compiler. Little endian MIPS + R4000 version with GOFAST floating point library. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is a little endian version of elf64.h. */ + +#define TARGET_ENDIAN_DEFAULT 0 + +#include "mips/elf64.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4000 -D_mips -D_MIPSEL -D_R4000" diff --git a/contrib/gcc/config/mips/elflorion.h b/contrib/gcc/config/mips/elflorion.h new file mode 100644 index 000000000000..4b7f111873ff --- /dev/null +++ b/contrib/gcc/config/mips/elflorion.h @@ -0,0 +1,24 @@ +/* Definitions of target machine for GNU compiler. MIPS ORION version with + GOFAST floating point library. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_CPU_STRING_DEFAULT "orion" + +#include "mips/elfl64.h" diff --git a/contrib/gcc/config/mips/elforion.h b/contrib/gcc/config/mips/elforion.h new file mode 100644 index 000000000000..aa1a058b50d3 --- /dev/null +++ b/contrib/gcc/config/mips/elforion.h @@ -0,0 +1,22 @@ +/* Definitions of target machine for GNU compiler. MIPS ORION version with + GOFAST floating point library. + Copyright (C) 1994, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_CPU_STRING_DEFAULT "orion" diff --git a/contrib/gcc/config/mips/gnu.h b/contrib/gcc/config/mips/gnu.h new file mode 100644 index 000000000000..734548b52115 --- /dev/null +++ b/contrib/gcc/config/mips/gnu.h @@ -0,0 +1,130 @@ +/* Definitions of target machine for GNU compiler. MIPS GNU Hurd version. + Copyright (C) 1995, 1996, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define TARGET_DEFAULT MASK_GAS + +#include <mips/mips.h> + +#undef SWITCH_TAKES_ARG +#undef ASM_FILE_END +#undef ASM_OUTPUT_IDENT +#undef ASM_OUTPUT_SOURCE_LINE +#undef READONLY_DATA_SECTION +#undef SELECT_SECTION +#undef ASM_DECLARE_FUNCTION_NAME +#undef ASM_DECLARE_OBJECT_NAME +/* #undef PREFERRED_DEBUGGING_TYPE */ + +#include <svr4.h> + +#undef MD_EXEC_PREFIX +#undef MD_STARTFILE_PREFIX +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (MIPS GNU/ELF)"); + +/* Output at beginning of assembler file. */ +/* The .file command should always begin the output. */ +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + mips_asm_file_start (FILE); \ + fprintf (FILE, "\t.version\t\"01.01\"\n"); \ + } while (0) + +#undef ASM_FILE_END +#define ASM_FILE_END(FILE) \ + do { \ + mips_asm_file_end(FILE); \ + if (!flag_no_ident) \ + fprintf ((FILE), "\t%s\t\"GCC: (GNU) %s\"\n", \ + IDENT_ASM_OP, version_string); \ + } while (0) + +#undef ASM_OUTPUT_SOURCE_LINE +#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ + do { \ + ++sym_lineno; \ + fprintf ((FILE), ".LM%d:\n\t%s %d,0,%d,.LM%d\n", \ + sym_lineno, ASM_STABN_OP, N_SLINE, (LINE), sym_lineno); \ + } while (0) + +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ + do { \ + extern FILE *asm_out_text_file; \ + \ + if (TARGET_GP_OPT) \ + STREAM = asm_out_text_file; \ + fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (STREAM, NAME); \ + putc (',', STREAM); \ + fprintf (STREAM, TYPE_OPERAND_FMT, "function"); \ + putc ('\n', STREAM); \ + ASM_DECLARE_RESULT (STREAM, DECL_RESULT (DECL)); \ + HALF_PIC_DECLARE (NAME); \ + } while (0) + +/* Switch Recognition by gcc.c. Add -G xx support */ +#undef SWITCH_TAKES_ARG +#define SWITCH_TAKES_ARG(CHAR) \ + (DEFAULT_SWITCH_TAKES_ARG(CHAR) || (CHAR) == 'G') + +#undef DEFAULT_PCC_STRUCT_RETURN +#define DEFAULT_PCC_STRUCT_RETURN 1 + +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ] + +#define MIPS_GNU + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -Acpu(mips) -Amachine(mips) \ +-Dunix -Asystem(unix) -DMACH -Asystem(mach) -D__GNU__ -Asystem(gnu) \ +-DMIPSEB -DR3000 -D_MIPSEB -D_R3000 \ +-D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32" + +#undef LINK_SPEC +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \ +-systype /gnu/ " + +#undef LIB_SPEC +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}" + +#undef MACHINE_TYPE +#define MACHINE_TYPE "GNU MIPS/ELF" + +#undef YES_UNDERSCORE + +#undef SDB_DEBUGGING_INFO +#undef DBX_DEBUGGING_INFO +#undef MIPS_DEBUGGING_INFO +#define DWARF_DEBUGGING_INFO + +#define NO_MIPS_SELECT_SECTION + +/* Get machine-independent configuration parameters for the GNU system. */ +#include <gnu.h> diff --git a/contrib/gcc/config/mips/iris3.h b/contrib/gcc/config/mips/iris3.h new file mode 100644 index 000000000000..1f690ffa466b --- /dev/null +++ b/contrib/gcc/config/mips/iris3.h @@ -0,0 +1,72 @@ +/* Definitions of target machine for GNU compiler. Iris version. + Copyright (C) 1991, 1993, 1995, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define SGI_TARGET 1 /* inform other mips files this is SGI */ + +/* Names to predefine in the preprocessor for this target machine. */ + +#define CPP_PREDEFINES "\ +-Dunix -Dmips -Dsgi -DSVR3 -Dhost_mips -DMIPSEB -DSYSTYPE_SYSV \ +-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)" + +#define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}" + +#define SUBTARGET_CPP_SPEC "\ +%{!ansi:-D__EXTENSIONS__} -D_MIPSEB -D_SYSTYPE_SYSV" + +#define LIB_SPEC \ + "%{!p:%{!pg:%{!static:%{!g*:-lc_s}} -lc}}%{p:-lc_p}%{pg:-lc_p} crtn.o%s" + +#define MACHINE_TYPE "Silicon Graphics Mips" + +/* Always use 1 for .file number. I [meissner@osf.org] wonder why + IRIS needs this. */ + +#define SET_FILE_NUMBER() num_source_filenames = 1 + +/* Put out a label after a .loc. I [meissner@osf.org] wonder why + IRIS needs this. */ + +#define LABEL_AFTER_LOC(STREAM) fprintf (STREAM, "LM%d:\n", ++sym_lineno) + +#define STACK_ARGS_ADJUST(SIZE) \ +{ \ + SIZE.constant += 4; \ + if (SIZE.constant < 32) \ + SIZE.constant = 32; \ +} + +/* Do not allow `$' in identifiers. */ + +#define DOLLARS_IN_IDENTIFIERS 0 + +/* Tell G++ not to create constructors or destructors with $'s in them. */ + +#define NO_DOLLAR_IN_LABEL 1 + +/* Specify wchar_t type. */ +#define WCHAR_TYPE "unsigned char" +#define WCHAR_TYPE_SIZE BITS_PER_UNIT + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* Plain char is unsigned in the SGI compiler. */ +#define DEFAULT_SIGNED_CHAR 0 diff --git a/contrib/gcc/config/mips/iris4.h b/contrib/gcc/config/mips/iris4.h new file mode 100644 index 000000000000..7ca0459c6254 --- /dev/null +++ b/contrib/gcc/config/mips/iris4.h @@ -0,0 +1,48 @@ +/* Definitions of target machine for GNU compiler. Iris version 4. + Copyright (C) 1991, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* Profiling is supported via libprof1.a not -lc_p as in Irix 3. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}" + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{!p:%{!pg:%{!static:%{!g*:-lc_s}}}}%{p:libprof1.a%s}%{pg:libprof1.a%s} -lc crtn.o%s" + +/* Some assemblers have a bug that causes backslash escaped chars in .ascii + to be misassembled, so we just completely avoid it. */ +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) diff --git a/contrib/gcc/config/mips/iris4loser.h b/contrib/gcc/config/mips/iris4loser.h new file mode 100644 index 000000000000..426c822b68a5 --- /dev/null +++ b/contrib/gcc/config/mips/iris4loser.h @@ -0,0 +1,5 @@ +/* Like iris4.h, but always inhibits assembler optimization for MIPS as. + Use this via mips-sgi-iris4loser if you need it. */ + +#define SUBTARGET_MIPS_AS_ASM_SPEC "-O0 %{v}" +#define SUBTARGET_ASM_OPTIMIZING_SPEC "" diff --git a/contrib/gcc/config/mips/iris5.h b/contrib/gcc/config/mips/iris5.h new file mode 100644 index 000000000000..7910eef88d6d --- /dev/null +++ b/contrib/gcc/config/mips/iris5.h @@ -0,0 +1,164 @@ +/* Definitions of target machine for GNU compiler. Iris version 5. + Copyright (C) 1993, 1995, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef TARGET_DEFAULT +#define TARGET_DEFAULT MASK_ABICALLS +#endif +#define ABICALLS_ASM_OP ".option pic2" + +#include "mips/iris3.h" +#include "mips/mips.h" +#include "mips/iris4.h" + +/* Irix 5 doesn't use COFF, so disable special COFF handling in collect2.c. */ +#undef OBJECT_FORMAT_COFF + +/* ??? This is correct, but not very useful, because there is no file that + uses this macro. */ +/* ??? The best way to handle global constructors under ELF is to use .init + and .fini sections. Unfortunately, there is apparently no way to get + the Irix 5.x (x <= 2) assembler to create these sections. So we instead + use collect. The linker can create these sections via -init and -fini + options, but using this would require modifying how crtstuff works, and + I will leave that for another time (or someone else). */ +#define OBJECT_FORMAT_ELF +#define HAS_INIT_SECTION +#define LD_INIT_SWITCH "-init" +#define LD_FINI_SWITCH "-fini" + +/* Specify wchar_t types. */ +#undef WCHAR_TYPE +#undef WCHAR_TYPE_SIZE +#undef MAX_WCHAR_TYPE_SIZE + +#define WCHAR_TYPE "long int" +#define WCHAR_TYPE_SIZE LONG_TYPE_SIZE +#define MAX_WCHAR_TYPE_SIZE MAX_LONG_TYPE_SIZE + +#define WORD_SWITCH_TAKES_ARG(STR) \ + (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ + || !strcmp (STR, "rpath")) + +#undef SUBTARGET_CC1_SPEC +#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}" + +/* ??? _MIPS_SIM and _MIPS_SZPTR should eventually depend on options when + options for them exist. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES \ + "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \ + -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \ + -D_MIPS_SIM=_MIPS_SIM_ABI32 -D_MIPS_SZPTR=32 \ + -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)" + +#undef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "\ +%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE -D_LONGLONG} \ +%{!mfp64: -D_MIPS_FPSET=16}%{mfp64: -D_MIPS_FPSET=32} \ +%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \ +%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \ +%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \ +%{!mips1: %{!mips2: %{!mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS1}}} \ +%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \ +%{!mlong64: -D_MIPS_SZLONG=32}%{mlong64: -D_MIPS_SZLONG=64}" + +#undef LINK_SPEC +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{static: -non_shared} \ +%{!static: \ + %{!shared:%{!non_shared:%{!call_shared: -call_shared -no_unresolved}}}} \ +%{rpath} \ +-_SYSTYPE_SVR4" + +/* We now support shared libraries. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "\ +%{!static: \ + %{!shared:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}}} \ +%{static: \ + %{pg:gcrt1.o%s} \ + %{!pg:%{p:/usr/lib/nonshared/mcrt1.o%s libprof1.a%s} \ + %{!p:/usr/lib/nonshared/crt1.o%s}}}" + +#undef LIB_SPEC +#define LIB_SPEC "%{!shared:%{p:-lprof1} %{pg:-lprof1} -lc}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "%{!shared:crtn.o%s}" + +/* We do not want to run mips-tfile! */ +#undef ASM_FINAL_SPEC + +/* The system header files are C++ aware. */ +/* ??? Unfortunately, most but not all of the headers are C++ aware. + Specifically, curses.h is not, and as a consequence, defining this + used to prevent libg++ building. This is no longer the case so + define it again to prevent other problems, e.g. with getopt in + unistd.h. We still need some way to fix just those files that need + fixing. */ +#define NO_IMPLICIT_EXTERN_C 1 + +/* We don't support debugging info for now. */ +#undef DBX_DEBUGGING_INFO +#undef SDB_DEBUGGING_INFO +#undef MIPS_DEBUGGING_INFO +#undef PREFERRED_DEBUGGING_TYPE + +/* Likewise, the assembler doesn't handle DWARF2 directives. */ +#define DWARF2_UNWIND_INFO 0 + +#undef MACHINE_TYPE +#define MACHINE_TYPE "SGI running IRIX 5.x" + + /* Dollar signs are OK in Irix5 but not in Irix3. */ +#undef DOLLARS_IN_IDENTIFIERS +#undef NO_DOLLAR_IN_LABEL + +/* -G is incompatible with -KPIC which is the default, so only allow objects + in the small data section if the user explicitly asks for it. */ +#undef MIPS_DEFAULT_GVALUE +#define MIPS_DEFAULT_GVALUE 0 + +/* In Irix 5, we must output a `.global name .text' directive for every used + but undefined function. If we don't, the linker may perform an optimization + (skipping over the insns that set $gp) when it is unsafe. This is used + indirectly by ASM_OUTPUT_EXTERNAL. */ +#define ASM_OUTPUT_UNDEF_FUNCTION(FILE, NAME) \ +do { \ + fputs ("\t.globl ", FILE); \ + assemble_name (FILE, NAME); \ + fputs (" .text\n", FILE); \ +} while (0) + +/* Also do this for libcalls. */ +#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \ + mips_output_external_libcall (FILE, XSTR (FUN, 0)) + +/* This does for functions what ASM_DECLARE_OBJECT_NAME does for variables. + This is used indirectly by ASM_OUTPUT_EXTERNAL. */ +#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ +do { \ + tree name_tree = get_identifier (NAME); \ + TREE_ASM_WRITTEN (name_tree) = 1; \ +} while (0) diff --git a/contrib/gcc/config/mips/iris5gas.h b/contrib/gcc/config/mips/iris5gas.h new file mode 100644 index 000000000000..477a55fb647c --- /dev/null +++ b/contrib/gcc/config/mips/iris5gas.h @@ -0,0 +1,34 @@ +/* Definitions of target machine for GNU compiler. Irix version 5 with gas. */ + +/* Enable debugging. */ +#define DBX_DEBUGGING_INFO +#define SDB_DEBUGGING_INFO +#define MIPS_DEBUGGING_INFO +#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG + +/* GNU as does handle DWARF2 directives. */ +#undef DWARF2_UNWIND_INFO +#define DWARF2_UNWIND_INFO 1 + +/* Irix 5 does not have some strange restrictions that Irix 3 had. */ +#undef SET_FILE_NUMBER +#define SET_FILE_NUMBER() ++num_source_filenames +#undef LABEL_AFTER_LOC +#define LABEL_AFTER_LOC(STREAM) + +/* We need to use .esize and .etype instead of .size and .type to + avoid conflicting with ELF directives. These are only recognized + by gas, anyhow, not the native assembler. */ +#undef PUT_SDB_SIZE +#define PUT_SDB_SIZE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.esize\t%d;", (a)); \ +} while (0) + +#undef PUT_SDB_TYPE +#define PUT_SDB_TYPE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a)); \ +} while (0) diff --git a/contrib/gcc/config/mips/iris6.h b/contrib/gcc/config/mips/iris6.h new file mode 100644 index 000000000000..9df7732e8b07 --- /dev/null +++ b/contrib/gcc/config/mips/iris6.h @@ -0,0 +1,567 @@ +/* Definitions of target machine for GNU compiler. Iris version 6. + Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Default to -mabi=n32 and -mips3. */ +#define MIPS_ISA_DEFAULT 3 +#define MIPS_ABI_DEFAULT ABI_N32 +#define MULTILIB_DEFAULTS { "mabi=n32" } + +#ifndef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_ABICALLS|MASK_FLOAT64|MASK_64BIT) +#endif + +#include "mips/iris5.h" +#include "mips/abi64.h" + +/* Irix6 assembler does handle DWARF2 directives. Override setting in + irix5.h file. */ +#undef DWARF2_UNWIND_INFO + +/* For Irix 6, -mabi=64 implies TARGET_LONG64. */ +/* This is handled in override_options. */ + +#undef SUBTARGET_CC1_SPEC +#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}" + +/* We must pass -D_LONGLONG always, even when -ansi is used, because irix6 + system header files require it. This is OK, because gcc never warns + when long long is used in system header files. Alternatively, we can + add support for the SGI builtin type __long_long. */ +#undef CPP_PREDEFINES +#define CPP_PREDEFINES \ + "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \ + -D_LONGLONG -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \ + -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)" + +#undef SUBTARGET_CPP_SIZE_SPEC +#define SUBTARGET_CPP_SIZE_SPEC "\ +%{mabi=32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \ +%{mabi=n32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \ +%{mabi=64: -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \ +%{!mabi*: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}" + +/* We must make -mips3 do what -mlong64 used to do. */ +/* ??? If no mipsX option given, but a mabi=X option is, then should set + _MIPS_ISA based on the mabi=X option. */ +/* ??? If no mabi=X option give, but a mipsX option is, then should set + _MIPS_SIM based on the mipsX option. */ +/* ??? Same for _MIPS_SZINT. */ +/* ??? Same for _MIPS_SZPTR. */ +/* ??? Same for __SIZE_TYPE and __PTRDIFF_TYPE. */ +#undef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "\ +%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE} \ +%{mfp32: -D_MIPS_FPSET=16}%{!mfp32: -D_MIPS_FPSET=32} \ +%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \ +%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \ +%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \ +%{mips4: -D_MIPS_ISA=_MIPS_ISA_MIPS4} \ +%{!mips*: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \ +%{mabi=32: -D_MIPS_SIM=_MIPS_SIM_ABI32} \ +%{mabi=n32: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \ +%{mabi=64: -D_ABI64=3 -D_MIPS_SIM=_ABI64} \ +%{!mabi*: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \ +%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \ +%{mabi=32: -D_MIPS_SZLONG=32} \ +%{mabi=n32: -D_MIPS_SZLONG=32} \ +%{mabi=64: -D_MIPS_SZLONG=64} \ +%{!mabi*: -D_MIPS_SZLONG=32} \ +%{mabi=32: -D_MIPS_SZPTR=32} \ +%{mabi=n32: -D_MIPS_SZPTR=32} \ +%{mabi=64: -D_MIPS_SZPTR=64} \ +%{!mabi*: -D_MIPS_SZPTR=32} \ +%{!mips1:%{!mips2: -D_COMPILER_VERSION=601}} \ +%{!mips*: -U__mips -D__mips=3} \ +%{mabi=32: -U__mips64} \ +%{mabi=n32: -D__mips64} \ +%{mabi=64: -D__mips64} \ +%{!mabi*: -D__mips64}" + +/* Irix 6 uses DWARF-2. */ +#define DWARF2_DEBUGGING_INFO +#define MIPS_DEBUGGING_INFO +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + +/* Force the generation of dwarf .debug_frame sections even if not + compiling -g. This guarantees that we can unwind the stack. */ +#define DWARF2_FRAME_INFO 1 +/* The size in bytes of a DWARF field indicating an offset or length + relative to a debug info section, specified to be 4 bytes in the DWARF-2 + specification. The SGI/MIPS ABI defines it to be the same as PTR_SIZE. */ +#define DWARF_OFFSET_SIZE PTR_SIZE + +/* There is no GNU as port for Irix6 yet, so we set MD_EXEC_PREFIX so that + gcc will automatically find SGI as instead of searching the user's path. + The latter can fail when building a cross compiler if the user has . in + the path before /usr/bin, since then gcc will find and try to use the link + to the cross assembler which can't possibly work. */ + +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/bin/" + +/* We have no need for MD_STARTFILE_PREFIX. */ +#undef MD_STARTFILE_PREFIX + +#undef MACHINE_TYPE +#define MACHINE_TYPE "SGI running IRIX 6.x" + +/* The Irix 6.0.1 assembler doesn't like labels in the text section, so + just avoid emitting them. */ +#define ASM_IDENTIFY_GCC(x) ((void)0) +#define ASM_IDENTIFY_LANGUAGE(x) ((void)0) + +/* Irix 5 stuff that we don't need for Irix 6. */ +/* ??? We do need this for the -mabi=32 switch though. */ +#undef ASM_OUTPUT_UNDEF_FUNCTION +#undef ASM_OUTPUT_EXTERNAL_LIBCALL +#undef ASM_DECLARE_FUNCTION_SIZE + +/* Stuff we need for Irix 6 that isn't in Irix 5. */ + +/* The SGI assembler doesn't like labels before the .ent, so we must output + the .ent and function name here, which is the normal place for it. */ + +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ + do { \ + fputs ("\t.ent\t", STREAM); \ + assemble_name (STREAM, NAME); \ + fputs ("\n", STREAM); \ + assemble_name (STREAM, NAME); \ + fputs (":\n", STREAM); \ + } while (0) + +/* Likewise, the SGI assembler doesn't like labels after the .end, so we + must output the .end here. */ +#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ + do { \ + fputs ("\t.end\t", STREAM); \ + assemble_name (STREAM, NAME); \ + fputs ("\n", STREAM); \ + } while (0) + +/* Tell function_prologue in mips.c that we have already output the .ent/.end + pseudo-ops. */ +#define FUNCTION_NAME_ALREADY_DECLARED + +#undef SET_ASM_OP /* Has no equivalent. See ASM_OUTPUT_DEF below. */ + +#if 0 +/* This is *NOT* how to equate one symbol to another symbol. The assembler + '=' syntax just equates a name to a constant expression. + See ASM_OUTPUT_WEAK_ALIAS. */ + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fprintf ((FILE), "\t"); \ + assemble_name (FILE, LABEL1); \ + fprintf (FILE, " = "); \ + assemble_name (FILE, LABEL2); \ + fprintf (FILE, "\n"); \ + } while (0) +#endif + +/* Define the strings used for the special svr4 .type and .size directives. */ + +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" + +/* This is how we tell the assembler that a symbol is weak. */ + +#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE) \ + do { \ + ASM_GLOBALIZE_LABEL (FILE, NAME); \ + fputs ("\t.weakext\t", FILE); \ + assemble_name (FILE, NAME); \ + if (VALUE) \ + { \ + fputc (' ', FILE); \ + assemble_name (FILE, VALUE); \ + } \ + fputc ('\n', FILE); \ + } while (0) + +#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0) + +#define POPSECTION_ASM_OP ".popsection" + +#define DEBUG_INFO_SECTION ".debug_info,0x7000001e,0,0,1" +#define DEBUG_LINE_SECTION ".debug_line,0x7000001e,0,0,1" +#define SFNAMES_SECTION ".debug_sfnames,0x7000001e,0,0,1" +#define SRCINFO_SECTION ".debug_srcinfo,0x7000001e,0,0,1" +#define MACINFO_SECTION ".debug_macinfo,0x7000001e,0,0,1" +#define PUBNAMES_SECTION ".debug_pubnames,0x7000001e,0,0,1" +#define ARANGES_SECTION ".debug_aranges,0x7000001e,0,0,1" +#define FRAME_SECTION ".debug_frame,0x7000001e,0x08000000,0,1" +#define ABBREV_SECTION ".debug_abbrev,0x7000001e,0,0,1" + +/* ??? If no mabi=X option give, but a mipsX option is, then should depend + on the mipsX option. */ +#undef SUBTARGET_ASM_SPEC +#define SUBTARGET_ASM_SPEC "%{!mabi*:-n32}" + +/* Must pass -g0 to the assembler, otherwise it may overwrite our + debug info with its own debug info. */ +/* Must pass -show instead of -v. */ +/* Must pass -G 0 to the assembler, otherwise we may get warnings about + GOT overflow. */ +/* ??? We pass -w to disable all assembler warnings. The `label should be + inside .ent/.end block' warning that we get for DWARF II debug info labels + is particularly annoying. */ +#undef SUBTARGET_MIPS_AS_ASM_SPEC +#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v:-show} -G 0 -w" + +#undef SUBTARGET_ASM_DEBUGGING_SPEC +#define SUBTARGET_ASM_DEBUGGING_SPEC "-g0" + +/* Stuff for constructors. Start here. */ + +/* The assembler now accepts .section pseudo-ops, but it does not allow + one to change the section in the middle of a function, so we can't use + the INIT_SECTION_ASM_OP code in crtstuff. But we can build up the ctor + and dtor lists this way, so we use -init and -fini to invoke the + do_global_* functions instead of running collect2. */ + +#define BSS_SECTION_ASM_OP ".section\t.bss" +#define CONST_SECTION_ASM_OP_32 "\t.rdata" +#define CONST_SECTION_ASM_OP_64 ".section\t.rodata" + +/* The IRIX 6 assembler .section directive takes four additional args: + section type, flags, entry size, and alignment. The alignment of the + .ctors and .dtors sections needs to be the same as the size of a pointer + so that the linker doesn't add padding between elements. */ +#if defined (CRT_BEGIN) || defined (CRT_END) + +/* If we are included from crtstuff.c, these need to be plain strings. + _MIPS_SZPTR is defined in SUBTARGET_CPP_SPEC above. */ +#if _MIPS_SZPTR == 64 +#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,8" +#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,8" +#else /* _MIPS_SZPTR != 64 */ +#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,4" +#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,4" +#endif /* _MIPS_SZPTR == 64 */ + +#else /* ! (defined (CRT_BEGIN) || defined (CRT_END)) */ + +/* If we are included from varasm.c, these need to depend on -mabi. */ +#define CTORS_SECTION_ASM_OP \ + (Pmode == DImode ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4") +#define DTORS_SECTION_ASM_OP \ + (Pmode == DImode ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4") +#endif /* defined (CRT_BEGIN) || defined (CRT_END) */ + +/* dwarf2out will handle padding this data properly. We definitely don't + want it 8-byte aligned on n32. */ +#define EH_FRAME_SECTION_ASM_OP ".section\t.eh_frame,1,2,0,1" + +/* A default list of other sections which we might be "in" at any given + time. For targets that use additional sections (e.g. .tdesc) you + should override this definition in the target-specific file which + includes this file. */ + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata, in_const, in_ctors, in_dtors + +/* A default list of extra section function definitions. For targets + that use additional sections (e.g. .tdesc) you should override this + definition in the target-specific file which includes this file. */ + +/* ??? rdata_section is now same as svr4 const_section. */ + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ +void \ +sdata_section () \ +{ \ + if (in_section != in_sdata) \ + { \ + fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \ + in_section = in_sdata; \ + } \ +} \ + \ +void \ +rdata_section () \ +{ \ + if (in_section != in_rdata) \ + { \ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) \ + fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP_64); \ + else \ + fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP_32); \ + in_section = in_rdata; \ + } \ +} \ + CTORS_SECTION_FUNCTION \ + DTORS_SECTION_FUNCTION + +#define CTORS_SECTION_FUNCTION \ +void \ +ctors_section () \ +{ \ + if (in_section != in_ctors) \ + { \ + fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ + in_section = in_ctors; \ + } \ +} + +#define DTORS_SECTION_FUNCTION \ +void \ +dtors_section () \ +{ \ + if (in_section != in_dtors) \ + { \ + fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ + in_section = in_dtors; \ + } \ +} + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t ", \ + (Pmode == DImode) ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t ", \ + (Pmode == DImode) ? ".dword" : ".word"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. */ + +#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \ +do { \ + extern FILE *asm_out_text_file; \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \ + fprintf (asm_out_text_file, "\t.section %s,1,6,4,4\n", (NAME)); \ + else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \ + fprintf (F, "\t.section %s,1,2,0,8\n", (NAME)); \ + else \ + fprintf (F, "\t.section %s,1,3,0,8\n", (NAME)); \ +} while (0) + +/* Stuff for constructors. End here. */ + +/* ??? Perhaps just include svr4.h in this file? */ + +/* ??? SGI assembler may core dump when compiling with -g. + Sometimes as succeeds, but then we get a linker error. (cmds.c in 072.sc) + Getting rid of .file solves both problems. */ +#undef ASM_OUTPUT_FILENAME +#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \ +do \ + { \ + fprintf (STREAM, "\t#.file\t%d ", NUM_SOURCE_FILENAMES); \ + output_quoted_string (STREAM, NAME); \ + fputs ("\n", STREAM); \ + } \ +while (0) + +/* ??? SGI assembler gives warning whenever .lcomm is used. */ +#undef ASM_OUTPUT_LOCAL +#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ +do \ + { \ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) \ + { \ + fprintf (STREAM, "%s\n", BSS_SECTION_ASM_OP); \ + mips_declare_object (STREAM, NAME, "", ":\n", 0); \ + ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \ + ASM_OUTPUT_SKIP (STREAM, SIZE); \ + fprintf (STREAM, "\t%s\n", POPSECTION_ASM_OP); \ + } \ + else \ + mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE)); \ + } \ +while (0) + +/* A C statement (sans semicolon) to output to the stdio stream + FILE the assembler definition of uninitialized global DECL named + NAME whose size is SIZE bytes and alignment is ALIGN bytes. + Try to use asm_output_aligned_bss to implement this macro. */ + +#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ + asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) + +/* Write the extra assembler code needed to declare an object properly. */ + +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ +do \ + { \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (STREAM, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (STREAM, NAME); \ + fprintf (STREAM, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + mips_declare_object (STREAM, NAME, "", ":\n", 0); \ + } \ +while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +#undef LOCAL_LABEL_PREFIX +#define LOCAL_LABEL_PREFIX ((mips_abi == ABI_32 || mips_abi == ABI_O64) \ + ? "$" : ".") + +/* Profiling is supported via libprof1.a not -lc_p as in Irix 3. */ +/* ??? If no mabi=X option give, but a mipsX option is, then should depend + on the mipsX option. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!static:%{!shared: \ + %{mabi=32:%{pg:gcrt1.o%s} \ + %{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \ + %{mabi=n32: \ + %{mips4:%{pg:/usr/lib32/mips4/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips4/mcrt1.o%s /usr/lib32/mips4/libprof1.a%s} \ + %{!p:/usr/lib32/mips4/crt1.o%s}}} \ + %{!mips4:%{pg:/usr/lib32/mips3/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips3/mcrt1.o%s /usr/lib32/mips3/libprof1.a%s} \ + %{!p:/usr/lib32/mips3/crt1.o%s}}}} \ + %{mabi=64: \ + %{mips4:%{pg:/usr/lib64/mips4/gcrt1.o} \ + %{!pg:%{p:/usr/lib64/mips4/mcrt1.o /usr/lib64/mips4/libprof1.a} \ + %{!p:/usr/lib64/mips4/crt1.o}}} \ + %{!mips4:%{pg:/usr/lib64/mips3/gcrt1.o} \ + %{!pg:%{p:/usr/lib64/mips3/mcrt1.o /usr/lib64/mips3/libprof1.a} \ + %{!p:/usr/lib64/mips3/crt1.o}}}} \ + %{!mabi*: \ + %{mips4:%{pg:/usr/lib32/mips4/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips4/mcrt1.o%s /usr/lib32/mips4/libprof1.a%s} \ + %{!p:/usr/lib32/mips4/crt1.o%s}}} \ + %{!mips4:%{pg:/usr/lib32/mips3/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips3/mcrt1.o%s /usr/lib32/mips3/libprof1.a%s} \ + %{!p:/usr/lib32/mips3/crt1.o%s}}}}}} \ + %{static: \ + %{mabi=32:%{pg:/usr/lib/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib/nonshared/mcrt1.o%s /usr/lib/nonshared/libprof1.a%s} \ + %{!p:/usr/lib/nonshared/crt1.o%s}}} \ + %{mabi=n32: \ + %{mips4:%{pg:/usr/lib32/mips4/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips4/nonshared/mcrt1.o%s \ + /usr/lib32/mips4/nonshared/libprof1.a%s} \ + %{!p:/usr/lib32/mips4/nonshared/crt1.o%s}}} \ + %{!mips4:%{pg:/usr/lib32/mips3/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \ + /usr/lib32/mips3/nonshared/libprof1.a%s} \ + %{!p:/usr/lib32/mips3/nonshared/crt1.o%s}}}} \ + %{mabi=64: \ + %{mips4:%{pg:/usr/lib64/mips4/nonshared/gcrt1.o} \ + %{!pg:%{p:/usr/lib64/mips4/nonshared/mcrt1.o \ + /usr/lib64/mips4/nonshared/libprof1.a} \ + %{!p:/usr/lib64/mips4/nonshared/crt1.o}}} \ + %{!mips4:%{pg:/usr/lib64/mips3/nonshared/gcrt1.o} \ + %{!pg:%{p:/usr/lib64/mips3/nonshared/mcrt1.o \ + /usr/lib64/mips3/nonshared/libprof1.a} \ + %{!p:/usr/lib64/mips3/nonshared/crt1.o}}}} \ + %{!mabi*: \ + %{mips4:%{pg:/usr/lib32/mips4/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips4/nonshared/mcrt1.o%s \ + /usr/lib32/mips4/nonshared/libprof1.a%s} \ + %{!p:/usr/lib32/mips4/nonshared/crt1.o%s}}} \ + %{!mips4:%{pg:/usr/lib32/mips3/nonshared/gcrt1.o%s} \ + %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \ + /usr/lib32/mips3/nonshared/libprof1.a%s} \ + %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \ + /usr/lib32/mips3/nonshared/libprof1.a%s} \ + %{!p:/usr/lib32/mips3/nonshared/crt1.o%s}}}}}} \ + crtbegin.o%s" + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{mabi=n32: %{mips4:-L/usr/lib32/mips4} %{!mips4:-L/usr/lib32/mips3} \ + -L/usr/lib32} \ + %{mabi=64: %{mips4:-L/usr/lib64/mips4} %{!mips4:-L/usr/lib64/mips3} \ + -L/usr/lib64} \ + %{!mabi*: %{mips4:-L/usr/lib32/mips4} %{!mips4:-L/usr/lib32/mips3} \ + -L/usr/lib32} \ + %{!shared: \ + -dont_warn_unused %{p:libprof1.a%s}%{pg:libprof1.a%s} -lc -warn_unused}" + +/* Avoid getting two warnings for libgcc.a everytime we link. */ +#undef LIBGCC_SPEC +#define LIBGCC_SPEC "-dont_warn_unused -lgcc -warn_unused" + +/* ??? If no mabi=X option give, but a mipsX option is, then should depend + on the mipsX option. */ +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "crtend.o%s \ + %{!shared: \ + %{mabi=32:crtn.o%s}\ + %{mabi=n32:%{mips4:/usr/lib32/mips4/crtn.o%s}\ + %{!mips4:/usr/lib32/mips3/crtn.o%s}}\ + %{mabi=64:%{mips4:/usr/lib64/mips4/crtn.o%s}\ + %{!mips4:/usr/lib64/mips3/crtn.o%s}}\ + %{!mabi*:%{mips4:/usr/lib32/mips4/crtn.o%s}\ + %{!mips4:/usr/lib32/mips3/crtn.o%s}}}" + +/* ??? If no mabi=X option give, but a mipsX option is, then should depend + on the mipsX option. */ +#undef LINK_SPEC +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} %{w} \ +%{static: -non_shared} \ +%{!static: \ + %{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}}} \ +%{rpath} -init __do_global_ctors -fini __do_global_dtors \ +%{shared:-hidden_symbol __do_global_ctors,__do_global_dtors,__EH_FRAME_BEGIN__,__frame_dummy} \ +-_SYSTYPE_SVR4 -woff 131 \ +%{mabi=32: -32}%{mabi=n32: -n32}%{mabi=64: -64}%{!mabi*: -n32}" diff --git a/contrib/gcc/config/mips/linux.h b/contrib/gcc/config/mips/linux.h new file mode 100644 index 000000000000..f4ed424a6056 --- /dev/null +++ b/contrib/gcc/config/mips/linux.h @@ -0,0 +1,99 @@ +/* Definitions for MIPS running Linux-based GNU systems with ELF format. + Copyright (C) 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Required to keep collect2.c happy */ +#undef OBJECT_FORMAT_COFF + +#define HAVE_ATEXIT + +/* If we don't set MASK_ABICALLS, we can't default to PIC. */ +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS) + + +/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add + the GNU/Linux magical crtbegin.o file (see crtstuff.c) which + provides part of the support for getting C++ file-scope static + object constructed before entering `main'. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shared: \ + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\ + crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" + +/* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on + the GNU/Linux magical crtend.o file (see crtstuff.c) which + provides part of the support for getting C++ file-scope static + object constructed before entering `main', followed by a normal + GNU/Linux "finalizer" file, `crtn.o'. */ + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s" + +/* From iris5.h */ +/* -G is incompatible with -KPIC which is the default, so only allow objects + in the small data section if the user explicitly asks for it. */ +#undef MIPS_DEFAULT_GVALUE +#define MIPS_DEFAULT_GVALUE 0 + +/* Borrowed from sparc/linux.h */ +#undef LINK_SPEC +#define LINK_SPEC "-Y P,/usr/lib %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}} \ + %{static:-static}}}" + + +#undef SUBTARGET_ASM_SPEC +#define SUBTARGET_ASM_SPEC "-KPIC" + +/* Undefine the following which were defined in elf.h. This will cause the linux + port to continue to use collect2 for constructors/destructors. These may be removed + when .ctor/.dtor section support is desired. */ + +#undef CTORS_SECTION_ASM_OP +#undef DTORS_SECTION_ASM_OP + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata + +#undef INVOKE__main +#undef NAME__MAIN +#undef SYMBOL__MAIN + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) + +#undef ASM_OUTPUT_CONSTRUCTOR +#undef ASM_OUTPUT_DESTRUCTOR + +#undef CTOR_LIST_BEGIN +#undef CTOR_LIST_END +#undef DTOR_LIST_BEGIN +#undef DTOR_LIST_END + +/* End of undefines to turn off .ctor/.dtor section support */ diff --git a/contrib/gcc/config/mips/mips-5.h b/contrib/gcc/config/mips/mips-5.h new file mode 100644 index 000000000000..f8b0941b0351 --- /dev/null +++ b/contrib/gcc/config/mips/mips-5.h @@ -0,0 +1,46 @@ +/* Definitions of target machine for GNU compiler. MIPS RISC-OS 5.0 + default version. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}" + +#include "mips/mips.h" + +/* Some assemblers have a bug that causes backslash escaped chars in .ascii + to be misassembled, so we just completely avoid it. */ +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) diff --git a/contrib/gcc/config/mips/mips.c b/contrib/gcc/config/mips/mips.c new file mode 100644 index 000000000000..20caaa441790 --- /dev/null +++ b/contrib/gcc/config/mips/mips.c @@ -0,0 +1,8522 @@ +/* Subroutines for insn-output.c for MIPS + Copyright (C) 1989, 90, 91, 93-98, 1999 Free Software Foundation, Inc. + Contributed by A. Lichnewsky, lich@inria.inria.fr. + Changes by Michael Meissner, meissner@osf.org. + 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and + Brendan Eich, brendan@microunity.com. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit + calling convention in 64 bit mode. It doesn't work though, and should + be replaced with something better designed. */ + +#include "config.h" +#include "system.h" +#include <signal.h> + +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "insn-attr.h" +#include "insn-codes.h" +#include "recog.h" +#include "toplev.h" + +#undef MAX /* sys/param.h may also define these */ +#undef MIN + +#include "tree.h" +#include "expr.h" +#include "flags.h" +#include "reload.h" +#include "output.h" + +#if defined(USG) || !defined(HAVE_STAB_H) +#include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */ +#else +#include <stab.h> /* On BSD, use the system's stab.h. */ +#endif /* not USG */ + +#ifdef __GNU_STAB__ +#define STAB_CODE_TYPE enum __stab_debug_code +#else +#define STAB_CODE_TYPE int +#endif + +extern char *mktemp (); +extern tree lookup_name (); + +/* Enumeration for all of the relational tests, so that we can build + arrays indexed by the test type, and not worry about the order + of EQ, NE, etc. */ + +enum internal_test { + ITEST_EQ, + ITEST_NE, + ITEST_GT, + ITEST_GE, + ITEST_LT, + ITEST_LE, + ITEST_GTU, + ITEST_GEU, + ITEST_LTU, + ITEST_LEU, + ITEST_MAX + }; + + +struct constant; +static enum internal_test map_test_to_internal_test PROTO ((enum rtx_code)); +static int mips16_simple_memory_operand PROTO ((rtx, rtx, + enum machine_mode)); +static int m16_check_op PROTO ((rtx, int, int, int)); +static void block_move_loop PROTO ((rtx, rtx, int, int, + rtx, rtx)); +static void block_move_call PROTO ((rtx, rtx, rtx)); +static FILE *make_temp_file PROTO ((void)); +static void save_restore_insns PROTO ((int, rtx, + long, FILE *)); +static void mips16_output_gp_offset PROTO ((FILE *, rtx)); +static void mips16_fp_args PROTO ((FILE *, int, int)); +static void build_mips16_function_stub PROTO ((FILE *)); +static void mips16_optimize_gp PROTO ((rtx)); +static rtx add_constant PROTO ((struct constant **, + rtx, + enum machine_mode)); +static void dump_constants PROTO ((struct constant *, + rtx)); +static rtx mips_find_symbol PROTO ((rtx)); +static void abort_with_insn PROTO ((rtx, const char *)) + ATTRIBUTE_NORETURN; + + +/* Global variables for machine-dependent things. */ + +/* Threshold for data being put into the small data/bss area, instead + of the normal data area (references to the small data/bss area take + 1 instruction, and use the global pointer, references to the normal + data area takes 2 instructions). */ +int mips_section_threshold = -1; + +/* Count the number of .file directives, so that .loc is up to date. */ +int num_source_filenames = 0; + +/* Count the number of sdb related labels are generated (to find block + start and end boundaries). */ +int sdb_label_count = 0; + +/* Next label # for each statement for Silicon Graphics IRIS systems. */ +int sym_lineno = 0; + +/* Non-zero if inside of a function, because the stupid MIPS asm can't + handle .files inside of functions. */ +int inside_function = 0; + +/* Files to separate the text and the data output, so that all of the data + can be emitted before the text, which will mean that the assembler will + generate smaller code, based on the global pointer. */ +FILE *asm_out_data_file; +FILE *asm_out_text_file; + +/* Linked list of all externals that are to be emitted when optimizing + for the global pointer if they haven't been declared by the end of + the program with an appropriate .comm or initialization. */ + +struct extern_list +{ + struct extern_list *next; /* next external */ + char *name; /* name of the external */ + int size; /* size in bytes */ +} *extern_head = 0; + +/* Name of the file containing the current function. */ +const char *current_function_file = ""; + +/* Warning given that Mips ECOFF can't support changing files + within a function. */ +int file_in_function_warning = FALSE; + +/* Whether to suppress issuing .loc's because the user attempted + to change the filename within a function. */ +int ignore_line_number = FALSE; + +/* Number of nested .set noreorder, noat, nomacro, and volatile requests. */ +int set_noreorder; +int set_noat; +int set_nomacro; +int set_volatile; + +/* The next branch instruction is a branch likely, not branch normal. */ +int mips_branch_likely; + +/* Count of delay slots and how many are filled. */ +int dslots_load_total; +int dslots_load_filled; +int dslots_jump_total; +int dslots_jump_filled; + +/* # of nops needed by previous insn */ +int dslots_number_nops; + +/* Number of 1/2/3 word references to data items (ie, not jal's). */ +int num_refs[3]; + +/* registers to check for load delay */ +rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4; + +/* Cached operands, and operator to compare for use in set/branch on + condition codes. */ +rtx branch_cmp[2]; + +/* what type of branch to use */ +enum cmp_type branch_type; + +/* Number of previously seen half-pic pointers and references. */ +static int prev_half_pic_ptrs = 0; +static int prev_half_pic_refs = 0; + +/* which cpu are we scheduling for */ +enum processor_type mips_cpu; + +/* which instruction set architecture to use. */ +int mips_isa; + +#ifdef MIPS_ABI_DEFAULT +/* Which ABI to use. This is defined to a constant in mips.h if the target + doesn't support multiple ABIs. */ +int mips_abi; +#endif + +/* Strings to hold which cpu and instruction set architecture to use. */ +const char *mips_cpu_string; /* for -mcpu=<xxx> */ +const char *mips_isa_string; /* for -mips{1,2,3,4} */ +const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */ + +/* Whether we are generating mips16 code. This is a synonym for + TARGET_MIPS16, and exists for use as an attribute. */ +int mips16; + +/* This variable is set by -mno-mips16. We only care whether + -mno-mips16 appears or not, and using a string in this fashion is + just a way to avoid using up another bit in target_flags. */ +const char *mips_no_mips16_string; + +/* This is only used to determine if an type size setting option was + explicitly specified (-mlong64, -mint64, -mlong32). The specs + set this option if such an option is used. */ +const char *mips_explicit_type_size_string; + +/* Whether we are generating mips16 hard float code. In mips16 mode + we always set TARGET_SOFT_FLOAT; this variable is nonzero if + -msoft-float was not specified by the user, which means that we + should arrange to call mips32 hard floating point code. */ +int mips16_hard_float; + +/* This variable is set by -mentry. We only care whether -mentry + appears or not, and using a string in this fashion is just a way to + avoid using up another bit in target_flags. */ +const char *mips_entry_string; + +/* Whether we should entry and exit pseudo-ops in mips16 mode. */ +int mips_entry; + +/* If TRUE, we split addresses into their high and low parts in the RTL. */ +int mips_split_addresses; + +/* Generating calls to position independent functions? */ +enum mips_abicalls_type mips_abicalls; + +/* High and low marks for floating point values which we will accept + as legitimate constants for LEGITIMATE_CONSTANT_P. These are + initialized in override_options. */ +REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow; + +/* Mode used for saving/restoring general purpose registers. */ +static enum machine_mode gpr_mode; + +/* Array giving truth value on whether or not a given hard register + can support a given mode. */ +char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; + +/* Current frame information calculated by compute_frame_size. */ +struct mips_frame_info current_frame_info; + +/* Zero structure to initialize current_frame_info. */ +struct mips_frame_info zero_frame_info; + +/* Temporary filename used to buffer .text until end of program + for -mgpopt. */ +static char *temp_filename; + +/* Pseudo-reg holding the address of the current function when + generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used + by mips_finalize_pic if it was created. */ +rtx embedded_pic_fnaddr_rtx; + +/* The length of all strings seen when compiling for the mips16. This + is used to tell how many strings are in the constant pool, so that + we can see if we may have an overflow. This is reset each time the + constant pool is output. */ +int mips_string_length; + +/* Pseudo-reg holding the value of $28 in a mips16 function which + refers to GP relative global variables. */ +rtx mips16_gp_pseudo_rtx; + +/* In mips16 mode, we build a list of all the string constants we see + in a particular function. */ + +struct string_constant +{ + struct string_constant *next; + char *label; +}; + +static struct string_constant *string_constants; + +/* List of all MIPS punctuation characters used by print_operand. */ +char mips_print_operand_punct[256]; + +/* Map GCC register number to debugger register number. */ +int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; + +/* Buffer to use to enclose a load/store operation with %{ %} to + turn on .set volatile. */ +static char volatile_buffer[60]; + +/* Hardware names for the registers. If -mrnames is used, this + will be overwritten with mips_sw_reg_names. */ + +char mips_reg_names[][8] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", + "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", + "$fcc5","$fcc6","$fcc7","$rap" +}; + +/* Mips software names for the registers, used to overwrite the + mips_reg_names array. */ + +char mips_sw_reg_names[][8] = +{ + "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3", + "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", + "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", + "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra", + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", + "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", + "$fcc5","$fcc6","$fcc7","$rap" +}; + +/* Map hard register number to register class */ +enum reg_class mips_regno_to_class[] = +{ + GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS, + M16_REGS, M16_REGS, M16_REGS, M16_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + T_REG, GR_REGS, GR_REGS, GR_REGS, + GR_REGS, GR_REGS, GR_REGS, GR_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, + HI_REG, LO_REG, HILO_REG, ST_REGS, + ST_REGS, ST_REGS, ST_REGS, ST_REGS, + ST_REGS, ST_REGS, ST_REGS, GR_REGS +}; + +/* Map register constraint character to register class. */ +enum reg_class mips_char_to_class[256] = +{ + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, + NO_REGS, NO_REGS, NO_REGS, NO_REGS, +}; + + +/* Return truth value of whether OP can be used as an operands + where a register or 16 bit unsigned integer is needed. */ + +int +uns_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op)) + return 1; + + return register_operand (op, mode); +} + +/* Return truth value of whether OP can be used as an operands + where a 16 bit integer is needed */ + +int +arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT && SMALL_INT (op)) + return 1; + + /* On the mips16, a GP relative value is a signed 16 bit offset. */ + if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op)) + return 1; + + return register_operand (op, mode); +} + +/* Return truth value of whether OP can be used as an operand in a two + address arithmetic insn (such as set 123456,%o4) of mode MODE. */ + +int +arith32_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT) + return 1; + + return register_operand (op, mode); +} + +/* Return truth value of whether OP is a integer which fits in 16 bits */ + +int +small_int (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); +} + +/* Return truth value of whether OP is a 32 bit integer which is too big to + be loaded with one instruction. */ + +int +large_int (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + HOST_WIDE_INT value; + + if (GET_CODE (op) != CONST_INT) + return 0; + + value = INTVAL (op); + + /* ior reg,$r0,value */ + if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0) + return 0; + + /* subu reg,$r0,value */ + if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767) + return 0; + + /* lui reg,value>>16 */ + if ((value & 0x0000ffff) == 0) + return 0; + + return 1; +} + +/* Return truth value of whether OP is a register or the constant 0. + In mips16 mode, we only accept a register, since the mips16 does + not have $0. */ + +int +reg_or_0_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case CONST_INT: + if (TARGET_MIPS16) + return 0; + return INTVAL (op) == 0; + + case CONST_DOUBLE: + if (TARGET_MIPS16) + return 0; + return op == CONST0_RTX (mode); + + case REG: + case SUBREG: + return register_operand (op, mode); + + default: + break; + } + + return 0; +} + +/* Return truth value of whether OP is a register or the constant 0, + even in mips16 mode. */ + +int +true_reg_or_0_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case CONST_INT: + return INTVAL (op) == 0; + + case CONST_DOUBLE: + return op == CONST0_RTX (mode); + + case REG: + case SUBREG: + return register_operand (op, mode); + + default: + break; + } + + return 0; +} + +/* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ + +int +mips_const_double_ok (op, mode) + rtx op; + enum machine_mode mode; +{ + REAL_VALUE_TYPE d; + + if (GET_CODE (op) != CONST_DOUBLE) + return 0; + + if (mode == VOIDmode) + return 1; + + if (mode != SFmode && mode != DFmode) + return 0; + + if (op == CONST0_RTX (mode)) + return 1; + + /* ??? li.s does not work right with SGI's Irix 6 assembler. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI) + return 0; + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + + if (REAL_VALUE_ISNAN (d)) + return FALSE; + + if (REAL_VALUE_NEGATIVE (d)) + d = REAL_VALUE_NEGATE (d); + + if (mode == DFmode) + { + if (REAL_VALUES_LESS (d, dfhigh) + && REAL_VALUES_LESS (dflow, d)) + return 1; + } + else + { + if (REAL_VALUES_LESS (d, sfhigh) + && REAL_VALUES_LESS (sflow, d)) + return 1; + } + + return 0; +} + +/* Accept the floating point constant 1 in the appropriate mode. */ + +int +const_float_1_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + REAL_VALUE_TYPE d; + static REAL_VALUE_TYPE onedf; + static REAL_VALUE_TYPE onesf; + static int one_initialized; + + if (GET_CODE (op) != CONST_DOUBLE + || mode != GET_MODE (op) + || (mode != DFmode && mode != SFmode)) + return 0; + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + + /* We only initialize these values if we need them, since we will + never get called unless mips_isa >= 4. */ + if (! one_initialized) + { + onedf = REAL_VALUE_ATOF ("1.0", DFmode); + onesf = REAL_VALUE_ATOF ("1.0", SFmode); + one_initialized = 1; + } + + if (mode == DFmode) + return REAL_VALUES_EQUAL (d, onedf); + else + return REAL_VALUES_EQUAL (d, onesf); +} + +/* Return true if a memory load or store of REG plus OFFSET in MODE + can be represented in a single word on the mips16. */ + +static int +mips16_simple_memory_operand (reg, offset, mode) + rtx reg; + rtx offset; + enum machine_mode mode; +{ + int size, off; + + if (mode == BLKmode) + { + /* We can't tell, because we don't know how the value will + eventually be accessed. Returning 0 here does no great + harm; it just prevents some possible instruction scheduling. */ + return 0; + } + + size = GET_MODE_SIZE (mode); + + if (INTVAL (offset) % size != 0) + return 0; + if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4) + off = 0x100; + else + off = 0x20; + if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size) + return 1; + return 0; +} + +/* Return truth value if a memory operand fits in a single instruction + (ie, register + small offset). */ + +int +simple_memory_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + rtx addr, plus0, plus1; + + /* Eliminate non-memory operations */ + if (GET_CODE (op) != MEM) + return 0; + + /* dword operations really put out 2 instructions, so eliminate them. */ + /* ??? This isn't strictly correct. It is OK to accept multiword modes + here, since the length attributes are being set correctly, but only + if the address is offsettable. LO_SUM is not offsettable. */ + if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD) + return 0; + + /* Decode the address now. */ + addr = XEXP (op, 0); + switch (GET_CODE (addr)) + { + case REG: + case LO_SUM: + return 1; + + case CONST_INT: + if (TARGET_MIPS16) + return 0; + return SMALL_INT (op); + + case PLUS: + plus0 = XEXP (addr, 0); + plus1 = XEXP (addr, 1); + if (GET_CODE (plus0) == REG + && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1) + && (! TARGET_MIPS16 + || mips16_simple_memory_operand (plus0, plus1, mode))) + return 1; + + else if (GET_CODE (plus1) == REG + && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0) + && (! TARGET_MIPS16 + || mips16_simple_memory_operand (plus1, plus0, mode))) + return 1; + + else + return 0; + +#if 0 + /* We used to allow small symbol refs here (ie, stuff in .sdata + or .sbss), but this causes some bugs in G++. Also, it won't + interfere if the MIPS linker rewrites the store instruction + because the function is PIC. */ + + case LABEL_REF: /* never gp relative */ + break; + + case CONST: + /* If -G 0, we can never have a GP relative memory operation. + Also, save some time if not optimizing. */ + if (!TARGET_GP_OPT) + return 0; + + { + rtx offset = const0_rtx; + addr = eliminate_constant_term (XEXP (addr, 0), &offset); + if (GET_CODE (op) != SYMBOL_REF) + return 0; + + /* let's be paranoid.... */ + if (! SMALL_INT (offset)) + return 0; + } + + /* fall through */ + + case SYMBOL_REF: + return SYMBOL_REF_FLAG (addr); +#endif + + /* This SYMBOL_REF case is for the mips16. If the above case is + reenabled, this one should be merged in. */ + case SYMBOL_REF: + /* References to the constant pool on the mips16 use a small + offset if the function is small. The only time we care about + getting this right is during delayed branch scheduling, so + don't need to check until then. The machine_dependent_reorg + function will set the total length of the instructions used + in the function in current_frame_info. If that is small + enough, we know for sure that this is a small offset. It + would be better if we could take into account the location of + the instruction within the function, but we can't, because we + don't know where we are. */ + if (TARGET_MIPS16 + && CONSTANT_POOL_ADDRESS_P (addr) + && current_frame_info.insns_len > 0) + { + long size; + + size = current_frame_info.insns_len + get_pool_size (); + if (GET_MODE_SIZE (mode) == 4) + return size < 4 * 0x100; + else if (GET_MODE_SIZE (mode) == 8) + return size < 8 * 0x20; + else + return 0; + } + + return 0; + + default: + break; + } + + return 0; +} + +/* Return nonzero for a memory address that can be used to load or store + a doubleword. */ + +int +double_memory_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + rtx addr; + + if (GET_CODE (op) != MEM + || ! memory_operand (op, mode)) + { + /* During reload, we accept a pseudo register if it has an + appropriate memory address. If we don't do this, we will + wind up reloading into a register, and then reloading that + register from memory, when we could just reload directly from + memory. */ + if (reload_in_progress + && GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (op)] < 0 + && reg_equiv_mem[REGNO (op)] != 0 + && double_memory_operand (reg_equiv_mem[REGNO (op)], mode)) + return 1; + + /* All reloaded addresses are valid in TARGET_64BIT mode. This is + the same test performed for 'm' in find_reloads. */ + + if (reload_in_progress + && TARGET_64BIT + && (GET_CODE (op) == MEM + || (GET_CODE (op) == REG + && REGNO (op) >= FIRST_PSEUDO_REGISTER + && reg_renumber[REGNO (op)] < 0))) + return 1; + + if (reload_in_progress + && TARGET_MIPS16 + && GET_CODE (op) == MEM) + { + rtx addr; + + addr = XEXP (op, 0); + + /* During reload on the mips16, we accept a large offset + from the frame pointer or the stack pointer. This large + address will get reloaded anyhow. */ + if (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 0)) == REG + && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM + || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM) + && ((GET_CODE (XEXP (addr, 1)) == CONST_INT + && ! SMALL_INT (XEXP (addr, 1))) + || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1))))) + return 1; + + /* Similarly, we accept a case where the memory address is + itself on the stack, and will be reloaded. */ + if (GET_CODE (addr) == MEM) + { + rtx maddr; + + maddr = XEXP (addr, 0); + if (GET_CODE (maddr) == PLUS + && GET_CODE (XEXP (maddr, 0)) == REG + && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM + || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM) + && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT + && ! SMALL_INT (XEXP (maddr, 1))) + || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1))))) + return 1; + } + + /* We also accept the same case when we have a 16 bit signed + offset mixed in as well. The large address will get + reloaded, and the 16 bit offset will be OK. */ + if (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 0)) == MEM + && GET_CODE (XEXP (addr, 1)) == CONST_INT + && SMALL_INT (XEXP (addr, 1))) + { + addr = XEXP (XEXP (addr, 0), 0); + if (GET_CODE (addr) == PLUS + && GET_CODE (XEXP (addr, 0)) == REG + && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM + || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM) + && ((GET_CODE (XEXP (addr, 1)) == CONST_INT + && ! SMALL_INT (XEXP (addr, 1))) + || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1))))) + return 1; + } + } + + return 0; + } + + if (TARGET_64BIT) + { + /* In this case we can use an instruction like sd. */ + return 1; + } + + /* Make sure that 4 added to the address is a valid memory address. + This essentially just checks for overflow in an added constant. */ + + addr = XEXP (op, 0); + + if (CONSTANT_ADDRESS_P (addr)) + return 1; + + return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT + ? SImode + : SFmode), + plus_constant_for_output (addr, 4)); +} + +/* Return nonzero if the code of this rtx pattern is EQ or NE. */ + +int +equality_op (op, mode) + rtx op; + enum machine_mode mode; +{ + if (mode != GET_MODE (op)) + return 0; + + return GET_CODE (op) == EQ || GET_CODE (op) == NE; +} + +/* Return nonzero if the code is a relational operations (EQ, LE, etc.) */ + +int +cmp_op (op, mode) + rtx op; + enum machine_mode mode; +{ + if (mode != GET_MODE (op)) + return 0; + + return GET_RTX_CLASS (GET_CODE (op)) == '<'; +} + +/* Return nonzero if the operand is either the PC or a label_ref. */ + +int +pc_or_label_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (op == pc_rtx) + return 1; + + if (GET_CODE (op) == LABEL_REF) + return 1; + + return 0; +} + +/* Test for a valid operand for a call instruction. + Don't allow the arg pointer register or virtual regs + since they may change into reg + const, which the patterns + can't handle yet. */ + +int +call_insn_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (CONSTANT_ADDRESS_P (op) + || (GET_CODE (op) == REG && op != arg_pointer_rtx + && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER + && REGNO (op) <= LAST_VIRTUAL_REGISTER))); +} + +/* Return nonzero if OPERAND is valid as a source operand for a move + instruction. */ + +int +move_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + /* Accept any general operand after reload has started; doing so + avoids losing if reload does an in-place replacement of a register + with a SYMBOL_REF or CONST. */ + return (general_operand (op, mode) + && (! (mips_split_addresses && mips_check_split (op, mode)) + || reload_in_progress || reload_completed) + && ! (TARGET_MIPS16 + && GET_CODE (op) == SYMBOL_REF + && ! mips16_constant (op, mode, 1, 0))); +} + +/* Return nonzero if OPERAND is valid as a source operand for movdi. + This accepts not only general_operand, but also sign extended + constants and registers. We need to accept sign extended constants + in case a sign extended register which is used in an expression, + and is equivalent to a constant, is spilled. */ + +int +movdi_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && (GET_MODE (XEXP (op, 0)) == SImode + || (GET_CODE (XEXP (op, 0)) == CONST_INT + && GET_MODE (XEXP (op, 0)) == VOIDmode)) + && (register_operand (XEXP (op, 0), SImode) + || immediate_operand (XEXP (op, 0), SImode))) + return 1; + + return (general_operand (op, mode) + && ! (TARGET_MIPS16 + && GET_CODE (op) == SYMBOL_REF + && ! mips16_constant (op, mode, 1, 0))); +} + +/* Like register_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_register_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return register_operand (op, mode); +} + +/* Like reg_or_0_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_reg_or_0_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return reg_or_0_operand (op, mode); +} + +/* Like uns_arith_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_uns_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return uns_arith_operand (op, mode); +} + +/* Like arith_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return arith_operand (op, mode); +} + +/* Like nonmemory_operand, but when in 64 bit mode also accept a sign + extend of a 32 bit register, since the value is known to be already + sign extended. */ + +int +se_nonmemory_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return nonmemory_operand (op, mode); +} + +/* Like nonimmediate_operand, but when in 64 bit mode also accept a + sign extend of a 32 bit register, since the value is known to be + already sign extended. */ + +int +se_nonimmediate_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (TARGET_64BIT + && mode == DImode + && GET_CODE (op) == SIGN_EXTEND + && GET_MODE (op) == DImode + && GET_MODE (XEXP (op, 0)) == SImode + && register_operand (XEXP (op, 0), SImode)) + return 1; + + return nonimmediate_operand (op, mode); +} + +/* Accept any operand that can appear in a mips16 constant table + instruction. We can't use any of the standard operand functions + because for these instructions we accept values that are not + accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */ + +int +consttable_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return CONSTANT_P (op); +} + +/* Return nonzero if we split the address into high and low parts. */ + +/* ??? We should also handle reg+array somewhere. We get four + instructions currently, lui %hi/addui %lo/addui reg/lw. Better is + lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept + (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken + out of the address, then we have 4 instructions to combine. Perhaps + add a 3->2 define_split for combine. */ + +/* ??? We could also split a CONST_INT here if it is a large_int(). + However, it doesn't seem to be very useful to have %hi(constant). + We would be better off by doing the masking ourselves and then putting + the explicit high part of the constant in the RTL. This will give better + optimization. Also, %hi(constant) needs assembler changes to work. + There is already a define_split that does this. */ + +int +mips_check_split (address, mode) + rtx address; + enum machine_mode mode; +{ + /* ??? This is the same check used in simple_memory_operand. + We use it here because LO_SUM is not offsettable. */ + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return 0; + + if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address)) + || (GET_CODE (address) == CONST + && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF + && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0))) + || GET_CODE (address) == LABEL_REF) + return 1; + + return 0; +} + +/* We need a lot of little routines to check constant values on the + mips16. These are used to figure out how long the instruction will + be. It would be much better to do this using constraints, but + there aren't nearly enough letters available. */ + +static int +m16_check_op (op, low, high, mask) + rtx op; + int low; + int high; + int mask; +{ + return (GET_CODE (op) == CONST_INT + && INTVAL (op) >= low + && INTVAL (op) <= high + && (INTVAL (op) & mask) == 0); +} + +int +m16_uimm3_b (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, 0x1, 0x8, 0); +} + +int +m16_simm4_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x8, 0x7, 0); +} + +int +m16_nsimm4_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x7, 0x8, 0); +} + +int +m16_simm5_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x10, 0xf, 0); +} + +int +m16_nsimm5_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0xf, 0x10, 0); +} + +int +m16_uimm5_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3); +} + +int +m16_nuimm5_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3); +} + +int +m16_simm8_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x80, 0x7f, 0); +} + +int +m16_nsimm8_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x7f, 0x80, 0); +} + +int +m16_uimm8_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, 0x0, 0xff, 0); +} + +int +m16_nuimm8_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0xff, 0x0, 0); +} + +int +m16_uimm8_m1_1 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, - 0x1, 0xfe, 0); +} + +int +m16_uimm8_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, 0x0, 0xff << 2, 3); +} + +int +m16_nuimm8_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0xff) << 2, 0x0, 3); +} + +int +m16_simm8_8 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7); +} + +int +m16_nsimm8_8 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7); +} + +/* References to the string table on the mips16 only use a small + offset if the function is small. See the comment in the SYMBOL_REF + case in simple_memory_operand. We can't check for LABEL_REF here, + because the offset is always large if the label is before the + referencing instruction. */ + +int +m16_usym8_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) == SYMBOL_REF + && SYMBOL_REF_FLAG (op) + && current_frame_info.insns_len > 0 + && XSTR (op, 0)[0] == '*' + && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) == 0 + && (current_frame_info.insns_len + get_pool_size () + mips_string_length + < 4 * 0x100)) + { + struct string_constant *l; + + /* Make sure this symbol is on thelist of string constants to be + output for this function. It is possible that it has already + been output, in which case this requires a large offset. */ + for (l = string_constants; l != NULL; l = l->next) + if (strcmp (l->label, XSTR (op, 0)) == 0) + return 1; + } + + return 0; +} + +int +m16_usym5_4 (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) == SYMBOL_REF + && SYMBOL_REF_FLAG (op) + && current_frame_info.insns_len > 0 + && XSTR (op, 0)[0] == '*' + && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) == 0 + && (current_frame_info.insns_len + get_pool_size () + mips_string_length + < 4 * 0x20)) + { + struct string_constant *l; + + /* Make sure this symbol is on thelist of string constants to be + output for this function. It is possible that it has already + been output, in which case this requires a large offset. */ + for (l = string_constants; l != NULL; l = l->next) + if (strcmp (l->label, XSTR (op, 0)) == 0) + return 1; + } + + return 0; +} + +/* Returns an operand string for the given instruction's delay slot, + after updating filled delay slot statistics. + + We assume that operands[0] is the target register that is set. + + In order to check the next insn, most of this functionality is moved + to FINAL_PRESCAN_INSN, and we just set the global variables that + it needs. */ + +/* ??? This function no longer does anything useful, because final_prescan_insn + now will never emit a nop. */ + +char * +mips_fill_delay_slot (ret, type, operands, cur_insn) + char *ret; /* normal string to return */ + enum delay_type type; /* type of delay */ + rtx operands[]; /* operands to use */ + rtx cur_insn; /* current insn */ +{ + register rtx set_reg; + register enum machine_mode mode; + register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX; + register int num_nops; + + if (type == DELAY_LOAD || type == DELAY_FCMP) + num_nops = 1; + + else if (type == DELAY_HILO) + num_nops = 2; + + else + num_nops = 0; + + /* Make sure that we don't put nop's after labels. */ + next_insn = NEXT_INSN (cur_insn); + while (next_insn != 0 && GET_CODE (next_insn) == NOTE) + next_insn = NEXT_INSN (next_insn); + + dslots_load_total += num_nops; + if (TARGET_DEBUG_F_MODE + || !optimize + || type == DELAY_NONE + || operands == 0 + || cur_insn == 0 + || next_insn == 0 + || GET_CODE (next_insn) == CODE_LABEL + || (set_reg = operands[0]) == 0) + { + dslots_number_nops = 0; + mips_load_reg = 0; + mips_load_reg2 = 0; + mips_load_reg3 = 0; + mips_load_reg4 = 0; + return ret; + } + + set_reg = operands[0]; + if (set_reg == 0) + return ret; + + while (GET_CODE (set_reg) == SUBREG) + set_reg = SUBREG_REG (set_reg); + + mode = GET_MODE (set_reg); + dslots_number_nops = num_nops; + mips_load_reg = set_reg; + if (GET_MODE_SIZE (mode) + > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD)) + mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1); + else + mips_load_reg2 = 0; + + if (type == DELAY_HILO) + { + mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST); + mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1); + } + else + { + mips_load_reg3 = 0; + mips_load_reg4 = 0; + } + + return ret; +} + + +/* Determine whether a memory reference takes one (based off of the GP + pointer), two (normal), or three (label + reg) instructions, and bump the + appropriate counter for -mstats. */ + +void +mips_count_memory_refs (op, num) + rtx op; + int num; +{ + int additional = 0; + int n_words = 0; + rtx addr, plus0, plus1; + enum rtx_code code0, code1; + int looping; + + if (TARGET_DEBUG_B_MODE) + { + fprintf (stderr, "\n========== mips_count_memory_refs:\n"); + debug_rtx (op); + } + + /* Skip MEM if passed, otherwise handle movsi of address. */ + addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0); + + /* Loop, going through the address RTL. */ + do + { + looping = FALSE; + switch (GET_CODE (addr)) + { + case REG: + case CONST_INT: + case LO_SUM: + break; + + case PLUS: + plus0 = XEXP (addr, 0); + plus1 = XEXP (addr, 1); + code0 = GET_CODE (plus0); + code1 = GET_CODE (plus1); + + if (code0 == REG) + { + additional++; + addr = plus1; + looping = 1; + continue; + } + + if (code0 == CONST_INT) + { + addr = plus1; + looping = 1; + continue; + } + + if (code1 == REG) + { + additional++; + addr = plus0; + looping = 1; + continue; + } + + if (code1 == CONST_INT) + { + addr = plus0; + looping = 1; + continue; + } + + if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST) + { + addr = plus0; + looping = 1; + continue; + } + + if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST) + { + addr = plus1; + looping = 1; + continue; + } + + break; + + case LABEL_REF: + n_words = 2; /* always 2 words */ + break; + + case CONST: + addr = XEXP (addr, 0); + looping = 1; + continue; + + case SYMBOL_REF: + n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2; + break; + + default: + break; + } + } + while (looping); + + if (n_words == 0) + return; + + n_words += additional; + if (n_words > 3) + n_words = 3; + + num_refs[n_words-1] += num; +} + + +/* Return RTL for the offset from the current function to the argument. + + ??? Which argument is this? */ + +rtx +embedded_pic_offset (x) + rtx x; +{ + if (embedded_pic_fnaddr_rtx == NULL) + { + rtx seq; + + embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode); + + /* Output code at function start to initialize the pseudo-reg. */ + /* ??? We used to do this in FINALIZE_PIC, but that does not work for + inline functions, because it is called after RTL for the function + has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however + does not get copied, and ends up not matching the rest of the RTL. + This solution works, but means that we get unnecessary code to + initialize this value every time a function is inlined into another + function. */ + start_sequence (); + emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx, + XEXP (DECL_RTL (current_function_decl), 0))); + seq = gen_sequence (); + end_sequence (); + push_topmost_sequence (); + emit_insn_after (seq, get_insns ()); + pop_topmost_sequence (); + } + + return gen_rtx (CONST, Pmode, + gen_rtx (MINUS, Pmode, x, + XEXP (DECL_RTL (current_function_decl), 0))); +} + +/* Return the appropriate instructions to move one operand to another. */ + +const char * +mips_move_1word (operands, insn, unsignedp) + rtx operands[]; + rtx insn; + int unsignedp; +{ + const char *ret = 0; + rtx op0 = operands[0]; + rtx op1 = operands[1]; + enum rtx_code code0 = GET_CODE (op0); + enum rtx_code code1 = GET_CODE (op1); + enum machine_mode mode = GET_MODE (op0); + int subreg_word0 = 0; + int subreg_word1 = 0; + enum delay_type delay = DELAY_NONE; + + while (code0 == SUBREG) + { + subreg_word0 += SUBREG_WORD (op0); + op0 = SUBREG_REG (op0); + code0 = GET_CODE (op0); + } + + while (code1 == SUBREG) + { + subreg_word1 += SUBREG_WORD (op1); + op1 = SUBREG_REG (op1); + code1 = GET_CODE (op1); + } + + /* For our purposes, a condition code mode is the same as SImode. */ + if (mode == CCmode) + mode = SImode; + + if (code0 == REG) + { + int regno0 = REGNO (op0) + subreg_word0; + + if (code1 == REG) + { + int regno1 = REGNO (op1) + subreg_word1; + + /* Just in case, don't do anything for assigning a register + to itself, unless we are filling a delay slot. */ + if (regno0 == regno1 && set_nomacro == 0) + ret = ""; + + else if (GP_REG_P (regno0)) + { + if (GP_REG_P (regno1)) + ret = "move\t%0,%1"; + + else if (MD_REG_P (regno1)) + { + delay = DELAY_HILO; + if (regno1 != HILO_REGNUM) + ret = "mf%1\t%0"; + else + ret = "mflo\t%0"; + } + + else if (ST_REG_P (regno1) && mips_isa >= 4) + ret = "li\t%0,1\n\tmovf\t%0,%.,%1"; + + else + { + delay = DELAY_LOAD; + if (FP_REG_P (regno1)) + ret = "mfc1\t%0,%1"; + + else if (regno1 == FPSW_REGNUM && mips_isa < 4) + ret = "cfc1\t%0,$31"; + } + } + + else if (FP_REG_P (regno0)) + { + if (GP_REG_P (regno1)) + { + delay = DELAY_LOAD; + ret = "mtc1\t%1,%0"; + } + + if (FP_REG_P (regno1)) + ret = "mov.s\t%0,%1"; + } + + else if (MD_REG_P (regno0)) + { + if (GP_REG_P (regno1)) + { + delay = DELAY_HILO; + if (regno0 != HILO_REGNUM && ! TARGET_MIPS16) + ret = "mt%0\t%1"; + } + } + + else if (regno0 == FPSW_REGNUM && mips_isa < 4) + { + if (GP_REG_P (regno1)) + { + delay = DELAY_LOAD; + ret = "ctc1\t%0,$31"; + } + } + } + + else if (code1 == MEM) + { + delay = DELAY_LOAD; + + if (TARGET_STATS) + mips_count_memory_refs (op1, 1); + + if (GP_REG_P (regno0)) + { + /* For loads, use the mode of the memory item, instead of the + target, so zero/sign extend can use this code as well. */ + switch (GET_MODE (op1)) + { + default: + break; + case SFmode: + ret = "lw\t%0,%1"; + break; + case SImode: + case CCmode: + ret = ((unsignedp && TARGET_64BIT) + ? "lwu\t%0,%1" + : "lw\t%0,%1"); + break; + case HImode: + ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1"; + break; + case QImode: + ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1"; + break; + } + } + + else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode)) + ret = "l.s\t%0,%1"; + + if (ret != (char *)0 && MEM_VOLATILE_P (op1)) + { + size_t i = strlen (ret); + if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) + abort (); + + sprintf (volatile_buffer, "%%{%s%%}", ret); + ret = volatile_buffer; + } + } + + else if (code1 == CONST_INT + || (code1 == CONST_DOUBLE + && GET_MODE (op1) == VOIDmode)) + { + if (code1 == CONST_DOUBLE) + { + /* This can happen when storing constants into long long + bitfields. Just store the least significant word of + the value. */ + operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); + } + + if (INTVAL (op1) == 0 && ! TARGET_MIPS16) + { + if (GP_REG_P (regno0)) + ret = "move\t%0,%z1"; + + else if (FP_REG_P (regno0)) + { + delay = DELAY_LOAD; + ret = "mtc1\t%z1,%0"; + } + + else if (MD_REG_P (regno0)) + { + delay = DELAY_HILO; + ret = "mt%0\t%."; + } + } + + else if (GP_REG_P (regno0)) + { + /* Don't use X format, because that will give out of + range numbers for 64 bit host and 32 bit target. */ + if (! TARGET_MIPS16) + ret = "li\t%0,%1\t\t\t# %X1"; + else + { + if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff) + ret = "li\t%0,%1"; + else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff) + ret = "li\t%0,%n1\n\tneg\t%0"; + } + } + } + + else if (code1 == CONST_DOUBLE && mode == SFmode) + { + if (op1 == CONST0_RTX (SFmode)) + { + if (GP_REG_P (regno0)) + ret = "move\t%0,%."; + + else if (FP_REG_P (regno0)) + { + delay = DELAY_LOAD; + ret = "mtc1\t%.,%0"; + } + } + + else + { + delay = DELAY_LOAD; + ret = "li.s\t%0,%1"; + } + } + + else if (code1 == LABEL_REF) + { + if (TARGET_STATS) + mips_count_memory_refs (op1, 1); + + ret = "la\t%0,%a1"; + } + + else if (code1 == SYMBOL_REF || code1 == CONST) + { + if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1)) + { + rtx offset = const0_rtx; + + if (GET_CODE (op1) == CONST) + op1 = eliminate_constant_term (XEXP (op1, 0), &offset); + + if (GET_CODE (op1) == SYMBOL_REF) + { + operands[2] = HALF_PIC_PTR (op1); + + if (TARGET_STATS) + mips_count_memory_refs (operands[2], 1); + + if (INTVAL (offset) == 0) + { + delay = DELAY_LOAD; + ret = (unsignedp && TARGET_64BIT + ? "lwu\t%0,%2" + : "lw\t%0,%2"); + } + else + { + dslots_load_total++; + operands[3] = offset; + if (unsignedp && TARGET_64BIT) + ret = (SMALL_INT (offset) + ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3" + : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]"); + else + ret = (SMALL_INT (offset) + ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3" + : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]"); + } + } + } + else if (TARGET_MIPS16 + && code1 == CONST + && GET_CODE (XEXP (op1, 0)) == REG + && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28) + { + /* This case arises on the mips16; see + mips16_gp_pseudo_reg. */ + ret = "move\t%0,%+"; + } + else if (TARGET_MIPS16 + && code1 == SYMBOL_REF + && SYMBOL_REF_FLAG (op1) + && (XSTR (op1, 0)[0] != '*' + || strncmp (XSTR (op1, 0) + 1, + LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) != 0)) + { + /* This can occur when reloading the address of a GP + relative symbol on the mips16. */ + ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)"; + } + else + { + if (TARGET_STATS) + mips_count_memory_refs (op1, 1); + + ret = "la\t%0,%a1"; + } + } + + else if (code1 == PLUS) + { + rtx add_op0 = XEXP (op1, 0); + rtx add_op1 = XEXP (op1, 1); + + if (GET_CODE (XEXP (op1, 1)) == REG + && GET_CODE (XEXP (op1, 0)) == CONST_INT) + add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0); + + operands[2] = add_op0; + operands[3] = add_op1; + ret = "add%:\t%0,%2,%3"; + } + + else if (code1 == HIGH) + { + operands[1] = XEXP (op1, 0); + ret = "lui\t%0,%%hi(%1)"; + } + } + + else if (code0 == MEM) + { + if (TARGET_STATS) + mips_count_memory_refs (op0, 1); + + if (code1 == REG) + { + int regno1 = REGNO (op1) + subreg_word1; + + if (GP_REG_P (regno1)) + { + switch (mode) + { + case SFmode: ret = "sw\t%1,%0"; break; + case SImode: ret = "sw\t%1,%0"; break; + case HImode: ret = "sh\t%1,%0"; break; + case QImode: ret = "sb\t%1,%0"; break; + default: break; + } + } + + else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode)) + ret = "s.s\t%1,%0"; + } + + else if (code1 == CONST_INT && INTVAL (op1) == 0) + { + switch (mode) + { + case SFmode: ret = "sw\t%z1,%0"; break; + case SImode: ret = "sw\t%z1,%0"; break; + case HImode: ret = "sh\t%z1,%0"; break; + case QImode: ret = "sb\t%z1,%0"; break; + default: break; + } + } + + else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode)) + { + switch (mode) + { + case SFmode: ret = "sw\t%.,%0"; break; + case SImode: ret = "sw\t%.,%0"; break; + case HImode: ret = "sh\t%.,%0"; break; + case QImode: ret = "sb\t%.,%0"; break; + default: break; + } + } + + if (ret != 0 && MEM_VOLATILE_P (op0)) + { + size_t i = strlen (ret); + + if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) + abort (); + + sprintf (volatile_buffer, "%%{%s%%}", ret); + ret = volatile_buffer; + } + } + + if (ret == 0) + { + abort_with_insn (insn, "Bad move"); + return 0; + } + + if (delay != DELAY_NONE) + return mips_fill_delay_slot (ret, delay, operands, insn); + + return ret; +} + + +/* Return the appropriate instructions to move 2 words */ + +const char * +mips_move_2words (operands, insn) + rtx operands[]; + rtx insn; +{ + const char *ret = 0; + rtx op0 = operands[0]; + rtx op1 = operands[1]; + enum rtx_code code0 = GET_CODE (operands[0]); + enum rtx_code code1 = GET_CODE (operands[1]); + int subreg_word0 = 0; + int subreg_word1 = 0; + enum delay_type delay = DELAY_NONE; + + while (code0 == SUBREG) + { + subreg_word0 += SUBREG_WORD (op0); + op0 = SUBREG_REG (op0); + code0 = GET_CODE (op0); + } + + if (code1 == SIGN_EXTEND) + { + op1 = XEXP (op1, 0); + code1 = GET_CODE (op1); + } + + while (code1 == SUBREG) + { + subreg_word1 += SUBREG_WORD (op1); + op1 = SUBREG_REG (op1); + code1 = GET_CODE (op1); + } + + /* Sanity check. */ + if (GET_CODE (operands[1]) == SIGN_EXTEND + && code1 != REG + && code1 != CONST_INT + /* The following three can happen as the result of a questionable + cast. */ + && code1 != LABEL_REF + && code1 != SYMBOL_REF + && code1 != CONST) + abort (); + + if (code0 == REG) + { + int regno0 = REGNO (op0) + subreg_word0; + + if (code1 == REG) + { + int regno1 = REGNO (op1) + subreg_word1; + + /* Just in case, don't do anything for assigning a register + to itself, unless we are filling a delay slot. */ + if (regno0 == regno1 && set_nomacro == 0) + ret = ""; + + else if (FP_REG_P (regno0)) + { + if (FP_REG_P (regno1)) + ret = "mov.d\t%0,%1"; + + else + { + delay = DELAY_LOAD; + if (TARGET_FLOAT64) + { + if (!TARGET_64BIT) + abort_with_insn (insn, "Bad move"); + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno1)) + ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0"; + else +#endif + ret = "dmtc1\t%1,%0"; + } + else + ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0"; + } + } + + else if (FP_REG_P (regno1)) + { + delay = DELAY_LOAD; + if (TARGET_FLOAT64) + { + if (!TARGET_64BIT) + abort_with_insn (insn, "Bad move"); + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno0)) + ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32"; + else +#endif + ret = "dmfc1\t%0,%1"; + } + else + ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1"; + } + + else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16) + { + delay = DELAY_HILO; + if (TARGET_64BIT) + { + if (regno0 != HILO_REGNUM) + ret = "mt%0\t%1"; + else if (regno1 == 0) + ret = "mtlo\t%.\n\tmthi\t%."; + } + else + ret = "mthi\t%M1\n\tmtlo\t%L1"; + } + + else if (GP_REG_P (regno0) && MD_REG_P (regno1)) + { + delay = DELAY_HILO; + if (TARGET_64BIT) + { + if (regno1 != HILO_REGNUM) + ret = "mf%1\t%0"; + } + else + ret = "mfhi\t%M0\n\tmflo\t%L0"; + } + + else if (TARGET_64BIT) + ret = "move\t%0,%1"; + + else if (regno0 != (regno1+1)) + ret = "move\t%0,%1\n\tmove\t%D0,%D1"; + + else + ret = "move\t%D0,%D1\n\tmove\t%0,%1"; + } + + else if (code1 == CONST_DOUBLE) + { + /* Move zero from $0 unless !TARGET_64BIT and recipient + is 64-bit fp reg, in which case generate a constant. */ + if (op1 != CONST0_RTX (GET_MODE (op1)) + || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0))) + { + if (GET_MODE (op1) == DFmode) + { + delay = DELAY_LOAD; + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno0)) + { + if (TARGET_FLOAT64 && !TARGET_64BIT) + { + split_double (op1, operands + 2, operands + 3); + ret = "li\t%0,%2\n\tli\t%D0,%3"; + } + else + ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32"; + } + else +#endif + ret = "li.d\t%0,%1"; + } + + else if (TARGET_64BIT) + { + if (! TARGET_MIPS16) + ret = "dli\t%0,%1"; + } + + else + { + split_double (op1, operands + 2, operands + 3); + ret = "li\t%0,%2\n\tli\t%D0,%3"; + } + } + + else + { + if (GP_REG_P (regno0)) + ret = (TARGET_64BIT +#ifdef TARGET_FP_CALL_32 + && ! FP_CALL_GP_REG_P (regno0) +#endif + ? "move\t%0,%." + : "move\t%0,%.\n\tmove\t%D0,%."); + + else if (FP_REG_P (regno0)) + { + delay = DELAY_LOAD; + ret = (TARGET_64BIT + ? "dmtc1\t%.,%0" + : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"); + } + } + } + + else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16) + { + if (GP_REG_P (regno0)) + ret = (TARGET_64BIT + ? "move\t%0,%." + : "move\t%0,%.\n\tmove\t%D0,%."); + + else if (FP_REG_P (regno0)) + { + delay = DELAY_LOAD; + ret = (TARGET_64BIT + ? "dmtc1\t%.,%0" + : (TARGET_FLOAT64 + ? "li.d\t%0,%1" + : "mtc1\t%.,%0\n\tmtc1\t%.,%D0")); + } + else if (MD_REG_P (regno0)) + { + delay = DELAY_HILO; + ret = (regno0 == HILO_REGNUM + ? "mtlo\t%.\n\tmthi\t%." + : "mt%0\t%.\n"); + } + } + + else if (code1 == CONST_INT && GET_MODE (op0) == DImode + && GP_REG_P (regno0)) + { + if (TARGET_64BIT) + { + if (TARGET_MIPS16) + { + if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff) + ret = "li\t%0,%1"; + else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff) + ret = "li\t%0,%n1\n\tneg\t%0"; + } + else if (GET_CODE (operands[1]) == SIGN_EXTEND) + ret = "li\t%0,%1\t\t# %X1"; + else if (HOST_BITS_PER_WIDE_INT < 64) + /* We can't use 'X' for negative numbers, because then we won't + get the right value for the upper 32 bits. */ + ret = (INTVAL (op1) < 0 + ? "dli\t%0,%1\t\t\t# %X1" + : "dli\t%0,%X1\t\t# %1"); + else + /* We must use 'X', because otherwise LONG_MIN will print as + a number that the assembler won't accept. */ + ret = "dli\t%0,%X1\t\t# %1"; + } + else if (HOST_BITS_PER_WIDE_INT < 64) + { + operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1); + if (TARGET_MIPS16) + { + if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff) + ret = "li\t%M0,%2\n\tli\t%L0,%1"; + else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff) + { + operands[2] = GEN_INT (1); + ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0"; + } + } + else + ret = "li\t%M0,%2\n\tli\t%L0,%1"; + } + else + { + /* We use multiple shifts here, to avoid warnings about out + of range shifts on 32 bit hosts. */ + operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16); + operands[1] + = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16); + ret = "li\t%M0,%2\n\tli\t%L0,%1"; + } + } + + else if (code1 == MEM) + { + delay = DELAY_LOAD; + + if (TARGET_STATS) + mips_count_memory_refs (op1, 2); + + if (FP_REG_P (regno0)) + ret = "l.d\t%0,%1"; + + else if (TARGET_64BIT) + { + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno0)) + ret = (double_memory_operand (op1, GET_MODE (op1)) + ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1" + : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32"); + else +#endif + ret = "ld\t%0,%1"; + } + + else if (double_memory_operand (op1, GET_MODE (op1))) + { + operands[2] = adj_offsettable_operand (op1, 4); + ret = (reg_mentioned_p (op0, op1) + ? "lw\t%D0,%2\n\tlw\t%0,%1" + : "lw\t%0,%1\n\tlw\t%D0,%2"); + } + + if (ret != 0 && MEM_VOLATILE_P (op1)) + { + size_t i = strlen (ret); + + if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) + abort (); + + sprintf (volatile_buffer, "%%{%s%%}", ret); + ret = volatile_buffer; + } + } + + else if (code1 == LABEL_REF) + { + if (TARGET_STATS) + mips_count_memory_refs (op1, 2); + + if (GET_CODE (operands[1]) == SIGN_EXTEND) + /* We deliberately remove the 'a' from '%1', so that we don't + have to add SIGN_EXTEND support to print_operand_address. + print_operand will just call print_operand_address in this + case, so there is no problem. */ + ret = "la\t%0,%1"; + else + ret = "dla\t%0,%a1"; + } + else if (code1 == SYMBOL_REF || code1 == CONST) + { + if (TARGET_MIPS16 + && code1 == CONST + && GET_CODE (XEXP (op1, 0)) == REG + && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28) + { + /* This case arises on the mips16; see + mips16_gp_pseudo_reg. */ + ret = "move\t%0,%+"; + } + else if (TARGET_MIPS16 + && code1 == SYMBOL_REF + && SYMBOL_REF_FLAG (op1) + && (XSTR (op1, 0)[0] != '*' + || strncmp (XSTR (op1, 0) + 1, + LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) != 0)) + { + /* This can occur when reloading the address of a GP + relative symbol on the mips16. */ + ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)"; + } + else + { + if (TARGET_STATS) + mips_count_memory_refs (op1, 2); + + if (GET_CODE (operands[1]) == SIGN_EXTEND) + /* We deliberately remove the 'a' from '%1', so that we don't + have to add SIGN_EXTEND support to print_operand_address. + print_operand will just call print_operand_address in this + case, so there is no problem. */ + ret = "la\t%0,%1"; + else + ret = "dla\t%0,%a1"; + } + } + } + + else if (code0 == MEM) + { + if (code1 == REG) + { + int regno1 = REGNO (op1) + subreg_word1; + + if (FP_REG_P (regno1)) + ret = "s.d\t%1,%0"; + + else if (TARGET_64BIT) + { + +#ifdef TARGET_FP_CALL_32 + if (FP_CALL_GP_REG_P (regno1)) + ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0"; + else +#endif + ret = "sd\t%1,%0"; + } + + else if (double_memory_operand (op0, GET_MODE (op0))) + { + operands[2] = adj_offsettable_operand (op0, 4); + ret = "sw\t%1,%0\n\tsw\t%D1,%2"; + } + } + + else if (((code1 == CONST_INT && INTVAL (op1) == 0) + || (code1 == CONST_DOUBLE + && op1 == CONST0_RTX (GET_MODE (op1)))) + && (TARGET_64BIT + || double_memory_operand (op0, GET_MODE (op0)))) + { + if (TARGET_64BIT) + ret = "sd\t%.,%0"; + else + { + operands[2] = adj_offsettable_operand (op0, 4); + ret = "sw\t%.,%0\n\tsw\t%.,%2"; + } + } + + if (TARGET_STATS) + mips_count_memory_refs (op0, 2); + + if (ret != 0 && MEM_VOLATILE_P (op0)) + { + size_t i = strlen (ret); + + if (i > sizeof (volatile_buffer) - sizeof ("%{%}")) + abort (); + + sprintf (volatile_buffer, "%%{%s%%}", ret); + ret = volatile_buffer; + } + } + + if (ret == 0) + { + abort_with_insn (insn, "Bad move"); + return 0; + } + + if (delay != DELAY_NONE) + return mips_fill_delay_slot (ret, delay, operands, insn); + + return ret; +} + +/* Provide the costs of an addressing mode that contains ADDR. + If ADDR is not a valid address, its cost is irrelevant. */ + +int +mips_address_cost (addr) + rtx addr; +{ + switch (GET_CODE (addr)) + { + case LO_SUM: + return 1; + + case LABEL_REF: + return 2; + + case CONST: + { + rtx offset = const0_rtx; + addr = eliminate_constant_term (XEXP (addr, 0), &offset); + if (GET_CODE (addr) == LABEL_REF) + return 2; + + if (GET_CODE (addr) != SYMBOL_REF) + return 4; + + if (! SMALL_INT (offset)) + return 2; + } + + /* ... fall through ... */ + + case SYMBOL_REF: + return SYMBOL_REF_FLAG (addr) ? 1 : 2; + + case PLUS: + { + register rtx plus0 = XEXP (addr, 0); + register rtx plus1 = XEXP (addr, 1); + + if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) + plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0); + + if (GET_CODE (plus0) != REG) + break; + + switch (GET_CODE (plus1)) + { + case CONST_INT: + return SMALL_INT (plus1) ? 1 : 2; + + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case HIGH: + case LO_SUM: + return mips_address_cost (plus1) + 1; + + default: + break; + } + } + + default: + break; + } + + return 4; +} + +/* Return nonzero if X is an address which needs a temporary register when + reloaded while generating PIC code. */ + +int +pic_address_needs_scratch (x) + rtx x; +{ + /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ + if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) + return 1; + + return 0; +} + +/* Make normal rtx_code into something we can index from an array */ + +static enum internal_test +map_test_to_internal_test (test_code) + enum rtx_code test_code; +{ + enum internal_test test = ITEST_MAX; + + switch (test_code) + { + case EQ: test = ITEST_EQ; break; + case NE: test = ITEST_NE; break; + case GT: test = ITEST_GT; break; + case GE: test = ITEST_GE; break; + case LT: test = ITEST_LT; break; + case LE: test = ITEST_LE; break; + case GTU: test = ITEST_GTU; break; + case GEU: test = ITEST_GEU; break; + case LTU: test = ITEST_LTU; break; + case LEU: test = ITEST_LEU; break; + default: break; + } + + return test; +} + + +/* Generate the code to compare two integer values. The return value is: + (reg:SI xx) The pseudo register the comparison is in + 0 No register, generate a simple branch. + + ??? This is called with result nonzero by the Scond patterns in + mips.md. These patterns are called with a target in the mode of + the Scond instruction pattern. Since this must be a constant, we + must use SImode. This means that if RESULT is non-zero, it will + always be an SImode register, even if TARGET_64BIT is true. We + cope with this by calling convert_move rather than emit_move_insn. + This will sometimes lead to an unnecessary extension of the result; + for example: + + long long + foo (long long i) + { + return i < 5; + } + + */ + +rtx +gen_int_relational (test_code, result, cmp0, cmp1, p_invert) + enum rtx_code test_code; /* relational test (EQ, etc) */ + rtx result; /* result to store comp. or 0 if branch */ + rtx cmp0; /* first operand to compare */ + rtx cmp1; /* second operand to compare */ + int *p_invert; /* NULL or ptr to hold whether branch needs */ + /* to reverse its test */ +{ + struct cmp_info + { + enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */ + int const_low; /* low bound of constant we can accept */ + int const_high; /* high bound of constant we can accept */ + int const_add; /* constant to add (convert LE -> LT) */ + int reverse_regs; /* reverse registers in test */ + int invert_const; /* != 0 if invert value if cmp1 is constant */ + int invert_reg; /* != 0 if invert value if cmp1 is register */ + int unsignedp; /* != 0 for unsigned comparisons. */ + }; + + static struct cmp_info info[ (int)ITEST_MAX ] = { + + { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */ + { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */ + { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */ + { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */ + { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */ + { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */ + { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */ + { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */ + { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */ + { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */ + }; + + enum internal_test test; + enum machine_mode mode; + struct cmp_info *p_info; + int branch_p; + int eqne_p; + int invert; + rtx reg; + rtx reg2; + + test = map_test_to_internal_test (test_code); + if (test == ITEST_MAX) + abort (); + + p_info = &info[(int) test]; + eqne_p = (p_info->test_code == XOR); + + mode = GET_MODE (cmp0); + if (mode == VOIDmode) + mode = GET_MODE (cmp1); + + /* Eliminate simple branches */ + branch_p = (result == 0); + if (branch_p) + { + if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG) + { + /* Comparisons against zero are simple branches */ + if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0 + && (! TARGET_MIPS16 || eqne_p)) + return 0; + + /* Test for beq/bne. */ + if (eqne_p && ! TARGET_MIPS16) + return 0; + } + + /* allocate a pseudo to calculate the value in. */ + result = gen_reg_rtx (mode); + } + + /* Make sure we can handle any constants given to us. */ + if (GET_CODE (cmp0) == CONST_INT) + cmp0 = force_reg (mode, cmp0); + + if (GET_CODE (cmp1) == CONST_INT) + { + HOST_WIDE_INT value = INTVAL (cmp1); + + if (value < p_info->const_low + || value > p_info->const_high + /* ??? Why? And why wasn't the similar code below modified too? */ + || (TARGET_64BIT + && HOST_BITS_PER_WIDE_INT < 64 + && p_info->const_add != 0 + && ((p_info->unsignedp + ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add) + > (unsigned HOST_WIDE_INT) INTVAL (cmp1)) + : (value + p_info->const_add) > INTVAL (cmp1)) + != (p_info->const_add > 0)))) + cmp1 = force_reg (mode, cmp1); + } + + /* See if we need to invert the result. */ + invert = (GET_CODE (cmp1) == CONST_INT + ? p_info->invert_const : p_info->invert_reg); + + if (p_invert != (int *)0) + { + *p_invert = invert; + invert = 0; + } + + /* Comparison to constants, may involve adding 1 to change a LT into LE. + Comparison between two registers, may involve switching operands. */ + if (GET_CODE (cmp1) == CONST_INT) + { + if (p_info->const_add != 0) + { + HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add; + + /* If modification of cmp1 caused overflow, + we would get the wrong answer if we follow the usual path; + thus, x > 0xffffffffU would turn into x > 0U. */ + if ((p_info->unsignedp + ? (unsigned HOST_WIDE_INT) new > + (unsigned HOST_WIDE_INT) INTVAL (cmp1) + : new > INTVAL (cmp1)) + != (p_info->const_add > 0)) + { + /* This test is always true, but if INVERT is true then + the result of the test needs to be inverted so 0 should + be returned instead. */ + emit_move_insn (result, invert ? const0_rtx : const_true_rtx); + return result; + } + else + cmp1 = GEN_INT (new); + } + } + + else if (p_info->reverse_regs) + { + rtx temp = cmp0; + cmp0 = cmp1; + cmp1 = temp; + } + + if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0) + reg = cmp0; + else + { + reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result; + convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0); + } + + if (test == ITEST_NE) + { + if (! TARGET_MIPS16) + { + convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0); + invert = 0; + } + else + { + reg2 = invert ? gen_reg_rtx (mode) : result; + convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0); + reg = reg2; + } + } + + else if (test == ITEST_EQ) + { + reg2 = invert ? gen_reg_rtx (mode) : result; + convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0); + reg = reg2; + } + + if (invert) + { + rtx one; + + if (! TARGET_MIPS16) + one = const1_rtx; + else + { + /* The value is in $24. Copy it to another register, so + that reload doesn't think it needs to store the $24 and + the input to the XOR in the same location. */ + reg2 = gen_reg_rtx (mode); + emit_move_insn (reg2, reg); + reg = reg2; + one = force_reg (mode, const1_rtx); + } + convert_move (result, gen_rtx (XOR, mode, reg, one), 0); + } + + return result; +} + +/* Emit the common code for doing conditional branches. + operand[0] is the label to jump to. + The comparison operands are saved away by cmp{si,di,sf,df}. */ + +void +gen_conditional_branch (operands, test_code) + rtx operands[]; + enum rtx_code test_code; +{ + enum cmp_type type = branch_type; + rtx cmp0 = branch_cmp[0]; + rtx cmp1 = branch_cmp[1]; + enum machine_mode mode; + rtx reg; + int invert; + rtx label1, label2; + + switch (type) + { + case CMP_SI: + case CMP_DI: + mode = type == CMP_SI ? SImode : DImode; + invert = 0; + reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert); + + if (reg) + { + cmp0 = reg; + cmp1 = const0_rtx; + test_code = NE; + } + else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0) + /* We don't want to build a comparison against a non-zero + constant. */ + cmp1 = force_reg (mode, cmp1); + + break; + + case CMP_SF: + case CMP_DF: + if (mips_isa < 4) + reg = gen_rtx (REG, CCmode, FPSW_REGNUM); + else + reg = gen_reg_rtx (CCmode); + + /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result == + 0 in the instruction built below. The MIPS FPU handles + inequality testing by testing for equality and looking for a + false result. */ + emit_insn (gen_rtx (SET, VOIDmode, reg, + gen_rtx (test_code == NE ? EQ : test_code, + CCmode, cmp0, cmp1))); + + test_code = test_code == NE ? EQ : NE; + mode = CCmode; + cmp0 = reg; + cmp1 = const0_rtx; + invert = 0; + break; + + default: + abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test"); + } + + /* Generate the branch. */ + + label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]); + label2 = pc_rtx; + + if (invert) + { + label2 = label1; + label1 = pc_rtx; + } + + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, + gen_rtx (IF_THEN_ELSE, VOIDmode, + gen_rtx (test_code, mode, cmp0, cmp1), + label1, label2))); +} + +/* Emit the common code for conditional moves. OPERANDS is the array + of operands passed to the conditional move defined_expand. */ + +void +gen_conditional_move (operands) + rtx *operands; +{ + rtx op0 = branch_cmp[0]; + rtx op1 = branch_cmp[1]; + enum machine_mode mode = GET_MODE (branch_cmp[0]); + enum rtx_code cmp_code = GET_CODE (operands[1]); + enum rtx_code move_code = NE; + enum machine_mode op_mode = GET_MODE (operands[0]); + enum machine_mode cmp_mode; + rtx cmp_reg; + + if (GET_MODE_CLASS (mode) != MODE_FLOAT) + { + switch (cmp_code) + { + case EQ: + cmp_code = XOR; + move_code = EQ; + break; + case NE: + cmp_code = XOR; + break; + case LT: + break; + case GE: + cmp_code = LT; + move_code = EQ; + break; + case GT: + cmp_code = LT; + op0 = force_reg (mode, branch_cmp[1]); + op1 = branch_cmp[0]; + break; + case LE: + cmp_code = LT; + op0 = force_reg (mode, branch_cmp[1]); + op1 = branch_cmp[0]; + move_code = EQ; + break; + case LTU: + break; + case GEU: + cmp_code = LTU; + move_code = EQ; + break; + case GTU: + cmp_code = LTU; + op0 = force_reg (mode, branch_cmp[1]); + op1 = branch_cmp[0]; + break; + case LEU: + cmp_code = LTU; + op0 = force_reg (mode, branch_cmp[1]); + op1 = branch_cmp[0]; + move_code = EQ; + break; + default: + abort (); + } + } + else if (cmp_code == NE) + cmp_code = EQ, move_code = EQ; + + if (mode == SImode || mode == DImode) + cmp_mode = mode; + else if (mode == SFmode || mode == DFmode) + cmp_mode = CCmode; + else + abort (); + + cmp_reg = gen_reg_rtx (cmp_mode); + emit_insn (gen_rtx (SET, cmp_mode, cmp_reg, + gen_rtx (cmp_code, cmp_mode, op0, op1))); + + emit_insn (gen_rtx (SET, op_mode, operands[0], + gen_rtx (IF_THEN_ELSE, op_mode, + gen_rtx (move_code, VOIDmode, + cmp_reg, CONST0_RTX (SImode)), + operands[2], operands[3]))); +} + +/* Write a loop to move a constant number of bytes. + Generate load/stores as follows: + + do { + temp1 = src[0]; + temp2 = src[1]; + ... + temp<last> = src[MAX_MOVE_REGS-1]; + dest[0] = temp1; + dest[1] = temp2; + ... + dest[MAX_MOVE_REGS-1] = temp<last>; + src += MAX_MOVE_REGS; + dest += MAX_MOVE_REGS; + } while (src != final); + + This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp + registers are needed. + + Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3 + cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every + (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */ + +#define MAX_MOVE_REGS 4 +#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD) + +static void +block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src) + rtx dest_reg; /* register holding destination address */ + rtx src_reg; /* register holding source address */ + int bytes; /* # bytes to move */ + int align; /* alignment */ + rtx orig_dest; /* original dest for change_address */ + rtx orig_src; /* original source for making a reg note */ +{ + rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg); + rtx src_mem = change_address (orig_src, BLKmode, src_reg); + rtx align_rtx = GEN_INT (align); + rtx label; + rtx final_src; + rtx bytes_rtx; + int leftover; + + if (bytes < 2 * MAX_MOVE_BYTES) + abort (); + + leftover = bytes % MAX_MOVE_BYTES; + bytes -= leftover; + + label = gen_label_rtx (); + final_src = gen_reg_rtx (Pmode); + bytes_rtx = GEN_INT (bytes); + + if (bytes > 0x7fff) + { + if (Pmode == DImode) + { + emit_insn (gen_movdi (final_src, bytes_rtx)); + emit_insn (gen_adddi3 (final_src, final_src, src_reg)); + } + else + { + emit_insn (gen_movsi (final_src, bytes_rtx)); + emit_insn (gen_addsi3 (final_src, final_src, src_reg)); + } + } + else + { + if (Pmode == DImode) + emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx)); + else + emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx)); + } + + emit_label (label); + + bytes_rtx = GEN_INT (MAX_MOVE_BYTES); + emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx)); + + if (Pmode == DImode) + { + emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx)); + emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx)); + emit_insn (gen_cmpdi (src_reg, final_src)); + } + else + { + emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx)); + emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx)); + emit_insn (gen_cmpsi (src_reg, final_src)); + } + + emit_jump_insn (gen_bne (label)); + + if (leftover) + emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover), + align_rtx)); +} + +/* Use a library function to move some bytes. */ + +static void +block_move_call (dest_reg, src_reg, bytes_rtx) + rtx dest_reg; + rtx src_reg; + rtx bytes_rtx; +{ + /* We want to pass the size as Pmode, which will normally be SImode + but will be DImode if we are using 64 bit longs and pointers. */ + if (GET_MODE (bytes_rtx) != VOIDmode + && GET_MODE (bytes_rtx) != Pmode) + bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1); + +#ifdef TARGET_MEM_FUNCTIONS + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0, + VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode, + convert_to_mode (TYPE_MODE (sizetype), bytes_rtx, + TREE_UNSIGNED (sizetype)), + TYPE_MODE (sizetype)); +#else + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0, + VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode, + convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx, + TREE_UNSIGNED (integer_type_node)), + TYPE_MODE (integer_type_node)); +#endif +} + +/* Expand string/block move operations. + + operands[0] is the pointer to the destination. + operands[1] is the pointer to the source. + operands[2] is the number of bytes to move. + operands[3] is the alignment. */ + +void +expand_block_move (operands) + rtx operands[]; +{ + rtx bytes_rtx = operands[2]; + rtx align_rtx = operands[3]; + int constp = GET_CODE (bytes_rtx) == CONST_INT; + HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0; + int align = INTVAL (align_rtx); + rtx orig_src = operands[1]; + rtx orig_dest = operands[0]; + rtx src_reg; + rtx dest_reg; + + if (constp && bytes <= 0) + return; + + if (align > UNITS_PER_WORD) + align = UNITS_PER_WORD; + + /* Move the address into scratch registers. */ + dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); + src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); + + if (TARGET_MEMCPY) + block_move_call (dest_reg, src_reg, bytes_rtx); + + else if (constp && bytes <= 2 * MAX_MOVE_BYTES + && align == UNITS_PER_WORD) + move_by_pieces (orig_dest, orig_src, bytes, align); + + else if (constp && bytes <= 2 * MAX_MOVE_BYTES) + emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode, + dest_reg), + change_address (orig_src, BLKmode, + src_reg), + bytes_rtx, align_rtx)); + + else if (constp && align >= UNITS_PER_WORD && optimize) + block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src); + + else if (constp && optimize) + { + /* If the alignment is not word aligned, generate a test at + runtime, to see whether things wound up aligned, and we + can use the faster lw/sw instead ulw/usw. */ + + rtx temp = gen_reg_rtx (Pmode); + rtx aligned_label = gen_label_rtx (); + rtx join_label = gen_label_rtx (); + int leftover = bytes % MAX_MOVE_BYTES; + + bytes -= leftover; + + if (Pmode == DImode) + { + emit_insn (gen_iordi3 (temp, src_reg, dest_reg)); + emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1))); + emit_insn (gen_cmpdi (temp, const0_rtx)); + } + else + { + emit_insn (gen_iorsi3 (temp, src_reg, dest_reg)); + emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1))); + emit_insn (gen_cmpsi (temp, const0_rtx)); + } + + emit_jump_insn (gen_beq (aligned_label)); + + /* Unaligned loop. */ + block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src); + emit_jump_insn (gen_jump (join_label)); + emit_barrier (); + + /* Aligned loop. */ + emit_label (aligned_label); + block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest, + orig_src); + emit_label (join_label); + + /* Bytes at the end of the loop. */ + if (leftover) + emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode, + dest_reg), + change_address (orig_src, BLKmode, + src_reg), + GEN_INT (leftover), + GEN_INT (align))); + } + + else + block_move_call (dest_reg, src_reg, bytes_rtx); +} + +/* Emit load/stores for a small constant block_move. + + operands[0] is the memory address of the destination. + operands[1] is the memory address of the source. + operands[2] is the number of bytes to move. + operands[3] is the alignment. + operands[4] is a temp register. + operands[5] is a temp register. + ... + operands[3+num_regs] is the last temp register. + + The block move type can be one of the following: + BLOCK_MOVE_NORMAL Do all of the block move. + BLOCK_MOVE_NOT_LAST Do all but the last store. + BLOCK_MOVE_LAST Do just the last store. */ + +const char * +output_block_move (insn, operands, num_regs, move_type) + rtx insn; + rtx operands[]; + int num_regs; + enum block_move_type move_type; +{ + rtx dest_reg = XEXP (operands[0], 0); + rtx src_reg = XEXP (operands[1], 0); + HOST_WIDE_INT bytes = INTVAL (operands[2]); + int align = INTVAL (operands[3]); + int num = 0; + int offset = 0; + int use_lwl_lwr = 0; + int last_operand = num_regs + 4; + int safe_regs = 4; + int i; + rtx xoperands[10]; + + struct { + const char *load; /* load insn without nop */ + const char *load_nop; /* load insn with trailing nop */ + const char *store; /* store insn */ + const char *final; /* if last_store used: NULL or swr */ + const char *last_store; /* last store instruction */ + int offset; /* current offset */ + enum machine_mode mode; /* mode to use on (MEM) */ + } load_store[4]; + + /* ??? Detect a bug in GCC, where it can give us a register + the same as one of the addressing registers and reduce + the number of registers available. */ + for (i = 4; + i < last_operand + && safe_regs < (int)(sizeof(xoperands) / sizeof(xoperands[0])); + i++) + if (! reg_mentioned_p (operands[i], operands[0]) + && ! reg_mentioned_p (operands[i], operands[1])) + xoperands[safe_regs++] = operands[i]; + + if (safe_regs < last_operand) + { + xoperands[0] = operands[0]; + xoperands[1] = operands[1]; + xoperands[2] = operands[2]; + xoperands[3] = operands[3]; + return output_block_move (insn, xoperands, safe_regs - 4, move_type); + } + + /* If we are given global or static addresses, and we would be + emitting a few instructions, try to save time by using a + temporary register for the pointer. */ + /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in + an ldl/ldr instruction pair. We play it safe, and always move + constant addresses into registers when generating N32/N64 code, just + in case we might emit an unaligned load instruction. */ + if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL + || mips_abi == ABI_N32 || mips_abi == ABI_64)) + { + if (CONSTANT_P (src_reg)) + { + if (TARGET_STATS) + mips_count_memory_refs (operands[1], 1); + + src_reg = operands[3 + num_regs--]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[1] = operands[1]; + xoperands[0] = src_reg; + if (Pmode == DImode) + output_asm_insn ("dla\t%0,%1", xoperands); + else + output_asm_insn ("la\t%0,%1", xoperands); + } + } + + if (CONSTANT_P (dest_reg)) + { + if (TARGET_STATS) + mips_count_memory_refs (operands[0], 1); + + dest_reg = operands[3 + num_regs--]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[1] = operands[0]; + xoperands[0] = dest_reg; + if (Pmode == DImode) + output_asm_insn ("dla\t%0,%1", xoperands); + else + output_asm_insn ("la\t%0,%1", xoperands); + } + } + } + + /* ??? We really shouldn't get any LO_SUM addresses here, because they + are not offsettable, however, offsettable_address_p says they are + offsettable. I think this is a bug in offsettable_address_p. + For expediency, we fix this by just loading the address into a register + if we happen to get one. */ + + if (GET_CODE (src_reg) == LO_SUM) + { + src_reg = operands[3 + num_regs--]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[2] = XEXP (XEXP (operands[1], 0), 1); + xoperands[1] = XEXP (XEXP (operands[1], 0), 0); + xoperands[0] = src_reg; + if (Pmode == DImode) + output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands); + else + output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands); + } + } + + if (GET_CODE (dest_reg) == LO_SUM) + { + dest_reg = operands[3 + num_regs--]; + if (move_type != BLOCK_MOVE_LAST) + { + xoperands[2] = XEXP (XEXP (operands[0], 0), 1); + xoperands[1] = XEXP (XEXP (operands[0], 0), 0); + xoperands[0] = dest_reg; + if (Pmode == DImode) + output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands); + else + output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands); + } + } + + if (num_regs > (int)(sizeof (load_store) / sizeof (load_store[0]))) + num_regs = sizeof (load_store) / sizeof (load_store[0]); + + else if (num_regs < 1) + abort_with_insn (insn, + "Cannot do block move, not enough scratch registers"); + + while (bytes > 0) + { + load_store[num].offset = offset; + + if (TARGET_64BIT && bytes >= 8 && align >= 8) + { + load_store[num].load = "ld\t%0,%1"; + load_store[num].load_nop = "ld\t%0,%1%#"; + load_store[num].store = "sd\t%0,%1"; + load_store[num].last_store = "sd\t%0,%1"; + load_store[num].final = 0; + load_store[num].mode = DImode; + offset += 8; + bytes -= 8; + } + + /* ??? Fails because of a MIPS assembler bug? */ + else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16) + { + if (BYTES_BIG_ENDIAN) + { + load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2"; + load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#"; + load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2"; + load_store[num].last_store = "sdr\t%0,%2"; + load_store[num].final = "sdl\t%0,%1"; + } + else + { + load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1"; + load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#"; + load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1"; + load_store[num].last_store = "sdr\t%0,%1"; + load_store[num].final = "sdl\t%0,%2"; + } + + load_store[num].mode = DImode; + offset += 8; + bytes -= 8; + use_lwl_lwr = 1; + } + + else if (bytes >= 4 && align >= 4) + { + load_store[num].load = "lw\t%0,%1"; + load_store[num].load_nop = "lw\t%0,%1%#"; + load_store[num].store = "sw\t%0,%1"; + load_store[num].last_store = "sw\t%0,%1"; + load_store[num].final = 0; + load_store[num].mode = SImode; + offset += 4; + bytes -= 4; + } + + else if (bytes >= 4 && ! TARGET_MIPS16) + { + if (BYTES_BIG_ENDIAN) + { + load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2"; + load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#"; + load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2"; + load_store[num].last_store = "swr\t%0,%2"; + load_store[num].final = "swl\t%0,%1"; + } + else + { + load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1"; + load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#"; + load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1"; + load_store[num].last_store = "swr\t%0,%1"; + load_store[num].final = "swl\t%0,%2"; + } + + load_store[num].mode = SImode; + offset += 4; + bytes -= 4; + use_lwl_lwr = 1; + } + + else if (bytes >= 2 && align >= 2) + { + load_store[num].load = "lh\t%0,%1"; + load_store[num].load_nop = "lh\t%0,%1%#"; + load_store[num].store = "sh\t%0,%1"; + load_store[num].last_store = "sh\t%0,%1"; + load_store[num].final = 0; + load_store[num].mode = HImode; + offset += 2; + bytes -= 2; + } + else + { + load_store[num].load = "lb\t%0,%1"; + load_store[num].load_nop = "lb\t%0,%1%#"; + load_store[num].store = "sb\t%0,%1"; + load_store[num].last_store = "sb\t%0,%1"; + load_store[num].final = 0; + load_store[num].mode = QImode; + offset++; + bytes--; + } + + if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) + { + dslots_load_total++; + dslots_load_filled++; + + if (CONSTANT_P (src_reg)) + mips_count_memory_refs (src_reg, 1); + + if (CONSTANT_P (dest_reg)) + mips_count_memory_refs (dest_reg, 1); + } + + /* Emit load/stores now if we have run out of registers or are + at the end of the move. */ + + if (++num == num_regs || bytes == 0) + { + /* If only load/store, we need a NOP after the load. */ + if (num == 1) + { + load_store[0].load = load_store[0].load_nop; + if (TARGET_STATS && move_type != BLOCK_MOVE_LAST) + dslots_load_filled--; + } + + if (move_type != BLOCK_MOVE_LAST) + { + for (i = 0; i < num; i++) + { + int offset; + + if (!operands[i + 4]) + abort (); + + if (GET_MODE (operands[i + 4]) != load_store[i].mode) + operands[i + 4] = gen_rtx (REG, load_store[i].mode, + REGNO (operands[i + 4])); + + offset = load_store[i].offset; + xoperands[0] = operands[i + 4]; + xoperands[1] = gen_rtx (MEM, load_store[i].mode, + plus_constant (src_reg, offset)); + + if (use_lwl_lwr) + { + int extra_offset + = GET_MODE_SIZE (load_store[i].mode) - 1; + + xoperands[2] = gen_rtx (MEM, load_store[i].mode, + plus_constant (src_reg, + extra_offset + + offset)); + } + + output_asm_insn (load_store[i].load, xoperands); + } + } + + for (i = 0; i < num; i++) + { + int last_p = (i == num-1 && bytes == 0); + int offset = load_store[i].offset; + + xoperands[0] = operands[i + 4]; + xoperands[1] = gen_rtx (MEM, load_store[i].mode, + plus_constant (dest_reg, offset)); + + + if (use_lwl_lwr) + { + int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1; + xoperands[2] = gen_rtx (MEM, load_store[i].mode, + plus_constant (dest_reg, + extra_offset + + offset)); + } + + if (move_type == BLOCK_MOVE_NORMAL) + output_asm_insn (load_store[i].store, xoperands); + + else if (move_type == BLOCK_MOVE_NOT_LAST) + { + if (!last_p) + output_asm_insn (load_store[i].store, xoperands); + + else if (load_store[i].final != 0) + output_asm_insn (load_store[i].final, xoperands); + } + + else if (last_p) + output_asm_insn (load_store[i].last_store, xoperands); + } + + num = 0; /* reset load_store */ + use_lwl_lwr = 0; + } + } + + return ""; +} + +/* Argument support functions. */ + +/* Initialize CUMULATIVE_ARGS for a function. */ + +void +init_cumulative_args (cum, fntype, libname) + CUMULATIVE_ARGS *cum; /* argument info to initialize */ + tree fntype; /* tree ptr for function decl */ + rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */ +{ + static CUMULATIVE_ARGS zero_cum; + tree param, next_param; + + if (TARGET_DEBUG_E_MODE) + { + fprintf (stderr, + "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype); + + if (!fntype) + fputc ('\n', stderr); + + else + { + tree ret_type = TREE_TYPE (fntype); + fprintf (stderr, ", fntype code = %s, ret code = %s\n", + tree_code_name[(int)TREE_CODE (fntype)], + tree_code_name[(int)TREE_CODE (ret_type)]); + } + } + + *cum = zero_cum; + + /* Determine if this function has variable arguments. This is + indicated by the last argument being 'void_type_mode' if there + are no variable arguments. The standard MIPS calling sequence + passes all arguments in the general purpose registers in this case. */ + + for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0; + param != 0; param = next_param) + { + next_param = TREE_CHAIN (param); + if (next_param == 0 && TREE_VALUE (param) != void_type_node) + cum->gp_reg_found = 1; + } +} + +/* Advance the argument to the next argument position. */ + +void +function_arg_advance (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named; /* whether or not the argument was named */ +{ + if (TARGET_DEBUG_E_MODE) + { + fprintf (stderr, + "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ", + cum->gp_reg_found, cum->arg_number, cum->arg_words, + GET_MODE_NAME (mode)); + fprintf (stderr, HOST_PTR_PRINTF, type); + fprintf (stderr, ", %d )\n\n", named); + } + + cum->arg_number++; + switch (mode) + { + case VOIDmode: + break; + + default: + if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT + && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) + abort (); + + cum->gp_reg_found = 1; + cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + break; + + case BLKmode: + cum->gp_reg_found = 1; + cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + break; + + case SFmode: + if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT) + cum->fp_arg_words++; + else + cum->arg_words++; + if (! cum->gp_reg_found && cum->arg_number <= 2) + cum->fp_code += 1 << ((cum->arg_number - 1) * 2); + break; + + case DFmode: + if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT) + cum->fp_arg_words += (TARGET_64BIT ? 1 : 2); + else + cum->arg_words += (TARGET_64BIT ? 1 : 2); + if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2) + cum->fp_code += 2 << ((cum->arg_number - 1) * 2); + break; + + case DImode: + cum->gp_reg_found = 1; + cum->arg_words += (TARGET_64BIT ? 1 : 2); + break; + + case QImode: + case HImode: + case SImode: + cum->gp_reg_found = 1; + cum->arg_words++; + break; + } +} + +/* Return an RTL expression containing the register for the given mode, + or 0 if the argument is to be passed on the stack. */ + +struct rtx_def * +function_arg (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named; /* != 0 for normal args, == 0 for ... args */ +{ + rtx ret; + int regbase = -1; + int bias = 0; + int *arg_words = &cum->arg_words; + int struct_p = (type != 0 + && (TREE_CODE (type) == RECORD_TYPE + || TREE_CODE (type) == UNION_TYPE + || TREE_CODE (type) == QUAL_UNION_TYPE)); + + if (TARGET_DEBUG_E_MODE) + { + fprintf (stderr, + "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ", + cum->gp_reg_found, cum->arg_number, cum->arg_words, + GET_MODE_NAME (mode)); + fprintf (stderr, HOST_PTR_PRINTF, type); + fprintf (stderr, ", %d ) = ", named); + } + + + cum->last_arg_fp = 0; + switch (mode) + { + case SFmode: + if (mips_abi == ABI_32 || mips_abi == ABI_O64) + { + if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT) + regbase = GP_ARG_FIRST; + else + { + regbase = FP_ARG_FIRST; + + /* If the first arg was a float in a floating point register, + then set bias to align this float arg properly. */ + if (cum->arg_words == 1) + bias = 1; + } + } + else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT) + { + if (! TARGET_64BIT) + cum->fp_arg_words += cum->fp_arg_words & 1; + cum->last_arg_fp = 1; + arg_words = &cum->fp_arg_words; + regbase = FP_ARG_FIRST; + } + else + regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST); + break; + + case DFmode: + if (! TARGET_64BIT) + { + if (mips_abi == ABI_EABI + && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT) + cum->fp_arg_words += cum->fp_arg_words & 1; + else + cum->arg_words += cum->arg_words & 1; + } + + if (mips_abi == ABI_32 || mips_abi == ABI_O64) + regbase = ((cum->gp_reg_found + || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT + || cum->arg_number >= 2) + ? GP_ARG_FIRST : FP_ARG_FIRST); + else if (mips_abi == ABI_EABI + && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT) + { + cum->last_arg_fp = 1; + arg_words = &cum->fp_arg_words; + regbase = FP_ARG_FIRST; + } + else + regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named + ? GP_ARG_FIRST : FP_ARG_FIRST); + break; + + default: + if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT + && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) + abort (); + + /* Drops through. */ + case BLKmode: + if (type != (tree)0 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD + && ! TARGET_64BIT && mips_abi != ABI_EABI) + cum->arg_words += (cum->arg_words & 1); + regbase = GP_ARG_FIRST; + break; + + case VOIDmode: + case QImode: + case HImode: + case SImode: + regbase = GP_ARG_FIRST; + break; + + case DImode: + if (! TARGET_64BIT) + cum->arg_words += (cum->arg_words & 1); + regbase = GP_ARG_FIRST; + } + + if (*arg_words >= MAX_ARGS_IN_REGISTERS) + { + if (TARGET_DEBUG_E_MODE) + fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : ""); + + ret = 0; + } + else + { + if (regbase == -1) + abort (); + + if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32 + || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named) + ret = gen_rtx (REG, mode, regbase + *arg_words + bias); + else + { + /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the + structure contains a double in its entirety, then that 64 bit + chunk is passed in a floating point register. */ + tree field; + + /* First check to see if there is any such field. */ + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + if (TREE_CODE (field) == FIELD_DECL + && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE + && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD + && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) + % BITS_PER_WORD == 0)) + break; + + /* If the whole struct fits a DFmode register, + we don't need the PARALLEL. */ + if (! field || mode == DFmode) + ret = gen_rtx (REG, mode, regbase + *arg_words + bias); + else + { + /* Now handle the special case by returning a PARALLEL + indicating where each 64 bit chunk goes. */ + int chunks; + int bitpos; + int regno; + int i; + + /* ??? If this is a packed structure, then the last hunk won't + be 64 bits. */ + + chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD; + if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS) + chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias; + + /* assign_parms checks the mode of ENTRY_PARM, so we must + use the actual mode here. */ + ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks)); + + bitpos = 0; + regno = regbase + *arg_words + bias; + field = TYPE_FIELDS (type); + for (i = 0; i < chunks; i++) + { + rtx reg; + + for (; field; field = TREE_CHAIN (field)) + if (TREE_CODE (field) == FIELD_DECL + && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) + >= bitpos)) + break; + + if (field + && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos + && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE + && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) + reg = gen_rtx (REG, DFmode, + regno + FP_ARG_FIRST - GP_ARG_FIRST); + else + reg = gen_rtx (REG, word_mode, regno); + + XVECEXP (ret, 0, i) + = gen_rtx (EXPR_LIST, VOIDmode, reg, + GEN_INT (bitpos / BITS_PER_UNIT)); + + bitpos += 64; + regno++; + } + } + } + + if (TARGET_DEBUG_E_MODE) + fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias], + struct_p ? ", [struct]" : ""); + + /* The following is a hack in order to pass 1 byte structures + the same way that the MIPS compiler does (namely by passing + the structure in the high byte or half word of the register). + This also makes varargs work. If we have such a structure, + we save the adjustment RTL, and the call define expands will + emit them. For the VOIDmode argument (argument after the + last real argument), pass back a parallel vector holding each + of the adjustments. */ + + /* ??? function_arg can be called more than once for each argument. + As a result, we compute more adjustments than we need here. + See the CUMULATIVE_ARGS definition in mips.h. */ + + /* ??? This scheme requires everything smaller than the word size to + shifted to the left, but when TARGET_64BIT and ! TARGET_INT64, + that would mean every int needs to be shifted left, which is very + inefficient. Let's not carry this compatibility to the 64 bit + calling convention for now. */ + + if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD + && ! TARGET_64BIT && mips_abi != ABI_EABI) + { + rtx amount = GEN_INT (BITS_PER_WORD + - int_size_in_bytes (type) * BITS_PER_UNIT); + rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias); + + if (TARGET_64BIT) + cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount); + else + cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount); + } + } + + /* We will be called with a mode of VOIDmode after the last argument + has been seen. Whatever we return will be passed to the call + insn. If we need any shifts for small structures, return them in + a PARALLEL; in that case, stuff the mips16 fp_code in as the + mode. Otherwise, if we have need a mips16 fp_code, return a REG + with the code stored as the mode. */ + if (mode == VOIDmode) + { + if (cum->num_adjusts > 0) + ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code, + gen_rtvec_v (cum->num_adjusts, cum->adjust)); + else if (TARGET_MIPS16 && cum->fp_code != 0) + ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0); + } + + return ret; +} + +int +function_arg_partial_nregs (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */ +{ + if ((mode == BLKmode + || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT + || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) + && cum->arg_words < MAX_ARGS_IN_REGISTERS + && mips_abi != ABI_EABI) + { + int words; + if (mode == BLKmode) + words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) + / UNITS_PER_WORD); + else + words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + + if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS) + return 0; /* structure fits in registers */ + + if (TARGET_DEBUG_E_MODE) + fprintf (stderr, "function_arg_partial_nregs = %d\n", + MAX_ARGS_IN_REGISTERS - cum->arg_words); + + return MAX_ARGS_IN_REGISTERS - cum->arg_words; + } + + else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1 + && ! TARGET_64BIT && mips_abi != ABI_EABI) + { + if (TARGET_DEBUG_E_MODE) + fprintf (stderr, "function_arg_partial_nregs = 1\n"); + + return 1; + } + + return 0; +} + +/* Abort after printing out a specific insn. */ + +static void +abort_with_insn (insn, reason) + rtx insn; + const char *reason; +{ + error (reason); + debug_rtx (insn); + abort (); +} + +/* Write a message to stderr (for use in macros expanded in files that do not + include stdio.h). */ + +void +trace (s, s1, s2) + char *s, *s1, *s2; +{ + fprintf (stderr, s, s1, s2); +} + +/* Set up the threshold for data to go into the small data area, instead + of the normal data area, and detect any conflicts in the switches. */ + +void +override_options () +{ + register int i, start; + register int regno; + register enum machine_mode mode; + + mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE; + + if (mips_section_threshold <= 0) + target_flags &= ~MASK_GPOPT; + else if (optimize) + target_flags |= MASK_GPOPT; + +#ifndef MIPS_ISA_DEFAULT +#define MIPS_ISA_DEFAULT 1 +#endif + + /* If both single-float and soft-float are set, then clear the one that + was set by TARGET_DEFAULT, leaving the one that was set by the + user. We assume here that the specs prevent both being set by the + user. */ +#ifdef TARGET_DEFAULT + if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT) + target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT)); +#endif + + /* Get the architectural level. */ + if (mips_isa_string == 0) + mips_isa = MIPS_ISA_DEFAULT; + + else if (ISDIGIT (*mips_isa_string)) + { + mips_isa = atoi (mips_isa_string); + if (mips_isa == 16) + { + /* -mno-mips16 overrides -mips16. */ + if (mips_no_mips16_string == NULL) + { + target_flags |= MASK_MIPS16; + if (TARGET_64BIT) + mips_isa = 3; + else + mips_isa = MIPS_ISA_DEFAULT; + } + else + { + mips_isa = MIPS_ISA_DEFAULT; + } + } + else if (mips_isa < 1 || mips_isa > 4) + { + error ("-mips%d not supported", mips_isa); + mips_isa = 1; + } + } + + else + { + error ("bad value (%s) for -mips switch", mips_isa_string); + mips_isa = 1; + } + +#ifdef MIPS_ABI_DEFAULT + /* Get the ABI to use. */ + if (mips_abi_string == (char *) 0) + mips_abi = MIPS_ABI_DEFAULT; + else if (! strcmp (mips_abi_string, "32")) + mips_abi = ABI_32; + else if (! strcmp (mips_abi_string, "o64")) + mips_abi = ABI_O64; + else if (! strcmp (mips_abi_string, "n32")) + mips_abi = ABI_N32; + else if (! strcmp (mips_abi_string, "64")) + mips_abi = ABI_64; + else if (! strcmp (mips_abi_string, "eabi")) + mips_abi = ABI_EABI; + else + error ("bad value (%s) for -mabi= switch", mips_abi_string); + + /* A specified ISA defaults the ABI if it was not specified. */ + if (mips_abi_string == 0 && mips_isa_string + && mips_abi != ABI_EABI && mips_abi != ABI_O64) + { + if (mips_isa <= 2) + mips_abi = ABI_32; + else + mips_abi = ABI_64; + } + + /* A specified ABI defaults the ISA if it was not specified. */ + else if (mips_isa_string == 0 && mips_abi_string + && mips_abi != ABI_EABI && mips_abi != ABI_O64) + { + if (mips_abi == ABI_32) + mips_isa = 1; + else if (mips_abi == ABI_N32) + mips_isa = 3; + else + mips_isa = 4; + } + + /* If both ABI and ISA were specified, check for conflicts. */ + else if (mips_isa_string && mips_abi_string) + { + if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64 + || mips_abi == ABI_O64)) + || (mips_isa >= 3 && mips_abi == ABI_32)) + error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa); + } + + /* Override TARGET_DEFAULT if necessary. */ + if (mips_abi == ABI_32) + target_flags &= ~ (MASK_FLOAT64|MASK_64BIT); + + /* If no type size setting options (-mlong64,-mint64,-mlong32) were used + then set the type sizes. In the EABI in 64 bit mode, longs and + pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */ + if (mips_explicit_type_size_string == NULL + && ((mips_abi == ABI_EABI && TARGET_64BIT) + || mips_abi == ABI_64)) + target_flags |= MASK_LONG64; + + /* ??? This doesn't work yet, so don't let people try to use it. */ + if (mips_abi == ABI_32) + error ("The -mabi=32 support does not work yet."); + +#else + if (mips_abi_string) + error ("This target does not support the -mabi switch."); +#endif + +#ifdef MIPS_CPU_STRING_DEFAULT + /* ??? There is a minor inconsistency here. If the user specifies an ISA + greater than that supported by the default processor, then the user gets + an error. Normally, the compiler will just default to the base level cpu + for the indicated isa. */ + if (mips_cpu_string == 0) + mips_cpu_string = MIPS_CPU_STRING_DEFAULT; +#endif + + /* Identify the processor type */ + if (mips_cpu_string == 0 + || !strcmp (mips_cpu_string, "default") + || !strcmp (mips_cpu_string, "DEFAULT")) + { + switch (mips_isa) + { + default: + mips_cpu_string = "3000"; + mips_cpu = PROCESSOR_R3000; + break; + case 2: + mips_cpu_string = "6000"; + mips_cpu = PROCESSOR_R6000; + break; + case 3: + mips_cpu_string = "4000"; + mips_cpu = PROCESSOR_R4000; + break; + case 4: + mips_cpu_string = "8000"; + mips_cpu = PROCESSOR_R8000; + break; + } + } + + else + { + const char *p = mips_cpu_string; + int seen_v = 0; + + /* We need to cope with the various "vr" prefixes for the NEC 4300 + and 4100 processors. */ + if (*p == 'v' || *p == 'V') + seen_v = 1, p++; + + if (*p == 'r' || *p == 'R') + p++; + + /* Since there is no difference between a R2000 and R3000 in + terms of the scheduler, we collapse them into just an R3000. */ + + mips_cpu = PROCESSOR_DEFAULT; + switch (*p) + { + case '2': + if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K")) + mips_cpu = PROCESSOR_R3000; + break; + + case '3': + if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K")) + mips_cpu = PROCESSOR_R3000; + else if (!strcmp (p, "3900")) + mips_cpu = PROCESSOR_R3900; + break; + + case '4': + if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K")) + mips_cpu = PROCESSOR_R4000; + /* The vr4100 is a non-FP ISA III processor with some extra + instructions. */ + else if (!strcmp (p, "4100")) + { + mips_cpu = PROCESSOR_R4100; + target_flags |= MASK_SOFT_FLOAT ; + } + /* The vr4300 is a standard ISA III processor, but with a different + pipeline. */ + else if (!strcmp (p, "4300")) + mips_cpu = PROCESSOR_R4300; + /* The r4400 is exactly the same as the r4000 from the compiler's + viewpoint. */ + else if (!strcmp (p, "4400")) + mips_cpu = PROCESSOR_R4000; + else if (!strcmp (p, "4600")) + mips_cpu = PROCESSOR_R4600; + else if (!strcmp (p, "4650")) + mips_cpu = PROCESSOR_R4650; + break; + + case '5': + if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K")) + mips_cpu = PROCESSOR_R5000; + break; + + case '6': + if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K")) + mips_cpu = PROCESSOR_R6000; + break; + + case '8': + if (!strcmp (p, "8000")) + mips_cpu = PROCESSOR_R8000; + break; + + case 'o': + if (!strcmp (p, "orion")) + mips_cpu = PROCESSOR_R4600; + break; + } + + if (seen_v + && mips_cpu != PROCESSOR_R4300 + && mips_cpu != PROCESSOR_R4100 + && mips_cpu != PROCESSOR_R5000) + mips_cpu = PROCESSOR_DEFAULT; + + if (mips_cpu == PROCESSOR_DEFAULT) + { + error ("bad value (%s) for -mcpu= switch", mips_cpu_string); + mips_cpu_string = "default"; + } + } + + if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1) + || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2) + || ((mips_cpu == PROCESSOR_R4000 + || mips_cpu == PROCESSOR_R4100 + || mips_cpu == PROCESSOR_R4300 + || mips_cpu == PROCESSOR_R4600 + || mips_cpu == PROCESSOR_R4650) + && mips_isa > 3)) + error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa); + + /* make sure sizes of ints/longs/etc. are ok */ + if (mips_isa < 3) + { + if (TARGET_FLOAT64) + fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers"); + + else if (TARGET_64BIT) + fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers"); + } + + if (mips_abi != ABI_32 && mips_abi != ABI_O64) + flag_pcc_struct_return = 0; + + /* Tell halfpic.c that we have half-pic code if we do. */ + if (TARGET_HALF_PIC) + HALF_PIC_INIT (); + + /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need + to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */ + /* ??? -non_shared turns off pic code generation, but this is not + implemented. */ + if (TARGET_ABICALLS) + { + mips_abicalls = MIPS_ABICALLS_YES; + flag_pic = 1; + if (mips_section_threshold > 0) + warning ("-G is incompatible with PIC code which is the default"); + } + else + mips_abicalls = MIPS_ABICALLS_NO; + + /* -membedded-pic is a form of PIC code suitable for embedded + systems. All calls are made using PC relative addressing, and + all data is addressed using the $gp register. This requires gas, + which does most of the work, and GNU ld, which automatically + expands PC relative calls which are out of range into a longer + instruction sequence. All gcc really does differently is + generate a different sequence for a switch. */ + if (TARGET_EMBEDDED_PIC) + { + flag_pic = 1; + if (TARGET_ABICALLS) + warning ("-membedded-pic and -mabicalls are incompatible"); + + if (g_switch_set) + warning ("-G and -membedded-pic are incompatible"); + + /* Setting mips_section_threshold is not required, because gas + will force everything to be GP addressable anyhow, but + setting it will cause gcc to make better estimates of the + number of instructions required to access a particular data + item. */ + mips_section_threshold = 0x7fffffff; + } + + /* This optimization requires a linker that can support a R_MIPS_LO16 + relocation which is not immediately preceded by a R_MIPS_HI16 relocation. + GNU ld has this support, but not all other MIPS linkers do, so we enable + this optimization only if the user requests it, or if GNU ld is the + standard linker for this configuration. */ + /* ??? This does not work when target addresses are DImode. + This is because we are missing DImode high/lo_sum patterns. */ + if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic + && Pmode == SImode) + mips_split_addresses = 1; + else + mips_split_addresses = 0; + + /* -mrnames says to use the MIPS software convention for register + names instead of the hardware names (ie, $a0 instead of $4). + We do this by switching the names in mips_reg_names, which the + reg_names points into via the REGISTER_NAMES macro. */ + + if (TARGET_NAME_REGS) + bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, + sizeof (mips_reg_names)); + + /* When compiling for the mips16, we can not use floating point. We + record the original hard float value in mips16_hard_float. */ + if (TARGET_MIPS16) + { + if (TARGET_SOFT_FLOAT) + mips16_hard_float = 0; + else + mips16_hard_float = 1; + target_flags |= MASK_SOFT_FLOAT; + + /* Don't run the scheduler before reload, since it tends to + increase register pressure. */ + flag_schedule_insns = 0; + } + + /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only + to avoid using up another bit in target_flags. */ + if (mips_entry_string != NULL) + { + if (*mips_entry_string != '\0') + error ("Invalid option `entry%s'", mips_entry_string); + + if (! TARGET_MIPS16) + warning ("-mentry is only meaningful with -mips-16"); + else + mips_entry = 1; + } + + /* We copy TARGET_MIPS16 into the mips16 global variable, so that + attributes can access it. */ + if (TARGET_MIPS16) + mips16 = 1; + else + mips16 = 0; + + /* Initialize the high and low values for legitimate floating point + constants. Rather than trying to get the accuracy down to the + last bit, just use approximate ranges. */ + dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode); + dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode); + sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode); + sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode); + + mips_print_operand_punct['?'] = 1; + mips_print_operand_punct['#'] = 1; + mips_print_operand_punct['&'] = 1; + mips_print_operand_punct['!'] = 1; + mips_print_operand_punct['*'] = 1; + mips_print_operand_punct['@'] = 1; + mips_print_operand_punct['.'] = 1; + mips_print_operand_punct['('] = 1; + mips_print_operand_punct[')'] = 1; + mips_print_operand_punct['['] = 1; + mips_print_operand_punct[']'] = 1; + mips_print_operand_punct['<'] = 1; + mips_print_operand_punct['>'] = 1; + mips_print_operand_punct['{'] = 1; + mips_print_operand_punct['}'] = 1; + mips_print_operand_punct['^'] = 1; + mips_print_operand_punct['$'] = 1; + mips_print_operand_punct['+'] = 1; + + mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS; + mips_char_to_class['e'] = M16_NA_REGS; + mips_char_to_class['t'] = T_REG; + mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS); + mips_char_to_class['h'] = HI_REG; + mips_char_to_class['l'] = LO_REG; + mips_char_to_class['a'] = HILO_REG; + mips_char_to_class['x'] = MD_REGS; + mips_char_to_class['b'] = ALL_REGS; + mips_char_to_class['y'] = GR_REGS; + mips_char_to_class['z'] = ST_REGS; + + /* Set up array to map GCC register number to debug register number. + Ignore the special purpose register numbers. */ + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + mips_dbx_regno[i] = -1; + + start = GP_DBX_FIRST - GP_REG_FIRST; + for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) + mips_dbx_regno[i] = i + start; + + start = FP_DBX_FIRST - FP_REG_FIRST; + for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) + mips_dbx_regno[i] = i + start; + + /* Set up array giving whether a given register can hold a given mode. + At present, restrict ints from being in FP registers, because reload + is a little enthusiastic about storing extra values in FP registers, + and this is not good for things like OS kernels. Also, due to the + mandatory delay, it is as fast to load from cached memory as to move + from the FP register. */ + + for (mode = VOIDmode; + mode != MAX_MACHINE_MODE; + mode = (enum machine_mode) ((int)mode + 1)) + { + register int size = GET_MODE_SIZE (mode); + register enum mode_class class = GET_MODE_CLASS (mode); + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + { + register int temp; + + if (mode == CCmode) + { + if (mips_isa < 4) + temp = (regno == FPSW_REGNUM); + else + temp = (ST_REG_P (regno) || GP_REG_P (regno) + || FP_REG_P (regno)); + } + + else if (GP_REG_P (regno)) + temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD); + + else if (FP_REG_P (regno)) + temp = ((TARGET_FLOAT64 || ((regno & 1) == 0)) + && (class == MODE_FLOAT + || class == MODE_COMPLEX_FLOAT + || (TARGET_DEBUG_H_MODE && class == MODE_INT)) + && (! TARGET_SINGLE_FLOAT || size <= 4)); + + else if (MD_REG_P (regno)) + temp = (class == MODE_INT + && (size <= UNITS_PER_WORD + || (regno == MD_REG_FIRST + && size == 2 * UNITS_PER_WORD))); + + else + temp = 0; + + mips_hard_regno_mode_ok[(int)mode][regno] = temp; + } + } + + /* Save GPR registers in word_mode sized hunks. word_mode hasn't been + initialized yet, so we can't use that here. */ + gpr_mode = TARGET_64BIT ? DImode : SImode; +} + +/* On the mips16, we want to allocate $24 (T_REG) before other + registers for instructions for which it is possible. This helps + avoid shuffling registers around in order to set up for an xor, + encouraging the compiler to use a cmp instead. */ + +void +mips_order_regs_for_local_alloc () +{ + register int i; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_alloc_order[i] = i; + + if (TARGET_MIPS16) + { + /* It really doesn't matter where we put register 0, since it is + a fixed register anyhow. */ + reg_alloc_order[0] = 24; + reg_alloc_order[24] = 0; + } +} + + +/* The MIPS debug format wants all automatic variables and arguments + to be in terms of the virtual frame pointer (stack pointer before + any adjustment in the function), while the MIPS 3.0 linker wants + the frame pointer to be the stack pointer after the initial + adjustment. So, we do the adjustment here. The arg pointer (which + is eliminated) points to the virtual frame pointer, while the frame + pointer (which may be eliminated) points to the stack pointer after + the initial adjustments. */ + +HOST_WIDE_INT +mips_debugger_offset (addr, offset) + rtx addr; + HOST_WIDE_INT offset; +{ + rtx offset2 = const0_rtx; + rtx reg = eliminate_constant_term (addr, &offset2); + + if (offset == 0) + offset = INTVAL (offset2); + + if (reg == stack_pointer_rtx || reg == frame_pointer_rtx + || reg == hard_frame_pointer_rtx) + { + HOST_WIDE_INT frame_size = (!current_frame_info.initialized) + ? compute_frame_size (get_frame_size ()) + : current_frame_info.total_size; + + /* MIPS16 frame is smaller */ + if (frame_pointer_needed && TARGET_MIPS16) + frame_size -= current_function_outgoing_args_size; + + offset = offset - frame_size; + } + + /* sdbout_parms does not want this to crash for unrecognized cases. */ +#if 0 + else if (reg != arg_pointer_rtx) + abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer."); +#endif + + return offset; +} + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand X. X is an RTL + expression. + + CODE is a value that can be used to specify one of several ways + of printing the operand. It is used when identical operands + must be printed differently depending on the context. CODE + comes from the `%' specification that was used to request + printing of the operand. If the specification was just `%DIGIT' + then CODE is 0; if the specification was `%LTR DIGIT' then CODE + is the ASCII code for LTR. + + If X is a register, this macro should print the register's name. + The names can be found in an array `reg_names' whose type is + `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. + + When the machine description has a specification `%PUNCT' (a `%' + followed by a punctuation character), this macro is called with + a null pointer for X and the punctuation character for CODE. + + The MIPS specific codes are: + + 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x", + 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x", + 'd' output integer constant in decimal, + 'z' if the operand is 0, use $0 instead of normal operand. + 'D' print second register of double-word register operand. + 'L' print low-order register of double-word register operand. + 'M' print high-order register of double-word register operand. + 'C' print part of opcode for a branch condition. + 'N' print part of opcode for a branch condition, inverted. + 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch). + 'B' print 'z' for EQ, 'n' for NE + 'b' print 'n' for EQ, 'z' for NE + 'T' print 'f' for EQ, 't' for NE + 't' print 't' for EQ, 'f' for NE + 'Z' print register and a comma, but print nothing for $fcc0 + '(' Turn on .set noreorder + ')' Turn on .set reorder + '[' Turn on .set noat + ']' Turn on .set at + '<' Turn on .set nomacro + '>' Turn on .set macro + '{' Turn on .set volatile (not GAS) + '}' Turn on .set novolatile (not GAS) + '&' Turn on .set noreorder if filling delay slots + '*' Turn on both .set noreorder and .set nomacro if filling delay slots + '!' Turn on .set nomacro if filling delay slots + '#' Print nop if in a .set noreorder section. + '?' Print 'l' if we are to use a branch likely instead of normal branch. + '@' Print the name of the assembler temporary register (at or $1). + '.' Print the name of the register with a hard-wired zero (zero or $0). + '^' Print the name of the pic call-through register (t9 or $25). + '$' Print the name of the stack pointer register (sp or $29). + '+' Print the name of the gp register (gp or $28). */ + +void +print_operand (file, op, letter) + FILE *file; /* file to write to */ + rtx op; /* operand to print */ + int letter; /* %<letter> or 0 */ +{ + register enum rtx_code code; + + if (PRINT_OPERAND_PUNCT_VALID_P (letter)) + { + switch (letter) + { + case '?': + if (mips_branch_likely) + putc ('l', file); + break; + + case '@': + fputs (reg_names [GP_REG_FIRST + 1], file); + break; + + case '^': + fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file); + break; + + case '.': + fputs (reg_names [GP_REG_FIRST + 0], file); + break; + + case '$': + fputs (reg_names[STACK_POINTER_REGNUM], file); + break; + + case '+': + fputs (reg_names[GP_REG_FIRST + 28], file); + break; + + case '&': + if (final_sequence != 0 && set_noreorder++ == 0) + fputs (".set\tnoreorder\n\t", file); + break; + + case '*': + if (final_sequence != 0) + { + if (set_noreorder++ == 0) + fputs (".set\tnoreorder\n\t", file); + + if (set_nomacro++ == 0) + fputs (".set\tnomacro\n\t", file); + } + break; + + case '!': + if (final_sequence != 0 && set_nomacro++ == 0) + fputs ("\n\t.set\tnomacro", file); + break; + + case '#': + if (set_noreorder != 0) + fputs ("\n\tnop", file); + else if (TARGET_STATS) + fputs ("\n\t#nop", file); + + break; + + case '(': + if (set_noreorder++ == 0) + fputs (".set\tnoreorder\n\t", file); + break; + + case ')': + if (set_noreorder == 0) + error ("internal error: %%) found without a %%( in assembler pattern"); + + else if (--set_noreorder == 0) + fputs ("\n\t.set\treorder", file); + + break; + + case '[': + if (set_noat++ == 0) + fputs (".set\tnoat\n\t", file); + break; + + case ']': + if (set_noat == 0) + error ("internal error: %%] found without a %%[ in assembler pattern"); + else if (--set_noat == 0) + fputs ("\n\t.set\tat", file); + + break; + + case '<': + if (set_nomacro++ == 0) + fputs (".set\tnomacro\n\t", file); + break; + + case '>': + if (set_nomacro == 0) + error ("internal error: %%> found without a %%< in assembler pattern"); + else if (--set_nomacro == 0) + fputs ("\n\t.set\tmacro", file); + + break; + + case '{': + if (set_volatile++ == 0) + fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#"); + break; + + case '}': + if (set_volatile == 0) + error ("internal error: %%} found without a %%{ in assembler pattern"); + else if (--set_volatile == 0) + fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#"); + + break; + + default: + error ("PRINT_OPERAND: Unknown punctuation '%c'", letter); + break; + } + + return; + } + + if (! op) + { + error ("PRINT_OPERAND null pointer"); + return; + } + + code = GET_CODE (op); + + if (code == SIGN_EXTEND) + op = XEXP (op, 0), code = GET_CODE (op); + + if (letter == 'C') + switch (code) + { + case EQ: fputs ("eq", file); break; + case NE: fputs ("ne", file); break; + case GT: fputs ("gt", file); break; + case GE: fputs ("ge", file); break; + case LT: fputs ("lt", file); break; + case LE: fputs ("le", file); break; + case GTU: fputs ("gtu", file); break; + case GEU: fputs ("geu", file); break; + case LTU: fputs ("ltu", file); break; + case LEU: fputs ("leu", file); break; + default: + abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C"); + } + + else if (letter == 'N') + switch (code) + { + case EQ: fputs ("ne", file); break; + case NE: fputs ("eq", file); break; + case GT: fputs ("le", file); break; + case GE: fputs ("lt", file); break; + case LT: fputs ("ge", file); break; + case LE: fputs ("gt", file); break; + case GTU: fputs ("leu", file); break; + case GEU: fputs ("ltu", file); break; + case LTU: fputs ("geu", file); break; + case LEU: fputs ("gtu", file); break; + default: + abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N"); + } + + else if (letter == 'S') + { + char buffer[100]; + + ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op)); + assemble_name (file, buffer); + } + + else if (letter == 'Z') + { + register int regnum; + + if (code != REG) + abort (); + + regnum = REGNO (op); + if (! ST_REG_P (regnum)) + abort (); + + if (regnum != ST_REG_FIRST) + fprintf (file, "%s,", reg_names[regnum]); + } + + else if (code == REG || code == SUBREG) + { + register int regnum; + + if (code == REG) + regnum = REGNO (op); + else + regnum = true_regnum (op); + + if ((letter == 'M' && ! WORDS_BIG_ENDIAN) + || (letter == 'L' && WORDS_BIG_ENDIAN) + || letter == 'D') + regnum++; + + fprintf (file, "%s", reg_names[regnum]); + } + + else if (code == MEM) + output_address (XEXP (op, 0)); + + else if (code == CONST_DOUBLE + && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT) + { + REAL_VALUE_TYPE d; + char s[30]; + + REAL_VALUE_FROM_CONST_DOUBLE (d, op); + REAL_VALUE_TO_DECIMAL (d, "%.20e", s); + fprintf (file, s); + } + + else if (letter == 'x' && GET_CODE (op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op)); + + else if (letter == 'X' && GET_CODE(op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); + + else if (letter == 'd' && GET_CODE(op) == CONST_INT) + fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op))); + + else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0) + fputs (reg_names[GP_REG_FIRST], file); + + else if (letter == 'd' || letter == 'x' || letter == 'X') + fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", + letter); + + else if (letter == 'B') + fputs (code == EQ ? "z" : "n", file); + else if (letter == 'b') + fputs (code == EQ ? "n" : "z", file); + else if (letter == 'T') + fputs (code == EQ ? "f" : "t", file); + else if (letter == 't') + fputs (code == EQ ? "t" : "f", file); + + else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG) + { + /* This case arises on the mips16; see mips16_gp_pseudo_reg. */ + print_operand (file, XEXP (op, 0), letter); + } + + else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op)) + { + fputs ("%gprel(", file); + mips16_output_gp_offset (file, op); + fputs (")", file); + } + + else + output_addr_const (file, op); +} + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand that is a memory + reference whose address is ADDR. ADDR is an RTL expression. + + On some machines, the syntax for a symbolic address depends on + the section that the address refers to. On these machines, + define the macro `ENCODE_SECTION_INFO' to store the information + into the `symbol_ref', and then check for it here. */ + +void +print_operand_address (file, addr) + FILE *file; + rtx addr; +{ + if (!addr) + error ("PRINT_OPERAND_ADDRESS, null pointer"); + + else + switch (GET_CODE (addr)) + { + case REG: + if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM) + abort_with_insn (addr, "Arg pointer not eliminated."); + + fprintf (file, "0(%s)", reg_names [REGNO (addr)]); + break; + + case LO_SUM: + { + register rtx arg0 = XEXP (addr, 0); + register rtx arg1 = XEXP (addr, 1); + + if (! mips_split_addresses) + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM."); + + if (GET_CODE (arg0) != REG) + abort_with_insn (addr, + "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."); + + fprintf (file, "%%lo("); + print_operand_address (file, arg1); + fprintf (file, ")(%s)", reg_names [REGNO (arg0)]); + } + break; + + case PLUS: + { + register rtx reg = 0; + register rtx offset = 0; + register rtx arg0 = XEXP (addr, 0); + register rtx arg1 = XEXP (addr, 1); + + if (GET_CODE (arg0) == REG) + { + reg = arg0; + offset = arg1; + if (GET_CODE (offset) == REG) + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs"); + } + + else if (GET_CODE (arg1) == REG) + reg = arg1, offset = arg0; + else if (CONSTANT_P (arg0) && CONSTANT_P (arg1)) + { + output_addr_const (file, addr); + break; + } + else + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs"); + + if (! CONSTANT_P (offset)) + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2"); + + if (REGNO (reg) == ARG_POINTER_REGNUM) + abort_with_insn (addr, "Arg pointer not eliminated."); + + if (TARGET_MIPS16 + && GET_CODE (offset) == CONST + && mips16_gp_offset_p (offset)) + { + fputs ("%gprel(", file); + mips16_output_gp_offset (file, offset); + fputs (")", file); + } + else + output_addr_const (file, offset); + fprintf (file, "(%s)", reg_names [REGNO (reg)]); + } + break; + + case LABEL_REF: + case SYMBOL_REF: + case CONST_INT: + case CONST: + output_addr_const (file, addr); + break; + + default: + abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1"); + break; + } +} + + +/* If optimizing for the global pointer, keep track of all of the externs, so + that at the end of the file, we can emit the appropriate .extern + declaration for them, before writing out the text section. We assume all + names passed to us are in the permanent obstack, so they will be valid at + the end of the compilation. + + If we have -G 0, or the extern size is unknown, or the object is in a user + specified section that is not .sbss/.sdata, don't bother emitting the + .externs. In the case of user specified sections this behaviour is + required as otherwise GAS will think the object lives in .sbss/.sdata. */ + +int +mips_output_external (file, decl, name) + FILE *file ATTRIBUTE_UNUSED; + tree decl; + char *name; +{ + register struct extern_list *p; + int len; + tree section_name; + + if (TARGET_GP_OPT + && TREE_CODE (decl) != FUNCTION_DECL + && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0 + && ((section_name = DECL_SECTION_NAME (decl)) == NULL + || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0 + || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0)) + { + p = (struct extern_list *) permalloc (sizeof (struct extern_list)); + p->next = extern_head; + p->name = name; + p->size = len; + extern_head = p; + } + +#ifdef ASM_OUTPUT_UNDEF_FUNCTION + if (TREE_CODE (decl) == FUNCTION_DECL + /* ??? Don't include alloca, since gcc will always expand it + inline. If we don't do this, the C++ library fails to build. */ + && strcmp (name, "alloca") + /* ??? Don't include __builtin_next_arg, because then gcc will not + bootstrap under Irix 5.1. */ + && strcmp (name, "__builtin_next_arg")) + { + p = (struct extern_list *) permalloc (sizeof (struct extern_list)); + p->next = extern_head; + p->name = name; + p->size = -1; + extern_head = p; + } +#endif + + return 0; +} + +#ifdef ASM_OUTPUT_UNDEF_FUNCTION +int +mips_output_external_libcall (file, name) + FILE *file; + char *name; +{ + register struct extern_list *p; + + p = (struct extern_list *) permalloc (sizeof (struct extern_list)); + p->next = extern_head; + p->name = name; + p->size = -1; + extern_head = p; + + return 0; +} +#endif + +/* Compute a string to use as a temporary file name. */ + +/* On MSDOS, write temp files in current dir + because there's no place else we can expect to use. */ +#if __MSDOS__ +#ifndef P_tmpdir +#define P_tmpdir "./" +#endif +#endif + +static FILE * +make_temp_file () +{ + FILE *stream; + const char *base = getenv ("TMPDIR"); + int len; + + if (base == 0) + { +#ifdef P_tmpdir + if (access (P_tmpdir, R_OK | W_OK) == 0) + base = P_tmpdir; + else +#endif + if (access ("/usr/tmp", R_OK | W_OK) == 0) + base = "/usr/tmp/"; + else + base = "/tmp/"; + } + + len = strlen (base); + /* temp_filename is global, so we must use malloc, not alloca. */ + temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX")); + strcpy (temp_filename, base); + if (len > 0 && temp_filename[len-1] != '/') + temp_filename[len++] = '/'; + + strcpy (temp_filename + len, "ctXXXXXX"); + mktemp (temp_filename); + + stream = fopen (temp_filename, "w+"); + if (!stream) + pfatal_with_name (temp_filename); + +#ifndef __MSDOS__ + /* In MSDOS, we cannot unlink the temporary file until we are finished using + it. Otherwise, we delete it now, so that it will be gone even if the + compiler happens to crash. */ + unlink (temp_filename); +#endif + return stream; +} + +/* Emit a new filename to a stream. If this is MIPS ECOFF, watch out + for .file's that start within a function. If we are smuggling stabs, try to + put out a MIPS ECOFF file and a stab. */ + +void +mips_output_filename (stream, name) + FILE *stream; + char *name; +{ + static int first_time = 1; + char ltext_label_name[100]; + + if (first_time) + { + first_time = 0; + SET_FILE_NUMBER (); + current_function_file = name; + ASM_OUTPUT_FILENAME (stream, num_source_filenames, name); + /* This tells mips-tfile that stabs will follow. */ + if (!TARGET_GAS && write_symbols == DBX_DEBUG) + fprintf (stream, "\t#@stabs\n"); + } + + else if (write_symbols == DBX_DEBUG) + { + ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0); + fprintf (stream, "%s ", ASM_STABS_OP); + output_quoted_string (stream, name); + fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]); + } + + else if (name != current_function_file + && strcmp (name, current_function_file) != 0) + { + if (inside_function && !TARGET_GAS) + { + if (!file_in_function_warning) + { + file_in_function_warning = 1; + ignore_line_number = 1; + warning ("MIPS ECOFF format does not allow changing filenames within functions with #line"); + } + } + else + { + SET_FILE_NUMBER (); + current_function_file = name; + ASM_OUTPUT_FILENAME (stream, num_source_filenames, name); + } + } +} + +/* Emit a linenumber. For encapsulated stabs, we need to put out a stab + as well as a .loc, since it is possible that MIPS ECOFF might not be + able to represent the location for inlines that come from a different + file. */ + +void +mips_output_lineno (stream, line) + FILE *stream; + int line; +{ + if (write_symbols == DBX_DEBUG) + { + ++sym_lineno; + fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n", + LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line, + LOCAL_LABEL_PREFIX, sym_lineno); + } + + else + { + fprintf (stream, "\n\t%s.loc\t%d %d\n", + (ignore_line_number) ? "#" : "", + num_source_filenames, line); + + LABEL_AFTER_LOC (stream); + } +} + +/* If defined, a C statement to be executed just prior to the output of + assembler code for INSN, to modify the extracted operands so they will be + output differently. + + Here the argument OPVEC is the vector containing the operands extracted + from INSN, and NOPERANDS is the number of elements of the vector which + contain meaningful data for this insn. The contents of this vector are + what will be used to convert the insn template into assembler code, so you + can change the assembler output by changing the contents of the vector. + + We use it to check if the current insn needs a nop in front of it because + of load delays, and also to update the delay slot statistics. */ + +/* ??? There is no real need for this function, because it never actually + emits a NOP anymore. */ + +void +final_prescan_insn (insn, opvec, noperands) + rtx insn; + rtx opvec[] ATTRIBUTE_UNUSED; + int noperands ATTRIBUTE_UNUSED; +{ + if (dslots_number_nops > 0) + { + rtx pattern = PATTERN (insn); + int length = get_attr_length (insn); + + /* Do we need to emit a NOP? */ + if (length == 0 + || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern)) + || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern)) + || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern)) + || (mips_load_reg4 != 0 + && reg_mentioned_p (mips_load_reg4, pattern))) + fputs ("\t#nop\n", asm_out_file); + + else + dslots_load_filled++; + + while (--dslots_number_nops > 0) + fputs ("\t#nop\n", asm_out_file); + + mips_load_reg = 0; + mips_load_reg2 = 0; + mips_load_reg3 = 0; + mips_load_reg4 = 0; + } + + if (TARGET_STATS + && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN)) + dslots_jump_total++; +} + +/* Output at beginning of assembler file. + + If we are optimizing to use the global pointer, create a temporary file to + hold all of the text stuff, and write it out to the end. This is needed + because the MIPS assembler is evidently one pass, and if it hasn't seen the + relevant .comm/.lcomm/.extern/.sdata declaration when the code is + processed, it generates a two instruction sequence. */ + +void +mips_asm_file_start (stream) + FILE *stream; +{ + ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename); + + /* Versions of the MIPS assembler before 2.20 generate errors if a branch + inside of a .set noreorder section jumps to a label outside of the .set + noreorder section. Revision 2.20 just set nobopt silently rather than + fixing the bug. */ + + if (TARGET_MIPS_AS && optimize && flag_delayed_branch) + fprintf (stream, "\t.set\tnobopt\n"); + + /* Generate the pseudo ops that System V.4 wants. */ +#ifndef ABICALLS_ASM_OP +#define ABICALLS_ASM_OP ".abicalls" +#endif + if (TARGET_ABICALLS) + /* ??? but do not want this (or want pic0) if -non-shared? */ + fprintf (stream, "\t%s\n", ABICALLS_ASM_OP); + + if (TARGET_MIPS16) + fprintf (stream, "\t.set\tmips16\n"); + + /* Start a section, so that the first .popsection directive is guaranteed + to have a previously defined section to pop back to. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI) + fprintf (stream, "\t.section\t.text\n"); + + /* This code exists so that we can put all externs before all symbol + references. This is necessary for the MIPS assembler's global pointer + optimizations to work. */ + if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16) + { + asm_out_data_file = stream; + asm_out_text_file = make_temp_file (); + } + + else + asm_out_data_file = asm_out_text_file = stream; + + if (flag_verbose_asm) + fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n", + ASM_COMMENT_START, + mips_section_threshold, mips_cpu_string, mips_isa); +} + +/* If we are optimizing the global pointer, emit the text section now and any + small externs which did not have .comm, etc that are needed. Also, give a + warning if the data area is more than 32K and -pic because 3 instructions + are needed to reference the data pointers. */ + +void +mips_asm_file_end (file) + FILE *file; +{ + char buffer[8192]; + tree name_tree; + struct extern_list *p; + int len; + + if (HALF_PIC_P ()) + { + HALF_PIC_FINISH (file); + } + + if (extern_head) + { + fputs ("\n", file); + + for (p = extern_head; p != 0; p = p->next) + { + name_tree = get_identifier (p->name); + + /* Positively ensure only one .extern for any given symbol. */ + if (! TREE_ASM_WRITTEN (name_tree)) + { + TREE_ASM_WRITTEN (name_tree) = 1; +#ifdef ASM_OUTPUT_UNDEF_FUNCTION + if (p->size == -1) + ASM_OUTPUT_UNDEF_FUNCTION (file, p->name); + else +#endif + { + fputs ("\t.extern\t", file); + assemble_name (file, p->name); + fprintf (file, ", %d\n", p->size); + } + } + } + } + + if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16) + { + fprintf (file, "\n\t.text\n"); + rewind (asm_out_text_file); + if (ferror (asm_out_text_file)) + fatal_io_error (temp_filename); + + while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0) + if ((int) fwrite (buffer, 1, len, file) != len) + pfatal_with_name (asm_file_name); + + if (len < 0) + pfatal_with_name (temp_filename); + + if (fclose (asm_out_text_file) != 0) + pfatal_with_name (temp_filename); + +#ifdef __MSDOS__ + unlink (temp_filename); +#endif + } +} + +/* Emit either a label, .comm, or .lcomm directive, and mark that the symbol + is used, so that we don't emit an .extern for it in mips_asm_file_end. */ + +void +mips_declare_object (stream, name, init_string, final_string, size) + FILE *stream; + char *name; + char *init_string; + char *final_string; + int size; +{ + fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */ + assemble_name (stream, name); + fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */ + + if (TARGET_GP_OPT) + { + tree name_tree = get_identifier (name); + TREE_ASM_WRITTEN (name_tree) = 1; + } +} + +/* Output a double precision value to the assembler. If both the + host and target are IEEE, emit the values in hex. */ + +void +mips_output_double (stream, value) + FILE *stream; + REAL_VALUE_TYPE value; +{ +#ifdef REAL_VALUE_TO_TARGET_DOUBLE + long value_long[2]; + REAL_VALUE_TO_TARGET_DOUBLE (value, value_long); + + fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n", + value_long[0], value, value_long[1]); +#else + fprintf (stream, "\t.double\t%.20g\n", value); +#endif +} + +/* Output a single precision value to the assembler. If both the + host and target are IEEE, emit the values in hex. */ + +void +mips_output_float (stream, value) + FILE *stream; + REAL_VALUE_TYPE value; +{ +#ifdef REAL_VALUE_TO_TARGET_SINGLE + long value_long; + REAL_VALUE_TO_TARGET_SINGLE (value, value_long); + + fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value); +#else + fprintf (stream, "\t.float\t%.12g\n", value); +#endif +} + +/* Return the bytes needed to compute the frame pointer from the current + stack pointer. + + Mips stack frames look like: + + Before call After call + +-----------------------+ +-----------------------+ + high | | | | + mem. | | | | + | caller's temps. | | caller's temps. | + | | | | + +-----------------------+ +-----------------------+ + | | | | + | arguments on stack. | | arguments on stack. | + | | | | + +-----------------------+ +-----------------------+ + | 4 words to save | | 4 words to save | + | arguments passed | | arguments passed | + | in registers, even | | in registers, even | + SP->| if not passed. | VFP->| if not passed. | + +-----------------------+ +-----------------------+ + | | + | fp register save | + | | + +-----------------------+ + | | + | gp register save | + | | + +-----------------------+ + | | + | local variables | + | | + +-----------------------+ + | | + | alloca allocations | + | | + +-----------------------+ + | | + | GP save for V.4 abi | + | | + +-----------------------+ + | | + | arguments on stack | + | | + +-----------------------+ + | 4 words to save | + | arguments passed | + | in registers, even | + low SP->| if not passed. | + memory +-----------------------+ + +*/ + +HOST_WIDE_INT +compute_frame_size (size) + HOST_WIDE_INT size; /* # of var. bytes allocated */ +{ + int regno; + HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */ + HOST_WIDE_INT var_size; /* # bytes that variables take up */ + HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */ + HOST_WIDE_INT extra_size; /* # extra bytes */ + HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */ + HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */ + HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */ + long mask; /* mask of saved gp registers */ + long fmask; /* mask of saved fp registers */ + int fp_inc; /* 1 or 2 depending on the size of fp regs */ + long fp_bits; /* bitmask to use for each fp register */ + + gp_reg_size = 0; + fp_reg_size = 0; + mask = 0; + fmask = 0; + extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0)); + var_size = MIPS_STACK_ALIGN (size); + args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size); + + /* The MIPS 3.0 linker does not like functions that dynamically + allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it + looks like we are trying to create a second frame pointer to the + function, so allocate some stack space to make it happy. */ + + if (args_size == 0 && current_function_calls_alloca) + args_size = 4 * UNITS_PER_WORD; + + total_size = var_size + args_size + extra_size; + + /* Calculate space needed for gp registers. */ + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + { + /* $18 is a special case on the mips16. It may be used to call + a function which returns a floating point value, but it is + marked in call_used_regs. $31 is also a special case. When + not using -mentry, it will be used to copy a return value + into the floating point registers if the return value is + floating point. */ + if (MUST_SAVE_REGISTER (regno) + || (TARGET_MIPS16 + && regno == GP_REG_FIRST + 18 + && regs_ever_live[regno]) + || (TARGET_MIPS16 + && regno == GP_REG_FIRST + 31 + && mips16_hard_float + && ! mips_entry + && ! aggregate_value_p (DECL_RESULT (current_function_decl)) + && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl))) + == MODE_FLOAT) + && (! TARGET_SINGLE_FLOAT + || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl))) + <= 4)))) + { + gp_reg_size += GET_MODE_SIZE (gpr_mode); + mask |= 1L << (regno - GP_REG_FIRST); + + /* The entry and exit pseudo instructions can not save $17 + without also saving $16. */ + if (mips_entry + && regno == GP_REG_FIRST + 17 + && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16)) + { + gp_reg_size += UNITS_PER_WORD; + mask |= 1L << 16; + } + } + } + + /* Calculate space needed for fp registers. */ + if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) + { + fp_inc = 1; + fp_bits = 1; + } + else + { + fp_inc = 2; + fp_bits = 3; + } + + /* This loop must iterate over the same space as its companion in + save_restore_regs. */ + for (regno = (FP_REG_LAST - fp_inc + 1); + regno >= FP_REG_FIRST; + regno -= fp_inc) + { + if (regs_ever_live[regno] && !call_used_regs[regno]) + { + fp_reg_size += fp_inc * UNITS_PER_FPREG; + fmask |= fp_bits << (regno - FP_REG_FIRST); + } + } + + gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); + total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size); + + /* The gp reg is caller saved in the 32 bit ABI, so there is no need + for leaf routines (total_size == extra_size) to save the gp reg. + The gp reg is callee saved in the 64 bit ABI, so all routines must + save the gp reg. This is not a leaf routine if -p, because of the + call to mcount. */ + if (total_size == extra_size + && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) + && ! profile_flag) + total_size = extra_size = 0; + else if (TARGET_ABICALLS) + { + /* Add the context-pointer to the saved registers. */ + gp_reg_size += UNITS_PER_WORD; + mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST); + total_size -= gp_reg_rounded; + gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); + total_size += gp_reg_rounded; + } + + /* Add in space reserved on the stack by the callee for storing arguments + passed in registers. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) + total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size); + + /* The entry pseudo instruction will allocate 32 bytes on the stack. */ + if (mips_entry && total_size > 0 && total_size < 32) + total_size = 32; + + /* Save other computed information. */ + current_frame_info.total_size = total_size; + current_frame_info.var_size = var_size; + current_frame_info.args_size = args_size; + current_frame_info.extra_size = extra_size; + current_frame_info.gp_reg_size = gp_reg_size; + current_frame_info.fp_reg_size = fp_reg_size; + current_frame_info.mask = mask; + current_frame_info.fmask = fmask; + current_frame_info.initialized = reload_completed; + current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD; + current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG); + + if (mask) + { + unsigned long offset; + + /* When using mips_entry, the registers are always saved at the + top of the stack. */ + if (! mips_entry) + offset = (args_size + extra_size + var_size + + gp_reg_size - GET_MODE_SIZE (gpr_mode)); + else + offset = total_size - GET_MODE_SIZE (gpr_mode); + + current_frame_info.gp_sp_offset = offset; + current_frame_info.gp_save_offset = offset - total_size; + } + else + { + current_frame_info.gp_sp_offset = 0; + current_frame_info.gp_save_offset = 0; + } + + if (fmask) + { + unsigned long offset = (args_size + extra_size + var_size + + gp_reg_rounded + fp_reg_size + - fp_inc * UNITS_PER_FPREG); + current_frame_info.fp_sp_offset = offset; + current_frame_info.fp_save_offset = offset - total_size; + } + else + { + current_frame_info.fp_sp_offset = 0; + current_frame_info.fp_save_offset = 0; + } + + /* Ok, we're done. */ + return total_size; +} + +/* Common code to emit the insns (or to write the instructions to a file) + to save/restore registers. + + Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg) + is not modified within save_restore_insns. */ + +#define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0) + +static void +save_restore_insns (store_p, large_reg, large_offset, file) + int store_p; /* true if this is prologue */ + rtx large_reg; /* register holding large offset constant or NULL */ + long large_offset; /* large constant offset value */ + FILE *file; /* file to write instructions instead of making RTL */ +{ + long mask = current_frame_info.mask; + long fmask = current_frame_info.fmask; + int regno; + rtx base_reg_rtx; + HOST_WIDE_INT base_offset; + HOST_WIDE_INT gp_offset; + HOST_WIDE_INT fp_offset; + HOST_WIDE_INT end_offset; + rtx insn; + + if (frame_pointer_needed + && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST)) + abort (); + + if (mask == 0 && fmask == 0) + return; + + /* Save registers starting from high to low. The debuggers prefer at least + the return register be stored at func+4, and also it allows us not to + need a nop in the epilog if at least one register is reloaded in + addition to return address. */ + + /* Save GP registers if needed. */ + if (mask) + { + /* Pick which pointer to use as a base register. For small frames, just + use the stack pointer. Otherwise, use a temporary register. Save 2 + cycles if the save area is near the end of a large frame, by reusing + the constant created in the prologue/epilogue to adjust the stack + frame. */ + + gp_offset = current_frame_info.gp_sp_offset; + end_offset + = gp_offset - (current_frame_info.gp_reg_size + - GET_MODE_SIZE (gpr_mode)); + + if (gp_offset < 0 || end_offset < 0) + fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.", + (long) gp_offset, (long) end_offset); + + /* If we see a large frame in mips16 mode, we save the registers + before adjusting the stack pointer, and load them afterward. */ + else if (TARGET_MIPS16 && large_offset > 32767) + base_reg_rtx = stack_pointer_rtx, base_offset = large_offset; + + else if (gp_offset < 32768) + base_reg_rtx = stack_pointer_rtx, base_offset = 0; + + else if (large_reg != 0 + && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768 + && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768) + { + base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); + base_offset = large_offset; + if (file == 0) + { + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, + stack_pointer_rtx)); + else + insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, + stack_pointer_rtx)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + fprintf (file, "\t%s\t%s,%s,%s\n", + Pmode == DImode ? "daddu" : "addu", + reg_names[MIPS_TEMP2_REGNUM], + reg_names[REGNO (large_reg)], + reg_names[STACK_POINTER_REGNUM]); + } + + else + { + base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); + base_offset = gp_offset; + if (file == 0) + { + rtx gp_offset_rtx = GEN_INT (gp_offset); + + /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P + bit, so make sure that we don't emit anything that can be + split. */ + /* ??? There is no DImode ori immediate pattern, so we can only + do this for 32 bit code. */ + if (large_int (gp_offset_rtx) + && GET_MODE (base_reg_rtx) == SImode) + { + insn = emit_move_insn (base_reg_rtx, + GEN_INT (gp_offset & 0xffff0000)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + insn + = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx, + GEN_INT (gp_offset & 0x0000ffff))); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (base_reg_rtx, gp_offset_rtx); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, + stack_pointer_rtx)); + else + insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, + stack_pointer_rtx)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + fprintf (file, "\tli\t%s,0x%.08lx\t# ", + reg_names[MIPS_TEMP2_REGNUM], (long) base_offset); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset); + fprintf (file, "\n\t%s\t%s,%s,%s\n", + Pmode == DImode ? "daddu" : "addu", + reg_names[MIPS_TEMP2_REGNUM], + reg_names[MIPS_TEMP2_REGNUM], + reg_names[STACK_POINTER_REGNUM]); + } + } + + /* When we restore the registers in MIPS16 mode, then if we are + using a frame pointer, and this is not a large frame, the + current stack pointer will be offset by + current_function_outgoing_args_size. Doing it this way lets + us avoid offsetting the frame pointer before copying it into + the stack pointer; there is no instruction to set the stack + pointer to the sum of a register and a constant. */ + if (TARGET_MIPS16 + && ! store_p + && frame_pointer_needed + && large_offset <= 32767) + base_offset += current_function_outgoing_args_size; + + for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) + if (BITSET_P (mask, regno - GP_REG_FIRST)) + { + if (file == 0) + { + rtx reg_rtx; + rtx mem_rtx + = gen_rtx (MEM, gpr_mode, + gen_rtx (PLUS, Pmode, base_reg_rtx, + GEN_INT (gp_offset - base_offset))); + + RTX_UNCHANGING_P (mem_rtx) = 1; + + /* The mips16 does not have an instruction to load + $31, so we load $7 instead, and work things out + in the caller. */ + if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31) + reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7); + /* The mips16 sometimes needs to save $18. */ + else if (TARGET_MIPS16 + && regno != GP_REG_FIRST + 31 + && ! M16_REG_P (regno)) + { + if (! store_p) + reg_rtx = gen_rtx (REG, gpr_mode, 6); + else + { + reg_rtx = gen_rtx (REG, gpr_mode, 3); + emit_move_insn (reg_rtx, + gen_rtx (REG, gpr_mode, regno)); + } + } + else + reg_rtx = gen_rtx (REG, gpr_mode, regno); + + if (store_p) + { + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + else if (!TARGET_ABICALLS + || (mips_abi != ABI_32 && mips_abi != ABI_O64) + || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) + { + emit_move_insn (reg_rtx, mem_rtx); + if (TARGET_MIPS16 + && regno != GP_REG_FIRST + 31 + && ! M16_REG_P (regno)) + emit_move_insn (gen_rtx (REG, gpr_mode, regno), + reg_rtx); + } + } + else + { + if (store_p || !TARGET_ABICALLS + || (mips_abi != ABI_32 && mips_abi != ABI_O64) + || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) + { + int r = regno; + + /* The mips16 does not have an instruction to + load $31, so we load $7 instead, and work + things out in the caller. */ + if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31) + r = GP_REG_FIRST + 7; + /* The mips16 sometimes needs to save $18. */ + if (TARGET_MIPS16 + && regno != GP_REG_FIRST + 31 + && ! M16_REG_P (regno)) + { + if (! store_p) + r = GP_REG_FIRST + 6; + else + { + r = GP_REG_FIRST + 3; + fprintf (file, "\tmove\t%s,%s\n", + reg_names[r], reg_names[regno]); + } + } + fprintf (file, "\t%s\t%s,", + (TARGET_64BIT + ? (store_p) ? "sd" : "ld" + : (store_p) ? "sw" : "lw"), + reg_names[r]); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, + gp_offset - base_offset); + fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]); + if (! store_p + && TARGET_MIPS16 + && regno != GP_REG_FIRST + 31 + && ! M16_REG_P (regno)) + fprintf (file, "\tmove\t%s,%s\n", + reg_names[regno], reg_names[r]); + } + + } + gp_offset -= GET_MODE_SIZE (gpr_mode); + } + } + else + base_reg_rtx = 0, base_offset = 0; + + /* Save floating point registers if needed. */ + if (fmask) + { + int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2; + int fp_size = fp_inc * UNITS_PER_FPREG; + + /* Pick which pointer to use as a base register. */ + fp_offset = current_frame_info.fp_sp_offset; + end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size); + + if (fp_offset < 0 || end_offset < 0) + fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.", + (long) fp_offset, (long) end_offset); + + else if (fp_offset < 32768) + base_reg_rtx = stack_pointer_rtx, base_offset = 0; + + else if (base_reg_rtx != 0 + && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768 + && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768) + ; /* already set up for gp registers above */ + + else if (large_reg != 0 + && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768 + && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768) + { + base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); + base_offset = large_offset; + if (file == 0) + { + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, + stack_pointer_rtx)); + else + insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, + stack_pointer_rtx)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + + else + fprintf (file, "\t%s\t%s,%s,%s\n", + Pmode == DImode ? "daddu" : "addu", + reg_names[MIPS_TEMP2_REGNUM], + reg_names[REGNO (large_reg)], + reg_names[STACK_POINTER_REGNUM]); + } + + else + { + base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM); + base_offset = fp_offset; + if (file == 0) + { + rtx fp_offset_rtx = GEN_INT (fp_offset); + + /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P + bit, so make sure that we don't emit anything that can be + split. */ + /* ??? There is no DImode ori immediate pattern, so we can only + do this for 32 bit code. */ + if (large_int (fp_offset_rtx) + && GET_MODE (base_reg_rtx) == SImode) + { + insn = emit_move_insn (base_reg_rtx, + GEN_INT (fp_offset & 0xffff0000)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx, + GEN_INT (fp_offset & 0x0000ffff))); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (base_reg_rtx, fp_offset_rtx); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, + stack_pointer_rtx)); + else + insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, + stack_pointer_rtx)); + if (store_p) + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + fprintf (file, "\tli\t%s,0x%.08lx\t# ", + reg_names[MIPS_TEMP2_REGNUM], (long) base_offset); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset); + fprintf (file, "\n\t%s\t%s,%s,%s\n", + Pmode == DImode ? "daddu" : "addu", + reg_names[MIPS_TEMP2_REGNUM], + reg_names[MIPS_TEMP2_REGNUM], + reg_names[STACK_POINTER_REGNUM]); + } + } + + /* This loop must iterate over the same space as its companion in + compute_frame_size. */ + for (regno = (FP_REG_LAST - fp_inc + 1); + regno >= FP_REG_FIRST; + regno -= fp_inc) + if (BITSET_P (fmask, regno - FP_REG_FIRST)) + { + if (file == 0) + { + enum machine_mode sz + = TARGET_SINGLE_FLOAT ? SFmode : DFmode; + rtx reg_rtx = gen_rtx (REG, sz, regno); + rtx mem_rtx = gen_rtx (MEM, sz, + gen_rtx (PLUS, Pmode, base_reg_rtx, + GEN_INT (fp_offset + - base_offset))); + RTX_UNCHANGING_P (mem_rtx) = 1; + + if (store_p) + { + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + else + emit_move_insn (reg_rtx, mem_rtx); + } + else + { + fprintf (file, "\t%s\t%s,", + (TARGET_SINGLE_FLOAT + ? (store_p ? "s.s" : "l.s") + : (store_p ? "s.d" : "l.d")), + reg_names[regno]); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, + fp_offset - base_offset); + fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]); + } + + fp_offset -= fp_size; + } + } +} + +/* Set up the stack and frame (if desired) for the function. */ + +void +function_prologue (file, size) + FILE *file; + int size ATTRIBUTE_UNUSED; +{ +#ifndef FUNCTION_NAME_ALREADY_DECLARED + char *fnname; +#endif + long tsize = current_frame_info.total_size; + + ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl)); + +#ifdef SDB_DEBUGGING_INFO + if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG) + ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); +#endif + + /* In mips16 mode, we may need to generate a 32 bit to handle + floating point arguments. The linker will arrange for any 32 bit + functions to call this stub, which will then jump to the 16 bit + function proper. */ + if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT + && current_function_args_info.fp_code != 0) + build_mips16_function_stub (file); + + inside_function = 1; + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + /* Get the function name the same way that toplev.c does before calling + assemble_start_function. This is needed so that the name used here + exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ + fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + + if (!flag_inhibit_size_directive) + { + fputs ("\t.ent\t", file); + assemble_name (file, fnname); + fputs ("\n", file); + } + + assemble_name (file, fnname); + fputs (":\n", file); +#endif + + if (!flag_inhibit_size_directive) + { + /* .frame FRAMEREG, FRAMESIZE, RETREG */ + fprintf (file, + "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", + (reg_names[(frame_pointer_needed) + ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]), + ((frame_pointer_needed && TARGET_MIPS16) + ? (tsize - current_function_outgoing_args_size) + : tsize), + reg_names[31 + GP_REG_FIRST], + current_frame_info.var_size, + current_frame_info.num_gp, + current_frame_info.num_fp, + current_function_outgoing_args_size, + current_frame_info.extra_size); + + /* .mask MASK, GPOFFSET; .fmask FPOFFSET */ + fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n", + current_frame_info.mask, + current_frame_info.gp_save_offset, + current_frame_info.fmask, + current_frame_info.fp_save_offset); + + /* Require: + OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg. + HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */ + } + + if (mips_entry && ! mips_can_use_return_insn ()) + { + int save16 = BITSET_P (current_frame_info.mask, 16); + int save17 = BITSET_P (current_frame_info.mask, 17); + int save31 = BITSET_P (current_frame_info.mask, 31); + int savearg = 0; + rtx insn; + + /* Look through the initial insns to see if any of them store + the function parameters into the incoming parameter storage + area. If they do, we delete the insn, and save the register + using the entry pseudo-instruction instead. We don't try to + look past a label, jump, or call. */ + for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) + { + rtx note, set, src, dest, base, offset; + int hireg; + + if (GET_CODE (insn) == CODE_LABEL + || GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + break; + if (GET_CODE (insn) != INSN) + continue; + set = PATTERN (insn); + if (GET_CODE (set) != SET) + continue; + + /* An insn storing a function parameter will still have a + REG_EQUIV note on it mentioning the argument pointer. */ + note = find_reg_note (insn, REG_EQUIV, NULL_RTX); + if (note == NULL_RTX) + continue; + if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0))) + continue; + + src = SET_SRC (set); + if (GET_CODE (src) != REG + || REGNO (src) < GP_REG_FIRST + 4 + || REGNO (src) > GP_REG_FIRST + 7) + continue; + + dest = SET_DEST (set); + if (GET_CODE (dest) != MEM) + continue; + if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD) + ; + else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD + && REGNO (src) < GP_REG_FIRST + 7) + ; + else + continue; + offset = const0_rtx; + base = eliminate_constant_term (XEXP (dest, 0), &offset); + if (GET_CODE (base) != REG + || GET_CODE (offset) != CONST_INT) + continue; + if (REGNO (base) == STACK_POINTER_REGNUM + && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD) + ; + else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM + && (INTVAL (offset) + == (tsize + + (REGNO (src) - 4) * UNITS_PER_WORD + - current_function_outgoing_args_size))) + ; + else + continue; + + /* This insn stores a parameter onto the stack, in the same + location where the entry pseudo-instruction will put it. + Delete the insn, and arrange to tell the entry + instruction to save the register. */ + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + + hireg = (REGNO (src) + + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest)) + - 1); + if (hireg > savearg) + savearg = hireg; + } + + /* If this is a varargs function, we need to save all the + registers onto the stack anyhow. */ + if (current_function_stdarg || current_function_varargs) + savearg = GP_REG_FIRST + 7; + + fprintf (file, "\tentry\t"); + if (savearg > 0) + { + if (savearg == GP_REG_FIRST + 4) + fprintf (file, "%s", reg_names[savearg]); + else + fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4], + reg_names[savearg]); + } + if (save16 || save17) + { + if (savearg > 0) + fprintf (file, ","); + fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]); + if (save17) + fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]); + } + if (save31) + { + if (savearg > 0 || save16 || save17) + fprintf (file, ","); + fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]); + } + fprintf (file, "\n"); + } + + if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)) + { + char *sp_str = reg_names[STACK_POINTER_REGNUM]; + + fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n", + reg_names[PIC_FUNCTION_ADDR_REGNUM]); + if (tsize > 0) + { + fprintf (file, "\t%s\t%s,%s,%ld\n", + (Pmode == DImode ? "dsubu" : "subu"), + sp_str, sp_str, tsize); + fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size); + } + + if (dwarf2out_do_frame ()) + dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize); + } +} + +/* Expand the prologue into a bunch of separate insns. */ + +void +mips_expand_prologue () +{ + int regno; + HOST_WIDE_INT tsize; + rtx tmp_rtx = 0; + char *arg_name = 0; + tree fndecl = current_function_decl; + tree fntype = TREE_TYPE (fndecl); + tree fnargs = DECL_ARGUMENTS (fndecl); + rtx next_arg_reg; + int i; + tree next_arg; + tree cur_arg; + CUMULATIVE_ARGS args_so_far; + rtx reg_18_save = NULL_RTX; + + /* If struct value address is treated as the first argument, make it so. */ + if (aggregate_value_p (DECL_RESULT (fndecl)) + && ! current_function_returns_pcc_struct + && struct_value_incoming_rtx == 0) + { + tree type = build_pointer_type (fntype); + tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type); + + DECL_ARG_TYPE (function_result_decl) = type; + TREE_CHAIN (function_result_decl) = fnargs; + fnargs = function_result_decl; + } + + /* Determine the last argument, and get its name. */ + + INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0); + regno = GP_ARG_FIRST; + + for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg) + { + tree passed_type = DECL_ARG_TYPE (cur_arg); + enum machine_mode passed_mode = TYPE_MODE (passed_type); + rtx entry_parm; + + if (TREE_ADDRESSABLE (passed_type)) + { + passed_type = build_pointer_type (passed_type); + passed_mode = Pmode; + } + + entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1); + + if (entry_parm) + { + int words; + + /* passed in a register, so will get homed automatically */ + if (GET_MODE (entry_parm) == BLKmode) + words = (int_size_in_bytes (passed_type) + 3) / 4; + else + words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4; + + regno = REGNO (entry_parm) + words - 1; + } + else + { + regno = GP_ARG_LAST+1; + break; + } + + FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1); + + next_arg = TREE_CHAIN (cur_arg); + if (next_arg == 0) + { + if (DECL_NAME (cur_arg)) + arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg)); + + break; + } + } + + /* In order to pass small structures by value in registers compatibly with + the MIPS compiler, we need to shift the value into the high part of the + register. Function_arg has encoded a PARALLEL rtx, holding a vector of + adjustments to be made as the next_arg_reg variable, so we split up the + insns, and emit them separately. */ + + next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1); + if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL) + { + rtvec adjust = XVEC (next_arg_reg, 0); + int num = GET_NUM_ELEM (adjust); + + for (i = 0; i < num; i++) + { + rtx pattern = RTVEC_ELT (adjust, i); + if (GET_CODE (pattern) != SET + || GET_CODE (SET_SRC (pattern)) != ASHIFT) + abort_with_insn (pattern, "Insn is not a shift"); + + PUT_CODE (SET_SRC (pattern), ASHIFTRT); + emit_insn (pattern); + } + } + + tsize = compute_frame_size (get_frame_size ()); + + /* If this function is a varargs function, store any registers that + would normally hold arguments ($4 - $7) on the stack. */ + if ((mips_abi == ABI_32 || mips_abi == ABI_O64) + && (! mips_entry || mips_can_use_return_insn ()) + && ((TYPE_ARG_TYPES (fntype) != 0 + && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) + != void_type_node)) + || (arg_name != 0 + && ((arg_name[0] == '_' + && strcmp (arg_name, "__builtin_va_alist") == 0) + || (arg_name[0] == 'v' + && strcmp (arg_name, "va_alist") == 0))))) + { + int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD; + rtx ptr = stack_pointer_rtx; + + /* If we are doing svr4-abi, sp has already been decremented by tsize. */ + if (TARGET_ABICALLS) + offset += tsize; + + for (; regno <= GP_ARG_LAST; regno++) + { + if (offset != 0) + ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset)); + emit_move_insn (gen_rtx (MEM, gpr_mode, ptr), + gen_rtx (REG, gpr_mode, regno)); + + offset += GET_MODE_SIZE (gpr_mode); + } + } + + /* If we are using the entry pseudo instruction, it will + automatically subtract 32 from the stack pointer, so we don't + need to. The entry pseudo instruction is emitted by + function_prologue. */ + if (mips_entry && ! mips_can_use_return_insn ()) + { + if (tsize > 0 && tsize <= 32 && frame_pointer_needed) + { + rtx insn; + + /* If we are using a frame pointer with a small stack frame, + we need to initialize it here since it won't be done + below. */ + if (TARGET_MIPS16 && current_function_outgoing_args_size != 0) + { + rtx incr = GEN_INT (current_function_outgoing_args_size); + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, + incr)); + else + insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, + incr)); + } + else if (Pmode == DImode) + insn = emit_insn (gen_movdi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + else + insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + + RTX_FRAME_RELATED_P (insn) = 1; + } + + /* We may need to save $18, if it is used to call a function + which may return a floating point value. Set up a sequence + of instructions to do so. Later on we emit them at the right + moment. */ + if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18)) + { + rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3); + long gp_offset, base_offset; + + gp_offset = current_frame_info.gp_sp_offset; + if (BITSET_P (current_frame_info.mask, 16)) + gp_offset -= UNITS_PER_WORD; + if (BITSET_P (current_frame_info.mask, 17)) + gp_offset -= UNITS_PER_WORD; + if (BITSET_P (current_frame_info.mask, 31)) + gp_offset -= UNITS_PER_WORD; + if (tsize > 32767) + base_offset = tsize; + else + base_offset = 0; + start_sequence (); + emit_move_insn (reg_rtx, + gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18)); + emit_move_insn (gen_rtx (MEM, gpr_mode, + gen_rtx (PLUS, Pmode, stack_pointer_rtx, + GEN_INT (gp_offset + - base_offset))), + reg_rtx); + reg_18_save = gen_sequence (); + end_sequence (); + } + + if (tsize > 32) + tsize -= 32; + else + { + tsize = 0; + if (reg_18_save != NULL_RTX) + emit_insn (reg_18_save); + } + } + + if (tsize > 0) + { + rtx tsize_rtx = GEN_INT (tsize); + + /* If we are doing svr4-abi, sp move is done by + function_prologue. In mips16 mode with a large frame, we + save the registers before adjusting the stack. */ + if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64)) + && (!TARGET_MIPS16 || tsize <= 32767)) + { + rtx insn; + + if (tsize > 32767) + { + tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM); + + /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P + bit, so make sure that we don't emit anything that can be + split. */ + /* ??? There is no DImode ori immediate pattern, so we can only + do this for 32 bit code. */ + if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode) + { + insn = emit_move_insn (tmp_rtx, + GEN_INT (tsize & 0xffff0000)); + RTX_FRAME_RELATED_P (insn) = 1; + insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx, + GEN_INT (tsize & 0x0000ffff))); + RTX_FRAME_RELATED_P (insn) = 1; + } + else + { + insn = emit_move_insn (tmp_rtx, tsize_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } + + tsize_rtx = tmp_rtx; + } + + if (Pmode == DImode) + insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, + tsize_rtx)); + else + insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, + tsize_rtx)); + + RTX_FRAME_RELATED_P (insn) = 1; + } + + if (! mips_entry) + save_restore_insns (1, tmp_rtx, tsize, (FILE *)0); + else if (reg_18_save != NULL_RTX) + emit_insn (reg_18_save); + + if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64)) + && TARGET_MIPS16 + && tsize > 32767) + { + rtx reg_rtx; + + if (!frame_pointer_needed) + abort (); + + reg_rtx = gen_rtx (REG, Pmode, 3); + emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); + emit_move_insn (reg_rtx, tsize_rtx); + if (Pmode == DImode) + emit_insn (gen_subdi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + reg_rtx)); + else + emit_insn (gen_subsi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + reg_rtx)); + emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); + } + + if (frame_pointer_needed) + { + rtx insn = 0; + + /* On the mips16, we encourage the use of unextended + instructions when using the frame pointer by pointing the + frame pointer ahead of the argument space allocated on + the stack. */ + if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64)) + && TARGET_MIPS16 + && tsize > 32767) + { + /* In this case, we have already copied the stack + pointer into the frame pointer, above. We need only + adjust for the outgoing argument size. */ + if (current_function_outgoing_args_size != 0) + { + rtx incr = GEN_INT (current_function_outgoing_args_size); + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + incr)); + else + insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + incr)); + } + } + else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0) + { + rtx incr = GEN_INT (current_function_outgoing_args_size); + if (Pmode == DImode) + insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, + incr)); + else + insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + stack_pointer_rtx, + incr)); + } + else if (Pmode == DImode) + insn = emit_insn (gen_movdi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + else + insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, + stack_pointer_rtx)); + + if (insn) + RTX_FRAME_RELATED_P (insn) = 1; + } + + if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64)) + emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0), + gen_rtx (REG, DImode, 25))); + } + + /* If we are profiling, make sure no instructions are scheduled before + the call to mcount. */ + + if (profile_flag || profile_block_flag) + emit_insn (gen_blockage ()); +} + +/* Do any necessary cleanup after a function to restore stack, frame, + and regs. */ + +#define RA_MASK ((long) 0x80000000) /* 1 << 31 */ +#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) + +void +function_epilogue (file, size) + FILE *file ATTRIBUTE_UNUSED; + HOST_WIDE_INT size ATTRIBUTE_UNUSED; +{ + char *fnname; + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + /* Get the function name the same way that toplev.c does before calling + assemble_start_function. This is needed so that the name used here + exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ + fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + + if (!flag_inhibit_size_directive) + { + fputs ("\t.end\t", file); + assemble_name (file, fnname); + fputs ("\n", file); + } +#endif + + if (TARGET_STATS) + { + int num_gp_regs = current_frame_info.gp_reg_size / 4; + int num_fp_regs = current_frame_info.fp_reg_size / 8; + int num_regs = num_gp_regs + num_fp_regs; + char *name = fnname; + + if (name[0] == '*') + name++; + + dslots_load_total += num_regs; + + fprintf (stderr, + "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d", + name, frame_pointer_needed ? 'y' : 'n', + (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y', + current_function_calls_alloca ? 'y' : 'n', + current_function_calls_setjmp ? 'y' : 'n', + current_frame_info.total_size, + current_function_outgoing_args_size, num_gp_regs, num_fp_regs, + dslots_load_total, dslots_load_filled, + dslots_jump_total, dslots_jump_filled, + num_refs[0], num_refs[1], num_refs[2]); + + if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs) + { + fprintf (stderr, + " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs); + prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS; + } + + if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs) + { + fprintf (stderr, + " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs); + prev_half_pic_refs = HALF_PIC_NUMBER_REFS; + } + + fputc ('\n', stderr); + } + + /* Reset state info for each function. */ + inside_function = 0; + ignore_line_number = 0; + dslots_load_total = 0; + dslots_jump_total = 0; + dslots_load_filled = 0; + dslots_jump_filled = 0; + num_refs[0] = 0; + num_refs[1] = 0; + num_refs[2] = 0; + mips_load_reg = 0; + mips_load_reg2 = 0; + current_frame_info = zero_frame_info; + + while (string_constants != NULL) + { + struct string_constant *next; + + next = string_constants->next; + free (string_constants); + string_constants = next; + } + + /* Restore the output file if optimizing the GP (optimizing the GP causes + the text to be diverted to a tempfile, so that data decls come before + references to the data). */ + + if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS) + asm_out_file = asm_out_data_file; +} + +/* Expand the epilogue into a bunch of separate insns. */ + +void +mips_expand_epilogue () +{ + HOST_WIDE_INT tsize = current_frame_info.total_size; + rtx tsize_rtx = GEN_INT (tsize); + rtx tmp_rtx = (rtx)0; + + if (mips_can_use_return_insn ()) + { + emit_insn (gen_return ()); + return; + } + + if (mips_entry && ! mips_can_use_return_insn ()) + tsize -= 32; + + if (tsize > 32767 && ! TARGET_MIPS16) + { + tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM); + emit_move_insn (tmp_rtx, tsize_rtx); + tsize_rtx = tmp_rtx; + } + + if (tsize > 0) + { + long orig_tsize = tsize; + + if (frame_pointer_needed) + { + emit_insn (gen_blockage ()); + + /* On the mips16, the frame pointer is offset from the stack + pointer by current_function_outgoing_args_size. We + account for that by changing tsize. Note that this can + actually make tsize negative. */ + if (TARGET_MIPS16) + { + tsize -= current_function_outgoing_args_size; + + /* If we have a large frame, it's easier to add to $17 + than to $sp, since the mips16 has no instruction to + add a register to $sp. */ + if (orig_tsize > 32767) + { + rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6); + + emit_move_insn (g6_rtx, GEN_INT (tsize)); + if (Pmode == DImode) + emit_insn (gen_adddi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + g6_rtx)); + else + emit_insn (gen_addsi3 (hard_frame_pointer_rtx, + hard_frame_pointer_rtx, + g6_rtx)); + tsize = 0; + } + + if (tsize && tsize != orig_tsize) + tsize_rtx = GEN_INT (tsize); + } + + if (Pmode == DImode) + emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx)); + else + emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); + } + + /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we + are going to restore it, then we must emit a blockage insn to + prevent the scheduler from moving the restore out of the epilogue. */ + else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64 + && (current_frame_info.mask + & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)))) + emit_insn (gen_blockage ()); + + save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0); + + /* In mips16 mode with a large frame, we adjust the stack + pointer before restoring the registers. In this case, we + should always be using a frame pointer, so everything should + have been handled above. */ + if (tsize > 32767 && TARGET_MIPS16) + abort (); + + emit_insn (gen_blockage ()); + if (Pmode == DImode && tsize != 0) + emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, + tsize_rtx)); + else if (tsize != 0) + emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, + tsize_rtx)); + } + + /* The mips16 loads the return address into $7, not $31. */ + if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0) + emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, + GP_REG_FIRST + 7))); + else + emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode, + GP_REG_FIRST + 31))); +} + +/* Return nonzero if this function is known to have a null epilogue. + This allows the optimizer to omit jumps to jumps if no stack + was created. */ + +int +mips_can_use_return_insn () +{ + if (! reload_completed) + return 0; + + if (regs_ever_live[31] || profile_flag) + return 0; + + /* In mips16 mode, a function which returns a floating point value + needs to arrange to copy the return value into the floating point + registers. */ + if (TARGET_MIPS16 + && mips16_hard_float + && ! aggregate_value_p (DECL_RESULT (current_function_decl)) + && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl))) + == MODE_FLOAT) + && (! TARGET_SINGLE_FLOAT + || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl))) + <= 4))) + return 0; + + if (current_frame_info.initialized) + return current_frame_info.total_size == 0; + + return compute_frame_size (get_frame_size ()) == 0; +} + +/* Choose the section to use for the constant rtx expression X that has + mode MODE. */ + +void +mips_select_rtx_section (mode, x) + enum machine_mode mode; + rtx x ATTRIBUTE_UNUSED; +{ + if (TARGET_MIPS16) + { + /* In mips16 mode, the constant table always goes in the same section + as the function, so that constants can be loaded using PC relative + addressing. */ + function_section (current_function_decl); + } + else if (TARGET_EMBEDDED_DATA) + { + /* For embedded applications, always put constants in read-only data, + in order to reduce RAM usage. */ + READONLY_DATA_SECTION (); + } + else + { + /* For hosted applications, always put constants in small data if + possible, as this gives the best performance. */ + + if (GET_MODE_SIZE (mode) <= mips_section_threshold + && mips_section_threshold > 0) + SMALL_DATA_SECTION (); + else + READONLY_DATA_SECTION (); + } +} + +/* Choose the section to use for DECL. RELOC is true if its value contains + any relocatable expression. + + Some of the logic used here needs to be replicated in + ENCODE_SECTION_INFO in mips.h so that references to these symbols + are done correctly. Specifically, at least all symbols assigned + here to rom (.text and/or .rodata) must not be referenced via + ENCODE_SECTION_INFO with %gprel, as the rom might be too far away. + + If you need to make a change here, you probably should check + ENCODE_SECTION_INFO to see if it needs a similar change. */ + +void +mips_select_section (decl, reloc) + tree decl; + int reloc; +{ + int size = int_size_in_bytes (TREE_TYPE (decl)); + + if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16) + && TREE_CODE (decl) == STRING_CST + && !flag_writable_strings) + /* For embedded position independent code, put constant strings in the + text section, because the data section is limited to 64K in size. + For mips16 code, put strings in the text section so that a PC + relative load instruction can be used to get their address. */ + text_section (); + else if (TARGET_EMBEDDED_DATA) + { + /* For embedded applications, always put an object in read-only data + if possible, in order to reduce RAM usage. */ + + if (((TREE_CODE (decl) == VAR_DECL + && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl) + && DECL_INITIAL (decl) + && (DECL_INITIAL (decl) == error_mark_node + || TREE_CONSTANT (DECL_INITIAL (decl)))) + /* Deal with calls from output_constant_def_contents. */ + || (TREE_CODE (decl) != VAR_DECL + && (TREE_CODE (decl) != STRING_CST + || !flag_writable_strings))) + && ! (flag_pic && reloc)) + READONLY_DATA_SECTION (); + else if (size > 0 && size <= mips_section_threshold) + SMALL_DATA_SECTION (); + else + data_section (); + } + else + { + /* For hosted applications, always put an object in small data if + possible, as this gives the best performance. */ + + if (size > 0 && size <= mips_section_threshold) + SMALL_DATA_SECTION (); + else if (((TREE_CODE (decl) == VAR_DECL + && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl) + && DECL_INITIAL (decl) + && (DECL_INITIAL (decl) == error_mark_node + || TREE_CONSTANT (DECL_INITIAL (decl)))) + /* Deal with calls from output_constant_def_contents. */ + || (TREE_CODE (decl) != VAR_DECL + && (TREE_CODE (decl) != STRING_CST + || !flag_writable_strings))) + && ! (flag_pic && reloc)) + READONLY_DATA_SECTION (); + else + data_section (); + } +} + +#ifdef MIPS_ABI_DEFAULT + +/* Support functions for the 64 bit ABI. */ + +/* Return register to use for a function return value with VALTYPE for function + FUNC. */ + +rtx +mips_function_value (valtype, func) + tree valtype; + tree func ATTRIBUTE_UNUSED; +{ + int reg = GP_RETURN; + enum machine_mode mode = TYPE_MODE (valtype); + enum mode_class mclass = GET_MODE_CLASS (mode); + int unsignedp = TREE_UNSIGNED (valtype); + + /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode + just as PROMOTE_MODE does. */ + mode = promote_mode (valtype, mode, &unsignedp, 1); + + /* ??? How should we return complex float? */ + if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) + { + if (TARGET_SINGLE_FLOAT + && (mclass == MODE_FLOAT + ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4)) + reg = GP_RETURN; + else + reg = FP_RETURN; + } + + else if (TREE_CODE (valtype) == RECORD_TYPE + && mips_abi != ABI_32 + && mips_abi != ABI_O64 + && mips_abi != ABI_EABI) + { + /* A struct with only one or two floating point fields is returned in + the floating point registers. */ + tree field, fields[2]; + int i; + + for (i = 0, field = TYPE_FIELDS (valtype); field; + field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) != FIELD_DECL) + continue; + + if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2) + break; + + fields[i++] = field; + } + + /* Must check i, so that we reject structures with no elements. */ + if (! field) + { + if (i == 1) + { + /* The structure has DImode, but we don't allow DImode values + in FP registers, so we use a PARALLEL even though it isn't + strictly necessary. */ + enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0])); + + return gen_rtx (PARALLEL, mode, + gen_rtvec (1, + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (REG, field_mode, + FP_RETURN), + const0_rtx))); + } + + else if (i == 2) + { + enum machine_mode first_mode + = TYPE_MODE (TREE_TYPE (fields[0])); + enum machine_mode second_mode + = TYPE_MODE (TREE_TYPE (fields[1])); + int first_offset + = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0])); + int second_offset + = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1])); + + return gen_rtx (PARALLEL, mode, + gen_rtvec (2, + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (REG, first_mode, + FP_RETURN), + GEN_INT (first_offset + / BITS_PER_UNIT)), + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (REG, second_mode, + FP_RETURN + 2), + GEN_INT (second_offset + / BITS_PER_UNIT)))); + } + } + } + + return gen_rtx (REG, mode, reg); +} + +/* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return + nonzero when an argument must be passed by reference. */ + +int +function_arg_pass_by_reference (cum, mode, type, named) + CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; + enum machine_mode mode; + tree type; + int named ATTRIBUTE_UNUSED; +{ + int size; + + if (mips_abi != ABI_EABI) + return 0; + + /* ??? How should SCmode be handled? */ + if (type == NULL_TREE || mode == DImode || mode == DFmode) + return 0; + + size = int_size_in_bytes (type); + return size == -1 || size > UNITS_PER_WORD; +} +#endif + +/* This function returns the register class required for a secondary + register when copying between one of the registers in CLASS, and X, + using MODE. If IN_P is nonzero, the copy is going from X to the + register, otherwise the register is the source. A return value of + NO_REGS means that no secondary register is required. */ + +enum reg_class +mips_secondary_reload_class (class, mode, x, in_p) + enum reg_class class; + enum machine_mode mode; + rtx x; + int in_p; +{ + enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS; + int regno = -1; + int gp_reg_p; + + if (GET_CODE (x) == SIGN_EXTEND) + { + int off = 0; + + x = XEXP (x, 0); + + /* We may be called with reg_renumber NULL from regclass. + ??? This is probably a bug. */ + if (reg_renumber) + regno = true_regnum (x); + else + { + while (GET_CODE (x) == SUBREG) + { + off += SUBREG_WORD (x); + x = SUBREG_REG (x); + } + + if (GET_CODE (x) == REG) + regno = REGNO (x) + off; + } + } + + else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) + regno = true_regnum (x); + + gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); + + /* We always require a general register when copying anything to + HILO_REGNUM, except when copying an SImode value from HILO_REGNUM + to a general register, or when copying from register 0. */ + if (class == HILO_REG && regno != GP_REG_FIRST + 0) + return ((! in_p + && gp_reg_p + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode)) + ? NO_REGS : gr_regs); + else if (regno == HILO_REGNUM) + return ((in_p + && class == gr_regs + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode)) + ? NO_REGS : gr_regs); + + /* Copying from HI or LO to anywhere other than a general register + requires a general register. */ + if (class == HI_REG || class == LO_REG || class == MD_REGS) + { + if (TARGET_MIPS16 && in_p) + { + /* We can't really copy to HI or LO at all in mips16 mode. */ + return M16_REGS; + } + return gp_reg_p ? NO_REGS : gr_regs; + } + if (MD_REG_P (regno)) + { + if (TARGET_MIPS16 && ! in_p) + { + /* We can't really copy to HI or LO at all in mips16 mode. */ + return M16_REGS; + } + return class == gr_regs ? NO_REGS : gr_regs; + } + + /* We can only copy a value to a condition code register from a + floating point register, and even then we require a scratch + floating point register. We can only copy a value out of a + condition code register into a general register. */ + if (class == ST_REGS) + { + if (in_p) + return FP_REGS; + return GP_REG_P (regno) ? NO_REGS : GR_REGS; + } + if (ST_REG_P (regno)) + { + if (! in_p) + return FP_REGS; + return class == GR_REGS ? NO_REGS : GR_REGS; + } + + /* In mips16 mode, going between memory and anything but M16_REGS + requires an M16_REG. */ + if (TARGET_MIPS16) + { + if (class != M16_REGS && class != M16_NA_REGS) + { + if (gp_reg_p) + return NO_REGS; + return M16_REGS; + } + if (! gp_reg_p) + { + if (class == M16_REGS || class == M16_NA_REGS) + return NO_REGS; + return M16_REGS; + } + } + + return NO_REGS; +} + +/* For each mips16 function which refers to GP relative symbols, we + use a pseudo register, initialized at the start of the function, to + hold the $gp value. */ + +rtx +mips16_gp_pseudo_reg () +{ + if (mips16_gp_pseudo_rtx == NULL_RTX) + { + rtx const_gp; + rtx insn, scan; + + mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); + RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1; + + /* We want to initialize this to a value which gcc will believe + is constant. */ + const_gp = gen_rtx (CONST, Pmode, + gen_rtx (REG, Pmode, GP_REG_FIRST + 28)); + + start_sequence (); + emit_move_insn (mips16_gp_pseudo_rtx, const_gp); + insn = gen_sequence (); + end_sequence (); + + push_topmost_sequence (); + /* We need to emit the initialization after the FUNCTION_BEG + note, so that it will be integrated. */ + for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan)) + if (GET_CODE (scan) == NOTE + && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG) + break; + if (scan == NULL_RTX) + scan = get_insns (); + insn = emit_insn_after (insn, scan); + pop_topmost_sequence (); + } + + return mips16_gp_pseudo_rtx; +} + +/* Return an RTX which represents the signed 16 bit offset from the + $gp register for the given symbol. This is only used on the + mips16. */ + +rtx +mips16_gp_offset (sym) + rtx sym; +{ + tree gp; + + if (GET_CODE (sym) != SYMBOL_REF + || ! SYMBOL_REF_FLAG (sym)) + abort (); + + /* We use a special identifier to represent the value of the gp + register. */ + gp = get_identifier ("__mips16_gp_value"); + + return gen_rtx (CONST, Pmode, + gen_rtx (MINUS, Pmode, sym, + gen_rtx (SYMBOL_REF, Pmode, + IDENTIFIER_POINTER (gp)))); +} + +/* Return nonzero if the given RTX represents a signed 16 bit offset + from the $gp register. */ + +int +mips16_gp_offset_p (x) + rtx x; +{ + if (GET_CODE (x) == CONST) + x = XEXP (x, 0); + + /* It's OK to add a small integer value to a gp offset. */ + if (GET_CODE (x) == PLUS) + { + if (GET_CODE (XEXP (x, 1)) == CONST_INT + && SMALL_INT (XEXP (x, 1))) + return mips16_gp_offset_p (XEXP (x, 0)); + if (GET_CODE (XEXP (x, 0)) == CONST_INT + && SMALL_INT (XEXP (x, 0))) + return mips16_gp_offset_p (XEXP (x, 1)); + return 0; + } + + /* Make sure it is in the form SYM - __mips16_gp_value. */ + return (GET_CODE (x) == MINUS + && GET_CODE (XEXP (x, 0)) == SYMBOL_REF + && SYMBOL_REF_FLAG (XEXP (x, 0)) + && GET_CODE (XEXP (x, 1)) == SYMBOL_REF + && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0); +} + +/* Output a GP offset. We don't want to print the subtraction of + __mips16_gp_value; it is implicitly represented by the %gprel which + should have been printed by the caller. */ + +static void +mips16_output_gp_offset (file, x) + FILE *file; + rtx x; +{ + if (GET_CODE (x) == CONST) + x = XEXP (x, 0); + + if (GET_CODE (x) == PLUS) + { + mips16_output_gp_offset (file, XEXP (x, 0)); + fputs ("+", file); + mips16_output_gp_offset (file, XEXP (x, 1)); + return; + } + + if (GET_CODE (x) == MINUS + && GET_CODE (XEXP (x, 1)) == SYMBOL_REF + && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0) + { + mips16_output_gp_offset (file, XEXP (x, 0)); + return; + } + + output_addr_const (file, x); +} + +/* Return nonzero if a constant should not be output until after the + function. This is true of most string constants, so that we can + use a more efficient PC relative reference. However, a static + inline function may never call assemble_function_end to write out + the constant pool, so don't try to postpone the constant in that + case. + + ??? It's really a bug that a static inline function can put stuff + in the constant pool even if the function itself is not output. + + We record which string constants we've seen, so that we know which + ones might use the more efficient reference. */ + +int +mips16_constant_after_function_p (x) + tree x; +{ + if (TREE_CODE (x) == STRING_CST + && ! flag_writable_strings + && current_function_decl != 0 + && ! DECL_DEFER_OUTPUT (current_function_decl) + && ! (DECL_INLINE (current_function_decl) + && ((! TREE_PUBLIC (current_function_decl) + && ! TREE_ADDRESSABLE (current_function_decl) + && ! flag_keep_inline_functions) + || DECL_EXTERNAL (current_function_decl)))) + { + struct string_constant *n; + + n = (struct string_constant *) xmalloc (sizeof *n); + n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0); + n->next = string_constants; + string_constants = n; + + return 1; + } + + return 0; +} + +/* Validate a constant for the mips16. This rejects general symbolic + addresses, which must be loaded from memory. If ADDR is nonzero, + this should reject anything which is not a legal address. If + ADDEND is nonzero, this is being added to something else. */ + +int +mips16_constant (x, mode, addr, addend) + rtx x; + enum machine_mode mode; + int addr; + int addend; +{ + while (GET_CODE (x) == CONST) + x = XEXP (x, 0); + + switch (GET_CODE (x)) + { + default: + return 0; + + case PLUS: + return (mips16_constant (XEXP (x, 0), mode, addr, 1) + && mips16_constant (XEXP (x, 1), mode, addr, 1)); + + case SYMBOL_REF: + if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8) + return 0; + if (CONSTANT_POOL_ADDRESS_P (x)) + return 1; + + /* If we aren't looking for a memory address, we can accept a GP + relative symbol, which will have SYMBOL_REF_FLAG set; movsi + knows how to handle this. We can always accept a string + constant, which is the other case in which SYMBOL_REF_FLAG + will be set. */ + if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode) + return 1; + + /* We can accept a string constant, which will have + SYMBOL_REF_FLAG set but must be recognized by name to + distinguish from a GP accessible symbol. The name of a + string constant will have been generated by + ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */ + if (SYMBOL_REF_FLAG (x)) + { + char *name = XSTR (x, 0); + + return (name[0] == '*' + && strncmp (name + 1, LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) == 0); + } + + return 0; + + case LABEL_REF: + if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8) + return 0; + return 1; + + case CONST_INT: + if (addr && ! addend) + return 0; + return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff; + + case REG: + /* We need to treat $gp as a legitimate constant, because + mips16_gp_pseudo_reg assumes that. */ + return REGNO (x) == GP_REG_FIRST + 28; + } +} + +/* Write out code to move floating point arguments in or out of + general registers. Output the instructions to FILE. FP_CODE is + the code describing which arguments are present (see the comment at + the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if + we are copying from the floating point registers. */ + +static void +mips16_fp_args (file, fp_code, from_fp_p) + FILE *file; + int fp_code; + int from_fp_p; +{ + const char *s; + int gparg, fparg; + unsigned int f; + + /* This code only works for the original 32 bit ABI and the O64 ABI. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) + abort (); + + if (from_fp_p) + s = "mfc1"; + else + s = "mtc1"; + gparg = GP_ARG_FIRST; + fparg = FP_ARG_FIRST; + for (f = (unsigned int) fp_code; f != 0; f >>= 2) + { + if ((f & 3) == 1) + { + if ((fparg & 1) != 0) + ++fparg; + fprintf (file, "\t%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg]); + } + else if ((f & 3) == 2) + { + if (TARGET_64BIT) + fprintf (file, "\td%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg]); + else + { + if ((fparg & 1) != 0) + ++fparg; + if (TARGET_BIG_ENDIAN) + fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg + 1], s, + reg_names[gparg + 1], reg_names[fparg]); + else + fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, + reg_names[gparg], reg_names[fparg], s, + reg_names[gparg + 1], reg_names[fparg + 1]); + ++gparg; + ++fparg; + } + } + else + abort (); + + ++gparg; + ++fparg; + } +} + +/* Build a mips16 function stub. This is used for functions which + take aruments in the floating point registers. It is 32 bit code + that moves the floating point args into the general registers, and + then jumps to the 16 bit code. */ + +static void +build_mips16_function_stub (file) + FILE *file; +{ + char *fnname; + char *secname, *stubname; + tree stubid, stubdecl; + int need_comma; + unsigned int f; + + fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + secname = (char *) alloca (strlen (fnname) + 20); + sprintf (secname, ".mips16.fn.%s", fnname); + stubname = (char *) alloca (strlen (fnname) + 20); + sprintf (stubname, "__fn_stub_%s", fnname); + stubid = get_identifier (stubname); + stubdecl = build_decl (FUNCTION_DECL, stubid, + build_function_type (void_type_node, NULL_TREE)); + DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); + + fprintf (file, "\t# Stub function for %s (", current_function_name); + need_comma = 0; + for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2) + { + fprintf (file, "%s%s", + need_comma ? ", " : "", + (f & 3) == 1 ? "float" : "double"); + need_comma = 1; + } + fprintf (file, ")\n"); + + fprintf (file, "\t.set\tnomips16\n"); + function_section (stubdecl); + ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT)); + + /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are + within a .ent, and we can not emit another .ent. */ +#ifndef FUNCTION_NAME_ALREADY_DECLARED + fputs ("\t.ent\t", file); + assemble_name (file, stubname); + fputs ("\n", file); +#endif + + assemble_name (file, stubname); + fputs (":\n", file); + + /* We don't want the assembler to insert any nops here. */ + fprintf (file, "\t.set\tnoreorder\n"); + + mips16_fp_args (file, current_function_args_info.fp_code, 1); + + fprintf (asm_out_file, "\t.set\tnoat\n"); + fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]); + assemble_name (file, fnname); + fprintf (file, "\n"); + fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]); + fprintf (asm_out_file, "\t.set\tat\n"); + + /* Unfortunately, we can't fill the jump delay slot. We can't fill + with one of the mfc1 instructions, because the result is not + available for one instruction, so if the very first instruction + in the function refers to the register, it will see the wrong + value. */ + fprintf (file, "\tnop\n"); + + fprintf (file, "\t.set\treorder\n"); + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + fputs ("\t.end\t", file); + assemble_name (file, stubname); + fputs ("\n", file); +#endif + + fprintf (file, "\t.set\tmips16\n"); + + function_section (current_function_decl); +} + +/* We keep a list of functions for which we have already built stubs + in build_mips16_call_stub. */ + +struct mips16_stub +{ + struct mips16_stub *next; + char *name; + int fpret; +}; + +static struct mips16_stub *mips16_stubs; + +/* Build a call stub for a mips16 call. A stub is needed if we are + passing any floating point values which should go into the floating + point registers. If we are, and the call turns out to be to a 32 + bit function, the stub will be used to move the values into the + floating point registers before calling the 32 bit function. The + linker will magically adjust the function call to either the 16 bit + function or the 32 bit stub, depending upon where the function call + is actually defined. + + Similarly, we need a stub if the return value might come back in a + floating point register. + + RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn + (RETVAL is NULL if this is call rather than call_value). FP_CODE + is the code built by function_arg. This function returns a nonzero + value if it builds the call instruction itself. */ + +int +build_mips16_call_stub (retval, fnmem, arg_size, fp_code) + rtx retval; + rtx fnmem; + rtx arg_size; + int fp_code; +{ + int fpret; + rtx fn; + char *fnname, *secname, *stubname; + struct mips16_stub *l; + tree stubid, stubdecl; + int need_comma; + unsigned int f; + + /* We don't need to do anything if we aren't in mips16 mode, or if + we were invoked with the -msoft-float option. */ + if (! TARGET_MIPS16 || ! mips16_hard_float) + return 0; + + /* Figure out whether the value might come back in a floating point + register. */ + fpret = (retval != 0 + && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT + && (! TARGET_SINGLE_FLOAT + || GET_MODE_SIZE (GET_MODE (retval)) <= 4)); + + /* We don't need to do anything if there were no floating point + arguments and the value will not be returned in a floating point + register. */ + if (fp_code == 0 && ! fpret) + return 0; + + if (GET_CODE (fnmem) != MEM) + abort (); + fn = XEXP (fnmem, 0); + + /* We don't need to do anything if this is a call to a special + mips16 support function. */ + if (GET_CODE (fn) == SYMBOL_REF + && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0) + return 0; + + /* This code will only work for o32 and o64 abis. The other ABI's + require more sophisticated support. */ + if (mips_abi != ABI_32 && mips_abi != ABI_O64) + abort (); + + /* We can only handle SFmode and DFmode floating point return + values. */ + if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode) + abort (); + + /* If we're calling via a function pointer, then we must always call + via a stub. There are magic stubs provided in libgcc.a for each + of the required cases. Each of them expects the function address + to arrive in register $2. */ + + if (GET_CODE (fn) != SYMBOL_REF) + { + char buf[30]; + tree id; + rtx stub_fn, stub_mem, insn; + + /* ??? If this code is modified to support other ABI's, we need + to handle PARALLEL return values here. */ + + sprintf (buf, "__mips16_call_stub_%s%d", + (fpret + ? (GET_MODE (retval) == SFmode ? "sf_" : "df_") + : ""), + fp_code); + id = get_identifier (buf); + stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id)); + stub_mem = gen_rtx (MEM, Pmode, stub_fn); + + emit_move_insn (gen_rtx (REG, Pmode, 2), fn); + + if (retval == NULL_RTX) + insn = gen_call_internal0 (stub_mem, arg_size, + gen_rtx (REG, SImode, + GP_REG_FIRST + 31)); + else + insn = gen_call_value_internal0 (retval, stub_mem, arg_size, + gen_rtx (REG, SImode, + GP_REG_FIRST + 31)); + insn = emit_call_insn (insn); + + /* Put the register usage information on the CALL. */ + if (GET_CODE (insn) != CALL_INSN) + abort (); + CALL_INSN_FUNCTION_USAGE (insn) = + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)), + CALL_INSN_FUNCTION_USAGE (insn)); + + /* If we are handling a floating point return value, we need to + save $18 in the function prologue. Putting a note on the + call will mean that regs_ever_live[$18] will be true if the + call is not eliminated, and we can check that in the prologue + code. */ + if (fpret) + CALL_INSN_FUNCTION_USAGE (insn) = + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)), + CALL_INSN_FUNCTION_USAGE (insn)); + + /* Return 1 to tell the caller that we've generated the call + insn. */ + return 1; + } + + /* We know the function we are going to call. If we have already + built a stub, we don't need to do anything further. */ + + fnname = XSTR (fn, 0); + for (l = mips16_stubs; l != NULL; l = l->next) + if (strcmp (l->name, fnname) == 0) + break; + + if (l == NULL) + { + /* Build a special purpose stub. When the linker sees a + function call in mips16 code, it will check where the target + is defined. If the target is a 32 bit call, the linker will + search for the section defined here. It can tell which + symbol this section is associated with by looking at the + relocation information (the name is unreliable, since this + might be a static function). If such a section is found, the + linker will redirect the call to the start of the magic + section. + + If the function does not return a floating point value, the + special stub section is named + .mips16.call.FNNAME + + If the function does return a floating point value, the stub + section is named + .mips16.call.fp.FNNAME + */ + + secname = (char *) alloca (strlen (fnname) + 40); + sprintf (secname, ".mips16.call.%s%s", + fpret ? "fp." : "", + fnname); + stubname = (char *) alloca (strlen (fnname) + 20); + sprintf (stubname, "__call_stub_%s%s", + fpret ? "fp_" : "", + fnname); + stubid = get_identifier (stubname); + stubdecl = build_decl (FUNCTION_DECL, stubid, + build_function_type (void_type_node, NULL_TREE)); + DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); + + fprintf (asm_out_file, "\t# Stub function to call %s%s (", + (fpret + ? (GET_MODE (retval) == SFmode ? "float " : "double ") + : ""), + fnname); + need_comma = 0; + for (f = (unsigned int) fp_code; f != 0; f >>= 2) + { + fprintf (asm_out_file, "%s%s", + need_comma ? ", " : "", + (f & 3) == 1 ? "float" : "double"); + need_comma = 1; + } + fprintf (asm_out_file, ")\n"); + + fprintf (asm_out_file, "\t.set\tnomips16\n"); + assemble_start_function (stubdecl, stubname); + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + fputs ("\t.ent\t", asm_out_file); + assemble_name (asm_out_file, stubname); + fputs ("\n", asm_out_file); + + assemble_name (asm_out_file, stubname); + fputs (":\n", asm_out_file); +#endif + + /* We build the stub code by hand. That's the only way we can + do it, since we can't generate 32 bit code during a 16 bit + compilation. */ + + /* We don't want the assembler to insert any nops here. */ + fprintf (asm_out_file, "\t.set\tnoreorder\n"); + + mips16_fp_args (asm_out_file, fp_code, 0); + + if (! fpret) + { + fprintf (asm_out_file, "\t.set\tnoat\n"); + fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1], + fnname); + fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]); + fprintf (asm_out_file, "\t.set\tat\n"); + /* Unfortunately, we can't fill the jump delay slot. We + can't fill with one of the mtc1 instructions, because the + result is not available for one instruction, so if the + very first instruction in the function refers to the + register, it will see the wrong value. */ + fprintf (asm_out_file, "\tnop\n"); + } + else + { + fprintf (asm_out_file, "\tmove\t%s,%s\n", + reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]); + fprintf (asm_out_file, "\tjal\t%s\n", fnname); + /* As above, we can't fill the delay slot. */ + fprintf (asm_out_file, "\tnop\n"); + if (GET_MODE (retval) == SFmode) + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]); + else + { + if (TARGET_BIG_ENDIAN) + { + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 2], + reg_names[FP_REG_FIRST + 1]); + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 3], + reg_names[FP_REG_FIRST + 0]); + } + else + { + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 2], + reg_names[FP_REG_FIRST + 0]); + fprintf (asm_out_file, "\tmfc1\t%s,%s\n", + reg_names[GP_REG_FIRST + 3], + reg_names[FP_REG_FIRST + 1]); + } + } + fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]); + /* As above, we can't fill the delay slot. */ + fprintf (asm_out_file, "\tnop\n"); + } + + fprintf (asm_out_file, "\t.set\treorder\n"); + +#ifdef ASM_DECLARE_FUNCTION_SIZE + ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl); +#endif + +#ifndef FUNCTION_NAME_ALREADY_DECLARED + fputs ("\t.end\t", asm_out_file); + assemble_name (asm_out_file, stubname); + fputs ("\n", asm_out_file); +#endif + + fprintf (asm_out_file, "\t.set\tmips16\n"); + + /* Record this stub. */ + l = (struct mips16_stub *) xmalloc (sizeof *l); + l->name = (char *) xmalloc (strlen (fnname) + 1); + strcpy (l->name, fnname); + l->fpret = fpret; + l->next = mips16_stubs; + mips16_stubs = l; + } + + /* If we expect a floating point return value, but we've built a + stub which does not expect one, then we're in trouble. We can't + use the existing stub, because it won't handle the floating point + value. We can't build a new stub, because the linker won't know + which stub to use for the various calls in this object file. + Fortunately, this case is illegal, since it means that a function + was declared in two different ways in a single compilation. */ + if (fpret && ! l->fpret) + error ("can not handle inconsistent calls to `%s'", fnname); + + /* If we are calling a stub which handles a floating point return + value, we need to arrange to save $18 in the prologue. We do + this by marking the function call as using the register. The + prologue will later see that it is used, and emit code to save + it. */ + + if (l->fpret) + { + rtx insn; + + if (retval == NULL_RTX) + insn = gen_call_internal0 (fnmem, arg_size, + gen_rtx (REG, SImode, + GP_REG_FIRST + 31)); + else + insn = gen_call_value_internal0 (retval, fnmem, arg_size, + gen_rtx (REG, SImode, + GP_REG_FIRST + 31)); + insn = emit_call_insn (insn); + + if (GET_CODE (insn) != CALL_INSN) + abort (); + + CALL_INSN_FUNCTION_USAGE (insn) = + gen_rtx (EXPR_LIST, VOIDmode, + gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)), + CALL_INSN_FUNCTION_USAGE (insn)); + + /* Return 1 to tell the caller that we've generated the call + insn. */ + return 1; + } + + /* Return 0 to let the caller generate the call insn. */ + return 0; +} + +/* This function looks through the code for a function, and tries to + optimize the usage of the $gp register. We arrange to copy $gp + into a pseudo-register, and then let gcc's normal reload handling + deal with the pseudo-register. Unfortunately, if reload choose to + put the pseudo-register into a call-clobbered register, it will + emit saves and restores for that register around any function + calls. We don't need the saves, and it's faster to copy $gp than + to do an actual restore. ??? This still means that we waste a + stack slot. + + This is an optimization, and the code which gcc has actually + generated is correct, so we do not need to catch all cases. */ + +static void +mips16_optimize_gp (first) + rtx first; +{ + rtx gpcopy, slot, insn; + + /* Look through the instructions. Set GPCOPY to the register which + holds a copy of $gp. Set SLOT to the stack slot where it is + saved. If we find an instruction which sets GPCOPY to anything + other than $gp or SLOT, then we can't use it. If we find an + instruction which sets SLOT to anything other than GPCOPY, we + can't use it. */ + + gpcopy = NULL_RTX; + slot = NULL_RTX; + for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn)) + { + rtx set; + + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + continue; + + set = PATTERN (insn); + + /* We know that all references to memory will be inside a SET, + because there is no other way to access memory on the mips16. + We don't have to worry about a PARALLEL here, because the + mips.md file will never generate them for memory references. */ + if (GET_CODE (set) != SET) + continue; + + if (gpcopy == NULL_RTX + && GET_CODE (SET_SRC (set)) == CONST + && GET_CODE (XEXP (SET_SRC (set), 0)) == REG + && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28 + && GET_CODE (SET_DEST (set)) == REG + && GET_MODE (SET_DEST (set)) == Pmode) + gpcopy = SET_DEST (set); + else if (slot == NULL_RTX + && gpcopy != NULL_RTX + && GET_CODE (SET_DEST (set)) == MEM + && GET_CODE (SET_SRC (set)) == REG + && REGNO (SET_SRC (set)) == REGNO (gpcopy) + && GET_MODE (SET_DEST (set)) == Pmode) + { + rtx base, offset; + + offset = const0_rtx; + base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); + if (GET_CODE (base) == REG + && (REGNO (base) == STACK_POINTER_REGNUM + || REGNO (base) == FRAME_POINTER_REGNUM)) + slot = SET_DEST (set); + } + else if (gpcopy != NULL_RTX + && (GET_CODE (SET_DEST (set)) == REG + || GET_CODE (SET_DEST (set)) == SUBREG) + && reg_overlap_mentioned_p (SET_DEST (set), gpcopy) + && (GET_CODE (SET_DEST (set)) != REG + || REGNO (SET_DEST (set)) != REGNO (gpcopy) + || GET_MODE (SET_DEST (set)) != Pmode + || ((GET_CODE (SET_SRC (set)) != CONST + || GET_CODE (XEXP (SET_SRC (set), 0)) != REG + || (REGNO (XEXP (SET_SRC (set), 0)) + != GP_REG_FIRST + 28)) + && ! rtx_equal_p (SET_SRC (set), slot)))) + break; + else if (slot != NULL_RTX + && GET_CODE (SET_DEST (set)) == MEM + && rtx_equal_p (SET_DEST (set), slot) + && (GET_CODE (SET_SRC (set)) != REG + || REGNO (SET_SRC (set)) != REGNO (gpcopy))) + break; + } + + /* If we couldn't find a unique value for GPCOPY or SLOT, then try a + different optimization. Any time we find a copy of $28 into a + register, followed by an add of a symbol_ref to that register, we + convert it to load the value from the constant table instead. + The copy and add will take six bytes, just as the load and + constant table entry will take six bytes. However, it is + possible that the constant table entry will be shared. + + This could be a peephole optimization, but I don't know if the + peephole code can call force_const_mem. + + Using the same register for the copy of $28 and the add of the + symbol_ref is actually pretty likely, since the add instruction + requires the destination and the first addend to be the same + register. */ + + if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX) + { + rtx next; + + /* This optimization is only reasonable if the constant table + entries are only 4 bytes. */ + if (Pmode != SImode) + return; + + for (insn = first; insn != NULL_RTX; insn = next) + { + rtx set1, set2; + + next = insn; + do + { + next = NEXT_INSN (next); + } + while (next != NULL_RTX + && (GET_CODE (next) == NOTE + || (GET_CODE (next) == INSN + && (GET_CODE (PATTERN (next)) == USE + || GET_CODE (PATTERN (next)) == CLOBBER)))); + + if (next == NULL_RTX) + break; + + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + continue; + + if (GET_RTX_CLASS (GET_CODE (next)) != 'i') + continue; + + set1 = PATTERN (insn); + if (GET_CODE (set1) != SET) + continue; + set2 = PATTERN (next); + if (GET_CODE (set2) != SET) + continue; + + if (GET_CODE (SET_DEST (set1)) == REG + && GET_CODE (SET_SRC (set1)) == CONST + && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG + && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28 + && rtx_equal_p (SET_DEST (set1), SET_DEST (set2)) + && GET_CODE (SET_SRC (set2)) == PLUS + && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0)) + && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1)) + && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS) + { + rtx sym; + + /* We've found a case we can change to load from the + constant table. */ + + sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0); + if (GET_CODE (sym) != SYMBOL_REF) + abort (); + emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1), + force_const_mem (Pmode, sym)), + next); + + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + + PUT_CODE (next, NOTE); + NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (next) = 0; + } + } + + return; + } + + /* We can safely remove all assignments to SLOT from GPCOPY, and + replace all assignments from SLOT to GPCOPY with assignments from + $28. */ + + for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn)) + { + rtx set; + + if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + continue; + + set = PATTERN (insn); + if (GET_CODE (set) != SET + || GET_MODE (SET_DEST (set)) != Pmode) + continue; + + if (GET_CODE (SET_DEST (set)) == MEM + && rtx_equal_p (SET_DEST (set), slot) + && GET_CODE (SET_SRC (set)) == REG + && REGNO (SET_SRC (set)) == REGNO (gpcopy)) + { + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + else if (GET_CODE (SET_DEST (set)) == REG + && REGNO (SET_DEST (set)) == REGNO (gpcopy) + && GET_CODE (SET_SRC (set)) == MEM + && rtx_equal_p (SET_SRC (set), slot)) + { + emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set), + gen_rtx (CONST, Pmode, + gen_rtx (REG, Pmode, + GP_REG_FIRST + 28))), + insn); + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + } + } +} + +/* We keep a list of constants we which we have to add to internal + constant tables in the middle of large functions. */ + +struct constant +{ + struct constant *next; + rtx value; + rtx label; + enum machine_mode mode; +}; + +/* Add a constant to the list in *PCONSTANTS. */ + +static rtx +add_constant (pconstants, val, mode) + struct constant **pconstants; + rtx val; + enum machine_mode mode; +{ + struct constant *c; + + for (c = *pconstants; c != NULL; c = c->next) + if (mode == c->mode && rtx_equal_p (val, c->value)) + return c->label; + + c = (struct constant *) xmalloc (sizeof *c); + c->value = val; + c->mode = mode; + c->label = gen_label_rtx (); + c->next = *pconstants; + *pconstants = c; + return c->label; +} + +/* Dump out the constants in CONSTANTS after INSN. */ + +static void +dump_constants (constants, insn) + struct constant *constants; + rtx insn; +{ + struct constant *c; + int align; + + c = constants; + align = 0; + while (c != NULL) + { + rtx r; + struct constant *next; + + switch (GET_MODE_SIZE (c->mode)) + { + case 1: + align = 0; + break; + case 2: + if (align < 1) + insn = emit_insn_after (gen_align_2 (), insn); + align = 1; + break; + case 4: + if (align < 2) + insn = emit_insn_after (gen_align_4 (), insn); + align = 2; + break; + default: + if (align < 3) + insn = emit_insn_after (gen_align_8 (), insn); + align = 3; + break; + } + + insn = emit_label_after (c->label, insn); + + switch (c->mode) + { + case QImode: + r = gen_consttable_qi (c->value); + break; + case HImode: + r = gen_consttable_hi (c->value); + break; + case SImode: + r = gen_consttable_si (c->value); + break; + case SFmode: + r = gen_consttable_sf (c->value); + break; + case DImode: + r = gen_consttable_di (c->value); + break; + case DFmode: + r = gen_consttable_df (c->value); + break; + default: + abort (); + } + + insn = emit_insn_after (r, insn); + + next = c->next; + free (c); + c = next; + } + + emit_barrier_after (insn); +} + +/* Find the symbol in an address expression. */ + +static rtx +mips_find_symbol (addr) + rtx addr; +{ + if (GET_CODE (addr) == MEM) + addr = XEXP (addr, 0); + while (GET_CODE (addr) == CONST) + addr = XEXP (addr, 0); + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) + return addr; + if (GET_CODE (addr) == PLUS) + { + rtx l1, l2; + + l1 = mips_find_symbol (XEXP (addr, 0)); + l2 = mips_find_symbol (XEXP (addr, 1)); + if (l1 != NULL_RTX && l2 == NULL_RTX) + return l1; + else if (l1 == NULL_RTX && l2 != NULL_RTX) + return l2; + } + return NULL_RTX; +} + +/* Exported to toplev.c. + + Do a final pass over the function, just before delayed branch + scheduling. */ + +void +machine_dependent_reorg (first) + rtx first; +{ + int insns_len, max_internal_pool_size, pool_size, addr; + rtx insn; + struct constant *constants; + + if (! TARGET_MIPS16) + return; + + /* If $gp is used, try to remove stores, and replace loads with + copies from $gp. */ + if (optimize) + mips16_optimize_gp (first); + + /* Scan the function looking for PC relative loads which may be out + of range. All such loads will either be from the constant table, + or be getting the address of a constant string. If the size of + the function plus the size of the constant table is less than + 0x8000, then all loads are in range. */ + + insns_len = 0; + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + insns_len += get_attr_length (insn) * 2; + + /* ??? We put switch tables in .text, but we don't define + JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not + compute their lengths correctly. */ + if (GET_CODE (insn) == JUMP_INSN) + { + rtx body; + + body = PATTERN (insn); + if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) + insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC) + * GET_MODE_SIZE (GET_MODE (body))); + insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1; + } + } + + /* Store the original value of insns_len in current_frame_info, so + that simple_memory_operand can look at it. */ + current_frame_info.insns_len = insns_len; + + pool_size = get_pool_size (); + if (insns_len + pool_size + mips_string_length < 0x8000) + return; + + /* Loop over the insns and figure out what the maximum internal pool + size could be. */ + max_internal_pool_size = 0; + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SET) + { + rtx src; + + src = mips_find_symbol (SET_SRC (PATTERN (insn))); + if (src == NULL_RTX) + continue; + if (CONSTANT_POOL_ADDRESS_P (src)) + max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src)); + else if (SYMBOL_REF_FLAG (src)) + max_internal_pool_size += GET_MODE_SIZE (Pmode); + } + } + + constants = NULL; + addr = 0; + + for (insn = first; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == INSN + && GET_CODE (PATTERN (insn)) == SET) + { + rtx val, src; + enum machine_mode mode; + + val = NULL_RTX; + src = mips_find_symbol (SET_SRC (PATTERN (insn))); + if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src)) + { + /* ??? This is very conservative, which means that we + will generate too many copies of the constant table. + The only solution would seem to be some form of + relaxing. */ + if (((insns_len - addr) + + max_internal_pool_size + + get_pool_offset (src)) + >= 0x8000) + { + val = get_pool_constant (src); + mode = get_pool_mode (src); + } + max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src)); + } + else if (src != NULL_RTX && SYMBOL_REF_FLAG (src)) + { + /* Including all of mips_string_length is conservative, + and so is including all of max_internal_pool_size. */ + if (((insns_len - addr) + + max_internal_pool_size + + pool_size + + mips_string_length) + >= 0x8000) + val = src; + mode = Pmode; + max_internal_pool_size -= Pmode; + } + + if (val != NULL_RTX) + { + rtx lab, newsrc; + + /* This PC relative load is out of range. ??? In the + case of a string constant, we are only guessing that + it is range, since we don't know the offset of a + particular string constant. */ + + lab = add_constant (&constants, val, mode); + newsrc = gen_rtx (MEM, mode, + gen_rtx (LABEL_REF, VOIDmode, lab)); + RTX_UNCHANGING_P (newsrc) = 1; + PATTERN (insn) = gen_rtx (SET, VOIDmode, + SET_DEST (PATTERN (insn)), + newsrc); + INSN_CODE (insn) = -1; + } + } + + addr += get_attr_length (insn) * 2; + + /* ??? We put switch tables in .text, but we don't define + JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not + compute their lengths correctly. */ + if (GET_CODE (insn) == JUMP_INSN) + { + rtx body; + + body = PATTERN (insn); + if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) + addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC) + * GET_MODE_SIZE (GET_MODE (body))); + addr += GET_MODE_SIZE (GET_MODE (body)) - 1; + } + + if (GET_CODE (insn) == BARRIER) + { + /* Output any constants we have accumulated. Note that we + don't need to change ADDR, since its only use is + subtraction from INSNS_LEN, and both would be changed by + the same amount. + ??? If the instructions up to the next barrier reuse a + constant, it would often be better to continue + accumulating. */ + if (constants != NULL) + dump_constants (constants, insn); + constants = NULL; + } + + /* ??? If we don't find a barrier within 0x8000 bytes of + instructions and constants in CONSTANTS, we need to invent + one. This seems sufficiently unlikely that I am not going to + worry about it. */ + } + + if (constants != NULL) + { + rtx label, jump, barrier; + + label = gen_label_rtx (); + jump = emit_jump_insn_after (gen_jump (label), get_last_insn ()); + JUMP_LABEL (jump) = label; + LABEL_NUSES (label) = 1; + barrier = emit_barrier_after (jump); + emit_label_after (label, barrier); + dump_constants (constants, barrier); + constants = NULL; + } + + /* ??? If we output all references to a constant in internal + constants table, we don't need to output the constant in the real + constant table, but we have no way to prevent that. */ +} + +/* Return nonzero if X is a SIGN or ZERO extend operator. */ +int +extend_operator (x, mode) + rtx x; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + enum rtx_code code = GET_CODE (x); + return code == SIGN_EXTEND || code == ZERO_EXTEND; +} + +/* Accept any operator that can be used to shift the high half of the + input value to the lower half, suitable for truncation. The + remainder (the lower half of the input, and the upper half of the + output) will be discarded. */ +int +highpart_shift_operator (x, mode) + rtx x; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + enum rtx_code code = GET_CODE (x); + return (code == LSHIFTRT + || code == ASHIFTRT + || code == ROTATERT + || code == ROTATE); +} diff --git a/contrib/gcc/config/mips/mips.h b/contrib/gcc/config/mips/mips.h new file mode 100644 index 000000000000..7360e1b5d64a --- /dev/null +++ b/contrib/gcc/config/mips/mips.h @@ -0,0 +1,4720 @@ +/* Definitions of target machine for GNU compiler. MIPS version. + Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc. + Contributed by A. Lichnewsky (lich@inria.inria.fr). + Changed by Michael Meissner (meissner@osf.org). + 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and + Brendan Eich (brendan@microunity.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* Standard GCC variables that we reference. */ + +extern char *asm_file_name; +extern char call_used_regs[]; +extern int current_function_calls_alloca; +extern char *language_string; +extern int may_call_alloca; +extern char **save_argv; +extern int target_flags; +extern char *version_string; + +/* MIPS external variables defined in mips.c. */ + +/* comparison type */ +enum cmp_type { + CMP_SI, /* compare four byte integers */ + CMP_DI, /* compare eight byte integers */ + CMP_SF, /* compare single precision floats */ + CMP_DF, /* compare double precision floats */ + CMP_MAX /* max comparison type */ +}; + +/* types of delay slot */ +enum delay_type { + DELAY_NONE, /* no delay slot */ + DELAY_LOAD, /* load from memory delay */ + DELAY_HILO, /* move from/to hi/lo registers */ + DELAY_FCMP /* delay after doing c.<xx>.{d,s} */ +}; + +/* Which processor to schedule for. Since there is no difference between + a R2000 and R3000 in terms of the scheduler, we collapse them into + just an R3000. The elements of the enumeration must match exactly + the cpu attribute in the mips.md machine description. */ + +enum processor_type { + PROCESSOR_DEFAULT, + PROCESSOR_R3000, + PROCESSOR_R3900, + PROCESSOR_R6000, + PROCESSOR_R4000, + PROCESSOR_R4100, + PROCESSOR_R4300, + PROCESSOR_R4600, + PROCESSOR_R4650, + PROCESSOR_R5000, + PROCESSOR_R8000 +}; + +/* Recast the cpu class to be the cpu attribute. */ +#define mips_cpu_attr ((enum attr_cpu)mips_cpu) + +/* Which ABI to use. These are constants because abi64.h must check their + value at preprocessing time. + + ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all + defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */ + +#define ABI_32 0 +#define ABI_N32 1 +#define ABI_64 2 +#define ABI_EABI 3 +#define ABI_O64 4 + +#ifndef MIPS_ABI_DEFAULT +/* We define this away so that there is no extra runtime cost if the target + doesn't support multiple ABIs. */ +#define mips_abi ABI_32 +#else +extern int mips_abi; +#endif + +/* Whether to emit abicalls code sequences or not. */ + +enum mips_abicalls_type { + MIPS_ABICALLS_NO, + MIPS_ABICALLS_YES +}; + +/* Recast the abicalls class to be the abicalls attribute. */ +#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls) + +/* Which type of block move to do (whether or not the last store is + split out so it can fill a branch delay slot). */ + +enum block_move_type { + BLOCK_MOVE_NORMAL, /* generate complete block move */ + BLOCK_MOVE_NOT_LAST, /* generate all but last store */ + BLOCK_MOVE_LAST /* generate just the last store */ +}; + +extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */ +extern char mips_print_operand_punct[]; /* print_operand punctuation chars */ +extern const char *current_function_file; /* filename current function is in */ +extern int num_source_filenames; /* current .file # */ +extern int inside_function; /* != 0 if inside of a function */ +extern int ignore_line_number; /* != 0 if we are to ignore next .loc */ +extern int file_in_function_warning; /* warning given about .file in func */ +extern int sdb_label_count; /* block start/end next label # */ +extern int sdb_begin_function_line; /* Starting Line of current function */ +extern int mips_section_threshold; /* # bytes of data/sdata cutoff */ +extern int g_switch_value; /* value of the -G xx switch */ +extern int g_switch_set; /* whether -G xx was passed. */ +extern int sym_lineno; /* sgi next label # for each stmt */ +extern int set_noreorder; /* # of nested .set noreorder's */ +extern int set_nomacro; /* # of nested .set nomacro's */ +extern int set_noat; /* # of nested .set noat's */ +extern int set_volatile; /* # of nested .set volatile's */ +extern int mips_branch_likely; /* emit 'l' after br (branch likely) */ +extern int mips_dbx_regno[]; /* Map register # to debug register # */ +extern struct rtx_def *branch_cmp[2]; /* operands for compare */ +extern enum cmp_type branch_type; /* what type of branch to use */ +extern enum processor_type mips_cpu; /* which cpu are we scheduling for */ +extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */ +extern int mips_isa; /* architectural level */ +extern int mips16; /* whether generating mips16 code */ +extern int mips16_hard_float; /* mips16 without -msoft-float */ +extern int mips_entry; /* generate entry/exit for mips16 */ +extern const char *mips_cpu_string; /* for -mcpu=<xxx> */ +extern const char *mips_isa_string; /* for -mips{1,2,3,4} */ +extern const char *mips_abi_string; /* for -mabi={32,n32,64} */ +extern const char *mips_entry_string; /* for -mentry */ +extern const char *mips_no_mips16_string;/* for -mno-mips16 */ +extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */ +extern int mips_split_addresses; /* perform high/lo_sum support */ +extern int dslots_load_total; /* total # load related delay slots */ +extern int dslots_load_filled; /* # filled load delay slots */ +extern int dslots_jump_total; /* total # jump related delay slots */ +extern int dslots_jump_filled; /* # filled jump delay slots */ +extern int dslots_number_nops; /* # of nops needed by previous insn */ +extern int num_refs[3]; /* # 1/2/3 word references */ +extern struct rtx_def *mips_load_reg; /* register to check for load delay */ +extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */ +extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */ +extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */ +extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */ +extern int mips_string_length; /* length of strings for mips16 */ +extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */ + +/* Functions within mips.c that we reference. Some of these return + type HOST_WIDE_INT, so define that here. */ + +#include "hwint.h" + +extern int arith32_operand (); +extern int arith_operand (); +extern int cmp_op (); +#ifdef HOST_WIDE_INT +extern HOST_WIDE_INT compute_frame_size (); +#endif +extern int const_float_1_operand (); +extern void expand_block_move (); +extern int equality_op (); +extern void final_prescan_insn (); +extern struct rtx_def * function_arg (); +extern void function_arg_advance (); +extern int function_arg_partial_nregs (); +extern int function_arg_pass_by_reference (); +extern void function_epilogue (); +extern void function_prologue (); +extern void gen_conditional_branch (); +extern void gen_conditional_move (); +extern struct rtx_def * gen_int_relational (); +extern void init_cumulative_args (); +extern int large_int (); +extern void machine_dependent_reorg (); +extern int mips_address_cost (); +extern void mips_asm_file_end (); +extern void mips_asm_file_start (); +extern int mips_can_use_return_insn (); +extern int mips_const_double_ok (); +extern void mips_count_memory_refs (); +#ifdef HOST_WIDE_INT +extern HOST_WIDE_INT mips_debugger_offset (); +#endif +extern void mips_declare_object (); +extern int mips_epilogue_delay_slots (); +extern void mips_expand_epilogue (); +extern void mips_expand_prologue (); +extern int mips_check_split (); +extern char *mips_fill_delay_slot (); +extern const char *mips_move_1word (); +extern const char *mips_move_2words (); +extern void mips_output_double (); +extern int mips_output_external (); +extern void mips_output_float (); +extern void mips_output_filename (); +extern void mips_output_lineno (); +extern const char *output_block_move (); +extern void override_options (); +extern int pc_or_label_operand (); +extern void print_operand_address (); +extern void print_operand (); +extern void print_options (); +extern int reg_or_0_operand (); +extern int true_reg_or_0_operand (); +extern int simple_epilogue_p (); +extern int simple_memory_operand (); +extern int double_memory_operand (); +extern int small_int (); +extern void trace (); +extern int uns_arith_operand (); +extern struct rtx_def * embedded_pic_offset (); +extern void mips_order_regs_for_local_alloc (); +extern struct rtx_def * mips16_gp_pseudo_reg (); +extern struct rtx_def * mips16_gp_offset (); +extern int mips16_gp_offset_p (); +extern int mips16_constant (); +extern int mips16_constant_after_function_p (); +extern int build_mips16_call_stub (); + +/* Recognition functions that return if a condition is true. */ +extern int address_operand (); +extern int call_insn_operand (); +extern int const_double_operand (); +extern int const_int_operand (); +extern int consttable_operand (); +extern int general_operand (); +extern int immediate_operand (); +extern int memory_address_p (); +extern int memory_operand (); +extern int nonimmediate_operand (); +extern int nonmemory_operand (); +extern int pic_address_needs_scratch (); +extern int register_operand (); +extern int scratch_operand (); +extern int move_operand (); +extern int movdi_operand (); +extern int se_register_operand (); +extern int se_reg_or_0_operand (); +extern int se_uns_arith_operand (); +extern int se_arith_operand (); +extern int se_nonmemory_operand (); +extern int se_nonimmediate_operand (); +extern int extend_operator (); +extern int highpart_shift_operator (); +extern int m16_uimm3_b (); +extern int m16_simm4_1 (); +extern int m16_nsimm4_1 (); +extern int m16_simm5_1 (); +extern int m16_nsimm5_1 (); +extern int m16_uimm5_4 (); +extern int m16_nuimm5_4 (); +extern int m16_simm8_1 (); +extern int m16_nsimm8_1 (); +extern int m16_uimm8_1 (); +extern int m16_nuimm8_1 (); +extern int m16_uimm8_m1_1 (); +extern int m16_uimm8_4 (); +extern int m16_nuimm8_4 (); +extern int m16_simm8_8 (); +extern int m16_nsimm8_8 (); +extern int m16_usym8_4 (); +extern int m16_usym5_4 (); + +/* Functions to change what output section we are using. */ +extern void data_section (); +extern void rdata_section (); +extern void readonly_data_section (); +extern void sdata_section (); +extern void text_section (); +extern void mips_select_rtx_section (); +extern void mips_select_section (); + +/* Stubs for half-pic support if not OSF/1 reference platform. */ + +#ifndef HALF_PIC_P +#define HALF_PIC_P() 0 +#define HALF_PIC_NUMBER_PTRS 0 +#define HALF_PIC_NUMBER_REFS 0 +#define HALF_PIC_ENCODE(DECL) +#define HALF_PIC_DECLARE(NAME) +#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") +#define HALF_PIC_ADDRESS_P(X) 0 +#define HALF_PIC_PTR(X) X +#define HALF_PIC_FINISH(STREAM) +#endif + + +/* Run-time compilation parameters selecting different hardware subsets. */ + +/* Macros used in the machine description to test the flags. */ + + /* Bits for real switches */ +#define MASK_INT64 0x00000001 /* ints are 64 bits */ +#define MASK_LONG64 0x00000002 /* longs are 64 bits */ +#define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */ +#define MASK_GPOPT 0x00000008 /* Optimize for global pointer */ +#define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */ +#define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */ +#define MASK_STATS 0x00000040 /* print statistics to stderr */ +#define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/ +#define MASK_SOFT_FLOAT 0x00000100 /* software floating point */ +#define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */ +#define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */ +#define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/ +#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */ +#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */ +#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */ +#define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */ +#define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */ +#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */ +#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */ +#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */ +#define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */ +#define MASK_MIPS16 0x01000000 /* Generate mips16 code */ +#define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */ +#define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */ + + /* Dummy switches used only in spec's*/ +#define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */ + + /* Debug switches, not documented */ +#define MASK_DEBUG 0 /* Eliminate version # in .s file */ +#define MASK_DEBUG_A 0x40000000 /* don't allow <label>($reg) addrs */ +#define MASK_DEBUG_B 0x20000000 /* GO_IF_LEGITIMATE_ADDRESS debug */ +#define MASK_DEBUG_C 0x10000000 /* don't expand seq, etc. */ +#define MASK_DEBUG_D 0 /* don't do define_split's */ +#define MASK_DEBUG_E 0 /* function_arg debug */ +#define MASK_DEBUG_F 0 +#define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */ +#define MASK_DEBUG_H 0 /* allow ints in FP registers */ +#define MASK_DEBUG_I 0 /* unused */ + + /* r4000 64 bit sizes */ +#define TARGET_INT64 (target_flags & MASK_INT64) +#define TARGET_LONG64 (target_flags & MASK_LONG64) +#define TARGET_FLOAT64 (target_flags & MASK_FLOAT64) +#define TARGET_64BIT (target_flags & MASK_64BIT) + + /* Mips vs. GNU linker */ +#define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR) + +/* generate mips 3900 insns */ +#define TARGET_MIPS3900 (target_flags & MASK_MIPS3900) + + /* Mips vs. GNU assembler */ +#define TARGET_GAS (target_flags & MASK_GAS) +#define TARGET_UNIX_ASM (!TARGET_GAS) +#define TARGET_MIPS_AS TARGET_UNIX_ASM + + /* Debug Mode */ +#define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG) +#define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A) +#define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B) +#define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C) +#define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D) +#define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E) +#define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F) +#define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G) +#define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H) +#define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I) + + /* Reg. Naming in .s ($21 vs. $a0) */ +#define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS) + + /* Optimize for Sdata/Sbss */ +#define TARGET_GP_OPT (target_flags & MASK_GPOPT) + + /* print program statistics */ +#define TARGET_STATS (target_flags & MASK_STATS) + + /* call memcpy instead of inline code */ +#define TARGET_MEMCPY (target_flags & MASK_MEMCPY) + + /* .abicalls, etc from Pyramid V.4 */ +#define TARGET_ABICALLS (target_flags & MASK_ABICALLS) + + /* OSF pic references to externs */ +#define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC) + + /* software floating point */ +#define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) +#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) + + /* always call through a register */ +#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS) + + /* generate embedded PIC code; + requires gas. */ +#define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC) + + /* for embedded systems, optimize for + reduced RAM space instead of for + fastest code. */ +#define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA) + + /* generate big endian code. */ +#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN) + +#define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT) +#define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT) + +#define TARGET_MAD (target_flags & MASK_MAD) + +#define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX) + +#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV) +#define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV) + +/* This is true if we must enable the assembly language file switching + code. */ + +#define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS) + +/* We must disable the function end stabs when doing the file switching trick, + because the Lscope stabs end up in the wrong place, making it impossible + to debug the resulting code. */ +#define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING + + /* Generate mips16 code */ +#define TARGET_MIPS16 (target_flags & MASK_MIPS16) + +/* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + +#define TARGET_SWITCHES \ +{ \ + {"int64", MASK_INT64 | MASK_LONG64, \ + "Use 64-bit int type"}, \ + {"long64", MASK_LONG64, \ + "Use 64-bit long type"}, \ + {"long32", -(MASK_LONG64 | MASK_INT64), \ + "Use 32-bit long type"}, \ + {"split-addresses", MASK_SPLIT_ADDR, \ + "Optimize lui/addiu address loads"}, \ + {"no-split-addresses", -MASK_SPLIT_ADDR, \ + "Don't optimize lui/addiu address loads"}, \ + {"mips-as", -MASK_GAS, \ + "Use MIPS as"}, \ + {"gas", MASK_GAS, \ + "Use GNU as"}, \ + {"rnames", MASK_NAME_REGS, \ + "Use symbolic register names"}, \ + {"no-rnames", -MASK_NAME_REGS, \ + "Don't use symbolic register names"}, \ + {"gpOPT", MASK_GPOPT, \ + "Use GP relative sdata/sbss sections"}, \ + {"gpopt", MASK_GPOPT, \ + "Use GP relative sdata/sbss sections"}, \ + {"no-gpOPT", -MASK_GPOPT, \ + "Don't use GP relative sdata/sbss sections"}, \ + {"no-gpopt", -MASK_GPOPT, \ + "Don't use GP relative sdata/sbss sections"}, \ + {"stats", MASK_STATS, \ + "Output compiler statistics"}, \ + {"no-stats", -MASK_STATS, \ + "Don't output compiler statistics"}, \ + {"memcpy", MASK_MEMCPY, \ + "Don't optimize block moves"}, \ + {"no-memcpy", -MASK_MEMCPY, \ + "Optimize block moves"}, \ + {"mips-tfile", MASK_MIPS_TFILE, \ + "Use mips-tfile asm postpass"}, \ + {"no-mips-tfile", -MASK_MIPS_TFILE, \ + "Don't use mips-tfile asm postpass"}, \ + {"soft-float", MASK_SOFT_FLOAT, \ + "Use software floating point"}, \ + {"hard-float", -MASK_SOFT_FLOAT, \ + "Use hardware floating point"}, \ + {"fp64", MASK_FLOAT64, \ + "Use 64-bit FP registers"}, \ + {"fp32", -MASK_FLOAT64, \ + "Use 32-bit FP registers"}, \ + {"gp64", MASK_64BIT, \ + "Use 64-bit general registers"}, \ + {"gp32", -MASK_64BIT, \ + "Use 32-bit general registers"}, \ + {"abicalls", MASK_ABICALLS, \ + "Use Irix PIC"}, \ + {"no-abicalls", -MASK_ABICALLS, \ + "Don't use Irix PIC"}, \ + {"half-pic", MASK_HALF_PIC, \ + "Use OSF PIC"}, \ + {"no-half-pic", -MASK_HALF_PIC, \ + "Don't use OSF PIC"}, \ + {"long-calls", MASK_LONG_CALLS, \ + "Use indirect calls"}, \ + {"no-long-calls", -MASK_LONG_CALLS, \ + "Don't use indirect calls"}, \ + {"embedded-pic", MASK_EMBEDDED_PIC, \ + "Use embedded PIC"}, \ + {"no-embedded-pic", -MASK_EMBEDDED_PIC, \ + "Don't use embedded PIC"}, \ + {"embedded-data", MASK_EMBEDDED_DATA, \ + "Use ROM instead of RAM"}, \ + {"no-embedded-data", -MASK_EMBEDDED_DATA, \ + "Don't use ROM instead of RAM"}, \ + {"eb", MASK_BIG_ENDIAN, \ + "Use big-endian byte order"}, \ + {"el", -MASK_BIG_ENDIAN, \ + "Use little-endian byte order"}, \ + {"single-float", MASK_SINGLE_FLOAT, \ + "Use single (32-bit) FP only"}, \ + {"double-float", -MASK_SINGLE_FLOAT, \ + "Don't use single (32-bit) FP only"}, \ + {"mad", MASK_MAD, \ + "Use multiply accumulate"}, \ + {"no-mad", -MASK_MAD, \ + "Don't use multiply accumulate"}, \ + {"fix4300", MASK_4300_MUL_FIX, \ + "Work around early 4300 hardware bug"}, \ + {"no-fix4300", -MASK_4300_MUL_FIX, \ + "Don't work around early 4300 hardware bug"}, \ + {"4650", MASK_MAD | MASK_SINGLE_FLOAT, \ + "Optimize for 4650"}, \ + {"3900", MASK_MIPS3900, \ + "Optimize for 3900"}, \ + {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \ + "Trap on integer divide by zero"}, \ + {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \ + "Don't trap on integer divide by zero"}, \ + {"check-range-division",MASK_CHECK_RANGE_DIV, \ + "Trap on integer divide overflow"}, \ + {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \ + "Don't trap on integer divide overflow"}, \ + {"debug", MASK_DEBUG, \ + NULL}, \ + {"debuga", MASK_DEBUG_A, \ + NULL}, \ + {"debugb", MASK_DEBUG_B, \ + NULL}, \ + {"debugc", MASK_DEBUG_C, \ + NULL}, \ + {"debugd", MASK_DEBUG_D, \ + NULL}, \ + {"debuge", MASK_DEBUG_E, \ + NULL}, \ + {"debugf", MASK_DEBUG_F, \ + NULL}, \ + {"debugg", MASK_DEBUG_G, \ + NULL}, \ + {"debugh", MASK_DEBUG_H, \ + NULL}, \ + {"debugi", MASK_DEBUG_I, \ + NULL}, \ + {"", (TARGET_DEFAULT \ + | TARGET_CPU_DEFAULT \ + | TARGET_ENDIAN_DEFAULT), \ + NULL}, \ +} + +/* Default target_flags if no switches are specified */ + +#ifndef TARGET_DEFAULT +#define TARGET_DEFAULT 0 +#endif + +#ifndef TARGET_CPU_DEFAULT +#define TARGET_CPU_DEFAULT 0 +#endif + +#ifndef TARGET_ENDIAN_DEFAULT +#ifndef DECSTATION +#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN +#else +#define TARGET_ENDIAN_DEFAULT 0 +#endif +#endif + +#ifndef MULTILIB_DEFAULTS +#if TARGET_ENDIAN_DEFAULT == 0 +#define MULTILIB_DEFAULTS { "EL", "mips1" } +#else +#define MULTILIB_DEFAULTS { "EB", "mips1" } +#endif +#endif + +/* We must pass -EL to the linker by default for little endian embedded + targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the + linker will default to using big-endian output files. The OUTPUT_FORMAT + line must be in the linker script, otherwise -EB/-EL will not work. */ + +#ifndef LINKER_ENDIAN_SPEC +#if TARGET_ENDIAN_DEFAULT == 0 +#define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}" +#else +#define LINKER_ENDIAN_SPEC "" +#endif +#endif + +/* This macro is similar to `TARGET_SWITCHES' but defines names of + command options that have values. Its definition is an + initializer with a subgrouping for each command option. + + Each subgrouping contains a string constant, that defines the + fixed part of the option name, and the address of a variable. + The variable, type `char *', is set to the variable part of the + given option if the fixed part matches. The actual option name + is made by appending `-m' to the specified name. + + Here is an example which defines `-mshort-data-NUMBER'. If the + given option is `-mshort-data-512', the variable `m88k_short_data' + will be set to the string `"512"'. + + extern char *m88k_short_data; + #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ + +#define TARGET_OPTIONS \ +{ \ + SUBTARGET_TARGET_OPTIONS \ + { "cpu=", &mips_cpu_string, \ + "Specify CPU for scheduling purposes"}, \ + { "ips", &mips_isa_string, \ + "Specify MIPS ISA"}, \ + { "entry", &mips_entry_string, \ + "Use mips16 entry/exit psuedo ops"}, \ + { "no-mips16", &mips_no_mips16_string, \ + "Don't use MIPS16 instructions"}, \ + { "explicit-type-size", &mips_explicit_type_size_string, \ + NULL}, \ +} + +/* This is meant to be redefined in the host dependent files. */ +#define SUBTARGET_TARGET_OPTIONS + +#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2))) + +/* Generate three-operand multiply instructions for both SImode and DImode. */ +#define GENERATE_MULT3 (TARGET_MIPS3900 \ + && !TARGET_MIPS16) + +/* Macros to decide whether certain features are available or not, + depending on the instruction set architecture level. */ + +#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY +#define HAVE_SQRT_P() (mips_isa >= 2) + +/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or + -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit + -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in + target_flags, and -mgp64 sets MASK_64BIT. + + Setting MASK_64BIT in target_flags will cause gcc to assume that + registers are 64 bits wide. int, long and void * will be 32 bit; + this may be changed with -mint64 or -mlong64. + + The gen* programs link code that refers to MASK_64BIT. They don't + actually use the information in target_flags; they just refer to + it. */ + +/* Switch Recognition by gcc.c. Add -G xx support */ + +#ifdef SWITCH_TAKES_ARG +#undef SWITCH_TAKES_ARG +#endif + +#define SWITCH_TAKES_ARG(CHAR) \ + (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') + +/* Sometimes certain combinations of command options do not make sense + on a particular target machine. You can define a macro + `OVERRIDE_OPTIONS' to take account of this. This macro, if + defined, is executed once just after all the command options have + been parsed. + + On the MIPS, it is used to handle -G. We also use it to set up all + of the tables referenced in the other macros. */ + +#define OVERRIDE_OPTIONS override_options () + +/* Zero or more C statements that may conditionally modify two + variables `fixed_regs' and `call_used_regs' (both of type `char + []') after they have been initialized from the two preceding + macros. + + This is necessary in case the fixed or call-clobbered registers + depend on target flags. + + You need not define this macro if it has no work to do. + + If the usage of an entire class of registers depends on the target + flags, you may indicate this to GCC by using this macro to modify + `fixed_regs' and `call_used_regs' to 1 for each of the registers in + the classes which should not be used by GCC. Also define the macro + `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a + letter for a class that shouldn't be used. + + (However, if this class is not included in `GENERAL_REGS' and all + of the insn patterns whose constraints permit this class are + controlled by target switches, then GCC will automatically avoid + using these registers when the target switches are opposed to + them.) */ + +#define CONDITIONAL_REGISTER_USAGE \ +do \ + { \ + if (!TARGET_HARD_FLOAT) \ + { \ + int regno; \ + \ + for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \ + fixed_regs[regno] = call_used_regs[regno] = 1; \ + for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \ + fixed_regs[regno] = call_used_regs[regno] = 1; \ + } \ + else if (mips_isa < 4) \ + { \ + int regno; \ + \ + /* We only have a single condition code register. We \ + implement this by hiding all the condition code registers, \ + and generating RTL that refers directly to ST_REG_FIRST. */ \ + for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \ + fixed_regs[regno] = call_used_regs[regno] = 1; \ + } \ + /* In mips16 mode, we permit the $t temporary registers to be used \ + for reload. We prohibit the unused $s registers, since they \ + are caller saved, and saving them via a mips16 register would \ + probably waste more time than just reloading the value. */ \ + if (TARGET_MIPS16) \ + { \ + fixed_regs[18] = call_used_regs[18] = 1; \ + fixed_regs[19] = call_used_regs[19] = 1; \ + fixed_regs[20] = call_used_regs[20] = 1; \ + fixed_regs[21] = call_used_regs[21] = 1; \ + fixed_regs[22] = call_used_regs[22] = 1; \ + fixed_regs[23] = call_used_regs[23] = 1; \ + fixed_regs[26] = call_used_regs[26] = 1; \ + fixed_regs[27] = call_used_regs[27] = 1; \ + fixed_regs[30] = call_used_regs[30] = 1; \ + } \ + SUBTARGET_CONDITIONAL_REGISTER_USAGE \ + } \ +while (0) + +/* This is meant to be redefined in the host dependent files. */ +#define SUBTARGET_CONDITIONAL_REGISTER_USAGE + +/* Show we can debug even without a frame pointer. */ +#define CAN_DEBUG_WITHOUT_FP + +/* Complain about missing specs and predefines that should be defined in each + of the target tm files to override the defaults. This is mostly a place- + holder until I can get each of the files updated [mm]. */ + +#if defined(OSF_OS) \ + || defined(DECSTATION) \ + || defined(SGI_TARGET) \ + || defined(MIPS_NEWS) \ + || defined(MIPS_SYSV) \ + || defined(MIPS_SVR4) \ + || defined(MIPS_BSD43) + +#ifndef CPP_PREDEFINES + #error "Define CPP_PREDEFINES in the appropriate tm.h file" +#endif + +#ifndef LIB_SPEC + #error "Define LIB_SPEC in the appropriate tm.h file" +#endif + +#ifndef STARTFILE_SPEC + #error "Define STARTFILE_SPEC in the appropriate tm.h file" +#endif + +#ifndef MACHINE_TYPE + #error "Define MACHINE_TYPE in the appropriate tm.h file" +#endif +#endif + +/* Tell collect what flags to pass to nm. */ +#ifndef NM_FLAGS +#define NM_FLAGS "-Bn" +#endif + + +/* Names to predefine in the preprocessor for this target machine. */ + +#ifndef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \ +-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)" +#endif + +/* Assembler specs. */ + +/* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather + than gas. */ + +#define MIPS_AS_ASM_SPEC "\ +%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \ +%{pipe: %e-pipe is not supported.} \ +%{K} %(subtarget_mips_as_asm_spec)" + +/* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler + rather than gas. It may be overridden by subtargets. */ + +#ifndef SUBTARGET_MIPS_AS_ASM_SPEC +#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}" +#endif + +/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS + assembler. */ + +#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}" + +/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or + GAS_ASM_SPEC as the default, depending upon the value of + TARGET_DEFAULT. */ + +#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0 +/* GAS */ + +#define TARGET_ASM_SPEC "\ +%{mmips-as: %(mips_as_asm_spec)} \ +%{!mmips-as: %(gas_asm_spec)}" + +#else /* not GAS */ + +#define TARGET_ASM_SPEC "\ +%{!mgas: %(mips_as_asm_spec)} \ +%{mgas: %(gas_asm_spec)}" + +#endif /* not GAS */ + +/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options + to the assembler. It may be overridden by subtargets. */ +#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC +#define SUBTARGET_ASM_OPTIMIZING_SPEC "\ +%{noasmopt:-O0} \ +%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}" +#endif + +/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to + the assembler. It may be overridden by subtargets. */ +#ifndef SUBTARGET_ASM_DEBUGGING_SPEC +#define SUBTARGET_ASM_DEBUGGING_SPEC "\ +%{g} %{g0} %{g1} %{g2} %{g3} \ +%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ +%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ +%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ +%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}" +#endif + +/* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be + overridden by subtargets. */ + +#ifndef SUBTARGET_ASM_SPEC +#define SUBTARGET_ASM_SPEC "" +#endif + +/* ASM_SPEC is the set of arguments to pass to the assembler. */ + +#define ASM_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \ +%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ +%(subtarget_asm_optimizing_spec) \ +%(subtarget_asm_debugging_spec) \ +%{membedded-pic} \ +%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \ +%(target_asm_spec) \ +%(subtarget_asm_spec)" + +/* Specify to run a post-processor, mips-tfile after the assembler + has run to stuff the mips debug information into the object file. + This is needed because the $#!%^ MIPS assembler provides no way + of specifying such information in the assembly file. If we are + cross compiling, disable mips-tfile unless the user specifies + -mmips-tfile. */ + +#ifndef ASM_FINAL_SPEC +#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0 +/* GAS */ +#define ASM_FINAL_SPEC "\ +%{mmips-as: %{!mno-mips-tfile: \ + \n mips-tfile %{v*: -v} \ + %{K: -I %b.o~} \ + %{!K: %{save-temps: -I %b.o~}} \ + %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \ + %{.s:%i} %{!.s:%g.s}}}" + +#else +/* not GAS */ +#define ASM_FINAL_SPEC "\ +%{!mgas: %{!mno-mips-tfile: \ + \n mips-tfile %{v*: -v} \ + %{K: -I %b.o~} \ + %{!K: %{save-temps: -I %b.o~}} \ + %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \ + %{.s:%i} %{!.s:%g.s}}}" + +#endif +#endif /* ASM_FINAL_SPEC */ + +/* Redefinition of libraries used. Mips doesn't support normal + UNIX style profiling via calling _mcount. It does offer + profiling that samples the PC, so do what we can... */ + +#ifndef LIB_SPEC +#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc" +#endif + +/* Extra switches sometimes passed to the linker. */ +/* ??? The bestGnum will never be passed to the linker, because the gcc driver + will interpret it as a -b option. */ + +#ifndef LINK_SPEC +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \ +%{bestGnum} %{shared} %{non_shared} \ +%(linker_endian_spec)" +#endif /* LINK_SPEC defined */ + +/* Specs for the compiler proper */ + +/* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be + overridden by subtargets. */ +#ifndef SUBTARGET_CC1_SPEC +#define SUBTARGET_CC1_SPEC "" +#endif + +/* CC1_SPEC is the set of arguments to pass to the compiler proper. */ + +#ifndef CC1_SPEC +#define CC1_SPEC "\ +%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ +%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\ +%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \ +%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \ +%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \ +%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \ +%{mint64|mlong64|mlong32:-mexplicit-type-size }\ +%{m4650:-mcpu=r4650} \ +%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \ +%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ +%{pic-none: -mno-half-pic} \ +%{pic-lib: -mhalf-pic} \ +%{pic-extern: -mhalf-pic} \ +%{pic-calls: -mhalf-pic} \ +%{save-temps: } \ +%(subtarget_cc1_spec) " +#endif + +/* Preprocessor specs. */ + +/* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may + be overridden by subtargets. */ + +#ifndef SUBTARGET_CPP_SIZE_SPEC +#define SUBTARGET_CPP_SIZE_SPEC "\ +%{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \ +%{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}" +#endif + +/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be + overridden by subtargets. */ +#ifndef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "" +#endif + +/* If we're using 64bit longs, then we have to define __LONG_MAX__ + correctly. Similarly for 64bit ints and __INT_MAX__. */ +#ifndef LONG_MAX_SPEC +#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64) +#define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}" +#else +#define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}" +#endif +#endif + +/* CPP_SPEC is the set of arguments to pass to the preprocessor. */ + +#ifndef CPP_SPEC +#define CPP_SPEC "\ +%{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ +%{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ +%{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \ +%{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \ +%{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ +%{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ +%{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \ +%(subtarget_cpp_size_spec) \ +%{mips3:-U__mips -D__mips=3 -D__mips64} \ +%{mips4:-U__mips -D__mips=4 -D__mips64} \ +%{mgp32:-U__mips64} %{mgp64:-D__mips64} \ +%{msingle-float:%{!msoft-float:-D__mips_single_float}} \ +%{m4650:%{!msoft-float:-D__mips_single_float}} \ +%{msoft-float:-D__mips_soft_float} \ +%{mabi=eabi:-D__mips_eabi} \ +%{mips16:%{!mno-mips16:-D__mips16}} \ +%{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \ +%{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \ +%(long_max_spec) \ +%(subtarget_cpp_spec) " +#endif + +/* This macro defines names of additional specifications to put in the specs + that can be used in various specifications like CC1_SPEC. Its definition + is an initializer with a subgrouping for each command option. + + Each subgrouping contains a string constant, that defines the + specification name, and a string constant that used by the GNU CC driver + program. + + Do not define this macro if it does not need to do anything. */ + +#define EXTRA_SPECS \ + { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ + { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ + { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \ + { "long_max_spec", LONG_MAX_SPEC }, \ + { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \ + { "gas_asm_spec", GAS_ASM_SPEC }, \ + { "target_asm_spec", TARGET_ASM_SPEC }, \ + { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \ + { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \ + { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ + { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ + { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \ + SUBTARGET_EXTRA_SPECS + +#ifndef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS +#endif + +/* If defined, this macro is an additional prefix to try after + `STANDARD_EXEC_PREFIX'. */ + +#ifndef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/" +#endif + +#ifndef MD_STARTFILE_PREFIX +#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/" +#endif + + +/* Print subsidiary information on the compiler version in use. */ + +#define MIPS_VERSION "[AL 1.1, MM 40]" + +#ifndef MACHINE_TYPE +#define MACHINE_TYPE "BSD Mips" +#endif + +#ifndef TARGET_VERSION_INTERNAL +#define TARGET_VERSION_INTERNAL(STREAM) \ + fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE) +#endif + +#ifndef TARGET_VERSION +#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr) +#endif + + +#define SDB_DEBUGGING_INFO /* generate info for mips-tfile */ +#define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */ +#define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */ + +#ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ +#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG +#endif + +/* By default, turn on GDB extensions. */ +#define DEFAULT_GDB_EXTENSIONS 1 + +/* If we are passing smuggling stabs through the MIPS ECOFF object + format, put a comment in front of the .stab<x> operation so + that the MIPS assembler does not choke. The mips-tfile program + will correctly put the stab into the object file. */ + +#define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs") +#define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn") +#define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd") + +/* Local compiler-generated symbols must have a prefix that the assembler + understands. By default, this is $, although some targets (e.g., + NetBSD-ELF) need to override this. */ + +#ifndef LOCAL_LABEL_PREFIX +#define LOCAL_LABEL_PREFIX "$" +#endif + +/* By default on the mips, external symbols do not have an underscore + prepended, but some targets (e.g., NetBSD) require this. */ + +#ifndef USER_LABEL_PREFIX +#define USER_LABEL_PREFIX "" +#endif + +/* Forward references to tags are allowed. */ +#define SDB_ALLOW_FORWARD_REFERENCES + +/* Unknown tags are also allowed. */ +#define SDB_ALLOW_UNKNOWN_REFERENCES + +/* On Sun 4, this limit is 2048. We use 1500 to be safe, + since the length can run past this up to a continuation point. */ +#define DBX_CONTIN_LENGTH 1500 + +/* How to renumber registers for dbx and gdb. */ +#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ] + +/* The mapping from gcc register number to DWARF 2 CFA column number. + This mapping does not allow for tracking register 0, since SGI's broken + dwarf reader thinks column 0 is used for the frame address, but since + register 0 is fixed this is not a problem. */ +#define DWARF_FRAME_REGNUM(REG) \ + (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG) + +/* The DWARF 2 CFA column which tracks the return address. */ +#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1) + +/* Before the prologue, RA lives in r31. */ +#define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31) + +/* Overrides for the COFF debug format. */ +#define PUT_SDB_SCL(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \ +} while (0) + +#define PUT_SDB_INT_VAL(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \ +} while (0) + +#define PUT_SDB_VAL(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fputs ("\t.val\t", asm_out_text_file); \ + output_addr_const (asm_out_text_file, (a)); \ + fputc (';', asm_out_text_file); \ +} while (0) + +#define PUT_SDB_DEF(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t%s.def\t", \ + (TARGET_GAS) ? "" : "#"); \ + ASM_OUTPUT_LABELREF (asm_out_text_file, a); \ + fputc (';', asm_out_text_file); \ +} while (0) + +#define PUT_SDB_PLAIN_DEF(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t%s.def\t.%s;", \ + (TARGET_GAS) ? "" : "#", (a)); \ +} while (0) + +#define PUT_SDB_ENDEF \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.endef\n"); \ +} while (0) + +#define PUT_SDB_TYPE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \ +} while (0) + +#define PUT_SDB_SIZE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \ +} while (0) + +#define PUT_SDB_DIM(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \ +} while (0) + +#ifndef PUT_SDB_START_DIM +#define PUT_SDB_START_DIM \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.dim\t"); \ +} while (0) +#endif + +#ifndef PUT_SDB_NEXT_DIM +#define PUT_SDB_NEXT_DIM(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "%d,", a); \ +} while (0) +#endif + +#ifndef PUT_SDB_LAST_DIM +#define PUT_SDB_LAST_DIM(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "%d;", a); \ +} while (0) +#endif + +#define PUT_SDB_TAG(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.tag\t"); \ + ASM_OUTPUT_LABELREF (asm_out_text_file, a); \ + fputc (';', asm_out_text_file); \ +} while (0) + +/* For block start and end, we create labels, so that + later we can figure out where the correct offset is. + The normal .ent/.end serve well enough for functions, + so those are just commented out. */ + +#define PUT_SDB_BLOCK_START(LINE) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, \ + "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \ + LOCAL_LABEL_PREFIX, \ + sdb_label_count, \ + (TARGET_GAS) ? "" : "#", \ + LOCAL_LABEL_PREFIX, \ + sdb_label_count, \ + (LINE)); \ + sdb_label_count++; \ +} while (0) + +#define PUT_SDB_BLOCK_END(LINE) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, \ + "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \ + LOCAL_LABEL_PREFIX, \ + sdb_label_count, \ + (TARGET_GAS) ? "" : "#", \ + LOCAL_LABEL_PREFIX, \ + sdb_label_count, \ + (LINE)); \ + sdb_label_count++; \ +} while (0) + +#define PUT_SDB_FUNCTION_START(LINE) + +#define PUT_SDB_FUNCTION_END(LINE) \ +do { \ + extern FILE *asm_out_text_file; \ + ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \ +} while (0) + +#define PUT_SDB_EPILOGUE_END(NAME) + +#define PUT_SDB_SRC_FILE(FILENAME) \ +do { \ + extern FILE *asm_out_text_file; \ + output_file_directive (asm_out_text_file, (FILENAME)); \ +} while (0) + +#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \ + sprintf ((BUFFER), ".%dfake", (NUMBER)); + +/* Correct the offset of automatic variables and arguments. Note that + the MIPS debug format wants all automatic variables and arguments + to be in terms of the virtual frame pointer (stack pointer before + any adjustment in the function), while the MIPS 3.0 linker wants + the frame pointer to be the stack pointer after the initial + adjustment. */ + +#define DEBUGGER_AUTO_OFFSET(X) \ + mips_debugger_offset (X, (HOST_WIDE_INT) 0) +#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ + mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) + +/* Tell collect that the object format is ECOFF */ +#ifndef OBJECT_FORMAT_ROSE +#define OBJECT_FORMAT_COFF /* Object file looks like COFF */ +#define EXTENDED_COFF /* ECOFF, not normal coff */ +#endif + +#if 0 /* These definitions normally have no effect because + MIPS systems define USE_COLLECT2, so + assemble_constructor does nothing anyway. */ + +/* Don't use the default definitions, because we don't have gld. + Also, we don't want stabs when generating ECOFF output. + Instead we depend on collect to handle these. */ + +#define ASM_OUTPUT_CONSTRUCTOR(file, name) +#define ASM_OUTPUT_DESTRUCTOR(file, name) + +#endif /* 0 */ + +/* Target machine storage layout */ + +/* Define in order to support both big and little endian float formats + in the same gcc binary. */ +#define REAL_ARITHMETIC + +/* Define this if most significant bit is lowest numbered + in instructions that operate on numbered bit-fields. +*/ +#define BITS_BIG_ENDIAN 0 + +/* Define this if most significant byte of a word is the lowest numbered. */ +#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) + +/* Define this if most significant word of a multiword number is the lowest. */ +#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) + +/* Define this to set the endianness to use in libgcc2.c, which can + not depend on target_flags. */ +#if !defined(MIPSEL) && !defined(__MIPSEL__) +#define LIBGCC2_WORDS_BIG_ENDIAN 1 +#else +#define LIBGCC2_WORDS_BIG_ENDIAN 0 +#endif + +/* Number of bits in an addressable storage unit */ +#define BITS_PER_UNIT 8 + +/* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 68000, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ +#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32) +#define MAX_BITS_PER_WORD 64 + +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) +#define MIN_UNITS_PER_WORD 4 + +/* For MIPS, width of a floating point register. */ +#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) + +/* A C expression for the size in bits of the type `int' on the + target machine. If you don't define this, the default is one + word. */ +#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32) +#define MAX_INT_TYPE_SIZE 64 + +/* Tell the preprocessor the maximum size of wchar_t. */ +#ifndef MAX_WCHAR_TYPE_SIZE +#ifndef WCHAR_TYPE_SIZE +#define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE +#endif +#endif + +/* A C expression for the size in bits of the type `short' on the + target machine. If you don't define this, the default is half a + word. (If this would be less than one storage unit, it is + rounded up to one unit.) */ +#define SHORT_TYPE_SIZE 16 + +/* A C expression for the size in bits of the type `long' on the + target machine. If you don't define this, the default is one + word. */ +#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) +#define MAX_LONG_TYPE_SIZE 64 + +/* A C expression for the size in bits of the type `long long' on the + target machine. If you don't define this, the default is two + words. */ +#define LONG_LONG_TYPE_SIZE 64 + +/* A C expression for the size in bits of the type `char' on the + target machine. If you don't define this, the default is one + quarter of a word. (If this would be less than one storage unit, + it is rounded up to one unit.) */ +#define CHAR_TYPE_SIZE BITS_PER_UNIT + +/* A C expression for the size in bits of the type `float' on the + target machine. If you don't define this, the default is one + word. */ +#define FLOAT_TYPE_SIZE 32 + +/* A C expression for the size in bits of the type `double' on the + target machine. If you don't define this, the default is two + words. */ +#define DOUBLE_TYPE_SIZE 64 + +/* A C expression for the size in bits of the type `long double' on + the target machine. If you don't define this, the default is two + words. */ +#define LONG_DOUBLE_TYPE_SIZE 64 + +/* Width in bits of a pointer. + See also the macro `Pmode' defined below. */ +#ifndef POINTER_SIZE +#define POINTER_SIZE (Pmode == DImode ? 64 : 32) +#endif + +/* Allocation boundary (in *bits*) for storing pointers in memory. */ +#define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32) + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) + +/* Allocation boundary (in *bits*) for the code of a function. */ +#define FUNCTION_BOUNDARY 32 + +/* Alignment of field after `int : 0' in a structure. */ +#define EMPTY_FIELD_BOUNDARY 32 + +/* Every structure's size must be a multiple of this. */ +/* 8 is observed right on a DECstation and on riscos 4.02. */ +#define STRUCTURE_SIZE_BOUNDARY 8 + +/* There is no point aligning anything to a rounder boundary than this. */ +#define BIGGEST_ALIGNMENT 64 + +/* Set this nonzero if move instructions will actually fail to work + when given unaligned data. */ +#define STRICT_ALIGNMENT 1 + +/* Define this if you wish to imitate the way many other C compilers + handle alignment of bitfields and the structures that contain + them. + + The behavior is that the type written for a bitfield (`int', + `short', or other integer type) imposes an alignment for the + entire structure, as if the structure really did contain an + ordinary field of that type. In addition, the bitfield is placed + within the structure so that it would fit within such a field, + not crossing a boundary for it. + + Thus, on most machines, a bitfield whose type is written as `int' + would not cross a four-byte boundary, and would force four-byte + alignment for the whole structure. (The alignment used may not + be four bytes; it is controlled by the other alignment + parameters.) + + If the macro is defined, its definition should be a C expression; + a nonzero value for the expression enables this behavior. */ + +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* If defined, a C expression to compute the alignment given to a + constant that is being placed in memory. CONSTANT is the constant + and ALIGN is the alignment that the object would ordinarily have. + The value of this macro is used instead of that alignment to align + the object. + + If this macro is not defined, then ALIGN is used. + + The typical use of this macro is to increase alignment for string + constants to be word aligned so that `strcpy' calls that copy + constants can be done inline. */ + +#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ + ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ + && (ALIGN) < BITS_PER_WORD \ + ? BITS_PER_WORD \ + : (ALIGN)) + +/* If defined, a C expression to compute the alignment for a static + variable. TYPE is the data type, and ALIGN is the alignment that + the object would ordinarily have. The value of this macro is used + instead of that alignment to align the object. + + If this macro is not defined, then ALIGN is used. + + One use of this macro is to increase alignment of medium-size + data to make it all fit in fewer cache lines. Another is to + cause character arrays to be word-aligned so that `strcpy' calls + that copy constants to character arrays can be done inline. */ + +#undef DATA_ALIGNMENT +#define DATA_ALIGNMENT(TYPE, ALIGN) \ + ((((ALIGN) < BITS_PER_WORD) \ + && (TREE_CODE (TYPE) == ARRAY_TYPE \ + || TREE_CODE (TYPE) == UNION_TYPE \ + || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) + +/* Define this macro if an argument declared as `char' or `short' in a + prototype should actually be passed as an `int'. In addition to + avoiding errors in certain cases of mismatch, it also makes for + better code on certain machines. */ + +#define PROMOTE_PROTOTYPES + +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. + + When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode + moves. All other referces are zero extended. */ +#define LOAD_EXTEND_OP(MODE) \ + (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ + ? SIGN_EXTEND : ZERO_EXTEND) + +/* Define this macro if it is advisable to hold scalars in registers + in a wider mode than that declared by the program. In such cases, + the value is constrained to be within the bounds of the declared + type, but kept valid in the wider mode. The signedness of the + extension may differ from that of the type. + + We promote any value smaller than SImode up to SImode. We don't + want to promote to DImode when in 64 bit mode, because that would + prevent us from using the faster SImode multiply and divide + instructions. */ + +#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ + && GET_MODE_SIZE (MODE) < 4) \ + (MODE) = SImode; + +/* Define this if function arguments should also be promoted using the above + procedure. */ + +#define PROMOTE_FUNCTION_ARGS + +/* Likewise, if the function return value is promoted. */ + +#define PROMOTE_FUNCTION_RETURN + +/* Standard register usage. */ + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. + + On the Mips, we have 32 integer registers, 32 floating point + registers, 8 condition code registers, and the special registers + hi, lo, hilo, and rap. The 8 condition code registers are only + used if mips_isa >= 4. The hilo register is only used in 64 bit + mode. It represents a 64 bit value stored as two 32 bit values in + the hi and lo registers; this is the result of the mult + instruction. rap is a pointer to the stack where the return + address reg ($31) was stored. This is needed for C++ exception + handling. */ + +#define FIRST_PSEUDO_REGISTER 76 + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + + On the MIPS, see conventions, page D-2 */ + +#define FIXED_REGISTERS \ +{ \ + 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \ +} + + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ + +#define CALL_USED_REGISTERS \ +{ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ +} + + +/* Internal macros to classify a register number as to whether it's a + general purpose register, a floating point register, a + multiply/divide register, or a status register. */ + +#define GP_REG_FIRST 0 +#define GP_REG_LAST 31 +#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) +#define GP_DBX_FIRST 0 + +#define FP_REG_FIRST 32 +#define FP_REG_LAST 63 +#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) +#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) + +#define MD_REG_FIRST 64 +#define MD_REG_LAST 66 +#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) + +#define ST_REG_FIRST 67 +#define ST_REG_LAST 74 +#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) + +#define RAP_REG_NUM 75 + +#define AT_REGNUM (GP_REG_FIRST + 1) +#define HI_REGNUM (MD_REG_FIRST + 0) +#define LO_REGNUM (MD_REG_FIRST + 1) +#define HILO_REGNUM (MD_REG_FIRST + 2) + +/* FPSW_REGNUM is the single condition code used if mips_isa < 4. If + mips_isa >= 4, it should not be used, and an arbitrary ST_REG + should be used instead. */ +#define FPSW_REGNUM ST_REG_FIRST + +#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) +#define M16_REG_P(REGNO) \ + (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) +#define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM) +#define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM) +#define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM) + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + + On the MIPS, all general registers are one word long. Except on + the R4000 with the FR bit set, the floating point uses register + pairs, with the second register not being allocable. */ + +#define HARD_REGNO_NREGS(REGNO, MODE) \ + (! FP_REG_P (REGNO) \ + ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG)) + +/* Value is 1 if hard register REGNO can hold a value of machine-mode + MODE. In 32 bit mode, require that DImode and DFmode be in even + registers. For DImode, this makes some of the insns easier to + write, since you don't have to worry about a DImode value in + registers 3 & 4, producing a result in 4 & 5. + + To make the code simpler HARD_REGNO_MODE_OK now just references an + array built in override_options. Because machmodes.h is not yet + included before this file is processed, the MODE bound can't be + expressed here. */ + +extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; + +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ +#define MODES_TIEABLE_P(MODE1, MODE2) \ + ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ + GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ + == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ + GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) + +/* MIPS pc is not overloaded on a register. */ +/* #define PC_REGNUM xx */ + +/* Register to use for pushing function arguments. */ +#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) + +/* Offset from the stack pointer to the first available location. Use + the default value zero. */ +/* #define STACK_POINTER_OFFSET 0 */ + +/* Base register for access to local variables of the function. We + pretend that the frame pointer is $1, and then eliminate it to + HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is + a fixed register, and will not be used for anything else. */ +#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1) + +/* $30 is not available on the mips16, so we use $17 as the frame + pointer. */ +#define HARD_FRAME_POINTER_REGNUM \ + (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) + +/* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. */ +#define FRAME_POINTER_REQUIRED (current_function_calls_alloca) + +/* Base register for access to arguments of the function. */ +#define ARG_POINTER_REGNUM GP_REG_FIRST + +/* Fake register that holds the address on the stack of the + current function's return address. */ +#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM + +/* Register in which static-chain is passed to a function. */ +#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) + +/* If the structure value address is passed in a register, then + `STRUCT_VALUE_REGNUM' should be the number of that register. */ +/* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */ + +/* If the structure value address is not passed in a register, define + `STRUCT_VALUE' as an expression returning an RTX for the place + where the address is passed. If it returns 0, the address is + passed as an "invisible" first argument. */ +#define STRUCT_VALUE 0 + +/* Mips registers used in prologue/epilogue code when the stack frame + is larger than 32K bytes. These registers must come from the + scratch register set, and not used for passing and returning + arguments and any other information used in the calling sequence + (such as pic). Must start at 12, since t0/t3 are parameter passing + registers in the 64 bit ABI. */ + +#define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12) +#define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13) + +/* Define this macro if it is as good or better to call a constant + function address than to call an address kept in a register. */ +#define NO_FUNCTION_CSE 1 + +/* Define this macro if it is as good or better for a function to + call itself with an explicit address than to call an address + kept in a register. */ +#define NO_RECURSIVE_FUNCTION_CSE 1 + +/* The register number of the register used to address a table of + static data addresses in memory. In some cases this register is + defined by a processor's "application binary interface" (ABI). + When this macro is defined, RTL is generated for this register + once, as with the stack pointer and frame pointer registers. If + this macro is not defined, it is up to the machine-dependent + files to allocate such a register (if necessary). */ +#define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28) + +#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25) + +/* Initialize embedded_pic_fnaddr_rtx before RTL generation for + each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC + isn't always called for static inline functions. */ +#define INIT_EXPANDERS \ +do { \ + embedded_pic_fnaddr_rtx = NULL; \ + mips16_gp_pseudo_rtx = NULL; \ +} while (0) + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. */ + +enum reg_class +{ + NO_REGS, /* no registers in set */ + M16_NA_REGS, /* mips16 regs not used to pass args */ + M16_REGS, /* mips16 directly accessible registers */ + T_REG, /* mips16 T register ($24) */ + M16_T_REGS, /* mips16 registers plus T register */ + GR_REGS, /* integer registers */ + FP_REGS, /* floating point registers */ + HI_REG, /* hi register */ + LO_REG, /* lo register */ + HILO_REG, /* hilo register pair for 64 bit mode mult */ + MD_REGS, /* multiply/divide registers (hi/lo) */ + HI_AND_GR_REGS, /* union classes */ + LO_AND_GR_REGS, + HILO_AND_GR_REGS, + ST_REGS, /* status registers (fp status) */ + ALL_REGS, /* all registers */ + LIM_REG_CLASSES /* max value + 1 */ +}; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +#define GENERAL_REGS GR_REGS + +/* An initializer containing the names of the register classes as C + string constants. These names are used in writing some of the + debugging dumps. */ + +#define REG_CLASS_NAMES \ +{ \ + "NO_REGS", \ + "M16_NA_REGS", \ + "M16_REGS", \ + "T_REG", \ + "M16_T_REGS", \ + "GR_REGS", \ + "FP_REGS", \ + "HI_REG", \ + "LO_REG", \ + "HILO_REG", \ + "MD_REGS", \ + "HI_AND_GR_REGS", \ + "LO_AND_GR_REGS", \ + "HILO_AND_GR_REGS", \ + "ST_REGS", \ + "ALL_REGS" \ +} + +/* An initializer containing the contents of the register classes, + as integers which are bit masks. The Nth integer specifies the + contents of class N. The way the integer MASK is interpreted is + that register R is in the class if `MASK & (1 << R)' is 1. + + When the machine has more than 32 registers, an integer does not + suffice. Then the integers are replaced by sub-initializers, + braced groupings containing several integers. Each + sub-initializer must be suitable as an initializer for the type + `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ + +#define REG_CLASS_CONTENTS \ +{ \ + { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \ + { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\ + { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \ + { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \ + { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \ + { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \ + { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \ + { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \ + { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \ + { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \ + { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \ + { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \ + { 0xffffffff, 0x00000000, 0x00000002 }, \ + { 0xffffffff, 0x00000000, 0x00000004 }, \ + { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \ + { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \ +} + + +/* A C expression whose value is a register class containing hard + register REGNO. In general there is more that one such class; + choose a class which is "minimal", meaning that no smaller class + also contains the register. */ + +extern enum reg_class mips_regno_to_class[]; + +#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] + +/* A macro whose definition is the name of the class to which a + valid base register must belong. A base register is one used in + an address which is the register value plus a displacement. */ + +#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS) + +/* A macro whose definition is the name of the class to which a + valid index register must belong. An index register is one used + in an address where its value is either multiplied by a scale + factor or added to another register (as well as added to a + displacement). */ + +#define INDEX_REG_CLASS NO_REGS + +/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows + registers explicitly used in the rtl to be used as spill registers + but prevents the compiler from extending the lifetime of these + registers. */ + +#define SMALL_REGISTER_CLASSES (TARGET_MIPS16) + +/* This macro is used later on in the file. */ +#define GR_REG_CLASS_P(CLASS) \ + ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \ + || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS) + +/* REG_ALLOC_ORDER is to order in which to allocate registers. This + is the default value (allocate the registers in numeric order). We + define it just so that we can override it for the mips16 target in + ORDER_REGS_FOR_LOCAL_ALLOC. */ + +#define REG_ALLOC_ORDER \ +{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \ +} + +/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order + to be rearranged based on a particular function. On the mips16, we + want to allocate $24 (T_REG) before other registers for + instructions for which it is possible. */ + +#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () + +/* REGISTER AND CONSTANT CLASSES */ + +/* Get reg_class from a letter such as appears in the machine + description. + + DEFINED REGISTER CLASSES: + + 'd' General (aka integer) registers + Normally this is GR_REGS, but in mips16 mode this is M16_REGS + 'y' General registers (in both mips16 and non mips16 mode) + 'e' mips16 non argument registers (M16_NA_REGS) + 't' mips16 temporary register ($24) + 'f' Floating point registers + 'h' Hi register + 'l' Lo register + 'x' Multiply/divide registers + 'a' HILO_REG + 'z' FP Status register + 'b' All registers */ + +extern enum reg_class mips_char_to_class[]; + +#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ] + +/* The letters I, J, K, L, M, N, O, and P in a register constraint + string can be used to stand for particular ranges of immediate + operands. This macro defines what the ranges are. C is the + letter, and VALUE is a constant value. Return 1 if VALUE is + in the range specified by C. */ + +/* For MIPS: + + `I' is used for the range of constants an arithmetic insn can + actually contain (16 bits signed integers). + + `J' is used for the range which is just zero (ie, $r0). + + `K' is used for the range of constants a logical insn can actually + contain (16 bit zero-extended integers). + + `L' is used for the range of constants that be loaded with lui + (ie, the bottom 16 bits are zero). + + `M' is used for the range of constants that take two words to load + (ie, not matched by `I', `K', and `L'). + + `N' is used for negative 16 bit constants other than -65536. + + `O' is a 15 bit signed integer. + + `P' is used for positive 16 bit constants. */ + +#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) +#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000) + +#define CONST_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \ + : (C) == 'J' ? ((VALUE) == 0) \ + : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \ + : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \ + && (((VALUE) & ~2147483647) == 0 \ + || ((VALUE) & ~2147483647) == ~2147483647)) \ + : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \ + && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \ + && (((VALUE) & 0x0000ffff) != 0 \ + || (((VALUE) & ~2147483647) != 0 \ + && ((VALUE) & ~2147483647) != ~2147483647))) \ + : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \ + : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \ + : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \ + : 0) + +/* Similar, but for floating constants, and defining letters G and H. + Here VALUE is the CONST_DOUBLE rtx itself. */ + +/* For Mips + + 'G' : Floating point 0 */ + +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'G' \ + && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) + +/* Letters in the range `Q' through `U' may be defined in a + machine-dependent fashion to stand for arbitrary operand types. + The machine description macro `EXTRA_CONSTRAINT' is passed the + operand as its first argument and the constraint letter as its + second operand. + + `Q' is for mips16 GP relative constants + `R' is for memory references which take 1 word for the instruction. + `S' is for references to extern items which are PIC for OSF/rose. + `T' is for memory addresses that can be used to load two words. */ + +#define EXTRA_CONSTRAINT(OP,CODE) \ + (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \ + : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \ + && mips16_gp_offset_p (OP)) \ + : (GET_CODE (OP) != MEM) ? FALSE \ + : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \ + : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \ + && HALF_PIC_ADDRESS_P (OP)) \ + : FALSE) + +/* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. */ + +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + ((CLASS) != ALL_REGS \ + ? (! TARGET_MIPS16 \ + ? (CLASS) \ + : ((CLASS) != GR_REGS \ + ? (CLASS) \ + : M16_REGS)) \ + : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \ + ? (TARGET_SOFT_FLOAT \ + ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \ + : FP_REGS) \ + : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ + || GET_MODE (X) == VOIDmode) \ + ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \ + : (CLASS)))) + +/* Certain machines have the property that some registers cannot be + copied to some other registers without using memory. Define this + macro on those machines to be a C expression that is non-zero if + objects of mode MODE in registers of CLASS1 can only be copied to + registers of class CLASS2 by storing a register of CLASS1 into + memory and loading that memory location into a register of CLASS2. + + Do not define this macro if its value would always be zero. */ + +#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ + ((!TARGET_DEBUG_H_MODE \ + && GET_MODE_CLASS (MODE) == MODE_INT \ + && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \ + || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \ + || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \ + && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \ + || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS)))) + +/* The HI and LO registers can only be reloaded via the general + registers. Condition code registers can only be loaded to the + general registers, and from the floating point registers. */ + +#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ + mips_secondary_reload_class (CLASS, MODE, X, 1) +#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ + mips_secondary_reload_class (CLASS, MODE, X, 0) + +/* Not declared above, with the other functions, because enum + reg_class is not declared yet. */ +extern enum reg_class mips_secondary_reload_class (); + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ + +#define CLASS_UNITS(mode, size) \ + ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) + +#define CLASS_MAX_NREGS(CLASS, MODE) \ + ((CLASS) == FP_REGS \ + ? (TARGET_FLOAT64 \ + ? CLASS_UNITS (MODE, 8) \ + : 2 * CLASS_UNITS (MODE, 8)) \ + : CLASS_UNITS (MODE, UNITS_PER_WORD)) + +/* If defined, this is a C expression whose value should be + nonzero if the insn INSN has the effect of mysteriously + clobbering the contents of hard register number REGNO. By + "mysterious" we mean that the insn's RTL expression doesn't + describe such an effect. + + If this macro is not defined, it means that no insn clobbers + registers mysteriously. This is the usual situation; all else + being equal, it is best for the RTL expression to show all the + activity. */ + +/* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */ + + +/* Stack layout; function entry, exit and calling. */ + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ +/* #define FRAME_GROWS_DOWNWARD */ + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +#define STARTING_FRAME_OFFSET \ + (current_function_outgoing_args_size \ + + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)) + +/* Offset from the stack pointer register to an item dynamically + allocated on the stack, e.g., by `alloca'. + + The default value for this macro is `STACK_POINTER_OFFSET' plus the + length of the outgoing arguments. The default is correct for most + machines. See `function.c' for details. + + The MIPS ABI states that functions which dynamically allocate the + stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like + we are trying to create a second frame pointer to the function, so + allocate some stack space to make it happy. + + However, the linker currently complains about linking any code that + dynamically allocates stack space, and there seems to be a bug in + STACK_DYNAMIC_OFFSET, so don't define this right now. */ + +#if 0 +#define STACK_DYNAMIC_OFFSET(FUNDECL) \ + ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \ + ? 4*UNITS_PER_WORD \ + : current_function_outgoing_args_size) +#endif + +/* The return address for the current frame is in r31 is this is a leaf + function. Otherwise, it is on the stack. It is at a variable offset + from sp/fp/ap, so we define a fake hard register rap which is a + poiner to the return address on the stack. This always gets eliminated + during reload to be either the frame pointer or the stack pointer plus + an offset. */ + +/* ??? This definition fails for leaf functions. There is currently no + general solution for this problem. */ + +/* ??? There appears to be no way to get the return address of any previous + frame except by disassembling instructions in the prologue/epilogue. + So currently we support only the current frame. */ + +#define RETURN_ADDR_RTX(count, frame) \ + ((count == 0) \ + ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\ + : (rtx) 0) + +/* Structure to be filled in by compute_frame_size with register + save masks, and offsets for the current function. */ + +struct mips_frame_info +{ + long total_size; /* # bytes that the entire frame takes up */ + long var_size; /* # bytes that variables take up */ + long args_size; /* # bytes that outgoing arguments take up */ + long extra_size; /* # bytes of extra gunk */ + int gp_reg_size; /* # bytes needed to store gp regs */ + int fp_reg_size; /* # bytes needed to store fp regs */ + long mask; /* mask of saved gp registers */ + long fmask; /* mask of saved fp registers */ + long gp_save_offset; /* offset from vfp to store gp registers */ + long fp_save_offset; /* offset from vfp to store fp registers */ + long gp_sp_offset; /* offset from new sp to store gp registers */ + long fp_sp_offset; /* offset from new sp to store fp registers */ + int initialized; /* != 0 if frame size already calculated */ + int num_gp; /* number of gp registers saved */ + int num_fp; /* number of fp registers saved */ + long insns_len; /* length of insns; mips16 only */ +}; + +extern struct mips_frame_info current_frame_info; + +/* If defined, this macro specifies a table of register pairs used to + eliminate unneeded registers that point into the stack frame. If + it is not defined, the only elimination attempted by the compiler + is to replace references to the frame pointer with references to + the stack pointer. + + The definition of this macro is a list of structure + initializations, each of which specifies an original and + replacement register. + + On some machines, the position of the argument pointer is not + known until the compilation is completed. In such a case, a + separate hard register must be used for the argument pointer. + This register can be eliminated by replacing it with either the + frame pointer or the argument pointer, depending on whether or not + the frame pointer has been eliminated. + + In this case, you might specify: + #define ELIMINABLE_REGS \ + {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ + {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} + + Note that the elimination of the argument pointer with the stack + pointer is specified first since that is the preferred elimination. + + The eliminations to $17 are only used on the mips16. See the + definition of HARD_FRAME_POINTER_REGNUM. */ + +#define ELIMINABLE_REGS \ +{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ + { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ + { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \ + { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \ + { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \ + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ + { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} + +/* A C expression that returns non-zero if the compiler is allowed to + try to replace register number FROM-REG with register number + TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is + defined, and will usually be the constant 1, since most of the + cases preventing register elimination are things that the compiler + already knows about. + + When not in mips16 and mips64, we can always eliminate to the + frame pointer. We can eliminate to the stack pointer unless + a frame pointer is needed. In mips16 mode, we need a frame + pointer for a large frame; otherwise, reload may be unable + to compute the address of a local variable, since there is + no way to add a large constant to the stack pointer + without using a temporary register. + + In mips16, for some instructions (eg lwu), we can't eliminate the + frame pointer for the stack pointer. These instructions are + only generated in TARGET_64BIT mode. + */ + +#define CAN_ELIMINATE(FROM, TO) \ + (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \ + || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \ + || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \ + && ((TO) == HARD_FRAME_POINTER_REGNUM \ + || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \ + && ! (TARGET_MIPS16 && TARGET_64BIT) \ + && (! TARGET_MIPS16 \ + || compute_frame_size (get_frame_size ()) < 32768))))) + +/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It + specifies the initial difference between the specified pair of + registers. This macro must be defined if `ELIMINABLE_REGS' is + defined. */ + +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ +{ compute_frame_size (get_frame_size ()); \ + if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \ + && (TO) == HARD_FRAME_POINTER_REGNUM) \ + (OFFSET) = - current_function_outgoing_args_size; \ + else if ((FROM) == FRAME_POINTER_REGNUM) \ + (OFFSET) = 0; \ + else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \ + && (TO) == HARD_FRAME_POINTER_REGNUM) \ + (OFFSET) = (current_frame_info.total_size \ + - current_function_outgoing_args_size \ + - ((mips_abi != ABI_32 \ + && mips_abi != ABI_O64 \ + && mips_abi != ABI_EABI) \ + ? current_function_pretend_args_size \ + : 0)); \ + else if ((FROM) == ARG_POINTER_REGNUM) \ + (OFFSET) = (current_frame_info.total_size \ + - ((mips_abi != ABI_32 \ + && mips_abi != ABI_O64 \ + && mips_abi != ABI_EABI) \ + ? current_function_pretend_args_size \ + : 0)); \ + /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \ + so we must add 4 bytes to the offset to get the right value. */ \ + else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \ + { \ + if (leaf_function_p ()) \ + (OFFSET) = 0; \ + else (OFFSET) = current_frame_info.gp_sp_offset \ + + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \ + * (BYTES_BIG_ENDIAN != 0)); \ + } \ +} + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On the vax, sp@- in a byte insn really pushes a word. */ + +/* #define PUSH_ROUNDING(BYTES) 0 */ + +/* If defined, the maximum amount of space required for outgoing + arguments will be computed and placed into the variable + `current_function_outgoing_args_size'. No space will be pushed + onto the stack for each call; instead, the function prologue + should increase the stack frame size by this amount. + + It is not proper to define both `PUSH_ROUNDING' and + `ACCUMULATE_OUTGOING_ARGS'. */ +#define ACCUMULATE_OUTGOING_ARGS + +/* Offset from the argument pointer register to the first argument's + address. On some machines it may depend on the data type of the + function. + + If `ARGS_GROW_DOWNWARD', this is the offset to the location above + the first argument's address. + + On the MIPS, we must skip the first argument position if we are + returning a structure or a union, to account for its address being + passed in $4. However, at the current time, this produces a compiler + that can't bootstrap, so comment it out for now. */ + +#if 0 +#define FIRST_PARM_OFFSET(FNDECL) \ + (FNDECL != 0 \ + && TREE_TYPE (FNDECL) != 0 \ + && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \ + && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \ + || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \ + ? UNITS_PER_WORD \ + : 0) +#else +#define FIRST_PARM_OFFSET(FNDECL) 0 +#endif + +/* When a parameter is passed in a register, stack space is still + allocated for it. For the MIPS, stack space must be allocated, cf + Asm Lang Prog Guide page 7-8. + + BEWARE that some space is also allocated for non existing arguments + in register. In case an argument list is of form GF used registers + are a0 (a2,a3), but we should push over a1... */ + +#define REG_PARM_STACK_SPACE(FNDECL) \ + ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL)) + +/* Define this if it is the responsibility of the caller to + allocate the area reserved for arguments passed in registers. + If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect + of this macro is to determine whether the space is included in + `current_function_outgoing_args_size'. */ +#define OUTGOING_REG_PARM_STACK_SPACE + +/* Align stack frames on 64 bits (Double Word ). */ +#ifndef STACK_BOUNDARY +#define STACK_BOUNDARY 64 +#endif + +/* Make sure 4 words are always allocated on the stack. */ + +#ifndef STACK_ARGS_ADJUST +#define STACK_ARGS_ADJUST(SIZE) \ +{ \ + if (SIZE.constant < 4 * UNITS_PER_WORD) \ + SIZE.constant = 4 * UNITS_PER_WORD; \ +} +#endif + + +/* A C expression that should indicate the number of bytes of its + own arguments that a function pops on returning, or 0 + if the function pops no arguments and the caller must therefore + pop them all after the function returns. + + FUNDECL is the declaration node of the function (as a tree). + + FUNTYPE is a C variable whose value is a tree node that + describes the function in question. Normally it is a node of + type `FUNCTION_TYPE' that describes the data type of the function. + From this it is possible to obtain the data types of the value + and arguments (if known). + + When a call to a library function is being considered, FUNTYPE + will contain an identifier node for the library function. Thus, + if you need to distinguish among various library functions, you + can do so by their names. Note that "library function" in this + context means a function used to perform arithmetic, whose name + is known specially in the compiler and was not mentioned in the + C code being compiled. + + STACK-SIZE is the number of bytes of arguments passed on the + stack. If a variable number of bytes is passed, it is zero, and + argument popping will always be the responsibility of the + calling function. */ + +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 + + +/* Symbolic macros for the registers used to return integer and floating + point values. */ + +#define GP_RETURN (GP_REG_FIRST + 2) +#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) + +/* Symbolic macros for the first/last argument registers. */ + +#define GP_ARG_FIRST (GP_REG_FIRST + 4) +#define GP_ARG_LAST (GP_REG_FIRST + 7) +#define FP_ARG_FIRST (FP_REG_FIRST + 12) +#define FP_ARG_LAST (FP_REG_FIRST + 15) + +#define MAX_ARGS_IN_REGISTERS 4 + +/* Define how to find the value returned by a library function + assuming the value has mode MODE. Because we define + PROMOTE_FUNCTION_RETURN, we must promote the mode just as + PROMOTE_MODE does. */ + +#define LIBCALL_VALUE(MODE) \ + gen_rtx (REG, \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), \ + ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ + && (! TARGET_SINGLE_FLOAT \ + || GET_MODE_SIZE (MODE) <= 4)) \ + ? FP_RETURN \ + : GP_RETURN)) + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ + +#define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE)) + + +/* 1 if N is a possible register number for a function value. + On the MIPS, R2 R3 and F0 F2 are the only register thus used. + Currently, R2 and F0 are only implemented here (C has no complex type) */ + +#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) + +/* 1 if N is a possible register number for function argument passing. + We have no FP argument registers when soft-float. When FP registers + are 32 bits, we can't directly reference the odd numbered ones. */ + +#define FUNCTION_ARG_REGNO_P(N) \ + (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \ + || ((! TARGET_SOFT_FLOAT \ + && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \ + && (TARGET_FLOAT64 || (0 == (N) % 2))) \ + && ! fixed_regs[N])) + +/* A C expression which can inhibit the returning of certain function + values in registers, based on the type of value. A nonzero value says + to return the function value in memory, just as large structures are + always returned. Here TYPE will be a C expression of type + `tree', representing the data type of the value. + + Note that values of mode `BLKmode' must be explicitly + handled by this macro. Also, the option `-fpcc-struct-return' + takes effect regardless of this macro. On most systems, it is + possible to leave the macro undefined; this causes a default + definition to be used, whose value is the constant 1 for BLKmode + values, and 0 otherwise. + + GCC normally converts 1 byte structures into chars, 2 byte + structs into shorts, and 4 byte structs into ints, and returns + them this way. Defining the following macro overrides this, + to give us MIPS cc compatibility. */ + +#define RETURN_IN_MEMORY(TYPE) \ + (TYPE_MODE (TYPE) == BLKmode) + +/* A code distinguishing the floating point format of the target + machine. There are three defined values: IEEE_FLOAT_FORMAT, + VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */ + +#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT + + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + + On the mips16, we need to keep track of which floating point + arguments were passed in general registers, but would have been + passed in the FP regs if this were a 32 bit function, so that we + can move them to the FP regs if we wind up calling a 32 bit + function. We record this information in fp_code, encoded in base + four. A zero digit means no floating point argument, a one digit + means an SFmode argument, and a two digit means a DFmode argument, + and a three digit is not used. The low order digit is the first + argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by + an SFmode argument. ??? A more sophisticated approach will be + needed if MIPS_ABI != ABI_32. */ + +typedef struct mips_args { + int gp_reg_found; /* whether a gp register was found yet */ + int arg_number; /* argument number */ + int arg_words; /* # total words the arguments take */ + int fp_arg_words; /* # words for FP args (MIPS_EABI only) */ + int last_arg_fp; /* nonzero if last arg was FP (EABI only) */ + int fp_code; /* Mode of FP arguments (mips16) */ + int num_adjusts; /* number of adjustments made */ + /* Adjustments made to args pass in regs. */ + /* ??? The size is doubled to work around a + bug in the code that sets the adjustments + in function_arg. */ + struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2]; +} CUMULATIVE_ARGS; + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. + +*/ + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ + init_cumulative_args (&CUM, FNTYPE, LIBNAME) \ + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + (TYPE is null for libcalls where that information may not be available.) */ + +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + function_arg_advance (&CUM, MODE, TYPE, NAMED) + +/* Determine where to put an argument to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ + function_arg( &CUM, MODE, TYPE, NAMED) + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. */ + +#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ + function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) + +/* If defined, a C expression that gives the alignment boundary, in + bits, of an argument with the specified mode and type. If it is + not defined, `PARM_BOUNDARY' is used for all arguments. */ + +#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ + (((TYPE) != 0) \ + ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \ + ? PARM_BOUNDARY \ + : TYPE_ALIGN(TYPE)) \ + : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \ + ? PARM_BOUNDARY \ + : GET_MODE_ALIGNMENT(MODE))) + + +/* This macro generates the assembly code for function entry. + FILE is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. */ + +#define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE) + +/* This macro generates the assembly code for function exit, + on machines that need it. If FUNCTION_EPILOGUE is not defined + then individual return instructions are generated for each + return statement. Args are same as for FUNCTION_PROLOGUE. */ + +#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE) + +/* Tell prologue and epilogue if register REGNO should be saved / restored. */ + +#define MUST_SAVE_REGISTER(regno) \ + ((regs_ever_live[regno] && !call_used_regs[regno]) \ + || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ + || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31])) + +/* ALIGN FRAMES on double word boundaries */ +#ifndef MIPS_STACK_ALIGN +#define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7) +#endif + + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (TARGET_MIPS16) \ + sorry ("mips16 function profiling"); \ + fprintf (FILE, "\t.set\tnoreorder\n"); \ + fprintf (FILE, "\t.set\tnoat\n"); \ + fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ + reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ + fprintf (FILE, "\tjal\t_mcount\n"); \ + fprintf (FILE, \ + "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ + TARGET_64BIT ? "dsubu" : "subu", \ + reg_names[STACK_POINTER_REGNUM], \ + reg_names[STACK_POINTER_REGNUM], \ + Pmode == DImode ? 16 : 8); \ + fprintf (FILE, "\t.set\treorder\n"); \ + fprintf (FILE, "\t.set\tat\n"); \ +} + +/* Define this macro if the code for function profiling should come + before the function prologue. Normally, the profiling code comes + after. */ + +/* #define PROFILE_BEFORE_PROLOGUE */ + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ + +#define EXIT_IGNORE_STACK 1 + + +/* A C statement to output, on the stream FILE, assembler code for a + block of data that contains the constant parts of a trampoline. + This code should not include a label--the label is taken care of + automatically. */ + +#define TRAMPOLINE_TEMPLATE(STREAM) \ +{ \ + fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \ + fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \ + fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \ + if (Pmode == DImode) \ + { \ + fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \ + fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \ + } \ + else \ + { \ + fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \ + fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \ + } \ + fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \ + fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \ + fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \ + if (Pmode == DImode) \ + { \ + fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \ + fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \ + } \ + else \ + { \ + fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \ + fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \ + } \ +} + +/* A C expression for the size in bytes of the trampoline, as an + integer. */ + +#define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8)) + +/* Alignment required for trampolines, in bits. */ + +#define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32) + +/* INITIALIZE_TRAMPOLINE calls this library function to flush + program and data caches. */ + +#ifndef CACHE_FLUSH_FUNC +#define CACHE_FLUSH_FUNC "_flush_cache" +#endif + +/* A C statement to initialize the variable parts of a trampoline. + ADDR is an RTX for the address of the trampoline; FNADDR is an + RTX for the address of the nested function; STATIC_CHAIN is an + RTX for the static chain value that should be passed to the + function when it is called. */ + +#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ +{ \ + rtx addr = ADDR; \ + if (Pmode == DImode) \ + { \ + emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \ + emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\ + } \ + else \ + { \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\ + } \ + \ + /* Flush both caches. We need to flush the data cache in case \ + the system has a write-back cache. */ \ + /* ??? Should check the return value for errors. */ \ + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \ + 0, VOIDmode, 3, addr, Pmode, \ + GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\ + GEN_INT (3), TYPE_MODE (integer_type_node)); \ +} + +/* Addressing modes, and classification of registers for them. */ + +/* #define HAVE_POST_INCREMENT 0 */ +/* #define HAVE_POST_DECREMENT 0 */ + +/* #define HAVE_PRE_DECREMENT 0 */ +/* #define HAVE_PRE_INCREMENT 0 */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + These definitions are NOT overridden anywhere. */ + +#define BASE_REG_P(regno, mode) \ + (TARGET_MIPS16 \ + ? (M16_REG_P (regno) \ + || (regno) == FRAME_POINTER_REGNUM \ + || (regno) == ARG_POINTER_REGNUM \ + || ((regno) == STACK_POINTER_REGNUM \ + && (GET_MODE_SIZE (mode) == 4 \ + || GET_MODE_SIZE (mode) == 8))) \ + : GP_REG_P (regno)) + +#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \ + BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \ + (mode)) + +#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \ + (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode)))) + +#define REGNO_OK_FOR_INDEX_P(regno) 0 +#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \ + GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode)) + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects them all. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Some source files that are used after register allocation + need to be strict. */ + +#ifndef REG_OK_STRICT + +#define REG_OK_STRICT_P 0 +#define REG_OK_FOR_INDEX_P(X) 0 +#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ + GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE)) + +#else + +#define REG_OK_STRICT_P 1 +#define REG_OK_FOR_INDEX_P(X) 0 +#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ + REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE)) + +#endif + + +/* Maximum number of registers that can appear in a valid memory address. */ + +#define MAX_REGS_PER_ADDRESS 1 + +/* A C compound statement with a conditional `goto LABEL;' executed + if X (an RTX) is a legitimate memory address on the target + machine for a memory operand of mode MODE. + + It usually pays to define several simpler macros to serve as + subroutines for this one. Otherwise it may be too complicated + to understand. + + This macro must exist in two variants: a strict variant and a + non-strict one. The strict variant is used in the reload pass. + It must be defined so that any pseudo-register that has not been + allocated a hard register is considered a memory reference. In + contexts where some kind of register is required, a + pseudo-register with no hard register must be rejected. + + The non-strict variant is used in other passes. It must be + defined to accept all pseudo-registers in every context where + some kind of register is required. + + Compiler source files that want to use the strict variant of + this macro define the macro `REG_OK_STRICT'. You should use an + `#ifdef REG_OK_STRICT' conditional to define the strict variant + in that case and the non-strict variant otherwise. + + Typically among the subroutines used to define + `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for + acceptable registers for various purposes (one for base + registers, one for index registers, and so on). Then only these + subroutine macros need have two variants; the higher levels of + macros may be the same whether strict or not. + + Normally, constant addresses which are the sum of a `symbol_ref' + and an integer are stored inside a `const' RTX to mark them as + constant. Therefore, there is no need to recognize such sums + specifically as legitimate addresses. Normally you would simply + recognize any `const' as legitimate. + + Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle + constant sums that are not marked with `const'. It assumes + that a naked `plus' indicates indexing. If so, then you *must* + reject such naked constant sums as illegitimate addresses, so + that none of them will be given to `PRINT_OPERAND_ADDRESS'. + + On some machines, whether a symbolic address is legitimate + depends on the section that the address refers to. On these + machines, define the macro `ENCODE_SECTION_INFO' to store the + information into the `symbol_ref', and then check for it here. + When you see a `const', you will have to look inside it to find + the `symbol_ref' in order to determine the section. */ + +#if 1 +#define GO_PRINTF(x) trace(x) +#define GO_PRINTF2(x,y) trace(x,y) +#define GO_DEBUG_RTX(x) debug_rtx(x) + +#else +#define GO_PRINTF(x) +#define GO_PRINTF2(x,y) +#define GO_DEBUG_RTX(x) +#endif + +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ \ + register rtx xinsn = (X); \ + \ + if (TARGET_DEBUG_B_MODE) \ + { \ + GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \ + (REG_OK_STRICT_P) ? "" : "not "); \ + GO_DEBUG_RTX (xinsn); \ + } \ + \ + /* The mips16 can only use the stack pointer as a base register when \ + loading SImode or DImode values. */ \ + if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \ + goto ADDR; \ + \ + if (CONSTANT_ADDRESS_P (xinsn) \ + && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \ + && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \ + goto ADDR; \ + \ + if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \ + { \ + register rtx xlow0 = XEXP (xinsn, 0); \ + register rtx xlow1 = XEXP (xinsn, 1); \ + \ + if (GET_CODE (xlow0) == REG \ + && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \ + && mips_check_split (xlow1, MODE)) \ + goto ADDR; \ + } \ + \ + if (GET_CODE (xinsn) == PLUS) \ + { \ + register rtx xplus0 = XEXP (xinsn, 0); \ + register rtx xplus1 = XEXP (xinsn, 1); \ + register enum rtx_code code0 = GET_CODE (xplus0); \ + register enum rtx_code code1 = GET_CODE (xplus1); \ + \ + /* The mips16 can only use the stack pointer as a base register \ + when loading SImode or DImode values. */ \ + if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \ + { \ + if (code1 == CONST_INT \ + && INTVAL (xplus1) >= -32768 \ + && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \ + goto ADDR; \ + \ + /* On the mips16, we represent GP relative offsets in RTL. \ + These are 16 bit signed values, and can serve as register \ + offsets. */ \ + if (TARGET_MIPS16 \ + && mips16_gp_offset_p (xplus1)) \ + goto ADDR; \ + \ + /* For some code sequences, you actually get better code by \ + pretending that the MIPS supports an address mode of a \ + constant address + a register, even though the real \ + machine doesn't support it. This is because the \ + assembler can use $r1 to load just the high 16 bits, add \ + in the register, and fold the low 16 bits into the memory \ + reference, whereas the compiler generates a 4 instruction \ + sequence. On the other hand, CSE is not as effective. \ + It would be a win to generate the lui directly, but the \ + MIPS assembler does not have syntax to generate the \ + appropriate relocation. */ \ + \ + /* Also accept CONST_INT addresses here, so no else. */ \ + /* Reject combining an embedded PIC text segment reference \ + with a register. That requires an additional \ + instruction. */ \ + /* ??? Reject combining an address with a register for the MIPS \ + 64 bit ABI, because the SGI assembler can not handle this. */ \ + if (!TARGET_DEBUG_A_MODE \ + && (mips_abi == ABI_32 \ + || mips_abi == ABI_O64 \ + || mips_abi == ABI_EABI) \ + && CONSTANT_ADDRESS_P (xplus1) \ + && ! mips_split_addresses \ + && (!TARGET_EMBEDDED_PIC \ + || code1 != CONST \ + || GET_CODE (XEXP (xplus1, 0)) != MINUS) \ + && !TARGET_MIPS16) \ + goto ADDR; \ + } \ + } \ + \ + if (TARGET_DEBUG_B_MODE) \ + GO_PRINTF ("Not a legitimate address\n"); \ +} + + +/* A C expression that is 1 if the RTX X is a constant which is a + valid address. This is defined to be the same as `CONSTANT_P (X)', + but rejecting CONST_DOUBLE. */ +/* When pic, we must reject addresses of the form symbol+large int. + This is because an instruction `sw $4,s+70000' needs to be converted + by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the + assembler would use $at as a temp to load in the large offset. In this + case $at is already in use. We convert such problem addresses to + `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */ +/* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */ +#define CONSTANT_ADDRESS_P(X) \ + ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ + || (GET_CODE (X) == CONST \ + && ! (flag_pic && pic_address_needs_scratch (X)) \ + && (mips_abi == ABI_32 \ + || mips_abi == ABI_O64 \ + || mips_abi == ABI_EABI))) \ + && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X))) + +/* Define this, so that when PIC, reload won't try to reload invalid + addresses which require two reload registers. */ + +#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. + + At present, GAS doesn't understand li.[sd], so don't allow it + to be generated at present. Also, the MIPS assembler does not + grok li.d Infinity. */ + +/* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */ +#define LEGITIMATE_CONSTANT_P(X) \ + ((GET_CODE (X) != CONST_DOUBLE \ + || mips_const_double_ok (X, GET_MODE (X))) \ + && ! (GET_CODE (X) == CONST \ + && mips_abi != ABI_32 \ + && mips_abi != ABI_O64 \ + && mips_abi != ABI_EABI) \ + && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0))) + +/* A C compound statement that attempts to replace X with a valid + memory address for an operand of mode MODE. WIN will be a C + statement label elsewhere in the code; the macro definition may + use + + GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); + + to avoid further processing if the address has become legitimate. + + X will always be the result of a call to `break_out_memory_refs', + and OLDX will be the operand that was given to that function to + produce X. + + The code generated by this macro should not alter the + substructure of X. If it transforms X into a more legitimate + form, it should assign X (which will always be a C variable) a + new value. + + It is not necessary for this macro to come up with a legitimate + address. The compiler has standard ways of doing so in all + cases. In fact, it is safe for this macro to do nothing. But + often a machine-dependent strategy can generate better code. + + For the MIPS, transform: + + memory(X + <large int>) + + into: + + Y = <large int> & ~0x7fff; + Z = X + Y + memory (Z + (<large int> & 0x7fff)); + + This is for CSE to find several similar references, and only use one Z. + + When PIC, convert addresses of the form memory (symbol+large int) to + memory (reg+large int). */ + + +#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ +{ \ + register rtx xinsn = (X); \ + \ + if (TARGET_DEBUG_B_MODE) \ + { \ + GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \ + GO_DEBUG_RTX (xinsn); \ + } \ + \ + if (mips_split_addresses && mips_check_split (X, MODE)) \ + { \ + /* ??? Is this ever executed? */ \ + X = gen_rtx (LO_SUM, Pmode, \ + copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \ + goto WIN; \ + } \ + \ + if (GET_CODE (xinsn) == CONST \ + && ((flag_pic && pic_address_needs_scratch (xinsn)) \ + /* ??? SGI's Irix 6 assembler can't handle CONST. */ \ + || (mips_abi != ABI_32 \ + && mips_abi != ABI_O64 \ + && mips_abi != ABI_EABI))) \ + { \ + rtx ptr_reg = gen_reg_rtx (Pmode); \ + rtx constant = XEXP (XEXP (xinsn, 0), 1); \ + \ + emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \ + \ + X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \ + if (SMALL_INT (constant)) \ + goto WIN; \ + /* Otherwise we fall through so the code below will fix the \ + constant. */ \ + xinsn = X; \ + } \ + \ + if (GET_CODE (xinsn) == PLUS) \ + { \ + register rtx xplus0 = XEXP (xinsn, 0); \ + register rtx xplus1 = XEXP (xinsn, 1); \ + register enum rtx_code code0 = GET_CODE (xplus0); \ + register enum rtx_code code1 = GET_CODE (xplus1); \ + \ + if (code0 != REG && code1 == REG) \ + { \ + xplus0 = XEXP (xinsn, 1); \ + xplus1 = XEXP (xinsn, 0); \ + code0 = GET_CODE (xplus0); \ + code1 = GET_CODE (xplus1); \ + } \ + \ + if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \ + && code1 == CONST_INT && !SMALL_INT (xplus1)) \ + { \ + rtx int_reg = gen_reg_rtx (Pmode); \ + rtx ptr_reg = gen_reg_rtx (Pmode); \ + \ + emit_move_insn (int_reg, \ + GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \ + \ + emit_insn (gen_rtx (SET, VOIDmode, \ + ptr_reg, \ + gen_rtx (PLUS, Pmode, xplus0, int_reg))); \ + \ + X = gen_rtx (PLUS, Pmode, ptr_reg, \ + GEN_INT (INTVAL (xplus1) & 0x7fff)); \ + goto WIN; \ + } \ + } \ + \ + if (TARGET_DEBUG_B_MODE) \ + GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \ +} + + +/* A C statement or compound statement with a conditional `goto + LABEL;' executed if memory address X (an RTX) can have different + meanings depending on the machine mode of the memory reference it + is used for. + + Autoincrement and autodecrement addresses typically have + mode-dependent effects because the amount of the increment or + decrement is the size of the operand being addressed. Some + machines have other mode-dependent addresses. Many RISC machines + have no mode-dependent addresses. + + You may assume that ADDR is a valid address for the machine. */ + +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} + + +/* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + The macro definition, if any, is executed immediately after the + rtl for DECL has been created and stored in `DECL_RTL (DECL)'. + The value of the rtl will be a `mem' whose address is a + `symbol_ref'. + + The usual thing for this macro to do is to a flag in the + `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified + name string in the `symbol_ref' (if one bit is not enough + information). + + The best way to modify the name string is by adding text to the + beginning, with suitable punctuation to prevent any ambiguity. + Allocate the new name in `saveable_obstack'. You will have to + modify `ASM_OUTPUT_LABELREF' to remove and decode the added text + and output the name accordingly. + + You can also check the information stored in the `symbol_ref' in + the definition of `GO_IF_LEGITIMATE_ADDRESS' or + `PRINT_OPERAND_ADDRESS'. + + When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all + small objects. + + When generating embedded PIC code, SYMBOL_REF_FLAG is set for + symbols which are not in the .text section. + + When generating mips16 code, SYMBOL_REF_FLAG is set for string + constants which are put in the .text section. We also record the + total length of all such strings; this total is used to decide + whether we need to split the constant table, and need not be + precisely correct. + + When not mips16 code nor embedded PIC, if a symbol is in a + gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from + splitting the reference so that gas can generate a gp relative + reference. + + When TARGET_EMBEDDED_DATA is set, we assume that all const + variables will be stored in ROM, which is too far from %gp to use + %gprel addressing. Note that (1) we include "extern const" + variables in this, which mips_select_section doesn't, and (2) we + can't always tell if they're really const (they might be const C++ + objects with non-const constructors), so we err on the side of + caution and won't use %gprel anyway (otherwise we'd have to defer + this decision to the linker/loader). The handling of extern consts + is why the DECL_INITIAL macros differ from mips_select_section. + + If you are changing this macro, you should look at + mips_select_section and see if it needs a similar change. */ + +#ifndef UNIQUE_SECTION_P +#define UNIQUE_SECTION_P(DECL) (0) +#endif + +#define ENCODE_SECTION_INFO(DECL) \ +do \ + { \ + if (TARGET_MIPS16) \ + { \ + if (TREE_CODE (DECL) == STRING_CST \ + && ! flag_writable_strings \ + /* If this string is from a function, and the function will \ + go in a gnu linkonce section, then we can't directly \ + access the string. This gets an assembler error \ + "unsupported PC relative reference to different section".\ + If we modify SELECT_SECTION to put it in function_section\ + instead of text_section, it still fails because \ + DECL_SECTION_NAME isn't set until assemble_start_function.\ + If we fix that, it still fails because strings are shared\ + among multiple functions, and we have cross section \ + references again. We force it to work by putting string \ + addresses in the constant pool and indirecting. */ \ + && (! current_function_decl \ + || ! UNIQUE_SECTION_P (current_function_decl))) \ + { \ + SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \ + mips_string_length += TREE_STRING_LENGTH (DECL); \ + } \ + } \ + \ + if (TARGET_EMBEDDED_DATA \ + && (TREE_CODE (DECL) == VAR_DECL \ + && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \ + && (!DECL_INITIAL (DECL) \ + || TREE_CONSTANT (DECL_INITIAL (DECL)))) \ + { \ + SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \ + } \ + \ + else if (TARGET_EMBEDDED_PIC) \ + { \ + if (TREE_CODE (DECL) == VAR_DECL) \ + SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ + else if (TREE_CODE (DECL) == FUNCTION_DECL) \ + SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \ + else if (TREE_CODE (DECL) == STRING_CST \ + && ! flag_writable_strings) \ + SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \ + else \ + SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \ + } \ + \ + else if (TREE_CODE (DECL) == VAR_DECL \ + && DECL_SECTION_NAME (DECL) != NULL_TREE \ + && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \ + ".sdata") \ + || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\ + ".sbss"))) \ + { \ + SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ + } \ + \ + /* We can not perform GP optimizations on variables which are in \ + specific sections, except for .sdata and .sbss which are \ + handled above. */ \ + else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \ + && DECL_SECTION_NAME (DECL) == NULL_TREE) \ + { \ + int size = int_size_in_bytes (TREE_TYPE (DECL)); \ + \ + if (size > 0 && size <= mips_section_threshold) \ + SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ + } \ + \ + else if (HALF_PIC_P ()) \ + { \ + HALF_PIC_ENCODE (DECL); \ + } \ + } \ +while (0) + +/* The mips16 wants the constant pool to be after the function, + because the PC relative load instructions use unsigned offsets. */ + +#define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16) + +#define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \ + mips_string_length = 0; + +#if 0 +/* In mips16 mode, put most string constants after the function. */ +#define CONSTANT_AFTER_FUNCTION_P(tree) \ + (TARGET_MIPS16 && mips16_constant_after_function_p (tree)) +#endif + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. + ??? Using HImode in mips16 mode can cause overflow. However, the + overflow is no more likely than the overflow in a branch + instruction. Large functions can currently break in both ways. */ +#define CASE_VECTOR_MODE \ + (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode) + +/* Define as C expression which evaluates to nonzero if the tablejump + instruction expects the table to contain offsets from the address of the + table. + Do not define this if the table should contain absolute addresses. */ +#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16) + +/* Specify the tree operation to be used to convert reals to integers. */ +#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + +/* This is the kind of divide that is easiest to do in the general case. */ +#define EASY_DIV_EXPR TRUNC_DIV_EXPR + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#ifndef DEFAULT_SIGNED_CHAR +#define DEFAULT_SIGNED_CHAR 1 +#endif + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ +#define MOVE_MAX (TARGET_64BIT ? 8 : 4) +#define MAX_MOVE_MAX 8 + +/* Define this macro as a C expression which is nonzero if + accessing less than a word of memory (i.e. a `char' or a + `short') is no faster than accessing a word of memory, i.e., if + such access require more than one instruction or if there is no + difference in cost between byte and (aligned) word loads. + + On RISC machines, it tends to generate better code to define + this as 1, since it avoids making a QI or HI mode register. */ +#define SLOW_BYTE_ACCESS 1 + +/* We assume that the store-condition-codes instructions store 0 for false + and some other value for true. This is the value stored for true. */ + +#define STORE_FLAG_VALUE 1 + +/* Define this if zero-extension is slow (more than one real instruction). */ +#define SLOW_ZERO_EXTEND + +/* Define this to be nonzero if shift instructions ignore all but the low-order + few bits. */ +#define SHIFT_COUNT_TRUNCATED 1 + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +/* In 64 bit mode, 32 bit instructions require that register values be properly + sign-extended to 64 bits. As a result, a truncate is not a no-op if it + converts a value >32 bits to a value <32 bits. */ +/* ??? This results in inefficient code for 64 bit to 32 conversions. + Something needs to be done about this. Perhaps not use any 32 bit + instructions? Perhaps use PROMOTE_MODE? */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ + (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. + + For MIPS we make pointers are the smaller of longs and gp-registers. */ + +#ifndef Pmode +#define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode) +#endif + +/* A function address in a call instruction + is a word address (for indexing purposes) + so give the MEM rtx a words's mode. */ + +#define FUNCTION_MODE (Pmode == DImode ? DImode : SImode) + +/* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and + memset, instead of the BSD functions bcopy and bzero. */ + +#if defined(MIPS_SYSV) || defined(OSF_OS) +#define TARGET_MEM_FUNCTIONS +#endif + + +/* A part of a C `switch' statement that describes the relative + costs of constant RTL expressions. It must contain `case' + labels for expression codes `const_int', `const', `symbol_ref', + `label_ref' and `const_double'. Each case must ultimately reach + a `return' statement to return the relative cost of the use of + that kind of constant value in an expression. The cost may + depend on the precise value of the constant, which is available + for examination in X. + + CODE is the expression code--redundant, since it can be obtained + with `GET_CODE (X)'. */ + +#define CONST_COSTS(X,CODE,OUTER_CODE) \ + case CONST_INT: \ + if (! TARGET_MIPS16) \ + { \ + /* Always return 0, since we don't have different sized \ + instructions, hence different costs according to Richard \ + Kenner */ \ + return 0; \ + } \ + if ((OUTER_CODE) == SET) \ + { \ + if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \ + return 0; \ + else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \ + || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \ + return COSTS_N_INSNS (1); \ + else \ + return COSTS_N_INSNS (2); \ + } \ + /* A PLUS could be an address. We don't want to force an address \ + to use a register, so accept any signed 16 bit value without \ + complaint. */ \ + if ((OUTER_CODE) == PLUS \ + && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \ + return 0; \ + /* A number between 1 and 8 inclusive is efficient for a shift. \ + Otherwise, we will need an extended instruction. */ \ + if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \ + || (OUTER_CODE) == LSHIFTRT) \ + { \ + if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \ + return 0; \ + return COSTS_N_INSNS (1); \ + } \ + /* We can use cmpi for an xor with an unsigned 16 bit value. */ \ + if ((OUTER_CODE) == XOR \ + && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \ + return 0; \ + /* We may be able to use slt or sltu for a comparison with a \ + signed 16 bit value. (The boundary conditions aren't quite \ + right, but this is just a heuristic anyhow.) */ \ + if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \ + || (OUTER_CODE) == GE || (OUTER_CODE) == GT \ + || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \ + || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \ + && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \ + return 0; \ + /* Equality comparisons with 0 are cheap. */ \ + if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \ + && INTVAL (X) == 0) \ + return 0; \ + \ + /* Otherwise, work out the cost to load the value into a \ + register. */ \ + if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \ + return COSTS_N_INSNS (1); \ + else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \ + || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \ + return COSTS_N_INSNS (2); \ + else \ + return COSTS_N_INSNS (3); \ + \ + case LABEL_REF: \ + return COSTS_N_INSNS (2); \ + \ + case CONST: \ + { \ + rtx offset = const0_rtx; \ + rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \ + \ + if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \ + { \ + /* Treat this like a signed 16 bit CONST_INT. */ \ + if ((OUTER_CODE) == PLUS) \ + return 0; \ + else if ((OUTER_CODE) == SET) \ + return COSTS_N_INSNS (1); \ + else \ + return COSTS_N_INSNS (2); \ + } \ + \ + if (GET_CODE (symref) == LABEL_REF) \ + return COSTS_N_INSNS (2); \ + \ + if (GET_CODE (symref) != SYMBOL_REF) \ + return COSTS_N_INSNS (4); \ + \ + /* let's be paranoid.... */ \ + if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \ + return COSTS_N_INSNS (2); \ + \ + return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \ + } \ + \ + case SYMBOL_REF: \ + return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \ + \ + case CONST_DOUBLE: \ + { \ + rtx high, low; \ + if (TARGET_MIPS16) \ + return COSTS_N_INSNS (4); \ + split_double (X, &high, &low); \ + return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \ + || low == CONST0_RTX (GET_MODE (low))) \ + ? 2 : 4); \ + } + +/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. + This can be used, for example, to indicate how costly a multiply + instruction is. In writing this macro, you can use the construct + `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions. + + This macro is optional; do not define it if the default cost + assumptions are adequate for the target machine. + + If -mdebugd is used, change the multiply cost to 2, so multiply by + a constant isn't converted to a series of shifts. This helps + strength reduction, and also makes it easier to identify what the + compiler is doing. */ + +/* ??? Fix this to be right for the R8000. */ +#define RTX_COSTS(X,CODE,OUTER_CODE) \ + case MEM: \ + { \ + int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \ + if (simple_memory_operand (X, GET_MODE (X))) \ + return COSTS_N_INSNS (num_words); \ + \ + return COSTS_N_INSNS (2*num_words); \ + } \ + \ + case FFS: \ + return COSTS_N_INSNS (6); \ + \ + case NOT: \ + return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \ + \ + case AND: \ + case IOR: \ + case XOR: \ + if (GET_MODE (X) == DImode && !TARGET_64BIT) \ + return COSTS_N_INSNS (2); \ + \ + break; \ + \ + case ASHIFT: \ + case ASHIFTRT: \ + case LSHIFTRT: \ + if (GET_MODE (X) == DImode && !TARGET_64BIT) \ + return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \ + \ + break; \ + \ + case ABS: \ + { \ + enum machine_mode xmode = GET_MODE (X); \ + if (xmode == SFmode || xmode == DFmode) \ + return COSTS_N_INSNS (1); \ + \ + return COSTS_N_INSNS (4); \ + } \ + \ + case PLUS: \ + case MINUS: \ + { \ + enum machine_mode xmode = GET_MODE (X); \ + if (xmode == SFmode || xmode == DFmode) \ + { \ + if (mips_cpu == PROCESSOR_R3000 \ + || mips_cpu == PROCESSOR_R3900) \ + return COSTS_N_INSNS (2); \ + else if (mips_cpu == PROCESSOR_R6000) \ + return COSTS_N_INSNS (3); \ + else \ + return COSTS_N_INSNS (6); \ + } \ + \ + if (xmode == DImode && !TARGET_64BIT) \ + return COSTS_N_INSNS (4); \ + \ + break; \ + } \ + \ + case NEG: \ + if (GET_MODE (X) == DImode && !TARGET_64BIT) \ + return 4; \ + \ + break; \ + \ + case MULT: \ + { \ + enum machine_mode xmode = GET_MODE (X); \ + if (xmode == SFmode) \ + { \ + if (mips_cpu == PROCESSOR_R3000 \ + || mips_cpu == PROCESSOR_R3900 \ + || mips_cpu == PROCESSOR_R5000) \ + return COSTS_N_INSNS (4); \ + else if (mips_cpu == PROCESSOR_R6000) \ + return COSTS_N_INSNS (5); \ + else \ + return COSTS_N_INSNS (7); \ + } \ + \ + if (xmode == DFmode) \ + { \ + if (mips_cpu == PROCESSOR_R3000 \ + || mips_cpu == PROCESSOR_R3900 \ + || mips_cpu == PROCESSOR_R5000) \ + return COSTS_N_INSNS (5); \ + else if (mips_cpu == PROCESSOR_R6000) \ + return COSTS_N_INSNS (6); \ + else \ + return COSTS_N_INSNS (8); \ + } \ + \ + if (mips_cpu == PROCESSOR_R3000) \ + return COSTS_N_INSNS (12); \ + else if (mips_cpu == PROCESSOR_R3900) \ + return COSTS_N_INSNS (2); \ + else if (mips_cpu == PROCESSOR_R6000) \ + return COSTS_N_INSNS (17); \ + else if (mips_cpu == PROCESSOR_R5000) \ + return COSTS_N_INSNS (5); \ + else \ + return COSTS_N_INSNS (10); \ + } \ + \ + case DIV: \ + case MOD: \ + { \ + enum machine_mode xmode = GET_MODE (X); \ + if (xmode == SFmode) \ + { \ + if (mips_cpu == PROCESSOR_R3000 \ + || mips_cpu == PROCESSOR_R3900) \ + return COSTS_N_INSNS (12); \ + else if (mips_cpu == PROCESSOR_R6000) \ + return COSTS_N_INSNS (15); \ + else \ + return COSTS_N_INSNS (23); \ + } \ + \ + if (xmode == DFmode) \ + { \ + if (mips_cpu == PROCESSOR_R3000 \ + || mips_cpu == PROCESSOR_R3900) \ + return COSTS_N_INSNS (19); \ + else if (mips_cpu == PROCESSOR_R6000) \ + return COSTS_N_INSNS (16); \ + else \ + return COSTS_N_INSNS (36); \ + } \ + } \ + /* fall through */ \ + \ + case UDIV: \ + case UMOD: \ + if (mips_cpu == PROCESSOR_R3000 \ + || mips_cpu == PROCESSOR_R3900) \ + return COSTS_N_INSNS (35); \ + else if (mips_cpu == PROCESSOR_R6000) \ + return COSTS_N_INSNS (38); \ + else if (mips_cpu == PROCESSOR_R5000) \ + return COSTS_N_INSNS (36); \ + else \ + return COSTS_N_INSNS (69); \ + \ + case SIGN_EXTEND: \ + /* A sign extend from SImode to DImode in 64 bit mode is often \ + zero instructions, because the result can often be used \ + directly by another instruction; we'll call it one. */ \ + if (TARGET_64BIT && GET_MODE (X) == DImode \ + && GET_MODE (XEXP (X, 0)) == SImode) \ + return COSTS_N_INSNS (1); \ + else \ + return COSTS_N_INSNS (2); \ + \ + case ZERO_EXTEND: \ + if (TARGET_64BIT && GET_MODE (X) == DImode \ + && GET_MODE (XEXP (X, 0)) == SImode) \ + return COSTS_N_INSNS (2); \ + else \ + return COSTS_N_INSNS (1); + +/* An expression giving the cost of an addressing mode that + contains ADDRESS. If not defined, the cost is computed from the + form of the ADDRESS expression and the `CONST_COSTS' values. + + For most CISC machines, the default cost is a good approximation + of the true cost of the addressing mode. However, on RISC + machines, all instructions normally have the same length and + execution time. Hence all addresses will have equal costs. + + In cases where more than one form of an address is known, the + form with the lowest cost will be used. If multiple forms have + the same, lowest, cost, the one that is the most complex will be + used. + + For example, suppose an address that is equal to the sum of a + register and a constant is used twice in the same basic block. + When this macro is not defined, the address will be computed in + a register and memory references will be indirect through that + register. On machines where the cost of the addressing mode + containing the sum is no higher than that of a simple indirect + reference, this will produce an additional instruction and + possibly require an additional register. Proper specification + of this macro eliminates this overhead for such machines. + + Similar use of this macro is made in strength reduction of loops. + + ADDRESS need not be valid as an address. In such a case, the + cost is not relevant and can be any value; invalid addresses + need not be assigned a different cost. + + On machines where an address involving more than one register is + as cheap as an address computation involving only one register, + defining `ADDRESS_COST' to reflect this can cause two registers + to be live over a region of code where only one would have been + if `ADDRESS_COST' were not defined in that manner. This effect + should be considered in the definition of this macro. + Equivalent costs should probably only be given to addresses with + different numbers of registers on machines with lots of registers. + + This macro will normally either not be defined or be defined as + a constant. */ + +#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR)) + +/* A C expression for the cost of moving data from a register in + class FROM to one in class TO. The classes are expressed using + the enumeration values such as `GENERAL_REGS'. A value of 2 is + the default; other values are interpreted relative to that. + + It is not required that the cost always equal 2 when FROM is the + same as TO; on some machines it is expensive to move between + registers if they are not general registers. + + If reload sees an insn consisting of a single `set' between two + hard registers, and if `REGISTER_MOVE_COST' applied to their + classes returns a value of 2, reload does not check to ensure + that the constraints of the insn are met. Setting a cost of + other than 2 will allow reload to verify that the constraints are + met. You should do this if the `movM' pattern's constraints do + not allow such copying. + + ??? We make make the cost of moving from HI/LO/HILO/MD into general + registers the same as for one of moving general registers to + HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a + pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it + isn't clear if it is wise. And it might not work in all cases. We + could solve the DImode LO reg problem by using a multiply, just like + reload_{in,out}si. We could solve the SImode/HImode HI reg problem + by using divide instructions. divu puts the remainder in the HI + reg, so doing a divide by -1 will move the value in the HI reg for + all values except -1. We could handle that case by using a signed + divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a + compare/branch to test the input value to see which instruction we + need to use. This gets pretty messy, but it is feasible. */ + +#define REGISTER_MOVE_COST(FROM, TO) \ + ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \ + : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \ + : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \ + : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \ + : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \ + : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \ + : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \ + : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \ + : (((FROM) == HI_REG || (FROM) == LO_REG \ + || (FROM) == MD_REGS || (FROM) == HILO_REG) \ + && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \ + : (((FROM) == HI_REG || (FROM) == LO_REG \ + || (FROM) == MD_REGS || (FROM) == HILO_REG) \ + && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \ + : (((TO) == HI_REG || (TO) == LO_REG \ + || (TO) == MD_REGS || (TO) == HILO_REG) \ + && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \ + : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \ + : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \ + : 12) + +/* ??? Fix this to be right for the R8000. */ +#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ + (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \ + + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) + +/* Define if copies to/from condition code registers should be avoided. + + This is needed for the MIPS because reload_outcc is not complete; + it needs to handle cases where the source is a general or another + condition code register. */ +#define AVOID_CCMODE_COPIES + +/* A C expression for the cost of a branch instruction. A value of + 1 is the default; other values are interpreted relative to that. */ + +/* ??? Fix this to be right for the R8000. */ +#define BRANCH_COST \ + ((! TARGET_MIPS16 \ + && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \ + ? 2 : 1) + +/* A C statement (sans semicolon) to update the integer variable COST + based on the relationship between INSN that is dependent on + DEP_INSN through the dependence LINK. The default is to make no + adjustment to COST. On the MIPS, ignore the cost of anti- and + output-dependencies. */ + +#define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ + if (REG_NOTE_KIND (LINK) != 0) \ + (COST) = 0; /* Anti or output dependence. */ + +/* Optionally define this if you have added predicates to + `MACHINE.c'. This macro is called within an initializer of an + array of structures. The first field in the structure is the + name of a predicate and the second field is an array of rtl + codes. For each predicate, list all rtl codes that can be in + expressions matched by the predicate. The list should have a + trailing comma. Here is an example of two entries in the list + for a typical RISC machine: + + #define PREDICATE_CODES \ + {"gen_reg_rtx_operand", {SUBREG, REG}}, \ + {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}}, + + Defining this macro does not affect the generated code (however, + incorrect definitions that omit an rtl code that may be matched + by the predicate can cause the compiler to malfunction). + Instead, it allows the table built by `genrecog' to be more + compact and efficient, thus speeding up the compiler. The most + important predicates to include in the list specified by this + macro are thoses used in the most insn patterns. */ + +#define PREDICATE_CODES \ + {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \ + {"arith_operand", { REG, CONST_INT, SUBREG }}, \ + {"arith32_operand", { REG, CONST_INT, SUBREG }}, \ + {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \ + {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \ + {"small_int", { CONST_INT }}, \ + {"large_int", { CONST_INT }}, \ + {"mips_const_double_ok", { CONST_DOUBLE }}, \ + {"const_float_1_operand", { CONST_DOUBLE }}, \ + {"simple_memory_operand", { MEM, SUBREG }}, \ + {"equality_op", { EQ, NE }}, \ + {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \ + LTU, LEU }}, \ + {"pc_or_label_operand", { PC, LABEL_REF }}, \ + {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \ + {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \ + SYMBOL_REF, LABEL_REF, SUBREG, \ + REG, MEM}}, \ + {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \ + SYMBOL_REF, LABEL_REF, SUBREG, REG, \ + MEM, SIGN_EXTEND }}, \ + {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \ + {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \ + SIGN_EXTEND }}, \ + {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \ + SIGN_EXTEND }}, \ + {"se_arith_operand", { REG, CONST_INT, SUBREG, \ + SIGN_EXTEND }}, \ + {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \ + SYMBOL_REF, LABEL_REF, SUBREG, \ + REG, SIGN_EXTEND }}, \ + {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \ + {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \ + CONST_DOUBLE, CONST }}, \ + {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \ + {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }}, + + + +/* If defined, a C statement to be executed just prior to the + output of assembler code for INSN, to modify the extracted + operands so they will be output differently. + + Here the argument OPVEC is the vector containing the operands + extracted from INSN, and NOPERANDS is the number of elements of + the vector which contain meaningful data for this insn. The + contents of this vector are what will be used to convert the + insn template into assembler code, so you can change the + assembler output by changing the contents of the vector. + + We use it to check if the current insn needs a nop in front of it + because of load delays, and also to update the delay slot + statistics. */ + +#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ + final_prescan_insn (INSN, OPVEC, NOPERANDS) + + +/* Control the assembler format that we output. */ + +/* Output at beginning of assembler file. + If we are optimizing to use the global pointer, create a temporary + file to hold all of the text stuff, and write it out to the end. + This is needed because the MIPS assembler is evidently one pass, + and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata + declaration when the code is processed, it generates a two + instruction sequence. */ + +#define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM) + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON " #APP\n" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF " #NO_APP\n" + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). + + In order to support the two different conventions for register names, + we use the name of a table set up in mips.c, which is overwritten + if -mrnames is used. */ + +#define REGISTER_NAMES \ +{ \ + &mips_reg_names[ 0][0], \ + &mips_reg_names[ 1][0], \ + &mips_reg_names[ 2][0], \ + &mips_reg_names[ 3][0], \ + &mips_reg_names[ 4][0], \ + &mips_reg_names[ 5][0], \ + &mips_reg_names[ 6][0], \ + &mips_reg_names[ 7][0], \ + &mips_reg_names[ 8][0], \ + &mips_reg_names[ 9][0], \ + &mips_reg_names[10][0], \ + &mips_reg_names[11][0], \ + &mips_reg_names[12][0], \ + &mips_reg_names[13][0], \ + &mips_reg_names[14][0], \ + &mips_reg_names[15][0], \ + &mips_reg_names[16][0], \ + &mips_reg_names[17][0], \ + &mips_reg_names[18][0], \ + &mips_reg_names[19][0], \ + &mips_reg_names[20][0], \ + &mips_reg_names[21][0], \ + &mips_reg_names[22][0], \ + &mips_reg_names[23][0], \ + &mips_reg_names[24][0], \ + &mips_reg_names[25][0], \ + &mips_reg_names[26][0], \ + &mips_reg_names[27][0], \ + &mips_reg_names[28][0], \ + &mips_reg_names[29][0], \ + &mips_reg_names[30][0], \ + &mips_reg_names[31][0], \ + &mips_reg_names[32][0], \ + &mips_reg_names[33][0], \ + &mips_reg_names[34][0], \ + &mips_reg_names[35][0], \ + &mips_reg_names[36][0], \ + &mips_reg_names[37][0], \ + &mips_reg_names[38][0], \ + &mips_reg_names[39][0], \ + &mips_reg_names[40][0], \ + &mips_reg_names[41][0], \ + &mips_reg_names[42][0], \ + &mips_reg_names[43][0], \ + &mips_reg_names[44][0], \ + &mips_reg_names[45][0], \ + &mips_reg_names[46][0], \ + &mips_reg_names[47][0], \ + &mips_reg_names[48][0], \ + &mips_reg_names[49][0], \ + &mips_reg_names[50][0], \ + &mips_reg_names[51][0], \ + &mips_reg_names[52][0], \ + &mips_reg_names[53][0], \ + &mips_reg_names[54][0], \ + &mips_reg_names[55][0], \ + &mips_reg_names[56][0], \ + &mips_reg_names[57][0], \ + &mips_reg_names[58][0], \ + &mips_reg_names[59][0], \ + &mips_reg_names[60][0], \ + &mips_reg_names[61][0], \ + &mips_reg_names[62][0], \ + &mips_reg_names[63][0], \ + &mips_reg_names[64][0], \ + &mips_reg_names[65][0], \ + &mips_reg_names[66][0], \ + &mips_reg_names[67][0], \ + &mips_reg_names[68][0], \ + &mips_reg_names[69][0], \ + &mips_reg_names[70][0], \ + &mips_reg_names[71][0], \ + &mips_reg_names[72][0], \ + &mips_reg_names[73][0], \ + &mips_reg_names[74][0], \ + &mips_reg_names[75][0], \ +} + +/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c. + So define this for it. */ +#define DEBUG_REGISTER_NAMES \ +{ \ + "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ + "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \ + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ + "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ + "$fcc5","$fcc6","$fcc7","$rap" \ +} + +/* If defined, a C initializer for an array of structures + containing a name and a register number. This macro defines + additional names for hard registers, thus allowing the `asm' + option in declarations to refer to registers using alternate + names. + + We define both names for the integer registers here. */ + +#define ADDITIONAL_REGISTER_NAMES \ +{ \ + { "$0", 0 + GP_REG_FIRST }, \ + { "$1", 1 + GP_REG_FIRST }, \ + { "$2", 2 + GP_REG_FIRST }, \ + { "$3", 3 + GP_REG_FIRST }, \ + { "$4", 4 + GP_REG_FIRST }, \ + { "$5", 5 + GP_REG_FIRST }, \ + { "$6", 6 + GP_REG_FIRST }, \ + { "$7", 7 + GP_REG_FIRST }, \ + { "$8", 8 + GP_REG_FIRST }, \ + { "$9", 9 + GP_REG_FIRST }, \ + { "$10", 10 + GP_REG_FIRST }, \ + { "$11", 11 + GP_REG_FIRST }, \ + { "$12", 12 + GP_REG_FIRST }, \ + { "$13", 13 + GP_REG_FIRST }, \ + { "$14", 14 + GP_REG_FIRST }, \ + { "$15", 15 + GP_REG_FIRST }, \ + { "$16", 16 + GP_REG_FIRST }, \ + { "$17", 17 + GP_REG_FIRST }, \ + { "$18", 18 + GP_REG_FIRST }, \ + { "$19", 19 + GP_REG_FIRST }, \ + { "$20", 20 + GP_REG_FIRST }, \ + { "$21", 21 + GP_REG_FIRST }, \ + { "$22", 22 + GP_REG_FIRST }, \ + { "$23", 23 + GP_REG_FIRST }, \ + { "$24", 24 + GP_REG_FIRST }, \ + { "$25", 25 + GP_REG_FIRST }, \ + { "$26", 26 + GP_REG_FIRST }, \ + { "$27", 27 + GP_REG_FIRST }, \ + { "$28", 28 + GP_REG_FIRST }, \ + { "$29", 29 + GP_REG_FIRST }, \ + { "$30", 30 + GP_REG_FIRST }, \ + { "$31", 31 + GP_REG_FIRST }, \ + { "$sp", 29 + GP_REG_FIRST }, \ + { "$fp", 30 + GP_REG_FIRST }, \ + { "at", 1 + GP_REG_FIRST }, \ + { "v0", 2 + GP_REG_FIRST }, \ + { "v1", 3 + GP_REG_FIRST }, \ + { "a0", 4 + GP_REG_FIRST }, \ + { "a1", 5 + GP_REG_FIRST }, \ + { "a2", 6 + GP_REG_FIRST }, \ + { "a3", 7 + GP_REG_FIRST }, \ + { "t0", 8 + GP_REG_FIRST }, \ + { "t1", 9 + GP_REG_FIRST }, \ + { "t2", 10 + GP_REG_FIRST }, \ + { "t3", 11 + GP_REG_FIRST }, \ + { "t4", 12 + GP_REG_FIRST }, \ + { "t5", 13 + GP_REG_FIRST }, \ + { "t6", 14 + GP_REG_FIRST }, \ + { "t7", 15 + GP_REG_FIRST }, \ + { "s0", 16 + GP_REG_FIRST }, \ + { "s1", 17 + GP_REG_FIRST }, \ + { "s2", 18 + GP_REG_FIRST }, \ + { "s3", 19 + GP_REG_FIRST }, \ + { "s4", 20 + GP_REG_FIRST }, \ + { "s5", 21 + GP_REG_FIRST }, \ + { "s6", 22 + GP_REG_FIRST }, \ + { "s7", 23 + GP_REG_FIRST }, \ + { "t8", 24 + GP_REG_FIRST }, \ + { "t9", 25 + GP_REG_FIRST }, \ + { "k0", 26 + GP_REG_FIRST }, \ + { "k1", 27 + GP_REG_FIRST }, \ + { "gp", 28 + GP_REG_FIRST }, \ + { "sp", 29 + GP_REG_FIRST }, \ + { "fp", 30 + GP_REG_FIRST }, \ + { "ra", 31 + GP_REG_FIRST }, \ + { "$sp", 29 + GP_REG_FIRST }, \ + { "$fp", 30 + GP_REG_FIRST } \ +} + +/* Define results of standard character escape sequences. */ +#define TARGET_BELL 007 +#define TARGET_BS 010 +#define TARGET_TAB 011 +#define TARGET_NEWLINE 012 +#define TARGET_VT 013 +#define TARGET_FF 014 +#define TARGET_CR 015 + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand X. X is an RTL + expression. + + CODE is a value that can be used to specify one of several ways + of printing the operand. It is used when identical operands + must be printed differently depending on the context. CODE + comes from the `%' specification that was used to request + printing of the operand. If the specification was just `%DIGIT' + then CODE is 0; if the specification was `%LTR DIGIT' then CODE + is the ASCII code for LTR. + + If X is a register, this macro should print the register's name. + The names can be found in an array `reg_names' whose type is + `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. + + When the machine description has a specification `%PUNCT' (a `%' + followed by a punctuation character), this macro is called with + a null pointer for X and the punctuation character for CODE. + + See mips.c for the MIPS specific codes. */ + +#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) + +/* A C expression which evaluates to true if CODE is a valid + punctuation character for use in the `PRINT_OPERAND' macro. If + `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no + punctuation characters (except for the standard one, `%') are + used in this way. */ + +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE] + +/* A C compound statement to output to stdio stream STREAM the + assembler syntax for an instruction operand that is a memory + reference whose address is ADDR. ADDR is an RTL expression. + + On some machines, the syntax for a symbolic address depends on + the section that the address refers to. On these machines, + define the macro `ENCODE_SECTION_INFO' to store the information + into the `symbol_ref', and then check for it here. */ + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) + + +/* A C statement, to be executed after all slot-filler instructions + have been output. If necessary, call `dbr_sequence_length' to + determine the number of slots filled in a sequence (zero if not + currently outputting a sequence), to decide how many no-ops to + output, or whatever. + + Don't define this macro if it has nothing to do, but it is + helpful in reading assembly output if the extent of the delay + sequence is made explicit (e.g. with white space). + + Note that output routines for instructions with delay slots must + be prepared to deal with not being output as part of a sequence + (i.e. when the scheduling pass is not run, or when no slot + fillers could be found.) The variable `final_sequence' is null + when not processing a sequence, otherwise it contains the + `sequence' rtx being output. */ + +#define DBR_OUTPUT_SEQEND(STREAM) \ +do \ + { \ + if (set_nomacro > 0 && --set_nomacro == 0) \ + fputs ("\t.set\tmacro\n", STREAM); \ + \ + if (set_noreorder > 0 && --set_noreorder == 0) \ + fputs ("\t.set\treorder\n", STREAM); \ + \ + dslots_jump_filled++; \ + fputs ("\n", STREAM); \ + } \ +while (0) + + +/* How to tell the debugger about changes of source files. Note, the + mips ECOFF format cannot deal with changes of files inside of + functions, which means the output of parser generators like bison + is generally not debuggable without using the -l switch. Lose, + lose, lose. Silicon graphics seems to want all .file's hardwired + to 1. */ + +#ifndef SET_FILE_NUMBER +#define SET_FILE_NUMBER() ++num_source_filenames +#endif + +#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ + mips_output_filename (STREAM, NAME) + +/* This is defined so that it can be overridden in iris6.h. */ +#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \ +do \ + { \ + fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \ + output_quoted_string (STREAM, NAME); \ + fputs ("\n", STREAM); \ + } \ +while (0) + +/* This is how to output a note the debugger telling it the line number + to which the following sequence of instructions corresponds. + Silicon graphics puts a label after each .loc. */ + +#ifndef LABEL_AFTER_LOC +#define LABEL_AFTER_LOC(STREAM) +#endif + +#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \ + mips_output_lineno (STREAM, LINE) + +/* The MIPS implementation uses some labels for its own purpose. The + following lists what labels are created, and are all formed by the + pattern $L[a-z].*. The machine independent portion of GCC creates + labels matching: $L[A-Z][0-9]+ and $L[0-9]+. + + LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. + $Lb[0-9]+ Begin blocks for MIPS debug support + $Lc[0-9]+ Label for use in s<xx> operation. + $Le[0-9]+ End blocks for MIPS debug support + $Lp\..+ Half-pic labels. */ + +/* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. + + If we are optimizing the gp, remember that this label has been put + out, so we know not to emit an .extern for it in mips_asm_file_end. + We use one of the common bits in the IDENTIFIER tree node for this, + since those bits seem to be unused, and we don't have any method + of getting the decl nodes from the name. */ + +#define ASM_OUTPUT_LABEL(STREAM,NAME) \ +do { \ + assemble_name (STREAM, NAME); \ + fputs (":\n", STREAM); \ +} while (0) + + +/* A C statement (sans semicolon) to output to the stdio stream + STREAM any text necessary for declaring the name NAME of an + initialized variable which is being defined. This macro must + output the label definition (perhaps using `ASM_OUTPUT_LABEL'). + The argument DECL is the `VAR_DECL' tree node representing the + variable. + + If this macro is not defined, then the variable name is defined + in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */ + +#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ +do \ + { \ + mips_declare_object (STREAM, NAME, "", ":\n", 0); \ + HALF_PIC_DECLARE (NAME); \ + } \ +while (0) + + +/* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + +#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ + do { \ + fputs ("\t.globl\t", STREAM); \ + assemble_name (STREAM, NAME); \ + fputs ("\n", STREAM); \ + } while (0) + +/* This says how to define a global common symbol. */ + +#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ + mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE)) + +/* This says how to define a local common symbol (ie, not visible to + linker). */ + +#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \ + mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE)) + + +/* This says how to output an external. It would be possible not to + output anything and let undefined symbol become external. However + the assembler uses length information on externals to allocate in + data/sdata bss/sbss, thereby saving exec time. */ + +#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ + mips_output_external(STREAM,DECL,NAME) + +/* This says what to print at the end of the assembly file */ +#define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM) + + +/* This is how to declare a function name. The actual work of + emitting the label is moved to function_prologue, so that we can + get the line number correctly emitted before the .ent directive, + and after any .file directives. + + Also, switch files if we are optimizing the global pointer. */ + +#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ +{ \ + extern FILE *asm_out_text_file; \ + if (TARGET_GP_OPT && ! TARGET_MIPS16) \ + { \ + STREAM = asm_out_text_file; \ + /* ??? text_section gets called too soon. If the previous \ + function is in a special section and we're not, we have \ + to switch back to the text section. We can't call \ + text_section again as gcc thinks we're already there. */ \ + /* ??? See varasm.c. There are other things that get output \ + too early, like alignment (before we've switched STREAM). */ \ + if (DECL_SECTION_NAME (DECL) == NULL_TREE) \ + fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \ + } \ + \ + HALF_PIC_DECLARE (NAME); \ +} + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \ + fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) + +/* This is how to output an assembler line defining a `double' constant. */ + +#define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \ + mips_output_double (STREAM, VALUE) + + +/* This is how to output an assembler line defining a `float' constant. */ + +#define ASM_OUTPUT_FLOAT(STREAM,VALUE) \ + mips_output_float (STREAM, VALUE) + + +/* This is how to output an assembler line defining an `int' constant. */ + +#define ASM_OUTPUT_INT(STREAM,VALUE) \ +do { \ + fprintf (STREAM, "\t.word\t"); \ + output_addr_const (STREAM, (VALUE)); \ + fprintf (STREAM, "\n"); \ +} while (0) + +/* Likewise for 64 bit, `char' and `short' constants. */ + +#define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \ +do { \ + if (TARGET_64BIT) \ + { \ + fprintf (STREAM, "\t.dword\t"); \ + if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \ + /* We can't use 'X' for negative numbers, because then we won't \ + get the right value for the upper 32 bits. */ \ + output_addr_const (STREAM, VALUE); \ + else \ + /* We must use 'X', because otherwise LONG_MIN will print as \ + a number that the Irix 6 assembler won't accept. */ \ + print_operand (STREAM, VALUE, 'X'); \ + fprintf (STREAM, "\n"); \ + } \ + else \ + { \ + assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \ + UNITS_PER_WORD, 1); \ + assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \ + UNITS_PER_WORD, 1); \ + } \ +} while (0) + +#define ASM_OUTPUT_SHORT(STREAM,VALUE) \ +{ \ + fprintf (STREAM, "\t.half\t"); \ + output_addr_const (STREAM, (VALUE)); \ + fprintf (STREAM, "\n"); \ +} + +#define ASM_OUTPUT_CHAR(STREAM,VALUE) \ +{ \ + fprintf (STREAM, "\t.byte\t"); \ + output_addr_const (STREAM, (VALUE)); \ + fprintf (STREAM, "\n"); \ +} + +/* This is how to output an assembler line for a numeric constant byte. */ + +#define ASM_OUTPUT_BYTE(STREAM,VALUE) \ + fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE)) + +/* This is how to output an element of a case-vector that is absolute. */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ + fprintf (STREAM, "\t%s\t%sL%d\n", \ + Pmode == DImode ? ".dword" : ".word", \ + LOCAL_LABEL_PREFIX, \ + VALUE) + +/* This is how to output an element of a case-vector that is relative. + This is used for pc-relative code (e.g. when TARGET_ABICALLS or + TARGET_EMBEDDED_PIC). */ + +#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ +do { \ + if (TARGET_MIPS16) \ + fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ + LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ + else if (TARGET_EMBEDDED_PIC) \ + fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \ + Pmode == DImode ? ".dword" : ".word", \ + LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ + else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \ + fprintf (STREAM, "\t%s\t%sL%d\n", \ + Pmode == DImode ? ".gpdword" : ".gpword", \ + LOCAL_LABEL_PREFIX, VALUE); \ + else \ + fprintf (STREAM, "\t%s\t%sL%d\n", \ + Pmode == DImode ? ".dword" : ".word", \ + LOCAL_LABEL_PREFIX, VALUE); \ +} while (0) + +/* When generating embedded PIC or mips16 code we want to put the jump + table in the .text section. In all other cases, we want to put the + jump table in the .rdata section. Unfortunately, we can't use + JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional. + Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text + section if appropriate. */ +#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \ +do { \ + if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \ + function_section (current_function_decl); \ + ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ +} while (0) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(STREAM,LOG) \ + fprintf (STREAM, "\t.align\t%d\n", (LOG)) + +/* This is how to output an assembler line to advance the location + counter by SIZE bytes. */ + +#define ASM_OUTPUT_SKIP(STREAM,SIZE) \ + fprintf (STREAM, "\t.space\t%u\n", (SIZE)) + +/* This is how to output a string. */ +#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \ +do { \ + register int i, c, len = (LEN), cur_pos = 17; \ + register unsigned char *string = (unsigned char *)(STRING); \ + fprintf ((STREAM), "\t.ascii\t\""); \ + for (i = 0; i < len; i++) \ + { \ + register int c = string[i]; \ + \ + switch (c) \ + { \ + case '\"': \ + case '\\': \ + putc ('\\', (STREAM)); \ + putc (c, (STREAM)); \ + cur_pos += 2; \ + break; \ + \ + case TARGET_NEWLINE: \ + fputs ("\\n", (STREAM)); \ + if (i+1 < len \ + && (((c = string[i+1]) >= '\040' && c <= '~') \ + || c == TARGET_TAB)) \ + cur_pos = 32767; /* break right here */ \ + else \ + cur_pos += 2; \ + break; \ + \ + case TARGET_TAB: \ + fputs ("\\t", (STREAM)); \ + cur_pos += 2; \ + break; \ + \ + case TARGET_FF: \ + fputs ("\\f", (STREAM)); \ + cur_pos += 2; \ + break; \ + \ + case TARGET_BS: \ + fputs ("\\b", (STREAM)); \ + cur_pos += 2; \ + break; \ + \ + case TARGET_CR: \ + fputs ("\\r", (STREAM)); \ + cur_pos += 2; \ + break; \ + \ + default: \ + if (c >= ' ' && c < 0177) \ + { \ + putc (c, (STREAM)); \ + cur_pos++; \ + } \ + else \ + { \ + fprintf ((STREAM), "\\%03o", c); \ + cur_pos += 4; \ + } \ + } \ + \ + if (cur_pos > 72 && i+1 < len) \ + { \ + cur_pos = 17; \ + fprintf ((STREAM), "\"\n\t.ascii\t\""); \ + } \ + } \ + fprintf ((STREAM), "\"\n"); \ +} while (0) + +/* Handle certain cpp directives used in header files on sysV. */ +#define SCCS_DIRECTIVE + +/* Output #ident as a in the read-only data section. */ +#define ASM_OUTPUT_IDENT(FILE, STRING) \ +{ \ + char *p = STRING; \ + int size = strlen (p) + 1; \ + rdata_section (); \ + assemble_string (p, size); \ +} + +/* Default to -G 8 */ +#ifndef MIPS_DEFAULT_GVALUE +#define MIPS_DEFAULT_GVALUE 8 +#endif + +/* Define the strings to put out for each section in the object file. */ +#define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ +#define DATA_SECTION_ASM_OP "\t.data" /* large data */ +#define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */ +#define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ +#define READONLY_DATA_SECTION rdata_section +#define SMALL_DATA_SECTION sdata_section + +/* What other sections we support other than the normal .data/.text. */ + +#define EXTRA_SECTIONS in_sdata, in_rdata + +/* Define the additional functions to select our additional sections. */ + +/* on the MIPS it is not a good idea to put constants in the text + section, since this defeats the sdata/data mechanism. This is + especially true when -O is used. In this case an effort is made to + address with faster (gp) register relative addressing, which can + only get at sdata and sbss items (there is no stext !!) However, + if the constant is too large for sdata, and it's readonly, it + will go into the .rdata section. */ + +#define EXTRA_SECTION_FUNCTIONS \ +void \ +sdata_section () \ +{ \ + if (in_section != in_sdata) \ + { \ + fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \ + in_section = in_sdata; \ + } \ +} \ + \ +void \ +rdata_section () \ +{ \ + if (in_section != in_rdata) \ + { \ + fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \ + in_section = in_rdata; \ + } \ +} + +/* Given a decl node or constant node, choose the section to output it in + and select that section. */ + +#define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX) + +#define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC) + + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + +#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ +do \ + { \ + fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \ + TARGET_64BIT ? "dsubu" : "subu", \ + reg_names[STACK_POINTER_REGNUM], \ + reg_names[STACK_POINTER_REGNUM], \ + TARGET_64BIT ? "sd" : "sw", \ + reg_names[REGNO], \ + reg_names[STACK_POINTER_REGNUM]); \ + } \ +while (0) + +#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ +do \ + { \ + if (! set_noreorder) \ + fprintf (STREAM, "\t.set\tnoreorder\n"); \ + \ + dslots_load_total++; \ + dslots_load_filled++; \ + fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ + TARGET_64BIT ? "ld" : "lw", \ + reg_names[REGNO], \ + reg_names[STACK_POINTER_REGNUM], \ + TARGET_64BIT ? "daddu" : "addu", \ + reg_names[STACK_POINTER_REGNUM], \ + reg_names[STACK_POINTER_REGNUM]); \ + \ + if (! set_noreorder) \ + fprintf (STREAM, "\t.set\treorder\n"); \ + } \ +while (0) + +/* Define the parentheses used to group arithmetic operations + in assembler code. */ + +#define ASM_OPEN_PAREN "(" +#define ASM_CLOSE_PAREN ")" + +/* How to start an assembler comment. + The leading space is important (the mips native assembler requires it). */ +#ifndef ASM_COMMENT_START +#define ASM_COMMENT_START " #" +#endif + + +/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for + and mips-tdump.c to print them out. + + These must match the corresponding definitions in gdb/mipsread.c. + Unfortunately, gcc and gdb do not currently share any directories. */ + +#define CODE_MASK 0x8F300 +#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) +#define MIPS_MARK_STAB(code) ((code)+CODE_MASK) +#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) + + +/* Default definitions for size_t and ptrdiff_t. */ + +#ifndef SIZE_TYPE +#define NO_BUILTIN_SIZE_TYPE +#define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int") +#endif + +#ifndef PTRDIFF_TYPE +#define NO_BUILTIN_PTRDIFF_TYPE +#define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int") +#endif + +/* See mips_expand_prologue's use of loadgp for when this should be + true. */ + +#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \ + && mips_abi != ABI_32 \ + && mips_abi != ABI_O64) + +/* In mips16 mode, we need to look through the function to check for + PC relative loads that are out of range. */ +#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X) + +/* We need to use a special set of functions to handle hard floating + point code in mips16 mode. */ + +#ifndef INIT_SUBTARGET_OPTABS +#define INIT_SUBTARGET_OPTABS +#endif + +#define INIT_TARGET_OPTABS \ +do \ + { \ + if (! TARGET_MIPS16 || ! mips16_hard_float) \ + INIT_SUBTARGET_OPTABS; \ + else \ + { \ + add_optab->handlers[(int) SFmode].libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \ + sub_optab->handlers[(int) SFmode].libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \ + smul_optab->handlers[(int) SFmode].libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \ + flodiv_optab->handlers[(int) SFmode].libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \ + \ + eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \ + nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \ + gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \ + gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \ + ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \ + lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \ + \ + floatsisf_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \ + fixsfsi_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \ + \ + if (TARGET_DOUBLE_FLOAT) \ + { \ + add_optab->handlers[(int) DFmode].libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \ + sub_optab->handlers[(int) DFmode].libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \ + smul_optab->handlers[(int) DFmode].libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \ + flodiv_optab->handlers[(int) DFmode].libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \ + \ + extendsfdf2_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \ + truncdfsf2_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \ + \ + eqdf2_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \ + nedf2_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \ + gtdf2_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \ + gedf2_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \ + ltdf2_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \ + ledf2_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \ + \ + floatsidf_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \ + fixdfsi_libfunc = \ + gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \ + } \ + } \ + } \ +while (0) diff --git a/contrib/gcc/config/mips/mips.md b/contrib/gcc/config/mips/mips.md new file mode 100644 index 000000000000..81c5cd38e381 --- /dev/null +++ b/contrib/gcc/config/mips/mips.md @@ -0,0 +1,10442 @@ +;; Mips.md Machine Description for MIPS based processors +;; Contributed by A. Lichnewsky, lich@inria.inria.fr +;; Changes by Michael Meissner, meissner@osf.org +;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and +;; Brendan Eich, brendan@microunity.com. +;; Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc. + +;; This file is part of GNU CC. + +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; ??? Currently does not have define_function_unit support for the R8000. +;; Must include new entries for fmadd in addition to existing entries. + + + +;; .................... +;; +;; Attributes +;; +;; .................... + +;; Classification of each insn. +;; branch conditional branch +;; jump unconditional jump +;; call unconditional call +;; load load instruction(s) +;; store store instruction(s) +;; move data movement within same register set +;; xfer transfer to/from coprocessor +;; hilo transfer of hi/lo registers +;; arith integer arithmetic instruction +;; darith double precision integer arithmetic instructions +;; imul integer multiply +;; idiv integer divide +;; icmp integer compare +;; fadd floating point add/subtract +;; fmul floating point multiply +;; fmadd floating point multiply-add +;; fdiv floating point divide +;; fabs floating point absolute value +;; fneg floating point negation +;; fcmp floating point compare +;; fcvt floating point convert +;; fsqrt floating point square root +;; multi multiword sequence (or user asm statements) +;; nop no operation + +(define_attr "type" + "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop" + (const_string "unknown")) + +;; Main data type used by the insn +(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown")) + +;; # instructions (4 bytes each) +(define_attr "length" "" (const_int 1)) + +;; Attribute describing the processor. This attribute must match exactly +;; with the processor_type enumeration in mips.h. + +;; Attribute describing the processor +;; (define_attr "cpu" "default,r3000,r6000,r4000" +;; (const +;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000") +;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000") +;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")] +;; (const_string "default")))) + +;; ??? Fix everything that tests this attribute. +(define_attr "cpu" + "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000" + (const (symbol_ref "mips_cpu_attr"))) + +;; Does the instruction have a mandatory delay slot? +;; The 3900, is (mostly) mips1, but does not have a manditory load delay +;; slot. +(define_attr "dslot" "no,yes" + (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp") + (and (eq_attr "type" "load") + (and (eq (symbol_ref "mips_isa") (const_int 1)) + (and (eq (symbol_ref "mips16") (const_int 0)) + (eq_attr "cpu" "!r3900"))))) + (const_string "yes") + (const_string "no"))) + +;; Attribute defining whether or not we can use the branch-likely instructions + +(define_attr "branch_likely" "no,yes" + (const + (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0)) + (const_string "yes") + (const_string "no")))) + + +;; Describe a user's asm statement. +(define_asm_attributes + [(set_attr "type" "multi")]) + +;; whether or not generating calls to position independent functions +(define_attr "abicalls" "no,yes" + (const (symbol_ref "mips_abicalls_attr"))) + + + +;; ......................... +;; +;; Delay slots, can't describe load/fcmp/xfer delay slots here +;; +;; ......................... + +(define_delay (and (eq_attr "type" "branch") + (eq (symbol_ref "mips16") (const_int 0))) + [(and (eq_attr "dslot" "no") (eq_attr "length" "1")) + (nil) + (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))]) + +(define_delay (eq_attr "type" "jump") + [(and (eq_attr "dslot" "no") (eq_attr "length" "1")) + (nil) + (nil)]) + +(define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no")) + [(and (eq_attr "dslot" "no") (eq_attr "length" "1")) + (nil) + (nil)]) + + + +;; ......................... +;; +;; Functional units +;; +;; ......................... + +; (define_function_unit NAME MULTIPLICITY SIMULTANEITY +; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) + +;; Make the default case (PROCESSOR_DEFAULT) handle the worst case + +(define_function_unit "memory" 1 0 + (and (eq_attr "type" "load") + (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000")) + 3 0) + +(define_function_unit "memory" 1 0 + (and (eq_attr "type" "load") + (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000")) + 2 0) + +(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) + +(define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0) + +(define_function_unit "imuldiv" 1 0 + (eq_attr "type" "hilo") + 1 3) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") + (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000")) + 17 17) + +;; On them mips16, we want to stronly discourage a mult from appearing +;; after an mflo, since that requires explicit nop instructions. We +;; do this by pretending that mflo ties up the function unit for long +;; enough that the scheduler will ignore load stalls and the like when +;; selecting instructions to between the two instructions. + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "hilo") (ne (symbol_ref "mips16") (const_int 0))) + 1 5) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000,r3900")) + 12 12) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600")) + 10 10) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650")) + 4 4) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") + (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100"))) + 1 1) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") + (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100"))) + 4 4) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") + (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000"))) + 5 5) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") + (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300"))) + 8 8) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "imul") + (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000"))) + 9 9) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000")) + 38 38) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900")) + 35 35) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600")) + 42 42) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650")) + 36 36) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000")) + 69 69) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100"))) + 35 35) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100"))) + 67 67) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300"))) + 37 37) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300"))) + 69 69) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000"))) + 36 36) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000"))) + 68 68) + +;; The R4300 does *NOT* have a separate Floating Point Unit, instead +;; the FP hardware is part of the normal ALU circuitry. This means FP +;; instructions affect the pipe-line, and no functional unit +;; parallelism can occur on R4300 processors. To force GCC into coding +;; for only a single functional unit, we force the R4300 FP +;; instructions to be processed in the "imuldiv" unit. + +(define_function_unit "adder" 1 1 + (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")) + 3 0) + +(define_function_unit "adder" 1 1 + (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000")) + 2 0) + +(define_function_unit "adder" 1 1 + (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000")) + 1 0) + +(define_function_unit "adder" 1 1 + (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300")) + 4 0) + +(define_function_unit "adder" 1 1 + (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900")) + 2 0) + +(define_function_unit "adder" 1 1 + (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000")) + 3 0) + +(define_function_unit "adder" 1 1 + (and (eq_attr "type" "fabs,fneg") + (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000")) + 2 0) + +(define_function_unit "adder" 1 1 + (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000")) + 1 0) + +(define_function_unit "mult" 1 1 + (and (eq_attr "type" "fmul") + (and (eq_attr "mode" "SF") + (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000"))) + 7 0) + +(define_function_unit "mult" 1 1 + (and (eq_attr "type" "fmul") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000"))) + 4 0) + +(define_function_unit "mult" 1 1 + (and (eq_attr "type" "fmul") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000"))) + 5 0) + +(define_function_unit "mult" 1 1 + (and (eq_attr "type" "fmul") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650"))) + 8 0) + +(define_function_unit "mult" 1 1 + (and (eq_attr "type" "fmul") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))) + 8 0) + +(define_function_unit "mult" 1 1 + (and (eq_attr "type" "fmul") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000"))) + 5 0) + +(define_function_unit "mult" 1 1 + (and (eq_attr "type" "fmul") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000"))) + 6 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "SF") + (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000"))) + 23 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900"))) + 12 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000"))) + 15 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650"))) + 32 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000"))) + 21 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "DF") + (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300"))) + 36 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900"))) + 19 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000"))) + 16 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fdiv") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650"))) + 61 0) + +;;; ??? Is this number right? +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fsqrt") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000"))) + 54 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fsqrt") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650"))) + 31 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fsqrt") + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000"))) + 21 0) + +;;; ??? Is this number right? +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fsqrt") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000"))) + 112 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fsqrt") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650"))) + 60 0) + +(define_function_unit "divide" 1 1 + (and (eq_attr "type" "fsqrt") + (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000"))) + 36 0) + +;; R4300 FP instruction classes treated as part of the "imuldiv" +;; functional unit: + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300")) + 3 3) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300")) + 1 1) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300"))) + 5 5) +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300"))) + 8 8) + +(define_function_unit "imuldiv" 1 0 + (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt")) + (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300"))) + 29 29) +(define_function_unit "imuldiv" 1 0 + (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt")) + (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300"))) + 58 58) + +;; The following functional units do not use the cpu type, and use +;; much less memory in genattrtab.c. + +;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0) +;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) +;; +;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0) +;; +;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0) +;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0) +;; +;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0) +;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0) +;; +;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0) +;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0) +;; +;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0) +;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0) +;; +;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0) +;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0) +;; +;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0) +;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0) + + +;; +;; .................... +;; +;; ADDITION +;; +;; .................... +;; + +(define_insn "adddf3" + [(set (match_operand:DF 0 "register_operand" "=f") + (plus:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "add.d\\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "addsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (plus:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "add.s\\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_expand "addsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + " +{ + /* The mips16 assembler handles -32768 correctly, and so does gas, + but some other MIPS assemblers think that -32768 needs to be + loaded into a register before it can be added in. */ + if (! TARGET_MIPS16 + && ! TARGET_GAS + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) == -32768) + operands[2] = force_reg (SImode, operands[2]); +}") + +(define_insn "addsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") + (match_operand:SI 2 "arith_operand" "dI")))] + "! TARGET_MIPS16 + && (TARGET_GAS + || GET_CODE (operands[2]) != CONST_INT + || INTVAL (operands[2]) != -32768)" + "addu\\t%0,%z1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +;; For the mips16, we need to recognize stack pointer additions +;; explicitly, since we don't have a constraint for $sp. These insns +;; will be generated by the save_restore_insns functions. + +(define_insn "" + [(set (reg:SI 29) + (plus:SI (reg:SI 29) + (match_operand:SI 0 "small_int" "I")))] + "TARGET_MIPS16" + "addu\\t%$,%$,%0" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (plus:SI (reg:SI 29) + (match_operand:SI 1 "small_int" "I")))] + "TARGET_MIPS16" + "addu\\t%0,%$,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_uimm8_4" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (plus:SI (match_operand:SI 1 "register_operand" "0,d,d") + (match_operand:SI 2 "arith_operand" "IQ,O,d")))] + "TARGET_MIPS16 + && (GET_CODE (operands[1]) != REG + || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER + || M16_REG_P (REGNO (operands[1])) + || REGNO (operands[1]) == ARG_POINTER_REGNUM + || REGNO (operands[1]) == FRAME_POINTER_REGNUM + || REGNO (operands[1]) == STACK_POINTER_REGNUM) + && (GET_CODE (operands[2]) != REG + || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER + || M16_REG_P (REGNO (operands[2])) + || REGNO (operands[2]) == ARG_POINTER_REGNUM + || REGNO (operands[2]) == FRAME_POINTER_REGNUM + || REGNO (operands[2]) == STACK_POINTER_REGNUM)" + "* +{ + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"addu\\t%0,%2\"; + return \"addu\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 2 "m16_simm4_1" "") + (const_int 1) + (const_int 2)) + (const_int 1)])]) + + +;; On the mips16, we can sometimes split an add of a constant which is +;; a 4 byte instruction into two adds which are both 2 byte +;; instructions. There are two cases: one where we are adding a +;; constant plus a register to another register, and one where we are +;; simply adding a constant to a register. + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand" "")))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && ((INTVAL (operands[1]) > 0x7f + && INTVAL (operands[1]) <= 0x7f + 0x7f) + || (INTVAL (operands[1]) < - 0x80 + && INTVAL (operands[1]) >= - 0x80 - 0x80))" + [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (val >= 0) + { + operands[1] = GEN_INT (0x7f); + operands[2] = GEN_INT (val - 0x7f); + } + else + { + operands[1] = GEN_INT (- 0x80); + operands[2] = GEN_INT (val + 0x80); + } +}") + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG + && M16_REG_P (REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1]) + && GET_CODE (operands[2]) == CONST_INT + && ((INTVAL (operands[2]) > 0x7 + && INTVAL (operands[2]) <= 0x7 + 0x7f) + || (INTVAL (operands[2]) < - 0x8 + && INTVAL (operands[2]) >= - 0x8 - 0x80))" + [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[2]); + + if (val >= 0) + { + operands[2] = GEN_INT (0x7); + operands[3] = GEN_INT (val - 0x7); + } + else + { + operands[2] = GEN_INT (- 0x8); + operands[3] = GEN_INT (val + 0x8); + } +}") + +(define_expand "adddi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:DI 2 "se_arith_operand" ""))) + (clobber (match_dup 3))])] + "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)" + " +{ + /* The mips16 assembler handles -32768 correctly, and so does gas, + but some other MIPS assemblers think that -32768 needs to be + loaded into a register before it can be added in. */ + if (! TARGET_MIPS16 + && ! TARGET_GAS + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) == -32768) + operands[2] = force_reg (DImode, operands[2]); + + if (TARGET_64BIT) + { + emit_insn (gen_adddi3_internal_3 (operands[0], operands[1], + operands[2])); + DONE; + } + + operands[3] = gen_reg_rtx (SImode); +}") + +(define_insn "adddi3_internal_1" + [(set (match_operand:DI 0 "register_operand" "=d,&d") + (plus:DI (match_operand:DI 1 "register_operand" "0,d") + (match_operand:DI 2 "register_operand" "d,d"))) + (clobber (match_operand:SI 3 "register_operand" "=d,d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" + "* +{ + return (REGNO (operands[0]) == REGNO (operands[1]) + && REGNO (operands[0]) == REGNO (operands[2])) + ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\" + : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2])) + && (REGNO (operands[0]) != REGNO (operands[1]) + || REGNO (operands[0]) != REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 0) + (plus:SI (subreg:SI (match_dup 1) 0) + (subreg:SI (match_dup 2) 0))) + + (set (match_dup 3) + (ltu:SI (subreg:SI (match_dup 0) 0) + (subreg:SI (match_dup 2) 0))) + + (set (subreg:SI (match_dup 0) 1) + (plus:SI (subreg:SI (match_dup 1) 1) + (subreg:SI (match_dup 2) 1))) + + (set (subreg:SI (match_dup 0) 1) + (plus:SI (subreg:SI (match_dup 0) 1) + (match_dup 3)))] + "") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2])) + && (REGNO (operands[0]) != REGNO (operands[1]) + || REGNO (operands[0]) != REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 1) + (plus:SI (subreg:SI (match_dup 1) 1) + (subreg:SI (match_dup 2) 1))) + + (set (match_dup 3) + (ltu:SI (subreg:SI (match_dup 0) 1) + (subreg:SI (match_dup 2) 1))) + + (set (subreg:SI (match_dup 0) 0) + (plus:SI (subreg:SI (match_dup 1) 0) + (subreg:SI (match_dup 2) 0))) + + (set (subreg:SI (match_dup 0) 0) + (plus:SI (subreg:SI (match_dup 0) 0) + (match_dup 3)))] + "") + +(define_insn "adddi3_internal_2" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d") + (match_operand:DI 2 "small_int" "P,J,N"))) + (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && (TARGET_GAS + || GET_CODE (operands[2]) != CONST_INT + || INTVAL (operands[2]) != -32768)" + "@ + addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3 + move\\t%L0,%L1\;move\\t%M0,%M1 + subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "3,2,4")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && INTVAL (operands[2]) > 0" + + [(set (subreg:SI (match_dup 0) 0) + (plus:SI (subreg:SI (match_dup 1) 0) + (match_dup 2))) + + (set (match_dup 3) + (ltu:SI (subreg:SI (match_dup 0) 0) + (match_dup 2))) + + (set (subreg:SI (match_dup 0) 1) + (plus:SI (subreg:SI (match_dup 1) 1) + (match_dup 3)))] + "") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && INTVAL (operands[2]) > 0" + + [(set (subreg:SI (match_dup 0) 1) + (plus:SI (subreg:SI (match_dup 1) 1) + (match_dup 2))) + + (set (match_dup 3) + (ltu:SI (subreg:SI (match_dup 0) 1) + (match_dup 2))) + + (set (subreg:SI (match_dup 0) 0) + (plus:SI (subreg:SI (match_dup 1) 0) + (match_dup 3)))] + "") + +(define_insn "adddi3_internal_3" + [(set (match_operand:DI 0 "register_operand" "=d") + (plus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ") + (match_operand:DI 2 "se_arith_operand" "dI")))] + "TARGET_64BIT + && !TARGET_MIPS16 + && (TARGET_GAS + || GET_CODE (operands[2]) != CONST_INT + || INTVAL (operands[2]) != -32768)" + "* +{ + return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) + ? \"dsubu\\t%0,%z1,%n2\" + : \"daddu\\t%0,%z1,%2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +;; For the mips16, we need to recognize stack pointer additions +;; explicitly, since we don't have a constraint for $sp. These insns +;; will be generated by the save_restore_insns functions. + +(define_insn "" + [(set (reg:DI 29) + (plus:DI (reg:DI 29) + (match_operand:DI 0 "small_int" "I")))] + "TARGET_MIPS16 && TARGET_64BIT" + "daddu\\t%$,%$,%0" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (plus:DI (reg:DI 29) + (match_operand:DI 1 "small_int" "I")))] + "TARGET_MIPS16 && TARGET_64BIT" + "daddu\\t%0,%$,%1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_uimm5_4" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (plus:DI (match_operand:DI 1 "register_operand" "0,d,d") + (match_operand:DI 2 "arith_operand" "IQ,O,d")))] + "TARGET_MIPS16 && TARGET_64BIT + && (GET_CODE (operands[1]) != REG + || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER + || M16_REG_P (REGNO (operands[1])) + || REGNO (operands[1]) == ARG_POINTER_REGNUM + || REGNO (operands[1]) == FRAME_POINTER_REGNUM + || REGNO (operands[1]) == STACK_POINTER_REGNUM) + && (GET_CODE (operands[2]) != REG + || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER + || M16_REG_P (REGNO (operands[2])) + || REGNO (operands[2]) == ARG_POINTER_REGNUM + || REGNO (operands[2]) == FRAME_POINTER_REGNUM + || REGNO (operands[2]) == STACK_POINTER_REGNUM)" + "* +{ + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"daddu\\t%0,%2\"; + return \"daddu\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(if_then_else (match_operand:VOID 2 "m16_simm5_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 2 "m16_simm4_1" "") + (const_int 1) + (const_int 2)) + (const_int 1)])]) + + +;; On the mips16, we can sometimes split an add of a constant which is +;; a 4 byte instruction into two adds which are both 2 byte +;; instructions. There are two cases: one where we are adding a +;; constant plus a register to another register, and one where we are +;; simply adding a constant to a register. + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_dup 0) + (match_operand:DI 1 "const_int_operand" "")))] + "TARGET_MIPS16 && TARGET_64BIT && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && ((INTVAL (operands[1]) > 0xf + && INTVAL (operands[1]) <= 0xf + 0xf) + || (INTVAL (operands[1]) < - 0x10 + && INTVAL (operands[1]) >= - 0x10 - 0x10))" + [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (val >= 0) + { + operands[1] = GEN_INT (0xf); + operands[2] = GEN_INT (val - 0xf); + } + else + { + operands[1] = GEN_INT (- 0x10); + operands[2] = GEN_INT (val + 0x10); + } +}") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "const_int_operand" "")))] + "TARGET_MIPS16 && TARGET_64BIT && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG + && M16_REG_P (REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1]) + && GET_CODE (operands[2]) == CONST_INT + && ((INTVAL (operands[2]) > 0x7 + && INTVAL (operands[2]) <= 0x7 + 0xf) + || (INTVAL (operands[2]) < - 0x8 + && INTVAL (operands[2]) >= - 0x8 - 0x10))" + [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[2]); + + if (val >= 0) + { + operands[2] = GEN_INT (0x7); + operands[3] = GEN_INT (val - 0x7); + } + else + { + operands[2] = GEN_INT (- 0x8); + operands[3] = GEN_INT (val + 0x8); + } +}") + +(define_insn "addsi3_internal_2" + [(set (match_operand:DI 0 "register_operand" "=d") + (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") + (match_operand:SI 2 "arith_operand" "dI"))))] + "TARGET_64BIT + && !TARGET_MIPS16 + && (TARGET_GAS + || GET_CODE (operands[2]) != CONST_INT + || INTVAL (operands[2]) != -32768)" + "* +{ + return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) + ? \"subu\\t%0,%z1,%n2\" + : \"addu\\t%0,%z1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "0,d,d") + (match_operand:SI 2 "arith_operand" "I,O,d"))))] + "TARGET_MIPS16 && TARGET_64BIT" + "* +{ + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"addu\\t%0,%2\"; + return \"addu\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 2 "m16_simm4_1" "") + (const_int 1) + (const_int 2)) + (const_int 1)])]) + + +;; +;; .................... +;; +;; SUBTRACTION +;; +;; .................... +;; + +(define_insn "subdf3" + [(set (match_operand:DF 0 "register_operand" "=f") + (minus:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "sub.d\\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "subsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (minus:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "sub.s\\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_expand "subsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + " +{ + if (GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) == -32768 + || (TARGET_MIPS16 + && INTVAL (operands[2]) == -0x4000))) + operands[2] = force_reg (SImode, operands[2]); +}") + +(define_insn "subsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=d") + (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") + (match_operand:SI 2 "arith_operand" "dI")))] + "!TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" + "subu\\t%0,%z1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +;; For the mips16, we need to recognize stack pointer subtractions +;; explicitly, since we don't have a constraint for $sp. These insns +;; will be generated by the save_restore_insns functions. + +(define_insn "" + [(set (reg:SI 29) + (minus:SI (reg:SI 29) + (match_operand:SI 0 "small_int" "I")))] + "TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" + "addu\\t%$,%$,%n0" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (minus:SI (reg:SI 29) + (match_operand:SI 1 "small_int" "I")))] + "TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" + "addu\\t%0,%$,%n1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_nuimm8_4" "") + (const_int 1) + (const_int 2)))]) + + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (minus:SI (match_operand:SI 1 "register_operand" "0,d,d") + (match_operand:SI 2 "arith_operand" "I,O,d")))] + "TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT + || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))" + "* +{ + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"subu\\t%0,%2\"; + return \"subu\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "") + (const_int 1) + (const_int 2)) + (const_int 1)])]) + +;; On the mips16, we can sometimes split an subtract of a constant +;; which is a 4 byte instruction into two adds which are both 2 byte +;; instructions. There are two cases: one where we are setting a +;; register to a register minus a constant, and one where we are +;; simply subtracting a constant from a register. + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand" "")))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && ((INTVAL (operands[1]) > 0x80 + && INTVAL (operands[1]) <= 0x80 + 0x80) + || (INTVAL (operands[1]) < - 0x7f + && INTVAL (operands[1]) >= - 0x7f - 0x7f))" + [(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (val >= 0) + { + operands[1] = GEN_INT (0x80); + operands[2] = GEN_INT (val - 0x80); + } + else + { + operands[1] = GEN_INT (- 0x7f); + operands[2] = GEN_INT (val + 0x7f); + } +}") + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG + && M16_REG_P (REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1]) + && GET_CODE (operands[2]) == CONST_INT + && ((INTVAL (operands[2]) > 0x8 + && INTVAL (operands[2]) <= 0x8 + 0x80) + || (INTVAL (operands[2]) < - 0x7 + && INTVAL (operands[2]) >= - 0x7 - 0x7f))" + [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 3)))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[2]); + + if (val >= 0) + { + operands[2] = GEN_INT (0x8); + operands[3] = GEN_INT (val - 0x8); + } + else + { + operands[2] = GEN_INT (- 0x7); + operands[3] = GEN_INT (val + 0x7); + } +}") + +(define_expand "subdi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "=d") + (minus:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (clobber (match_dup 3))])] + "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)" + " +{ + if (TARGET_64BIT) + { + emit_insn (gen_subdi3_internal_3 (operands[0], operands[1], + operands[2])); + DONE; + } + + operands[3] = gen_reg_rtx (SImode); +}") + +(define_insn "subdi3_internal" + [(set (match_operand:DI 0 "register_operand" "=d") + (minus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" + "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (match_dup 3) + (ltu:SI (subreg:SI (match_dup 1) 0) + (subreg:SI (match_dup 2) 0))) + + (set (subreg:SI (match_dup 0) 0) + (minus:SI (subreg:SI (match_dup 1) 0) + (subreg:SI (match_dup 2) 0))) + + (set (subreg:SI (match_dup 0) 1) + (minus:SI (subreg:SI (match_dup 1) 1) + (subreg:SI (match_dup 2) 1))) + + (set (subreg:SI (match_dup 0) 1) + (minus:SI (subreg:SI (match_dup 0) 1) + (match_dup 3)))] + "") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (match_dup 3) + (ltu:SI (subreg:SI (match_dup 1) 1) + (subreg:SI (match_dup 2) 1))) + + (set (subreg:SI (match_dup 0) 1) + (minus:SI (subreg:SI (match_dup 1) 1) + (subreg:SI (match_dup 2) 1))) + + (set (subreg:SI (match_dup 0) 0) + (minus:SI (subreg:SI (match_dup 1) 0) + (subreg:SI (match_dup 2) 0))) + + (set (subreg:SI (match_dup 0) 0) + (minus:SI (subreg:SI (match_dup 0) 0) + (match_dup 3)))] + "") + +(define_insn "subdi3_internal_2" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") + (match_operand:DI 2 "small_int" "P,J,N"))) + (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && INTVAL (operands[2]) != -32768" + "@ + sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3 + move\\t%L0,%L1\;move\\t%M0,%M1 + sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "3,2,4")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && INTVAL (operands[2]) > 0" + + [(set (match_dup 3) + (ltu:SI (subreg:SI (match_dup 1) 0) + (match_dup 2))) + + (set (subreg:SI (match_dup 0) 0) + (minus:SI (subreg:SI (match_dup 1) 0) + (match_dup 2))) + + (set (subreg:SI (match_dup 0) 1) + (minus:SI (subreg:SI (match_dup 1) 1) + (match_dup 3)))] + "") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && INTVAL (operands[2]) > 0" + + [(set (match_dup 3) + (ltu:SI (subreg:SI (match_dup 1) 1) + (match_dup 2))) + + (set (subreg:SI (match_dup 0) 1) + (minus:SI (subreg:SI (match_dup 1) 1) + (match_dup 2))) + + (set (subreg:SI (match_dup 0) 0) + (minus:SI (subreg:SI (match_dup 1) 0) + (match_dup 3)))] + "") + +(define_insn "subdi3_internal_3" + [(set (match_operand:DI 0 "register_operand" "=d") + (minus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ") + (match_operand:DI 2 "se_arith_operand" "dI")))] + "TARGET_64BIT && !TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" + "* +{ + return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) + ? \"daddu\\t%0,%z1,%n2\" + : \"dsubu\\t%0,%z1,%2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +;; For the mips16, we need to recognize stack pointer subtractions +;; explicitly, since we don't have a constraint for $sp. These insns +;; will be generated by the save_restore_insns functions. + +(define_insn "" + [(set (reg:DI 29) + (minus:DI (reg:DI 29) + (match_operand:DI 0 "small_int" "I")))] + "TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" + "daddu\\t%$,%$,%n0" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (minus:DI (reg:DI 29) + (match_operand:DI 1 "small_int" "I")))] + "TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" + "daddu\\t%0,%$,%n1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nuimm5_4" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (minus:DI (match_operand:DI 1 "register_operand" "0,d,d") + (match_operand:DI 2 "arith_operand" "I,O,d")))] + "TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT + || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))" + "* +{ + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"dsubu\\t%0,%2\"; + return \"dsubu\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(if_then_else (match_operand:VOID 2 "m16_nsimm5_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "") + (const_int 1) + (const_int 2)) + (const_int 1)])]) + +;; On the mips16, we can sometimes split an add of a constant which is +;; a 4 byte instruction into two adds which are both 2 byte +;; instructions. There are two cases: one where we are adding a +;; constant plus a register to another register, and one where we are +;; simply adding a constant to a register. + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_dup 0) + (match_operand:DI 1 "const_int_operand" "")))] + "TARGET_MIPS16 && TARGET_64BIT && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && ((INTVAL (operands[1]) > 0x10 + && INTVAL (operands[1]) <= 0x10 + 0x10) + || (INTVAL (operands[1]) < - 0xf + && INTVAL (operands[1]) >= - 0xf - 0xf))" + [(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (val >= 0) + { + operands[1] = GEN_INT (0xf); + operands[2] = GEN_INT (val - 0xf); + } + else + { + operands[1] = GEN_INT (- 0x10); + operands[2] = GEN_INT (val + 0x10); + } +}") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "const_int_operand" "")))] + "TARGET_MIPS16 && TARGET_64BIT && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG + && M16_REG_P (REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1]) + && GET_CODE (operands[2]) == CONST_INT + && ((INTVAL (operands[2]) > 0x8 + && INTVAL (operands[2]) <= 0x8 + 0x10) + || (INTVAL (operands[2]) < - 0x7 + && INTVAL (operands[2]) >= - 0x7 - 0xf))" + [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[2]); + + if (val >= 0) + { + operands[2] = GEN_INT (0x8); + operands[3] = GEN_INT (val - 0x8); + } + else + { + operands[2] = GEN_INT (- 0x7); + operands[3] = GEN_INT (val + 0x7); + } +}") + +(define_insn "subsi3_internal_2" + [(set (match_operand:DI 0 "register_operand" "=d") + (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") + (match_operand:SI 2 "arith_operand" "dI"))))] + "TARGET_64BIT && !TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)" + "* +{ + return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) + ? \"addu\\t%0,%z1,%n2\" + : \"subu\\t%0,%z1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (minus:SI (match_operand:SI 1 "register_operand" "0,d,d") + (match_operand:SI 2 "arith_operand" "I,O,d"))))] + "TARGET_64BIT && TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT + || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))" + "* +{ + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"subu\\t%0,%2\"; + return \"subu\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "") + (const_int 1) + (const_int 2)) + (const_int 1)])]) + + + +;; +;; .................... +;; +;; MULTIPLICATION +;; +;; .................... +;; + +;; Early Vr4300 silicon has a CPU bug where multiplies with certain +;; operands may corrupt immediately following multiplies. This is a +;; simple fix to insert NOPs. + +(define_expand "muldf3" + [(set (match_operand:DF 0 "register_operand" "=f") + (mult:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + " +{ + if (mips_cpu != PROCESSOR_R4300) + emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2])); + else + emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2])); + DONE; +}") + +(define_insn "muldf3_internal" + [(set (match_operand:DF 0 "register_operand" "=f") + (mult:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300" + "mul.d\\t%0,%1,%2" + [(set_attr "type" "fmul") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "muldf3_r4300" + [(set (match_operand:DF 0 "register_operand" "=f") + (mult:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300" + "* +{ + output_asm_insn (\"mul.d\\t%0,%1,%2\", operands); + if (TARGET_4300_MUL_FIX) + output_asm_insn (\"nop\", operands); + return \"\"; +}" + [(set_attr "type" "fmul") + (set_attr "mode" "DF") + (set_attr "length" "2")]) ;; mul.d + nop + +(define_expand "mulsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (mult:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + " +{ + if (mips_cpu != PROCESSOR_R4300) + emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2])); + else + emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2])); + DONE; +}") + +(define_insn "mulsf3_internal" + [(set (match_operand:SF 0 "register_operand" "=f") + (mult:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300" + "mul.s\\t%0,%1,%2" + [(set_attr "type" "fmul") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "mulsf3_r4300" + [(set (match_operand:SF 0 "register_operand" "=f") + (mult:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300" + "* +{ + output_asm_insn (\"mul.s\\t%0,%1,%2\", operands); + if (TARGET_4300_MUL_FIX) + output_asm_insn (\"nop\", operands); + return \"\"; +}" + [(set_attr "type" "fmul") + (set_attr "mode" "SF") + (set_attr "length" "2")]) ;; mul.s + nop + + +;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while +;; a multiply is in progress, it may give an incorrect result. Avoid +;; this by keeping the mflo with the mult on the R4000. + +(define_expand "mulsi3" + [(set (match_operand:SI 0 "register_operand" "=l") + (mult:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "" + " +{ + if (HAVE_mulsi3_mult3) + emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2])); + else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16) + emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2])); + else + emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2])); + DONE; +}") + +(define_insn "mulsi3_mult3" + [(set (match_operand:SI 0 "register_operand" "=d,l") + (mult:SI (match_operand:SI 1 "register_operand" "d,d") + (match_operand:SI 2 "register_operand" "d,d"))) + (clobber (match_scratch:SI 3 "=h,h")) + (clobber (match_scratch:SI 4 "=l,X")) + (clobber (match_scratch:SI 5 "=a,a"))] + "GENERATE_MULT3 + || TARGET_MAD" + "* +{ + if (which_alternative == 1) + return \"mult\\t%1,%2\"; + if (TARGET_MAD) + return \"mul\\t%0,%1,%2\"; + return \"mult\\t%0,%1,%2\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "mulsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=l") + (mult:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16" + "mult\\t%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "mulsi3_r4000" + [(set (match_operand:SI 0 "register_operand" "=d") + (mult:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=l")) + (clobber (match_scratch:SI 5 "=a"))] + "mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16" + "* +{ + rtx xoperands[10]; + + xoperands[0] = operands[0]; + xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM); + + output_asm_insn (\"mult\\t%1,%2\", operands); + output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); + return \"\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "3")]) ;; mult + mflo + delay + +;; Multiply-accumulate patterns + +;; For processors that can copy the output to a general register: +;; +;; The all-d alternative is needed because the combiner will find this +;; pattern and then register alloc/reload will move registers around to +;; make them fit, and we don't want to trigger unnecessary loads to LO. +;; +;; The last alternative should be made slightly less desirable, but adding +;; "?" to the constraint is too strong, and causes values to be loaded into +;; LO even when that's more costly. For now, using "*d" mostly does the +;; trick. +(define_insn "*mul_acc_si" + [(set (match_operand:SI 0 "register_operand" "=l,*d,*d") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") + (match_operand:SI 2 "register_operand" "d,d,d")) + (match_operand:SI 3 "register_operand" "0,l,*d"))) + (clobber (match_scratch:SI 4 "=h,h,h")) + (clobber (match_scratch:SI 5 "=X,3,l")) + (clobber (match_scratch:SI 6 "=a,a,a")) + (clobber (match_scratch:SI 7 "=X,X,d"))] + "TARGET_MIPS3900 + && !TARGET_MIPS16" + "* +{ + static const char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" }; + if (which_alternative == 2) + return \"#\"; + return madd[which_alternative]; +}" + [(set_attr "type" "imul,imul,multi") + (set_attr "mode" "SI") + (set_attr "length" "1,1,2")]) + +;; Split the above insn if we failed to get LO allocated. +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "register_operand" "")) + (match_operand:SI 3 "register_operand" ""))) + (clobber (match_scratch:SI 4 "")) + (clobber (match_scratch:SI 5 "")) + (clobber (match_scratch:SI 6 "")) + (clobber (match_scratch:SI 7 ""))] + "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[3]))" + [(parallel [(set (match_dup 7) + (mult:SI (match_dup 1) (match_dup 2))) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (clobber (match_dup 6))]) + (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 3)))] + "") + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_operand:SI 1 "register_operand" "") + (mult:SI (match_operand:SI 2 "register_operand" "") + (match_operand:SI 3 "register_operand" "")))) + (clobber (match_scratch:SI 4 "")) + (clobber (match_scratch:SI 5 "")) + (clobber (match_scratch:SI 6 "")) + (clobber (match_scratch:SI 7 ""))] + "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[1]))" + [(parallel [(set (match_dup 7) + (mult:SI (match_dup 2) (match_dup 3))) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (clobber (match_dup 6))]) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))] + "") + +(define_expand "muldi3" + [(set (match_operand:DI 0 "register_operand" "=l") + (mult:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "register_operand" "d"))) + (clobber (match_scratch:DI 3 "=h")) + (clobber (match_scratch:DI 4 "=a"))] + "TARGET_64BIT" + + " +{ + if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16) + emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2])); + DONE; +}") + +;; Don't accept both operands using se_register_operand, because if +;; both operands are sign extended we would prefer to use mult in the +;; mulsidi3 pattern. Commutativity should permit either operand to be +;; sign extended. + +(define_insn "muldi3_internal" + [(set (match_operand:DI 0 "register_operand" "=l") + (mult:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "register_operand" "d"))) + (clobber (match_scratch:DI 3 "=h")) + (clobber (match_scratch:DI 4 "=a"))] + "TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16" + "dmult\\t%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "muldi3_internal2" + [(set (match_operand:DI 0 "register_operand" "=d") + (mult:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "register_operand" "d"))) + (clobber (match_scratch:DI 3 "=h")) + (clobber (match_scratch:DI 4 "=l")) + (clobber (match_scratch:DI 5 "=a"))] + "TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)" + "* +{ + if (GENERATE_MULT3) + output_asm_insn (\"dmult\\t%0,%1,%2\", operands); + else + { + rtx xoperands[10]; + + xoperands[0] = operands[0]; + xoperands[1] = gen_rtx (REG, DImode, LO_REGNUM); + + output_asm_insn (\"dmult\\t%1,%2\", operands); + output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); + } + return \"\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set (attr "length") + (if_then_else (ne (symbol_ref "GENERATE_MULT3") (const_int 0)) + (const_int 1) + (const_int 3)))]) ;; mult + mflo + delay + +;; ??? We could define a mulditi3 pattern when TARGET_64BIT. + +(define_expand "mulsidi3" + [(set (match_operand:DI 0 "register_operand" "=x") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] + "" + " +{ + rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx); + if (TARGET_64BIT) + emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2], + dummy, dummy)); + else + emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2], + dummy, dummy)); + DONE; +}") + +(define_expand "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=x") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] + "" + " +{ + rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx); + if (TARGET_64BIT) + emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2], + dummy, dummy)); + else + emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2], + dummy, dummy)); + DONE; +}") + +(define_insn "mulsidi3_internal" + [(set (match_operand:DI 0 "register_operand" "=x") + (mult:DI (match_operator:DI 3 "extend_operator" + [(match_operand:SI 1 "register_operand" "d")]) + (match_operator:DI 4 "extend_operator" + [(match_operand:SI 2 "register_operand" "d")]))) + (clobber (match_scratch:SI 5 "=a"))] + "!TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])" + "* +{ + if (GET_CODE (operands[3]) == SIGN_EXTEND) + return \"mult\\t%1,%2\"; + return \"multu\\t%1,%2\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "mulsidi3_64bit" + [(set (match_operand:DI 0 "register_operand" "=a") + (mult:DI (match_operator:DI 3 "extend_operator" + [(match_operand:SI 1 "register_operand" "d")]) + (match_operator:DI 4 "extend_operator" + [(match_operand:SI 2 "register_operand" "d")]))) + (clobber (match_scratch:DI 5 "=l")) + (clobber (match_scratch:DI 6 "=h"))] + "TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])" + "* +{ + if (GET_CODE (operands[3]) == SIGN_EXTEND) + return \"mult\\t%1,%2\"; + return \"multu\\t%1,%2\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +;; _highpart patterns +(define_expand "smulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=h") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))) + (const_int 32))))] + "" + " +{ + rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx); + rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx); +#ifndef NO_MD_PROTOTYPES + rtx (*genfn) PROTO((rtx, rtx, rtx, rtx, rtx, rtx)); +#else + rtx (*genfn) (); +#endif + genfn = gen_xmulsi3_highpart_internal; + emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy, + dummy, dummy2)); + DONE; +}") + +(define_expand "umulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=h") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))) + (const_int 32))))] + "" + " +{ + rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx); + rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx); +#ifndef NO_MD_PROTOTYPES + rtx (*genfn) PROTO((rtx, rtx, rtx, rtx, rtx, rtx)); +#else + rtx (*genfn) (); +#endif + genfn = gen_xmulsi3_highpart_internal; + emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy, + dummy, dummy2)); + DONE; +}") + +(define_insn "xmulsi3_highpart_internal" + [(set (match_operand:SI 0 "register_operand" "=h") + (truncate:SI + (match_operator:DI 5 "highpart_shift_operator" + [(mult:DI (match_operator:DI 3 "extend_operator" + [(match_operand:SI 1 "register_operand" "d")]) + (match_operator:DI 4 "extend_operator" + [(match_operand:SI 2 "register_operand" "d")])) + (const_int 32)]))) + (clobber (match_scratch:SI 6 "=l")) + (clobber (match_scratch:SI 7 "=a"))] + "GET_CODE (operands[3]) == GET_CODE (operands[4])" + "* +{ + if (GET_CODE (operands[3]) == SIGN_EXTEND) + return \"mult\\t%1,%2\"; + else + return \"multu\\t%1,%2\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "smuldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "=h") + (truncate:DI + (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "se_register_operand" "d")) + (sign_extend:TI (match_operand:DI 2 "se_register_operand" "d"))) + (const_int 64)))) + (clobber (match_scratch:DI 3 "=l")) + (clobber (match_scratch:DI 4 "=a"))] + "TARGET_64BIT" + "dmult\\t%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "umuldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "=h") + (truncate:DI + (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "se_register_operand" "d")) + (zero_extend:TI (match_operand:DI 2 "se_register_operand" "d"))) + (const_int 64)))) + (clobber (match_scratch:DI 3 "=l")) + (clobber (match_scratch:DI 4 "=a"))] + "TARGET_64BIT" + "dmultu\\t%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +;; The R4650 supports a 32 bit multiply/ 64 bit accumulate +;; instruction. The HI/LO registers are used as a 64 bit accumulator. + +(define_insn "madsi" + [(set (match_operand:SI 0 "register_operand" "+l") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")) + (match_dup 0))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "TARGET_MAD" + "mad\\t%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "*mul_acc_di" + [(set (match_operand:DI 0 "register_operand" "+x") + (plus:DI (mult:DI (match_operator:DI 3 "extend_operator" + [(match_operand:SI 1 "register_operand" "d")]) + (match_operator:DI 4 "extend_operator" + [(match_operand:SI 2 "register_operand" "d")])) + (match_dup 0))) + (clobber (match_scratch:SI 5 "=a"))] + "TARGET_MAD + && ! TARGET_64BIT + && GET_CODE (operands[3]) == GET_CODE (operands[4])" + "* +{ + if (GET_CODE (operands[3]) == SIGN_EXTEND) + return \"mad\\t%1,%2\"; + else + return \"madu\\t%1,%2\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "*mul_acc_64bit_di" + [(set (match_operand:DI 0 "register_operand" "+a") + (plus:DI (mult:DI (match_operator:DI 3 "extend_operator" + [(match_operand:SI 1 "register_operand" "d")]) + (match_operator:DI 4 "extend_operator" + [(match_operand:SI 2 "register_operand" "d")])) + (match_dup 0))) + (clobber (match_scratch:SI 5 "=h")) + (clobber (match_scratch:SI 6 "=l"))] + "TARGET_MAD + && TARGET_64BIT + && GET_CODE (operands[3]) == GET_CODE (operands[4])" + "* +{ + if (GET_CODE (operands[3]) == SIGN_EXTEND) + return \"mad\\t%1,%2\"; + else + return \"madu\\t%1,%2\"; +}" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +;; Floating point multiply accumulate instructions. + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")) + (match_operand:DF 3 "register_operand" "f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "madd.d\\t%0,%3,%1,%2" + [(set_attr "type" "fmadd") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")) + (match_operand:SF 3 "register_operand" "f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "madd.s\\t%0,%3,%1,%2" + [(set_attr "type" "fmadd") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")) + (match_operand:DF 3 "register_operand" "f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "msub.d\\t%0,%3,%1,%2" + [(set_attr "type" "fmadd") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")) + (match_operand:SF 3 "register_operand" "f")))] + + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "msub.s\\t%0,%3,%1,%2" + [(set_attr "type" "fmadd") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")) + (match_operand:DF 3 "register_operand" "f"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "nmadd.d\\t%0,%3,%1,%2" + [(set_attr "type" "fmadd") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")) + (match_operand:SF 3 "register_operand" "f"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "nmadd.s\\t%0,%3,%1,%2" + [(set_attr "type" "fmadd") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (minus:DF (match_operand:DF 1 "register_operand" "f") + (mult:DF (match_operand:DF 2 "register_operand" "f") + (match_operand:DF 3 "register_operand" "f"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "nmsub.d\\t%0,%1,%2,%3" + [(set_attr "type" "fmadd") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (minus:SF (match_operand:SF 1 "register_operand" "f") + (mult:SF (match_operand:SF 2 "register_operand" "f") + (match_operand:SF 3 "register_operand" "f"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "nmsub.s\\t%0,%1,%2,%3" + [(set_attr "type" "fmadd") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +;; +;; .................... +;; +;; DIVISION and REMAINDER +;; +;; .................... +;; + +(define_insn "divdf3" + [(set (match_operand:DF 0 "register_operand" "=f") + (div:DF (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "div.d\\t%0,%1,%2" + [(set_attr "type" "fdiv") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "divsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (div:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "div.s\\t%0,%1,%2" + [(set_attr "type" "fdiv") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (div:DF (match_operand:DF 1 "const_float_1_operand" "") + (match_operand:DF 2 "register_operand" "f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math" + "recip.d\\t%0,%2" + [(set_attr "type" "fdiv") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (div:SF (match_operand:SF 1 "const_float_1_operand" "") + (match_operand:SF 2 "register_operand" "f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math" + "recip.s\\t%0,%2" + [(set_attr "type" "fdiv") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +;; If optimizing, prefer the divmod functions over separate div and +;; mod functions, since this will allow using one instruction for both +;; the quotient and remainder. At present, the divmod is not moved out +;; of loops if it is constant within the loop, so allow -mdebugc to +;; use the old method of doing things. + +;; 64 is the multiply/divide hi register +;; 65 is the multiply/divide lo register + +;; ??? We can't accept constants here, because the MIPS assembler will replace +;; a divide by power of 2 with a shift, and then the remainder is no longer +;; available. + +(define_expand "divmodsi4" + [(set (match_operand:SI 0 "register_operand" "=d") + (div:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (set (match_operand:SI 3 "register_operand" "=d") + (mod:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:SI 4 "=l")) + (clobber (match_scratch:SI 5 "=h")) + (clobber (match_scratch:SI 6 "=a"))] + "optimize" + " +{ + emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2], + operands[3])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + if (TARGET_CHECK_RANGE_DIV) + { + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (SImode, GEN_INT (-1)), + GEN_INT (0x6))); + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (SImode, GEN_INT (0x80000000)), + GEN_INT (0x6))); + } + + DONE; +}") + +(define_insn "divmodsi4_internal" + [(set (match_operand:SI 0 "register_operand" "=l") + (div:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (set (match_operand:SI 3 "register_operand" "=h") + (mod:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:SI 6 "=a"))] + "optimize" + "div\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "divmoddi4" + [(set (match_operand:DI 0 "register_operand" "=d") + (div:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (set (match_operand:DI 3 "register_operand" "=d") + (mod:DI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:DI 4 "=l")) + (clobber (match_scratch:DI 5 "=h")) + (clobber (match_scratch:DI 6 "=a"))] + "TARGET_64BIT && optimize" + " +{ + emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2], + operands[3])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + if (TARGET_CHECK_RANGE_DIV) + { + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (DImode, GEN_INT (-1)), + GEN_INT (0x6))); + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (DImode, GEN_INT (0x80000000)), + GEN_INT (0x6))); + } + + DONE; +}") + +(define_insn "divmoddi4_internal" + [(set (match_operand:DI 0 "register_operand" "=l") + (div:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (set (match_operand:DI 3 "register_operand" "=h") + (mod:DI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:DI 6 "=a"))] + "TARGET_64BIT && optimize" + "ddiv\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "udivmodsi4" + [(set (match_operand:SI 0 "register_operand" "=d") + (udiv:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (set (match_operand:SI 3 "register_operand" "=d") + (umod:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:SI 4 "=l")) + (clobber (match_scratch:SI 5 "=h")) + (clobber (match_scratch:SI 6 "=a"))] + "optimize" + " +{ + emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2], + operands[3])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + + DONE; +}") + +(define_insn "udivmodsi4_internal" + [(set (match_operand:SI 0 "register_operand" "=l") + (udiv:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (set (match_operand:SI 3 "register_operand" "=h") + (umod:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:SI 6 "=a"))] + "optimize" + "divu\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "udivmoddi4" + [(set (match_operand:DI 0 "register_operand" "=d") + (udiv:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (set (match_operand:DI 3 "register_operand" "=d") + (umod:DI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:DI 4 "=l")) + (clobber (match_scratch:DI 5 "=h")) + (clobber (match_scratch:DI 6 "=a"))] + "TARGET_64BIT && optimize" + " +{ + emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2], + operands[3])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + + DONE; +}") + +(define_insn "udivmoddi4_internal" + [(set (match_operand:DI 0 "register_operand" "=l") + (udiv:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (set (match_operand:DI 3 "register_operand" "=h") + (umod:DI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:DI 6 "=a"))] + "TARGET_64BIT && optimize" + "ddivu\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +;; Division trap + +(define_expand "div_trap" + [(trap_if (eq (match_operand 0 "register_operand" "d") + (match_operand 1 "true_reg_or_0_operand" "dJ")) + (match_operand 2 "immediate_operand" ""))] + "" + " +{ + if (TARGET_MIPS16) + emit_insn (gen_div_trap_mips16 (operands[0],operands[1],operands[2])); + else + emit_insn (gen_div_trap_normal (operands[0],operands[1],operands[2])); + DONE; +}") + +(define_insn "div_trap_normal" + [(trap_if (eq (match_operand 0 "register_operand" "d") + (match_operand 1 "true_reg_or_0_operand" "dJ")) + (match_operand 2 "immediate_operand" ""))] + "!TARGET_MIPS16" + "* +{ + rtx link; + int have_dep_anti = 0; + + /* For divmod if one division is not needed then we don't need an extra + divide by zero trap, which is anti dependent on previous trap */ + for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) + + if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link) + && GET_CODE (XEXP (link, 0)) == INSN + && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF + && REGNO (operands[1]) == 0) + have_dep_anti = 1; + if (! have_dep_anti) + { + if (GENERATE_BRANCHLIKELY) + { + if (GET_CODE (operands[1]) == CONST_INT) + return \"%(beql\\t%0,$0,1f\\n\\tbreak\\t%2\\n1:%)\"; + else + return \"%(beql\\t%0,%1,1f\\n\\tbreak\\t%2\\n1:%)\"; + } + else + { + if (GET_CODE (operands[1]) == CONST_INT) + return \"%(bne\\t%0,$0,1f\\n\\tnop\\n\\tbreak\\t%2\\n1:%)\"; + else + return \"%(bne\\t%0,%1,1f\\n\\tnop\\n\\tbreak\\t%2\\n1:%)\"; + } + } + return \"\"; +}" + [(set_attr "type" "unknown") + (set_attr "length" "3")]) + + +;; The mips16 bne insns is a macro which uses reg 24 as an intermediate. + +(define_insn "div_trap_mips16" + [(trap_if (eq (match_operand 0 "register_operand" "d") + (match_operand 1 "true_reg_or_0_operand" "dJ")) + (match_operand 2 "immediate_operand" "")) + (clobber (reg:SI 24))] + "TARGET_MIPS16" + "* +{ + rtx link; + int have_dep_anti = 0; + + /* For divmod if one division is not needed then we don't need an extra + divide by zero trap, which is anti dependent on previous trap */ + for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) + + if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link) + && GET_CODE (XEXP (link, 0)) == INSN + && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF + && REGNO (operands[1]) == 0) + have_dep_anti = 1; + if (! have_dep_anti) + { + /* No branch delay slots on mips16. */ + if (GET_CODE (operands[1]) == CONST_INT) + return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n1:%)\"; + else + return \"%(bne\\t%0,%1,1f\\n\\tbreak\\t%2\\n1:%)\"; + } + return \"\"; +}" + [(set_attr "type" "unknown") + (set_attr "length" "3")]) + +(define_expand "divsi3" + [(set (match_operand:SI 0 "register_operand" "=l") + (div:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "!optimize" + " +{ + emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + if (TARGET_CHECK_RANGE_DIV) + { + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (SImode, GEN_INT (-1)), + GEN_INT (0x6))); + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (SImode, GEN_INT (0x80000000)), + GEN_INT (0x6))); + } + + DONE; +}") + +(define_insn "divsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=l") + (div:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "nonmemory_operand" "di"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "!optimize" + "div\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "divdi3" + [(set (match_operand:DI 0 "register_operand" "=l") + (div:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (clobber (match_scratch:DI 3 "=h")) + (clobber (match_scratch:DI 4 "=a"))] + "TARGET_64BIT && !optimize" + " +{ + emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + if (TARGET_CHECK_RANGE_DIV) + { + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (DImode, GEN_INT (-1)), + GEN_INT (0x6))); + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (DImode, GEN_INT (0x80000000)), + GEN_INT (0x6))); + } + + DONE; +}") + +(define_insn "divdi3_internal" + [(set (match_operand:DI 0 "register_operand" "=l") + (div:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_nonmemory_operand" "di"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "TARGET_64BIT && !optimize" + "ddiv\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_expand "modsi3" + [(set (match_operand:SI 0 "register_operand" "=h") + (mod:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_scratch:SI 3 "=l")) + (clobber (match_scratch:SI 4 "=a"))] + "!optimize" + " +{ + emit_insn (gen_modsi3_internal (operands[0], operands[1], operands[2])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + if (TARGET_CHECK_RANGE_DIV) + { + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (SImode, GEN_INT (-1)), + GEN_INT (0x6))); + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (SImode, GEN_INT (0x80000000)), + GEN_INT (0x6))); + } + + DONE; +}") + +(define_insn "modsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=h") + (mod:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "nonmemory_operand" "di"))) + (clobber (match_scratch:SI 3 "=l")) + (clobber (match_scratch:SI 4 "=a"))] + "!optimize" + "div\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "moddi3" + [(set (match_operand:DI 0 "register_operand" "=h") + (mod:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (clobber (match_scratch:DI 3 "=l")) + (clobber (match_scratch:DI 4 "=a"))] + "TARGET_64BIT && !optimize" + " +{ + emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + if (TARGET_CHECK_RANGE_DIV) + { + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (DImode, GEN_INT (-1)), + GEN_INT (0x6))); + emit_insn (gen_div_trap (operands[2], + copy_to_mode_reg (DImode, GEN_INT (0x80000000)), + GEN_INT (0x6))); + } + + DONE; +}") + +(define_insn "moddi3_internal" + [(set (match_operand:DI 0 "register_operand" "=h") + (mod:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_nonmemory_operand" "di"))) + (clobber (match_scratch:SI 3 "=l")) + (clobber (match_scratch:SI 4 "=a"))] + "TARGET_64BIT && !optimize" + "ddiv\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_expand "udivsi3" + [(set (match_operand:SI 0 "register_operand" "=l") + (udiv:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "!optimize" + " +{ + emit_insn (gen_udivsi3_internal (operands[0], operands[1], operands[2])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + + DONE; +}") + +(define_insn "udivsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=l") + (udiv:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "nonmemory_operand" "di"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "!optimize" + "divu\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "udivdi3" + [(set (match_operand:DI 0 "register_operand" "=l") + (udiv:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "di"))) + (clobber (match_scratch:DI 3 "=h")) + (clobber (match_scratch:DI 4 "=a"))] + "TARGET_64BIT && !optimize" + " +{ + emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + + DONE; +}") + +(define_insn "udivdi3_internal" + [(set (match_operand:DI 0 "register_operand" "=l") + (udiv:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_nonmemory_operand" "di"))) + (clobber (match_scratch:SI 3 "=h")) + (clobber (match_scratch:SI 4 "=a"))] + "TARGET_64BIT && !optimize" + "ddivu\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_expand "umodsi3" + [(set (match_operand:SI 0 "register_operand" "=h") + (umod:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_scratch:SI 3 "=l")) + (clobber (match_scratch:SI 4 "=a"))] + "!optimize" + " +{ + emit_insn (gen_umodsi3_internal (operands[0], operands[1], operands[2])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + + DONE; +}") + +(define_insn "umodsi3_internal" + [(set (match_operand:SI 0 "register_operand" "=h") + (umod:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "nonmemory_operand" "di"))) + (clobber (match_scratch:SI 3 "=l")) + (clobber (match_scratch:SI 4 "=a"))] + "!optimize" + "divu\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "umoddi3" + [(set (match_operand:DI 0 "register_operand" "=h") + (umod:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "di"))) + (clobber (match_scratch:DI 3 "=l")) + (clobber (match_scratch:DI 4 "=a"))] + "TARGET_64BIT && !optimize" + " +{ + emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2])); + if (!TARGET_NO_CHECK_ZERO_DIV) + { + emit_insn (gen_div_trap (operands[2], + GEN_INT (0), + GEN_INT (0x7))); + } + + DONE; +}") + +(define_insn "umoddi3_internal" + [(set (match_operand:DI 0 "register_operand" "=h") + (umod:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_nonmemory_operand" "di"))) + (clobber (match_scratch:SI 3 "=l")) + (clobber (match_scratch:SI 4 "=a"))] + "TARGET_64BIT && !optimize" + "ddivu\\t$0,%1,%2" + [(set_attr "type" "idiv") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +;; +;; .................... +;; +;; SQUARE ROOT +;; +;; .................... + +(define_insn "sqrtdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (sqrt:DF (match_operand:DF 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT" + "sqrt.d\\t%0,%1" + [(set_attr "type" "fsqrt") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "sqrtsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && HAVE_SQRT_P()" + "sqrt.s\\t%0,%1" + [(set_attr "type" "fsqrt") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (div:DF (match_operand:DF 1 "const_float_1_operand" "") + (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math" + "rsqrt.d\\t%0,%2" + [(set_attr "type" "fsqrt") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (div:SF (match_operand:SF 1 "const_float_1_operand" "") + (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math" + "rsqrt.s\\t%0,%2" + [(set_attr "type" "fsqrt") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + + +;; +;; .................... +;; +;; ABSOLUTE VALUE +;; +;; .................... + +;; Do not use the integer abs macro instruction, since that signals an +;; exception on -2147483648 (sigh). + +(define_insn "abssi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (abs:SI (match_operand:SI 1 "register_operand" "d")))] + "!TARGET_MIPS16" + "* +{ + dslots_jump_total++; + dslots_jump_filled++; + operands[2] = const0_rtx; + + if (REGNO (operands[0]) == REGNO (operands[1])) + { + if (GENERATE_BRANCHLIKELY) + return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n1:%)\"; + else + return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\"; + } + else + return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\"; +}" + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "3")]) + +(define_insn "absdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (abs:DI (match_operand:DI 1 "se_register_operand" "d")))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + dslots_jump_total++; + dslots_jump_filled++; + operands[2] = const0_rtx; + + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\"; + else + return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\"; +}" + [(set_attr "type" "multi") + (set_attr "mode" "DI") + (set_attr "length" "3")]) + +(define_insn "absdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (abs:DF (match_operand:DF 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "abs.d\\t%0,%1" + [(set_attr "type" "fabs") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "abssf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (abs:SF (match_operand:SF 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "abs.s\\t%0,%1" + [(set_attr "type" "fabs") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + + +;; +;; .................... +;; +;; FIND FIRST BIT INSTRUCTION +;; +;; .................... +;; + +(define_insn "ffssi2" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ffs:SI (match_operand:SI 1 "register_operand" "d"))) + (clobber (match_scratch:SI 2 "=&d")) + (clobber (match_scratch:SI 3 "=&d"))] + "!TARGET_MIPS16" + "* +{ + dslots_jump_total += 2; + dslots_jump_filled += 2; + operands[4] = const0_rtx; + + if (optimize && find_reg_note (insn, REG_DEAD, operands[1])) + return \"%(\\ +move\\t%0,%z4\\n\\ +\\tbeq\\t%1,%z4,2f\\n\\ +1:\\tand\\t%2,%1,0x0001\\n\\ +\\taddu\\t%0,%0,1\\n\\ +\\tbeq\\t%2,%z4,1b\\n\\ +\\tsrl\\t%1,%1,1\\n\\ +2:%)\"; + + return \"%(\\ +move\\t%0,%z4\\n\\ +\\tmove\\t%3,%1\\n\\ +\\tbeq\\t%3,%z4,2f\\n\\ +1:\\tand\\t%2,%3,0x0001\\n\\ +\\taddu\\t%0,%0,1\\n\\ +\\tbeq\\t%2,%z4,1b\\n\\ +\\tsrl\\t%3,%3,1\\n\\ +2:%)\"; +}" + [(set_attr "type" "multi") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn "ffsdi2" + [(set (match_operand:DI 0 "register_operand" "=&d") + (ffs:DI (match_operand:DI 1 "se_register_operand" "d"))) + (clobber (match_scratch:DI 2 "=&d")) + (clobber (match_scratch:DI 3 "=&d"))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + dslots_jump_total += 2; + dslots_jump_filled += 2; + operands[4] = const0_rtx; + + if (optimize && find_reg_note (insn, REG_DEAD, operands[1])) + return \"%(\\ +move\\t%0,%z4\\n\\ +\\tbeq\\t%1,%z4,2f\\n\\ +1:\\tand\\t%2,%1,0x0001\\n\\ +\\tdaddu\\t%0,%0,1\\n\\ +\\tbeq\\t%2,%z4,1b\\n\\ +\\tdsrl\\t%1,%1,1\\n\\ +2:%)\"; + + return \"%(\\ +move\\t%0,%z4\\n\\ +\\tmove\\t%3,%1\\n\\ +\\tbeq\\t%3,%z4,2f\\n\\ +1:\\tand\\t%2,%3,0x0001\\n\\ +\\tdaddu\\t%0,%0,1\\n\\ +\\tbeq\\t%2,%z4,1b\\n\\ +\\tdsrl\\t%3,%3,1\\n\\ +2:%)\"; +}" + [(set_attr "type" "multi") + (set_attr "mode" "DI") + (set_attr "length" "6")]) + + +;; +;; .................... +;; +;; NEGATION and ONE'S COMPLEMENT +;; +;; .................... + +(define_insn "negsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (neg:SI (match_operand:SI 1 "register_operand" "d")))] + "" + "* +{ + if (TARGET_MIPS16) + return \"neg\\t%0,%1\"; + operands[2] = const0_rtx; + return \"subu\\t%0,%z2,%1\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "negdi2" + [(parallel [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "se_register_operand" "d"))) + (clobber (match_dup 2))])] + "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16" + " +{ + if (TARGET_64BIT) + { + emit_insn (gen_negdi2_internal_2 (operands[0], operands[1])); + DONE; + } + + operands[2] = gen_reg_rtx (SImode); +}") + +(define_insn "negdi2_internal" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d"))) + (clobber (match_operand:SI 2 "register_operand" "=d"))] + "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" + "* +{ + operands[3] = const0_rtx; + return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + +(define_insn "negdi2_internal_2" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "se_register_operand" "d")))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + operands[2] = const0_rtx; + return \"dsubu\\t%0,%z2,%1\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "negdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (neg:DF (match_operand:DF 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "neg.d\\t%0,%1" + [(set_attr "type" "fneg") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "negsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (neg:SF (match_operand:SF 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "neg.s\\t%0,%1" + [(set_attr "type" "fneg") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "one_cmplsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (not:SI (match_operand:SI 1 "register_operand" "d")))] + "" + "* +{ + if (TARGET_MIPS16) + return \"not\\t%0,%1\"; + operands[2] = const0_rtx; + return \"nor\\t%0,%z2,%1\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "one_cmpldi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "se_register_operand" "d")))] + "" + "* +{ + if (TARGET_MIPS16) + { + if (TARGET_64BIT) + return \"not\\t%0,%1\"; + return \"not\\t%M0,%M1\;not\\t%L0,%L1\"; + } + operands[2] = const0_rtx; + if (TARGET_64BIT) + return \"nor\\t%0,%z2,%1\"; + return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set (attr "length") + (if_then_else (ge (symbol_ref "mips_isa") (const_int 3)) + (const_int 1) + (const_int 2)))]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (not:DI (match_operand:DI 1 "register_operand" "")))] + "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" + + [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) + (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))] + "") + + +;; +;; .................... +;; +;; LOGICAL +;; +;; .................... +;; + +;; Many of these instructions uses trivial define_expands, because we +;; want to use a different set of constraints when TARGET_MIPS16. + +(define_expand "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] + "" + " +{ + if (TARGET_MIPS16) + operands[2] = force_reg (SImode, operands[2]); +}") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] + "!TARGET_MIPS16" + "@ + and\\t%0,%1,%2 + andi\\t%0,%1,%x2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (and:SI (match_operand:SI 1 "register_operand" "%0") + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_MIPS16" + "and\\t%0,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_expand "anddi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "TARGET_64BIT || !TARGET_DEBUG_G_MODE" + " +{ + if (TARGET_MIPS16) + operands[2] = force_reg (DImode, operands[2]); +}") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16" + "* +{ + if (TARGET_64BIT) + return \"and\\t%0,%1,%2\"; + return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set (attr "length") + (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (match_operand:DI 1 "se_register_operand" "0") + (match_operand:DI 2 "se_register_operand" "d")))] + "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16" + "* +{ + if (TARGET_64BIT) + return \"and\\t%0,%2\"; + return \"and\\t%M0,%M2\;and\\t%L0,%L2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set (attr "length") + (if_then_else (ge (symbol_ref "mips_isa") (const_int 3)) + (const_int 1) + (const_int 2)))]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")))] + "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) + (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] + "") + +(define_insn "anddi3_internal1" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (and:DI (match_operand:DI 1 "se_register_operand" "%d,d") + (match_operand:DI 2 "se_uns_arith_operand" "d,K")))] + "TARGET_64BIT && !TARGET_MIPS16" + "@ + and\\t%0,%1,%2 + andi\\t%0,%1,%x2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_expand "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] + "" + " +{ + if (TARGET_MIPS16) + operands[2] = force_reg (SImode, operands[2]); +}") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] + "!TARGET_MIPS16" + "@ + or\\t%0,%1,%2 + ori\\t%0,%1,%x2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (ior:SI (match_operand:SI 1 "register_operand" "%0") + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_MIPS16" + "or\\t%0,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +;;; ??? There is no iordi3 pattern which accepts 'K' constants when +;;; TARGET_64BIT + +(define_expand "iordi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (ior:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "TARGET_64BIT || !TARGET_DEBUG_G_MODE" + "") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (ior:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16" + "* +{ + if (TARGET_64BIT) + return \"or\\t%0,%1,%2\"; + return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set (attr "length") + (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (ior:DI (match_operand:DI 1 "se_register_operand" "0") + (match_operand:DI 2 "se_register_operand" "d")))] + "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16" + "* +{ + if (TARGET_64BIT) + return \"or\\t%0,%2\"; + return \"or\\t%M0,%M2\;or\\t%L0,%L2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set (attr "length") + (if_then_else (ge (symbol_ref "mips_isa") (const_int 3)) + (const_int 1) + (const_int 2)))]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ior:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")))] + "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) + (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] + "") + +(define_expand "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] + "" + "") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] + "!TARGET_MIPS16" + "@ + xor\\t%0,%1,%2 + xori\\t%0,%1,%x2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,t,t") + (xor:SI (match_operand:SI 1 "uns_arith_operand" "%0,d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K,d")))] + "TARGET_MIPS16" + "@ + xor\\t%0,%2 + cmpi\\t%1,%2 + cmp\\t%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "") + (const_int 1) + (const_int 2)) + (const_int 1)])]) + +;; ??? If delete the 32-bit long long patterns, then could merge this with +;; the following xordi3_internal pattern. +(define_expand "xordi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (xor:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "TARGET_64BIT || !TARGET_DEBUG_G_MODE" + "") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (xor:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16" + "* +{ + if (TARGET_64BIT) + return \"xor\\t%0,%1,%2\"; + return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set (attr "length") + (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (const_int 1) + (const_int 2)))]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (xor:DI (match_operand:DI 1 "se_register_operand" "0") + (match_operand:DI 2 "se_register_operand" "d")))] + "!TARGET_64BIT && TARGET_MIPS16" + "xor\\t%M0,%M2\;xor\\t%L0,%L2" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,t,t") + (xor:DI (match_operand:DI 1 "se_register_operand" "%0,d,d") + (match_operand:DI 2 "se_uns_arith_operand" "d,K,d")))] + "TARGET_64BIT && TARGET_MIPS16" + "@ + xor\\t%0,%2 + cmpi\\t%1,%2 + cmp\\t%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "") + (const_int 1) + (const_int 2)) + (const_int 1)])]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (xor:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")))] + "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) + (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] + "") + +(define_insn "xordi3_immed" + [(set (match_operand:DI 0 "register_operand" "=d") + (xor:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_uns_arith_operand" "K")))] + "TARGET_64BIT && !TARGET_MIPS16" + "xori\\t%0,%1,%x2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "*norsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (and:SI (not:SI (match_operand:SI 1 "register_operand" "d")) + (not:SI (match_operand:SI 2 "register_operand" "d"))))] + "!TARGET_MIPS16" + "nor\\t%0,%z1,%z2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "*nordi3" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (not:DI (match_operand:DI 1 "se_register_operand" "d")) + (not:DI (match_operand:DI 2 "se_register_operand" "d"))))] + "!TARGET_MIPS16" + "* +{ + if (TARGET_64BIT) + return \"nor\\t%0,%z1,%z2\"; + return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set (attr "length") + (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (const_int 1) + (const_int 2)))]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (not:DI (match_operand:DI 1 "register_operand" "")) + (not:DI (match_operand:DI 2 "register_operand" ""))))] + "reload_completed && !TARGET_MIPS16 && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) + && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" + + [(set (subreg:SI (match_dup 0) 0) (and:SI (not:SI (subreg:SI (match_dup 1) 0)) (not:SI (subreg:SI (match_dup 2) 0)))) + (set (subreg:SI (match_dup 0) 1) (and:SI (not:SI (subreg:SI (match_dup 1) 1)) (not:SI (subreg:SI (match_dup 2) 1))))] + "") + +;; +;; .................... +;; +;; TRUNCATION +;; +;; .................... + +(define_insn "truncdfsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "cvt.s.d\\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "truncdisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI (match_operand:DI 1 "se_register_operand" "d")))] + "TARGET_64BIT" + "* +{ + if (TARGET_MIPS16) + return \"dsll\\t%0,%1,32\;dsra\\t%0,32\"; + return \"dsll\\t%0,%1,32\;dsra\\t%0,%0,32\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "SI") + (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0)) + (const_int 2) + (const_int 4)))]) + +(define_insn "truncdihi2" + [(set (match_operand:HI 0 "register_operand" "=d") + (truncate:HI (match_operand:DI 1 "se_register_operand" "d")))] + "TARGET_64BIT" + "* +{ + if (TARGET_MIPS16) + return \"dsll\\t%0,%1,48\;dsra\\t%0,48\"; + return \"andi\\t%0,%1,0xffff\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "HI") + (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0)) + (const_int 1) + (const_int 4)))]) +(define_insn "truncdiqi2" + [(set (match_operand:QI 0 "register_operand" "=d") + (truncate:QI (match_operand:DI 1 "se_register_operand" "d")))] + "TARGET_64BIT" + "* +{ + if (TARGET_MIPS16) + return \"dsll\\t%0,%1,56\;dsra\\t%0,56\"; + return \"andi\\t%0,%1,0x00ff\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "QI") + (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0)) + (const_int 1) + (const_int 4)))]) + +;; Combiner patterns to optimize shift/truncate combinations. +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "small_int" "I"))))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + int shift_amt = INTVAL (operands[2]) & 0x3f; + + if (shift_amt < 32) + { + operands[2] = GEN_INT (32 - shift_amt); + return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\"; + } + else + { + operands[2] = GEN_INT (shift_amt); + return \"dsra\\t%0,%1,%2\"; + } +}" + [(set_attr "type" "darith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "small_int" "I"))))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + int shift_amt = INTVAL (operands[2]) & 0x3f; + + if (shift_amt < 32) + { + operands[2] = GEN_INT (32 - shift_amt); + return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\"; + } + else if (shift_amt == 32) + return \"dsra\\t%0,%1,32\"; + else + { + operands[2] = GEN_INT (shift_amt); + return \"dsrl\\t%0,%1,%2\"; + } +}" + [(set_attr "type" "darith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI (ashift:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "small_int" "I"))))] + "TARGET_64BIT" + "* +{ + int shift_amt = INTVAL (operands[2]) & 0x3f; + + if (shift_amt < 32) + { + operands[2] = GEN_INT (32 + shift_amt); + if (TARGET_MIPS16) + return \"dsll\\t%0,%1,%2\;dsra\\t%0,32\"; + return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\"; + } + else + return \"move\\t%0,%.\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +;; Combiner patterns to optimize truncate/zero_extend combinations. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI (truncate:HI + (match_operand:DI 1 "se_register_operand" "d"))))] + "TARGET_64BIT && !TARGET_MIPS16" + "andi\\t%0,%1,0xffff" + [(set_attr "type" "darith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (zero_extend:SI (truncate:QI + (match_operand:DI 1 "se_register_operand" "d"))))] + "TARGET_64BIT && !TARGET_MIPS16" + "andi\\t%0,%1,0xff" + [(set_attr "type" "darith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:HI 0 "register_operand" "=d") + (zero_extend:HI (truncate:QI + (match_operand:DI 1 "se_register_operand" "d"))))] + "TARGET_64BIT && !TARGET_MIPS16" + "andi\\t%0,%1,0xff" + [(set_attr "type" "darith") + (set_attr "mode" "HI") + (set_attr "length" "1")]) + +;; +;; .................... +;; +;; ZERO EXTENSION +;; +;; .................... + +;; Extension insns. +;; Those for integer source operand are ordered widest source type first. + +(define_expand "zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] + "TARGET_64BIT" + " +{ + if (optimize && GET_CODE (operands[1]) == MEM) + operands[1] = force_not_mem (operands[1]); + + if (GET_CODE (operands[1]) != MEM) + { + rtx op1 = gen_lowpart (DImode, operands[1]); + rtx temp = gen_reg_rtx (DImode); + rtx shift = GEN_INT (32); + + emit_insn (gen_ashldi3 (temp, op1, shift)); + emit_insn (gen_lshrdi3 (operands[0], temp, shift)); + DONE; + } +}") + +(define_insn "zero_extendsidi2_internal" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))] + "TARGET_64BIT" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "load") + (set_attr "mode" "DI") + (set_attr "length" "1,2")]) + +(define_expand "zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] + "" + " +{ + if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM) + { + rtx op = gen_lowpart (SImode, operands[1]); + rtx temp = force_reg (SImode, GEN_INT (0xffff)); + + emit_insn (gen_andsi3 (operands[0], op, temp)); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))] + "!TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"andi\\t%0,%1,0xffff\"; + else + return mips_move_1word (operands, insn, TRUE); +}" + [(set_attr "type" "arith,load,load") + (set_attr "mode" "SI") + (set_attr "length" "1,1,2")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (zero_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))] + "TARGET_MIPS16" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "load,load") + (set_attr "mode" "SI") + (set_attr "length" "1,2")]) + +(define_expand "zero_extendhidi2" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))] + "TARGET_64BIT" + " +{ + if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM) + { + rtx op = gen_lowpart (DImode, operands[1]); + rtx temp = force_reg (DImode, GEN_INT (0xffff)); + + emit_insn (gen_anddi3 (operands[0], op, temp)); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"andi\\t%0,%1,0xffff\"; + else + return mips_move_1word (operands, insn, TRUE); +}" + [(set_attr "type" "arith,load,load") + (set_attr "mode" "DI") + (set_attr "length" "1,1,2")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (zero_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))] + "TARGET_64BIT && TARGET_MIPS16" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "load,load") + (set_attr "mode" "DI") + (set_attr "length" "1,2")]) + +(define_expand "zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand" "") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] + "" + " +{ + if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM) + { + rtx op0 = gen_lowpart (SImode, operands[0]); + rtx op1 = gen_lowpart (SImode, operands[1]); + rtx temp = force_reg (SImode, GEN_INT (0xff)); + + emit_insn (gen_andsi3 (op0, op1, temp)); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:HI 0 "register_operand" "=d,d,d") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] + "!TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"andi\\t%0,%1,0x00ff\"; + else + return mips_move_1word (operands, insn, TRUE); +}" + [(set_attr "type" "arith,load,load") + (set_attr "mode" "HI") + (set_attr "length" "1,1,2")]) + +(define_insn "" + [(set (match_operand:HI 0 "register_operand" "=d,d") + (zero_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))] + "TARGET_MIPS16" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "load,load") + (set_attr "mode" "HI") + (set_attr "length" "1,2")]) + +(define_expand "zero_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] + "" + " +{ + if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM) + { + rtx op = gen_lowpart (SImode, operands[1]); + rtx temp = force_reg (SImode, GEN_INT (0xff)); + + emit_insn (gen_andsi3 (operands[0], op, temp)); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] + "!TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"andi\\t%0,%1,0x00ff\"; + else + return mips_move_1word (operands, insn, TRUE); +}" + [(set_attr "type" "arith,load,load") + (set_attr "mode" "SI") + (set_attr "length" "1,1,2")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (zero_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))] + "TARGET_MIPS16" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "load,load") + (set_attr "mode" "SI") + (set_attr "length" "1,2")]) + +(define_expand "zero_extendqidi2" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))] + "TARGET_64BIT" + " +{ + if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM) + { + rtx op = gen_lowpart (DImode, operands[1]); + rtx temp = force_reg (DImode, GEN_INT (0xff)); + + emit_insn (gen_anddi3 (operands[0], op, temp)); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"andi\\t%0,%1,0x00ff\"; + else + return mips_move_1word (operands, insn, TRUE); +}" + [(set_attr "type" "arith,load,load") + (set_attr "mode" "DI") + (set_attr "length" "1,1,2")]) + +;; These can be created when a paradoxical subreg operand with an implicit +;; sign_extend operator is reloaded. Because of the subreg, this is really +;; a zero extend. +;; ??? It might be possible to eliminate the need for these patterns by adding +;; more support to reload for implicit sign_extend operators. +(define_insn "*paradoxical_extendhidi2" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (sign_extend:DI + (subreg:SI (match_operand:HI 1 "memory_operand" "R,m") 0)))] + "TARGET_64BIT" + "* +{ + return mips_move_1word (operands, insn, TRUE); +}" + [(set_attr "type" "load,load") + (set_attr "mode" "DI") + (set_attr "length" "1,2")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (zero_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))] + "TARGET_64BIT && TARGET_MIPS16" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "load,load") + (set_attr "mode" "DI") + (set_attr "length" "1,2")]) + +;; +;; .................... +;; +;; SIGN EXTENSION +;; +;; .................... + +;; Extension insns. +;; Those for integer source operand are ordered widest source type first. + +;; In 64 bit mode, 32 bit values in general registers are always +;; correctly sign extended. That means that if the target is a +;; general register, we can sign extend from SImode to DImode just by +;; doing a move. + +(define_insn "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x,R,m")))] + "TARGET_64BIT" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "move,move,move,hilo,load,load") + (set_attr "mode" "DI") + (set_attr "length" "1,1,1,1,1,2")]) + +;; These patterns originally accepted general_operands, however, slightly +;; better code is generated by only accepting register_operands, and then +;; letting combine generate the lh and lb insns. + +(define_expand "extendhidi2" + [(set (match_operand:DI 0 "register_operand" "") + (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))] + "TARGET_64BIT" + " +{ + if (optimize && GET_CODE (operands[1]) == MEM) + operands[1] = force_not_mem (operands[1]); + + if (GET_CODE (operands[1]) != MEM) + { + rtx op1 = gen_lowpart (DImode, operands[1]); + rtx temp = gen_reg_rtx (DImode); + rtx shift = GEN_INT (48); + + emit_insn (gen_ashldi3 (temp, op1, shift)); + emit_insn (gen_ashrdi3 (operands[0], temp, shift)); + DONE; + } +}") + +(define_insn "extendhidi2_internal" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))] + "TARGET_64BIT" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "load") + (set_attr "mode" "DI") + (set_attr "length" "1,2")]) + +(define_expand "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] + "" + " +{ + if (optimize && GET_CODE (operands[1]) == MEM) + operands[1] = force_not_mem (operands[1]); + + if (GET_CODE (operands[1]) != MEM) + { + rtx op1 = gen_lowpart (SImode, operands[1]); + rtx temp = gen_reg_rtx (SImode); + rtx shift = GEN_INT (16); + + emit_insn (gen_ashlsi3 (temp, op1, shift)); + emit_insn (gen_ashrsi3 (operands[0], temp, shift)); + DONE; + } +}") + +(define_insn "extendhisi2_internal" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))] + "" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "load") + (set_attr "mode" "SI") + (set_attr "length" "1,2")]) + +(define_expand "extendqihi2" + [(set (match_operand:HI 0 "register_operand" "") + (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] + "" + " +{ + if (optimize && GET_CODE (operands[1]) == MEM) + operands[1] = force_not_mem (operands[1]); + + if (GET_CODE (operands[1]) != MEM) + { + rtx op0 = gen_lowpart (SImode, operands[0]); + rtx op1 = gen_lowpart (SImode, operands[1]); + rtx temp = gen_reg_rtx (SImode); + rtx shift = GEN_INT (24); + + emit_insn (gen_ashlsi3 (temp, op1, shift)); + emit_insn (gen_ashrsi3 (op0, temp, shift)); + DONE; + } +}") + +(define_insn "extendqihi2_internal" + [(set (match_operand:HI 0 "register_operand" "=d,d") + (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))] + "" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "load") + (set_attr "mode" "SI") + (set_attr "length" "1,2")]) + + +(define_expand "extendqisi2" + [(set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] + "" + " +{ + if (optimize && GET_CODE (operands[1]) == MEM) + operands[1] = force_not_mem (operands[1]); + + if (GET_CODE (operands[1]) != MEM) + { + rtx op1 = gen_lowpart (SImode, operands[1]); + rtx temp = gen_reg_rtx (SImode); + rtx shift = GEN_INT (24); + + emit_insn (gen_ashlsi3 (temp, op1, shift)); + emit_insn (gen_ashrsi3 (operands[0], temp, shift)); + DONE; + } +}") + +(define_insn "extendqisi2_insn" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))] + "" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "load") + (set_attr "mode" "SI") + (set_attr "length" "1,2")]) + +(define_expand "extendqidi2" + [(set (match_operand:DI 0 "register_operand" "") + (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))] + "TARGET_64BIT" + " +{ + if (optimize && GET_CODE (operands[1]) == MEM) + operands[1] = force_not_mem (operands[1]); + + if (GET_CODE (operands[1]) != MEM) + { + rtx op1 = gen_lowpart (DImode, operands[1]); + rtx temp = gen_reg_rtx (DImode); + rtx shift = GEN_INT (56); + + emit_insn (gen_ashldi3 (temp, op1, shift)); + emit_insn (gen_ashrdi3 (operands[0], temp, shift)); + DONE; + } +}") + +(define_insn "extendqidi2_insn" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))] + "TARGET_64BIT" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "load") + (set_attr "mode" "DI") + (set_attr "length" "1,2")]) + + +(define_insn "extendsfdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "cvt.d.s\\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + + + +;; +;; .................... +;; +;; CONVERSIONS +;; +;; .................... + +;; The SImode scratch register can not be shared with address regs used for +;; operand zero, because then the address in the move instruction will be +;; clobbered. We mark the scratch register as early clobbered to prevent this. + +;; We need the ?X in alternative 1 so that it will be choosen only if the +;; destination is a floating point register. Otherwise, alternative 1 can +;; have lower cost than alternative 0 (because there is one less loser), and +;; can be choosen when it won't work (because integral reloads into FP +;; registers are not supported). + +(define_insn "fix_truncdfsi2" + [(set (match_operand:SI 0 "general_operand" "=d,*f,R,To") + (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f"))) + (clobber (match_scratch:SI 2 "=d,*d,&d,&d")) + (clobber (match_scratch:DF 3 "=f,?*X,f,f"))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "* +{ + rtx xoperands[10]; + + if (which_alternative == 1) + return \"trunc.w.d %0,%1,%2\"; + + output_asm_insn (\"trunc.w.d %3,%1,%2\", operands); + + xoperands[0] = operands[0]; + xoperands[1] = operands[3]; + output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); + return \"\"; +}" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") + (set_attr "length" "11,9,10,11")]) + + +(define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "general_operand" "=d,*f,R,To") + (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f"))) + (clobber (match_scratch:SI 2 "=d,*d,&d,&d")) + (clobber (match_scratch:SF 3 "=f,?*X,f,f"))] + "TARGET_HARD_FLOAT" + "* +{ + rtx xoperands[10]; + + if (which_alternative == 1) + return \"trunc.w.s %0,%1,%2\"; + + output_asm_insn (\"trunc.w.s %3,%1,%2\", operands); + + xoperands[0] = operands[0]; + xoperands[1] = operands[3]; + output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands); + return \"\"; +}" + [(set_attr "type" "fcvt") + (set_attr "mode" "SF") + (set_attr "length" "11,9,10,11")]) + + +;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals +;;; but not in the chapter that describes the FPU. It is not mentioned at all +;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction. + +;;; Deleting this means that we now need two libgcc2.a libraries. One for +;;; the 32 bit calling convention and one for the 64 bit calling convention. + +;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also. + +(define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "general_operand" "=d,*f,R,To") + (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f"))) + (clobber (match_scratch:DF 2 "=f,?*X,f,f"))] + "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" + "* +{ + rtx xoperands[10]; + + if (which_alternative == 1) + return \"trunc.l.d %0,%1\"; + + output_asm_insn (\"trunc.l.d %2,%1\", operands); + + xoperands[0] = operands[0]; + xoperands[1] = operands[2]; + output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands); + return \"\"; +}" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") + (set_attr "length" "2,1,2,3")]) + + +;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals +;;; but not in the chapter that describes the FPU. It is not mentioned at all +;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction. +(define_insn "fix_truncsfdi2" + [(set (match_operand:DI 0 "general_operand" "=d,*f,R,To") + (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f"))) + (clobber (match_scratch:DF 2 "=f,?*X,f,f"))] + "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" + "* +{ + rtx xoperands[10]; + + if (which_alternative == 1) + return \"trunc.l.s %0,%1\"; + + output_asm_insn (\"trunc.l.s %2,%1\", operands); + + xoperands[0] = operands[0]; + xoperands[1] = operands[2]; + output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands); + return \"\"; +}" + [(set_attr "type" "fcvt") + (set_attr "mode" "SF") + (set_attr "length" "2,1,2,3")]) + + +(define_insn "floatsidf2" + [(set (match_operand:DF 0 "register_operand" "=f,f,f") + (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "* +{ + dslots_load_total++; + if (GET_CODE (operands[1]) == MEM) + return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\"; + + return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\"; +}" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") + (set_attr "length" "3,4,3")]) + + +(define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=f,f,f") + (float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))] + "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" + "* +{ + dslots_load_total++; + if (GET_CODE (operands[1]) == MEM) + return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\"; + + return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\"; +}" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") + (set_attr "length" "3,4,3")]) + + +(define_insn "floatsisf2" + [(set (match_operand:SF 0 "register_operand" "=f,f,f") + (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] + "TARGET_HARD_FLOAT" + "* +{ + dslots_load_total++; + if (GET_CODE (operands[1]) == MEM) + return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\"; + + return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\"; +}" + [(set_attr "type" "fcvt") + (set_attr "mode" "SF") + (set_attr "length" "3,4,3")]) + + +(define_insn "floatdisf2" + [(set (match_operand:SF 0 "register_operand" "=f,f,f") + (float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))] + "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" + "* +{ + dslots_load_total++; + if (GET_CODE (operands[1]) == MEM) + return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\"; + + return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\"; +}" + [(set_attr "type" "fcvt") + (set_attr "mode" "SF") + (set_attr "length" "3,4,3")]) + + +(define_expand "fixuns_truncdfsi2" + [(set (match_operand:SI 0 "register_operand" "") + (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + " +{ + rtx reg1 = gen_reg_rtx (DFmode); + rtx reg2 = gen_reg_rtx (DFmode); + rtx reg3 = gen_reg_rtx (SImode); + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31); + + if (reg1) /* turn off complaints about unreached code */ + { + emit_move_insn (reg1, immed_real_const_1 (offset, DFmode)); + do_pending_stack_adjust (); + + emit_insn (gen_cmpdf (operands[1], reg1)); + emit_jump_insn (gen_bge (label1)); + + emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1])); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, + gen_rtx (LABEL_REF, VOIDmode, label2))); + emit_barrier (); + + emit_label (label1); + emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1)); + emit_move_insn (reg3, GEN_INT (0x80000000)); + + emit_insn (gen_fix_truncdfsi2 (operands[0], reg2)); + emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); + + emit_label (label2); + + /* allow REG_NOTES to be set on last insn (labels don't have enough + fields, and can't be used for REG_NOTES anyway). */ + emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); + DONE; + } +}") + + +(define_expand "fixuns_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "") + (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] + "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" + " +{ + rtx reg1 = gen_reg_rtx (DFmode); + rtx reg2 = gen_reg_rtx (DFmode); + rtx reg3 = gen_reg_rtx (DImode); + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63); + + if (reg1) /* turn off complaints about unreached code */ + { + emit_move_insn (reg1, immed_real_const_1 (offset, DFmode)); + do_pending_stack_adjust (); + + emit_insn (gen_cmpdf (operands[1], reg1)); + emit_jump_insn (gen_bge (label1)); + + emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1])); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, + gen_rtx (LABEL_REF, VOIDmode, label2))); + emit_barrier (); + + emit_label (label1); + emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1)); + emit_move_insn (reg3, GEN_INT (0x80000000)); + emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); + + emit_insn (gen_fix_truncdfdi2 (operands[0], reg2)); + emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); + + emit_label (label2); + + /* allow REG_NOTES to be set on last insn (labels don't have enough + fields, and can't be used for REG_NOTES anyway). */ + emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); + DONE; + } +}") + + +(define_expand "fixuns_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "") + (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] + "TARGET_HARD_FLOAT" + " +{ + rtx reg1 = gen_reg_rtx (SFmode); + rtx reg2 = gen_reg_rtx (SFmode); + rtx reg3 = gen_reg_rtx (SImode); + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31); + + if (reg1) /* turn off complaints about unreached code */ + { + emit_move_insn (reg1, immed_real_const_1 (offset, SFmode)); + do_pending_stack_adjust (); + + emit_insn (gen_cmpsf (operands[1], reg1)); + emit_jump_insn (gen_bge (label1)); + + emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1])); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, + gen_rtx (LABEL_REF, VOIDmode, label2))); + emit_barrier (); + + emit_label (label1); + emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1)); + emit_move_insn (reg3, GEN_INT (0x80000000)); + + emit_insn (gen_fix_truncsfsi2 (operands[0], reg2)); + emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); + + emit_label (label2); + + /* allow REG_NOTES to be set on last insn (labels don't have enough + fields, and can't be used for REG_NOTES anyway). */ + emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); + DONE; + } +}") + + +(define_expand "fixuns_truncsfdi2" + [(set (match_operand:DI 0 "register_operand" "") + (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] + "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" + " +{ + rtx reg1 = gen_reg_rtx (SFmode); + rtx reg2 = gen_reg_rtx (SFmode); + rtx reg3 = gen_reg_rtx (DImode); + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63); + + if (reg1) /* turn off complaints about unreached code */ + { + emit_move_insn (reg1, immed_real_const_1 (offset, SFmode)); + do_pending_stack_adjust (); + + emit_insn (gen_cmpsf (operands[1], reg1)); + emit_jump_insn (gen_bge (label1)); + + emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1])); + emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, + gen_rtx (LABEL_REF, VOIDmode, label2))); + emit_barrier (); + + emit_label (label1); + emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1)); + emit_move_insn (reg3, GEN_INT (0x80000000)); + emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); + + emit_insn (gen_fix_truncsfdi2 (operands[0], reg2)); + emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); + + emit_label (label2); + + /* allow REG_NOTES to be set on last insn (labels don't have enough + fields, and can't be used for REG_NOTES anyway). */ + emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); + DONE; + } +}") + + +;; +;; .................... +;; +;; DATA MOVEMENT +;; +;; .................... + +;; Bit field extract patterns which use lwl/lwr. + +;; ??? There could be HImode variants for the ulh/ulhu/ush macros. +;; It isn't clear whether this will give better code. + +;; Only specify the mode operand 1, the rest are assumed to be word_mode. +(define_expand "extv" + [(set (match_operand 0 "register_operand" "") + (sign_extract (match_operand:QI 1 "memory_operand" "") + (match_operand 2 "immediate_operand" "") + (match_operand 3 "immediate_operand" "")))] + "!TARGET_MIPS16" + " +{ + /* If the field does not start on a byte boundary, then fail. */ + if (INTVAL (operands[3]) % 8 != 0) + FAIL; + + /* MIPS I and MIPS II can only handle a 32bit field. */ + if (!TARGET_64BIT && INTVAL (operands[2]) != 32) + FAIL; + + /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */ + if (TARGET_64BIT + && INTVAL (operands[2]) != 64 + && INTVAL (operands[2]) != 32) + FAIL; + + /* This can happen for a 64 bit target, when extracting a value from + a 64 bit union member. extract_bit_field doesn't verify that our + source matches the predicate, so we force it to be a MEM here. */ + if (GET_CODE (operands[1]) != MEM) + FAIL; + + /* Change the mode to BLKmode for aliasing purposes. */ + operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0)); + + /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value. */ + if (INTVAL (operands[2]) == 64) + emit_insn (gen_movdi_uld (operands[0], operands[1])); + else + { + if (TARGET_64BIT) + { + operands[0] = gen_lowpart (SImode, operands[0]); + if (operands[0] == NULL_RTX) + FAIL; + } + emit_insn (gen_movsi_ulw (operands[0], operands[1])); + } + DONE; +}") + +;; Only specify the mode operand 1, the rest are assumed to be word_mode. +(define_expand "extzv" + [(set (match_operand 0 "register_operand" "") + (zero_extract (match_operand:QI 1 "memory_operand" "") + (match_operand 2 "immediate_operand" "") + (match_operand 3 "immediate_operand" "")))] + "!TARGET_MIPS16" + " +{ + /* If the field does not start on a byte boundary, then fail. */ + if (INTVAL (operands[3]) % 8 != 0) + FAIL; + + /* MIPS I and MIPS II can only handle a 32bit field. */ + if (!TARGET_64BIT && INTVAL (operands[2]) != 32) + FAIL; + + /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */ + if (TARGET_64BIT + && INTVAL (operands[2]) != 64 + && INTVAL (operands[2]) != 32) + FAIL; + + /* This can happen for a 64 bit target, when extracting a value from + a 64 bit union member. extract_bit_field doesn't verify that our + source matches the predicate, so we force it to be a MEM here. */ + if (GET_CODE (operands[1]) != MEM) + FAIL; + + /* Change the mode to BLKmode for aliasing purposes. */ + operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0)); + + /* Otherwise, emit a lwl/lwr pair to load the value. */ + if (INTVAL (operands[2]) == 64) + emit_insn (gen_movdi_uld (operands[0], operands[1])); + else + { + if (TARGET_64BIT) + { + operands[0] = gen_lowpart (SImode, operands[0]); + if (operands[0] == NULL_RTX) + FAIL; + } + emit_insn (gen_movsi_ulw (operands[0], operands[1])); + } + DONE; +}") + +;; Only specify the mode operands 0, the rest are assumed to be word_mode. +(define_expand "insv" + [(set (zero_extract (match_operand:QI 0 "memory_operand" "") + (match_operand 1 "immediate_operand" "") + (match_operand 2 "immediate_operand" "")) + (match_operand 3 "register_operand" ""))] + "!TARGET_MIPS16" + " +{ + /* If the field does not start on a byte boundary, then fail. */ + if (INTVAL (operands[2]) % 8 != 0) + FAIL; + + /* MIPS I and MIPS II can only handle a 32bit field. */ + if (!TARGET_64BIT && INTVAL (operands[1]) != 32) + FAIL; + + /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */ + if (TARGET_64BIT + && INTVAL (operands[1]) != 64 + && INTVAL (operands[1]) != 32) + FAIL; + + /* This can happen for a 64 bit target, when storing into a 32 bit union + member. store_bit_field doesn't verify that our target matches the + predicate, so we force it to be a MEM here. */ + if (GET_CODE (operands[0]) != MEM) + FAIL; + + /* Change the mode to BLKmode for aliasing purposes. */ + operands[0] = change_address (operands[0], BLKmode, XEXP (operands[0], 0)); + + /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value. */ + if (INTVAL (operands[1]) == 64) + emit_insn (gen_movdi_usd (operands[0], operands[3])); + else + { + if (TARGET_64BIT) + { + operands[3] = gen_lowpart (SImode, operands[3]); + if (operands[3] == NULL_RTX) + FAIL; + } + emit_insn (gen_movsi_usw (operands[0], operands[3])); + } + DONE; +}") + +;; unaligned word moves generated by the bit field patterns + +(define_insn "movsi_ulw" + [(set (match_operand:SI 0 "register_operand" "=&d,&d") + (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))] + "!TARGET_MIPS16" + "* +{ + rtx offset = const0_rtx; + rtx addr = XEXP (operands[1], 0); + rtx mem_addr = eliminate_constant_term (addr, &offset); + const char *ret; + + if (TARGET_STATS) + mips_count_memory_refs (operands[1], 2); + + /* The stack/frame pointers are always aligned, so we can convert + to the faster lw if we are referencing an aligned stack location. */ + + if ((INTVAL (offset) & 3) == 0 + && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) + ret = \"lw\\t%0,%1\"; + else + ret = \"ulw\\t%0,%1\"; + + return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn); +}" + [(set_attr "type" "load,load") + (set_attr "mode" "SI") + (set_attr "length" "2,4")]) + +(define_insn "movsi_usw" + [(set (match_operand:BLK 0 "memory_operand" "=R,o") + (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))] + "!TARGET_MIPS16" + "* +{ + rtx offset = const0_rtx; + rtx addr = XEXP (operands[0], 0); + rtx mem_addr = eliminate_constant_term (addr, &offset); + + if (TARGET_STATS) + mips_count_memory_refs (operands[0], 2); + + /* The stack/frame pointers are always aligned, so we can convert + to the faster sw if we are referencing an aligned stack location. */ + + if ((INTVAL (offset) & 3) == 0 + && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) + return \"sw\\t%1,%0\"; + + return \"usw\\t%z1,%0\"; +}" + [(set_attr "type" "store") + (set_attr "mode" "SI") + (set_attr "length" "2,4")]) + +;; Bit field extract patterns which use ldl/ldr. + +;; unaligned double word moves generated by the bit field patterns + +(define_insn "movdi_uld" + [(set (match_operand:DI 0 "register_operand" "=&d,&d") + (unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")] 0))] + "" + "* +{ + rtx offset = const0_rtx; + rtx addr = XEXP (operands[1], 0); + rtx mem_addr = eliminate_constant_term (addr, &offset); + const char *ret; + + if (TARGET_STATS) + mips_count_memory_refs (operands[1], 2); + + /* The stack/frame pointers are always aligned, so we can convert + to the faster lw if we are referencing an aligned stack location. */ + + if ((INTVAL (offset) & 7) == 0 + && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) + ret = \"ld\\t%0,%1\"; + else + ret = \"uld\\t%0,%1\"; + + return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn); +}" + [(set_attr "type" "load,load") + (set_attr "mode" "SI") + (set_attr "length" "2,4")]) + +(define_insn "movdi_usd" + [(set (match_operand:BLK 0 "memory_operand" "=R,o") + (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")] 1))] + "" + "* +{ + rtx offset = const0_rtx; + rtx addr = XEXP (operands[0], 0); + rtx mem_addr = eliminate_constant_term (addr, &offset); + + if (TARGET_STATS) + mips_count_memory_refs (operands[0], 2); + + /* The stack/frame pointers are always aligned, so we can convert + to the faster sw if we are referencing an aligned stack location. */ + + if ((INTVAL (offset) & 7) == 0 + && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx)) + return \"sd\\t%1,%0\"; + + return \"usd\\t%z1,%0\"; +}" + [(set_attr "type" "store") + (set_attr "mode" "SI") + (set_attr "length" "2,4")]) + +;; These two patterns support loading addresses with two instructions instead +;; of using the macro instruction la. + +;; ??? mips_move_1word has support for HIGH, so this pattern may be +;; unnecessary. + +(define_insn "high" + [(set (match_operand:SI 0 "register_operand" "=r") + (high:SI (match_operand:SI 1 "immediate_operand" "")))] + "mips_split_addresses && !TARGET_MIPS16" + "lui\\t%0,%%hi(%1) # high" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "low" + [(set (match_operand:SI 0 "register_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "")))] + "mips_split_addresses && !TARGET_MIPS16" + "addiu\\t%0,%1,%%lo(%2) # low" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +;; 64-bit integer moves + +;; Unlike most other insns, the move insns can't be split with +;; different predicates, because register spilling and other parts of +;; the compiler, have memoized the insn number already. + +(define_expand "movdi" + [(set (match_operand:DI 0 "nonimmediate_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + " +{ + if (mips_split_addresses && mips_check_split (operands[1], DImode)) + { + enum machine_mode mode = GET_MODE (operands[0]); + rtx tem = ((reload_in_progress | reload_completed) + ? operands[0] : gen_reg_rtx (mode)); + + emit_insn (gen_rtx (SET, VOIDmode, tem, + gen_rtx (HIGH, mode, operands[1]))); + + operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]); + } + + /* If we are generating embedded PIC code, and we are referring to a + symbol in the .text section, we must use an offset from the start + of the function. */ + if (TARGET_EMBEDDED_PIC + && (GET_CODE (operands[1]) == LABEL_REF + || (GET_CODE (operands[1]) == SYMBOL_REF + && ! SYMBOL_REF_FLAG (operands[1])))) + { + rtx temp; + + temp = embedded_pic_offset (operands[1]); + temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx, + force_reg (DImode, temp)); + emit_move_insn (operands[0], force_reg (DImode, temp)); + DONE; + } + + /* If operands[1] is a constant address illegal for pic, then we need to + handle it just like LEGITIMIZE_ADDRESS does. */ + if (flag_pic && pic_address_needs_scratch (operands[1])) + { + rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); + rtx temp2 = XEXP (XEXP (operands[1], 0), 1); + + if (! SMALL_INT (temp2)) + temp2 = force_reg (DImode, temp2); + + emit_move_insn (operands[0], gen_rtx (PLUS, DImode, temp, temp2)); + DONE; + } + + /* On the mips16, we can handle a GP relative reference by adding in + $gp. We need to check the name to see whether this is a string + constant. */ + if (TARGET_MIPS16 + && register_operand (operands[0], DImode) + && GET_CODE (operands[1]) == SYMBOL_REF + && SYMBOL_REF_FLAG (operands[1])) + { + char *name = XSTR (operands[1], 0); + + if (name[0] != '*' + || strncmp (name + 1, LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) != 0) + { + rtx base_reg; + + if (reload_in_progress || reload_completed) + { + /* In movsi we use the constant table here. However, in + this case, we're better off copying $28 into a + register and adding, because the constant table entry + would be 8 bytes. */ + base_reg = operands[0]; + emit_move_insn (base_reg, + gen_rtx (CONST, DImode, + gen_rtx (REG, DImode, + GP_REG_FIRST + 28))); + } + else + { + base_reg = gen_reg_rtx (Pmode); + emit_move_insn (base_reg, mips16_gp_pseudo_reg ()); + } + + emit_move_insn (operands[0], + gen_rtx (PLUS, Pmode, base_reg, + mips16_gp_offset (operands[1]))); + DONE; + } + } + + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], DImode) + && !register_operand (operands[1], DImode) + && (TARGET_MIPS16 + || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) + && operands[1] != CONST0_RTX (DImode)))) + { + rtx temp = force_reg (DImode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } +}") + +;; For mips16, we need a special case to handle storing $31 into +;; memory, since we don't have a constraint to match $31. This +;; instruction can be generated by save_restore_insns. + +(define_insn "" + [(set (match_operand:DI 0 "memory_operand" "R,m") + (reg:DI 31))] + "TARGET_MIPS16 && TARGET_64BIT" + "* +{ + operands[1] = gen_rtx (REG, DImode, 31); + return mips_move_2words (operands, insn); +}" + [(set_attr "type" "store") + (set_attr "mode" "DI") + (set_attr "length" "1,2")]) + +(define_insn "movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x") + (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))] + "!TARGET_64BIT && !TARGET_MIPS16 + && (register_operand (operands[0], DImode) + || register_operand (operands[1], DImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) + || operands[1] == CONST0_RTX (DImode))" + "* return mips_move_2words (operands, insn); " + [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo,hilo") + (set_attr "mode" "DI") + (set_attr "length" "2,4,2,4,2,4,2,2,2")]) + +(define_insn "" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d") + (match_operand:DI 1 "general_operand" "d,d,y,K,N,R,To,d,d,*x"))] + "!TARGET_64BIT && TARGET_MIPS16 + && (register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "* return mips_move_2words (operands, insn);" + [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo") + (set_attr "mode" "DI") + (set_attr "length" "2,2,2,2,3,2,4,2,4,2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" ""))] + "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" + + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))] + "") + +(define_insn "movdi_internal2" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x,*d,*x,*a") + (match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J"))] + "TARGET_64BIT && !TARGET_MIPS16 + && (register_operand (operands[0], DImode) + || se_register_operand (operands[1], DImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) + || operands[1] == CONST0_RTX (DImode))" + "* return mips_move_2words (operands, insn); " + [(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo") + (set_attr "mode" "DI") + (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,2")]) + +(define_insn "" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d") + (match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x"))] + "TARGET_64BIT && TARGET_MIPS16 + && (register_operand (operands[0], DImode) + || se_register_operand (operands[1], DImode))" + "* return mips_move_2words (operands, insn);" + [(set_attr "type" "move,move,move,arith,arith,arith,load,load,store,store,hilo") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(const_int 1) + (const_int 1) + (const_int 1) + (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "") + (const_int 2) + (const_int 3)) + (if_then_else (match_operand:VOID 1 "m16_usym5_4" "") + (const_int 1) + (const_int 2)) + (const_int 1) + (const_int 2) + (const_int 1) + (const_int 2) + (const_int 1)])]) + +;; On the mips16, we can split ld $r,N($r) into an add and a load, +;; when the original load is a 4 byte instruction but the add and the +;; load are 2 2 byte instructions. + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (mem:DI (plus:DI (match_dup 0) + (match_operand:DI 1 "const_int_operand" ""))))] + "TARGET_64BIT && TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && ((INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) >= -0x10) + || (INTVAL (operands[1]) >= 32 * 8 + && INTVAL (operands[1]) <= 31 * 8 + 0x8) + || (INTVAL (operands[1]) >= 0 + && INTVAL (operands[1]) < 32 * 8 + && (INTVAL (operands[1]) & 7) != 0))" + [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (val < 0) + operands[2] = GEN_INT (0); + else if (val >= 32 * 8) + { + int off = val & 7; + + operands[1] = GEN_INT (0x8 + off); + operands[2] = GEN_INT (val - off - 0x8); + } + else + { + int off = val & 7; + + operands[1] = GEN_INT (off); + operands[2] = GEN_INT (val - off); + } +}") + +;; Handle input reloads in DImode. +;; This is mainly to handle reloading HILO_REGNUM. Note that we may +;; see it as the source or the destination, depending upon which way +;; reload handles the instruction. +;; Making the second operand TImode is a trick. The compiler may +;; reuse the same register for operand 0 and operand 2. Using TImode +;; gives us two registers, so we can always use the one which is not +;; used. + +(define_expand "reload_indi" + [(set (match_operand:DI 0 "register_operand" "=b") + (match_operand:DI 1 "" "b")) + (clobber (match_operand:TI 2 "register_operand" "=&d"))] + "TARGET_64BIT" + " +{ + rtx scratch = gen_rtx (REG, DImode, + (REGNO (operands[0]) == REGNO (operands[2]) + ? REGNO (operands[2]) + 1 + : REGNO (operands[2]))); + + if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM) + { + if (GET_CODE (operands[1]) == MEM) + { + rtx memword, offword, hiword, loword; + rtx addr = find_replacement (&XEXP (operands[1], 0)); + rtx op1 = change_address (operands[1], VOIDmode, addr); + + scratch = gen_rtx (REG, SImode, REGNO (scratch)); + memword = change_address (op1, SImode, NULL_RTX); + offword = change_address (adj_offsettable_operand (op1, 4), + SImode, NULL_RTX); + if (BYTES_BIG_ENDIAN) + { + hiword = memword; + loword = offword; + } + else + { + hiword = offword; + loword = memword; + } + emit_move_insn (scratch, hiword); + emit_move_insn (gen_rtx (REG, SImode, 64), scratch); + emit_move_insn (scratch, loword); + emit_move_insn (gen_rtx (REG, SImode, 65), scratch); + emit_insn (gen_rtx_USE (VOIDmode, operands[0])); + } + else + { + emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32))); + emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch)); + emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32))); + emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32))); + emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch)); + emit_insn (gen_rtx_USE (VOIDmode, operands[0])); + } + DONE; + } + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM) + { + emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65))); + emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32))); + emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32))); + emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64))); + emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32))); + emit_insn (gen_iordi3 (operands[0], operands[0], scratch)); + emit_insn (gen_rtx_USE (VOIDmode, operands[1])); + DONE; + } + /* This handles moves between a float register and HI/LO. */ + emit_move_insn (scratch, operands[1]); + emit_move_insn (operands[0], scratch); + DONE; +}") + +;; Handle output reloads in DImode. + +;; Reloading HILO_REG in MIPS16 mode requires two scratch registers, so we +;; use a TImode scratch reg. + +(define_expand "reload_outdi" + [(set (match_operand:DI 0 "" "=b") + (match_operand:DI 1 "se_register_operand" "b")) + (clobber (match_operand:TI 2 "register_operand" "=&d"))] + "TARGET_64BIT" + " +{ + rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2])); + + if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM) + { + emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32))); + emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch)); + emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32))); + emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32))); + emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch)); + emit_insn (gen_rtx_USE (VOIDmode, operands[0])); + DONE; + } + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM) + { + if (GET_CODE (operands[0]) == MEM) + { + rtx scratch, memword, offword, hiword, loword; + rtx addr = find_replacement (&XEXP (operands[0], 0)); + rtx op0 = change_address (operands[0], VOIDmode, addr); + + scratch = gen_rtx (REG, SImode, REGNO (operands[2])); + memword = change_address (op0, SImode, NULL_RTX); + offword = change_address (adj_offsettable_operand (op0, 4), + SImode, NULL_RTX); + if (BYTES_BIG_ENDIAN) + { + hiword = memword; + loword = offword; + } + else + { + hiword = offword; + loword = memword; + } + emit_move_insn (scratch, gen_rtx (REG, SImode, 64)); + emit_move_insn (hiword, scratch); + emit_move_insn (scratch, gen_rtx (REG, SImode, 65)); + emit_move_insn (loword, scratch); + emit_insn (gen_rtx_USE (VOIDmode, operands[1])); + } + else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0]))) + { + /* Handle the case where operand[0] is not a 'd' register, + and hence we can not directly move from the HILO register + into it. */ + rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1); + emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65))); + emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32))); + emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32))); + emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64))); + emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32))); + emit_insn (gen_iordi3 (scratch, scratch, scratch2)); + emit_insn (gen_movdi (operands[0], scratch)); + emit_insn (gen_rtx_USE (VOIDmode, operands[1])); + } + else + { + emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65))); + emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32))); + emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32))); + emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64))); + emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32))); + emit_insn (gen_iordi3 (operands[0], operands[0], scratch)); + emit_insn (gen_rtx_USE (VOIDmode, operands[1])); + } + DONE; + } + /* This handles moves between a float register and HI/LO. */ + emit_move_insn (scratch, operands[1]); + emit_move_insn (operands[0], scratch); + DONE; +}") + +;; 32-bit Integer moves + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "large_int" ""))] + "!TARGET_DEBUG_D_MODE && !TARGET_MIPS16" + [(set (match_dup 0) + (match_dup 2)) + (set (match_dup 0) + (ior:SI (match_dup 0) + (match_dup 3)))] + " +{ + operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); + operands[3] = GEN_INT (INTVAL (operands[1]) & 0x0000ffff); +}") + +;; Unlike most other insns, the move insns can't be split with +;; different predicates, because register spilling and other parts of +;; the compiler, have memoized the insn number already. + +(define_expand "movsi" + [(set (match_operand:SI 0 "nonimmediate_operand" "") + (match_operand:SI 1 "general_operand" ""))] + "" + " +{ + if (mips_split_addresses && mips_check_split (operands[1], SImode)) + { + enum machine_mode mode = GET_MODE (operands[0]); + rtx tem = ((reload_in_progress | reload_completed) + ? operands[0] : gen_reg_rtx (mode)); + + emit_insn (gen_rtx (SET, VOIDmode, tem, + gen_rtx (HIGH, mode, operands[1]))); + + operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]); + } + + /* If we are generating embedded PIC code, and we are referring to a + symbol in the .text section, we must use an offset from the start + of the function. */ + if (TARGET_EMBEDDED_PIC + && (GET_CODE (operands[1]) == LABEL_REF + || (GET_CODE (operands[1]) == SYMBOL_REF + && ! SYMBOL_REF_FLAG (operands[1])))) + { + rtx temp; + + temp = embedded_pic_offset (operands[1]); + temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx, + force_reg (SImode, temp)); + emit_move_insn (operands[0], force_reg (SImode, temp)); + DONE; + } + + /* If operands[1] is a constant address invalid for pic, then we need to + handle it just like LEGITIMIZE_ADDRESS does. */ + if (flag_pic && pic_address_needs_scratch (operands[1])) + { + rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0)); + rtx temp2 = XEXP (XEXP (operands[1], 0), 1); + + if (! SMALL_INT (temp2)) + temp2 = force_reg (SImode, temp2); + + emit_move_insn (operands[0], gen_rtx (PLUS, SImode, temp, temp2)); + DONE; + } + + /* On the mips16, we can handle a GP relative reference by adding in + $gp. We need to check the name to see whether this is a string + constant. */ + if (TARGET_MIPS16 + && register_operand (operands[0], SImode) + && GET_CODE (operands[1]) == SYMBOL_REF + && SYMBOL_REF_FLAG (operands[1])) + { + char *name = XSTR (operands[1], 0); + + if (name[0] != '*' + || strncmp (name + 1, LOCAL_LABEL_PREFIX, + sizeof LOCAL_LABEL_PREFIX - 1) != 0) + { + rtx base_reg; + + if (reload_in_progress || reload_completed) + { + /* We need to reload this address. In this case we + aren't going to have a chance to combine loading the + address with the load or store. That means that we + can either generate a 2 byte move followed by a 4 + byte addition, or a 2 byte load with a 4 byte entry + in the constant table. Since the entry in the + constant table might be shared, we're better off, on + average, loading the address from the constant table. */ + emit_move_insn (operands[0], + force_const_mem (SImode, operands[1])); + DONE; + } + + base_reg = gen_reg_rtx (Pmode); + emit_move_insn (base_reg, mips16_gp_pseudo_reg ()); + + emit_move_insn (operands[0], + gen_rtx (PLUS, Pmode, base_reg, + mips16_gp_offset (operands[1]))); + DONE; + } + } + + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], SImode) + && !register_operand (operands[1], SImode) + && (TARGET_MIPS16 + || GET_CODE (operands[1]) != CONST_INT + || INTVAL (operands[1]) != 0)) + { + rtx temp = force_reg (SImode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } +}") + +;; For mips16, we need a special case to handle storing $31 into +;; memory, since we don't have a constraint to match $31. This +;; instruction can be generated by save_restore_insns. + +(define_insn "" + [(set (match_operand:SI 0 "memory_operand" "R,m") + (reg:SI 31))] + "TARGET_MIPS16" + "* +{ + operands[1] = gen_rtx (REG, SImode, 31); + return mips_move_1word (operands, insn, FALSE); +}" + [(set_attr "type" "store") + (set_attr "mode" "SI") + (set_attr "length" "1,2")]) + +;; The difference between these two is whether or not ints are allowed +;; in FP registers (off by default, use -mdebugh to enable). + +(define_insn "movsi_internal1" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d") + (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a"))] + "TARGET_DEBUG_H_MODE && !TARGET_MIPS16 + && (register_operand (operands[0], SImode) + || register_operand (operands[1], SImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo") + (set_attr "mode" "SI") + (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1,1,1")]) + +(define_insn "movsi_internal2" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d") + (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))] + "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16 + && (register_operand (operands[0], SImode) + || register_operand (operands[1], SImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo") + (set_attr "mode" "SI") + (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,1,1")]) + +;; This is the mips16 movsi instruction. We accept a small integer as +;; the source if the destination is a GP memory reference. This is +;; because we want the combine pass to turn adding a GP reference to a +;; register into a direct GP reference, but the combine pass will pass +;; in the source as a constant if it finds an equivalent one. If the +;; instruction is recognized, reload will force the constant back out +;; into a register. + +(define_insn "" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,d,R,m,*d,*d") + (match_operand:SI 1 "move_operand" "d,d,y,S,K,N,s,R,m,d,d,*x,*a"))] + "TARGET_MIPS16 + && (register_operand (operands[0], SImode) + || register_operand (operands[1], SImode) + || (GET_CODE (operands[0]) == MEM + && GET_CODE (XEXP (operands[0], 0)) == PLUS + && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST + && mips16_gp_offset_p (XEXP (XEXP (operands[0], 0), 1)) + && GET_CODE (operands[1]) == CONST_INT + && (SMALL_INT (operands[1]) + || SMALL_INT_UNSIGNED (operands[1]))))" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "move,move,move,load,arith,arith,arith,load,load,store,store,hilo,hilo") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(const_int 1) + (const_int 1) + (const_int 1) + (const_int 2) + (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "") + (const_int 2) + (const_int 3)) + (if_then_else (match_operand:VOID 1 "m16_usym8_4" "") + (const_int 1) + (const_int 2)) + (const_int 1) + (const_int 2) + (const_int 1) + (const_int 2) + (const_int 1) + (const_int 1)])]) + +;; On the mips16, we can split lw $r,N($r) into an add and a load, +;; when the original load is a 4 byte instruction but the add and the +;; load are 2 2 byte instructions. + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (mem:SI (plus:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand" ""))))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && ((INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) >= -0x80) + || (INTVAL (operands[1]) >= 32 * 4 + && INTVAL (operands[1]) <= 31 * 4 + 0x7c) + || (INTVAL (operands[1]) >= 0 + && INTVAL (operands[1]) < 32 * 4 + && (INTVAL (operands[1]) & 3) != 0))" + [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (val < 0) + operands[2] = GEN_INT (0); + else if (val >= 32 * 4) + { + int off = val & 3; + + operands[1] = GEN_INT (0x7c + off); + operands[2] = GEN_INT (val - off - 0x7c); + } + else + { + int off = val & 3; + + operands[1] = GEN_INT (off); + operands[2] = GEN_INT (val - off); + } +}") + +;; On the mips16, we can split a load of certain constants into a load +;; and an add. This turns a 4 byte instruction into 2 2 byte +;; instructions. + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "const_int_operand" ""))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >= 0x100 + && INTVAL (operands[1]) <= 0xff + 0x7f" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] + " +{ + int val = INTVAL (operands[1]); + + operands[1] = GEN_INT (0xff); + operands[2] = GEN_INT (val - 0xff); +}") + +;; On the mips16, we can split a load of a negative constant into a +;; load and a neg. That's what mips_move_1word will generate anyhow. + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "const_int_operand" ""))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) > - 0x8000" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 0) (neg:SI (match_dup 0)))] + " +{ + operands[1] = GEN_INT (- INTVAL (operands[1])); +}") + +;; Reload HILO_REGNUM in SI mode. This needs a scratch register in +;; order to set the sign bit correctly in the HI register. + +(define_expand "reload_outsi" + [(set (match_operand:SI 0 "general_operand" "=b") + (match_operand:SI 1 "register_operand" "b")) + (clobber (match_operand:SI 2 "register_operand" "=&d"))] + "TARGET_64BIT || TARGET_MIPS16" + " +{ + if (TARGET_64BIT + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM) + { + emit_insn (gen_movsi (gen_rtx (REG, SImode, 65), operands[1])); + emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31))); + emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2])); + emit_insn (gen_rtx_USE (VOIDmode, operands[0])); + DONE; + } + /* Use a mult to reload LO on mips16. ??? This is hideous. */ + if (TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM) + { + emit_insn (gen_movsi (operands[2], GEN_INT (1))); + /* This is gen_mulsi3_internal, but we need to fill in the + scratch registers. */ + emit_insn (gen_rtx (PARALLEL, VOIDmode, + gen_rtvec (3, + gen_rtx (SET, VOIDmode, + operands[0], + gen_rtx (MULT, SImode, + operands[1], + operands[2])), + gen_rtx (CLOBBER, VOIDmode, + gen_rtx (REG, SImode, 64)), + gen_rtx (CLOBBER, VOIDmode, + gen_rtx (REG, SImode, 66))))); + DONE; + } + /* FIXME: I don't know how to get a value into the HI register. */ + if (GET_CODE (operands[0]) == REG + && (TARGET_MIPS16 ? M16_REG_P (REGNO (operands[0])) + : GP_REG_P (REGNO (operands[0])))) + { + emit_move_insn (operands[0], operands[1]); + DONE; + } + /* This handles moves between a float register and HI/LO. */ + emit_move_insn (operands[2], operands[1]); + emit_move_insn (operands[0], operands[2]); + DONE; +}") + +;; Reload a value into HI or LO. There is no mthi or mtlo on mips16, +;; so we use a mult. ??? This is hideous, and we ought to figure out +;; something better. + +(define_expand "reload_insi" + [(set (match_operand:SI 0 "register_operand" "=b") + (match_operand:SI 1 "register_operand" "b")) + (clobber (match_operand:SI 2 "register_operand" "=&d"))] + "TARGET_MIPS16" + " +{ + if (TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM) + { + emit_insn (gen_movsi (operands[2], GEN_INT (1))); + /* This is gen_mulsi3_internal, but we need to fill in the + scratch registers. */ + emit_insn (gen_rtx (PARALLEL, VOIDmode, + gen_rtvec (3, + gen_rtx (SET, VOIDmode, + operands[0], + gen_rtx (MULT, SImode, + operands[1], + operands[2])), + gen_rtx (CLOBBER, VOIDmode, + gen_rtx (REG, SImode, 64)), + gen_rtx (CLOBBER, VOIDmode, + gen_rtx (REG, SImode, 66))))); + DONE; + } + /* FIXME: I don't know how to get a value into the HI register. */ + emit_move_insn (operands[0], operands[1]); + DONE; +}") + +;; This insn handles moving CCmode values. It's really just a +;; slightly simplified copy of movsi_internal2, with additional cases +;; to move a condition register to a general register and to move +;; between the general registers and the floating point registers. + +(define_insn "movcc" + [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m") + (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store") + (set_attr "mode" "SI") + (set_attr "length" "2,1,1,2,1,2,1,1,1,1,2,1,2")]) + +;; Reload condition code registers. These need scratch registers. + +(define_expand "reload_incc" + [(set (match_operand:CC 0 "register_operand" "=z") + (match_operand:CC 1 "general_operand" "z")) + (clobber (match_operand:TF 2 "register_operand" "=&f"))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + " +{ + rtx source; + rtx fp1, fp2; + + /* This is called when are copying some value into a condition code + register. Operand 0 is the condition code register. Operand 1 + is the source. Operand 2 is a scratch register; we use TFmode + because we actually need two floating point registers. */ + if (! ST_REG_P (true_regnum (operands[0])) + || ! FP_REG_P (true_regnum (operands[2]))) + abort (); + + /* We need to get the source in SFmode so that the insn is + recognized. */ + if (GET_CODE (operands[1]) == MEM) + source = change_address (operands[1], SFmode, NULL_RTX); + else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG) + source = gen_rtx (REG, SFmode, true_regnum (operands[1])); + else + source = operands[1]; + + fp1 = gen_rtx (REG, SFmode, REGNO (operands[2])); + fp2 = gen_rtx (REG, SFmode, REGNO (operands[2]) + 1); + + emit_insn (gen_move_insn (fp1, source)); + emit_insn (gen_move_insn (fp2, gen_rtx (REG, SFmode, 0))); + emit_insn (gen_rtx (SET, VOIDmode, operands[0], + gen_rtx (LT, CCmode, fp2, fp1))); + + DONE; +}") + +(define_expand "reload_outcc" + [(set (match_operand:CC 0 "general_operand" "=z") + (match_operand:CC 1 "register_operand" "z")) + (clobber (match_operand:CC 2 "register_operand" "=&d"))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + " +{ + /* This is called when we are copying a condition code register out + to save it somewhere. Operand 0 should be the location we are + going to save it to. Operand 1 should be the condition code + register. Operand 2 should be a scratch general purpose register + created for us by reload. The mips_secondary_reload_class + function should have told reload that we don't need a scratch + register if the destination is a general purpose register anyhow. */ + if (ST_REG_P (true_regnum (operands[0])) + || GP_REG_P (true_regnum (operands[0])) + || ! ST_REG_P (true_regnum (operands[1])) + || ! GP_REG_P (true_regnum (operands[2]))) + abort (); + + /* All we have to do is copy the value from the condition code to + the data register, which movcc can handle, and then store the + value into the real final destination. */ + emit_insn (gen_move_insn (operands[2], operands[1])); + emit_insn (gen_move_insn (operands[0], operands[2])); + + DONE; +}") + +;; MIPS4 supports loading and storing a floating point register from +;; the sum of two general registers. We use two versions for each of +;; these four instructions: one where the two general registers are +;; SImode, and one where they are DImode. This is because general +;; registers will be in SImode when they hold 32 bit values, but, +;; since the 32 bit values are always sign extended, the [ls][wd]xc1 +;; instructions will still work correctly. + +;; ??? Perhaps it would be better to support these instructions by +;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since +;; these instructions can only be used to load and store floating +;; point registers, that would probably cause trouble in reload. + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "lwxc1\\t%0,%1(%2)" + [(set_attr "type" "load") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "lwxc1\\t%0,%1(%2)" + [(set_attr "type" "load") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ldxc1\\t%0,%1(%2)" + [(set_attr "type" "load") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ldxc1\\t%0,%1(%2)" + [(set_attr "type" "load") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (match_operand:SF 0 "register_operand" "=f"))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "swxc1\\t%0,%1(%2)" + [(set_attr "type" "store") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (match_operand:SF 0 "register_operand" "=f"))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "swxc1\\t%0,%1(%2)" + [(set_attr "type" "store") + (set_attr "mode" "SF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (match_operand:DF 0 "register_operand" "=f"))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "sdxc1\\t%0,%1(%2)" + [(set_attr "type" "store") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +(define_insn "" + [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d"))) + (match_operand:DF 0 "register_operand" "=f"))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "sdxc1\\t%0,%1(%2)" + [(set_attr "type" "store") + (set_attr "mode" "DF") + (set_attr "length" "1")]) + +;; 16-bit Integer moves + +;; Unlike most other insns, the move insns can't be split with +;; different predicates, because register spilling and other parts of +;; the compiler, have memoized the insn number already. +;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined + +(define_expand "movhi" + [(set (match_operand:HI 0 "nonimmediate_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" + " +{ + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], HImode) + && !register_operand (operands[1], HImode) + && (TARGET_MIPS16 + || (GET_CODE (operands[1]) != CONST_INT + || INTVAL (operands[1]) != 0))) + { + rtx temp = force_reg (HImode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } +}") + +;; The difference between these two is whether or not ints are allowed +;; in FP registers (off by default, use -mdebugh to enable). + +(define_insn "movhi_internal1" + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d") + (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))] + "TARGET_DEBUG_H_MODE && !TARGET_MIPS16 + && (register_operand (operands[0], HImode) + || register_operand (operands[1], HImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo") + (set_attr "mode" "HI") + (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")]) + +(define_insn "movhi_internal2" + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d") + (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))] + "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16 + && (register_operand (operands[0], HImode) + || register_operand (operands[1], HImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo") + (set_attr "mode" "HI") + (set_attr "length" "1,1,1,2,1,2,1,1,1,1")]) + +(define_insn "" + [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d") + (match_operand:HI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))] + "TARGET_MIPS16 + && (register_operand (operands[0], HImode) + || register_operand (operands[1], HImode))" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo") + (set_attr "mode" "HI") + (set_attr_alternative "length" + [(const_int 1) + (const_int 1) + (const_int 1) + (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "") + (const_int 2) + (const_int 3)) + (const_int 1) + (const_int 2) + (const_int 1) + (const_int 2) + (const_int 1)])]) + + +;; On the mips16, we can split lh $r,N($r) into an add and a load, +;; when the original load is a 4 byte instruction but the add and the +;; load are 2 2 byte instructions. + +(define_split + [(set (match_operand:HI 0 "register_operand" "") + (mem:HI (plus:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand" ""))))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && ((INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) >= -0x80) + || (INTVAL (operands[1]) >= 32 * 2 + && INTVAL (operands[1]) <= 31 * 2 + 0x7e) + || (INTVAL (operands[1]) >= 0 + && INTVAL (operands[1]) < 32 * 2 + && (INTVAL (operands[1]) & 1) != 0))" + [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (val < 0) + operands[2] = GEN_INT (0); + else if (val >= 32 * 2) + { + int off = val & 1; + + operands[1] = GEN_INT (0x7e + off); + operands[2] = GEN_INT (val - off - 0x7e); + } + else + { + int off = val & 1; + + operands[1] = GEN_INT (off); + operands[2] = GEN_INT (val - off); + } +}") + +;; 8-bit Integer moves + +;; Unlike most other insns, the move insns can't be split with +;; different predicates, because register spilling and other parts of +;; the compiler, have memoized the insn number already. +;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined + +(define_expand "movqi" + [(set (match_operand:QI 0 "nonimmediate_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], QImode) + && !register_operand (operands[1], QImode) + && (TARGET_MIPS16 + || (GET_CODE (operands[1]) != CONST_INT + || INTVAL (operands[1]) != 0))) + { + rtx temp = force_reg (QImode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } +}") + +;; The difference between these two is whether or not ints are allowed +;; in FP registers (off by default, use -mdebugh to enable). + +(define_insn "movqi_internal1" + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d") + (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))] + "TARGET_DEBUG_H_MODE && !TARGET_MIPS16 + && (register_operand (operands[0], QImode) + || register_operand (operands[1], QImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo") + (set_attr "mode" "QI") + (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")]) + +(define_insn "movqi_internal2" + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d") + (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))] + "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16 + && (register_operand (operands[0], QImode) + || register_operand (operands[1], QImode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo") + (set_attr "mode" "QI") + (set_attr "length" "1,1,1,2,1,2,1,1,1,1")]) + +(define_insn "" + [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d") + (match_operand:QI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))] + "TARGET_MIPS16 + && (register_operand (operands[0], QImode) + || register_operand (operands[1], QImode))" + "* return mips_move_1word (operands, insn, TRUE);" + [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo") + (set_attr "mode" "QI") + (set_attr_alternative "length" + [(const_int 1) + (const_int 1) + (const_int 1) + (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "") + (const_int 1) + (const_int 2)) + (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "") + (const_int 2) + (const_int 3)) + (const_int 1) + (const_int 2) + (const_int 1) + (const_int 2) + (const_int 1)])]) + + +;; On the mips16, we can split lb $r,N($r) into an add and a load, +;; when the original load is a 4 byte instruction but the add and the +;; load are 2 2 byte instructions. + +(define_split + [(set (match_operand:QI 0 "register_operand" "") + (mem:QI (plus:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand" ""))))] + "TARGET_MIPS16 && reload_completed + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == CONST_INT + && ((INTVAL (operands[1]) < 0 + && INTVAL (operands[1]) >= -0x80) + || (INTVAL (operands[1]) >= 32 + && INTVAL (operands[1]) <= 31 + 0x7f))" + [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))] + " +{ + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (val < 0) + operands[2] = GEN_INT (0); + else + { + operands[1] = GEN_INT (0x7f); + operands[2] = GEN_INT (val - 0x7f); + } +}") + +;; 32-bit floating point moves + +(define_expand "movsf" + [(set (match_operand:SF 0 "nonimmediate_operand" "") + (match_operand:SF 1 "general_operand" ""))] + "" + " +{ + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], SFmode) + && !register_operand (operands[1], SFmode) + && (TARGET_MIPS16 + || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) + && operands[1] != CONST0_RTX (SFmode)))) + { + rtx temp = force_reg (SFmode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } +}") + +(define_insn "movsf_internal1" + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m") + (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))] + "TARGET_HARD_FLOAT + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) + || operands[1] == CONST0_RTX (SFmode))" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store") + (set_attr "mode" "SF") + (set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")]) + + +(define_insn "movsf_internal2" + [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m") + (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))] + "TARGET_SOFT_FLOAT && !TARGET_MIPS16 + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) + || operands[1] == CONST0_RTX (SFmode))" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "move,load,load,store,store") + (set_attr "mode" "SF") + (set_attr "length" "1,1,2,1,2")]) + +(define_insn "" + [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,d,R,m") + (match_operand:SF 1 "general_operand" "d,d,y,R,Fm,d,d"))] + "TARGET_MIPS16 + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode))" + "* return mips_move_1word (operands, insn, FALSE);" + [(set_attr "type" "move,move,move,load,load,store,store") + (set_attr "mode" "SF") + (set_attr "length" "1,1,1,1,2,1,2")]) + + +;; 64-bit floating point moves + +(define_expand "movdf" + [(set (match_operand:DF 0 "nonimmediate_operand" "") + (match_operand:DF 1 "general_operand" ""))] + "" + " +{ + if ((reload_in_progress | reload_completed) == 0 + && !register_operand (operands[0], DFmode) + && !register_operand (operands[1], DFmode) + && (TARGET_MIPS16 + || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) + && operands[1] != CONST0_RTX (DFmode)))) + { + rtx temp = force_reg (DFmode, operands[1]); + emit_move_insn (operands[0], temp); + DONE; + } +}") + +(define_insn "movdf_internal1" + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,To,f,*f,*d,*d,*d,*d,*R,*T") + (match_operand:DF 1 "general_operand" "f,R,To,fG,fG,F,*d,*f,*d*G,*R,*T*F,*d,*d"))] + "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT) + && TARGET_DOUBLE_FLOAT + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) + || operands[1] == CONST0_RTX (DFmode))" + "* return mips_move_2words (operands, insn); " + [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store") + (set_attr "mode" "DF") + (set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")]) + +(define_insn "movdf_internal1a" + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,To,To,f,*d,*d,*d,*To,*R") + (match_operand:DF 1 "general_operand" " f,To,f,G,f,G,F,*F,*To,*R,*d,*d"))] + "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT) + && TARGET_DOUBLE_FLOAT + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode) + || (GET_CODE (operands [0]) == MEM + && ((GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) == 0) + || operands[1] == CONST0_RTX (DFmode))))" + "* return mips_move_2words (operands, insn); " + [(set_attr "type" "move,load,store,store,store,store,load,load,load,load,store,store") + (set_attr "mode" "DF") + (set_attr "length" "1,2,1,1,2,2,2,2,2,1,2,1")]) + +(define_insn "movdf_internal2" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,To") + (match_operand:DF 1 "general_operand" "dG,R,ToF,d,d"))] + "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode) + || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0) + || operands[1] == CONST0_RTX (DFmode))" + "* return mips_move_2words (operands, insn); " + [(set_attr "type" "move,load,load,store,store") + (set_attr "mode" "DF") + (set_attr "length" "2,2,4,2,4")]) + +(define_insn "" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,d,R,To") + (match_operand:DF 1 "general_operand" "d,d,y,R,ToF,d,d"))] + "TARGET_MIPS16 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "* return mips_move_2words (operands, insn);" + [(set_attr "type" "move,move,move,load,load,store,store") + (set_attr "mode" "DF") + (set_attr "length" "2,2,2,2,4,2,4")]) + +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "register_operand" ""))] + "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))] + "") + +;; Instructions to load the global pointer register. +;; This is volatile to make sure that the scheduler won't move any symbol_ref +;; uses in front of it. All symbol_refs implicitly use the gp reg. + +(define_insn "loadgp" + [(set (reg:DI 28) + (unspec_volatile:DI [(match_operand:DI 0 "address_operand" "") + (match_operand:DI 1 "register_operand" "")] 2)) + (clobber (reg:DI 1))] + "" + "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]" + [(set_attr "type" "move") + (set_attr "mode" "DI") + (set_attr "length" "3")]) + +;; Block moves, see mips.c for more details. +;; Argument 0 is the destination +;; Argument 1 is the source +;; Argument 2 is the length +;; Argument 3 is the alignment + +(define_expand "movstrsi" + [(parallel [(set (match_operand:BLK 0 "general_operand" "") + (match_operand:BLK 1 "general_operand" "")) + (use (match_operand:SI 2 "arith32_operand" "")) + (use (match_operand:SI 3 "immediate_operand" ""))])] + "!TARGET_MIPS16" + " +{ + if (operands[0]) /* avoid unused code messages */ + { + expand_block_move (operands); + DONE; + } +}") + +;; Insn generated by block moves + +(define_insn "movstrsi_internal" + [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination + (match_operand:BLK 1 "memory_operand" "o")) ;; source + (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 + (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 + (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 + (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 + (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move + (use (match_operand:SI 3 "small_int" "I")) ;; alignment + (use (const_int 0))] ;; normal block move + "" + "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);" + [(set_attr "type" "store") + (set_attr "mode" "none") + (set_attr "length" "20")]) + +;; We need mips16 versions, because an offset from the stack pointer +;; is not offsettable, since the stack pointer can only handle 4 and 8 +;; byte loads. + +(define_insn "" + [(set (match_operand:BLK 0 "memory_operand" "=d") ;; destination + (match_operand:BLK 1 "memory_operand" "d")) ;; source + (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 + (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 + (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 + (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 + (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move + (use (match_operand:SI 3 "small_int" "I")) ;; alignment + (use (const_int 0))] ;; normal block move + "TARGET_MIPS16" + "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);" + [(set_attr "type" "multi") + (set_attr "mode" "none") + (set_attr "length" "20")]) + +(define_insn "" + [(set (match_operand:BLK 0 "memory_operand" "=d") ;; destination + (match_operand:BLK 1 "memory_operand" "o")) ;; source + (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 + (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 + (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 + (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 + (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move + (use (match_operand:SI 3 "small_int" "I")) ;; alignment + (use (const_int 0))] ;; normal block move + "TARGET_MIPS16" + "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);" + [(set_attr "type" "multi") + (set_attr "mode" "none") + (set_attr "length" "20")]) + +(define_insn "" + [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination + (match_operand:BLK 1 "memory_operand" "d")) ;; source + (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 + (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 + (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 + (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 + (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move + (use (match_operand:SI 3 "small_int" "I")) ;; alignment + (use (const_int 0))] ;; normal block move + "TARGET_MIPS16" + "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);" + [(set_attr "type" "multi") + (set_attr "mode" "none") + (set_attr "length" "20")]) + +;; Split a block move into 2 parts, the first part is everything +;; except for the last move, and the second part is just the last +;; store, which is exactly 1 instruction (ie, not a usw), so it can +;; fill a delay slot. This also prevents a bug in delayed branches +;; from showing up, which reuses one of the registers in our clobbers. + +(define_split + [(set (mem:BLK (match_operand:SI 0 "register_operand" "")) + (mem:BLK (match_operand:SI 1 "register_operand" ""))) + (clobber (match_operand:SI 4 "register_operand" "")) + (clobber (match_operand:SI 5 "register_operand" "")) + (clobber (match_operand:SI 6 "register_operand" "")) + (clobber (match_operand:SI 7 "register_operand" "")) + (use (match_operand:SI 2 "small_int" "")) + (use (match_operand:SI 3 "small_int" "")) + (use (const_int 0))] + + "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0" + + ;; All but the last move + [(parallel [(set (mem:BLK (match_dup 0)) + (mem:BLK (match_dup 1))) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (clobber (match_dup 6)) + (clobber (match_dup 7)) + (use (match_dup 2)) + (use (match_dup 3)) + (use (const_int 1))]) + + ;; The last store, so it can fill a delay slot + (parallel [(set (mem:BLK (match_dup 0)) + (mem:BLK (match_dup 1))) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (clobber (match_dup 6)) + (clobber (match_dup 7)) + (use (match_dup 2)) + (use (match_dup 3)) + (use (const_int 2))])] + + "") + +(define_insn "movstrsi_internal2" + [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination + (match_operand:BLK 1 "memory_operand" "o")) ;; source + (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 + (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 + (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 + (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 + (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move + (use (match_operand:SI 3 "small_int" "I")) ;; alignment + (use (const_int 1))] ;; all but last store + "" + "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);" + [(set_attr "type" "store") + (set_attr "mode" "none") + (set_attr "length" "20")]) + +(define_insn "" + [(set (match_operand:BLK 0 "memory_operand" "=d") ;; destination + (match_operand:BLK 1 "memory_operand" "d")) ;; source + (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 + (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 + (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 + (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 + (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move + (use (match_operand:SI 3 "small_int" "I")) ;; alignment + (use (const_int 1))] ;; all but last store + "TARGET_MIPS16" + "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);" + [(set_attr "type" "multi") + (set_attr "mode" "none") + (set_attr "length" "20")]) + +(define_insn "movstrsi_internal3" + [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination + (match_operand:BLK 1 "memory_operand" "Ro")) ;; source + (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 + (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 + (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 + (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 + (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move + (use (match_operand:SI 3 "small_int" "I")) ;; alignment + (use (const_int 2))] ;; just last store of block move + "" + "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);" + [(set_attr "type" "store") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:BLK 0 "memory_operand" "=d") ;; destination + (match_operand:BLK 1 "memory_operand" "d")) ;; source + (clobber (match_scratch:SI 4 "=&d")) ;; temp 1 + (clobber (match_scratch:SI 5 "=&d")) ;; temp 2 + (clobber (match_scratch:SI 6 "=&d")) ;; temp 3 + (clobber (match_scratch:SI 7 "=&d")) ;; temp 4 + (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move + (use (match_operand:SI 3 "small_int" "I")) ;; alignment + (use (const_int 2))] ;; just last store of block move + "TARGET_MIPS16" + "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);" + [(set_attr "type" "store") + (set_attr "mode" "none") + (set_attr "length" "1")]) + + +;; +;; .................... +;; +;; SHIFTS +;; +;; .................... + +;; Many of these instructions uses trivial define_expands, because we +;; want to use a different set of constraints when TARGET_MIPS16. + +(define_expand "ashlsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + " +{ + /* On the mips16, a shift of more than 8 is a four byte instruction, + so, for a shift between 8 and 16, it is just as fast to do two + shifts of 8 or less. If there is a lot of shifting going on, we + may win in CSE. Otherwise combine will put the shifts back + together again. This can be called by function_arg, so we must + be careful not to allocate a new register if we've reached the + reload pass. */ + if (TARGET_MIPS16 + && optimize + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16 + && ! reload_in_progress + && ! reload_completed) + { + rtx temp = gen_reg_rtx (SImode); + + emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8))); + emit_insn (gen_ashlsi3_internal2 (operands[0], temp, + GEN_INT (INTVAL (operands[2]) - 8))); + DONE; + } +}") + +(define_insn "ashlsi3_internal1" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashift:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "!TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"sll\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "ashlsi3_internal2" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ashift:SI (match_operand:SI 1 "register_operand" "0,d") + (match_operand:SI 2 "arith_operand" "d,I")))] + "TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"sll\\t%0,%2\"; + + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"sll\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "") + (const_int 1) + (const_int 2))])]) + +;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (ashift:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_MIPS16 + && reload_completed + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16" + [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8))) + (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))] +" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) - 8); +}") + +(define_expand "ashldi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:SI 2 "arith_operand" ""))) + (clobber (match_dup 3))])] + "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)" + " +{ + if (TARGET_64BIT) + { + /* On the mips16, a shift of more than 8 is a four byte + instruction, so, for a shift between 8 and 16, it is just as + fast to do two shifts of 8 or less. If there is a lot of + shifting going on, we may win in CSE. Otherwise combine will + put the shifts back together again. This can be called by + function_arg, so we must be careful not to allocate a new + register if we've reached the reload pass. */ + if (TARGET_MIPS16 + && optimize + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16 + && ! reload_in_progress + && ! reload_completed) + { + rtx temp = gen_reg_rtx (DImode); + + emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8))); + emit_insn (gen_ashldi3_internal4 (operands[0], temp, + GEN_INT (INTVAL (operands[2]) - 8))); + DONE; + } + + emit_insn (gen_ashldi3_internal4 (operands[0], operands[1], + operands[2])); + DONE; + } + + operands[3] = gen_reg_rtx (SImode); +}") + + +(define_insn "ashldi3_internal" + [(set (match_operand:DI 0 "register_operand" "=&d") + (ashift:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" + "* +{ + operands[4] = const0_rtx; + dslots_jump_total += 3; + dslots_jump_filled += 2; + + return \"sll\\t%3,%2,26\\n\\ +\\tbgez\\t%3,1f\\n\\ +\\tsll\\t%M0,%L1,%2\\n\\ +\\t%(b\\t3f\\n\\ +\\tmove\\t%L0,%z4%)\\n\\ +\\n\\ +1:\\n\\ +\\t%(beq\\t%3,%z4,2f\\n\\ +\\tsll\\t%M0,%M1,%2%)\\n\\ +\\n\\ +\\tsubu\\t%3,%z4,%2\\n\\ +\\tsrl\\t%3,%L1,%3\\n\\ +\\tor\\t%M0,%M0,%3\\n\\ +2:\\n\\ +\\tsll\\t%L0,%L1,%2\\n\\ +3:\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "SI") + (set_attr "length" "12")]) + + +(define_insn "ashldi3_internal2" + [(set (match_operand:DI 0 "register_operand" "=d") + (ashift:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "IJK"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && (INTVAL (operands[2]) & 32) != 0" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + operands[4] = const0_rtx; + return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 32) != 0" + + [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) + (set (subreg:SI (match_dup 0) 0) (const_int 0))] + + "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 32) != 0" + + [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) + (set (subreg:SI (match_dup 0) 1) (const_int 0))] + + "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") + + +(define_insn "ashldi3_internal3" + [(set (match_operand:DI 0 "register_operand" "=d") + (ashift:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "IJK"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + "* +{ + int amount = INTVAL (operands[2]); + + operands[2] = GEN_INT ((amount & 31)); + operands[4] = const0_rtx; + operands[5] = GEN_INT (((-amount) & 31)); + + return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + + [(set (subreg:SI (match_dup 0) 1) + (ashift:SI (subreg:SI (match_dup 1) 1) + (match_dup 2))) + + (set (match_dup 3) + (lshiftrt:SI (subreg:SI (match_dup 1) 0) + (match_dup 4))) + + (set (subreg:SI (match_dup 0) 1) + (ior:SI (subreg:SI (match_dup 0) 1) + (match_dup 3))) + + (set (subreg:SI (match_dup 0) 0) + (ashift:SI (subreg:SI (match_dup 1) 0) + (match_dup 2)))] + " +{ + int amount = INTVAL (operands[2]); + operands[2] = GEN_INT ((amount & 31)); + operands[4] = GEN_INT (((-amount) & 31)); +}") + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + + [(set (subreg:SI (match_dup 0) 0) + (ashift:SI (subreg:SI (match_dup 1) 0) + (match_dup 2))) + + (set (match_dup 3) + (lshiftrt:SI (subreg:SI (match_dup 1) 1) + (match_dup 4))) + + (set (subreg:SI (match_dup 0) 0) + (ior:SI (subreg:SI (match_dup 0) 0) + (match_dup 3))) + + (set (subreg:SI (match_dup 0) 1) + (ashift:SI (subreg:SI (match_dup 1) 1) + (match_dup 2)))] + " +{ + int amount = INTVAL (operands[2]); + operands[2] = GEN_INT ((amount & 31)); + operands[4] = GEN_INT (((-amount) & 31)); +}") + + +(define_insn "ashldi3_internal4" + [(set (match_operand:DI 0 "register_operand" "=d") + (ashift:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"dsll\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashift:DI (match_operand:DI 1 "se_register_operand" "0,d") + (match_operand:SI 2 "arith_operand" "d,I")))] + "TARGET_64BIT && TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"dsll\\t%0,%2\"; + + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"dsll\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "") + (const_int 1) + (const_int 2))])]) + + +;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_MIPS16 && TARGET_64BIT + && reload_completed + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16" + [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8))) + (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))] +" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) - 8); +}") + +(define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + " +{ + /* On the mips16, a shift of more than 8 is a four byte instruction, + so, for a shift between 8 and 16, it is just as fast to do two + shifts of 8 or less. If there is a lot of shifting going on, we + may win in CSE. Otherwise combine will put the shifts back + together again. */ + if (TARGET_MIPS16 + && optimize + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16) + { + rtx temp = gen_reg_rtx (SImode); + + emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8))); + emit_insn (gen_ashrsi3_internal2 (operands[0], temp, + GEN_INT (INTVAL (operands[2]) - 8))); + DONE; + } +}") + +(define_insn "ashrsi3_internal1" + [(set (match_operand:SI 0 "register_operand" "=d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "!TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"sra\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "ashrsi3_internal2" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") + (match_operand:SI 2 "arith_operand" "d,I")))] + "TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"sra\\t%0,%2\"; + + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"sra\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "") + (const_int 1) + (const_int 2))])]) + + +;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_MIPS16 + && reload_completed + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16" + [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8))) + (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] +" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) - 8); +}") + +(define_expand "ashrdi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:SI 2 "arith_operand" ""))) + (clobber (match_dup 3))])] + "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)" + " +{ + if (TARGET_64BIT) + { + /* On the mips16, a shift of more than 8 is a four byte + instruction, so, for a shift between 8 and 16, it is just as + fast to do two shifts of 8 or less. If there is a lot of + shifting going on, we may win in CSE. Otherwise combine will + put the shifts back together again. */ + if (TARGET_MIPS16 + && optimize + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16) + { + rtx temp = gen_reg_rtx (DImode); + + emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8))); + emit_insn (gen_ashrdi3_internal4 (operands[0], temp, + GEN_INT (INTVAL (operands[2]) - 8))); + DONE; + } + + emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1], + operands[2])); + DONE; + } + + operands[3] = gen_reg_rtx (SImode); +}") + + +(define_insn "ashrdi3_internal" + [(set (match_operand:DI 0 "register_operand" "=&d") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" + "* +{ + operands[4] = const0_rtx; + dslots_jump_total += 3; + dslots_jump_filled += 2; + + return \"sll\\t%3,%2,26\\n\\ +\\tbgez\\t%3,1f\\n\\ +\\tsra\\t%L0,%M1,%2\\n\\ +\\t%(b\\t3f\\n\\ +\\tsra\\t%M0,%M1,31%)\\n\\ +\\n\\ +1:\\n\\ +\\t%(beq\\t%3,%z4,2f\\n\\ +\\tsrl\\t%L0,%L1,%2%)\\n\\ +\\n\\ +\\tsubu\\t%3,%z4,%2\\n\\ +\\tsll\\t%3,%M1,%3\\n\\ +\\tor\\t%L0,%L0,%3\\n\\ +2:\\n\\ +\\tsra\\t%M0,%M1,%2\\n\\ +3:\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "12")]) + + +(define_insn "ashrdi3_internal2" + [(set (match_operand:DI 0 "register_operand" "=d") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "IJK"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 32) != 0" + + [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) + (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))] + + "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 32) != 0" + + [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) + (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))] + + "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") + + +(define_insn "ashrdi3_internal3" + [(set (match_operand:DI 0 "register_operand" "=d") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "IJK"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + "* +{ + int amount = INTVAL (operands[2]); + + operands[2] = GEN_INT ((amount & 31)); + operands[4] = GEN_INT (((-amount) & 31)); + + return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + + [(set (subreg:SI (match_dup 0) 0) + (lshiftrt:SI (subreg:SI (match_dup 1) 0) + (match_dup 2))) + + (set (match_dup 3) + (ashift:SI (subreg:SI (match_dup 1) 1) + (match_dup 4))) + + (set (subreg:SI (match_dup 0) 0) + (ior:SI (subreg:SI (match_dup 0) 0) + (match_dup 3))) + + (set (subreg:SI (match_dup 0) 1) + (ashiftrt:SI (subreg:SI (match_dup 1) 1) + (match_dup 2)))] + " +{ + int amount = INTVAL (operands[2]); + operands[2] = GEN_INT ((amount & 31)); + operands[4] = GEN_INT (((-amount) & 31)); +}") + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + + [(set (subreg:SI (match_dup 0) 1) + (lshiftrt:SI (subreg:SI (match_dup 1) 1) + (match_dup 2))) + + (set (match_dup 3) + (ashift:SI (subreg:SI (match_dup 1) 0) + (match_dup 4))) + + (set (subreg:SI (match_dup 0) 1) + (ior:SI (subreg:SI (match_dup 0) 1) + (match_dup 3))) + + (set (subreg:SI (match_dup 0) 0) + (ashiftrt:SI (subreg:SI (match_dup 1) 0) + (match_dup 2)))] + " +{ + int amount = INTVAL (operands[2]); + operands[2] = GEN_INT ((amount & 31)); + operands[4] = GEN_INT (((-amount) & 31)); +}") + + +(define_insn "ashrdi3_internal4" + [(set (match_operand:DI 0 "register_operand" "=d") + (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"dsra\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0") + (match_operand:SI 2 "arith_operand" "d,I")))] + "TARGET_64BIT && TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"dsra\\t%0,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "") + (const_int 1) + (const_int 2))])]) + +;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_MIPS16 && TARGET_64BIT + && reload_completed + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16" + [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8))) + (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))] +" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) - 8); +}") + +(define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "" + " +{ + /* On the mips16, a shift of more than 8 is a four byte instruction, + so, for a shift between 8 and 16, it is just as fast to do two + shifts of 8 or less. If there is a lot of shifting going on, we + may win in CSE. Otherwise combine will put the shifts back + together again. */ + if (TARGET_MIPS16 + && optimize + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16) + { + rtx temp = gen_reg_rtx (SImode); + + emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8))); + emit_insn (gen_lshrsi3_internal2 (operands[0], temp, + GEN_INT (INTVAL (operands[2]) - 8))); + DONE; + } +}") + +(define_insn "lshrsi3_internal1" + [(set (match_operand:SI 0 "register_operand" "=d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "!TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"srl\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "lshrsi3_internal2" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d") + (match_operand:SI 2 "arith_operand" "d,I")))] + "TARGET_MIPS16" + "* +{ + if (which_alternative == 0) + return \"srl\\t%0,%2\"; + + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"srl\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "") + (const_int 1) + (const_int 2))])]) + + +;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_MIPS16 + && reload_completed + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16" + [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8))) + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] +" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) - 8); +}") + +;; If we load a byte on the mips16 as a bitfield, the resulting +;; sequence of instructions is too complicated for combine, because it +;; involves four instructions: a load, a shift, a constant load into a +;; register, and an and (the key problem here is that the mips16 does +;; not have and immediate). We recognize a shift of a load in order +;; to make it simple enough for combine to understand. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (lshiftrt:SI (match_operand:SI 1 "memory_operand" "R,m") + (match_operand:SI 2 "immediate_operand" "I,I")))] + "TARGET_MIPS16" + "lw\\t%0,%1\;srl\\t%0,%2" + [(set_attr "type" "load") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "") + (const_int 2) + (const_int 3)) + (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "") + (const_int 3) + (const_int 4))])]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (lshiftrt:SI (match_operand:SI 1 "memory_operand" "") + (match_operand:SI 2 "immediate_operand" "")))] + "TARGET_MIPS16" + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] + "") + +(define_expand "lshrdi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:SI 2 "arith_operand" ""))) + (clobber (match_dup 3))])] + "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)" + " +{ + if (TARGET_64BIT) + { + /* On the mips16, a shift of more than 8 is a four byte + instruction, so, for a shift between 8 and 16, it is just as + fast to do two shifts of 8 or less. If there is a lot of + shifting going on, we may win in CSE. Otherwise combine will + put the shifts back together again. */ + if (TARGET_MIPS16 + && optimize + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16) + { + rtx temp = gen_reg_rtx (DImode); + + emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8))); + emit_insn (gen_lshrdi3_internal4 (operands[0], temp, + GEN_INT (INTVAL (operands[2]) - 8))); + DONE; + } + + emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1], + operands[2])); + DONE; + } + + operands[3] = gen_reg_rtx (SImode); +}") + + +(define_insn "lshrdi3_internal" + [(set (match_operand:DI 0 "register_operand" "=&d") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16" + "* +{ + operands[4] = const0_rtx; + dslots_jump_total += 3; + dslots_jump_filled += 2; + + return \"sll\\t%3,%2,26\\n\\ +\\tbgez\\t%3,1f\\n\\ +\\tsrl\\t%L0,%M1,%2\\n\\ +\\t%(b\\t3f\\n\\ +\\tmove\\t%M0,%z4%)\\n\\ +\\n\\ +1:\\n\\ +\\t%(beq\\t%3,%z4,2f\\n\\ +\\tsrl\\t%L0,%L1,%2%)\\n\\ +\\n\\ +\\tsubu\\t%3,%z4,%2\\n\\ +\\tsll\\t%3,%M1,%3\\n\\ +\\tor\\t%L0,%L0,%3\\n\\ +2:\\n\\ +\\tsrl\\t%M0,%M1,%2\\n\\ +3:\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "12")]) + + +(define_insn "lshrdi3_internal2" + [(set (match_operand:DI 0 "register_operand" "=d") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "IJK"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && (INTVAL (operands[2]) & 32) != 0" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + operands[4] = const0_rtx; + return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 32) != 0" + + [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) + (set (subreg:SI (match_dup 0) 1) (const_int 0))] + + "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 32) != 0" + + [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) + (set (subreg:SI (match_dup 0) 0) (const_int 0))] + + "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") + + +(define_insn "lshrdi3_internal3" + [(set (match_operand:DI 0 "register_operand" "=d") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "IJK"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + "* +{ + int amount = INTVAL (operands[2]); + + operands[2] = GEN_INT ((amount & 31)); + operands[4] = GEN_INT (((-amount) & 31)); + + return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\"; +}" + [(set_attr "type" "darith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + + [(set (subreg:SI (match_dup 0) 0) + (lshiftrt:SI (subreg:SI (match_dup 1) 0) + (match_dup 2))) + + (set (match_dup 3) + (ashift:SI (subreg:SI (match_dup 1) 1) + (match_dup 4))) + + (set (subreg:SI (match_dup 0) 0) + (ior:SI (subreg:SI (match_dup 0) 0) + (match_dup 3))) + + (set (subreg:SI (match_dup 0) 1) + (lshiftrt:SI (subreg:SI (match_dup 1) 1) + (match_dup 2)))] + " +{ + int amount = INTVAL (operands[2]); + operands[2] = GEN_INT ((amount & 31)); + operands[4] = GEN_INT (((-amount) & 31)); +}") + + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "small_int" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT + && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER + && (INTVAL (operands[2]) & 63) < 32 + && (INTVAL (operands[2]) & 63) != 0" + + [(set (subreg:SI (match_dup 0) 1) + (lshiftrt:SI (subreg:SI (match_dup 1) 1) + (match_dup 2))) + + (set (match_dup 3) + (ashift:SI (subreg:SI (match_dup 1) 0) + (match_dup 4))) + + (set (subreg:SI (match_dup 0) 1) + (ior:SI (subreg:SI (match_dup 0) 1) + (match_dup 3))) + + (set (subreg:SI (match_dup 0) 0) + (lshiftrt:SI (subreg:SI (match_dup 1) 0) + (match_dup 2)))] + " +{ + int amount = INTVAL (operands[2]); + operands[2] = GEN_INT ((amount & 31)); + operands[4] = GEN_INT (((-amount) & 31)); +}") + + +(define_insn "lshrdi3_internal4" + [(set (match_operand:DI 0 "register_operand" "=d") + (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "TARGET_64BIT && !TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"dsrl\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0") + (match_operand:SI 2 "arith_operand" "d,I")))] + "TARGET_64BIT && TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"dsrl\\t%0,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "") + (const_int 1) + (const_int 2))])]) + +;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_MIPS16 + && reload_completed + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16" + [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8))) + (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))] +" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) - 8); +}") + + +;; +;; .................... +;; +;; COMPARISONS +;; +;; .................... + +;; Flow here is rather complex: +;; +;; 1) The cmp{si,di,sf,df} routine is called. It deposits the +;; arguments into the branch_cmp array, and the type into +;; branch_type. No RTL is generated. +;; +;; 2) The appropriate branch define_expand is called, which then +;; creates the appropriate RTL for the comparison and branch. +;; Different CC modes are used, based on what type of branch is +;; done, so that we can constrain things appropriately. There +;; are assumptions in the rest of GCC that break if we fold the +;; operands into the branchs for integer operations, and use cc0 +;; for floating point, so we use the fp status register instead. +;; If needed, an appropriate temporary is created to hold the +;; of the integer compare. + +(define_expand "cmpsi" + [(set (cc0) + (compare:CC (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "arith_operand" "")))] + "" + " +{ + if (operands[0]) /* avoid unused code message */ + { + branch_cmp[0] = operands[0]; + branch_cmp[1] = operands[1]; + branch_type = CMP_SI; + DONE; + } +}") + +(define_expand "tstsi" + [(set (cc0) + (match_operand:SI 0 "register_operand" ""))] + "" + " +{ + if (operands[0]) /* avoid unused code message */ + { + branch_cmp[0] = operands[0]; + branch_cmp[1] = const0_rtx; + branch_type = CMP_SI; + DONE; + } +}") + +(define_expand "cmpdi" + [(set (cc0) + (compare:CC (match_operand:DI 0 "se_register_operand" "") + (match_operand:DI 1 "se_arith_operand" "")))] + "TARGET_64BIT" + " +{ + if (operands[0]) /* avoid unused code message */ + { + branch_cmp[0] = operands[0]; + branch_cmp[1] = operands[1]; + branch_type = CMP_DI; + DONE; + } +}") + +(define_expand "tstdi" + [(set (cc0) + (match_operand:DI 0 "se_register_operand" ""))] + "TARGET_64BIT" + " +{ + if (operands[0]) /* avoid unused code message */ + { + branch_cmp[0] = operands[0]; + branch_cmp[1] = const0_rtx; + branch_type = CMP_DI; + DONE; + } +}") + +(define_expand "cmpdf" + [(set (cc0) + (compare:CC (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "register_operand" "")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + " +{ + if (operands[0]) /* avoid unused code message */ + { + branch_cmp[0] = operands[0]; + branch_cmp[1] = operands[1]; + branch_type = CMP_DF; + DONE; + } +}") + +(define_expand "cmpsf" + [(set (cc0) + (compare:CC (match_operand:SF 0 "register_operand" "") + (match_operand:SF 1 "register_operand" "")))] + "TARGET_HARD_FLOAT" + " +{ + if (operands[0]) /* avoid unused code message */ + { + branch_cmp[0] = operands[0]; + branch_cmp[1] = operands[1]; + branch_type = CMP_SF; + DONE; + } +}") + + +;; +;; .................... +;; +;; CONDITIONAL BRANCHES +;; +;; .................... + +(define_insn "branch_fp_ne" + [(set (pc) + (if_then_else (ne:CC (match_operand:CC 0 "register_operand" "z") + (const_int 0)) + (match_operand 1 "pc_or_label_operand" "") + (match_operand 2 "pc_or_label_operand" "")))] + "TARGET_HARD_FLOAT" + "* +{ + mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); + return (operands[1] != pc_rtx) ? \"%*bc1t%?\\t%Z0%1\" : \"%*bc1f%?\\t%Z0%2\"; +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "branch_fp_eq" + [(set (pc) + (if_then_else (eq:CC (match_operand:CC 0 "register_operand" "z") + (const_int 0)) + (match_operand 1 "pc_or_label_operand" "") + (match_operand 2 "pc_or_label_operand" "")))] + "TARGET_HARD_FLOAT" + "* +{ + mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); + return (operands[1] != pc_rtx) ? \"%*bc1f%?\\t%Z0%1\" : \"%*bc1t%?\\t%Z0%2\"; +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "branch_zero" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" + [(match_operand:SI 1 "register_operand" "d") + (const_int 0)]) + (match_operand 2 "pc_or_label_operand" "") + (match_operand 3 "pc_or_label_operand" "")))] + "!TARGET_MIPS16" + "* +{ + mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); + if (operands[2] != pc_rtx) + { /* normal jump */ + switch (GET_CODE (operands[0])) + { + case EQ: return \"%*beq%?\\t%z1,%.,%2\"; + case NE: return \"%*bne%?\\t%z1,%.,%2\"; + case GTU: return \"%*bne%?\\t%z1,%.,%2\"; + case LEU: return \"%*beq%?\\t%z1,%.,%2\"; + case GEU: return \"%*j\\t%2\"; + case LTU: return \"%*bne%?\\t%.,%.,%2\"; + default: + break; + } + + return \"%*b%C0z%?\\t%z1,%2\"; + } + else + { /* inverted jump */ + switch (GET_CODE (operands[0])) + { + case EQ: return \"%*bne%?\\t%z1,%.,%3\"; + case NE: return \"%*beq%?\\t%z1,%.,%3\"; + case GTU: return \"%*beq%?\\t%z1,%.,%3\"; + case LEU: return \"%*bne%?\\t%z1,%.,%3\"; + case GEU: return \"%*beq%?\\t%.,%.,%3\"; + case LTU: return \"%*j\\t%3\"; + default: + break; + } + + return \"%*b%N0z%?\\t%z1,%3\"; + } +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "1")]) + + +(define_insn "" + [(set (pc) + (if_then_else (match_operator:SI 0 "equality_op" + [(match_operand:SI 1 "register_operand" "d,t") + (const_int 0)]) + (match_operand 2 "pc_or_label_operand" "") + (match_operand 3 "pc_or_label_operand" "")))] + "TARGET_MIPS16" + "* +{ + if (operands[2] != pc_rtx) + { + if (which_alternative == 0) + return \"%*b%C0z\\t%1,%2\"; + else + return \"%*bt%C0z\\t%2\"; + } + else + { + if (which_alternative == 0) + return \"%*b%N0z\\t%1,%3\"; + else + return \"%*bt%N0z\\t%3\"; + } +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_insn "branch_zero_di" + [(set (pc) + (if_then_else (match_operator:DI 0 "cmp_op" + [(match_operand:DI 1 "se_register_operand" "d") + (const_int 0)]) + (match_operand 2 "pc_or_label_operand" "") + (match_operand 3 "pc_or_label_operand" "")))] + "!TARGET_MIPS16" + "* +{ + mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); + if (operands[2] != pc_rtx) + { /* normal jump */ + switch (GET_CODE (operands[0])) + { + case EQ: return \"%*beq%?\\t%z1,%.,%2\"; + case NE: return \"%*bne%?\\t%z1,%.,%2\"; + case GTU: return \"%*bne%?\\t%z1,%.,%2\"; + case LEU: return \"%*beq%?\\t%z1,%.,%2\"; + case GEU: return \"%*j\\t%2\"; + case LTU: return \"%*bne%?\\t%.,%.,%2\"; + default: + break; + } + + return \"%*b%C0z%?\\t%z1,%2\"; + } + else + { /* inverted jump */ + switch (GET_CODE (operands[0])) + { + case EQ: return \"%*bne%?\\t%z1,%.,%3\"; + case NE: return \"%*beq%?\\t%z1,%.,%3\"; + case GTU: return \"%*beq%?\\t%z1,%.,%3\"; + case LEU: return \"%*bne%?\\t%z1,%.,%3\"; + case GEU: return \"%*beq%?\\t%.,%.,%3\"; + case LTU: return \"%*j\\t%3\"; + default: + break; + } + + return \"%*b%N0z%?\\t%z1,%3\"; + } +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "" + [(set (pc) + (if_then_else (match_operator:DI 0 "equality_op" + [(match_operand:DI 1 "se_register_operand" "d,t") + (const_int 0)]) + (match_operand 2 "pc_or_label_operand" "") + (match_operand 3 "pc_or_label_operand" "")))] + "TARGET_MIPS16" + "* +{ + if (operands[2] != pc_rtx) + { + if (which_alternative == 0) + return \"%*b%C0z\\t%1,%2\"; + else + return \"%*bt%C0z\\t%2\"; + } + else + { + if (which_alternative == 0) + return \"%*b%N0z\\t%1,%3\"; + else + return \"%*bt%N0z\\t%3\"; + } +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "2")]) + + +(define_insn "branch_equality" + [(set (pc) + (if_then_else (match_operator:SI 0 "equality_op" + [(match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")]) + (match_operand 3 "pc_or_label_operand" "") + (match_operand 4 "pc_or_label_operand" "")))] + "!TARGET_MIPS16" + "* +{ + mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); + return (operands[3] != pc_rtx) + ? \"%*b%C0%?\\t%z1,%z2,%3\" + : \"%*b%N0%?\\t%z1,%z2,%4\"; +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "1")]) + + +(define_insn "branch_equality_di" + [(set (pc) + (if_then_else (match_operator:DI 0 "equality_op" + [(match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")]) + (match_operand 3 "pc_or_label_operand" "") + (match_operand 4 "pc_or_label_operand" "")))] + "!TARGET_MIPS16" + "* +{ + mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); + return (operands[3] != pc_rtx) + ? \"%*b%C0%?\\t%z1,%z2,%3\" + : \"%*b%N0%?\\t%z1,%z2,%4\"; +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "1")]) + + +(define_expand "beq" + [(set (pc) + (if_then_else (eq:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, EQ); + DONE; + } +}") + +(define_expand "bne" + [(set (pc) + (if_then_else (ne:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, NE); + DONE; + } +}") + +(define_expand "bgt" + [(set (pc) + (if_then_else (gt:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, GT); + DONE; + } +}") + +(define_expand "bge" + [(set (pc) + (if_then_else (ge:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, GE); + DONE; + } +}") + +(define_expand "blt" + [(set (pc) + (if_then_else (lt:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, LT); + DONE; + } +}") + +(define_expand "ble" + [(set (pc) + (if_then_else (le:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, LE); + DONE; + } +}") + +(define_expand "bgtu" + [(set (pc) + (if_then_else (gtu:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, GTU); + DONE; + } +}") + +(define_expand "bgeu" + [(set (pc) + (if_then_else (geu:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, GEU); + DONE; + } +}") + + +(define_expand "bltu" + [(set (pc) + (if_then_else (ltu:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, LTU); + DONE; + } +}") + +(define_expand "bleu" + [(set (pc) + (if_then_else (leu:CC (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (operands[0]) /* avoid unused code warning */ + { + gen_conditional_branch (operands, LEU); + DONE; + } +}") + + +;; +;; .................... +;; +;; SETTING A REGISTER FROM A COMPARISON +;; +;; .................... + +(define_expand "seq" + [(set (match_operand:SI 0 "register_operand" "=d") + (eq:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) + operands[2] = force_reg (SImode, operands[2]); + + /* fall through and generate default code */ +}") + + +(define_insn "seq_si_zero" + [(set (match_operand:SI 0 "register_operand" "=d") + (eq:SI (match_operand:SI 1 "register_operand" "d") + (const_int 0)))] + "!TARGET_MIPS16" + "sltu\\t%0,%1,1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=t") + (eq:SI (match_operand:SI 1 "register_operand" "d") + (const_int 0)))] + "TARGET_MIPS16" + "sltu\\t%1,1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "seq_di_zero" + [(set (match_operand:DI 0 "register_operand" "=d") + (eq:DI (match_operand:DI 1 "se_register_operand" "d") + (const_int 0)))] + "TARGET_64BIT && !TARGET_MIPS16" + "sltu\\t%0,%1,1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=t") + (eq:DI (match_operand:DI 1 "se_register_operand" "d") + (const_int 0)))] + "TARGET_64BIT && TARGET_MIPS16" + "sltu\\t%1,1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "seq_si" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (eq:SI (match_operand:SI 1 "register_operand" "%d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] + "TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "@ + xor\\t%0,%1,%2\;sltu\\t%0,%0,1 + xori\\t%0,%1,%2\;sltu\\t%0,%0,1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (eq:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "uns_arith_operand" "")))] + "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" + [(set (match_dup 0) + (xor:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (ltu:SI (match_dup 0) + (const_int 1)))] + "") + +(define_insn "seq_di" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (eq:DI (match_operand:DI 1 "se_register_operand" "%d,d") + (match_operand:DI 2 "se_uns_arith_operand" "d,K")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "@ + xor\\t%0,%1,%2\;sltu\\t%0,%0,1 + xori\\t%0,%1,%2\;sltu\\t%0,%0,1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (eq:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:DI 2 "se_uns_arith_operand" "")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE + && !TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" + [(set (match_dup 0) + (xor:DI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (ltu:DI (match_dup 0) + (const_int 1)))] + "") + +;; On the mips16 the default code is better than using sltu. + +(define_expand "sne" + [(set (match_operand:SI 0 "register_operand" "=d") + (ne:SI (match_dup 1) + (match_dup 2)))] + "!TARGET_MIPS16" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE) + { + gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) + operands[2] = force_reg (SImode, operands[2]); + + /* fall through and generate default code */ +}") + +(define_insn "sne_si_zero" + [(set (match_operand:SI 0 "register_operand" "=d") + (ne:SI (match_operand:SI 1 "register_operand" "d") + (const_int 0)))] + "!TARGET_MIPS16" + "sltu\\t%0,%.,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "sne_di_zero" + [(set (match_operand:DI 0 "register_operand" "=d") + (ne:DI (match_operand:DI 1 "se_register_operand" "d") + (const_int 0)))] + "TARGET_64BIT && !TARGET_MIPS16" + "sltu\\t%0,%.,%1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "sne_si" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ne:SI (match_operand:SI 1 "register_operand" "%d,d") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] + "TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "@ + xor\\t%0,%1,%2\;sltu\\t%0,%.,%0 + xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (ne:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "uns_arith_operand" "")))] + "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" + [(set (match_dup 0) + (xor:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (gtu:SI (match_dup 0) + (const_int 0)))] + "") + +(define_insn "sne_di" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ne:DI (match_operand:DI 1 "se_register_operand" "%d,d") + (match_operand:DI 2 "se_uns_arith_operand" "d,K")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "@ + xor\\t%0,%1,%2\;sltu\\t%0,%.,%0 + xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ne:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:DI 2 "se_uns_arith_operand" "")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE + && !TARGET_MIPS16 + && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)" + [(set (match_dup 0) + (xor:DI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (gtu:DI (match_dup 0) + (const_int 0)))] + "") + +(define_expand "sgt" + [(set (match_operand:SI 0 "register_operand" "=d") + (gt:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) + operands[2] = force_reg (SImode, operands[2]); + + /* fall through and generate default code */ +}") + +(define_insn "sgt_si" + [(set (match_operand:SI 0 "register_operand" "=d") + (gt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "reg_or_0_operand" "dJ")))] + "!TARGET_MIPS16" + "slt\\t%0,%z2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=t") + (gt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_MIPS16" + "slt\\t%2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "sgt_di" + [(set (match_operand:DI 0 "register_operand" "=d") + (gt:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))] + "TARGET_64BIT && !TARGET_MIPS16" + "slt\\t%0,%z2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (gt:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "TARGET_64BIT && TARGET_MIPS16" + "slt\\t%2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_expand "sge" + [(set (match_operand:SI 0 "register_operand" "=d") + (ge:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + /* fall through and generate default code */ +}") + +(define_insn "sge_si" + [(set (match_operand:SI 0 "register_operand" "=d") + (ge:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (ge:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "arith_operand" "")))] + "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16" + [(set (match_dup 0) + (lt:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (xor:SI (match_dup 0) + (const_int 1)))] + "") + +(define_insn "sge_di" + [(set (match_operand:DI 0 "register_operand" "=d") + (ge:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_arith_operand" "dI")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ge:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:DI 2 "se_arith_operand" "")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE + && !TARGET_MIPS16" + [(set (match_dup 0) + (lt:DI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (xor:DI (match_dup 0) + (const_int 1)))] + "") + +(define_expand "slt" + [(set (match_operand:SI 0 "register_operand" "=d") + (lt:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + /* fall through and generate default code */ +}") + +(define_insn "slt_si" + [(set (match_operand:SI 0 "register_operand" "=d") + (lt:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "!TARGET_MIPS16" + "slt\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=t,t") + (lt:SI (match_operand:SI 1 "register_operand" "d,d") + (match_operand:SI 2 "arith_operand" "d,I")))] + "TARGET_MIPS16" + "slt\\t%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "") + (const_int 1) + (const_int 2))])]) + +(define_insn "slt_di" + [(set (match_operand:DI 0 "register_operand" "=d") + (lt:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_arith_operand" "dI")))] + "TARGET_64BIT && !TARGET_MIPS16" + "slt\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=t,t") + (lt:DI (match_operand:DI 1 "se_register_operand" "d,d") + (match_operand:DI 2 "se_arith_operand" "d,I")))] + "TARGET_64BIT && TARGET_MIPS16" + "slt\\t%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "") + (const_int 1) + (const_int 2))])]) + +(define_expand "sle" + [(set (match_operand:SI 0 "register_operand" "=d") + (le:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767) + operands[2] = force_reg (SImode, operands[2]); + + /* fall through and generate default code */ +}") + +(define_insn "sle_si_const" + [(set (match_operand:SI 0 "register_operand" "=d") + (le:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "I")))] + "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2])+1); + return \"slt\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=t") + (le:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "I")))] + "TARGET_MIPS16 && INTVAL (operands[2]) < 32767" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2])+1); + return \"slt\\t%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "sle_di_const" + [(set (match_operand:DI 0 "register_operand" "=d") + (le:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "small_int" "I")))] + "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2])+1); + return \"slt\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=t") + (le:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "small_int" "I")))] + "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2])+1); + return \"slt\\t%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "sle_si_reg" + [(set (match_operand:SI 0 "register_operand" "=d") + (le:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (le:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "register_operand" "")))] + "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16" + [(set (match_dup 0) + (lt:SI (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (xor:SI (match_dup 0) + (const_int 1)))] + "") + +(define_insn "sle_di_reg" + [(set (match_operand:DI 0 "register_operand" "=d") + (le:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (le:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:DI 2 "se_register_operand" "")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE + && !TARGET_MIPS16" + [(set (match_dup 0) + (lt:DI (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (xor:DI (match_dup 0) + (const_int 1)))] + "") + +(define_expand "sgtu" + [(set (match_operand:SI 0 "register_operand" "=d") + (gtu:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) + operands[2] = force_reg (SImode, operands[2]); + + /* fall through and generate default code */ +}") + +(define_insn "sgtu_si" + [(set (match_operand:SI 0 "register_operand" "=d") + (gtu:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "reg_or_0_operand" "dJ")))] + "" + "sltu\\t%0,%z2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=t") + (gtu:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "" + "sltu\\t%2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "sgtu_di" + [(set (match_operand:DI 0 "register_operand" "=d") + (gtu:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))] + "TARGET_64BIT" + "sltu\\t%0,%z2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=t") + (gtu:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "TARGET_64BIT" + "sltu\\t%2,%1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_expand "sgeu" + [(set (match_operand:SI 0 "register_operand" "=d") + (geu:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + /* fall through and generate default code */ +}") + +(define_insn "sgeu_si" + [(set (match_operand:SI 0 "register_operand" "=d") + (geu:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (geu:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "arith_operand" "")))] + "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16" + [(set (match_dup 0) + (ltu:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (xor:SI (match_dup 0) + (const_int 1)))] + "") + +(define_insn "sgeu_di" + [(set (match_operand:DI 0 "register_operand" "=d") + (geu:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_arith_operand" "dI")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (geu:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:DI 2 "se_arith_operand" "")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE + && !TARGET_MIPS16" + [(set (match_dup 0) + (ltu:DI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (xor:DI (match_dup 0) + (const_int 1)))] + "") + +(define_expand "sltu" + [(set (match_operand:SI 0 "register_operand" "=d") + (ltu:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + /* fall through and generate default code */ +}") + +(define_insn "sltu_si" + [(set (match_operand:SI 0 "register_operand" "=d") + (ltu:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "arith_operand" "dI")))] + "!TARGET_MIPS16" + "sltu\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=t,t") + (ltu:SI (match_operand:SI 1 "register_operand" "d,d") + (match_operand:SI 2 "arith_operand" "d,I")))] + "TARGET_MIPS16" + "sltu\\t%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "") + (const_int 1) + (const_int 2))])]) + +(define_insn "sltu_di" + [(set (match_operand:DI 0 "register_operand" "=d") + (ltu:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_arith_operand" "dI")))] + "TARGET_64BIT && !TARGET_MIPS16" + "sltu\\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=t,t") + (ltu:DI (match_operand:DI 1 "se_register_operand" "d,d") + (match_operand:DI 2 "se_arith_operand" "d,I")))] + "TARGET_64BIT && TARGET_MIPS16" + "sltu\\t%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr_alternative "length" + [(const_int 1) + (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "") + (const_int 1) + (const_int 2))])]) + +(define_expand "sleu" + [(set (match_operand:SI 0 "register_operand" "=d") + (leu:SI (match_dup 1) + (match_dup 2)))] + "" + " +{ + if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI)) + FAIL; + + /* set up operands from compare. */ + operands[1] = branch_cmp[0]; + operands[2] = branch_cmp[1]; + + if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16) + { + gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0); + DONE; + } + + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767) + operands[2] = force_reg (SImode, operands[2]); + + /* fall through and generate default code */ +}") + +(define_insn "sleu_si_const" + [(set (match_operand:SI 0 "register_operand" "=d") + (leu:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "I")))] + "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2])+1); + return \"sltu\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=t") + (leu:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "small_int" "I")))] + "TARGET_MIPS16 && INTVAL (operands[2]) < 32767" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2])+1); + return \"sltu\\t%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "sleu_di_const" + [(set (match_operand:DI 0 "register_operand" "=d") + (leu:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "small_int" "I")))] + "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2])+1); + return \"sltu\\t%0,%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "1")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=t") + (leu:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "small_int" "I")))] + "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2])+1); + return \"sltu\\t%1,%2\"; +}" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "") + (const_int 1) + (const_int 2)))]) + +(define_insn "sleu_si_reg" + [(set (match_operand:SI 0 "register_operand" "=d") + (leu:SI (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "d")))] + "TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (leu:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "register_operand" "")))] + "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16" + [(set (match_dup 0) + (ltu:SI (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (xor:SI (match_dup 0) + (const_int 1)))] + "") + +(define_insn "sleu_di_reg" + [(set (match_operand:DI 0 "register_operand" "=d") + (leu:DI (match_operand:DI 1 "se_register_operand" "d") + (match_operand:DI 2 "se_register_operand" "d")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16" + "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (leu:DI (match_operand:DI 1 "se_register_operand" "") + (match_operand:DI 2 "se_register_operand" "")))] + "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE + && !TARGET_MIPS16" + [(set (match_dup 0) + (ltu:DI (match_dup 2) + (match_dup 1))) + (set (match_dup 0) + (xor:DI (match_dup 0) + (const_int 1)))] + "") + + +;; +;; .................... +;; +;; FLOATING POINT COMPARISONS +;; +;; .................... + +(define_insn "seq_df" + [(set (match_operand:CC 0 "register_operand" "=z") + (eq:CC (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "slt_df" + [(set (match_operand:CC 0 "register_operand" "=z") + (lt:CC (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "sle_df" + [(set (match_operand:CC 0 "register_operand" "=z") + (le:CC (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "sgt_df" + [(set (match_operand:CC 0 "register_operand" "=z") + (gt:CC (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "sge_df" + [(set (match_operand:CC 0 "register_operand" "=z") + (ge:CC (match_operand:DF 1 "register_operand" "f") + (match_operand:DF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "seq_sf" + [(set (match_operand:CC 0 "register_operand" "=z") + (eq:CC (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "slt_sf" + [(set (match_operand:CC 0 "register_operand" "=z") + (lt:CC (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "sle_sf" + [(set (match_operand:CC 0 "register_operand" "=z") + (le:CC (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "sgt_sf" + [(set (match_operand:CC 0 "register_operand" "=z") + (gt:CC (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + +(define_insn "sge_sf" + [(set (match_operand:CC 0 "register_operand" "=z") + (ge:CC (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_HARD_FLOAT" + "* +{ + return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn); +}" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW") + (set_attr "length" "1")]) + + +;; +;; .................... +;; +;; UNCONDITIONAL BRANCHES +;; +;; .................... + +;; Unconditional branches. + +(define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "!TARGET_MIPS16" + "* +{ + if (GET_CODE (operands[0]) == REG) + return \"%*j\\t%0\"; + /* ??? I don't know why this is necessary. This works around an + assembler problem that appears when a label is defined, then referenced + in a switch table, then used in a `j' instruction. */ + else if (mips_abi != ABI_32 && mips_abi != ABI_O64) + return \"%*b\\t%l0\"; + else + return \"%*j\\t%l0\"; +}" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +;; We need a different insn for the mips16, because a mips16 branch +;; does not have a delay slot. + +(define_insn "" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "TARGET_MIPS16 && GET_CODE (operands[0]) != REG" + "b\\t%l0" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_expand "indirect_jump" + [(set (pc) (match_operand 0 "register_operand" "d"))] + "" + " +{ + rtx dest; + + if (operands[0]) /* eliminate unused code warnings */ + { + dest = operands[0]; + if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode) + operands[0] = copy_to_mode_reg (Pmode, dest); + + if (!(Pmode == DImode)) + emit_jump_insn (gen_indirect_jump_internal1 (operands[0])); + else + emit_jump_insn (gen_indirect_jump_internal2 (operands[0])); + + DONE; + } +}") + +(define_insn "indirect_jump_internal1" + [(set (pc) (match_operand:SI 0 "register_operand" "d"))] + "!(Pmode == DImode)" + "%*j\\t%0" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "indirect_jump_internal2" + [(set (pc) (match_operand:DI 0 "se_register_operand" "d"))] + "Pmode == DImode" + "%*j\\t%0" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_expand "tablejump" + [(set (pc) + (match_operand 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + " +{ + if (operands[0]) /* eliminate unused code warnings */ + { + if (TARGET_MIPS16) + { + if (GET_MODE (operands[0]) != HImode) + abort (); + if (!(Pmode == DImode)) + emit_jump_insn (gen_tablejump_mips161 (operands[0], operands[1])); + else + emit_jump_insn (gen_tablejump_mips162 (operands[0], operands[1])); + DONE; + } + + if (GET_MODE (operands[0]) != Pmode) + abort (); + + if (! flag_pic) + { + if (!(Pmode == DImode)) + emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); + else + emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); + } + else + { + if (!(Pmode == DImode)) + emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); + else + emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); + } + + DONE; + } +}") + +(define_insn "tablejump_internal1" + [(set (pc) + (match_operand:SI 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "!(Pmode == DImode)" + "%*j\\t%0" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "tablejump_internal2" + [(set (pc) + (match_operand:DI 0 "se_register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "Pmode == DImode" + "%*j\\t%0" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_expand "tablejump_internal3" + [(parallel [(set (pc) + (plus:SI (match_operand:SI 0 "register_operand" "d") + (label_ref:SI (match_operand:SI 1 "" "")))) + (use (label_ref:SI (match_dup 1)))])] + "" + "") + +(define_expand "tablejump_mips161" + [(set (pc) (plus:SI (sign_extend:SI + (match_operand:HI 0 "register_operand" "d")) + (label_ref:SI (match_operand:SI 1 "" ""))))] + "TARGET_MIPS16 && !(Pmode == DImode)" + " +{ + if (operands[0]) /* eliminate unused code warnings. */ + { + rtx t1, t2, t3; + + t1 = gen_reg_rtx (SImode); + t2 = gen_reg_rtx (SImode); + t3 = gen_reg_rtx (SImode); + emit_insn (gen_extendhisi2 (t1, operands[0])); + emit_move_insn (t2, gen_rtx (LABEL_REF, SImode, operands[1])); + emit_insn (gen_addsi3 (t3, t1, t2)); + emit_insn (gen_tablejump_internal1 (t3, operands[1])); + DONE; + } +}") + +(define_expand "tablejump_mips162" + [(set (pc) (plus:DI (sign_extend:DI + (match_operand:HI 0 "register_operand" "d")) + (label_ref:DI (match_operand:SI 1 "" ""))))] + "TARGET_MIPS16 && Pmode == DImode" + " +{ + if (operands[0]) /* eliminate unused code warnings. */ + { + rtx t1, t2, t3; + + t1 = gen_reg_rtx (DImode); + t2 = gen_reg_rtx (DImode); + t3 = gen_reg_rtx (DImode); + emit_insn (gen_extendhidi2 (t1, operands[0])); + emit_move_insn (t2, gen_rtx (LABEL_REF, DImode, operands[1])); + emit_insn (gen_adddi3 (t3, t1, t2)); + emit_insn (gen_tablejump_internal2 (t3, operands[1])); + DONE; + } +}") + +;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise +;;; it is not valid. ??? With the USE, the condition tests may not be required +;;; any longer. + +;;; ??? The length depends on the ABI. It is two for o32, and one for n32. +;;; We just use the conservative number here. + +(define_insn "" + [(set (pc) + (plus:SI (match_operand:SI 0 "register_operand" "d") + (label_ref:SI (match_operand:SI 1 "" "")))) + (use (label_ref:SI (match_dup 1)))] + "!(Pmode == DImode) && next_active_insn (insn) != 0 + && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC + && PREV_INSN (next_active_insn (insn)) == operands[1]" + "* +{ + /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic. */ + if (mips_abi == ABI_32 || mips_abi == ABI_O64) + output_asm_insn (\".cpadd\\t%0\", operands); + return \"%*j\\t%0\"; +}" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_expand "tablejump_internal4" + [(parallel [(set (pc) + (plus:DI (match_operand:DI 0 "se_register_operand" "d") + (label_ref:DI (match_operand:SI 1 "" "")))) + (use (label_ref:DI (match_dup 1)))])] + "" + "") + +;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise +;;; it is not valid. ??? With the USE, the condition tests may not be required +;;; any longer. + +(define_insn "" + [(set (pc) + (plus:DI (match_operand:DI 0 "se_register_operand" "d") + (label_ref:DI (match_operand:SI 1 "" "")))) + (use (label_ref:DI (match_dup 1)))] + "Pmode == DImode && next_active_insn (insn) != 0 + && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC + && PREV_INSN (next_active_insn (insn)) == operands[1]" + "%*j\\t%0" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +;; Implement a switch statement when generating embedded PIC code. +;; Switches are implemented by `tablejump' when not using -membedded-pic. + +(define_expand "casesi" + [(set (match_dup 5) + (minus:SI (match_operand:SI 0 "register_operand" "d") + (match_operand:SI 1 "arith_operand" "dI"))) + (set (cc0) + (compare:CC (match_dup 5) + (match_operand:SI 2 "arith_operand" ""))) + (set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (label_ref (match_operand 4 "" "")) + (pc))) + (parallel + [(set (pc) + (mem:SI (plus:SI (mult:SI (match_dup 5) + (const_int 4)) + (label_ref (match_operand 3 "" ""))))) + (clobber (match_scratch:SI 6 "")) + (clobber (reg:SI 31))])] + "TARGET_EMBEDDED_PIC" + " +{ + /* We need slightly different code for eight byte table entries. */ + if (Pmode == DImode) + abort (); + + if (operands[0]) + { + rtx reg = gen_reg_rtx (SImode); + + /* If the index is too large, go to the default label. */ + emit_insn (gen_subsi3 (reg, operands[0], operands[1])); + emit_insn (gen_cmpsi (reg, operands[2])); + emit_insn (gen_bgtu (operands[4])); + + /* Do the PIC jump. */ + emit_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode))); + + DONE; + } +}") + +;; An embedded PIC switch statement looks like this: +;; bal $LS1 +;; sll $reg,$index,2 +;; $LS1: +;; addu $reg,$reg,$31 +;; lw $reg,$L1-$LS1($reg) +;; addu $reg,$reg,$31 +;; j $reg +;; $L1: +;; .word case1-$LS1 +;; .word case2-$LS1 +;; ... + +(define_insn "casesi_internal" + [(set (pc) + (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d") + (const_int 4)) + (label_ref (match_operand 1 "" ""))))) + (clobber (match_operand:SI 2 "register_operand" "d")) + (clobber (reg:SI 31))] + "TARGET_EMBEDDED_PIC" + "* +{ + output_asm_insn (\"%(bal\\t%S1\;sll\\t%0,2\\n%S1:\", operands); + output_asm_insn (\"addu\\t%0,%0,$31%)\", operands); + output_asm_insn (\"lw\\t%0,%1-%S1(%0)\;addu\\t%0,%0,$31\", operands); + return \"j\\t%0\"; +}" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "6")]) + +;; For o32/n32/n64, we save the gp in the jmp_buf as well. While it is +;; possible to either pull it off the stack (in the o32 case) or recalculate +;; it given t9 and our target label, it takes 3 or 4 insns to do so, and +;; this is easy. + +(define_expand "builtin_setjmp_setup" + [(unspec [(match_operand 0 "register_operand" "r")] 20)] + "TARGET_ABICALLS" + " +{ + if (Pmode == DImode) + emit_insn (gen_builtin_setjmp_setup_64 (operands[0])); + else + emit_insn (gen_builtin_setjmp_setup_32 (operands[0])); + DONE; +}") + +(define_expand "builtin_setjmp_setup_32" + [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r") + (const_int 12))) + (reg:SI 28))] + "TARGET_ABICALLS && ! (Pmode == DImode)" + "") + +(define_expand "builtin_setjmp_setup_64" + [(set (mem:DI (plus:DI (match_operand:DI 0 "register_operand" "r") + (const_int 24))) + (reg:DI 28))] + "TARGET_ABICALLS && Pmode == DImode" + "") + +;; For o32/n32/n64, we need to arrange for longjmp to put the +;; target address in t9 so that we can use it for loading $gp. + +(define_expand "builtin_longjmp" + [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)] + "TARGET_ABICALLS" + " +{ + /* The elements of the buffer are, in order: */ + int W = (Pmode == DImode ? 8 : 4); + rtx fp = gen_rtx_MEM (Pmode, operands[0]); + rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W)); + rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W)); + rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W)); + rtx pv = gen_rtx_REG (Pmode, 25); + rtx gp = gen_rtx_REG (Pmode, 28); + + /* This bit is the same as expand_builtin_longjmp. */ + emit_move_insn (hard_frame_pointer_rtx, fp); + emit_move_insn (pv, lab); + emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); + emit_move_insn (gp, gpv); + emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx)); + emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); + emit_insn (gen_rtx_USE (VOIDmode, gp)); + emit_indirect_jump (pv); + DONE; +}") + +;; +;; .................... +;; +;; Function prologue/epilogue +;; +;; .................... +;; + +(define_expand "prologue" + [(const_int 1)] + "" + " +{ + if (mips_isa >= 0) /* avoid unused code warnings */ + { + mips_expand_prologue (); + DONE; + } +}") + +;; Block any insns from being moved before this point, since the +;; profiling call to mcount can use various registers that aren't +;; saved or used to pass arguments. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "" + [(set_attr "type" "unknown") + (set_attr "mode" "none") + (set_attr "length" "0")]) + +(define_expand "epilogue" + [(const_int 2)] + "" + " +{ + if (mips_isa >= 0) /* avoid unused code warnings */ + { + mips_expand_epilogue (); + DONE; + } +}") + +;; Trivial return. Make it look like a normal return insn as that +;; allows jump optimizations to work better . +(define_insn "return" + [(return)] + "mips_can_use_return_insn ()" + "%*j\\t$31" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +;; Normal return. +;; We match any mode for the return address, so that this will work with +;; both 32 bit and 64 bit targets. +(define_insn "return_internal" + [(use (match_operand 0 "register_operand" "")) + (return)] + "" + "* +{ + return \"%*j\\t%0\"; +}" + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +;; When generating embedded PIC code we need to get the address of the +;; current function. This specialized instruction does just that. + +(define_insn "get_fnaddr" + [(set (match_operand 0 "register_operand" "=d") + (unspec [(match_operand 1 "" "")] 1)) + (clobber (reg:SI 31))] + "TARGET_EMBEDDED_PIC + && GET_CODE (operands[1]) == SYMBOL_REF" + "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "4")]) + + +;; +;; .................... +;; +;; FUNCTION CALLS +;; +;; .................... + +;; calls.c now passes a third argument, make saber happy + +(define_expand "call" + [(parallel [(call (match_operand 0 "memory_operand" "m") + (match_operand 1 "" "i")) + (clobber (reg:SI 31)) + (use (match_operand 2 "" "")) ;; next_arg_reg + (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx + "" + " +{ + rtx addr; + + if (operands[0]) /* eliminate unused code warnings */ + { + addr = XEXP (operands[0], 0); + if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS)) + || ! call_insn_operand (addr, VOIDmode)) + XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr); + + /* In order to pass small structures by value in registers + compatibly with the MIPS compiler, we need to shift the value + into the high part of the register. Function_arg has encoded + a PARALLEL rtx, holding a vector of adjustments to be made + as the next_arg_reg variable, so we split up the insns, + and emit them separately. */ + + if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL) + { + rtvec adjust = XVEC (operands[2], 0); + int num = GET_NUM_ELEM (adjust); + int i; + + for (i = 0; i < num; i++) + emit_insn (RTVEC_ELT (adjust, i)); + } + + if (TARGET_MIPS16 + && mips16_hard_float + && operands[2] != 0 + && (int) GET_MODE (operands[2]) != 0) + { + if (build_mips16_call_stub (NULL_RTX, operands[0], operands[1], + (int) GET_MODE (operands[2]))) + DONE; + } + + emit_call_insn (gen_call_internal0 (operands[0], operands[1], + gen_rtx (REG, SImode, GP_REG_FIRST + 31))); + + DONE; + } +}") + +(define_expand "call_internal0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) + (clobber (match_operand:SI 2 "" ""))])] + "" + "") + +;; We need to recognize reg:SI 31 specially for the mips16, because we +;; don't have a constraint letter for it. + +(define_insn "" + [(call (mem (match_operand 0 "call_insn_operand" "ei")) + (match_operand 1 "" "i")) + (clobber (match_operand:SI 2 "register_operand" "=y"))] + "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS + && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31" + "%*jal\\t%0" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_insn "call_internal1" + [(call (mem (match_operand 0 "call_insn_operand" "ri")) + (match_operand 1 "" "i")) + (clobber (match_operand:SI 2 "register_operand" "=d"))] + "!TARGET_ABICALLS && !TARGET_LONG_CALLS" + "* +{ + register rtx target = operands[0]; + + if (GET_CODE (target) == SYMBOL_REF) + return \"%*jal\\t%0\"; + else if (GET_CODE (target) == CONST_INT) + return \"%[li\\t%@,%0\\n\\t%*jal\\t%2,%@%]\"; + else + return \"%*jal\\t%2,%0\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "call_internal2" + [(call (mem (match_operand 0 "call_insn_operand" "ri")) + (match_operand 1 "" "i")) + (clobber (match_operand:SI 2 "register_operand" "=d"))] + "TARGET_ABICALLS && !TARGET_LONG_CALLS" + "* +{ + register rtx target = operands[0]; + + if (GET_CODE (target) == SYMBOL_REF) + { + if (GET_MODE (target) == SImode) + return \"la\\t%^,%0\\n\\tjal\\t%2,%^\"; + else + return \"dla\\t%^,%0\\n\\tjal\\t%2,%^\"; + } + else if (GET_CODE (target) == CONST_INT) + return \"li\\t%^,%0\\n\\tjal\\t%2,%^\"; + else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM) + return \"move\\t%^,%0\\n\\tjal\\t%2,%^\"; + else + return \"jal\\t%2,%0\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_insn "call_internal3a" + [(call (mem:SI (match_operand:SI 0 "register_operand" "r")) + (match_operand 1 "" "i")) + (clobber (match_operand:SI 2 "register_operand" "=d"))] + "!(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS" + "%*jal\\t%2,%0" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "call_internal3b" + [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r")) + (match_operand 1 "" "i")) + (clobber (match_operand:SI 2 "register_operand" "=d"))] + "Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS" + "%*jal\\t%2,%0" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "call_internal4a" + [(call (mem:SI (match_operand:SI 0 "register_operand" "r")) + (match_operand 1 "" "i")) + (clobber (match_operand:SI 2 "register_operand" "=d"))] + "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS" + "* +{ + if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM) + return \"move\\t%^,%0\\n\\tjal\\t%2,%^\"; + else + return \"jal\\t%2,%0\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_insn "call_internal4b" + [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r")) + (match_operand 1 "" "i")) + (clobber (match_operand:SI 2 "register_operand" "=d"))] + "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS" + "* +{ + if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM) + return \"move\\t%^,%0\\n\\tjal\\t%2,%^\"; + else + return \"jal\\t%2,%0\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +;; calls.c now passes a fourth argument, make saber happy + +(define_expand "call_value" + [(parallel [(set (match_operand 0 "register_operand" "=df") + (call (match_operand 1 "memory_operand" "m") + (match_operand 2 "" "i"))) + (clobber (reg:SI 31)) + (use (match_operand 3 "" ""))])] ;; next_arg_reg + "" + " +{ + rtx addr; + + if (operands[0]) /* eliminate unused code warning */ + { + addr = XEXP (operands[1], 0); + if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS)) + || ! call_insn_operand (addr, VOIDmode)) + XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr); + + /* In order to pass small structures by value in registers + compatibly with the MIPS compiler, we need to shift the value + into the high part of the register. Function_arg has encoded + a PARALLEL rtx, holding a vector of adjustments to be made + as the next_arg_reg variable, so we split up the insns, + and emit them separately. */ + + if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL) + { + rtvec adjust = XVEC (operands[3], 0); + int num = GET_NUM_ELEM (adjust); + int i; + + for (i = 0; i < num; i++) + emit_insn (RTVEC_ELT (adjust, i)); + } + + if (TARGET_MIPS16 + && mips16_hard_float + && ((operands[3] != 0 + && (int) GET_MODE (operands[3]) != 0) + || GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)) + { + if (build_mips16_call_stub (operands[0], operands[1], operands[2], + (operands[3] == 0 ? 0 + : (int) GET_MODE (operands[3])))) + DONE; + } + + /* Handle Irix6 function calls that have multiple non-contiguous + results. */ + if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1) + { + emit_call_insn (gen_call_value_multiple_internal0 + (XEXP (XVECEXP (operands[0], 0, 0), 0), + operands[1], operands[2], + XEXP (XVECEXP (operands[0], 0, 1), 0), + gen_rtx (REG, SImode, GP_REG_FIRST + 31))); + DONE; + } + + /* We have a call returning a DImode structure in an FP reg. + Strip off the now unnecessary PARALLEL. */ + if (GET_CODE (operands[0]) == PARALLEL) + operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0); + + emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2], + gen_rtx (REG, SImode, GP_REG_FIRST + 31))); + + DONE; + } +}") + +(define_expand "call_value_internal0" + [(parallel [(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) + (clobber (match_operand:SI 3 "" ""))])] + "" + "") + +;; Recognize $31 specially on the mips16, because we don't have a +;; constraint letter for it. + +(define_insn "" + [(set (match_operand 0 "register_operand" "=d") + (call (mem (match_operand 1 "call_insn_operand" "ei")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=y"))] + "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS + && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31" + "%*jal\\t%1" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_insn "call_value_internal1" + [(set (match_operand 0 "register_operand" "=df") + (call (mem (match_operand 1 "call_insn_operand" "ri")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_ABICALLS && !TARGET_LONG_CALLS" + "* +{ + register rtx target = operands[1]; + + if (GET_CODE (target) == SYMBOL_REF) + return \"%*jal\\t%1\"; + else if (GET_CODE (target) == CONST_INT) + return \"%[li\\t%@,%1\\n\\t%*jal\\t%3,%@%]\"; + else + return \"%*jal\\t%3,%1\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "call_value_internal2" + [(set (match_operand 0 "register_operand" "=df") + (call (mem (match_operand 1 "call_insn_operand" "ri")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "TARGET_ABICALLS && !TARGET_LONG_CALLS" + "* +{ + register rtx target = operands[1]; + + if (GET_CODE (target) == SYMBOL_REF) + { + if (GET_MODE (target) == SImode) + return \"la\\t%^,%1\\n\\tjal\\t%3,%^\"; + else + return \"dla\\t%^,%1\\n\\tjal\\t%3,%^\"; + } + else if (GET_CODE (target) == CONST_INT) + return \"li\\t%^,%1\\n\\tjal\\t%3,%^\"; + else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM) + return \"move\\t%^,%1\\n\\tjal\\t%3,%^\"; + else + return \"jal\\t%3,%1\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_insn "call_value_internal3a" + [(set (match_operand 0 "register_operand" "=df") + (call (mem:SI (match_operand:SI 1 "register_operand" "r")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_MIPS16 + && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS" + "%*jal\\t%3,%1" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "call_value_internal3b" + [(set (match_operand 0 "register_operand" "=df") + (call (mem:DI (match_operand:DI 1 "se_register_operand" "r")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!TARGET_MIPS16 + && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS" + "%*jal\\t%3,%1" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "call_value_internal3c" + [(set (match_operand 0 "register_operand" "=df") + (call (mem:SI (match_operand:SI 1 "register_operand" "e")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=y"))] + "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS + && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31" + "%*jal\\t%3,%1" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +(define_insn "call_value_internal4a" + [(set (match_operand 0 "register_operand" "=df") + (call (mem:SI (match_operand:SI 1 "register_operand" "r")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS" + "* +{ + if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM) + return \"move\\t%^,%1\\n\\tjal\\t%3,%^\"; + else + return \"jal\\t%3,%1\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_insn "call_value_internal4b" + [(set (match_operand 0 "register_operand" "=df") + (call (mem:DI (match_operand:DI 1 "se_register_operand" "r")) + (match_operand 2 "" "i"))) + (clobber (match_operand:SI 3 "register_operand" "=d"))] + "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS" + "* +{ + if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM) + return \"move\\t%^,%1\\n\\tjal\\t%3,%^\"; + else + return \"jal\\t%3,%1\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_expand "call_value_multiple_internal0" + [(parallel [(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) + (set (match_operand 3 "" "") + (call (match_dup 1) + (match_dup 2))) + (clobber (match_operand:SI 4 "" ""))])] + "" + "") + +;; ??? May eventually need all 6 versions of the call patterns with multiple +;; return values. + +(define_insn "call_value_multiple_internal2" + [(set (match_operand 0 "register_operand" "=df") + (call (mem (match_operand 1 "call_insn_operand" "ri")) + (match_operand 2 "" "i"))) + (set (match_operand 3 "register_operand" "=df") + (call (mem (match_dup 1)) + (match_dup 2))) + (clobber (match_operand:SI 4 "register_operand" "=d"))] + "TARGET_ABICALLS && !TARGET_LONG_CALLS" + "* +{ + register rtx target = operands[1]; + + if (GET_CODE (target) == SYMBOL_REF) + { + if (GET_MODE (target) == SImode) + return \"la\\t%^,%1\\n\\tjal\\t%4,%^\"; + else + return \"la\\t%^,%1\\n\\tjal\\t%4,%^\"; + } + else if (GET_CODE (target) == CONST_INT) + return \"li\\t%^,%1\\n\\tjal\\t%4,%^\"; + else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM) + return \"move\\t%^,%1\\n\\tjal\\t%4,%^\"; + else + return \"jal\\t%4,%1\"; +}" + [(set_attr "type" "call") + (set_attr "mode" "none") + (set_attr "length" "2")]) + + +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + if (operands[0]) /* silence statement not reached warnings */ + { + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + emit_insn (gen_blockage ()); + DONE; + } +}") + +;; +;; .................... +;; +;; MISC. +;; +;; .................... +;; + +(define_insn "nop" + [(const_int 0)] + "" + "%(nop%)" + [(set_attr "type" "nop") + (set_attr "mode" "none") + (set_attr "length" "1")]) + +;; The MIPS chip does not seem to require stack probes. +;; +;; (define_expand "probe" +;; [(set (match_dup 0) +;; (match_dup 1))] +;; "" +;; " +;; { +;; operands[0] = gen_reg_rtx (SImode); +;; operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx); +;; MEM_VOLATILE_P (operands[1]) = TRUE; +;; +;; /* fall through and generate default code */ +;; }") +;; + +;; +;; MIPS4 Conditional move instructions. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (if_then_else:SI + (match_operator 4 "equality_op" + [(match_operand:SI 1 "register_operand" "d,d") + (const_int 0)]) + (match_operand:SI 2 "reg_or_0_operand" "dJ,0") + (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))] + "mips_isa >= 4" + "@ + mov%B4\\t%0,%z2,%1 + mov%b4\\t%0,%z3,%1" + [(set_attr "type" "move") + (set_attr "mode" "SI")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (if_then_else:SI + (match_operator 4 "equality_op" + [(match_operand:DI 1 "se_register_operand" "d,d") + (const_int 0)]) + (match_operand:SI 2 "reg_or_0_operand" "dJ,0") + (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))] + "mips_isa >= 4" + "@ + mov%B4\\t%0,%z2,%1 + mov%b4\\t%0,%z3,%1" + [(set_attr "type" "move") + (set_attr "mode" "SI")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (if_then_else:SI + (match_operator 3 "equality_op" [(match_operand:CC 4 + "register_operand" + "z,z") + (const_int 0)]) + (match_operand:SI 1 "reg_or_0_operand" "dJ,0") + (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "@ + mov%T3\\t%0,%z1,%4 + mov%t3\\t%0,%z2,%4" + [(set_attr "type" "move") + (set_attr "mode" "SI")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (if_then_else:DI + (match_operator 4 "equality_op" + [(match_operand:SI 1 "register_operand" "d,d") + (const_int 0)]) + (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0") + (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))] + "mips_isa >= 4" + "@ + mov%B4\\t%0,%z2,%1 + mov%b4\\t%0,%z3,%1" + [(set_attr "type" "move") + (set_attr "mode" "DI")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (if_then_else:DI + (match_operator 4 "equality_op" + [(match_operand:DI 1 "se_register_operand" "d,d") + (const_int 0)]) + (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0") + (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))] + "mips_isa >= 4" + "@ + mov%B4\\t%0,%z2,%1 + mov%b4\\t%0,%z3,%1" + [(set_attr "type" "move") + (set_attr "mode" "DI")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (if_then_else:DI + (match_operator 3 "equality_op" [(match_operand:CC 4 + "register_operand" + "z,z") + (const_int 0)]) + (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0") + (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "@ + mov%T3\\t%0,%z1,%4 + mov%t3\\t%0,%z2,%4" + [(set_attr "type" "move") + (set_attr "mode" "DI")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (if_then_else:SF + (match_operator 4 "equality_op" + [(match_operand:SI 1 "register_operand" "d,d") + (const_int 0)]) + (match_operand:SF 2 "register_operand" "f,0") + (match_operand:SF 3 "register_operand" "0,f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "@ + mov%B4.s\\t%0,%2,%1 + mov%b4.s\\t%0,%3,%1" + [(set_attr "type" "move") + (set_attr "mode" "SF")]) + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (if_then_else:SF + (match_operator 3 "equality_op" [(match_operand:CC 4 + "register_operand" + "z,z") + (const_int 0)]) + (match_operand:SF 1 "register_operand" "f,0") + (match_operand:SF 2 "register_operand" "0,f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + "@ + mov%T3.s\\t%0,%1,%4 + mov%t3.s\\t%0,%2,%4" + [(set_attr "type" "move") + (set_attr "mode" "SF")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (if_then_else:DF + (match_operator 4 "equality_op" + [(match_operand:SI 1 "register_operand" "d,d") + (const_int 0)]) + (match_operand:DF 2 "register_operand" "f,0") + (match_operand:DF 3 "register_operand" "0,f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "@ + mov%B4.d\\t%0,%2,%1 + mov%b4.d\\t%0,%3,%1" + [(set_attr "type" "move") + (set_attr "mode" "DF")]) + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (if_then_else:DF + (match_operator 3 "equality_op" [(match_operand:CC 4 + "register_operand" + "z,z") + (const_int 0)]) + (match_operand:DF 1 "register_operand" "f,0") + (match_operand:DF 2 "register_operand" "0,f")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "@ + mov%T3.d\\t%0,%1,%4 + mov%t3.d\\t%0,%2,%4" + [(set_attr "type" "move") + (set_attr "mode" "DF")]) + +;; These are the main define_expand's used to make conditional moves. + +(define_expand "movsicc" + [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) + (set (match_operand:SI 0 "register_operand" "") + (if_then_else:SI (match_dup 5) + (match_operand:SI 2 "reg_or_0_operand" "") + (match_operand:SI 3 "reg_or_0_operand" "")))] + "mips_isa >= 4" + " +{ + gen_conditional_move (operands); + DONE; +}") + +(define_expand "movdicc" + [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) + (set (match_operand:DI 0 "register_operand" "") + (if_then_else:DI (match_dup 5) + (match_operand:DI 2 "se_reg_or_0_operand" "") + (match_operand:DI 3 "se_reg_or_0_operand" "")))] + "mips_isa >= 4" + " +{ + gen_conditional_move (operands); + DONE; +}") + +(define_expand "movsfcc" + [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) + (set (match_operand:SF 0 "register_operand" "") + (if_then_else:SF (match_dup 5) + (match_operand:SF 2 "register_operand" "") + (match_operand:SF 3 "register_operand" "")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT" + " +{ + gen_conditional_move (operands); + DONE; +}") + +(define_expand "movdfcc" + [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) + (set (match_operand:DF 0 "register_operand" "") + (if_then_else:DF (match_dup 5) + (match_operand:DF 2 "register_operand" "") + (match_operand:DF 3 "register_operand" "")))] + "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + " +{ + gen_conditional_move (operands); + DONE; +}") + +;; +;; .................... +;; +;; mips16 inline constant tables +;; +;; .................... +;; + +(define_insn "consttable_qi" + [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")] 10)] + "TARGET_MIPS16" + "* +{ + assemble_integer (operands[0], 1, 1); + return \"\"; +}" + [(set_attr "type" "unknown") + (set_attr "mode" "QI") + (set_attr "length" "2")]) + +(define_insn "consttable_hi" + [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")] 11)] + "TARGET_MIPS16" + "* +{ + assemble_integer (operands[0], 2, 1); + return \"\"; +}" + [(set_attr "type" "unknown") + (set_attr "mode" "HI") + (set_attr "length" "2")]) + +(define_insn "consttable_si" + [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")] 12)] + "TARGET_MIPS16" + "* +{ + assemble_integer (operands[0], 4, 1); + return \"\"; +}" + [(set_attr "type" "unknown") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_insn "consttable_di" + [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")] 13)] + "TARGET_MIPS16" + "* +{ + assemble_integer (operands[0], 8, 1); + return \"\"; +}" + [(set_attr "type" "unknown") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + +(define_insn "consttable_sf" + [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")] 14)] + "TARGET_MIPS16" + "* +{ + union real_extract u; + + if (GET_CODE (operands[0]) != CONST_DOUBLE) + abort (); + bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u); + assemble_real (u.d, SFmode); + return \"\"; +}" + [(set_attr "type" "unknown") + (set_attr "mode" "SF") + (set_attr "length" "2")]) + +(define_insn "consttable_df" + [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")] 15)] + "TARGET_MIPS16" + "* +{ + union real_extract u; + + if (GET_CODE (operands[0]) != CONST_DOUBLE) + abort (); + bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u); + assemble_real (u.d, DFmode); + return \"\"; +}" + [(set_attr "type" "unknown") + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +(define_insn "align_2" + [(unspec_volatile [(const_int 0)] 16)] + "TARGET_MIPS16" + ".align 1" + [(set_attr "type" "unknown") + (set_attr "mode" "HI") + (set_attr "length" "2")]) + +(define_insn "align_4" + [(unspec_volatile [(const_int 0)] 17)] + "TARGET_MIPS16" + ".align 2" + [(set_attr "type" "unknown") + (set_attr "mode" "SI") + (set_attr "length" "2")]) + +(define_insn "align_8" + [(unspec_volatile [(const_int 0)] 18)] + "TARGET_MIPS16" + ".align 3" + [(set_attr "type" "unknown") + (set_attr "mode" "DI") + (set_attr "length" "3")]) + +;; +;; .................... +;; +;; mips16 peepholes +;; +;; .................... +;; + +;; On the mips16, reload will sometimes decide that a pseudo register +;; should go into $24, and then later on have to reload that register. +;; When that happens, we get a load of a general register followed by +;; a move from the general register to $24 followed by a branch. +;; These peepholes catch the common case, and fix it to just use the +;; general register for the branch. + +(define_peephole + [(set (match_operand:SI 0 "register_operand" "=t") + (match_operand:SI 1 "register_operand" "d")) + (set (pc) + (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0) + (const_int 0)]) + (match_operand 3 "pc_or_label_operand" "") + (match_operand 4 "pc_or_label_operand" "")))] + "TARGET_MIPS16 + && GET_CODE (operands[0]) == REG + && REGNO (operands[0]) == 24 + && dead_or_set_p (insn, operands[0]) + && GET_CODE (operands[1]) == REG + && M16_REG_P (REGNO (operands[1]))" + "* +{ + if (operands[3] != pc_rtx) + return \"%*b%C2z\\t%1,%3\"; + else + return \"%*b%N2z\\t%1,%4\"; +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_peephole + [(set (match_operand:DI 0 "register_operand" "=t") + (match_operand:DI 1 "register_operand" "d")) + (set (pc) + (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0) + (const_int 0)]) + (match_operand 3 "pc_or_label_operand" "") + (match_operand 4 "pc_or_label_operand" "")))] + "TARGET_MIPS16 && TARGET_64BIT + && GET_CODE (operands[0]) == REG + && REGNO (operands[0]) == 24 + && dead_or_set_p (insn, operands[0]) + && GET_CODE (operands[1]) == REG + && M16_REG_P (REGNO (operands[1]))" + "* +{ + if (operands[3] != pc_rtx) + return \"%*b%C2z\\t%1,%3\"; + else + return \"%*b%N2z\\t%1,%4\"; +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +;; We can also have the reverse reload: reload will spill $24 into +;; another register, and then do a branch on that register when it +;; could have just stuck with $24. + +(define_peephole + [(set (match_operand:SI 0 "register_operand" "=d") + (match_operand:SI 1 "register_operand" "t")) + (set (pc) + (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0) + (const_int 0)]) + (match_operand 3 "pc_or_label_operand" "") + (match_operand 4 "pc_or_label_operand" "")))] + "TARGET_MIPS16 + && GET_CODE (operands[1]) == REG + && REGNO (operands[1]) == 24 + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && dead_or_set_p (insn, operands[0])" + "* +{ + if (operands[3] != pc_rtx) + return \"%*bt%C2z\\t%3\"; + else + return \"%*bt%N2z\\t%4\"; +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +(define_peephole + [(set (match_operand:DI 0 "register_operand" "=d") + (match_operand:DI 1 "register_operand" "t")) + (set (pc) + (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0) + (const_int 0)]) + (match_operand 3 "pc_or_label_operand" "") + (match_operand 4 "pc_or_label_operand" "")))] + "TARGET_MIPS16 && TARGET_64BIT + && GET_CODE (operands[1]) == REG + && REGNO (operands[1]) == 24 + && GET_CODE (operands[0]) == REG + && M16_REG_P (REGNO (operands[0])) + && dead_or_set_p (insn, operands[0])" + "* +{ + if (operands[3] != pc_rtx) + return \"%*bt%C2z\\t%3\"; + else + return \"%*bt%N2z\\t%4\"; +}" + [(set_attr "type" "branch") + (set_attr "mode" "none") + (set_attr "length" "2")]) + +;; For the rare case where we need to load an address into a register +;; that can not be recognized by the normal movsi/addsi instructions. +;; I have no idea how many insns this can actually generate. It should +;; be rare, so over-estimating as 10 instructions should not have any +;; real performance impact. +(define_insn "leasi" + [(set (match_operand:SI 0 "register_operand" "=d") + (match_operand:SI 1 "address_operand" "p"))] + "Pmode == SImode" + "la %0,%a1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "10")]) + +;; Similarly for targets where we have 64bit pointers. +(define_insn "leadi" + [(set (match_operand:DI 0 "register_operand" "=d") + (match_operand:DI 1 "address_operand" "p"))] + "Pmode == DImode" + "la %0,%a1" + [(set_attr "type" "arith") + (set_attr "mode" "DI") + (set_attr "length" "10")]) diff --git a/contrib/gcc/config/mips/mips16.S b/contrib/gcc/config/mips/mips16.S new file mode 100644 index 000000000000..f21f10f2118b --- /dev/null +++ b/contrib/gcc/config/mips/mips16.S @@ -0,0 +1,740 @@ +/* mips16 floating point support code + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by Cygnus Support + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file with other programs, and to distribute +those programs without any restriction coming from the use of this +file. (The General Public License restrictions do apply in other +respects; for example, they cover modification of the file, and +distribution when not linked into another program.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with other files, + some of which are compiled with GCC, to produce an executable, + this library does not by itself cause the resulting executable + to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +/* This file contains mips16 floating point support functions. These + functions are called by mips16 code to handle floating point when + -msoft-float is not used. They accept the arguments and return + values using the soft-float calling convention, but do the actual + operation using the hard floating point instructions. */ + +/* This file contains 32 bit assembly code. */ + .set nomips16 + +/* Start a function. */ + +#define STARTFN(NAME) .globl NAME; .ent NAME; NAME: + +/* Finish a function. */ + +#define ENDFN(NAME) .end NAME + +/* Single precision math. */ + +/* This macro defines a function which loads two single precision + values, performs an operation, and returns the single precision + result. */ + +#define SFOP(NAME, OPCODE) \ +STARTFN (NAME); \ + .set noreorder; \ + mtc1 $4,$f0; \ + mtc1 $5,$f2; \ + nop; \ + OPCODE $f0,$f0,$f2; \ + mfc1 $2,$f0; \ + j $31; \ + nop; \ + .set reorder; \ + ENDFN (NAME) + +#ifdef L_m16addsf3 +SFOP(__mips16_addsf3, add.s) +#endif +#ifdef L_m16subsf3 +SFOP(__mips16_subsf3, sub.s) +#endif +#ifdef L_m16mulsf3 +SFOP(__mips16_mulsf3, mul.s) +#endif +#ifdef L_m16divsf3 +SFOP(__mips16_divsf3, div.s) +#endif + +#define SFOP2(NAME, OPCODE) \ +STARTFN (NAME); \ + .set noreorder; \ + mtc1 $4,$f0; \ + nop; \ + OPCODE $f0,$f0; \ + mfc1 $2,$f0; \ + j $31; \ + nop; \ + .set reorder; \ + ENDFN (NAME) + +#ifdef L_m16negsf2 +SFOP2(__mips16_negsf2, neg.s) +#endif +#ifdef L_m16abssf2 +SFOP2(__mips16_abssf2, abs.s) +#endif + +/* Single precision comparisons. */ + +/* This macro defines a function which loads two single precision + values, performs a floating point comparison, and returns the + specified values according to whether the comparison is true or + false. */ + +#define SFCMP(NAME, OPCODE, TRUE, FALSE) \ +STARTFN (NAME); \ + mtc1 $4,$f0; \ + mtc1 $5,$f2; \ + OPCODE $f0,$f2; \ + li $2,TRUE; \ + bc1t 1f; \ + li $2,FALSE; \ +1:; \ + j $31; \ + ENDFN (NAME) + +/* This macro is like SFCMP, but it reverses the comparison. */ + +#define SFREVCMP(NAME, OPCODE, TRUE, FALSE) \ +STARTFN (NAME); \ + mtc1 $4,$f0; \ + mtc1 $5,$f2; \ + OPCODE $f2,$f0; \ + li $2,TRUE; \ + bc1t 1f; \ + li $2,FALSE; \ +1:; \ + j $31; \ + ENDFN (NAME) + +#ifdef L_m16eqsf2 +SFCMP(__mips16_eqsf2, c.eq.s, 0, 1) +#endif +#ifdef L_m16nesf2 +SFCMP(__mips16_nesf2, c.eq.s, 0, 1) +#endif +#ifdef L_m16gtsf2 +SFREVCMP(__mips16_gtsf2, c.lt.s, 1, 0) +#endif +#ifdef L_m16gesf2 +SFREVCMP(__mips16_gesf2, c.le.s, 0, -1) +#endif +#ifdef L_m16lesf2 +SFCMP(__mips16_lesf2, c.le.s, 0, 1) +#endif +#ifdef L_m16ltsf2 +SFCMP(__mips16_ltsf2, c.lt.s, -1, 0) +#endif + +/* Single precision conversions. */ + +#ifdef L_m16fltsisf +STARTFN (__mips16_floatsisf) + .set noreorder + mtc1 $4,$f0 + nop + cvt.s.w $f0,$f0 + mfc1 $2,$f0 + j $31 + nop + .set reorder + ENDFN (__mips16_floatsisf) +#endif + +#ifdef L_m16fixsfsi +STARTFN (__mips16_fixsfsi) + .set noreorder + mtc1 $4,$f0 + nop + trunc.w.s $f0,$f0,$4 + mfc1 $2,$f0 + j $31 + nop + .set reorder + ENDFN (__mips16_fixsfsi) +#endif + +#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT) + +/* The double precision operations. We need to use different code + based on the preprocessor symbol __mips64, because the way in which + double precision values will change. Without __mips64, the value + is passed in two 32 bit registers. With __mips64, the value is + passed in a single 64 bit register. */ + +/* Load the first double precision operand. */ + +#if defined(__mips64) +#define LDDBL1 dmtc1 $4,$f12 +#elif defined(__mipsfp64) +#define LDDBL1 sw $4,0($29); sw $5,4($29); l.d $f12,0($29) +#elif defined(__MIPSEB__) +#define LDDBL1 mtc1 $4,$f13; mtc1 $5,$f12 +#else +#define LDDBL1 mtc1 $4,$f12; mtc1 $5,$f13 +#endif + +/* Load the second double precision operand. */ + +#if defined(__mips64) +/* XXX this should be $6 for Algo arg passing model */ +#define LDDBL2 dmtc1 $5,$f14 +#elif defined(__mipsfp64) +#define LDDBL2 sw $6,8($29); sw $7,12($29); l.d $f14,8($29) +#elif defined(__MIPSEB__) +#define LDDBL2 mtc1 $6,$f15; mtc1 $7,$f14 +#else +#define LDDBL2 mtc1 $6,$f14; mtc1 $7,$f15 +#endif + +/* Move the double precision return value to the right place. */ + +#if defined(__mips64) +#define RETDBL dmfc1 $2,$f0 +#elif defined(__mipsfp64) +#define RETDBL s.d $f0,0($29); lw $2,0($29); lw $3,4($29) +#elif defined(__MIPSEB__) +#define RETDBL mfc1 $2,$f1; mfc1 $3,$f0 +#else +#define RETDBL mfc1 $2,$f0; mfc1 $3,$f1 +#endif + +/* Double precision math. */ + +/* This macro defines a function which loads two double precision + values, performs an operation, and returns the double precision + result. */ + +#define DFOP(NAME, OPCODE) \ +STARTFN (NAME); \ + .set noreorder; \ + LDDBL1; \ + LDDBL2; \ + nop; \ + OPCODE $f0,$f12,$f14; \ + RETDBL; \ + j $31; \ + nop; \ + .set reorder; \ + ENDFN (NAME) + +#ifdef L_m16adddf3 +DFOP(__mips16_adddf3, add.d) +#endif +#ifdef L_m16subdf3 +DFOP(__mips16_subdf3, sub.d) +#endif +#ifdef L_m16muldf3 +DFOP(__mips16_muldf3, mul.d) +#endif +#ifdef L_m16divdf3 +DFOP(__mips16_divdf3, div.d) +#endif + +#define DFOP2(NAME, OPCODE) \ +STARTFN (NAME); \ + .set noreorder; \ + LDDBL1; \ + nop; \ + OPCODE $f0,$f12; \ + RETDBL; \ + j $31; \ + nop; \ + .set reorder; \ + ENDFN (NAME) + +#ifdef L_m16negdf2 +DFOP2(__mips16_negdf2, neg.d) +#endif +#ifdef L_m16absdf2 +DFOP2(__mips16_absdf2, abs.d) +#endif + + +/* Conversions between single and double precision. */ + +#ifdef L_m16extsfdf2 +STARTFN (__mips16_extendsfdf2) + .set noreorder + mtc1 $4,$f12 + nop + cvt.d.s $f0,$f12 + RETDBL + j $31 + nop + .set reorder + ENDFN (__mips16_extendsfdf2) +#endif + +#ifdef L_m16trdfsf2 +STARTFN (__mips16_truncdfsf2) + .set noreorder + LDDBL1 + nop + cvt.s.d $f0,$f12 + mfc1 $2,$f0 + j $31 + nop + .set reorder + ENDFN (__mips16_truncdfsf2) +#endif + +/* Double precision comparisons. */ + +/* This macro defines a function which loads two double precision + values, performs a floating point comparison, and returns the + specified values according to whether the comparison is true or + false. */ + +#define DFCMP(NAME, OPCODE, TRUE, FALSE) \ +STARTFN (NAME); \ + LDDBL1; \ + LDDBL2; \ + OPCODE $f12,$f14; \ + li $2,TRUE; \ + bc1t 1f; \ + li $2,FALSE; \ +1:; \ + j $31; \ + ENDFN (NAME) + +/* This macro is like DFCMP, but it reverses the comparison. */ + +#define DFREVCMP(NAME, OPCODE, TRUE, FALSE) \ +STARTFN (NAME); \ + LDDBL1; \ + LDDBL2; \ + OPCODE $f14,$f12; \ + li $2,TRUE; \ + bc1t 1f; \ + li $2,FALSE; \ +1:; \ + j $31; \ + ENDFN (NAME) + +#ifdef L_m16eqdf2 +DFCMP(__mips16_eqdf2, c.eq.d, 0, 1) +#endif +#ifdef L_m16nedf2 +DFCMP(__mips16_nedf2, c.eq.d, 0, 1) +#endif +#ifdef L_m16gtdf2 +DFREVCMP(__mips16_gtdf2, c.lt.d, 1, 0) +#endif +#ifdef L_m16gedf2 +DFREVCMP(__mips16_gedf2, c.le.d, 0, -1) +#endif +#ifdef L_m16ledf2 +DFCMP(__mips16_ledf2, c.le.d, 0, 1) +#endif +#ifdef L_m16ltdf2 +DFCMP(__mips16_ltdf2, c.lt.d, -1, 0) +#endif + +/* Double precision conversions. */ + +#ifdef L_m16fltsidf +STARTFN (__mips16_floatsidf) + .set noreorder + mtc1 $4,$f12 + nop + cvt.d.w $f0,$f12 + RETDBL + j $31 + nop + .set reorder + ENDFN (__mips16_floatsidf) +#endif + +#ifdef L_m16fixdfsi +STARTFN (__mips16_fixdfsi) + .set noreorder + LDDBL1 + nop + trunc.w.d $f0,$f12,$4 + mfc1 $2,$f0 + j $31 + nop + .set reorder + ENDFN (__mips16_fixdfsi) +#endif +#endif /* !__mips_single_float */ + +/* These functions are used to return floating point values from + mips16 functions which do not use -mentry. In this case we can + put mtc1 in a jump delay slot, because we know that the next + instruction will not refer to a floating point register. */ + +#ifdef L_m16retsf +STARTFN (__mips16_ret_sf) + .set noreorder + j $31 + mtc1 $2,$f0 + .set reorder + ENDFN (__mips16_ret_sf) +#endif + +#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT) +#ifdef L_m16retdf +STARTFN (__mips16_ret_df) + .set noreorder +#if defined(__mips64) + j $31 + dmtc1 $2,$f0 +#elif defined(__mipsfp64) + sw $2,0($29) + sw $3,4($29) + l.d $f0,0($29) +#elif defined(__MIPSEB__) + mtc1 $2,$f1 + j $31 + mtc1 $3,$f0 +#else + mtc1 $2,$f0 + j $31 + mtc1 $3,$f1 +#endif + .set reorder + ENDFN (__mips16_ret_df) +#endif +#endif /* !__mips_single_float */ + +/* These functions are used by 16 bit code when calling via a function + pointer. They must copy the floating point arguments from the gp + regs into the fp regs. The function to call will be in $2. The + exact set of floating point arguments to copy is encoded in the + function name; the final number is an fp_code, as described in + mips.h in the comment about CUMULATIVE_ARGS. */ + +#ifdef L_m16stub1 +/* (float) */ +STARTFN (__mips16_call_stub_1) + .set noreorder + mtc1 $4,$f12 + j $2 + nop + .set reorder + ENDFN (__mips16_call_stub_1) +#endif + +#ifdef L_m16stub5 +/* (float, float) */ +STARTFN (__mips16_call_stub_5) + .set noreorder + mtc1 $4,$f12 + mtc1 $5,$f14 + j $2 + nop + .set reorder + ENDFN (__mips16_call_stub_5) +#endif + +#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT) + +#ifdef L_m16stub2 +/* (double) */ +STARTFN (__mips16_call_stub_2) + .set noreorder + LDDBL1 + j $2 + nop + .set reorder + ENDFN (__mips16_call_stub_2) +#endif + +#ifdef L_m16stub6 +/* (double, float) */ +STARTFN (__mips16_call_stub_6) + .set noreorder + LDDBL1 + mtc1 $6,$f14 + j $2 + nop + .set reorder + ENDFN (__mips16_call_stub_6) +#endif + +#ifdef L_m16stub9 +/* (float, double) */ +STARTFN (__mips16_call_stub_9) + .set noreorder + mtc1 $4,$f12 + LDDBL2 + j $2 + nop + .set reorder + ENDFN (__mips16_call_stub_9) +#endif + +#ifdef L_m16stub10 +/* (double, double) */ +STARTFN (__mips16_call_stub_10) + .set noreorder + LDDBL1 + LDDBL2 + j $2 + nop + .set reorder + ENDFN (__mips16_call_stub_10) +#endif +#endif /* !__mips_single_float */ + +/* Now we have the same set of functions, except that this time the + function being called returns an SFmode value. The calling + function will arrange to preserve $18, so these functions are free + to use it to hold the return address. + + Note that we do not know whether the function we are calling is 16 + bit or 32 bit. However, it does not matter, because 16 bit + functions always return floating point values in both the gp and + the fp regs. It would be possible to check whether the function + being called is 16 bits, in which case the copy is unnecessary; + however, it's faster to always do the copy. */ + +#ifdef L_m16stubsf0 +/* () */ +STARTFN (__mips16_call_stub_sf_0) + .set noreorder + move $18,$31 + jal $2 + nop + mfc1 $2,$f0 + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_sf_0) +#endif + +#ifdef L_m16stubsf1 +/* (float) */ +STARTFN (__mips16_call_stub_sf_1) + .set noreorder + mtc1 $4,$f12 + move $18,$31 + jal $2 + nop + mfc1 $2,$f0 + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_sf_1) +#endif + +#ifdef L_m16stubsf5 +/* (float, float) */ +STARTFN (__mips16_call_stub_sf_5) + .set noreorder + mtc1 $4,$f12 + mtc1 $5,$f14 + move $18,$31 + jal $2 + nop + mfc1 $2,$f0 + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_sf_5) +#endif + +#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT) +#ifdef L_m16stubsf2 +/* (double) */ +STARTFN (__mips16_call_stub_sf_2) + .set noreorder + LDDBL1 + move $18,$31 + jal $2 + nop + mfc1 $2,$f0 + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_sf_2) +#endif + +#ifdef L_m16stubsf6 +/* (double, float) */ +STARTFN (__mips16_call_stub_sf_6) + .set noreorder + LDDBL1 + mtc1 $6,$f14 + move $18,$31 + jal $2 + nop + mfc1 $2,$f0 + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_sf_6) +#endif + +#ifdef L_m16stubsf9 +/* (float, double) */ +STARTFN (__mips16_call_stub_sf_9) + .set noreorder + mtc1 $4,$f12 + LDDBL2 + move $18,$31 + jal $2 + nop + mfc1 $2,$f0 + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_sf_9) +#endif + +#ifdef L_m16stubsf10 +/* (double, double) */ +STARTFN (__mips16_call_stub_sf_10) + .set noreorder + LDDBL1 + LDDBL2 + move $18,$31 + jal $2 + nop + mfc1 $2,$f0 + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_sf_10) +#endif + +/* Now we have the same set of functions again, except that this time + the function being called returns an DFmode value. */ + +#ifdef L_m16stubdf0 +/* () */ +STARTFN (__mips16_call_stub_df_0) + .set noreorder + move $18,$31 + jal $2 + nop + RETDBL + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_df_0) +#endif + +#ifdef L_m16stubdf1 +/* (float) */ +STARTFN (__mips16_call_stub_df_1) + .set noreorder + mtc1 $4,$f12 + move $18,$31 + jal $2 + nop + RETDBL + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_df_1) +#endif + +#ifdef L_m16stubdf2 +/* (double) */ +STARTFN (__mips16_call_stub_df_2) + .set noreorder + LDDBL1 + move $18,$31 + jal $2 + nop + RETDBL + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_df_2) +#endif + +#ifdef L_m16stubdf5 +/* (float, float) */ +STARTFN (__mips16_call_stub_df_5) + .set noreorder + mtc1 $4,$f12 + mtc1 $5,$f14 + move $18,$31 + jal $2 + nop + RETDBL + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_df_5) +#endif + +#ifdef L_m16stubdf6 +/* (double, float) */ +STARTFN (__mips16_call_stub_df_6) + .set noreorder + LDDBL1 + mtc1 $6,$f14 + move $18,$31 + jal $2 + nop + RETDBL + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_df_6) +#endif + +#ifdef L_m16stubdf9 +/* (float, double) */ +STARTFN (__mips16_call_stub_df_9) + .set noreorder + mtc1 $4,$f12 + LDDBL2 + move $18,$31 + jal $2 + nop + RETDBL + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_df_9) +#endif + +#ifdef L_m16stubdf10 +/* (double, double) */ +STARTFN (__mips16_call_stub_df_10) + .set noreorder + LDDBL1 + LDDBL2 + move $18,$31 + jal $2 + nop + RETDBL + j $18 + nop + .set reorder + ENDFN (__mips16_call_stub_df_10) +#endif +#endif /* !__mips_single_float */ + diff --git a/contrib/gcc/config/mips/netbsd.h b/contrib/gcc/config/mips/netbsd.h new file mode 100644 index 000000000000..3fce9fb1de3f --- /dev/null +++ b/contrib/gcc/config/mips/netbsd.h @@ -0,0 +1,227 @@ +/* Definitions for DECstation running BSD as target machine for GNU compiler. + Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define DECSTATION + +/* Look for the include files in the system-defined places. */ + +#ifndef CROSS_COMPILE +#undef GPLUSPLUS_INCLUDE_DIR +#define GPLUSPLUS_INCLUDE_DIR "/usr/include/g++" + +#undef GCC_INCLUDE_DIR +#define GCC_INCLUDE_DIR "/usr/include" + +#undef INCLUDE_DEFAULTS +#define INCLUDE_DEFAULTS \ + { \ + { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1 }, \ + { GCC_INCLUDE_DIR, "GCC", 0, 0 }, \ + { 0, 0, 0, 0 } \ + } + +/* Under NetBSD, the normal location of the various *crt*.o files is the + /usr/lib directory. */ + +#undef STANDARD_STARTFILE_PREFIX +#define STANDARD_STARTFILE_PREFIX "/usr/lib/" +#endif + +/* Provide a LINK_SPEC appropriate for NetBSD. Here we provide support + for the special GCC options -static, -assert, and -nostdlib. */ + +#undef LINK_SPEC +#define LINK_SPEC \ + "%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ + %{!nostartfiles:%{!r*:%{!e*:-e __start}}} -dc -dp %{static:-Bstatic} %{assert*}" + +/* We have atexit(3). */ + +#define HAVE_ATEXIT + +/* Implicit library calls should use memcpy, not bcopy, etc. */ + +#define TARGET_MEM_FUNCTIONS + +/* Define mips-specific netbsd predefines... */ +#ifndef CPP_PREDEFINES +#define CPP_PREDEFINES "-D__ANSI_COMPAT \ +-DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -D__NetBSD__ -Dmips \ +-D__NO_LEADING_UNDERSCORES__ -D__GP_SUPPORT__ \ +-Dunix -D_R3000 \ +-Asystem(unix) -Asystem(NetBSD) -Amachine(mips)" +#endif + +#ifndef SUBTARGET_CPP_SPEC +#define SUBTARGET_CPP_SPEC "%{posix:-D_POSIX_SOURCE}" +#endif + +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" +#define STARTFILE_SPEC "" + +#ifndef MACHINE_TYPE +#define MACHINE_TYPE "NetBSD/pmax" +#endif + +#define TARGET_DEFAULT MASK_GAS +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "mips/mips.h" + +/* + * Some imports from svr4.h in support of shared libraries. + * Currently, we need the DECLARE_OBJECT_SIZE stuff. + */ + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#undef TYPE_ASM_OP +#undef SIZE_ASM_OP +#undef WEAK_ASM_OP +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" +#define WEAK_ASM_OP ".weak" + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#undef TYPE_OPERAND_FMT +#define TYPE_OPERAND_FMT "@%s" + +/* Write the extra assembler code needed to declare a function's result. + Most svr4 assemblers don't require any special declaration of the + result value, but there are exceptions. */ + +#ifndef ASM_DECLARE_RESULT +#define ASM_DECLARE_RESULT(FILE, RESULT) +#endif + +/* These macros generate the special .type and .size directives which + are used to set the corresponding fields of the linker symbol table + entries in an ELF object file under SVR4. These macros also output + the starting labels for the relevant functions/objects. */ + +/* Write the extra assembler code needed to declare a function properly. + Some svr4 assemblers need to also have something extra said about the + function's return value. We allow for that here. */ + +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ + putc ('\n', FILE); \ + ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ + } while (0) + +/* Write the extra assembler code needed to declare an object properly. */ + +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + ASM_OUTPUT_LABEL(FILE, NAME); \ + } while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#undef ASM_FINISH_DECLARE_OBJECT +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +/* This is how to declare the size of a function. */ + +#undef ASM_DECLARE_FUNCTION_SIZE +#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ + do { \ + if (!flag_inhibit_size_directive) \ + { \ + char label[256]; \ + static int labelno; \ + labelno++; \ + ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ + ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, (FNAME)); \ + fprintf (FILE, ","); \ + assemble_name (FILE, label); \ + fprintf (FILE, "-"); \ + assemble_name (FILE, (FNAME)); \ + putc ('\n', FILE); \ + } \ + } while (0) + +/* + A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. Some target formats do not support arbitrary sections. Do not + define this macro in such cases. +*/ +#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \ +do { \ + extern FILE *asm_out_text_file; \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \ + fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \ + else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \ + fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME)); \ + else \ + fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME)); \ +} while (0) + +/* Since gas and gld are standard on NetBSD, we don't need these */ +#undef ASM_FINAL_SPEC +#undef STARTFILE_SPEC diff --git a/contrib/gcc/config/mips/news4.h b/contrib/gcc/config/mips/news4.h new file mode 100644 index 000000000000..502affa67c70 --- /dev/null +++ b/contrib/gcc/config/mips/news4.h @@ -0,0 +1,39 @@ +/* Definitions of target machine for GNU compiler. Sony RISC NEWS (mips) + Copyright (C) 1991, 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_NEWS + +#define CPP_PREDEFINES "\ +-Dr3000 -Dnews3700 -DLANGUAGE_C -DMIPSEB -DSYSTYPE_BSD \ +-Dsony_news -Dsony -Dunix -Dmips -Dhost_mips \ +-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)" + +#define SYSTEM_INCLUDE_DIR "/usr/include2.0" + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" + +#define MACHINE_TYPE "RISC NEWS-OS" + +/* INITIALIZE_TRAMPOLINE calls this library function to flush + program and data caches. */ +#define CACHE_FLUSH_FUNC "cacheflush" + diff --git a/contrib/gcc/config/mips/news5.h b/contrib/gcc/config/mips/news5.h new file mode 100644 index 000000000000..a776064d1930 --- /dev/null +++ b/contrib/gcc/config/mips/news5.h @@ -0,0 +1,62 @@ +/* Definitions of target machine for GNU compiler. + Sony RISC NEWS (mips) System V version. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_SYSV + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -Dsony -Dsonyrisc -DMIPSEB -DSYSTYPE_SYSV \ +-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)" + +#define MD_STARTFILE_PREFIX "/usr/ccs/lib/" + +#define LIB_SPEC "\ +%{ZBSD43: -L/usr/ucblib -lucb -lresolv -lsocket -lnsl} \ +-nocount %{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s values-Xt.o%s" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:-nocount crt1.o%s -count}}" + +#define MACHINE_TYPE "Sony RISC NEWS (SVR4 mips)" + +#define NO_LIB_PROTOTYPE + +#define NO_DOLLAR_IN_LABEL + +#define NM_FLAGS "-Bp" + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* Mips System V.4 doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + +#ifdef L_trampoline +#include <sys/param.h> +#include <unistd.h> + +#ifdef _SC_PAGE_SIZE +#define getpagesize() sysconf(_SC_PAGE_SIZE) + +#else /* older rev of OS */ +#define getpagesize() (NBPC) +#endif /* !_SC_PAGE_SIZE */ +#endif /* L_trampoline */ + diff --git a/contrib/gcc/config/mips/nws3250v4.h b/contrib/gcc/config/mips/nws3250v4.h new file mode 100644 index 000000000000..611effe02a16 --- /dev/null +++ b/contrib/gcc/config/mips/nws3250v4.h @@ -0,0 +1,36 @@ +/* Definitions of target machine for GNU compiler. Sony RISC NEWS (mips) + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_NEWS + +#define CPP_PREDEFINES "\ +-Dmips -Dhost_mips -Dsony -Dsonyrisc -Dunix \ +-DLANGUAGE_C -DMIPSEB -DSYSTYPE_SYSV \ +-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)" + +#define MD_STARTFILE_PREFIX "/usr/ccs/lib/" + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s values-Xt.o%s" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}" + +#define MACHINE_TYPE "RISC NEWS-OS SVr4" + +#include "mips/mips.h" diff --git a/contrib/gcc/config/mips/osfrose.h b/contrib/gcc/config/mips/osfrose.h new file mode 100644 index 000000000000..3d92619c3e58 --- /dev/null +++ b/contrib/gcc/config/mips/osfrose.h @@ -0,0 +1,150 @@ +/* Definitions of target machine for GNU compiler. + DECstation (OSF/1 reference port with OSF/rose) version. + Copyright (C) 1991, 1992, 1995, 1996, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define DECSTATION +#define OSF_OS + +#define HALF_PIC_DEBUG TARGET_DEBUG_B_MODE +#define HALF_PIC_PREFIX "$Lp." + +#include "halfpic.h" + +#define WORD_SWITCH_TAKES_ARG(STR) \ + (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) || !strcmp (STR, "pic-names")) + +#define CPP_PREDEFINES "\ +-DOSF -DOSF1 -Dbsd4_2 -DMIPSEL -Dhost_mips -Dmips -Dunix -DR3000 -DSYSTYPE_BSD \ +-Asystem(unix) -Asystem(xpg4) -Acpu(mips) -Amachine(mips)" + +#define SUBTARGET_CPP_SIZE_SPEC "\ +%{mlong64:-D__PTRDIFF_TYPE__=long\\ int} \ +%{!mlong64:-D__PTRDIFF_TYPE__=int}" + +#define SUBTARGET_CPP_SPEC "\ +%{.S: %{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \ +%{.s: %{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}}" + +/* ??? This assumes that GNU as is always used with GNU ld, and MIPS as is + always used with MIPS ld. */ +#define LINK_SPEC "\ +%{G*} %{EL} %{EB} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} \ +%{!mmips-as: \ + %{v*: -v} \ + %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \ + %{nostdlib} %{noshrlib} %{glue}}" + +#define LIB_SPEC "-lc" + +/* Define this macro meaning that `gcc' should find the library + `libgcc.a' by hand, rather than passing the argument `-lgcc' to + tell the linker to do the search. */ + +#define LINK_LIBGCC_SPECIAL 1 + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" + +#define MACHINE_TYPE "DECstation with OSF/rose objects" + +#ifndef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/ccs/gcc/" +#endif + +#ifndef MD_STARTFILE_PREFIX +#define MD_STARTFILE_PREFIX "/usr/ccs/lib/" +#endif + +/* Turn on -mpic-extern by default. */ +#define CC1_SPEC "\ +%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ +%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32} %{mips3:-mfp64 -mgp64} \ +%{mint64|mlong64|mlong32:-mexplicit-type-size }\ +%{G*} \ +%{pic-none: -mno-half-pic} \ +%{pic-lib: -mhalf-pic} \ +%{pic-extern: -mhalf-pic} \ +%{pic-calls: -mhalf-pic} \ +%{pic-names*: -mhalf-pic} \ +%{!pic-*: -mhalf-pic}" + +/* Specify size_t and wchar_t types. */ +#define SIZE_TYPE "long unsigned int" +#define WCHAR_TYPE "unsigned int" +#define WCHAR_TYPE_SIZE BITS_PER_WORD +#define MAX_WCHAR_TYPE_SIZE MAX_LONG_TYPE_SIZE + +/* OSF/1 uses gas, not the mips assembler. */ +#define TARGET_DEFAULT MASK_GAS + +/* OSF/rose uses stabs, not ECOFF. */ +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +/* enable dwarf debugging for testing */ +#define DWARF_DEBUGGING_INFO +/* This is needed by dwarfout.c. */ +#define SET_ASM_OP ".set" + +/* Tell collect that the object format is OSF/rose. */ +#define OBJECT_FORMAT_ROSE + +/* Tell collect where the appropriate binaries are. */ +#define REAL_LD_FILE_NAME "/usr/ccs/gcc/gld" +#define REAL_NM_FILE_NAME "/usr/ccs/bin/nm" +#define REAL_STRIP_FILE_NAME "/usr/ccs/bin/strip" + +/* Default to -G 0 unless doing ecoff work. */ +#define MIPS_DEFAULT_GVALUE ((TARGET_MIPS_AS) ? 8 : 0) + +/* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* A C statement to output assembler commands which will identify + the object file as having been compiled with GNU CC (or another + GNU compiler). + + If you don't define this macro, the string `gcc2_compiled.:' is + output. This string is calculated to define a symbol which, on + BSD systems, will never be defined for any other reason. GDB + checks for the presence of this symbol when reading the symbol + table of an executable. + + On non-BSD systems, you must arrange communication with GDB in + some other fashion. If GDB is not used on your system, you can + define this macro with an empty body. + + On OSF/1, gcc2_compiled. confuses the kernel debugger, so don't + put it out. */ + +#define ASM_IDENTIFY_GCC(STREAM) + +/* Identify the front-end which produced this file. To keep symbol + space down, and not confuse kdb, only do this if the language is + not C. */ + +#define ASM_IDENTIFY_LANGUAGE(STREAM) \ +{ \ + if (strcmp (lang_identify (), "c") != 0) \ + output_lang_identify (STREAM); \ +} diff --git a/contrib/gcc/config/mips/r3900.h b/contrib/gcc/config/mips/r3900.h new file mode 100644 index 000000000000..3d7cac5edc11 --- /dev/null +++ b/contrib/gcc/config/mips/r3900.h @@ -0,0 +1,72 @@ +/* Definitions of MIPS sub target machine for GNU compiler. + Toshiba r3900. You should include mips.h after this. + + Copyright (C) 1989, 90-6, 1997 Free Software Foundation, Inc. + Contributed by Gavin Koch (gavin@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define SUBTARGET_CPP_SPEC "\ +%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}} \ +%{!msingle-float:-D__mips_soft_float} \ +%{mhard-float:%e-mhard-float not supported.} \ +%{msingle-float:%{msoft-float: \ + %e-msingle-float and -msoft-float can not both be specified.}}" + +/* The following is needed because -mips3 and -mips4 set gp64 which in + combination with abi=eabi, causes long64 to be set. */ +#define SUBTARGET_CPP_SIZE_SPEC "\ +%{mips3:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \ +%{mips4:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \ +%{!mips3:%{!mips4:%{!m4650:\ + -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}} " + +/* by default (if not mips-something-else) produce code for the r3900 */ +#define SUBTARGET_CC1_SPEC "\ +%{mhard-float:%e-mhard-float not supported.} \ +%{msingle-float:%{msoft-float: \ + %e-msingle-float and -msoft-float can not both be specified.}}" + +#define TARGET_DEFAULT (MASK_SOFT_FLOAT | MASK_MIPS3900) +#define MIPS_CPU_STRING_DEFAULT "R3900" +#define MIPS_ISA_DEFAULT 1 + +#define MULTILIB_DEFAULTS { "EB", "msoft-float" } + +/* We use the MIPS EABI by default. */ +#define MIPS_ABI_DEFAULT ABI_EABI + + +/* Debugging */ + +#define DWARF2_DEBUGGING_INFO +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + +/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the + gnu assembler not to generate debugging information. */ + +#define SUBTARGET_ASM_DEBUGGING_SPEC "\ +%{!mmips-as: \ + %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \ + %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \ + %{gdwarf-2*:-g0}} \ +%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ +%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ +%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}" + +/* eof */ diff --git a/contrib/gcc/config/mips/rtems64.h b/contrib/gcc/config/mips/rtems64.h new file mode 100644 index 000000000000..cd7997086385 --- /dev/null +++ b/contrib/gcc/config/mips/rtems64.h @@ -0,0 +1,63 @@ +/* Definitions for rtems targeting a MIPS ORION using ecoff. + Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. + Contributed by Joel Sherrill (joel@OARcorp.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000 \ + -Drtems -D__rtems__ -Asystem(rtems)" + +/* Generate calls to memcpy, memcmp and memset. */ +#ifndef TARGET_MEM_FUNCTIONS +#define TARGET_MEM_FUNCTIONS +#endif + +/* Undefine the following which were defined in elf64.h. This will cause the rtems64 + port to continue to use collect2 for constructors/destructors. These may be removed + when .ctor/.dtor section support is desired. */ + +#undef CTORS_SECTION_ASM_OP +#undef DTORS_SECTION_ASM_OP + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata + +#undef INVOKE__main +#undef NAME__MAIN +#undef SYMBOL__MAIN + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) + +#undef ASM_OUTPUT_CONSTRUCTOR +#undef ASM_OUTPUT_DESTRUCTOR + +#undef CTOR_LIST_BEGIN +#undef CTOR_LIST_END +#undef DTOR_LIST_BEGIN +#undef DTOR_LIST_END + +#undef STARTFILE_SPEC +#undef ENDFILE_SPEC + +/* End of undefines to turn off .ctor/.dtor section support */ diff --git a/contrib/gcc/config/mips/sni-gas.h b/contrib/gcc/config/mips/sni-gas.h new file mode 100644 index 000000000000..5b3699820f37 --- /dev/null +++ b/contrib/gcc/config/mips/sni-gas.h @@ -0,0 +1,38 @@ +/* Enable debugging. */ +#define DBX_DEBUGGING_INFO +#define SDB_DEBUGGING_INFO +#define MIPS_DEBUGGING_INFO + +#define DWARF_DEBUGGING_INFO +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG + +/* We need to use .esize and .etype instead of .size and .type to + avoid conflicting with ELF directives. These are only recognized + by gas, anyhow, not the native assembler. */ +#undef PUT_SDB_SIZE +#define PUT_SDB_SIZE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.esize\t%d;", (a)); \ +} while (0) + +#undef PUT_SDB_TYPE +#define PUT_SDB_TYPE(a) \ +do { \ + extern FILE *asm_out_text_file; \ + fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a)); \ +} while (0) + + +/* This is how to equate one symbol to another symbol. The syntax used is + `SYM1=SYM2'. Note that this is different from the way equates are done + with most svr4 assemblers, where the syntax is `.set SYM1,SYM2'. */ + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fprintf ((FILE), "\t"); \ + assemble_name (FILE, LABEL1); \ + fprintf (FILE, " = "); \ + assemble_name (FILE, LABEL2); \ + fprintf (FILE, "\n"); \ + } while (0) diff --git a/contrib/gcc/config/mips/sni-svr4.h b/contrib/gcc/config/mips/sni-svr4.h new file mode 100644 index 000000000000..cf6edbccad6c --- /dev/null +++ b/contrib/gcc/config/mips/sni-svr4.h @@ -0,0 +1,100 @@ +/* Definitions of target machine for GNU compiler. SNI SINIX version. + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Marco Walther (Marco.Walther@mch.sni.de). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_SVR4 + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 -Dsinix -DSNI \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \ +-Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)" + +#define SUBTARGET_CPP_SIZE_SPEC "\ +-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int" + +#define LINK_SPEC "\ +%{G*} \ +%{!mgas: \ + %{dy} %{dn}}" + +#define LIB_SPEC "\ + %{p:-lprof1} \ + %{!p:%{pg:-lprof1} \ + %{!pg:-L/usr/ccs/lib/ -lc /usr/ccs/lib/crtn.o%s}}" + +#define STARTFILE_SPEC "\ + %{pg:gcrt0.o%s} \ + %{!pg:%{p:mcrt0.o%s} \ + %{!p:/usr/ccs/lib/crt1.o /usr/ccs/lib/crti.o /usr/ccs/lib/values-Xt.o%s}}" + +/* Mips System V.4 doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + +#ifdef L_trampoline +#include <unistd.h> + +#define getpagesize() sysconf(_SC_PAGE_SIZE) +#endif /* L_trampoline */ + +/* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +#define OBJECT_FORMAT_ELF + +#define TARGET_DEFAULT MASK_ABICALLS +#define ABICALLS_ASM_OP ".option pic2" + +#define MACHINE_TYPE "SNI running SINIX 5.42" + +#define MIPS_DEFAULT_GVALUE 0 + +#define NM_FLAGS "-p" + +/* wir haben ein Problem, wenn in einem Assembler-File keine .text-section + erzeugt wird. Dann landen diese Pseudo-Labels in irgendeiner anderen + section, z.B. .reginfo. Das macht den ld sehr ungluecklich. */ + +#define ASM_IDENTIFY_GCC(mw_stream) \ + fprintf(mw_stream, "\t.ident \"gcc2_compiled.\"\n"); + +#define ASM_IDENTIFY_LANGUAGE(STREAM) + +#define ASM_LONG ".word\t" +#define ASM_GLOBAL ".rdata\n\t\t.globl\t" + +#include "mips/mips.h" + +/* We do not want to run mips-tfile! */ +#undef ASM_FINAL_SPEC + +#undef OBJECT_FORMAT_COFF + +/* We don't support debugging info for now. */ +#undef DBX_DEBUGGING_INFO +#undef SDB_DEBUGGING_INFO +#undef MIPS_DEBUGGING_INFO +#undef PREFERRED_DEBUGGING_TYPE + +#define DWARF2_UNWIND_INFO 0 diff --git a/contrib/gcc/config/mips/svr3-4.h b/contrib/gcc/config/mips/svr3-4.h new file mode 100644 index 000000000000..18303ac24ec1 --- /dev/null +++ b/contrib/gcc/config/mips/svr3-4.h @@ -0,0 +1,63 @@ +/* Definitions of target machine for GNU compiler. + MIPS RISC-OS System V version. + Copyright (C) 1991 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_SYSV + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SYSV \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SYSV \ +-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)" + +#define STANDARD_INCLUDE_DIR "/sysv/usr/include" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +-systype /sysv/" + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}" + +#define MACHINE_TYPE "RISC-OS System V Mips" + +/* Override defaults for finding the MIPS tools. */ +#define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/" + +/* Mips System V doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + +#ifdef L_trampoline +#include <sys/param.h> +#include <unistd.h> + +#ifdef _SC_PAGE_SIZE +#define getpagesize() sysconf(_SC_PAGE_SIZE) + +#else /* older rev of OS */ +#define getpagesize() (NBPC) +#endif /* !_SC_PAGE_SIZE */ +#endif /* L_trampoline */ + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS diff --git a/contrib/gcc/config/mips/svr3-5.h b/contrib/gcc/config/mips/svr3-5.h new file mode 100644 index 000000000000..495b389989a8 --- /dev/null +++ b/contrib/gcc/config/mips/svr3-5.h @@ -0,0 +1,89 @@ +/* Definitions of target machine for GNU compiler. + MIPS RISC-OS 5.0 System V version. + Copyright (C) 1991, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_SYSV + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SYSV \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SYSV \ +-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)" + +#define STANDARD_INCLUDE_DIR "/sysv/usr/include" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \ +-systype /sysv/ " + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}" + +#define MACHINE_TYPE "RISC-OS System V Mips" + +/* Override defaults for finding the MIPS tools. */ +#define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/" + +/* Mips System V doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + +#ifdef L_trampoline +#include <sys/param.h> +#include <unistd.h> + +/* In at least 5.0 and 5.01, there is no _SC_PAGE_SIZE macro, only a + _SC_PAGESIZE macro. */ +#ifdef _SC_PAGESIZE +#define _SC_PAGE_SIZE _SC_PAGESIZE +#endif + +#ifdef _SC_PAGE_SIZE +#define getpagesize() sysconf(_SC_PAGE_SIZE) + +#else /* older rev of OS */ +#define getpagesize() (NBPC) +#endif /* !_SC_PAGE_SIZE */ +#endif /* L_trampoline */ + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +#include "mips/mips.h" + +/* Some assemblers have a bug that causes backslash escaped chars in .ascii + to be misassembled, so we just completely avoid it. */ +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) diff --git a/contrib/gcc/config/mips/svr4-4.h b/contrib/gcc/config/mips/svr4-4.h new file mode 100644 index 000000000000..d1ba64de0290 --- /dev/null +++ b/contrib/gcc/config/mips/svr4-4.h @@ -0,0 +1,61 @@ +/* Definitions of target machine for GNU compiler. + MIPS RISC-OS System V.4 version. + Copyright (C) 1992, 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_SVR4 + +#define CPP_PREDEFINES "\ +-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \ +-Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)" + +#define STANDARD_INCLUDE_DIR "/svr4/usr/include" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +-systype /svr4/" + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}" + +#define MACHINE_TYPE "RISC-OS System V.4 Mips" + +/* Override defaults for finding the MIPS tools. */ +#define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/" + +/* Mips System V.4 doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + +#ifdef L_trampoline +#include <unistd.h> + +#define getpagesize() sysconf(_SC_PAGE_SIZE) +#endif /* L_trampoline */ + +/* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS diff --git a/contrib/gcc/config/mips/svr4-5.h b/contrib/gcc/config/mips/svr4-5.h new file mode 100644 index 000000000000..799e1cdf1e75 --- /dev/null +++ b/contrib/gcc/config/mips/svr4-5.h @@ -0,0 +1,92 @@ +/* Definitions of target machine for GNU compiler. + MIPS RISC-OS 5.0 System V.4 version. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define MIPS_SVR4 + +#define CPP_PREDEFINES \ +"-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 \ +-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \ +-D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32 \ +-Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)" + +#define STANDARD_INCLUDE_DIR "/svr4/usr/include" + +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \ +-systype /svr4/ " + +#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s" + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}\ + %{ansi:/svr4/usr/ccs/lib/values-Xc.o%s} \ + %{!ansi: \ + %{traditional:/svr4/usr/ccs/lib/values-Xt.o%s} \ + %{!traditional:/svr4/usr/ccs/lib/values-Xa.o%s}}" + +#define MACHINE_TYPE "RISC-OS System V.4 Mips" + +/* Override defaults for finding the MIPS tools. */ +#define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/" + +/* Mips System V.4 doesn't have a getpagesize() function needed by the + trampoline code, so use the POSIX sysconf function to get it. + This is only done when compiling the trampoline code. */ + +#ifdef L_trampoline +#include <unistd.h> + +/* In at least 5.0 and 5.01, there is no _SC_PAGE_SIZE macro, only a + _SC_PAGESIZE macro. */ +#ifdef _SC_PAGESIZE +#define _SC_PAGE_SIZE _SC_PAGESIZE +#endif + +#define getpagesize() sysconf(_SC_PAGE_SIZE) +#endif /* L_trampoline */ + +/* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +#include "mips/mips.h" + +/* Some assemblers have a bug that causes backslash escaped chars in .ascii + to be misassembled, so we just completely avoid it. */ +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) diff --git a/contrib/gcc/config/mips/svr4-t.h b/contrib/gcc/config/mips/svr4-t.h new file mode 100644 index 000000000000..b457aa5f07dc --- /dev/null +++ b/contrib/gcc/config/mips/svr4-t.h @@ -0,0 +1,29 @@ +/* Definitions of target machine for GNU compiler. Tandem S2 w/ NonStop UX. */ + +/* Use the default value for this. */ +#undef STANDARD_INCLUDE_DIR + +#undef MACHINE_TYPE +#define MACHINE_TYPE "TANDEM System V.4 Mips" + +/* Use the default values in mips.h. */ +#undef MD_STARTFILE_PREFIX +#undef MD_EXEC_PREFIX +#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/" +#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/" + +/* These are the same as the ones in svr4-5.h, except that references to + /svr4/ have been removed. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}\ + %{ansi:/usr/lib/values-Xc.o%s} \ + %{!ansi: \ + %{traditional:/usr/lib/values-Xt.o%s} \ + %{!traditional:/usr/lib/values-Xa.o%s}}" + +#undef LINK_SPEC +#define LINK_SPEC "\ +%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \ +%{bestGnum} %{shared} %{non_shared} \ +%{call_shared} %{no_archive} %{exact_version} \ +%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}" diff --git a/contrib/gcc/config/mips/t-bsd b/contrib/gcc/config/mips/t-bsd new file mode 100644 index 000000000000..f9c6fc840049 --- /dev/null +++ b/contrib/gcc/config/mips/t-bsd @@ -0,0 +1,12 @@ +# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR +# to point to the bsd43 include files. +SYSTEM_HEADER_DIR = /bsd43/usr/include + +# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab. +# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c +# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/t-bsd-gas b/contrib/gcc/config/mips/t-bsd-gas new file mode 100644 index 000000000000..bfa5a7ec38b3 --- /dev/null +++ b/contrib/gcc/config/mips/t-bsd-gas @@ -0,0 +1,8 @@ +# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR +# to point to the bsd43 include files. +SYSTEM_HEADER_DIR = /bsd43/usr/include + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/t-cross64 b/contrib/gcc/config/mips/t-cross64 new file mode 100644 index 000000000000..bfca95072f71 --- /dev/null +++ b/contrib/gcc/config/mips/t-cross64 @@ -0,0 +1,17 @@ +SYSTEM_HEADER_DIR = /usr/cross64/usr/include + +AR = /usr/cross64/usr/bin/ar + +# The rest of the file is identical to t-iris6. + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = + +MULTILIB_OPTIONS=mips1/mips2/mips3/mips4 +MULTILIB_DIRNAMES= +MULTILIB_MATCHES= + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/config/mips/t-ecoff b/contrib/gcc/config/mips/t-ecoff new file mode 100644 index 000000000000..8de03ffd758a --- /dev/null +++ b/contrib/gcc/config/mips/t-ecoff @@ -0,0 +1,92 @@ +CONFIG2_H = $(srcdir)/config/mips/ecoff.h + +# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab. +# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c +# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = + +# When building a cross compiler, put the mips16 support functions in +# libgcc1.a. +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = mips/mips16.S +LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \ + _m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \ + _m16fltsisf _m16fixsfsi \ + _m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \ + _m16extsfdf2 _m16trdfsf2 \ + _m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \ + _m16fltsidf _m16fixdfsi \ + _m16retsf _m16retdf \ + _m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \ + _m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \ + _m16stubsf9 _m16stubsf10 \ + _m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \ + _m16stubdf9 _m16stubdf10 + +# We must build libgcc2.a with -G 0, in case the user wants to link +# without the $gp register. +TARGET_LIBGCC2_CFLAGS = -G 0 + +# fp-bit and dp-bit are really part of libgcc1, but this will cause +# them to be built correctly, so... [taken from t-sparclite] +LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + echo '#ifdef __MIPSEL__' > dp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c + echo '#endif' >> dp-bit.c + echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c + cat $(srcdir)/config/fp-bit.c >> dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + echo '#ifdef __MIPSEL__' >> fp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c + echo '#endif' >> fp-bit.c + echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +# Build the libraries for both hard and soft floating point + +MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3 +MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3 +MULTILIB_MATCHES = msingle-float=m4650 + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +# Add additional dependencies to recompile selected modules whenever the +# tm.h file changes. The files compiled are: +# +# gcc.c (*_SPEC changes) +# toplev.c (new switches + assembly output changes) +# sdbout.c (debug format changes) +# dbxout.c (debug format changes) +# dwarfout.c (debug format changes) +# final.c (assembly output changes) +# varasm.c (assembly output changes) +# cse.c (cost functions) +# insn-output.c (possible ifdef changes in tm.h) +# regclass.c (fixed/call used register changes) +# cccp.c (new preprocessor macros, -v version #) +# explow.c (GO_IF_LEGITIMATE_ADDRESS) +# recog.c (GO_IF_LEGITIMATE_ADDRESS) +# reload.c (GO_IF_LEGITIMATE_ADDRESS) + +gcc.o: $(CONFIG2_H) +toplev.o: $(CONFIG2_H) +sdbout.o: $(CONFIG2_H) +dbxout.o: $(CONFIG2_H) +dwarfout.o: $(CONFIG2_H) +final.o: $(CONFIG2_H) +varasm.o: $(CONFIG2_H) +cse.o: $(CONFIG2_H) +insn-output.o: $(CONFIG2_H) +regclass.o: $(CONFIG2_H) +cccp.o: $(CONFIG2_H) +explow.o: $(CONFIG2_H) +recog.o: $(CONFIG2_H) +reload.o: $(CONFIG2_H) diff --git a/contrib/gcc/config/mips/t-elf b/contrib/gcc/config/mips/t-elf new file mode 100644 index 000000000000..dd01b7fd4a71 --- /dev/null +++ b/contrib/gcc/config/mips/t-elf @@ -0,0 +1,96 @@ +CONFIG2_H = $(srcdir)/config/mips/ecoff.h + +# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab. +# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c +# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = + +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o +# Don't let CTOR_LIST end up in sdata section. +CRTSTUFF_T_CFLAGS = -G 0 + +# When building a cross compiler, put the mips16 support functions in +# libgcc1.a. +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = mips/mips16.S +LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \ + _m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \ + _m16fltsisf _m16fixsfsi \ + _m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \ + _m16extsfdf2 _m16trdfsf2 \ + _m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \ + _m16fltsidf _m16fixdfsi \ + _m16retsf _m16retdf \ + _m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \ + _m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \ + _m16stubsf9 _m16stubsf10 \ + _m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \ + _m16stubdf9 _m16stubdf10 + +# We must build libgcc2.a with -G 0, in case the user wants to link +# without the $gp register. +TARGET_LIBGCC2_CFLAGS = -G 0 + +# fp-bit and dp-bit are really part of libgcc1, but this will cause +# them to be built correctly, so... [taken from t-sparclite] +LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + echo '#ifdef __MIPSEL__' > dp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c + echo '#endif' >> dp-bit.c + echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c + cat $(srcdir)/config/fp-bit.c >> dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + echo '#ifdef __MIPSEL__' >> fp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c + echo '#endif' >> fp-bit.c + echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +# Build the libraries for both hard and soft floating point + +MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3 +MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3 +MULTILIB_MATCHES = msingle-float=m4650 + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +# Add additional dependencies to recompile selected modules whenever the +# tm.h file changes. The files compiled are: +# +# gcc.c (*_SPEC changes) +# toplev.c (new switches + assembly output changes) +# sdbout.c (debug format changes) +# dbxout.c (debug format changes) +# dwarfout.c (debug format changes) +# final.c (assembly output changes) +# varasm.c (assembly output changes) +# cse.c (cost functions) +# insn-output.c (possible ifdef changes in tm.h) +# regclass.c (fixed/call used register changes) +# cccp.c (new preprocessor macros, -v version #) +# explow.c (GO_IF_LEGITIMATE_ADDRESS) +# recog.c (GO_IF_LEGITIMATE_ADDRESS) +# reload.c (GO_IF_LEGITIMATE_ADDRESS) + +gcc.o: $(CONFIG2_H) +toplev.o: $(CONFIG2_H) +sdbout.o: $(CONFIG2_H) +dbxout.o: $(CONFIG2_H) +dwarfout.o: $(CONFIG2_H) +final.o: $(CONFIG2_H) +varasm.o: $(CONFIG2_H) +cse.o: $(CONFIG2_H) +insn-output.o: $(CONFIG2_H) +regclass.o: $(CONFIG2_H) +cccp.o: $(CONFIG2_H) +explow.o: $(CONFIG2_H) +recog.o: $(CONFIG2_H) +reload.o: $(CONFIG2_H) diff --git a/contrib/gcc/config/mips/t-iris6 b/contrib/gcc/config/mips/t-iris6 new file mode 100644 index 000000000000..85a63f06e2e7 --- /dev/null +++ b/contrib/gcc/config/mips/t-iris6 @@ -0,0 +1,20 @@ +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = + +# ??? If no mabi=X option given, but a mipsX option is, then should deal +# with that. +# ??? mabi=32 is deliberately left off the list because it doesn't work yet. +MULTILIB_OPTIONS=mabi=n32/mabi=64 +MULTILIB_DIRNAMES= +MULTILIB_MATCHES= + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +# For svr4 we build crtbegin.o and crtend.o which serve to add begin and +# end labels to the .ctors and .dtors section when we link using gcc. + +EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o +CRTSTUFF_T_CFLAGS=-g1 diff --git a/contrib/gcc/config/mips/t-mips b/contrib/gcc/config/mips/t-mips new file mode 100644 index 000000000000..e57a55af5de9 --- /dev/null +++ b/contrib/gcc/config/mips/t-mips @@ -0,0 +1,8 @@ +# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab. +# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c +# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/t-mips-gas b/contrib/gcc/config/mips/t-mips-gas new file mode 100644 index 000000000000..94f1c442b68a --- /dev/null +++ b/contrib/gcc/config/mips/t-mips-gas @@ -0,0 +1,4 @@ +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/t-osfrose b/contrib/gcc/config/mips/t-osfrose new file mode 100644 index 000000000000..e57a55af5de9 --- /dev/null +++ b/contrib/gcc/config/mips/t-osfrose @@ -0,0 +1,8 @@ +# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab. +# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c +# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/t-r3900 b/contrib/gcc/config/mips/t-r3900 new file mode 100644 index 000000000000..055143ff05c7 --- /dev/null +++ b/contrib/gcc/config/mips/t-r3900 @@ -0,0 +1,95 @@ +CONFIG2_H = $(srcdir)/config/mips/ecoff.h + +# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab. +# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c +# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = + +# When building a cross compiler, put the mips16 support functions in +# libgcc1.a. +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = mips/mips16.S +LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \ + _m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \ + _m16fltsisf _m16fixsfsi \ + _m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \ + _m16extsfdf2 _m16trdfsf2 \ + _m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \ + _m16fltsidf _m16fixdfsi \ + _m16retsf _m16retdf \ + _m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \ + _m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \ + _m16stubsf9 _m16stubsf10 \ + _m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \ + _m16stubdf9 _m16stubdf10 + +# We must build libgcc2.a with -G 0, in case the user wants to link +# without the $gp register. +TARGET_LIBGCC2_CFLAGS = -G 0 + +# fp-bit and dp-bit are really part of libgcc1, but this will cause +# them to be built correctly, so... [taken from t-sparclite] +LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + echo '#ifdef __MIPSEL__' > dp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c + echo '#endif' >> dp-bit.c + echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c + cat $(srcdir)/config/fp-bit.c >> dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + echo '#ifdef __MIPSEL__' >> fp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c + echo '#endif' >> fp-bit.c + echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o +# Don't let CTOR_LIST end up in sdata section. +CRTSTUFF_T_CFLAGS = -G 0 + +# Build the libraries for both hard and soft floating point + +MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB +MULTILIB_DIRNAMES = soft-float single el eb + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +# Add additional dependencies to recompile selected modules whenever the +# tm.h file changes. The files compiled are: +# +# gcc.c (*_SPEC changes) +# toplev.c (new switches + assembly output changes) +# sdbout.c (debug format changes) +# dbxout.c (debug format changes) +# dwarfout.c (debug format changes) +# final.c (assembly output changes) +# varasm.c (assembly output changes) +# cse.c (cost functions) +# insn-output.c (possible ifdef changes in tm.h) +# regclass.c (fixed/call used register changes) +# cccp.c (new preprocessor macros, -v version #) +# explow.c (GO_IF_LEGITIMATE_ADDRESS) +# recog.c (GO_IF_LEGITIMATE_ADDRESS) +# reload.c (GO_IF_LEGITIMATE_ADDRESS) + +gcc.o: $(CONFIG2_H) +toplev.o: $(CONFIG2_H) +sdbout.o: $(CONFIG2_H) +dbxout.o: $(CONFIG2_H) +dwarfout.o: $(CONFIG2_H) +final.o: $(CONFIG2_H) +varasm.o: $(CONFIG2_H) +cse.o: $(CONFIG2_H) +insn-output.o: $(CONFIG2_H) +regclass.o: $(CONFIG2_H) +cccp.o: $(CONFIG2_H) +explow.o: $(CONFIG2_H) +recog.o: $(CONFIG2_H) +reload.o: $(CONFIG2_H) diff --git a/contrib/gcc/config/mips/t-svr3 b/contrib/gcc/config/mips/t-svr3 new file mode 100644 index 000000000000..273c710882ac --- /dev/null +++ b/contrib/gcc/config/mips/t-svr3 @@ -0,0 +1,12 @@ +# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR +# to point to the svr3 include files. +SYSTEM_HEADER_DIR = /sysv/usr/include + +# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab. +# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c +# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/t-svr3-gas b/contrib/gcc/config/mips/t-svr3-gas new file mode 100644 index 000000000000..99238f25928d --- /dev/null +++ b/contrib/gcc/config/mips/t-svr3-gas @@ -0,0 +1,8 @@ +# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR +# to point to the svr3 include files. +SYSTEM_HEADER_DIR = /sysv/usr/include + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/t-svr4 b/contrib/gcc/config/mips/t-svr4 new file mode 100644 index 000000000000..88029b92a552 --- /dev/null +++ b/contrib/gcc/config/mips/t-svr4 @@ -0,0 +1,12 @@ +# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR +# to point to the svr4 include files. +SYSTEM_HEADER_DIR = /svr4/usr/include + +# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab. +# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c +# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/t-svr4-gas b/contrib/gcc/config/mips/t-svr4-gas new file mode 100644 index 000000000000..845b091ef383 --- /dev/null +++ b/contrib/gcc/config/mips/t-svr4-gas @@ -0,0 +1,8 @@ +# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR +# to point to the svr4 include files. +SYSTEM_HEADER_DIR = /svr4/usr/include + +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/mips/vxworks.h b/contrib/gcc/config/mips/vxworks.h new file mode 100644 index 000000000000..0856c37343a7 --- /dev/null +++ b/contrib/gcc/config/mips/vxworks.h @@ -0,0 +1,50 @@ +/* Copyright (C) 1999 Free Software Foundation, Inc. */ + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Undefine the following which were defined in elf.h. Thise will cause the mips-vxworks + port to continue to use collect2 for constructors/destructors. This entire file may + be removed when .ctor/.dtor section support is desired. */ + +#undef CTORS_SECTION_ASM_OP +#undef DTORS_SECTION_ASM_OP + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_sdata, in_rdata + +#undef INVOKE__main +#undef NAME__MAIN +#undef SYMBOL__MAIN + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \ + SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) + +#undef ASM_OUTPUT_CONSTRUCTOR +#undef ASM_OUTPUT_DESTRUCTOR + +#undef CTOR_LIST_BEGIN +#undef CTOR_LIST_END +#undef DTOR_LIST_BEGIN +#undef DTOR_LIST_END + +#undef STARTFILE_SPEC +#undef ENDFILE_SPEC + +/* End of undefines to turn off .ctor/.dtor section support */ diff --git a/contrib/gcc/config/mips/x-dec-osf1 b/contrib/gcc/config/mips/x-dec-osf1 new file mode 100644 index 000000000000..6e46f0eafd50 --- /dev/null +++ b/contrib/gcc/config/mips/x-dec-osf1 @@ -0,0 +1,17 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). We need to pass +# the -Wf,-XNg1500 option so the compiler can compile the +# G++ file cp-parse.c. Otherwise it complains about +# too many case statements. -Olimit is so the user +# can use -O2. Down with fixed size tables! + +CC = $(OLDCC) +OPT = -O1 +OLDCC = cc -Wf,-XNg1500 -Olimit 3000 $(OPT) + +# The bison output files are machine-indep, +# so different flags for a particular machine are not useful. +#BISONFLAGS = -l diff --git a/contrib/gcc/config/mips/x-iris b/contrib/gcc/config/mips/x-iris new file mode 100644 index 000000000000..cf135d172bdc --- /dev/null +++ b/contrib/gcc/config/mips/x-iris @@ -0,0 +1,31 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). We need to pass +# the -Wf,-XNg1500 option so the compiler can compile the +# G++ file cp-parse.c. Otherwise it complains about +# too many case statements. -Olimit is so the user +# can use -O2. Down with fixed size tables! +# The -cckr is to turn off strict ANSI checking. + +# These definitions are commented out because they cause trouble with +# autoconf. It is believed that they aren't needed anymore. +#CC = $(OLDCC) +#OPT = -O1 +#OLDCC = cc -Wf,-XNh2000,-XNg1500 -Olimit 3000 -cckr $(OPT) + +# The bison output files are machine-indep, +# so different flags for a particular machine are not useful. +#BISONFLAGS = -l + +# -lmld is so we can link collect2 running native. +# -lmalloc is supposed to be faster than the normal malloc +CLIB = -lmld -lmalloc + +# Show we need to use the C version of ALLOCA +ALLOCA = alloca.o + +# Find all of the declarations from the header files +FIXPROTO_DEFINES= -D__EXTENSIONS__ -D_SGI_SOURCE -D_LANGUAGE_C_PLUS_PLUS + diff --git a/contrib/gcc/config/mips/x-iris3 b/contrib/gcc/config/mips/x-iris3 new file mode 100644 index 000000000000..2743ab743d93 --- /dev/null +++ b/contrib/gcc/config/mips/x-iris3 @@ -0,0 +1,30 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). We need to pass +# the -Wf,-XNg1500 option so the compiler can compile the +# G++ file cp-parse.c. Otherwise it complains about +# too many case statements. -Olimit is so the user +# can use -O2. Down with fixed size tables! + +# In at least one version of Irix, v3.3.2, the compiler does not accept +# the -cckr option, so, lets try without it for all versions of Irix 3.x. +# The -cckr is to turn off strict ANSI checking. + +# These definitions are commented out because they cause trouble with +# autoconf. It is believed that they aren't needed anymore. +#CC = $(OLDCC) +#OPT = -O1 +#OLDCC = cc -Wf,-XNh2000,-XNg1500 -Olimit 3000 $(OPT) + +# The bison output files are machine-indep, +# so different flags for a particular machine are not useful. +#BISONFLAGS = -l + +# -lmld is so we can link collect2 running native. +# -lmalloc is supposed to be faster than the normal malloc +CLIB = -lmld -lmalloc + +# Show we need to use the C version of ALLOCA +ALLOCA = alloca.o diff --git a/contrib/gcc/config/mips/x-iris6 b/contrib/gcc/config/mips/x-iris6 new file mode 100644 index 000000000000..88c41f4dfe45 --- /dev/null +++ b/contrib/gcc/config/mips/x-iris6 @@ -0,0 +1,11 @@ +# We force the use of the O32 ABI for two reasons. +# 1) For consistency, because some versions of Irix 6 default to the O32 ABI +# and some versions default to the N64 ABI. +# 2) To avoid SGI compiler bugs. The v6.x and v7.0 compilers from SGI have +# bugs that cause gcc to be miscompiled when the N32 or N64 ABIs are used. +# The O32 ABI is known to be OK. +CC = $(OLDCC) +OLDCC = cc -32 + +# Find all of the declarations from the header files +FIXPROTO_DEFINES= -D__EXTENSIONS__ -D_SGI_SOURCE -D_LANGUAGE_C_PLUS_PLUS diff --git a/contrib/gcc/config/mips/x-mips b/contrib/gcc/config/mips/x-mips new file mode 100644 index 000000000000..7b407431a810 --- /dev/null +++ b/contrib/gcc/config/mips/x-mips @@ -0,0 +1,20 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). We need to pass +# the -Wf,-XNg1500 option so the compiler can compile the +# G++ file cp-parse.c. Otherwise it complains about +# too many case statements. The -Olimit is so the user +# can use -O2. Down with fixed size tables! + +CC = $(OLDCC) +OPT = -O1 +OLDCC = cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT) + +# The bison output files are machine-indep, +# so different flags for a particular machine are not useful. +#BISONFLAGS = -l + +# This is so we can link collect2 running native. +CLIB = -lmld diff --git a/contrib/gcc/config/mips/x-netbsd b/contrib/gcc/config/mips/x-netbsd new file mode 100644 index 000000000000..49a89f35d1bd --- /dev/null +++ b/contrib/gcc/config/mips/x-netbsd @@ -0,0 +1,17 @@ +# Don't run fixproto +STMP_FIXPROTO = + +# We don't need GCC's own include files. +USER_H = $(srcdir)/ginclude/stdarg.h $(srcdir)/ginclude/varargs.h \ + $(srcdir)/ginclude/va-mips.h $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS) + +XLIMITS_H = + +# We don't need even the files GCC insists we need. +GENINCLUDES = Makefile.in + +# A lot of stuff needs to go elsewhere. +includedir=$(exec_prefix)/include +infodir=$(exec_prefix)/share/info +tooldir=$(libdir)/cross/$(target) +mandir=$(exec_prefix)/share/man/man1 diff --git a/contrib/gcc/config/mips/x-nws3250v4 b/contrib/gcc/config/mips/x-nws3250v4 new file mode 100644 index 000000000000..4f5cf26eede7 --- /dev/null +++ b/contrib/gcc/config/mips/x-nws3250v4 @@ -0,0 +1,19 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). We need to pass +# the -Wf,-XNg1500 option so the compiler can compile the +# G++ file cp-parse.c. Otherwise it complains about +# too many case statements. Down with fixed size tables! + +CC = $(OLDCC) +OLDCC = cc -Wf,-XNg1500 +CCLIBFLAGS = -G 0 + +ALLOCA = alloca.o + +# The bison output files are machine-indep, +# so different flags for a particular machine are not useful. +#BISONFLAGS = -l + diff --git a/contrib/gcc/config/mips/x-osfrose b/contrib/gcc/config/mips/x-osfrose new file mode 100644 index 000000000000..825276c25c71 --- /dev/null +++ b/contrib/gcc/config/mips/x-osfrose @@ -0,0 +1,32 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). + +BUILD = +CC = $(OLDCC) +CLIB = -lld +X_CFLAGS = $(DEB_OPT) $(MSTATS) $(SHLIB) $(X_DEFINES) +X_CFLAGS_NODEBUG = $(NO_DEBUG) $(MSTATS) $(OPT) $(PROFILE) $(SHLIB) $(X_DEFINES) $(XCFLAGS) +CCLIBFLAGS = -O -pic-extern +CPP_ABORT = # -Dabort=fancy_abort +CPPFLAGS = $(CPP_ABORT) $(SYSTEM_INCLUDES) +DEB_OPT = $(OPT) $(DEBUG) $(PROFILE) +DEBUG = +DEBUG_COLLECT = # -DDEBUG +CCLIBFLAGS = -O -DNO_HALF_PIC +GCC_CFLAGS = $(INTERNAL_CFLAGS) $(X_CFLAGS) $(T_CFLAGS) $(CFLAGS) -B./ -DPOSIX -DNO_HALF_PIC +LIBGCC2_CFLAGS = -O2 $(GCC_CFLAGS) -g1 -pic-extern +LDFLAGS = +MSTATS = # -mstats +OLDCC = /usr/ccs/gcc/gcc +OPT = -O2 +PROFILE = +SHLIB = -pic-none +SYSTEM_INCLUDES = # -I${BUILD}/usr/include +X_DEFINES = -Dvfork=fork + +libdir = /usr/ccs +mandir = /usr/ccs/gcc/$(target)/$(version) +bindir = /usr/ccs/gcc/$(target)/$(version) diff --git a/contrib/gcc/config/mips/x-sni-svr4 b/contrib/gcc/config/mips/x-sni-svr4 new file mode 100644 index 000000000000..f986f88162f4 --- /dev/null +++ b/contrib/gcc/config/mips/x-sni-svr4 @@ -0,0 +1,18 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). +# -Olimit is so the user can use -O2. Down with fixed +# size tables! + +CC = $(OLDCC) +OPT = +OLDCC = cc -Olimit 3000 $(OPT) + +X_CFLAGS = -DNO_SYS_SIGLIST + +# Show we need to use the C version of ALLOCA +# The SVR3 configurations have it, but the SVR4 configurations don't. +# For now, just try using it for all SVR* configurations. +ALLOCA = alloca.o diff --git a/contrib/gcc/config/mips/x-sony b/contrib/gcc/config/mips/x-sony new file mode 100644 index 000000000000..c64593d7d7d3 --- /dev/null +++ b/contrib/gcc/config/mips/x-sony @@ -0,0 +1,18 @@ +# Make internal tables bigger. +OLDCC=cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT) + +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). We need to pass +# the -Wf,-XNg1500 option so the compiler can compile the +# G++ file cp-parse.c. Otherwise it complains about +# too many case statements. The -Olimit is so the user +# can use -O2. Down with fixed size tables! + +CC = $(OLDCC) +OPT = -O1 + +# This is so we can link collect2 running native. +CLIB = -lmld diff --git a/contrib/gcc/config/mips/x-sysv b/contrib/gcc/config/mips/x-sysv new file mode 100644 index 000000000000..2c173b159a56 --- /dev/null +++ b/contrib/gcc/config/mips/x-sysv @@ -0,0 +1,26 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). We need to pass +# the -Wf,-XNg1500 option so the compiler can compile the +# G++ file cp-parse.c. Otherwise it complains about +# too many case statements. -Olimit is so the user +# can use -O2. Down with fixed size tables! + +CC = $(OLDCC) +OPT = -O1 +OLDCC = cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT) + +# The bison output files are machine-indep, +# so different flags for a particular machine are not useful. +#BISONFLAGS = -l + +# This enables collect2 to link. +# Some systems use version 2.11 of the compilers. Some use version 3.11. +CLIB= -L/usr/lib/cmplrs/cc2.11 -L/usr/lib/cmplrs/cc3.11 -lmld + +# Show we need to use the C version of ALLOCA +# The SVR3 configurations have it, but the SVR4 configurations don't. +# For now, just try using it for all SVR* configurations. +ALLOCA = alloca.o diff --git a/contrib/gcc/config/mips/xm-iris3.h b/contrib/gcc/config/mips/xm-iris3.h new file mode 100644 index 000000000000..448b7ac80bb3 --- /dev/null +++ b/contrib/gcc/config/mips/xm-iris3.h @@ -0,0 +1,3 @@ +#include "mips/xm-mips.h" + +#define USG diff --git a/contrib/gcc/config/mips/xm-iris4.h b/contrib/gcc/config/mips/xm-iris4.h new file mode 100644 index 000000000000..c01d3f48a789 --- /dev/null +++ b/contrib/gcc/config/mips/xm-iris4.h @@ -0,0 +1,13 @@ +#include "mips/xm-mips.h" + +#define USG + +#if 0 +#ifdef __GNUC__ +/* The normal irix compiler requires alloca.h or alloca doesn't work. + However, the IRIX compiler doesn't allow alloca to be stored in + something like ptr->field = alloca(), so we just use the normal + C alloca. */ +#include <alloca.h> +#endif +#endif diff --git a/contrib/gcc/config/mips/xm-iris5.h b/contrib/gcc/config/mips/xm-iris5.h new file mode 100644 index 000000000000..616055f27f72 --- /dev/null +++ b/contrib/gcc/config/mips/xm-iris5.h @@ -0,0 +1,9 @@ +#include "mips/xm-mips.h" + +/* On SGI IRIX 5.3, inttypes.h clashes with sys/types.h, but the clash + (when compiled with GCC) is a warning, so configure.in thinks it's OK + to use it. Work around this problem. */ + +#ifdef HAVE_INTTYPES_H +#undef HAVE_INTTYPES_H +#endif diff --git a/contrib/gcc/config/mips/xm-iris6.h b/contrib/gcc/config/mips/xm-iris6.h new file mode 100644 index 000000000000..4d429c72edcc --- /dev/null +++ b/contrib/gcc/config/mips/xm-iris6.h @@ -0,0 +1,17 @@ +#define MIPS_OVERRIDE_ALLOCA +#ifndef __GNUC__ +#include <alloca.h> +#else +extern void *alloca (); +#endif + +#include "mips/xm-mips.h" + +#define USG + +#undef HOST_BITS_PER_LONG +#define HOST_BITS_PER_LONG _MIPS_SZLONG + +#ifndef inhibit_libc +#include "string.h" +#endif diff --git a/contrib/gcc/config/mips/xm-mips.h b/contrib/gcc/config/mips/xm-mips.h new file mode 100644 index 000000000000..ad49d7f48378 --- /dev/null +++ b/contrib/gcc/config/mips/xm-mips.h @@ -0,0 +1,76 @@ +/* Configuration for GNU C-compiler for MIPS Rx000 family + Copyright (C) 1989, 1990, 1991, 1993, 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +#if !defined(MIPSEL) && !defined(__MIPSEL__) +#define HOST_WORDS_BIG_ENDIAN +#endif + +/* Enable host-conditionals for MIPS machines. */ +#ifndef MIPS +#define MIPS 1 +#endif + +/* A code distinguishing the floating point format of the host + machine. There are three defined values: IEEE_FLOAT_FORMAT, + VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */ + +#define HOST_FLOAT_FORMAT IEEE_FLOAT_FORMAT + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ +#include "tm.h" + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +#ifndef __GNUC__ +/* The MIPS compiler gets it wrong, and treats enumerated bitfields + as signed quantities, making it impossible to use an 8-bit enum + for compiling GNU C++. */ +#define ONLY_INT_FIELDS 1 +#endif + +#ifndef MIPS_OVERRIDE_ALLOCA +#ifndef __GNUC__ +#define USE_C_ALLOCA + +#ifdef __STDC__ +extern void * alloca (); +#else +extern char * alloca (); +#endif + +/* for the emacs version of alloca */ +#define STACK_DIRECTION -1 +#endif +#endif /* not MIPS_OVERRIDE_ALLOCA */ diff --git a/contrib/gcc/config/mips/xm-netbsd.h b/contrib/gcc/config/mips/xm-netbsd.h new file mode 100644 index 000000000000..b9d3c709d9d8 --- /dev/null +++ b/contrib/gcc/config/mips/xm-netbsd.h @@ -0,0 +1,2 @@ +#include "mips/xm-mips.h" +#include "config/xm-netbsd.h" diff --git a/contrib/gcc/config/mips/xm-news.h b/contrib/gcc/config/mips/xm-news.h new file mode 100644 index 000000000000..e3eda9db1410 --- /dev/null +++ b/contrib/gcc/config/mips/xm-news.h @@ -0,0 +1,8 @@ +/* This file is for the Sony Mips News running "NewsOS Version 5", + which is really System V. */ +#include "mips/xm-sysv.h" + +/* Sony has a funny name for this symbol. */ +#define sys_siglist _sys_siglist +#undef SYS_SIGLIST_DECLARED +#define SYS_SIGLIST_DECLARED diff --git a/contrib/gcc/config/mips/xm-nws3250v4.h b/contrib/gcc/config/mips/xm-nws3250v4.h new file mode 100644 index 000000000000..34ab631acb48 --- /dev/null +++ b/contrib/gcc/config/mips/xm-nws3250v4.h @@ -0,0 +1,9 @@ +#define USG + +#include "xm-mips.h" + +/* If compiling with mips compiler, we are probably using alloca.c, + so help it work right. */ +#ifndef __GNUC__ +#define USE_C_ALLOCA +#endif diff --git a/contrib/gcc/config/mips/xm-sysv.h b/contrib/gcc/config/mips/xm-sysv.h new file mode 100644 index 000000000000..05a8d6c1154e --- /dev/null +++ b/contrib/gcc/config/mips/xm-sysv.h @@ -0,0 +1,30 @@ +/* Configuration for GNU C-compiler for UMIPS operating system + Copyright (C) 1989, 1990, 1991, 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* + * Notes for compiling gcc on umips (v3.0) + * - change the -g in the CFLAGS to a -g3 or take it out all together. + * - do not define DBX_DEBUGGING_INFO in tm.h, it doesn't exist (unless + * you get one from a bsd system) + */ + +#define USG + +#include "mips/xm-mips.h" diff --git a/contrib/gcc/config/mips/xm-sysv4.h b/contrib/gcc/config/mips/xm-sysv4.h new file mode 100644 index 000000000000..b79664bf1fba --- /dev/null +++ b/contrib/gcc/config/mips/xm-sysv4.h @@ -0,0 +1,7 @@ +#include "mips/xm-sysv.h" + +/* SVR4 provides no sys_siglist, + but does offer the same data under another name. */ +#define sys_siglist _sys_siglist +#undef SYS_SIGLIST_DECLARED +#define SYS_SIGLIST_DECLARED diff --git a/contrib/gcc/config/sparc/aout.h b/contrib/gcc/config/sparc/aout.h new file mode 100644 index 000000000000..478d710f82fd --- /dev/null +++ b/contrib/gcc/config/sparc/aout.h @@ -0,0 +1,26 @@ +/* Definitions of target machine for GNU compiler, for SPARC using a.out. + Copyright (C) 1994, 1996 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/sparc.h" /* SPARC definitions */ +#include "aoutos.h" /* A.out definitions */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -Acpu(sparc) -Amachine(sparc)" diff --git a/contrib/gcc/config/sparc/bsd.h b/contrib/gcc/config/sparc/bsd.h new file mode 100644 index 000000000000..761abe2671b8 --- /dev/null +++ b/contrib/gcc/config/sparc/bsd.h @@ -0,0 +1,7 @@ +#include "sparc/sparc.h" + +#undef LIB_SPEC +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:gcrt0.o%s}%{!p:crt0.o%s}}" diff --git a/contrib/gcc/config/sparc/elf.h b/contrib/gcc/config/sparc/elf.h new file mode 100644 index 000000000000..635238f5b1f2 --- /dev/null +++ b/contrib/gcc/config/sparc/elf.h @@ -0,0 +1,58 @@ +/* Definitions of target machine for GNU compiler, + for SPARC running in an embedded environment using the ELF file format. + Copyright (C) 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sol2.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -D__elf__ -Acpu(sparc) -Amachine(sparc)" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend.o%s crtn.o%s" + +/* Use the default. */ +#undef LINK_SPEC + +/* Don't set the target flags, this is done by the linker script */ +#undef LIB_SPEC +#define LIB_SPEC "" + +/* FIXME: until fixed */ +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 64 + +/* This solaris2 define does not apply. */ +#undef STDC_0_IN_SYSTEM_HEADERS + +/* We don't want to use the Solaris2 specific long long int conversion + routines. */ +#undef INIT_SUBTARGET_OPTABS +#define INIT_SUBTARGET_OPTABS + +/* ??? We haven't added Solaris2 equivalent 64 bit library routines to + lb1sp*.asm, so we need to avoid using them. */ +#undef MULDI3_LIBCALL +#undef DIVDI3_LIBCALL +#undef UDIVDI3_LIBCALL +#undef MODDI3_LIBCALL +#undef UMODDI3_LIBCALL diff --git a/contrib/gcc/config/sparc/gmon-sol2.c b/contrib/gcc/config/sparc/gmon-sol2.c new file mode 100644 index 000000000000..a6abcabcc51f --- /dev/null +++ b/contrib/gcc/config/sparc/gmon-sol2.c @@ -0,0 +1,425 @@ +/*- + * Copyright (c) 1991 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* Mangled into a form that works on Sparc Solaris 2 by Mark Eichin + * for Cygnus Support, July 1992. + */ + +#include "config.h" +#include "system.h" + +#if 0 +#include "sparc/gmon.h" +#else +struct phdr { + char *lpc; + char *hpc; + int ncnt; +}; +#define HISTFRACTION 2 +#define HISTCOUNTER unsigned short +#define HASHFRACTION 1 +#define ARCDENSITY 2 +#define MINARCS 50 +struct tostruct { + char *selfpc; + long count; + unsigned short link; +}; +struct rawarc { + unsigned long raw_frompc; + unsigned long raw_selfpc; + long raw_count; +}; +#define ROUNDDOWN(x,y) (((x)/(y))*(y)) +#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) + +#endif + +/* extern mcount() asm ("mcount"); */ +/*extern*/ char *minbrk /* asm ("minbrk") */; + + /* + * froms is actually a bunch of unsigned shorts indexing tos + */ +static int profiling = 3; +static unsigned short *froms; +static struct tostruct *tos = 0; +static long tolimit = 0; +static char *s_lowpc = 0; +static char *s_highpc = 0; +static unsigned long s_textsize = 0; + +static int ssiz; +static char *sbuf; +static int s_scale; + /* see profil(2) where this is describe (incorrectly) */ +#define SCALE_1_TO_1 0x10000L + +#define MSG "No space for profiling buffer(s)\n" + +static void moncontrol PROTO ((int)); +extern void monstartup PROTO ((char *, char *)); +extern void _mcleanup PROTO ((void)); + +void monstartup(lowpc, highpc) + char *lowpc; + char *highpc; +{ + int monsize; + char *buffer; + register int o; + + /* + * round lowpc and highpc to multiples of the density we're using + * so the rest of the scaling (here and in gprof) stays in ints. + */ + lowpc = (char *) + ROUNDDOWN((unsigned)lowpc, HISTFRACTION*sizeof(HISTCOUNTER)); + s_lowpc = lowpc; + highpc = (char *) + ROUNDUP((unsigned)highpc, HISTFRACTION*sizeof(HISTCOUNTER)); + s_highpc = highpc; + s_textsize = highpc - lowpc; + monsize = (s_textsize / HISTFRACTION) + sizeof(struct phdr); + buffer = sbrk( monsize ); + if ( buffer == (char *) -1 ) { + write( 2 , MSG , sizeof(MSG) ); + return; + } + froms = (unsigned short *) sbrk( s_textsize / HASHFRACTION ); + if ( froms == (unsigned short *) -1 ) { + write( 2 , MSG , sizeof(MSG) ); + froms = 0; + return; + } + tolimit = s_textsize * ARCDENSITY / 100; + if ( tolimit < MINARCS ) { + tolimit = MINARCS; + } else if ( tolimit > 65534 ) { + tolimit = 65534; + } + tos = (struct tostruct *) sbrk( tolimit * sizeof( struct tostruct ) ); + if ( tos == (struct tostruct *) -1 ) { + write( 2 , MSG , sizeof(MSG) ); + froms = 0; + tos = 0; + return; + } + minbrk = sbrk(0); + tos[0].link = 0; + sbuf = buffer; + ssiz = monsize; + ( (struct phdr *) buffer ) -> lpc = lowpc; + ( (struct phdr *) buffer ) -> hpc = highpc; + ( (struct phdr *) buffer ) -> ncnt = ssiz; + monsize -= sizeof(struct phdr); + if ( monsize <= 0 ) + return; + o = highpc - lowpc; + if( monsize < o ) +#ifndef hp300 + s_scale = ( (float) monsize / o ) * SCALE_1_TO_1; +#else /* avoid floating point */ + { + int quot = o / monsize; + + if (quot >= 0x10000) + s_scale = 1; + else if (quot >= 0x100) + s_scale = 0x10000 / quot; + else if (o >= 0x800000) + s_scale = 0x1000000 / (o / (monsize >> 8)); + else + s_scale = 0x1000000 / ((o << 8) / monsize); + } +#endif + else + s_scale = SCALE_1_TO_1; + moncontrol(1); +} + +void +_mcleanup() +{ + int fd; + int fromindex; + int endfrom; + char *frompc; + int toindex; + struct rawarc rawarc; + char *profdir; + const char *proffile; + char *progname; + char buf[PATH_MAX]; + extern char **___Argv; + + moncontrol(0); + + if ((profdir = getenv("PROFDIR")) != NULL) { + /* If PROFDIR contains a null value, no profiling output is produced */ + if (*profdir == '\0') { + return; + } + + progname=strrchr(___Argv[0], '/'); + if (progname == NULL) + progname=___Argv[0]; + else + progname++; + + sprintf(buf, "%s/%ld.%s", profdir, getpid(), progname); + proffile = buf; + } else { + proffile = "gmon.out"; + } + + fd = creat( proffile, 0666 ); + if ( fd < 0 ) { + perror( proffile ); + return; + } +# ifdef DEBUG + fprintf( stderr , "[mcleanup] sbuf 0x%x ssiz %d\n" , sbuf , ssiz ); +# endif DEBUG + write( fd , sbuf , ssiz ); + endfrom = s_textsize / (HASHFRACTION * sizeof(*froms)); + for ( fromindex = 0 ; fromindex < endfrom ; fromindex++ ) { + if ( froms[fromindex] == 0 ) { + continue; + } + frompc = s_lowpc + (fromindex * HASHFRACTION * sizeof(*froms)); + for (toindex=froms[fromindex]; toindex!=0; toindex=tos[toindex].link) { +# ifdef DEBUG + fprintf( stderr , + "[mcleanup] frompc 0x%x selfpc 0x%x count %d\n" , + frompc , tos[toindex].selfpc , tos[toindex].count ); +# endif DEBUG + rawarc.raw_frompc = (unsigned long) frompc; + rawarc.raw_selfpc = (unsigned long) tos[toindex].selfpc; + rawarc.raw_count = tos[toindex].count; + write( fd , &rawarc , sizeof rawarc ); + } + } + close( fd ); +} + +/* + * The Sparc stack frame is only held together by the frame pointers + * in the register windows. According to the SVR4 SPARC ABI + * Supplement, Low Level System Information/Operating System + * Interface/Software Trap Types, a type 3 trap will flush all of the + * register windows to the stack, which will make it possible to walk + * the frames and find the return addresses. + * However, it seems awfully expensive to incur a trap (system + * call) for every function call. It turns out that "call" simply puts + * the return address in %o7 expecting the "save" in the procedure to + * shift it into %i7; this means that before the "save" occurs, %o7 + * contains the address of the call to mcount, and %i7 still contains + * the caller above that. The asm mcount here simply saves those + * registers in argument registers and branches to internal_mcount, + * simulating a call with arguments. + * Kludges: + * 1) the branch to internal_mcount is hard coded; it should be + * possible to tell asm to use the assembler-name of a symbol. + * 2) in theory, the function calling mcount could have saved %i7 + * somewhere and reused the register; in practice, I *think* this will + * break longjmp (and maybe the debugger) but I'm not certain. (I take + * some comfort in the knowledge that it will break the native mcount + * as well.) + * 3) if builtin_return_address worked, this could be portable. + * However, it would really have to be optimized for arguments of 0 + * and 1 and do something like what we have here in order to avoid the + * trap per function call performance hit. + * 4) the atexit and monsetup calls prevent this from simply + * being a leaf routine that doesn't do a "save" (and would thus have + * access to %o7 and %i7 directly) but the call to write() at the end + * would have also prevented this. + * + * -- [eichin:19920702.1107EST] + */ + +static void internal_mcount PROTO((char *, unsigned short *)) ATTRIBUTE_UNUSED; + +/* i7 == last ret, -> frompcindex */ +/* o7 == current ret, -> selfpc */ +/* Solaris 2 libraries use _mcount. */ +asm(".global _mcount; _mcount: mov %i7,%o1; mov %o7,%o0;b,a internal_mcount"); +/* This is for compatibility with old versions of gcc which used mcount. */ +asm(".global mcount; mcount: mov %i7,%o1; mov %o7,%o0;b,a internal_mcount"); + +static void internal_mcount(selfpc, frompcindex) + register char *selfpc; + register unsigned short *frompcindex; +{ + register struct tostruct *top; + register struct tostruct *prevtop; + register long toindex; + static char already_setup; + + /* + * find the return address for mcount, + * and the return address for mcount's caller. + */ + + if(!already_setup) { + extern char etext[]; + already_setup = 1; + monstartup(0, (char *)etext); +#ifdef USE_ONEXIT + on_exit(_mcleanup, 0); +#else + atexit(_mcleanup); +#endif + } + /* + * check that we are profiling + * and that we aren't recursively invoked. + */ + if (profiling) { + goto out; + } + profiling++; + /* + * check that frompcindex is a reasonable pc value. + * for example: signal catchers get called from the stack, + * not from text space. too bad. + */ + frompcindex = (unsigned short *)((long)frompcindex - (long)s_lowpc); + if ((unsigned long)frompcindex > s_textsize) { + goto done; + } + frompcindex = + &froms[((long)frompcindex) / (HASHFRACTION * sizeof(*froms))]; + toindex = *frompcindex; + if (toindex == 0) { + /* + * first time traversing this arc + */ + toindex = ++tos[0].link; + if (toindex >= tolimit) { + goto overflow; + } + *frompcindex = toindex; + top = &tos[toindex]; + top->selfpc = selfpc; + top->count = 1; + top->link = 0; + goto done; + } + top = &tos[toindex]; + if (top->selfpc == selfpc) { + /* + * arc at front of chain; usual case. + */ + top->count++; + goto done; + } + /* + * have to go looking down chain for it. + * top points to what we are looking at, + * prevtop points to previous top. + * we know it is not at the head of the chain. + */ + for (; /* goto done */; ) { + if (top->link == 0) { + /* + * top is end of the chain and none of the chain + * had top->selfpc == selfpc. + * so we allocate a new tostruct + * and link it to the head of the chain. + */ + toindex = ++tos[0].link; + if (toindex >= tolimit) { + goto overflow; + } + top = &tos[toindex]; + top->selfpc = selfpc; + top->count = 1; + top->link = *frompcindex; + *frompcindex = toindex; + goto done; + } + /* + * otherwise, check the next arc on the chain. + */ + prevtop = top; + top = &tos[top->link]; + if (top->selfpc == selfpc) { + /* + * there it is. + * increment its count + * move it to the head of the chain. + */ + top->count++; + toindex = prevtop->link; + prevtop->link = top->link; + top->link = *frompcindex; + *frompcindex = toindex; + goto done; + } + + } +done: + profiling--; + /* and fall through */ +out: + return; /* normal return restores saved registers */ + +overflow: + profiling++; /* halt further profiling */ +# define TOLIMIT "mcount: tos overflow\n" + write(2, TOLIMIT, sizeof(TOLIMIT)); + goto out; +} + +/* + * Control profiling + * profiling is what mcount checks to see if + * all the data structures are ready. + */ +static void moncontrol(mode) + int mode; +{ + if (mode) { + /* start */ + profil((unsigned short *)(sbuf + sizeof(struct phdr)), + ssiz - sizeof(struct phdr), + (int)s_lowpc, s_scale); + profiling = 0; + } else { + /* stop */ + profil((unsigned short *)0, 0, 0, 0); + profiling = 3; + } +} diff --git a/contrib/gcc/config/sparc/hal.h b/contrib/gcc/config/sparc/hal.h new file mode 100644 index 000000000000..0222b819e0eb --- /dev/null +++ b/contrib/gcc/config/sparc/hal.h @@ -0,0 +1,33 @@ +/* Definitions of target machine for GNU compiler, for HAL + SPARC running Solaris 2 HALOS + Copyright 1998 Free Software Foundation, Inc. + Contributed by Carol LePage (carolo@hal.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Need different command line for assembler */ + +#undef ASM_SPEC +#define ASM_SPEC \ + "%{V} %{v:%{!V:-V}} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -e1 \ + %{fpic:-K PIC} %{fPIC:-K PIC}" + +/* Need DWARF for debuggers. */ + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG diff --git a/contrib/gcc/config/sparc/lb1spc.asm b/contrib/gcc/config/sparc/lb1spc.asm new file mode 100644 index 000000000000..831f33a988fb --- /dev/null +++ b/contrib/gcc/config/sparc/lb1spc.asm @@ -0,0 +1,784 @@ +/* This is an assembly language implementation of libgcc1.c for the sparc + processor. + + These routines are derived from the Sparc Architecture Manual, version 8, + slightly edited to match the desired calling convention, and also to + optimize them for our purposes. */ + +#ifdef L_mulsi3 +.text + .align 4 + .global .umul + .proc 4 +.umul: + or %o0, %o1, %o4 ! logical or of multiplier and multiplicand + mov %o0, %y ! multiplier to Y register + andncc %o4, 0xfff, %o5 ! mask out lower 12 bits + be mul_shortway ! can do it the short way + andcc %g0, %g0, %o4 ! zero the partial product and clear NV cc + ! + ! long multiply + ! + mulscc %o4, %o1, %o4 ! first iteration of 33 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 ! 32nd iteration + mulscc %o4, %g0, %o4 ! last iteration only shifts + ! the upper 32 bits of product are wrong, but we do not care + retl + rd %y, %o0 + ! + ! short multiply + ! +mul_shortway: + mulscc %o4, %o1, %o4 ! first iteration of 13 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 + mulscc %o4, %o1, %o4 ! 12th iteration + mulscc %o4, %g0, %o4 ! last iteration only shifts + rd %y, %o5 + sll %o4, 12, %o4 ! left shift partial product by 12 bits + srl %o5, 20, %o5 ! right shift partial product by 20 bits + retl + or %o5, %o4, %o0 ! merge for true product +#endif + +#ifdef L_divsi3 +/* + * Division and remainder, from Appendix E of the Sparc Version 8 + * Architecture Manual, with fixes from Gordon Irlam. + */ + +/* + * Input: dividend and divisor in %o0 and %o1 respectively. + * + * m4 parameters: + * .div name of function to generate + * div div=div => %o0 / %o1; div=rem => %o0 % %o1 + * true true=true => signed; true=false => unsigned + * + * Algorithm parameters: + * N how many bits per iteration we try to get (4) + * WORDSIZE total number of bits (32) + * + * Derived constants: + * TOPBITS number of bits in the top decade of a number + * + * Important variables: + * Q the partial quotient under development (initially 0) + * R the remainder so far, initially the dividend + * ITER number of main division loop iterations required; + * equal to ceil(log2(quotient) / N). Note that this + * is the log base (2^N) of the quotient. + * V the current comparand, initially divisor*2^(ITER*N-1) + * + * Cost: + * Current estimate for non-large dividend is + * ceil(log2(quotient) / N) * (10 + 7N/2) + C + * A large dividend is one greater than 2^(31-TOPBITS) and takes a + * different path, as the upper bits of the quotient must be developed + * one bit at a time. + */ + .global .udiv + .align 4 + .proc 4 + .text +.udiv: + b ready_to_divide + mov 0, %g3 ! result is always positive + + .global .div + .align 4 + .proc 4 + .text +.div: + ! compute sign of result; if neither is negative, no problem + orcc %o1, %o0, %g0 ! either negative? + bge ready_to_divide ! no, go do the divide + xor %o1, %o0, %g3 ! compute sign in any case + tst %o1 + bge 1f + tst %o0 + ! %o1 is definitely negative; %o0 might also be negative + bge ready_to_divide ! if %o0 not negative... + sub %g0, %o1, %o1 ! in any case, make %o1 nonneg +1: ! %o0 is negative, %o1 is nonnegative + sub %g0, %o0, %o0 ! make %o0 nonnegative + + +ready_to_divide: + + ! Ready to divide. Compute size of quotient; scale comparand. + orcc %o1, %g0, %o5 + bne 1f + mov %o0, %o3 + + ! Divide by zero trap. If it returns, return 0 (about as + ! wrong as possible, but that is what SunOS does...). + ta 0x2 ! ST_DIV0 + retl + clr %o0 + +1: + cmp %o3, %o5 ! if %o1 exceeds %o0, done + blu got_result ! (and algorithm fails otherwise) + clr %o2 + sethi %hi(1 << (32 - 4 - 1)), %g1 + cmp %o3, %g1 + blu not_really_big + clr %o4 + + ! Here the dividend is >= 2**(31-N) or so. We must be careful here, + ! as our usual N-at-a-shot divide step will cause overflow and havoc. + ! The number of bits in the result here is N*ITER+SC, where SC <= N. + ! Compute ITER in an unorthodox manner: know we need to shift V into + ! the top decade: so do not even bother to compare to R. + 1: + cmp %o5, %g1 + bgeu 3f + mov 1, %g2 + sll %o5, 4, %o5 + b 1b + add %o4, 1, %o4 + + ! Now compute %g2. + 2: addcc %o5, %o5, %o5 + bcc not_too_big + add %g2, 1, %g2 + + ! We get here if the %o1 overflowed while shifting. + ! This means that %o3 has the high-order bit set. + ! Restore %o5 and subtract from %o3. + sll %g1, 4, %g1 ! high order bit + srl %o5, 1, %o5 ! rest of %o5 + add %o5, %g1, %o5 + b do_single_div + sub %g2, 1, %g2 + + not_too_big: + 3: cmp %o5, %o3 + blu 2b + nop + be do_single_div + nop + /* NB: these are commented out in the V8-Sparc manual as well */ + /* (I do not understand this) */ + ! %o5 > %o3: went too far: back up 1 step + ! srl %o5, 1, %o5 + ! dec %g2 + ! do single-bit divide steps + ! + ! We have to be careful here. We know that %o3 >= %o5, so we can do the + ! first divide step without thinking. BUT, the others are conditional, + ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- + ! order bit set in the first step, just falling into the regular + ! division loop will mess up the first time around. + ! So we unroll slightly... + do_single_div: + subcc %g2, 1, %g2 + bl end_regular_divide + nop + sub %o3, %o5, %o3 + mov 1, %o2 + b end_single_divloop + nop + single_divloop: + sll %o2, 1, %o2 + bl 1f + srl %o5, 1, %o5 + ! %o3 >= 0 + sub %o3, %o5, %o3 + b 2f + add %o2, 1, %o2 + 1: ! %o3 < 0 + add %o3, %o5, %o3 + sub %o2, 1, %o2 + 2: + end_single_divloop: + subcc %g2, 1, %g2 + bge single_divloop + tst %o3 + b,a end_regular_divide + +not_really_big: +1: + sll %o5, 4, %o5 + cmp %o5, %o3 + bleu 1b + addcc %o4, 1, %o4 + be got_result + sub %o4, 1, %o4 + + tst %o3 ! set up for initial iteration +divloop: + sll %o2, 4, %o2 + ! depth 1, accumulated bits 0 + bl L1.16 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 2, accumulated bits 1 + bl L2.17 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits 3 + bl L3.19 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 7 + bl L4.23 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (7*2+1), %o2 + +L4.23: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (7*2-1), %o2 + + +L3.19: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 5 + bl L4.21 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (5*2+1), %o2 + +L4.21: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (5*2-1), %o2 + +L2.17: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits 1 + bl L3.17 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 3 + bl L4.19 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (3*2+1), %o2 + +L4.19: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (3*2-1), %o2 + +L3.17: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 1 + bl L4.17 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (1*2+1), %o2 + +L4.17: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (1*2-1), %o2 + +L1.16: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 2, accumulated bits -1 + bl L2.15 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits -1 + bl L3.15 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -1 + bl L4.15 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2+1), %o2 + +L4.15: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2-1), %o2 + +L3.15: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -3 + bl L4.13 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2+1), %o2 + +L4.13: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2-1), %o2 + +L2.15: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits -3 + bl L3.13 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -5 + bl L4.11 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2+1), %o2 + +L4.11: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2-1), %o2 + +L3.13: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -7 + bl L4.9 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2+1), %o2 + +L4.9: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2-1), %o2 + + 9: +end_regular_divide: + subcc %o4, 1, %o4 + bge divloop + tst %o3 + bl,a got_result + ! non-restoring fixup here (one instruction only!) + sub %o2, 1, %o2 + + +got_result: + ! check to see if answer should be < 0 + tst %g3 + bl,a 1f + sub %g0, %o2, %o2 +1: + retl + mov %o2, %o0 +#endif + +#ifdef L_modsi3 +/* This implementation was taken from glibc: + * + * Input: dividend and divisor in %o0 and %o1 respectively. + * + * Algorithm parameters: + * N how many bits per iteration we try to get (4) + * WORDSIZE total number of bits (32) + * + * Derived constants: + * TOPBITS number of bits in the top decade of a number + * + * Important variables: + * Q the partial quotient under development (initially 0) + * R the remainder so far, initially the dividend + * ITER number of main division loop iterations required; + * equal to ceil(log2(quotient) / N). Note that this + * is the log base (2^N) of the quotient. + * V the current comparand, initially divisor*2^(ITER*N-1) + * + * Cost: + * Current estimate for non-large dividend is + * ceil(log2(quotient) / N) * (10 + 7N/2) + C + * A large dividend is one greater than 2^(31-TOPBITS) and takes a + * different path, as the upper bits of the quotient must be developed + * one bit at a time. + */ +.text + .align 4 + .global .urem + .proc 4 +.urem: + b divide + mov 0, %g3 ! result always positive + + .align 4 + .global .rem + .proc 4 +.rem: + ! compute sign of result; if neither is negative, no problem + orcc %o1, %o0, %g0 ! either negative? + bge 2f ! no, go do the divide + mov %o0, %g3 ! sign of remainder matches %o0 + tst %o1 + bge 1f + tst %o0 + ! %o1 is definitely negative; %o0 might also be negative + bge 2f ! if %o0 not negative... + sub %g0, %o1, %o1 ! in any case, make %o1 nonneg +1: ! %o0 is negative, %o1 is nonnegative + sub %g0, %o0, %o0 ! make %o0 nonnegative +2: + + ! Ready to divide. Compute size of quotient; scale comparand. +divide: + orcc %o1, %g0, %o5 + bne 1f + mov %o0, %o3 + + ! Divide by zero trap. If it returns, return 0 (about as + ! wrong as possible, but that is what SunOS does...). + ta 0x2 !ST_DIV0 + retl + clr %o0 + +1: + cmp %o3, %o5 ! if %o1 exceeds %o0, done + blu got_result ! (and algorithm fails otherwise) + clr %o2 + sethi %hi(1 << (32 - 4 - 1)), %g1 + cmp %o3, %g1 + blu not_really_big + clr %o4 + + ! Here the dividend is >= 2**(31-N) or so. We must be careful here, + ! as our usual N-at-a-shot divide step will cause overflow and havoc. + ! The number of bits in the result here is N*ITER+SC, where SC <= N. + ! Compute ITER in an unorthodox manner: know we need to shift V into + ! the top decade: so do not even bother to compare to R. + 1: + cmp %o5, %g1 + bgeu 3f + mov 1, %g2 + sll %o5, 4, %o5 + b 1b + add %o4, 1, %o4 + + ! Now compute %g2. + 2: addcc %o5, %o5, %o5 + bcc not_too_big + add %g2, 1, %g2 + + ! We get here if the %o1 overflowed while shifting. + ! This means that %o3 has the high-order bit set. + ! Restore %o5 and subtract from %o3. + sll %g1, 4, %g1 ! high order bit + srl %o5, 1, %o5 ! rest of %o5 + add %o5, %g1, %o5 + b do_single_div + sub %g2, 1, %g2 + + not_too_big: + 3: cmp %o5, %o3 + blu 2b + nop + be do_single_div + nop + /* NB: these are commented out in the V8-Sparc manual as well */ + /* (I do not understand this) */ + ! %o5 > %o3: went too far: back up 1 step + ! srl %o5, 1, %o5 + ! dec %g2 + ! do single-bit divide steps + ! + ! We have to be careful here. We know that %o3 >= %o5, so we can do the + ! first divide step without thinking. BUT, the others are conditional, + ! and are only done if %o3 >= 0. Because both %o3 and %o5 may have the high- + ! order bit set in the first step, just falling into the regular + ! division loop will mess up the first time around. + ! So we unroll slightly... + do_single_div: + subcc %g2, 1, %g2 + bl end_regular_divide + nop + sub %o3, %o5, %o3 + mov 1, %o2 + b end_single_divloop + nop + single_divloop: + sll %o2, 1, %o2 + bl 1f + srl %o5, 1, %o5 + ! %o3 >= 0 + sub %o3, %o5, %o3 + b 2f + add %o2, 1, %o2 + 1: ! %o3 < 0 + add %o3, %o5, %o3 + sub %o2, 1, %o2 + 2: + end_single_divloop: + subcc %g2, 1, %g2 + bge single_divloop + tst %o3 + b,a end_regular_divide + +not_really_big: +1: + sll %o5, 4, %o5 + cmp %o5, %o3 + bleu 1b + addcc %o4, 1, %o4 + be got_result + sub %o4, 1, %o4 + + tst %o3 ! set up for initial iteration +divloop: + sll %o2, 4, %o2 + ! depth 1, accumulated bits 0 + bl L1.16 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 2, accumulated bits 1 + bl L2.17 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits 3 + bl L3.19 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 7 + bl L4.23 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (7*2+1), %o2 +L4.23: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (7*2-1), %o2 + +L3.19: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 5 + bl L4.21 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (5*2+1), %o2 + +L4.21: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (5*2-1), %o2 + +L2.17: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits 1 + bl L3.17 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits 3 + bl L4.19 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (3*2+1), %o2 + +L4.19: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (3*2-1), %o2 + +L3.17: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits 1 + bl L4.17 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (1*2+1), %o2 + +L4.17: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (1*2-1), %o2 + +L1.16: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 2, accumulated bits -1 + bl L2.15 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 3, accumulated bits -1 + bl L3.15 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -1 + bl L4.15 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2+1), %o2 + +L4.15: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-1*2-1), %o2 + +L3.15: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -3 + bl L4.13 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2+1), %o2 + +L4.13: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-3*2-1), %o2 + +L2.15: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 3, accumulated bits -3 + bl L3.13 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + ! depth 4, accumulated bits -5 + bl L4.11 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2+1), %o2 + +L4.11: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-5*2-1), %o2 + +L3.13: + ! remainder is negative + addcc %o3,%o5,%o3 + ! depth 4, accumulated bits -7 + bl L4.9 + srl %o5,1,%o5 + ! remainder is positive + subcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2+1), %o2 + +L4.9: + ! remainder is negative + addcc %o3,%o5,%o3 + b 9f + add %o2, (-7*2-1), %o2 + + 9: +end_regular_divide: + subcc %o4, 1, %o4 + bge divloop + tst %o3 + bl,a got_result + ! non-restoring fixup here (one instruction only!) + add %o3, %o1, %o3 + +got_result: + ! check to see if answer should be < 0 + tst %g3 + bl,a 1f + sub %g0, %o3, %o3 +1: + retl + mov %o3, %o0 + +#endif + diff --git a/contrib/gcc/config/sparc/lb1spl.asm b/contrib/gcc/config/sparc/lb1spl.asm new file mode 100644 index 000000000000..4c8bc30b83d5 --- /dev/null +++ b/contrib/gcc/config/sparc/lb1spl.asm @@ -0,0 +1,246 @@ +/* This is an assembly language implementation of libgcc1.c for the sparclite + processor. + + These routines are all from the Sparclite User's Guide, slightly edited + to match the desired calling convention, and also to optimize them. */ + +#ifdef L_udivsi3 +.text + .align 4 + .global .udiv + .proc 04 +.udiv: + wr %g0,%g0,%y ! Not a delayed write for sparclite + tst %g0 + divscc %o0,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + retl + divscc %g1,%o1,%o0 +#endif + +#ifdef L_umodsi3 +.text + .align 4 + .global .urem + .proc 04 +.urem: + wr %g0,%g0,%y ! Not a delayed write for sparclite + tst %g0 + divscc %o0,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + divscc %g1,%o1,%g1 + bl 1f + rd %y,%o0 + retl + nop +1: retl + add %o0,%o1,%o0 +#endif + +#ifdef L_divsi3 +.text + .align 4 + .global .div + .proc 04 +! ??? This routine could be made faster if was optimized, and if it was +! rewritten to only calculate the quotient. +.div: + wr %g0,%g0,%y ! Not a delayed write for sparclite + mov %o1,%o4 + tst %o1 + bl,a 1f + sub %g0,%o4,%o4 +1: tst %o0 + bl,a 2f + mov -1,%y +2: divscc %o0,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + be 6f + mov %y,%o3 + bg 4f + addcc %o3,%o4,%g0 + be,a 6f + mov %g0,%o3 + tst %o0 + bl 5f + tst %g1 + ba 5f + add %o3,%o4,%o3 +4: subcc %o3,%o4,%g0 + be,a 6f + mov %g0,%o3 + tst %o0 + bge 5f + tst %g1 + sub %o3,%o4,%o3 +5: bl,a 6f + add %g1,1,%g1 +6: tst %o1 + bl,a 7f + sub %g0,%g1,%g1 +7: retl + mov %g1,%o0 ! Quotient is in %g1. +#endif + +#ifdef L_modsi3 +.text + .align 4 + .global .rem + .proc 04 +! ??? This routine could be made faster if was optimized, and if it was +! rewritten to only calculate the remainder. +.rem: + wr %g0,%g0,%y ! Not a delayed write for sparclite + mov %o1,%o4 + tst %o1 + bl,a 1f + sub %g0,%o4,%o4 +1: tst %o0 + bl,a 2f + mov -1,%y +2: divscc %o0,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + divscc %g1,%o4,%g1 + be 6f + mov %y,%o3 + bg 4f + addcc %o3,%o4,%g0 + be,a 6f + mov %g0,%o3 + tst %o0 + bl 5f + tst %g1 + ba 5f + add %o3,%o4,%o3 +4: subcc %o3,%o4,%g0 + be,a 6f + mov %g0,%o3 + tst %o0 + bge 5f + tst %g1 + sub %o3,%o4,%o3 +5: bl,a 6f + add %g1,1,%g1 +6: tst %o1 + bl,a 7f + sub %g0,%g1,%g1 +7: retl + mov %o3,%o0 ! Remainder is in %o3. +#endif diff --git a/contrib/gcc/config/sparc/linux-aout.h b/contrib/gcc/config/sparc/linux-aout.h new file mode 100644 index 000000000000..76d7653eaae6 --- /dev/null +++ b/contrib/gcc/config/sparc/linux-aout.h @@ -0,0 +1,130 @@ +/* Definitions for SPARC running Linux-based GNU systems with a.out. + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Eddie C. Dost (ecd@skynet.be) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <aoutos.h> +#include <sparc/sparc.h> + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +#undef HAVE_ATEXIT +#define HAVE_ATEXIT + +/* GNU/Linux uses ctype from glibc.a. I am not sure how complete it is. + For now, we play safe. It may change later. */ + +#if 0 +#undef MULTIBYTE_CHARS +#define MULTIBYTE_CHARS 1 +#endif + +/* We need that too. */ +#define HANDLE_SYSV_PRAGMA + +#undef MD_EXEC_PREFIX +#undef MD_STARTFILE_PREFIX + +/* Output at beginning of assembler file. */ +/* The .file command should always begin the output. */ +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + output_file_directive (FILE, main_input_filename); \ + fprintf (FILE, "\t.version\t\"01.01\"\n"); \ + } while (0) + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}" + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with a.out)"); + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Dsparc -Dlinux -Asystem(unix) -Asystem(posix)" + +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC \ +"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}" + +/* Don't default to pcc-struct-return, because gcc is the only compiler, + and we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +#undef LIB_SPEC + +#if 1 +/* We no longer link with libc_p.a or libg.a by default. If you + want to profile or debug the GNU/Linux C library, please add + -lc_p or -ggdb to LDFLAGS at the link time, respectively. */ +#define LIB_SPEC \ +"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}" +#else +#define LIB_SPEC \ +"%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \ + %{!p:%{!pg:%{!g*:-lc} %{g*:-lg -static}}}" +#endif + +#undef LINK_SPEC +#define LINK_SPEC "-m sparclinux" + +/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). + It's safe to pass -s always, even if -g is not used. */ +#undef ASM_SPEC +#define ASM_SPEC \ + "%{V} %{v:%{!V:-V}} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s %{fpic:-K PIC} %{fPIC:-K PIC}" + +#if 0 +/* Define for support of TFmode long double and REAL_ARITHMETIC. + Sparc ABI says that long double is 4 words. GNU/Linux does not support + long double yet. */ +#define LONG_DOUBLE_TYPE_SIZE 128 +#endif + +/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special + traps available which can get and set the condition codes + reliably. */ +#undef MACHINE_STATE_SAVE +#define MACHINE_STATE_SAVE(ID) \ + unsigned long int ms_flags, ms_saveret; \ + asm volatile("ta 0x20\n\t" \ + "mov %%g1, %0\n\t" \ + "mov %%g2, %1\n\t" \ + : "=r" (ms_flags), "=r" (ms_saveret)); + +#undef MACHINE_STATE_RESTORE +#define MACHINE_STATE_RESTORE(ID) \ + asm volatile("mov %0, %%g1\n\t" \ + "mov %1, %%g2\n\t" \ + "ta 0x21\n\t" \ + : /* no outputs */ \ + : "r" (ms_flags), "r" (ms_saveret)); diff --git a/contrib/gcc/config/sparc/linux.h b/contrib/gcc/config/sparc/linux.h new file mode 100644 index 000000000000..40694908b68d --- /dev/null +++ b/contrib/gcc/config/sparc/linux.h @@ -0,0 +1,259 @@ +/* Definitions for SPARC running Linux-based GNU systems with ELF. + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by Eddie C. Dost (ecd@skynet.be) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define LINUX_DEFAULT_ELF + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +#undef HAVE_ATEXIT +#define HAVE_ATEXIT + +/* GNU/Linux uses ctype from glibc.a. I am not sure how complete it is. + For now, we play safe. It may change later. */ + +#if 0 +#undef MULTIBYTE_CHARS +#define MULTIBYTE_CHARS 1 +#endif + +#ifndef USE_GNULIBC_1 +#undef DEFAULT_VTABLE_THUNKS +#define DEFAULT_VTABLE_THUNKS 2 +#endif + +/* Use stabs instead of DWARF debug format. */ +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include <sparc/sysv4.h> + +#undef MD_EXEC_PREFIX +#undef MD_STARTFILE_PREFIX + +/* Output at beginning of assembler file. */ +/* The .file command should always begin the output. */ +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + output_file_directive (FILE, main_input_filename); \ + fprintf (FILE, "\t.version\t\"01.01\"\n"); \ + } while (0) + +/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add + the GNU/Linux magical crtbegin.o file (see crtstuff.c) which + provides part of the support for getting C++ file-scope static + object constructed before entering `main'. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shared: \ + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\ + crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" + +/* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on + the GNU/Linux magical crtend.o file (see crtstuff.c) which + provides part of the support for getting C++ file-scope static + object constructed before entering `main', followed by a normal + GNU/Linux "finalizer" file, `crtn.o'. */ + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s" + +/* This is for -profile to use -lc_p instead of -lc. */ +#undef CC1_SPEC +#define CC1_SPEC "%{profile:-p} \ +%{sun4:} %{target:} \ +%{mcypress:-mcpu=cypress} \ +%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ +%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ +" + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with ELF)"); + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-D__ELF__ -Dunix -D__sparc__ -Dlinux -Asystem(unix) -Asystem(posix)" + +#undef CPP_SUBTARGET_SPEC +#ifdef USE_GNULIBC_1 +#define CPP_SUBTARGET_SPEC \ +"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE}" +#else +#define CPP_SUBTARGET_SPEC \ +"%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}" +#endif + +#undef LIB_SPEC +/* We no longer link with libc_p.a or libg.a by default. If you + want to profile or debug the GNU/Linux C library, please add + -lc_p or -ggdb to LDFLAGS at the link time, respectively. */ +#if 1 +#ifdef USE_GNULIBC_1 +#define LIB_SPEC \ + "%{!shared: %{p:-lgmon} %{pg:-lgmon} %{profile:-lgmon -lc_p} \ + %{!profile:%{!ggdb:-lc} %{ggdb:-lg}}}" +#else +#define LIB_SPEC \ + "%{shared: -lc} \ + %{!shared: %{mieee-fp:-lieee} %{pthread:-lpthread} \ + %{profile:-lc_p} %{!profile: -lc}}" +#endif +#else +#define LIB_SPEC \ + "%{!shared: \ + %{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \ + %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}}" +#endif + +/* Provide a LINK_SPEC appropriate for GNU/Linux. Here we provide support + for the special GCC options -static and -shared, which allow us to + link things in one of these three modes by applying the appropriate + combinations of options at link-time. We like to support here for + as many of the other GNU linker options as possible. But I don't + have the time to search for those flags. I am sure how to add + support for -soname shared_object_name. H.J. + + I took out %{v:%{!V:-V}}. It is too much :-(. They can use + -Wl,-V. + + When the -shared link option is used a final link is not being + done. */ + +/* If ELF is the default format, we should not use /lib/elf. */ + +#undef LINK_SPEC +#ifdef USE_GNULIBC_1 +#ifndef LINUX_DEFAULT_ELF +#define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/elf/ld-linux.so.1} \ + %{!rpath:-rpath /lib/elf/}} %{static:-static}}}" +#else +#define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.1}} \ + %{static:-static}}}" +#endif +#else +#define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2}} \ + %{static:-static}}}" +#endif + +/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). + It's safe to pass -s always, even if -g is not used. */ +#undef ASM_SPEC +#define ASM_SPEC \ + "%{V} %{v:%{!V:-V}} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s %{fpic:-K PIC} %{fPIC:-K PIC}" + +/* Same as sparc.h */ +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(REGNO) (REGNO) + +/* We use stabs-in-elf for debugging, because that is what the native + toolchain uses. XXX */ +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#undef ASM_OUTPUT_ALIGNED_LOCAL +#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ +do { \ + fputs ("\t.local\t", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + putc ('\n', (FILE)); \ + ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN); \ +} while (0) + +#undef COMMON_ASM_OP +#define COMMON_ASM_OP "\t.common" + +/* This is how to output a definition of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".L%s%d:\n", PREFIX, NUM) + +/* This is how to output a reference to an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABELREF +#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ + fprintf (FILE, ".L%s%d", PREFIX, NUM) + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf (LABEL, "*.L%s%d", PREFIX, NUM) + + +#if 0 +/* Define for support of TFmode long double and REAL_ARITHMETIC. + Sparc ABI says that long double is 4 words. GNU/Linux does not support + long double yet. */ +#define LONG_DOUBLE_TYPE_SIZE 128 +#endif + +/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special + traps available which can get and set the condition codes + reliably. */ +#undef MACHINE_STATE_SAVE +#define MACHINE_STATE_SAVE(ID) \ + unsigned long int ms_flags, ms_saveret; \ + asm volatile("ta 0x20\n\t" \ + "mov %%g1, %0\n\t" \ + "mov %%g2, %1\n\t" \ + : "=r" (ms_flags), "=r" (ms_saveret)); + +#undef MACHINE_STATE_RESTORE +#define MACHINE_STATE_RESTORE(ID) \ + asm volatile("mov %0, %%g1\n\t" \ + "mov %1, %%g2\n\t" \ + "ta 0x21\n\t" \ + : /* no outputs */ \ + : "r" (ms_flags), "r" (ms_saveret)); diff --git a/contrib/gcc/config/sparc/linux64.h b/contrib/gcc/config/sparc/linux64.h new file mode 100644 index 000000000000..705b5ca33a04 --- /dev/null +++ b/contrib/gcc/config/sparc/linux64.h @@ -0,0 +1,366 @@ +/* Definitions for 64-bit SPARC running Linux-based GNU systems with ELF. + Copyright 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@caip.rutgers.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define SPARC_BI_ARCH + +#define LINUX_DEFAULT_ELF + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +#undef HAVE_ATEXIT +#define HAVE_ATEXIT + +#include <sparc/sysv4.h> + +#undef MD_EXEC_PREFIX +#undef MD_STARTFILE_PREFIX + +#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc +/* A 64 bit v9 compiler with stack-bias, + in a Medium/Low code model environment. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT \ + (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \ + + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) +#endif + +/* Output at beginning of assembler file. */ +/* The .file command should always begin the output. */ +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + output_file_directive (FILE, main_input_filename); \ + fprintf (FILE, "\t.version\t\"01.01\"\n"); \ + } while (0) + +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC "-Av9a" + +/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add + the GNU/Linux magical crtbegin.o file (see crtstuff.c) which + provides part of the support for getting C++ file-scope static + object constructed before entering `main'. */ + +#undef STARTFILE_SPEC + +#define STARTFILE_SPEC32 \ + "%{!shared: \ + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\ + crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" + +#define STARTFILE_SPEC64 \ + "%{!shared: \ + %{pg:/usr/lib64/gcrt1.o%s} %{!pg:%{p:/usr/lib64/gcrt1.o%s} %{!p:/usr/lib64/crt1.o%s}}}\ + /usr/lib64/crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" + +#ifdef SPARC_BI_ARCH + +#if DEFAULT_ARCH32_P +#define STARTFILE_SPEC "\ +%{m32:" STARTFILE_SPEC32 "} \ +%{m64:" STARTFILE_SPEC64 "} \ +%{!m32:%{!m64:" STARTFILE_SPEC32 "}}" +#else +#define STARTFILE_SPEC "\ +%{m32:" STARTFILE_SPEC32 "} \ +%{m64:" STARTFILE_SPEC64 "} \ +%{!m32:%{!m64:" STARTFILE_SPEC64 "}}" +#endif + +#else + +#define STARTFILE_SPEC STARTFILE_SPEC64 + +#endif + +/* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on + the GNU/Linux magical crtend.o file (see crtstuff.c) which + provides part of the support for getting C++ file-scope static + object constructed before entering `main', followed by a normal + GNU/Linux "finalizer" file, `crtn.o'. */ + +#undef ENDFILE_SPEC + +#define ENDFILE_SPEC32 \ + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s" + +#define ENDFILE_SPEC64 \ + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} /usr/lib64/crtn.o%s" + +#ifdef SPARC_BI_ARCH + +#if DEFAULT_ARCH32_P +#define ENDFILE_SPEC "\ +%{m32:" ENDFILE_SPEC32 "} \ +%{m64:" ENDFILE_SPEC64 "} \ +%{!m32:%{!m64:" ENDFILE_SPEC32 "}}" +#else +#define ENDFILE_SPEC "\ +%{m32:" ENDFILE_SPEC32 "} \ +%{m64:" ENDFILE_SPEC64 "} \ +%{!m32:%{!m64:" ENDFILE_SPEC64 "}}" +#endif + +#else + +#define ENDFILE_SPEC ENDFILE_SPEC64 + +#endif + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (sparc64 GNU/Linux with ELF)"); + +/* The default code model. */ +#undef SPARC_DEFAULT_CMODEL +#define SPARC_DEFAULT_CMODEL CM_MEDLOW + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 128 + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-D__ELF__ -Dunix -D_LONGLONG -D__sparc__ -Dlinux -Asystem(unix) -Asystem(posix)" + +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC "\ +%{fPIC:-D__PIC__ -D__pic__} \ +%{fpic:-D__PIC__ -D__pic__} \ +%{posix:-D_POSIX_SOURCE} \ +%{pthread:-D_REENTRANT} \ +" + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{shared: -lc} \ + %{!shared: %{mieee-fp:-lieee} %{pthread:-lpthread} \ + %{profile:-lc_p} %{!profile: -lc}}" + +/* Provide a LINK_SPEC appropriate for GNU/Linux. Here we provide support + for the special GCC options -static and -shared, which allow us to + link things in one of these three modes by applying the appropriate + combinations of options at link-time. We like to support here for + as many of the other GNU linker options as possible. But I don't + have the time to search for those flags. I am sure how to add + support for -soname shared_object_name. H.J. + + I took out %{v:%{!V:-V}}. It is too much :-(. They can use + -Wl,-V. + + When the -shared link option is used a final link is not being + done. */ + +/* If ELF is the default format, we should not use /lib/elf. */ + +#ifdef SPARC_BI_ARCH + +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "link_arch32", LINK_ARCH32_SPEC }, \ + { "link_arch64", LINK_ARCH64_SPEC }, \ + { "link_arch_default", LINK_ARCH_DEFAULT_SPEC }, \ + { "link_arch", LINK_ARCH_SPEC }, + +#define LINK_ARCH32_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2}} \ + %{static:-static}}} \ +" + +#define LINK_ARCH64_SPEC "-m elf64_sparc -Y P,/usr/lib64 %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib64/ld-linux.so.2}} \ + %{static:-static}}} \ +" + +#define LINK_ARCH_SPEC "\ +%{m32:%(link_arch32)} \ +%{m64:%(link_arch64)} \ +%{!m32:%{!m64:%(link_arch_default)}} \ +" + +#define LINK_ARCH_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? LINK_ARCH32_SPEC : LINK_ARCH64_SPEC) + +#undef LINK_SPEC +#define LINK_SPEC "\ +%(link_arch) \ +%{mlittle-endian:-EL} \ +" + +#undef CC1_SPEC +#if DEFAULT_ARCH32_P +#define CC1_SPEC "\ +%{sun4:} %{target:} \ +%{mcypress:-mcpu=cypress} \ +%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ +%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ +%{m64:-mptr64 -mcpu=ultrasparc -mstack-bias} \ +" +#else +#define CC1_SPEC "\ +%{sun4:} %{target:} \ +%{mcypress:-mcpu=cypress} \ +%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ +%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ +%{m32:-mptr32 -mcpu=cypress -mno-stack-bias} \ +" +#endif + +#if DEFAULT_ARCH32_P +#define MULTILIB_DEFAULTS { "m32" } +#else +#define MULTILIB_DEFAULTS { "m64" } +#endif + +#else /* !SPARC_BI_ARCH */ + +#undef LINK_SPEC +#define LINK_ARCH_SPEC "-m elf64_sparc -Y P,/usr/lib64 %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib64/ld-linux.so.2}} \ + %{static:-static}}} \ +%{mlittle-endian:-EL} \ +" + +#endif /* !SPARC_BI_ARCH */ + +/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). + It's safe to pass -s always, even if -g is not used. */ +#undef ASM_SPEC +#define ASM_SPEC "\ +%{V} \ +%{v:%{!V:-V}} \ +%{!Qn:-Qy} \ +%{n} \ +%{T} \ +%{Ym,*} \ +%{Wa,*:%*} \ +-s %{fpic:-K PIC} %{fPIC:-K PIC} \ +%{mlittle-endian:-EL} \ +%(asm_cpu) %(asm_arch) \ +" + +/* Same as sparc.h */ +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(REGNO) (REGNO) + +/* System V Release 4 uses DWARF debugging info. Buf DWARF1 doesn't do + 64-bit anything, so we use DWARF2. */ + +#undef DWARF2_DEBUGGING_INFO +#undef DWARF_DEBUGGING_INFO +#undef DBX_DEBUGGING_INFO +#define DWARF2_DEBUGGING_INFO +#define DBX_DEBUGGING_INFO + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + +#undef ASM_OUTPUT_ALIGNED_LOCAL +#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ +do { \ + fputs ("\t.local\t", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + putc ('\n', (FILE)); \ + ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN); \ +} while (0) + +#undef COMMON_ASM_OP +#define COMMON_ASM_OP "\t.common" + +/* This is how to output a definition of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".L%s%d:\n", PREFIX, NUM) + +/* This is how to output a reference to an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABELREF +#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ + fprintf (FILE, ".L%s%d", PREFIX, NUM) + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf (LABEL, "*.L%s%d", PREFIX, NUM) + +/* Stabs doesn't use this, and it confuses a simulator. */ +/* ??? Need to see what DWARF needs, if anything. */ +#undef ASM_IDENTIFY_GCC +#define ASM_IDENTIFY_GCC(FILE) + +/* Define the names of various pseudo-ops used by the Sparc/svr4 assembler. + ??? If ints are 64 bits then UNALIGNED_INT_ASM_OP (defined elsewhere) is + misnamed. These should all refer to explicit sizes (half/word/xword?), + anything other than short/int/long/etc. */ + +#define UNALIGNED_DOUBLE_INT_ASM_OP ".uaxword" + +/* DWARF bits. */ + +/* Follow Irix 6 and not the Dwarf2 draft in using 64-bit offsets. + Obviously the Dwarf2 folks havn't tried to actually build systems + with their spec. On a 64-bit system, only 64-bit relocs become + RELATIVE relocations. */ + +/* #define DWARF_OFFSET_SIZE PTR_SIZE */ + +/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special + traps available which can get and set the condition codes + reliably. */ +#undef MACHINE_STATE_SAVE +#define MACHINE_STATE_SAVE(ID) \ + unsigned long int ms_flags, ms_saveret; \ + asm volatile("ta 0x20\n\t" \ + "mov %%g1, %0\n\t" \ + "mov %%g2, %1\n\t" \ + : "=r" (ms_flags), "=r" (ms_saveret)); + +#undef MACHINE_STATE_RESTORE +#define MACHINE_STATE_RESTORE(ID) \ + asm volatile("mov %0, %%g1\n\t" \ + "mov %1, %%g2\n\t" \ + "ta 0x21\n\t" \ + : /* no outputs */ \ + : "r" (ms_flags), "r" (ms_saveret)); diff --git a/contrib/gcc/config/sparc/lite.h b/contrib/gcc/config/sparc/lite.h new file mode 100644 index 000000000000..55c232ac7798 --- /dev/null +++ b/contrib/gcc/config/sparc/lite.h @@ -0,0 +1,38 @@ +/* Definitions of target machine for GNU compiler, for SPARClite w/o FPU. + Copyright (C) 1993, 1996 Free Software Foundation, Inc. + Contributed by Jim Wilson (wilson@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/sparc.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -Dsparclite -Acpu(sparc) -Amachine(sparc)" + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (sparclite)"); + +/* Enable app-regs and epilogue options. Do not enable the fpu. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE) + +/* US Software GOFAST library support. */ +#include "gofast.h" +#undef INIT_SUBTARGET_OPTABS +#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS diff --git a/contrib/gcc/config/sparc/litecoff.h b/contrib/gcc/config/sparc/litecoff.h new file mode 100644 index 000000000000..bd89e1b46865 --- /dev/null +++ b/contrib/gcc/config/sparc/litecoff.h @@ -0,0 +1,113 @@ +/* Definitions of target machine for GNU compiler, for SPARClite w/o FPU, COFF. + Copyright (C) 1994, 1996 Free Software Foundation, Inc. + Written by Ken Raeburn (raeburn@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/lite.h" + +#undef ASM_OUTPUT_IDENT + +#undef SELECT_SECTION +#undef SELECT_RTX_SECTION +#define BSS_SECTION_ASM_OP ".section\t\".bss\"" + +#include "svr3.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -Dsparclite -Acpu(sparc) -Amachine(sparc)" + +/* Default to stabs in COFF. */ + +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "dbxcoff.h" + +/* Support the ctors and dtors sections for g++. */ + +#undef INIT_SECTION_ASM_OP + +/* Support the ctors and dtors sections for g++. */ + +#undef CTORS_SECTION_ASM_OP +#define CTORS_SECTION_ASM_OP ".section\t.ctors,\"x\"" +#undef DTORS_SECTION_ASM_OP +#define DTORS_SECTION_ASM_OP ".section\t.dtors,\"x\"" + +/* A list of other sections which the compiler might be "in" at any + given time. */ + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_const, in_ctors, in_dtors + +/* A list of extra section function definitions. */ + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CONST_SECTION_FUNCTION \ + CTORS_SECTION_FUNCTION \ + DTORS_SECTION_FUNCTION + +#define CTORS_SECTION_FUNCTION \ +void \ +ctors_section () \ +{ \ + if (in_section != in_ctors) \ + { \ + fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ + in_section = in_ctors; \ + } \ +} + +#define DTORS_SECTION_FUNCTION \ +void \ +dtors_section () \ +{ \ + if (in_section != in_dtors) \ + { \ + fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ + in_section = in_dtors; \ + } \ +} + +#define INT_ASM_OP ".long" + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#undef ASM_OUTPUT_CONSTRUCTOR +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t ", INT_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#undef ASM_OUTPUT_DESTRUCTOR +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t ", INT_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#undef DO_GLOBAL_CTORS_BODY +#undef DO_GLOBAL_DTORS_BODY diff --git a/contrib/gcc/config/sparc/lynx-ng.h b/contrib/gcc/config/sparc/lynx-ng.h new file mode 100644 index 000000000000..9e9f82cf10b6 --- /dev/null +++ b/contrib/gcc/config/sparc/lynx-ng.h @@ -0,0 +1,41 @@ +/* Definitions for SPARC running LynxOS, using Lynx's old as and ld. + Copyright (C) 1993, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <sparc/sparc.h> +#include <lynx-ng.h> + +/* ??? Must redefine to get sparclite and v8 defines. Can this be done + differently? */ + +#undef CPP_SPEC +#define CPP_SPEC "%{mthreads:-D_MULTITHREADED} \ + %{mposix:-D_POSIX_SOURCE} \ + %{msystem-v:-I/usr/include_v} \ + %(cpp_cpu)" + +/* Names to predefine in the preprocessor for this target machine. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Dsparc -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(sparc) -Amachine(sparc)" + +/* Provide required defaults for linker switches. */ + +#undef LINK_SPEC +#define LINK_SPEC "-e __main -T 0 %{msystem-v:-V} %{mcoff:-k}" diff --git a/contrib/gcc/config/sparc/lynx.h b/contrib/gcc/config/sparc/lynx.h new file mode 100644 index 000000000000..99b319a0df22 --- /dev/null +++ b/contrib/gcc/config/sparc/lynx.h @@ -0,0 +1,53 @@ +/* Definitions for SPARC running LynxOS. + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <sparc/sparc.h> + +#undef ASM_OUTPUT_IDENT +#undef SELECT_SECTION +#undef SELECT_RTX_SECTION + +#define BSS_SECTION_ASM_OP ".section\t\".bss\"" + +#include <lynx.h> + +/* ??? Must redefine to get sparclite and v8 defines. Can this be done + differently? */ + +#undef CPP_SPEC +#define CPP_SPEC "%{mthreads:-D_MULTITHREADED} \ + %{mposix:-D_POSIX_SOURCE} \ + %{msystem-v:-I/usr/include_v} \ + %(cpp_cpu)" + +/* Names to predefine in the preprocessor for this target machine. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Dsparc -DSPARC -DLynx -DLYNX -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(sparc) -Amachine(sparc)" + +#undef LINK_SPEC + +/* Sparc version of libc.a has references to libm.a (printf calls pow for + instance), so we must always link both. */ + +#undef LIB_SPEC +#define LIB_SPEC "%{mthreads:-L/lib/thread/} \ + %{msystem-v:-lc_v -lm_v -lc_v} \ + %{!msystem-v:%{mposix:-lc_p} -lc -lm -lc}" diff --git a/contrib/gcc/config/sparc/netbsd.h b/contrib/gcc/config/sparc/netbsd.h new file mode 100644 index 000000000000..a512f41e1553 --- /dev/null +++ b/contrib/gcc/config/sparc/netbsd.h @@ -0,0 +1,46 @@ +#include <sparc/sparc.h> + +/* Get generic NetBSD definitions. */ + +#include <netbsd.h> + +/* Names to predefine in the preprocessor for this target machine. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Dsparc -D__NetBSD__ -Asystem(unix) -Asystem(NetBSD) -Acpu(sparc) -Amachine(sparc)" + +/* Make gcc agree with <machine/ansi.h> */ + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "int" + +#undef WCHAR_UNSIGNED +#define WCHAR_UNSIGNED 0 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 32 + +/* This is BSD, so it wants DBX format. */ + +#define DBX_DEBUGGING_INFO + +/* This is the char to use for continuation (in case we need to turn + continuation back on). */ + +#define DBX_CONTIN_CHAR '?' + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#undef DEFAULT_PCC_STRUCT_RETURN +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* Until they use ELF or something that handles dwarf2 unwinds + and initialization stuff better. */ +#define DWARF2_UNWIND_INFO 0 + diff --git a/contrib/gcc/config/sparc/openbsd.h b/contrib/gcc/config/sparc/openbsd.h new file mode 100644 index 000000000000..19ece975e99e --- /dev/null +++ b/contrib/gcc/config/sparc/openbsd.h @@ -0,0 +1,68 @@ +/* Configuration file for sparc OpenBSD target. + Copyright (C) 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <sparc/sparc.h> + +/* Get generic OpenBSD definitions. */ +#define OBSD_OLD_GAS +#include <openbsd.h> + +/* Run-time target specifications. */ +#define CPP_PREDEFINES "-D__unix__ -D__sparc__ -D__OpenBSD__ -Asystem(unix) -Asystem(OpenBSD) -Acpu(sparc) -Amachine(sparc)" + +/* Layout of source language data types */ + +/* This must agree with <machine/ansi.h> */ +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 32 + +/* Specific options for DBX Output. */ + +/* This is BSD, so it wants DBX format. */ +#define DBX_DEBUGGING_INFO + +/* This is the char to use for continuation */ +#define DBX_CONTIN_CHAR '?' + +/* Stack & calling: aggregate returns. */ + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#undef DEFAULT_PCC_STRUCT_RETURN +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* Assembler format: exception region output. */ + +/* All configurations that don't use elf must be explicit about not using + dwarf unwind information. egcs doesn't try too hard to check internal + configuration files... */ +#define DWARF2_UNWIND_INFO 0 + +/* Default sparc.h does already define ASM_OUTPUT_MI_THUNK */ + diff --git a/contrib/gcc/config/sparc/pbd.h b/contrib/gcc/config/sparc/pbd.h new file mode 100644 index 000000000000..b70fdcb259b5 --- /dev/null +++ b/contrib/gcc/config/sparc/pbd.h @@ -0,0 +1,156 @@ +/* Definitions of target machine for GNU compiler, Citicorp/TTI Unicom PBD + version (using GAS and COFF (encapsulated is unacceptable) ) + Copyright (C) 1990, 1996 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/sparc.h" + +/* Names to predefine in the preprocessor for this target machine. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -DUnicomPBD -Dunix -D__GCC_NEW_VARARGS__ -Asystem(unix) -Acpu(sparc) -Amachine(sparc)" + +/* We want DBX format for use with gdb under COFF. */ + +#define DBX_DEBUGGING_INFO + +/* Generate calls to memcpy, memcmp and memset. */ + +#define TARGET_MEM_FUNCTIONS + +/* we use /lib/libp/lib* when profiling */ + +#undef LIB_SPEC +#define LIB_SPEC "%{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp} -lc" + + +/* Use crt1.o as a startup file and crtn.o as a closing file. */ +/* + * The loader directive file gcc.ifile defines how to merge the constructor + * sections into the data section. Also, since gas only puts out those + * sections in response to N_SETT stabs, and does not (yet) have a + * ".sections" directive, gcc.ifile also defines the list symbols + * __DTOR_LIST__ and __CTOR_LIST__. + * + * Finally, we must explicitly specify the file from libgcc.a that defines + * exit(), otherwise if the user specifies (for example) "-lc_s" on the + * command line, the wrong exit() will be used and global destructors will + * not get called . + */ + +#define STARTFILE_SPEC \ +"%{!r: gcc.ifile%s} %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} \ +%{!r:_exit.o%s}" + +#define ENDFILE_SPEC "crtn.o%s" + +/* cpp has to support a #sccs directive for the /usr/include files */ + +#define SCCS_DIRECTIVE + +/* LINK_SPEC is needed only for SunOS 4. */ + +#undef LINK_SPEC + +/* Although the gas we use can create .ctor and .dtor sections from N_SETT + stabs, it does not support section directives, so we need to have the loader + define the lists. + */ +#define CTOR_LISTS_DEFINED_EXTERNALLY + +/* similar to default, but allows for the table defined by ld with gcc.ifile. + nptrs is always 0. So we need to instead check that __DTOR_LIST__[1] != 0. + The old check is left in so that the same macro can be used if and when + a future version of gas does support section directives. */ + +#define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \ + if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0)) \ + for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); \ + for (i = nptrs; i >= 1; i--) \ + __DTOR_LIST__[i] (); } + +/* + * Here is an example gcc.ifile. I've tested it on PBD sparc + * systems. The NEXT(0x200000) works on just about all 386 and m68k systems, + * but can be reduced to any power of 2 that is >= NBPS (0x40000 on a pbd). + + SECTIONS { + .text BIND(0x41000200) BLOCK (0x200) : + { *(.init) *(.text) vfork = fork; *(.fini) } + + GROUP BIND( NEXT(0x200000) + ADDR(.text) + SIZEOF(.text)): + { .data : { __CTOR_LIST__ = . ; . += 4; *(.ctor) . += 4 ; + __DTOR_LIST__ = . ; . += 4; *(.dtor) . += 4 ; } + .bss : { } + } + } + */ + +/* The prefix to add to user-visible assembler symbols. */ + +#undef USER_LABEL_PREFIX +#define USER_LABEL_PREFIX "" + +/* fixes: */ +/* + * Internal labels are prefixed with a period. + */ + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL + +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf (LABEL, "*.%s%d", PREFIX, NUM) + + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) + +/* This is how to output an element of a case-vector that is relative. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ + fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL) + +/* This is how to output an element of a case-vector that is absolute. + (The 68000 does not use such vectors, + but we must define this macro anyway.) */ + +#undef ASM_OUTPUT_ADDR_VEC_ELT +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + fprintf (FILE, "\t.word .L%d\n", VALUE) + +/* This is needed for SunOS 4.0, and should not hurt for 3.2 + versions either. */ +#undef ASM_OUTPUT_SOURCE_LINE(file, line) +#define ASM_OUTPUT_SOURCE_LINE(file, line) \ + { static int sym_lineno = 1; \ + fprintf (file, ".stabn 68,0,%d,.LM%d\n.LM%d:\n", \ + line, sym_lineno, sym_lineno); \ + sym_lineno += 1; } + +#define ASM_INT_OP ".long " diff --git a/contrib/gcc/config/sparc/rtems.h b/contrib/gcc/config/sparc/rtems.h new file mode 100644 index 000000000000..1ab0a4216fd9 --- /dev/null +++ b/contrib/gcc/config/sparc/rtems.h @@ -0,0 +1,35 @@ +/* Definitions for rtems targeting a SPARC using a.out. + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Joel Sherrill (joel@OARcorp.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/aout.h" + +/* Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -D__GCC_NEW_VARARGS__ -Drtems -D__rtems__ \ + -Asystem(rtems) -Acpu(sparc) -Amachine(sparc)" + +/* Generate calls to memcpy, memcmp and memset. */ +#ifndef TARGET_MEM_FUNCTIONS +#define TARGET_MEM_FUNCTIONS +#endif + +/* end of sparc/rtems.h */ diff --git a/contrib/gcc/config/sparc/sol2-c1.asm b/contrib/gcc/config/sparc/sol2-c1.asm new file mode 100644 index 000000000000..894a8c34c084 --- /dev/null +++ b/contrib/gcc/config/sparc/sol2-c1.asm @@ -0,0 +1,110 @@ +! crt1.s for sparc & sparcv9 (SunOS 5) + +! Copyright (C) 1992 Free Software Foundation, Inc. +! Written By David Vinayak Henkel-Wallace, June 1992 +! +! This file is free software; you can redistribute it and/or modify it +! under the terms of the GNU General Public License as published by the +! Free Software Foundation; either version 2, or (at your option) any +! later version. +! +! In addition to the permissions in the GNU General Public License, the +! Free Software Foundation gives you unlimited permission to link the +! compiled version of this file with other programs, and to distribute +! those programs without any restriction coming from the use of this +! file. (The General Public License restrictions do apply in other +! respects; for example, they cover modification of the file, and +! distribution when not linked into another program.) +! +! This file is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! General Public License for more details. +! +! You should have received a copy of the GNU General Public License +! along with this program; see the file COPYING. If not, write to +! the Free Software Foundation, 59 Temple Place - Suite 330, +! Boston, MA 02111-1307, USA. +! +! As a special exception, if you link this library with files +! compiled with GCC to produce an executable, this does not cause +! the resulting executable to be covered by the GNU General Public License. +! This exception does not however invalidate any other reasons why +! the executable file might be covered by the GNU General Public License. +! + +! This file takes control of the process from the kernel, as specified +! in section 3 of the SVr4 ABI. +! This file is the first thing linked into any executable. + +#ifdef __sparcv9 +#define CPTRSIZE 8 +#define CPTRSHIFT 3 +#define STACK_BIAS 2047 +#define ldn ldx +#define stn stx +#define setn(s, scratch, dst) setx s, scratch, dst +#else +#define CPTRSIZE 4 +#define CPTRSHIFT 2 +#define STACK_BIAS 0 +#define ldn ld +#define stn st +#define setn(s, scratch, dst) set s, dst +#endif + + .section ".text" + .proc 022 + .global _start + +_start: + mov 0, %fp ! Mark bottom frame pointer + ldn [%sp + (16 * CPTRSIZE) + STACK_BIAS], %l0 ! argc + add %sp, (17 * CPTRSIZE) + STACK_BIAS, %l1 ! argv + + ! Leave some room for a call. Sun leaves 32 octets (to sit on + ! a cache line?) so we do too. +#ifdef __sparcv9 + sub %sp, 48, %sp +#else + sub %sp, 32, %sp +#endif + + ! %g1 may contain a function to be registered w/atexit + orcc %g0, %g1, %g0 +#ifdef __sparcv9 + be %xcc, .nope +#else + be .nope +#endif + mov %g1, %o0 + call atexit + nop +.nope: + ! Now make sure constructors and destructors are handled. + setn(_fini, %o1, %o0) + call atexit, 1 + nop + call _init, 0 + nop + + ! We ignore the auxiliary vector; there is no defined way to + ! access those data anyway. Instead, go straight to main: + mov %l0, %o0 ! argc + mov %l1, %o1 ! argv + ! Skip argc words past argv, to env: + sll %l0, CPTRSHIFT, %o2 + add %o2, CPTRSIZE, %o2 + add %l1, %o2, %o2 ! env + setn(_environ, %o4, %o3) + stn %o2, [%o3] ! *_environ + call main, 4 + nop + call exit, 0 + nop + call _exit, 0 + nop + ! We should never get here. + + .type _start,#function + .size _start,.-_start diff --git a/contrib/gcc/config/sparc/sol2-ci.asm b/contrib/gcc/config/sparc/sol2-ci.asm new file mode 100644 index 000000000000..3dc793c0c89c --- /dev/null +++ b/contrib/gcc/config/sparc/sol2-ci.asm @@ -0,0 +1,68 @@ +! crti.s for solaris 2.0. + +! Copyright (C) 1992 Free Software Foundation, Inc. +! Written By David Vinayak Henkel-Wallace, June 1992 +! +! This file is free software; you can redistribute it and/or modify it +! under the terms of the GNU General Public License as published by the +! Free Software Foundation; either version 2, or (at your option) any +! later version. +! +! In addition to the permissions in the GNU General Public License, the +! Free Software Foundation gives you unlimited permission to link the +! compiled version of this file with other programs, and to distribute +! those programs without any restriction coming from the use of this +! file. (The General Public License restrictions do apply in other +! respects; for example, they cover modification of the file, and +! distribution when not linked into another program.) +! +! This file is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! General Public License for more details. +! +! You should have received a copy of the GNU General Public License +! along with this program; see the file COPYING. If not, write to +! the Free Software Foundation, 59 Temple Place - Suite 330, +! Boston, MA 02111-1307, USA. +! +! As a special exception, if you link this library with files +! compiled with GCC to produce an executable, this does not cause +! the resulting executable to be covered by the GNU General Public License. +! This exception does not however invalidate any other reasons why +! the executable file might be covered by the GNU General Public License. +! + +! This file just make a stack frame for the contents of the .fini and +! .init sections. Users may put any desired instructions in those +! sections. + +! This file is linked in before the Values-Xx.o files and also before +! crtbegin, with which perhaps it should be merged. + + .file "crti.s" + + .section ".init" + .proc 022 + .global _init + .type _init,#function + .align 4 +_init: +#ifdef __sparcv9 + save %sp, -176, %sp +#else + save %sp, -96, %sp +#endif + + + .section ".fini" + .proc 022 + .global _fini + .type _fini,#function + .align 4 +_fini: +#ifdef __sparcv9 + save %sp, -176, %sp +#else + save %sp, -96, %sp +#endif diff --git a/contrib/gcc/config/sparc/sol2-cn.asm b/contrib/gcc/config/sparc/sol2-cn.asm new file mode 100644 index 000000000000..49e070f34f4c --- /dev/null +++ b/contrib/gcc/config/sparc/sol2-cn.asm @@ -0,0 +1,54 @@ +! crtn.s for solaris 2.0. + +! Copyright (C) 1992 Free Software Foundation, Inc. +! Written By David Vinayak Henkel-Wallace, June 1992 +! +! This file is free software; you can redistribute it and/or modify it +! under the terms of the GNU General Public License as published by the +! Free Software Foundation; either version 2, or (at your option) any +! later version. +! +! In addition to the permissions in the GNU General Public License, the +! Free Software Foundation gives you unlimited permission to link the +! compiled version of this file with other programs, and to distribute +! those programs without any restriction coming from the use of this +! file. (The General Public License restrictions do apply in other +! respects; for example, they cover modification of the file, and +! distribution when not linked into another program.) +! +! This file is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! General Public License for more details. +! +! You should have received a copy of the GNU General Public License +! along with this program; see the file COPYING. If not, write to +! the Free Software Foundation, 59 Temple Place - Suite 330, +! Boston, MA 02111-1307, USA. +! +! As a special exception, if you link this library with files +! compiled with GCC to produce an executable, this does not cause +! the resulting executable to be covered by the GNU General Public License. +! This exception does not however invalidate any other reasons why +! the executable file might be covered by the GNU General Public License. +! + +! This file just makes sure that the .fini and .init sections do in +! fact return. Users may put any desired instructions in those sections. +! This file is the last thing linked into any executable. + + .file "crtn.s" + + .section ".init" + .align 4 + + ret + restore + + .section ".fini" + .align 4 + + ret + restore + +! Th-th-th-that is all folks! diff --git a/contrib/gcc/config/sparc/sol2-g1.asm b/contrib/gcc/config/sparc/sol2-g1.asm new file mode 100644 index 000000000000..b9d878856f8d --- /dev/null +++ b/contrib/gcc/config/sparc/sol2-g1.asm @@ -0,0 +1,88 @@ +! gcrt1.s for solaris 2.0. + +! Copyright (C) 1992 Free Software Foundation, Inc. +! Written By David Vinayak Henkel-Wallace, June 1992 +! +! This file is free software; you can redistribute it and/or modify it +! under the terms of the GNU General Public License as published by the +! Free Software Foundation; either version 2, or (at your option) any +! later version. +! +! In addition to the permissions in the GNU General Public License, the +! Free Software Foundation gives you unlimited permission to link the +! compiled version of this file with other programs, and to distribute +! those programs without any restriction coming from the use of this +! file. (The General Public License restrictions do apply in other +! respects; for example, they cover modification of the file, and +! distribution when not linked into another program.) +! +! This file is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! General Public License for more details. +! +! You should have received a copy of the GNU General Public License +! along with this program; see the file COPYING. If not, write to +! the Free Software Foundation, 59 Temple Place - Suite 330, +! Boston, MA 02111-1307, USA. +! +! As a special exception, if you link this library with files +! compiled with GCC to produce an executable, this does not cause +! the resulting executable to be covered by the GNU General Public License. +! This exception does not however invalidate any other reasons why +! the executable file might be covered by the GNU General Public License. +! + +! This file takes control of the process from the kernel, as specified +! in section 3 of the SVr4 ABI. +! This file is the first thing linked into any executable. + + .section ".text" + .proc 022 + .global _start + +_start: + mov 0, %fp ! Mark bottom frame pointer + ld [%sp + 64], %l0 ! argc + add %sp, 68, %l1 ! argv + + ! Leave some room for a call. Sun leaves 32 octets (to sit on + ! a cache line?) so we do too. + sub %sp, 32, %sp + + ! %g1 may contain a function to be registered w/atexit + orcc %g0, %g1, %g0 + be .nope + mov %g1, %o0 + call atexit + nop +.nope: + ! Now make sure constructors and destructors are handled. + set _fini, %o0 + call atexit, 1 + nop + call _init, 0 + nop + + ! We ignore the auxiliary vector; there's no defined way to + ! access those data anyway. Instead, go straight to main: + mov %l0, %o0 ! argc + mov %l1, %o1 ! argv + set ___Argv, %o3 + st %o1, [%o3] ! *___Argv + ! Skip argc words past argv, to env: + sll %l0, 2, %o2 + add %o2, 4, %o2 + add %l1, %o2, %o2 ! env + set _environ, %o3 + st %o2, [%o3] ! *_environ + call main, 4 + nop + call exit, 0 + nop + call _exit, 0 + nop + ! We should never get here. + + .type _start,#function + .size _start,.-_start diff --git a/contrib/gcc/config/sparc/sol2-sld-64.h b/contrib/gcc/config/sparc/sol2-sld-64.h new file mode 100644 index 000000000000..c2518d8def0b --- /dev/null +++ b/contrib/gcc/config/sparc/sol2-sld-64.h @@ -0,0 +1,363 @@ +/* Definitions of target machine for GNU compiler, for 64-bit SPARC + running Solaris 2 using the system linker. */ + +#define SPARC_BI_ARCH + +#include "sparc/sol2.h" + +/* At least up through Solaris 2.6, + the system linker does not work with DWARF or DWARF2, + since it does not have working support for relocations + to unaligned data. */ + +#define LINKER_DOES_NOT_WORK_WITH_DWARF2 + +/* A 64 bit v9 compiler with stack-bias */ + +#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc +#undef TARGET_DEFAULT +#define TARGET_DEFAULT \ + (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ + \ + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) +#endif + +/* The default code model. */ +#undef SPARC_DEFAULT_CMODEL +#define SPARC_DEFAULT_CMODEL CM_MEDANY + +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 128 + +#undef ASM_CPU32_DEFAULT_SPEC +#define ASM_CPU32_DEFAULT_SPEC "" +#undef ASM_CPU64_DEFAULT_SPEC +#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9" + +#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 +#undef CPP_CPU64_DEFAULT_SPEC +#define CPP_CPU64_DEFAULT_SPEC "" +#undef ASM_CPU32_DEFAULT_SPEC +#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" +#endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc +#undef CPP_CPU64_DEFAULT_SPEC +#define CPP_CPU64_DEFAULT_SPEC "" +#undef ASM_CPU32_DEFAULT_SPEC +#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusa" +#undef ASM_CPU64_DEFAULT_SPEC +#define ASM_CPU64_DEFAULT_SPEC "-xarch=v9a" +#endif + +/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). + It's safe to pass -s always, even if -g is not used. */ +#undef ASM_SPEC +#define ASM_SPEC "\ +%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \ +%{fpic:-K PIC} %{fPIC:-K PIC} \ +%(asm_cpu)\ +" + +#if DEFAULT_ARCH32_P +#define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}" +#define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}" +#else +#define DEF_ARCH32_SPEC(__str) "%{m32:" __str "}" +#define DEF_ARCH64_SPEC(__str) "%{!m32:" __str "}" +#endif + +#undef CPP_CPU_SPEC +#define CPP_CPU_SPEC "\ +%{mcypress:} \ +%{msparclite:-D__sparclite__} \ +%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ +%{mv8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{msupersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ +%{mcpu=sparclite:-D__sparclite__} \ +%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ +%{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{mcpu=v9:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ +" + +#undef ASM_CPU_SPEC +#define ASM_CPU_SPEC "\ +%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC("-xarch=v9a") "} \ +%{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC("-xarch=v9") "} \ +%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}} \ +%{!mcpu*:%(asm_cpu_default)} \ +" + +#define STARTFILE_SPEC32 "\ +%{ansi:values-Xc.o%s} \ +%{!ansi: \ + %{traditional:values-Xt.o%s} \ + %{!traditional:values-Xa.o%s}}" + +#define STARTFILE_SPEC64 "\ +%{ansi:/usr/lib/sparcv9/values-Xc.o%s} \ +%{!ansi: \ + %{traditional:/usr/lib/sparcv9/values-Xt.o%s} \ + %{!traditional:/usr/lib/sparcv9/values-Xa.o%s}}" + +#ifdef SPARC_BI_ARCH + +#if DEFAULT_ARCH32_P +#define STARTFILE_ARCH_SPEC "\ +%{m32:" STARTFILE_SPEC32 "} \ +%{m64:" STARTFILE_SPEC64 "} \ +%{!m32:%{!m64:" STARTFILE_SPEC32 "}}" +#else +#define STARTFILE_ARCH_SPEC "\ +%{m32:" STARTFILE_SPEC32 "} \ +%{m64:" STARTFILE_SPEC64 "} \ +%{!m32:%{!m64:" STARTFILE_SPEC64 "}}" +#endif + +#else /* !SPARC_BI_ARCH */ + +/* In this case we define MD_STARTFILE_PREFIX to /usr/lib/sparcv9/ */ +#define STARTFILE_ARCH_SPEC STARTFILE_SPEC32 + +#endif /* !SPARC_BI_ARCH */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{!shared: \ + %{!symbolic: \ + %{p:mcrt1.o%s} \ + %{!p: \ + %{pg:gcrt1.o%s gmon.o%s} \ + %{!pg:crt1.o%s}}}} \ + crti.o%s" STARTFILE_ARCH_SPEC " \ + crtbegin.o%s" + +#ifdef SPARC_BI_ARCH + +#undef CPP_CPU_DEFAULT_SPEC +#define CPP_CPU_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? "\ +%{m64:" CPP_CPU64_DEFAULT_SPEC "} \ +%{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ +" : "\ +%{m32:" CPP_CPU32_DEFAULT_SPEC "} \ +%{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ +") + +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? "\ +%{m64:" ASM_CPU64_DEFAULT_SPEC "} \ +%{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ +" : "\ +%{m32:" ASM_CPU32_DEFAULT_SPEC "} \ +%{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ +") + +#undef CPP_ARCH32_SPEC +#define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \ +-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)" +#undef CPP_ARCH64_SPEC +#define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \ +-D__arch64__ -Acpu(sparc64) -Amachine(sparcv9) -D__sparcv9" + +#undef CPP_ARCH_SPEC +#define CPP_ARCH_SPEC "\ +%{m32:%(cpp_arch32)} \ +%{m64:%(cpp_arch64)} \ +%{!m32:%{!m64:%(cpp_arch_default)}} \ +" + +#undef ASM_ARCH_SPEC +#define ASM_ARCH_SPEC "" + +#undef ASM_ARCH32_SPEC +#define ASM_ARCH32_SPEC "" + +#undef ASM_ARCH64_SPEC +#define ASM_ARCH64_SPEC "" + +#undef ASM_ARCH_DEFAULT_SPEC +#define ASM_ARCH_DEFAULT_SPEC "" + +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "link_arch32", LINK_ARCH32_SPEC }, \ + { "link_arch64", LINK_ARCH64_SPEC }, \ + { "link_arch_default", LINK_ARCH_DEFAULT_SPEC }, \ + { "link_arch", LINK_ARCH_SPEC }, + +/* This should be the same as in svr4.h, except with -R added. */ +#define LINK_ARCH32_SPEC \ + "%{G:-G} \ + %{YP,*} \ + %{R*} \ + %{compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{pg:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{!p:%{!pg:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}}} \ + -R /usr/ucblib} \ + %{!compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{pg:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{!p:%{!pg:-Y P,/usr/ccs/lib:/usr/lib}}}}" + +#define LINK_ARCH64_SPEC \ + "%{mcmodel=medlow:-M /usr/lib/ld/sparcv9/map.below4G} \ + %{G:-G} \ + %{YP,*} \ + %{R*} \ + %{compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{!p:%{!pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/sparcv9}}} \ + -R /usr/ucblib} \ + %{!compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{pg:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{!p:%{!pg:-Y P,/usr/lib/sparcv9}}}}" + +#define LINK_ARCH_SPEC "\ +%{m32:%(link_arch32)} \ +%{m64:%(link_arch64)} \ +%{!m32:%{!m64:%(link_arch_default)}} \ +" + +#define LINK_ARCH_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? LINK_ARCH32_SPEC : LINK_ARCH64_SPEC) + +#undef LINK_SPEC +#define LINK_SPEC \ + "%{h*} %{v:-V} \ + %{b} %{Wl,*:%*} \ + %{static:-dn -Bstatic} \ + %{shared:-G -dy %{!mimpure-text:-z text}} \ + %{symbolic:-Bsymbolic -G -dy -z text} \ + %(link_arch) \ + %{Qy:} %{!Qn:-Qy}" + +#undef CC1_SPEC +#if DEFAULT_ARCH32_P +#define CC1_SPEC "\ +%{sun4:} %{target:} \ +%{mcypress:-mcpu=cypress} \ +%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ +%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ +%{m64:-mptr64 -mcpu=v9 -mstack-bias -mno-v8plus} \ +" +#else +#define CC1_SPEC "\ +%{sun4:} %{target:} \ +%{mcypress:-mcpu=cypress} \ +%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ +%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ +%{m32:-mptr32 -mcpu=cypress -mno-stack-bias} \ +%{mv8plus:-m32 -mptr32 -mcpu=cypress -mno-stack-bias} \ +" +#endif + +#if DEFAULT_ARCH32_P +#define MULTILIB_DEFAULTS { "m32" } +#else +#define MULTILIB_DEFAULTS { "m64" } +#endif + +#else /* !SPARC_BI_ARCH */ + +/* + * This should be the same as in sol2-sld.h, except with "/sparcv9" + * appended to the paths and /usr/ccs/lib is no longer necessary + */ +#undef LINK_SPEC +#define LINK_SPEC \ + "%{h*} %{v:-V} \ + %{b} %{Wl,*:%*} \ + %{static:-dn -Bstatic} \ + %{shared:-G -dy %{!mimpure-text:-z text}} \ + %{symbolic:-Bsymbolic -G -dy -z text} \ + %{mcmodel=medlow:-M /usr/lib/ld/sparcv9/map.below4G} \ + %{G:-G} \ + %{YP,*} \ + %{R*} \ + %{compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{!p:%{!pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/sparcv9}}} \ + -R /usr/ucblib} \ + %{!compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{pg:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{!p:%{!pg:-Y P,/usr/lib/sparcv9}}}} \ + %{Qy:} %{!Qn:-Qy}" + +#undef MD_STARTFILE_PREFIX +#define MD_STARTFILE_PREFIX "/usr/lib/sparcv9/" + +#endif /* ! SPARC_BI_ARCH */ + +/* + * Attempt to turn on access permissions for the stack. + * + * This code must be defined when compiling gcc but not when compiling + * libgcc2.a, unless we're generating code for 64 bits SPARC + * + * _SC_STACK_PROT is only defined for post 2.6, but we want this code + * to run always. 2.6 can change the stack protection but has no way to + * query it. + * + */ + +#define TRANSFER_FROM_TRAMPOLINE \ +static int need_enable_exec_stack; \ + \ +static void check_enabling(void) __attribute__ ((constructor)); \ +static void check_enabling(void) \ +{ \ + extern long sysconf(int); \ + \ + int prot = (int) sysconf(515 /*_SC_STACK_PROT */); \ + if (prot != 7) \ + need_enable_exec_stack = 1; \ +} \ + \ +void \ +__enable_execute_stack (addr) \ + void *addr; \ +{ \ + if (!need_enable_exec_stack) \ + return; \ + else { \ + long size = getpagesize (); \ + long mask = ~(size-1); \ + char *page = (char *) (((long) addr) & mask); \ + char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \ + \ + /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ \ + if (mprotect (page, end - page, 7) < 0) \ + perror ("mprotect of trampoline code"); \ + } \ +} + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#undef ASM_OUTPUT_CONSTRUCTOR +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t ", TARGET_ARCH64 ? ASM_LONGLONG : INT_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#undef ASM_OUTPUT_DESTRUCTOR +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t ", TARGET_ARCH64 ? ASM_LONGLONG : INT_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + diff --git a/contrib/gcc/config/sparc/sol2-sld.h b/contrib/gcc/config/sparc/sol2-sld.h new file mode 100644 index 000000000000..a82498791b90 --- /dev/null +++ b/contrib/gcc/config/sparc/sol2-sld.h @@ -0,0 +1,11 @@ +/* Definitions of target machine for GNU compiler, for SPARC running Solaris 2 + using the system linker. */ + +#include "sparc/sol2.h" + +/* At least up through Solaris 2.6, + the system linker does not work with DWARF or DWARF2, + since it does not have working support for relocations + to unaligned data. */ + +#define LINKER_DOES_NOT_WORK_WITH_DWARF2 diff --git a/contrib/gcc/config/sparc/sol2.h b/contrib/gcc/config/sparc/sol2.h new file mode 100644 index 000000000000..9274f9d9108e --- /dev/null +++ b/contrib/gcc/config/sparc/sol2.h @@ -0,0 +1,236 @@ +/* Definitions of target machine for GNU compiler, for SPARC running Solaris 2 + Copyright 1992, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by Ron Guilmette (rfg@netcom.com). + Additional changes by David V. Henkel-Wallace (gumby@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Supposedly the same as vanilla sparc svr4, except for the stuff below: */ +#include "sparc/sysv4.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES \ +"-Dsparc -Dsun -Dunix -D__svr4__ -D__SVR4 \ +-Asystem(unix) -Asystem(svr4)" + +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC "\ +%{pthreads:-D_REENTRANT -D_PTHREADS} \ +%{!pthreads:%{threads:-D_REENTRANT -D_SOLARIS_THREADS}} \ +%{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude} \ +" + +/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). + It's safe to pass -s always, even if -g is not used. */ +#undef ASM_SPEC +#define ASM_SPEC "\ +%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \ +%{fpic:-K PIC} %{fPIC:-K PIC} \ +%(asm_cpu) \ +" + +/* This is here rather than in sparc.h because it's not known what + other assemblers will accept. */ +#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plus" +#endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusa" +#endif +#undef ASM_CPU_SPEC +#define ASM_CPU_SPEC "\ +%{mcpu=v8plus:-xarch=v8plus} \ +%{mcpu=ultrasparc:-xarch=v8plusa} \ +%{!mcpu*:%(asm_cpu_default)} \ +" + +/* However it appears that Solaris 2.0 uses the same reg numbering as + the old BSD-style system did. */ + +#undef DBX_REGISTER_NUMBER +/* Same as sparc.h */ +#define DBX_REGISTER_NUMBER(REGNO) \ + (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO) + +/* We use stabs-in-elf for debugging, because that is what the native + toolchain uses. */ +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +/* The Solaris 2 assembler uses .skip, not .zero, so put this back. */ +#undef ASM_OUTPUT_SKIP +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.skip %u\n", (SIZE)) + +/* Use .uahalf/.uaword so packed structure members don't generate + assembler errors when using the native assembler. */ +#undef ASM_SHORT +#define ASM_SHORT ".uahalf" +#undef ASM_LONG +#define ASM_LONG ".uaword" + +/* This is how to output a definition of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".L%s%d:\n", PREFIX, NUM) + +/* This is how to output a reference to an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABELREF +#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ + fprintf (FILE, ".L%s%d", PREFIX, NUM) + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf ((LABEL), "*.L%s%ld", (PREFIX), (long)(NUM)) + + +/* We don't use the standard svr4 STARTFILE_SPEC because it's wrong for us. + We don't use the standard LIB_SPEC only because we don't yet support c++ */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{!shared: \ + %{!symbolic: \ + %{p:mcrt1.o%s} \ + %{!p: \ + %{pg:gcrt1.o%s gmon.o%s} \ + %{!pg:crt1.o%s}}}} \ + crti.o%s \ + %{ansi:values-Xc.o%s} \ + %{!ansi: \ + %{traditional:values-Xt.o%s} \ + %{!traditional:values-Xa.o%s}} \ + crtbegin.o%s" + +/* ??? Note: in order for -compat-bsd to work fully, + we must somehow arrange to fixincludes /usr/ucbinclude + and put the result in $(libsubdir)/ucbinclude. */ + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{compat-bsd:-lucb -lsocket -lnsl -lelf -laio} \ + %{!shared:\ + %{!symbolic:\ + %{pthreads:-lpthread} \ + %{!pthreads:%{threads:-lthread}} \ + -lc}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend.o%s crtn.o%s" + +/* This should be the same as in svr4.h, except with -R added. */ +#undef LINK_SPEC +#define LINK_SPEC \ + "%{h*} %{v:-V} \ + %{b} %{Wl,*:%*} \ + %{static:-dn -Bstatic} \ + %{shared:-G -dy %{!mimpure-text:-z text}} \ + %{symbolic:-Bsymbolic -G -dy -z text} \ + %{G:-G} \ + %{YP,*} \ + %{R*} \ + %{compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{pg:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{!p:%{!pg:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}}} \ + -R /usr/ucblib} \ + %{!compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{pg:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{!p:%{!pg:-Y P,/usr/ccs/lib:/usr/lib}}}} \ + %{Qy:} %{!Qn:-Qy}" + +/* This defines which switch letters take arguments. + It is as in svr4.h but with -R added. */ + +#undef SWITCH_TAKES_ARG +#define SWITCH_TAKES_ARG(CHAR) \ + (DEFAULT_SWITCH_TAKES_ARG(CHAR) \ + || (CHAR) == 'R' \ + || (CHAR) == 'h' \ + || (CHAR) == 'x' \ + || (CHAR) == 'z') + +/* ??? This does not work in SunOS 4.x, so it is not enabled in sparc.h. + Instead, it is enabled here, because it does work under Solaris. */ +/* Define for support of TFmode long double and REAL_ARITHMETIC. + Sparc ABI says that long double is 4 words. */ +#define LONG_DOUBLE_TYPE_SIZE 128 + +/* But indicate that it isn't supported by the hardware. */ +#define WIDEST_HARDWARE_FP_SIZE 64 + +#define STDC_0_IN_SYSTEM_HEADERS + +#define MULDI3_LIBCALL "__mul64" +#define DIVDI3_LIBCALL "__div64" +#define UDIVDI3_LIBCALL "__udiv64" +#define MODDI3_LIBCALL "__rem64" +#define UMODDI3_LIBCALL "__urem64" + +#undef INIT_SUBTARGET_OPTABS +#define INIT_SUBTARGET_OPTABS \ + fixsfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, \ + TARGET_ARCH64 ? "__ftol" : "__ftoll"); \ + fixunssfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, \ + TARGET_ARCH64 ? "__ftoul" : "__ftoull"); \ + fixdfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, \ + TARGET_ARCH64 ? "__dtol" : "__dtoll"); \ + fixunsdfdi_libfunc = gen_rtx_SYMBOL_REF (Pmode, \ + TARGET_ARCH64 ? "__dtoul" : "__dtoull") + +/* No weird SPARC variants on Solaris */ +#undef TARGET_LIVE_G0 +#define TARGET_LIVE_G0 0 +#undef TARGET_BROKEN_SAVERESTORE +#define TARGET_BROKEN_SAVERESTORE 0 + +/* Solaris allows 64 bit out and global registers in 32 bit mode. + sparc_override_options will disable V8+ if not generating V9 code. */ +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_V8PLUS) + +/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special + traps available which can get and set the condition codes + reliably. */ +#undef MACHINE_STATE_SAVE +#define MACHINE_STATE_SAVE(ID) \ + unsigned long int ms_flags, ms_saveret; \ + asm volatile("ta 0x20\n\t" \ + "mov %%g1, %0\n\t" \ + "mov %%g2, %1\n\t" \ + : "=r" (ms_flags), "=r" (ms_saveret)); + +#undef MACHINE_STATE_RESTORE +#define MACHINE_STATE_RESTORE(ID) \ + asm volatile("mov %0, %%g1\n\t" \ + "mov %1, %%g2\n\t" \ + "ta 0x21\n\t" \ + : /* no outputs */ \ + : "r" (ms_flags), "r" (ms_saveret)); + diff --git a/contrib/gcc/config/sparc/sp64-aout.h b/contrib/gcc/config/sparc/sp64-aout.h new file mode 100644 index 000000000000..e3056dfbc54e --- /dev/null +++ b/contrib/gcc/config/sparc/sp64-aout.h @@ -0,0 +1,38 @@ +/* Definitions of target machine for GNU compiler, for SPARC64, a.out. + Copyright (C) 1994, 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by Doug Evans, dje@cygnus.com. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/sparc.h" +#include "aoutos.h" + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (sparc64-aout)") + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT \ + (MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \ + + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS) + +/* The only code model supported is Medium/Low. */ +#undef SPARC_DEFAULT_CMODEL +#define SPARC_DEFAULT_CMODEL CM_MEDLOW + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -Acpu(sparc) -Amachine(sparc)" diff --git a/contrib/gcc/config/sparc/sp64-elf.h b/contrib/gcc/config/sparc/sp64-elf.h new file mode 100644 index 000000000000..4fd81c55c470 --- /dev/null +++ b/contrib/gcc/config/sparc/sp64-elf.h @@ -0,0 +1,158 @@ +/* Definitions of target machine for GNU compiler, for SPARC64, ELF. + Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by Doug Evans, dje@cygnus.com. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* ??? We're taking the scheme of including another file and then overriding + the values we don't like a bit too far here. The alternative is to more or + less duplicate all of svr4.h, sparc/sysv4.h, and sparc/sol2.h here + (suitably cleaned up). */ + +#include "sparc/sol2.h" + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (sparc64-elf)") + +/* A 64 bit v9 compiler in a Medium/Anywhere code model environment. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT \ +(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \ + + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS) + +#undef SPARC_DEFAULT_CMODEL +#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -D__ELF__ -Acpu(sparc) -Amachine(sparc)" + +/* __svr4__ is used by the C library (FIXME) */ +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC "-D__svr4__" + +#undef MD_EXEC_PREFIX +#undef MD_STARTFILE_PREFIX + +#undef ASM_SPEC +#define ASM_SPEC "\ +%{v:-V} -s %{fpic:-K PIC} %{fPIC:-K PIC} \ +%{mlittle-endian:-EL} \ +%(asm_cpu) %(asm_arch) \ +" + +/* This is taken from sol2.h. */ +#undef LINK_SPEC +#define LINK_SPEC "\ +%{v:-V} \ +%{mlittle-endian:-EL} \ +" + +/* We need something a little simpler for the embedded environment. + Profiling doesn't really work yet so we just copy the default. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "\ +%{!shared:%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}} \ +crtbegin.o%s \ +" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend.o%s" + +/* Use the default (for now). */ +#undef LIB_SPEC + +/* V9 chips can handle either endianness. */ +#undef SUBTARGET_SWITCHES +#define SUBTARGET_SWITCHES \ +{"big-endian", -MASK_LITTLE_ENDIAN, "Generate code for big endian" }, \ +{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" }, + +#undef BYTES_BIG_ENDIAN +#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) + +#undef WORDS_BIG_ENDIAN +#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) + +/* ??? This should be 32 bits for v9 but what can we do? */ +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 + +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 128 + +/* The medium/anywhere code model practically requires us to put jump tables + in the text section as gcc is unable to distinguish LABEL_REF's of jump + tables from other label refs (when we need to). */ +/* But we now defer the tables to the end of the function, so we make + this 0 to not confuse the branch shortening code. */ +#undef JUMP_TABLES_IN_TEXT_SECTION +#define JUMP_TABLES_IN_TEXT_SECTION 0 + +/* System V Release 4 uses DWARF debugging info. + GDB doesn't support 64 bit stabs yet and the desired debug format is DWARF + anyway so it is the default. */ + +#define DWARF_DEBUGGING_INFO +#define DWARF2_DEBUGGING_INFO +#define DBX_DEBUGGING_INFO + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + +/* Stabs doesn't use this, and it confuses a simulator. */ +/* ??? Need to see what DWARF needs, if anything. */ +#undef ASM_IDENTIFY_GCC +#define ASM_IDENTIFY_GCC(FILE) + +/* Define the names of various pseudo-ops used by the Sparc/svr4 assembler. + ??? If ints are 64 bits then UNALIGNED_INT_ASM_OP (defined elsewhere) is + misnamed. These should all refer to explicit sizes (half/word/xword?), + anything other than short/int/long/etc. */ + +#define UNALIGNED_LONGLONG_ASM_OP ".uaxword" + +/* DWARF stuff. */ + +#define ASM_OUTPUT_DWARF_ADDR(FILE, LABEL) \ +do { \ + fprintf ((FILE), "\t%s\t", UNALIGNED_LONGLONG_ASM_OP); \ + assemble_name ((FILE), (LABEL)); \ + fprintf ((FILE), "\n"); \ +} while (0) + +#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, RTX) \ +do { \ + fprintf ((FILE), "\t%s\t", UNALIGNED_LONGLONG_ASM_OP); \ + output_addr_const ((FILE), (RTX)); \ + fputc ('\n', (FILE)); \ +} while (0) + +#define ASM_OUTPUT_DWARF2_ADDR_CONST(FILE, ADDR) \ + fprintf ((FILE), "\t%s\t%s", UNALIGNED_LONGLONG_ASM_OP, (ADDR)) + +/* ??? Not sure if this should be 4 or 8 bytes. 4 works for now. */ +#define ASM_OUTPUT_DWARF_REF(FILE, LABEL) \ +do { \ + fprintf ((FILE), "\t%s\t", UNALIGNED_INT_ASM_OP); \ + assemble_name ((FILE), (LABEL)); \ + fprintf ((FILE), "\n"); \ +} while (0) diff --git a/contrib/gcc/config/sparc/sparc.c b/contrib/gcc/config/sparc/sparc.c new file mode 100644 index 000000000000..45862a77bc73 --- /dev/null +++ b/contrib/gcc/config/sparc/sparc.c @@ -0,0 +1,7843 @@ +/* Subroutines for insn-output.c for Sun SPARC. + Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com) + 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, + at Cygnus Support. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "config.h" +#include "system.h" +#include "tree.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" +#include "flags.h" +#include "expr.h" +#include "recog.h" +#include "toplev.h" + +/* 1 if the caller has placed an "unimp" insn immediately after the call. + This is used in v8 code when calling a function that returns a structure. + v9 doesn't have this. Be careful to have this test be the same as that + used on the call. */ + +#define SKIP_CALLERS_UNIMP_P \ +(!TARGET_ARCH64 && current_function_returns_struct \ + && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ + && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ + == INTEGER_CST)) + +/* Global variables for machine-dependent things. */ + +/* Size of frame. Need to know this to emit return insns from leaf procedures. + ACTUAL_FSIZE is set by compute_frame_size() which is called during the + reload pass. This is important as the value is later used in insn + scheduling (to see what can go in a delay slot). + APPARENT_FSIZE is the size of the stack less the register save area and less + the outgoing argument area. It is used when saving call preserved regs. */ +static int apparent_fsize; +static int actual_fsize; + +/* Save the operands last given to a compare for use when we + generate a scc or bcc insn. */ + +rtx sparc_compare_op0, sparc_compare_op1; + +/* We may need an epilogue if we spill too many registers. + If this is non-zero, then we branch here for the epilogue. */ +static rtx leaf_label; + +#ifdef LEAF_REGISTERS + +/* Vector to say how input registers are mapped to output + registers. FRAME_POINTER_REGNUM cannot be remapped by + this function to eliminate it. You must use -fomit-frame-pointer + to get that. */ +char leaf_reg_remap[] = +{ 0, 1, 2, 3, 4, 5, 6, 7, + -1, -1, -1, -1, -1, -1, 14, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + 8, 9, 10, 11, 12, 13, -1, 15, + + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100}; + +#endif + +/* Name of where we pretend to think the frame pointer points. + Normally, this is "%fp", but if we are in a leaf procedure, + this is "%sp+something". We record "something" separately as it may be + too big for reg+constant addressing. */ + +static const char *frame_base_name; +static int frame_base_offset; + +static rtx pic_setup_code PROTO((void)); +static void sparc_init_modes PROTO((void)); +static int save_regs PROTO((FILE *, int, int, const char *, + int, int, int)); +static int restore_regs PROTO((FILE *, int, int, const char *, int, int)); +static void build_big_number PROTO((FILE *, int, const char *)); +static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *, + enum machine_mode, tree, int, int, + int *, int *)); + +static int supersparc_adjust_cost PROTO((rtx, rtx, rtx, int)); +static int hypersparc_adjust_cost PROTO((rtx, rtx, rtx, int)); +static int ultrasparc_adjust_cost PROTO((rtx, rtx, rtx, int)); + +static void sparc_output_addr_vec PROTO((rtx)); +static void sparc_output_addr_diff_vec PROTO((rtx)); +static void sparc_output_deferred_case_vectors PROTO((void)); + + +#ifdef DWARF2_DEBUGGING_INFO +extern char *dwarf2out_cfi_label (); +#endif + +/* Option handling. */ + +/* Code model option as passed by user. */ +const char *sparc_cmodel_string; +/* Parsed value. */ +enum cmodel sparc_cmodel; + +/* Record alignment options as passed by user. */ +const char *sparc_align_loops_string; +const char *sparc_align_jumps_string; +const char *sparc_align_funcs_string; + +/* Parsed values, as a power of two. */ +int sparc_align_loops; +int sparc_align_jumps; +int sparc_align_funcs; + +struct sparc_cpu_select sparc_select[] = +{ + /* switch name, tune arch */ + { (char *)0, "default", 1, 1 }, + { (char *)0, "-mcpu=", 1, 1 }, + { (char *)0, "-mtune=", 1, 0 }, + { 0, 0, 0, 0 } +}; + +/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ +enum processor_type sparc_cpu; + +/* Validate and override various options, and do some machine dependent + initialization. */ + +void +sparc_override_options () +{ + static struct code_model { + const char *name; + int value; + } cmodels[] = { + { "32", CM_32 }, + { "medlow", CM_MEDLOW }, + { "medmid", CM_MEDMID }, + { "medany", CM_MEDANY }, + { "embmedany", CM_EMBMEDANY }, + { 0, 0 } + }; + struct code_model *cmodel; + /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ + static struct cpu_default { + int cpu; + const char *name; + } cpu_default[] = { + /* There must be one entry here for each TARGET_CPU value. */ + { TARGET_CPU_sparc, "cypress" }, + { TARGET_CPU_sparclet, "tsc701" }, + { TARGET_CPU_sparclite, "f930" }, + { TARGET_CPU_v8, "v8" }, + { TARGET_CPU_hypersparc, "hypersparc" }, + { TARGET_CPU_sparclite86x, "sparclite86x" }, + { TARGET_CPU_supersparc, "supersparc" }, + { TARGET_CPU_v9, "v9" }, + { TARGET_CPU_ultrasparc, "ultrasparc" }, + { 0, 0 } + }; + struct cpu_default *def; + /* Table of values for -m{cpu,tune}=. */ + static struct cpu_table { + const char *name; + enum processor_type processor; + int disable; + int enable; + } cpu_table[] = { + { "v7", PROCESSOR_V7, MASK_ISA, 0 }, + { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, + { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, + /* TI TMS390Z55 supersparc */ + { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, + { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, + /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. + The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ + { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, + { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, + { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, + { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, MASK_V8 }, + { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, + /* TEMIC sparclet */ + { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, + { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, + /* TI ultrasparc */ + { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 }, + { 0, 0, 0, 0 } + }; + struct cpu_table *cpu; + struct sparc_cpu_select *sel; + int fpu; + +#ifndef SPARC_BI_ARCH + /* Check for unsupported architecture size. */ + if (! TARGET_64BIT != DEFAULT_ARCH32_P) + { + error ("%s is not supported by this configuration", + DEFAULT_ARCH32_P ? "-m64" : "-m32"); + } +#endif + + /* At the moment we don't allow different pointer size and architecture */ + if (! TARGET_64BIT != ! TARGET_PTR64) + { + error ("-mptr%d not allowed on -m%d", + TARGET_PTR64 ? 64 : 32, TARGET_64BIT ? 64 : 32); + if (TARGET_64BIT) + target_flags |= MASK_PTR64; + else + target_flags &= ~MASK_PTR64; + } + + /* Code model selection. */ + sparc_cmodel = SPARC_DEFAULT_CMODEL; + +#ifdef SPARC_BI_ARCH + if (TARGET_ARCH32) + sparc_cmodel = CM_32; +#endif + + if (sparc_cmodel_string != NULL) + { + if (TARGET_ARCH64) + { + for (cmodel = &cmodels[0]; cmodel->name; cmodel++) + if (strcmp (sparc_cmodel_string, cmodel->name) == 0) + break; + if (cmodel->name == NULL) + error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); + else + sparc_cmodel = cmodel->value; + } + else + error ("-mcmodel= is not supported on 32 bit systems"); + } + + fpu = TARGET_FPU; /* save current -mfpu status */ + + /* Set the default CPU. */ + for (def = &cpu_default[0]; def->name; ++def) + if (def->cpu == TARGET_CPU_DEFAULT) + break; + if (! def->name) + abort (); + sparc_select[0].string = def->name; + + for (sel = &sparc_select[0]; sel->name; ++sel) + { + if (sel->string) + { + for (cpu = &cpu_table[0]; cpu->name; ++cpu) + if (! strcmp (sel->string, cpu->name)) + { + if (sel->set_tune_p) + sparc_cpu = cpu->processor; + + if (sel->set_arch_p) + { + target_flags &= ~cpu->disable; + target_flags |= cpu->enable; + } + break; + } + + if (! cpu->name) + error ("bad value (%s) for %s switch", sel->string, sel->name); + } + } + + /* If -mfpu or -mno-fpu was explicitly used, don't override with + the processor default. */ + if (TARGET_FPU_SET) + target_flags = (target_flags & ~MASK_FPU) | fpu; + + /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ + if (TARGET_V9 && TARGET_ARCH32) + target_flags |= MASK_DEPRECATED_V8_INSNS; + + /* V8PLUS requires V9, makes no sense in 64 bit mode. */ + if (! TARGET_V9 || TARGET_ARCH64) + target_flags &= ~MASK_V8PLUS; + + /* Don't use stack biasing in 32 bit mode. */ + if (TARGET_ARCH32) + target_flags &= ~MASK_STACK_BIAS; + + /* Don't allow -mvis if FPU is disabled. */ + if (! TARGET_FPU) + target_flags &= ~MASK_VIS; + + /* Validate -malign-loops= value, or provide default. */ + if (sparc_align_loops_string) + { + sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string)); + if (sparc_align_loops < 2 || sparc_align_loops > 7) + fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two", + sparc_align_loops_string); + } + else + { + /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if + its 0. This sounds a bit kludgey. */ + sparc_align_loops = 0; + } + + /* Validate -malign-jumps= value, or provide default. */ + if (sparc_align_jumps_string) + { + sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string)); + if (sparc_align_jumps < 2 || sparc_align_loops > 7) + fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two", + sparc_align_jumps_string); + } + else + { + /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if + its 0. This sounds a bit kludgey. */ + sparc_align_jumps = 0; + } + + /* Validate -malign-functions= value, or provide default. */ + if (sparc_align_funcs_string) + { + sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string)); + if (sparc_align_funcs < 2 || sparc_align_loops > 7) + fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two", + sparc_align_funcs_string); + } + else + sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS; + + /* Validate PCC_STRUCT_RETURN. */ + if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) + flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); + + /* Do various machine dependent initializations. */ + sparc_init_modes (); + + if ((profile_flag || profile_block_flag) + && sparc_cmodel != CM_MEDLOW) + { + error ("profiling does not support code models other than medlow"); + } +} + +/* Miscellaneous utilities. */ + +/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move + or branch on register contents instructions. */ + +int +v9_regcmp_p (code) + enum rtx_code code; +{ + return (code == EQ || code == NE || code == GE || code == LT + || code == LE || code == GT); +} + + +/* Operand constraints. */ + +/* Return non-zero only if OP is a register of mode MODE, + or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because + %g0 may contain anything. */ + +int +reg_or_0_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (register_operand (op, mode)) + return 1; + if (TARGET_LIVE_G0) + return 0; + if (op == const0_rtx) + return 1; + if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_HIGH (op) == 0 + && CONST_DOUBLE_LOW (op) == 0) + return 1; + if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT + && GET_CODE (op) == CONST_DOUBLE + && fp_zero_operand (op)) + return 1; + return 0; +} + +/* Nonzero if OP is a floating point value with value 0.0. */ + +int +fp_zero_operand (op) + rtx op; +{ + REAL_VALUE_TYPE r; + + REAL_VALUE_FROM_CONST_DOUBLE (r, op); + return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r)); +} + +/* Nonzero if OP is an integer register. */ + +int +intreg_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (register_operand (op, SImode) + || (TARGET_ARCH64 && register_operand (op, DImode))); +} + +/* Nonzero if OP is a floating point condition code register. */ + +int +fcc_reg_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + /* This can happen when recog is called from combine. Op may be a MEM. + Fail instead of calling abort in this case. */ + if (GET_CODE (op) != REG) + return 0; + + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + if (mode == VOIDmode + && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) + return 0; + +#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ + if (reg_renumber == 0) + return REGNO (op) >= FIRST_PSEUDO_REGISTER; + return REGNO_OK_FOR_CCFP_P (REGNO (op)); +#else + return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; +#endif +} + +/* Nonzero if OP is an integer or floating point condition code register. */ + +int +icc_or_fcc_reg_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) + { + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + if (mode == VOIDmode + && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) + return 0; + return 1; + } + + return fcc_reg_operand (op, mode); +} + +/* Nonzero if OP can appear as the dest of a RESTORE insn. */ +int +restore_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (GET_CODE (op) == REG && GET_MODE (op) == mode + && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); +} + +/* Call insn on SPARC can take a PC-relative constant address, or any regular + memory address. */ + +int +call_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) != MEM) + abort (); + op = XEXP (op, 0); + return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); +} + +int +call_operand_address (op, mode) + rtx op; + enum machine_mode mode; +{ + return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); +} + +/* Returns 1 if OP is either a symbol reference or a sum of a symbol + reference and a constant. */ + +int +symbolic_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case SYMBOL_REF: + case LABEL_REF: + return 1; + + case CONST: + op = XEXP (op, 0); + return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF + || GET_CODE (XEXP (op, 0)) == LABEL_REF) + && GET_CODE (XEXP (op, 1)) == CONST_INT); + + /* ??? This clause seems to be irrelevant. */ + case CONST_DOUBLE: + return GET_MODE (op) == mode; + + default: + return 0; + } +} + +/* Return truth value of statement that OP is a symbolic memory + operand of mode MODE. */ + +int +symbolic_memory_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + if (GET_CODE (op) != MEM) + return 0; + op = XEXP (op, 0); + return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST + || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); +} + +/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ + +int +label_ref_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) != LABEL_REF) + return 0; + if (GET_MODE (op) != mode) + return 0; + return 1; +} + +/* Return 1 if the operand is an argument used in generating pic references + in either the medium/low or medium/anywhere code models of sparc64. */ + +int +sp64_medium_pic_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + /* Check for (const (minus (symbol_ref:GOT) + (const (minus (label) (pc))))). */ + if (GET_CODE (op) != CONST) + return 0; + op = XEXP (op, 0); + if (GET_CODE (op) != MINUS) + return 0; + if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) + return 0; + /* ??? Ensure symbol is GOT. */ + if (GET_CODE (XEXP (op, 1)) != CONST) + return 0; + if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) + return 0; + return 1; +} + +/* Return 1 if the operand is a data segment reference. This includes + the readonly data segment, or in other words anything but the text segment. + This is needed in the medium/anywhere code model on v9. These values + are accessed with EMBMEDANY_BASE_REG. */ + +int +data_segment_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + switch (GET_CODE (op)) + { + case SYMBOL_REF : + return ! SYMBOL_REF_FLAG (op); + case PLUS : + /* Assume canonical format of symbol + constant. + Fall through. */ + case CONST : + return data_segment_operand (XEXP (op, 0)); + default : + return 0; + } +} + +/* Return 1 if the operand is a text segment reference. + This is needed in the medium/anywhere code model on v9. */ + +int +text_segment_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + switch (GET_CODE (op)) + { + case LABEL_REF : + return 1; + case SYMBOL_REF : + return SYMBOL_REF_FLAG (op); + case PLUS : + /* Assume canonical format of symbol + constant. + Fall through. */ + case CONST : + return text_segment_operand (XEXP (op, 0)); + default : + return 0; + } +} + +/* Return 1 if the operand is either a register or a memory operand that is + not symbolic. */ + +int +reg_or_nonsymb_mem_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (register_operand (op, mode)) + return 1; + + if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) + return 1; + + return 0; +} + +int +splittable_symbolic_memory_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) != MEM) + return 0; + if (! symbolic_operand (XEXP (op, 0), Pmode)) + return 0; + return 1; +} + +int +splittable_immediate_memory_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) != MEM) + return 0; + if (! immediate_operand (XEXP (op, 0), Pmode)) + return 0; + return 1; +} + +/* Return truth value of whether OP is EQ or NE. */ + +int +eq_or_neq (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (GET_CODE (op) == EQ || GET_CODE (op) == NE); +} + +/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, + or LTU for non-floating-point. We handle those specially. */ + +int +normal_comp_operator (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + enum rtx_code code = GET_CODE (op); + + if (GET_RTX_CLASS (code) != '<') + return 0; + + if (GET_MODE (XEXP (op, 0)) == CCFPmode + || GET_MODE (XEXP (op, 0)) == CCFPEmode) + return 1; + + return (code != NE && code != EQ && code != GEU && code != LTU); +} + +/* Return 1 if this is a comparison operator. This allows the use of + MATCH_OPERATOR to recognize all the branch insns. */ + +int +noov_compare_op (op, mode) + register rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + enum rtx_code code = GET_CODE (op); + + if (GET_RTX_CLASS (code) != '<') + return 0; + + if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) + /* These are the only branches which work with CC_NOOVmode. */ + return (code == EQ || code == NE || code == GE || code == LT); + return 1; +} + +/* Nonzero if OP is a comparison operator suitable for use in v9 + conditional move or branch on register contents instructions. */ + +int +v9_regcmp_op (op, mode) + register rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + enum rtx_code code = GET_CODE (op); + + if (GET_RTX_CLASS (code) != '<') + return 0; + + return v9_regcmp_p (code); +} + +/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ + +int +extend_op (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; +} + +/* Return nonzero if OP is an operator of mode MODE which can set + the condition codes explicitly. We do not include PLUS and MINUS + because these require CC_NOOVmode, which we handle explicitly. */ + +int +cc_arithop (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) == AND + || GET_CODE (op) == IOR + || GET_CODE (op) == XOR) + return 1; + + return 0; +} + +/* Return nonzero if OP is an operator of mode MODE which can bitwise + complement its second operand and set the condition codes explicitly. */ + +int +cc_arithopn (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + /* XOR is not here because combine canonicalizes (xor (not ...) ...) + and (xor ... (not ...)) to (not (xor ...)). */ + return (GET_CODE (op) == AND + || GET_CODE (op) == IOR); +} + +/* Return true if OP is a register, or is a CONST_INT that can fit in a + signed 13 bit immediate field. This is an acceptable SImode operand for + most 3 address instructions. */ + +int +arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + int val; + if (register_operand (op, mode)) + return 1; + if (GET_CODE (op) != CONST_INT) + return 0; + val = INTVAL (op) & 0xffffffff; + return SPARC_SIMM13_P (val); +} + +/* Return true if OP is a constant 4096 */ + +int +arith_4096_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + int val; + if (GET_CODE (op) != CONST_INT) + return 0; + val = INTVAL (op) & 0xffffffff; + return val == 4096; +} + +/* Return true if OP is suitable as second operand for add/sub */ + +int +arith_add_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return arith_operand (op, mode) || arith_4096_operand (op, mode); +} + +/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the + immediate field of OR and XOR instructions. Used for 64-bit + constant formation patterns. */ +int +const64_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return ((GET_CODE (op) == CONST_INT + && SPARC_SIMM13_P (INTVAL (op))) +#if HOST_BITS_PER_WIDE_INT != 64 + || (GET_CODE (op) == CONST_DOUBLE + && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) + && (CONST_DOUBLE_HIGH (op) == + ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? + (HOST_WIDE_INT)0xffffffff : 0))) +#endif + ); +} + +/* The same, but only for sethi instructions. */ +int +const64_high_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return ((GET_CODE (op) == CONST_INT + && (INTVAL (op) & 0xfffffc00) != 0 + && SPARC_SETHI_P (INTVAL (op)) +#if HOST_BITS_PER_WIDE_INT != 64 + /* Must be positive on non-64bit host else the + optimizer is fooled into thinking that sethi + sign extends, even though it does not. */ + && INTVAL (op) >= 0 +#endif + ) + || (GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_HIGH (op) == 0 + && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0 + && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); +} + +/* Return true if OP is a register, or is a CONST_INT that can fit in a + signed 11 bit immediate field. This is an acceptable SImode operand for + the movcc instructions. */ + +int +arith11_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (register_operand (op, mode) + || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); +} + +/* Return true if OP is a register, or is a CONST_INT that can fit in a + signed 10 bit immediate field. This is an acceptable SImode operand for + the movrcc instructions. */ + +int +arith10_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (register_operand (op, mode) + || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); +} + +/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit + immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit + immediate field. + v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that + can fit in a 13 bit immediate field. This is an acceptable DImode operand + for most 3 address instructions. */ + +int +arith_double_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (register_operand (op, mode) + || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) + || (! TARGET_ARCH64 + && GET_CODE (op) == CONST_DOUBLE + && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 + && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) + || (TARGET_ARCH64 + && GET_CODE (op) == CONST_DOUBLE + && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 + && ((CONST_DOUBLE_HIGH (op) == -1 + && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) + || (CONST_DOUBLE_HIGH (op) == 0 + && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); +} + +/* Return true if OP is a constant 4096 for DImode on ARCH64 */ + +int +arith_double_4096_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (TARGET_ARCH64 && + ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || + (GET_CODE (op) == CONST_DOUBLE && + CONST_DOUBLE_LOW (op) == 4096 && + CONST_DOUBLE_HIGH (op) == 0))); +} + +/* Return true if OP is suitable as second operand for add/sub in DImode */ + +int +arith_double_add_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); +} + +/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that + can fit in an 11 bit immediate field. This is an acceptable DImode + operand for the movcc instructions. */ +/* ??? Replace with arith11_operand? */ + +int +arith11_double_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (register_operand (op, mode) + || (GET_CODE (op) == CONST_DOUBLE + && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) + && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 + && ((CONST_DOUBLE_HIGH (op) == -1 + && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) + || (CONST_DOUBLE_HIGH (op) == 0 + && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) + || (GET_CODE (op) == CONST_INT + && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) + && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); +} + +/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that + can fit in an 10 bit immediate field. This is an acceptable DImode + operand for the movrcc instructions. */ +/* ??? Replace with arith10_operand? */ + +int +arith10_double_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (register_operand (op, mode) + || (GET_CODE (op) == CONST_DOUBLE + && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) + && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 + && ((CONST_DOUBLE_HIGH (op) == -1 + && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) + || (CONST_DOUBLE_HIGH (op) == 0 + && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) + || (GET_CODE (op) == CONST_INT + && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) + && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); +} + +/* Return truth value of whether OP is a integer which fits the + range constraining immediate operands in most three-address insns, + which have a 13 bit immediate field. */ + +int +small_int (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); +} + +int +small_int_or_double (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) + || (GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_HIGH (op) == 0 + && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); +} + +/* Recognize operand values for the umul instruction. That instruction sign + extends immediate values just like all other sparc instructions, but + interprets the extended result as an unsigned number. */ + +int +uns_small_int (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ +#if HOST_BITS_PER_WIDE_INT > 32 + /* All allowed constants will fit a CONST_INT. */ + return (GET_CODE (op) == CONST_INT + && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) + || (INTVAL (op) >= 0xFFFFF000 + && INTVAL (op) < 0x100000000))); +#else + return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) + || (GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_HIGH (op) == 0 + && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); +#endif +} + +int +uns_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return register_operand (op, mode) || uns_small_int (op, mode); +} + +/* Return truth value of statement that OP is a call-clobbered register. */ +int +clobbered_register (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); +} + +/* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */ + +int +zero_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return op == const0_rtx; +} + +/* Return 1 if OP is a valid operand for the source of a move insn. */ + +int +input_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + /* If both modes are non-void they must be the same. */ + if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) + return 0; + + /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ + if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) + return 1; + + /* Allow any one instruction integer constant, and all CONST_INT + variants when we are working in DImode and !arch64. */ + if (GET_MODE_CLASS (mode) == MODE_INT + && ((GET_CODE (op) == CONST_INT + && ((SPARC_SETHI_P (INTVAL (op)) + && (! TARGET_ARCH64 + || (INTVAL (op) >= 0) + || mode == SImode)) + || SPARC_SIMM13_P (INTVAL (op)) + || (mode == DImode + && ! TARGET_ARCH64))) + || (TARGET_ARCH64 + && GET_CODE (op) == CONST_DOUBLE + && ((CONST_DOUBLE_HIGH (op) == 0 + && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) + || +#if HOST_BITS_PER_WIDE_INT == 64 + (CONST_DOUBLE_HIGH (op) == 0 + && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) +#else + (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) + && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 + && CONST_DOUBLE_HIGH (op) == 0) + || (CONST_DOUBLE_HIGH (op) == -1))) +#endif + )))) + return 1; + + /* If !arch64 and this is a DImode const, allow it so that + the splits can be generated. */ + if (! TARGET_ARCH64 + && mode == DImode + && GET_CODE (op) == CONST_DOUBLE) + return 1; + + if (register_operand (op, mode)) + return 1; + + /* If this is a SUBREG, look inside so that we handle + paradoxical ones. */ + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + /* Check for valid MEM forms. */ + if (GET_CODE (op) == MEM) + { + rtx inside = XEXP (op, 0); + + if (GET_CODE (inside) == LO_SUM) + { + /* We can't allow these because all of the splits + (eventually as they trickle down into DFmode + splits) require offsettable memory references. */ + if (! TARGET_V9 + && GET_MODE (op) == TFmode) + return 0; + + return (register_operand (XEXP (inside, 0), Pmode) + && CONSTANT_P (XEXP (inside, 1))); + } + return memory_address_p (mode, inside); + } + + return 0; +} + + +/* We know it can't be done in one insn when we get here, + the movsi expander guarentees this. */ +void +sparc_emit_set_const32 (op0, op1) + rtx op0; + rtx op1; +{ + enum machine_mode mode = GET_MODE (op0); + rtx temp; + + if (GET_CODE (op1) == CONST_INT) + { + HOST_WIDE_INT value = INTVAL (op1); + + if (SPARC_SETHI_P (value) + || SPARC_SIMM13_P (value)) + abort (); + } + + /* Full 2-insn decomposition is needed. */ + if (reload_in_progress || reload_completed) + temp = op0; + else + temp = gen_reg_rtx (mode); + + if (GET_CODE (op1) == CONST_INT) + { + /* Emit them as real moves instead of a HIGH/LO_SUM, + this way CSE can see everything and reuse intermediate + values if it wants. */ + if (TARGET_ARCH64 + && HOST_BITS_PER_WIDE_INT != 64 + && (INTVAL (op1) & 0x80000000) != 0) + { + emit_insn (gen_rtx_SET (VOIDmode, + temp, + gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, + INTVAL (op1) & 0xfffffc00, 0))); + } + else + { + emit_insn (gen_rtx_SET (VOIDmode, + temp, + GEN_INT (INTVAL (op1) & 0xfffffc00))); + } + emit_insn (gen_rtx_SET (VOIDmode, + op0, + gen_rtx_IOR (mode, + temp, + GEN_INT (INTVAL (op1) & 0x3ff)))); + } + else + { + /* A symbol, emit in the traditional way. */ + emit_insn (gen_rtx_SET (VOIDmode, + temp, + gen_rtx_HIGH (mode, + op1))); + emit_insn (gen_rtx_SET (VOIDmode, + op0, + gen_rtx_LO_SUM (mode, + temp, + op1))); + + } +} + + +/* Sparc-v9 code-model support. */ +void +sparc_emit_set_symbolic_const64 (op0, op1, temp1) + rtx op0; + rtx op1; + rtx temp1; +{ + switch (sparc_cmodel) + { + case CM_MEDLOW: + /* The range spanned by all instructions in the object is less + than 2^31 bytes (2GB) and the distance from any instruction + to the location of the label _GLOBAL_OFFSET_TABLE_ is less + than 2^31 bytes (2GB). + + The executable must be in the low 4TB of the virtual address + space. + + sethi %hi(symbol), %temp + or %temp, %lo(symbol), %reg */ + emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); + emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); + break; + + case CM_MEDMID: + /* The range spanned by all instructions in the object is less + than 2^31 bytes (2GB) and the distance from any instruction + to the location of the label _GLOBAL_OFFSET_TABLE_ is less + than 2^31 bytes (2GB). + + The executable must be in the low 16TB of the virtual address + space. + + sethi %h44(symbol), %temp1 + or %temp1, %m44(symbol), %temp2 + sllx %temp2, 12, %temp3 + or %temp3, %l44(symbol), %reg */ + emit_insn (gen_seth44 (op0, op1)); + emit_insn (gen_setm44 (op0, op0, op1)); + emit_insn (gen_rtx_SET (VOIDmode, temp1, + gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); + emit_insn (gen_setl44 (op0, temp1, op1)); + break; + + case CM_MEDANY: + /* The range spanned by all instructions in the object is less + than 2^31 bytes (2GB) and the distance from any instruction + to the location of the label _GLOBAL_OFFSET_TABLE_ is less + than 2^31 bytes (2GB). + + The executable can be placed anywhere in the virtual address + space. + + sethi %hh(symbol), %temp1 + sethi %lm(symbol), %temp2 + or %temp1, %hm(symbol), %temp3 + or %temp2, %lo(symbol), %temp4 + sllx %temp3, 32, %temp5 + or %temp4, %temp5, %reg */ + + /* Getting this right wrt. reloading is really tricky. + We _MUST_ have a seperate temporary at this point, + if we don't barf immediately instead of generating + incorrect code. */ + if (temp1 == op0) + abort (); + + emit_insn (gen_sethh (op0, op1)); + emit_insn (gen_setlm (temp1, op1)); + emit_insn (gen_sethm (op0, op0, op1)); + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_PLUS (DImode, op0, temp1))); + emit_insn (gen_setlo (op0, op0, op1)); + break; + + case CM_EMBMEDANY: + /* Old old old backwards compatibility kruft here. + Essentially it is MEDLOW with a fixed 64-bit + virtual base added to all data segment addresses. + Text-segment stuff is computed like MEDANY, we can't + reuse the code above because the relocation knobs + look different. + + Data segment: sethi %hi(symbol), %temp1 + or %temp1, %lo(symbol), %temp2 + add %temp2, EMBMEDANY_BASE_REG, %reg + + Text segment: sethi %uhi(symbol), %temp1 + sethi %hi(symbol), %temp2 + or %temp1, %ulo(symbol), %temp3 + or %temp2, %lo(symbol), %temp4 + sllx %temp3, 32, %temp5 + or %temp4, %temp5, %reg */ + if (data_segment_operand (op1, GET_MODE (op1))) + { + emit_insn (gen_embmedany_sethi (temp1, op1)); + emit_insn (gen_embmedany_brsum (op0, temp1)); + emit_insn (gen_embmedany_losum (op0, op0, op1)); + } + else + { + /* Getting this right wrt. reloading is really tricky. + We _MUST_ have a seperate temporary at this point, + so we barf immediately instead of generating + incorrect code. */ + if (temp1 == op0) + abort (); + + emit_insn (gen_embmedany_textuhi (op0, op1)); + emit_insn (gen_embmedany_texthi (temp1, op1)); + emit_insn (gen_embmedany_textulo (op0, op0, op1)); + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_PLUS (DImode, op0, temp1))); + emit_insn (gen_embmedany_textlo (op0, op0, op1)); + } + break; + + default: + abort(); + } +} + +/* These avoid problems when cross compiling. If we do not + go through all this hair then the optimizer will see + invalid REG_EQUAL notes or in some cases none at all. */ +static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT)); +static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT)); +static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT)); +static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT)); + +#if HOST_BITS_PER_WIDE_INT == 64 +#define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00) +#define GEN_INT64(__x) GEN_INT (__x) +#else +#define GEN_HIGHINT64(__x) \ + gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ + (__x) & 0xfffffc00, 0) +#define GEN_INT64(__x) \ + gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ + (__x) & 0xffffffff, \ + ((__x) & 0x80000000 \ + ? 0xffffffff : 0)) +#endif + +/* The optimizer is not to assume anything about exactly + which bits are set for a HIGH, they are unspecified. + Unfortunately this leads to many missed optimizations + during CSE. We mask out the non-HIGH bits, and matches + a plain movdi, to alleviate this problem. */ +static void +sparc_emit_set_safe_HIGH64 (dest, val) + rtx dest; + HOST_WIDE_INT val; +{ + emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); +} + +static rtx +gen_safe_SET64 (dest, val) + rtx dest; + HOST_WIDE_INT val; +{ + return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); +} + +static rtx +gen_safe_OR64 (src, val) + rtx src; + HOST_WIDE_INT val; +{ + return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); +} + +static rtx +gen_safe_XOR64 (src, val) + rtx src; + HOST_WIDE_INT val; +{ + return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); +} + +/* Worker routines for 64-bit constant formation on arch64. + One of the key things to be doing in these emissions is + to create as many temp REGs as possible. This makes it + possible for half-built constants to be used later when + such values are similar to something required later on. + Without doing this, the optimizer cannot see such + opportunities. */ + +static void sparc_emit_set_const64_quick1 + PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int)); + +static void +sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) + rtx op0; + rtx temp; + unsigned HOST_WIDE_INT low_bits; + int is_neg; +{ + unsigned HOST_WIDE_INT high_bits; + + if (is_neg) + high_bits = (~low_bits) & 0xffffffff; + else + high_bits = low_bits; + + sparc_emit_set_safe_HIGH64 (temp, high_bits); + if (!is_neg) + { + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_safe_OR64 (temp, (high_bits & 0x3ff)))); + } + else + { + /* If we are XOR'ing with -1, then we should emit a one's complement + instead. This way the combiner will notice logical operations + such as ANDN later on and substitute. */ + if ((low_bits & 0x3ff) == 0x3ff) + { + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_NOT (DImode, temp))); + } + else + { + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_safe_XOR64 (temp, + (-0x400 | (low_bits & 0x3ff))))); + } + } +} + +static void sparc_emit_set_const64_quick2 + PROTO((rtx, rtx, unsigned HOST_WIDE_INT, + unsigned HOST_WIDE_INT, int)); + +static void +sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) + rtx op0; + rtx temp; + unsigned HOST_WIDE_INT high_bits; + unsigned HOST_WIDE_INT low_immediate; + int shift_count; +{ + rtx temp2 = op0; + + if ((high_bits & 0xfffffc00) != 0) + { + sparc_emit_set_safe_HIGH64 (temp, high_bits); + if ((high_bits & ~0xfffffc00) != 0) + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_safe_OR64 (temp, (high_bits & 0x3ff)))); + else + temp2 = temp; + } + else + { + emit_insn (gen_safe_SET64 (temp, high_bits)); + temp2 = temp; + } + + /* Now shift it up into place. */ + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_ASHIFT (DImode, temp2, + GEN_INT (shift_count)))); + + /* If there is a low immediate part piece, finish up by + putting that in as well. */ + if (low_immediate != 0) + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_safe_OR64 (op0, low_immediate))); +} + +static void sparc_emit_set_const64_longway + PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); + +/* Full 64-bit constant decomposition. Even though this is the + 'worst' case, we still optimize a few things away. */ +static void +sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) + rtx op0; + rtx temp; + unsigned HOST_WIDE_INT high_bits; + unsigned HOST_WIDE_INT low_bits; +{ + rtx sub_temp; + + if (reload_in_progress || reload_completed) + sub_temp = op0; + else + sub_temp = gen_reg_rtx (DImode); + + if ((high_bits & 0xfffffc00) != 0) + { + sparc_emit_set_safe_HIGH64 (temp, high_bits); + if ((high_bits & ~0xfffffc00) != 0) + emit_insn (gen_rtx_SET (VOIDmode, + sub_temp, + gen_safe_OR64 (temp, (high_bits & 0x3ff)))); + else + sub_temp = temp; + } + else + { + emit_insn (gen_safe_SET64 (temp, high_bits)); + sub_temp = temp; + } + + if (!reload_in_progress && !reload_completed) + { + rtx temp2 = gen_reg_rtx (DImode); + rtx temp3 = gen_reg_rtx (DImode); + rtx temp4 = gen_reg_rtx (DImode); + + emit_insn (gen_rtx_SET (VOIDmode, temp4, + gen_rtx_ASHIFT (DImode, sub_temp, + GEN_INT (32)))); + + sparc_emit_set_safe_HIGH64 (temp2, low_bits); + if ((low_bits & ~0xfffffc00) != 0) + { + emit_insn (gen_rtx_SET (VOIDmode, temp3, + gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_PLUS (DImode, temp4, temp3))); + } + else + { + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_PLUS (DImode, temp4, temp2))); + } + } + else + { + rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); + rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); + rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); + int to_shift = 12; + + /* We are in the middle of reload, so this is really + painful. However we do still make an attempt to + avoid emitting truly stupid code. */ + if (low1 != const0_rtx) + { + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_ASHIFT (DImode, sub_temp, + GEN_INT (to_shift)))); + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_IOR (DImode, op0, low1))); + sub_temp = op0; + to_shift = 12; + } + else + { + to_shift += 12; + } + if (low2 != const0_rtx) + { + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_ASHIFT (DImode, sub_temp, + GEN_INT (to_shift)))); + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_IOR (DImode, op0, low2))); + sub_temp = op0; + to_shift = 8; + } + else + { + to_shift += 8; + } + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_ASHIFT (DImode, sub_temp, + GEN_INT (to_shift)))); + if (low3 != const0_rtx) + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_IOR (DImode, op0, low3))); + /* phew... */ + } +} + +/* Analyze a 64-bit constant for certain properties. */ +static void analyze_64bit_constant + PROTO((unsigned HOST_WIDE_INT, + unsigned HOST_WIDE_INT, + int *, int *, int *)); + +static void +analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) + unsigned HOST_WIDE_INT high_bits, low_bits; + int *hbsp, *lbsp, *abbasp; +{ + int lowest_bit_set, highest_bit_set, all_bits_between_are_set; + int i; + + lowest_bit_set = highest_bit_set = -1; + i = 0; + do + { + if ((lowest_bit_set == -1) + && ((low_bits >> i) & 1)) + lowest_bit_set = i; + if ((highest_bit_set == -1) + && ((high_bits >> (32 - i - 1)) & 1)) + highest_bit_set = (64 - i - 1); + } + while (++i < 32 + && ((highest_bit_set == -1) + || (lowest_bit_set == -1))); + if (i == 32) + { + i = 0; + do + { + if ((lowest_bit_set == -1) + && ((high_bits >> i) & 1)) + lowest_bit_set = i + 32; + if ((highest_bit_set == -1) + && ((low_bits >> (32 - i - 1)) & 1)) + highest_bit_set = 32 - i - 1; + } + while (++i < 32 + && ((highest_bit_set == -1) + || (lowest_bit_set == -1))); + } + /* If there are no bits set this should have gone out + as one instruction! */ + if (lowest_bit_set == -1 + || highest_bit_set == -1) + abort (); + all_bits_between_are_set = 1; + for (i = lowest_bit_set; i <= highest_bit_set; i++) + { + if (i < 32) + { + if ((low_bits & (1 << i)) != 0) + continue; + } + else + { + if ((high_bits & (1 << (i - 32))) != 0) + continue; + } + all_bits_between_are_set = 0; + break; + } + *hbsp = highest_bit_set; + *lbsp = lowest_bit_set; + *abbasp = all_bits_between_are_set; +} + +static int const64_is_2insns + PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); + +static int +const64_is_2insns (high_bits, low_bits) + unsigned HOST_WIDE_INT high_bits, low_bits; +{ + int highest_bit_set, lowest_bit_set, all_bits_between_are_set; + + if (high_bits == 0 + || high_bits == 0xffffffff) + return 1; + + analyze_64bit_constant (high_bits, low_bits, + &highest_bit_set, &lowest_bit_set, + &all_bits_between_are_set); + + if ((highest_bit_set == 63 + || lowest_bit_set == 0) + && all_bits_between_are_set != 0) + return 1; + + if ((highest_bit_set - lowest_bit_set) < 21) + return 1; + + return 0; +} + +static unsigned HOST_WIDE_INT create_simple_focus_bits + PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, + int, int)); + +static unsigned HOST_WIDE_INT +create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) + unsigned HOST_WIDE_INT high_bits, low_bits; + int lowest_bit_set, shift; +{ + HOST_WIDE_INT hi, lo; + + if (lowest_bit_set < 32) + { + lo = (low_bits >> lowest_bit_set) << shift; + hi = ((high_bits << (32 - lowest_bit_set)) << shift); + } + else + { + lo = 0; + hi = ((high_bits >> (lowest_bit_set - 32)) << shift); + } + if (hi & lo) + abort (); + return (hi | lo); +} + +/* Here we are sure to be arch64 and this is an integer constant + being loaded into a register. Emit the most efficient + insn sequence possible. Detection of all the 1-insn cases + has been done already. */ +void +sparc_emit_set_const64 (op0, op1) + rtx op0; + rtx op1; +{ + unsigned HOST_WIDE_INT high_bits, low_bits; + int lowest_bit_set, highest_bit_set; + int all_bits_between_are_set; + rtx temp; + + /* Sanity check that we know what we are working with. */ + if (! TARGET_ARCH64 + || GET_CODE (op0) != REG + || (REGNO (op0) >= SPARC_FIRST_FP_REG + && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) + abort (); + + if (reload_in_progress || reload_completed) + temp = op0; + else + temp = gen_reg_rtx (DImode); + + if (GET_CODE (op1) != CONST_DOUBLE + && GET_CODE (op1) != CONST_INT) + { + sparc_emit_set_symbolic_const64 (op0, op1, temp); + return; + } + + if (GET_CODE (op1) == CONST_DOUBLE) + { +#if HOST_BITS_PER_WIDE_INT == 64 + high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; + low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; +#else + high_bits = CONST_DOUBLE_HIGH (op1); + low_bits = CONST_DOUBLE_LOW (op1); +#endif + } + else + { +#if HOST_BITS_PER_WIDE_INT == 64 + high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); + low_bits = (INTVAL (op1) & 0xffffffff); +#else + high_bits = ((INTVAL (op1) < 0) ? + 0xffffffff : + 0x00000000); + low_bits = INTVAL (op1); +#endif + } + + /* low_bits bits 0 --> 31 + high_bits bits 32 --> 63 */ + + analyze_64bit_constant (high_bits, low_bits, + &highest_bit_set, &lowest_bit_set, + &all_bits_between_are_set); + + /* First try for a 2-insn sequence. */ + + /* These situations are preferred because the optimizer can + * do more things with them: + * 1) mov -1, %reg + * sllx %reg, shift, %reg + * 2) mov -1, %reg + * srlx %reg, shift, %reg + * 3) mov some_small_const, %reg + * sllx %reg, shift, %reg + */ + if (((highest_bit_set == 63 + || lowest_bit_set == 0) + && all_bits_between_are_set != 0) + || ((highest_bit_set - lowest_bit_set) < 12)) + { + HOST_WIDE_INT the_const = -1; + int shift = lowest_bit_set; + + if ((highest_bit_set != 63 + && lowest_bit_set != 0) + || all_bits_between_are_set == 0) + { + the_const = + create_simple_focus_bits (high_bits, low_bits, + lowest_bit_set, 0); + } + else if (lowest_bit_set == 0) + shift = -(63 - highest_bit_set); + + if (! SPARC_SIMM13_P (the_const)) + abort (); + + emit_insn (gen_safe_SET64 (temp, the_const)); + if (shift > 0) + emit_insn (gen_rtx_SET (VOIDmode, + op0, + gen_rtx_ASHIFT (DImode, + temp, + GEN_INT (shift)))); + else if (shift < 0) + emit_insn (gen_rtx_SET (VOIDmode, + op0, + gen_rtx_LSHIFTRT (DImode, + temp, + GEN_INT (-shift)))); + else + abort (); + return; + } + + /* Now a range of 22 or less bits set somewhere. + * 1) sethi %hi(focus_bits), %reg + * sllx %reg, shift, %reg + * 2) sethi %hi(focus_bits), %reg + * srlx %reg, shift, %reg + */ + if ((highest_bit_set - lowest_bit_set) < 21) + { + unsigned HOST_WIDE_INT focus_bits = + create_simple_focus_bits (high_bits, low_bits, + lowest_bit_set, 10); + + if (! SPARC_SETHI_P (focus_bits)) + abort (); + + sparc_emit_set_safe_HIGH64 (temp, focus_bits); + + /* If lowest_bit_set == 10 then a sethi alone could have done it. */ + if (lowest_bit_set < 10) + emit_insn (gen_rtx_SET (VOIDmode, + op0, + gen_rtx_LSHIFTRT (DImode, temp, + GEN_INT (10 - lowest_bit_set)))); + else if (lowest_bit_set > 10) + emit_insn (gen_rtx_SET (VOIDmode, + op0, + gen_rtx_ASHIFT (DImode, temp, + GEN_INT (lowest_bit_set - 10)))); + else + abort (); + return; + } + + /* 1) sethi %hi(low_bits), %reg + * or %reg, %lo(low_bits), %reg + * 2) sethi %hi(~low_bits), %reg + * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg + */ + if (high_bits == 0 + || high_bits == 0xffffffff) + { + sparc_emit_set_const64_quick1 (op0, temp, low_bits, + (high_bits == 0xffffffff)); + return; + } + + /* Now, try 3-insn sequences. */ + + /* 1) sethi %hi(high_bits), %reg + * or %reg, %lo(high_bits), %reg + * sllx %reg, 32, %reg + */ + if (low_bits == 0) + { + sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); + return; + } + + /* We may be able to do something quick + when the constant is negated, so try that. */ + if (const64_is_2insns ((~high_bits) & 0xffffffff, + (~low_bits) & 0xfffffc00)) + { + /* NOTE: The trailing bits get XOR'd so we need the + non-negated bits, not the negated ones. */ + unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; + + if ((((~high_bits) & 0xffffffff) == 0 + && ((~low_bits) & 0x80000000) == 0) + || (((~high_bits) & 0xffffffff) == 0xffffffff + && ((~low_bits) & 0x80000000) != 0)) + { + int fast_int = (~low_bits & 0xffffffff); + + if ((SPARC_SETHI_P (fast_int) + && (~high_bits & 0xffffffff) == 0) + || SPARC_SIMM13_P (fast_int)) + emit_insn (gen_safe_SET64 (temp, fast_int)); + else + sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); + } + else + { + rtx negated_const; +#if HOST_BITS_PER_WIDE_INT == 64 + negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | + (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); +#else + negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx, + (~low_bits) & 0xfffffc00, + (~high_bits) & 0xffffffff); +#endif + sparc_emit_set_const64 (temp, negated_const); + } + + /* If we are XOR'ing with -1, then we should emit a one's complement + instead. This way the combiner will notice logical operations + such as ANDN later on and substitute. */ + if (trailing_bits == 0x3ff) + { + emit_insn (gen_rtx_SET (VOIDmode, op0, + gen_rtx_NOT (DImode, temp))); + } + else + { + emit_insn (gen_rtx_SET (VOIDmode, + op0, + gen_safe_XOR64 (temp, + (-0x400 | trailing_bits)))); + } + return; + } + + /* 1) sethi %hi(xxx), %reg + * or %reg, %lo(xxx), %reg + * sllx %reg, yyy, %reg + * + * ??? This is just a generalized version of the low_bits==0 + * thing above, FIXME... + */ + if ((highest_bit_set - lowest_bit_set) < 32) + { + unsigned HOST_WIDE_INT focus_bits = + create_simple_focus_bits (high_bits, low_bits, + lowest_bit_set, 0); + + /* We can't get here in this state. */ + if (highest_bit_set < 32 + || lowest_bit_set >= 32) + abort (); + + /* So what we know is that the set bits straddle the + middle of the 64-bit word. */ + sparc_emit_set_const64_quick2 (op0, temp, + focus_bits, 0, + lowest_bit_set); + return; + } + + /* 1) sethi %hi(high_bits), %reg + * or %reg, %lo(high_bits), %reg + * sllx %reg, 32, %reg + * or %reg, low_bits, %reg + */ + if (SPARC_SIMM13_P(low_bits) + && ((int)low_bits > 0)) + { + sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); + return; + } + + /* The easiest way when all else fails, is full decomposition. */ +#if 0 + printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", + high_bits, low_bits, ~high_bits, ~low_bits); +#endif + sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); +} + +/* X and Y are two things to compare using CODE. Emit the compare insn and + return the rtx for the cc reg in the proper mode. */ + +rtx +gen_compare_reg (code, x, y) + enum rtx_code code; + rtx x, y; +{ + enum machine_mode mode = SELECT_CC_MODE (code, x, y); + rtx cc_reg; + + /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the + fcc regs (cse can't tell they're really call clobbered regs and will + remove a duplicate comparison even if there is an intervening function + call - it will then try to reload the cc reg via an int reg which is why + we need the movcc patterns). It is possible to provide the movcc + patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two + registers (say %g1,%g5) and it takes about 6 insns. A better fix would be + to tell cse that CCFPE mode registers (even pseudos) are call + clobbered. */ + + /* ??? This is an experiment. Rather than making changes to cse which may + or may not be easy/clean, we do our own cse. This is possible because + we will generate hard registers. Cse knows they're call clobbered (it + doesn't know the same thing about pseudos). If we guess wrong, no big + deal, but if we win, great! */ + + if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) +#if 1 /* experiment */ + { + int reg; + /* We cycle through the registers to ensure they're all exercised. */ + static int next_fcc_reg = 0; + /* Previous x,y for each fcc reg. */ + static rtx prev_args[4][2]; + + /* Scan prev_args for x,y. */ + for (reg = 0; reg < 4; reg++) + if (prev_args[reg][0] == x && prev_args[reg][1] == y) + break; + if (reg == 4) + { + reg = next_fcc_reg; + prev_args[reg][0] = x; + prev_args[reg][1] = y; + next_fcc_reg = (next_fcc_reg + 1) & 3; + } + cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); + } +#else + cc_reg = gen_reg_rtx (mode); +#endif /* ! experiment */ + else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); + else + cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); + + emit_insn (gen_rtx_SET (VOIDmode, cc_reg, + gen_rtx_COMPARE (mode, x, y))); + + return cc_reg; +} + +/* This function is used for v9 only. + CODE is the code for an Scc's comparison. + OPERANDS[0] is the target of the Scc insn. + OPERANDS[1] is the value we compare against const0_rtx (which hasn't + been generated yet). + + This function is needed to turn + + (set (reg:SI 110) + (gt (reg:CCX 100 %icc) + (const_int 0))) + into + (set (reg:SI 110) + (gt:DI (reg:CCX 100 %icc) + (const_int 0))) + + IE: The instruction recognizer needs to see the mode of the comparison to + find the right instruction. We could use "gt:DI" right in the + define_expand, but leaving it out allows us to handle DI, SI, etc. + + We refer to the global sparc compare operands sparc_compare_op0 and + sparc_compare_op1. */ + +int +gen_v9_scc (compare_code, operands) + enum rtx_code compare_code; + register rtx *operands; +{ + rtx temp, op0, op1; + + if (! TARGET_ARCH64 + && (GET_MODE (sparc_compare_op0) == DImode + || GET_MODE (operands[0]) == DImode)) + return 0; + + /* Handle the case where operands[0] == sparc_compare_op0. + We "early clobber" the result. */ + if (REGNO (operands[0]) == REGNO (sparc_compare_op0)) + { + op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); + emit_move_insn (op0, sparc_compare_op0); + } + else + op0 = sparc_compare_op0; + /* For consistency in the following. */ + op1 = sparc_compare_op1; + + /* Try to use the movrCC insns. */ + if (TARGET_ARCH64 + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT + && op1 == const0_rtx + && v9_regcmp_p (compare_code)) + { + /* Special case for op0 != 0. This can be done with one instruction if + operands[0] == sparc_compare_op0. We don't assume they are equal + now though. */ + + if (compare_code == NE + && GET_MODE (operands[0]) == DImode + && GET_MODE (op0) == DImode) + { + emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_IF_THEN_ELSE (DImode, + gen_rtx_fmt_ee (compare_code, DImode, + op0, const0_rtx), + const1_rtx, + operands[0]))); + return 1; + } + + emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); + if (GET_MODE (op0) != DImode) + { + temp = gen_reg_rtx (DImode); + convert_move (temp, op0, 0); + } + else + temp = op0; + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), + gen_rtx_fmt_ee (compare_code, DImode, + temp, const0_rtx), + const1_rtx, + operands[0]))); + return 1; + } + else + { + operands[1] = gen_compare_reg (compare_code, op0, op1); + + switch (GET_MODE (operands[1])) + { + case CCmode : + case CCXmode : + case CCFPEmode : + case CCFPmode : + break; + default : + abort (); + } + emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), + gen_rtx_fmt_ee (compare_code, + GET_MODE (operands[1]), + operands[1], const0_rtx), + const1_rtx, operands[0]))); + return 1; + } +} + +/* Emit a conditional jump insn for the v9 architecture using comparison code + CODE and jump target LABEL. + This function exists to take advantage of the v9 brxx insns. */ + +void +emit_v9_brxx_insn (code, op0, label) + enum rtx_code code; + rtx op0, label; +{ + emit_jump_insn (gen_rtx_SET (VOIDmode, + pc_rtx, + gen_rtx_IF_THEN_ELSE (VOIDmode, + gen_rtx_fmt_ee (code, GET_MODE (op0), + op0, const0_rtx), + gen_rtx_LABEL_REF (VOIDmode, label), + pc_rtx))); +} + +/* Return nonzero if a return peephole merging return with + setting of output register is ok. */ +int +leaf_return_peephole_ok () +{ + return (actual_fsize == 0); +} + +/* Return nonzero if TRIAL can go into the function epilogue's + delay slot. SLOT is the slot we are trying to fill. */ + +int +eligible_for_epilogue_delay (trial, slot) + rtx trial; + int slot; +{ + rtx pat, src; + + if (slot >= 1) + return 0; + + if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) + return 0; + + if (get_attr_length (trial) != 1) + return 0; + + /* If %g0 is live, there are lots of things we can't handle. + Rather than trying to find them all now, let's punt and only + optimize things as necessary. */ + if (TARGET_LIVE_G0) + return 0; + + /* In the case of a true leaf function, anything can go into the delay slot. + A delay slot only exists however if the frame size is zero, otherwise + we will put an insn to adjust the stack after the return. */ + if (current_function_uses_only_leaf_regs) + { + if (leaf_return_peephole_ok ()) + return ((get_attr_in_uncond_branch_delay (trial) + == IN_BRANCH_DELAY_TRUE)); + return 0; + } + + /* If only trivial `restore' insns work, nothing can go in the + delay slot. */ + else if (TARGET_BROKEN_SAVERESTORE) + return 0; + + pat = PATTERN (trial); + + /* Otherwise, only operations which can be done in tandem with + a `restore' insn can go into the delay slot. */ + if (GET_CODE (SET_DEST (pat)) != REG + || REGNO (SET_DEST (pat)) >= 32 + || REGNO (SET_DEST (pat)) < 24) + return 0; + + /* The set of insns matched here must agree precisely with the set of + patterns paired with a RETURN in sparc.md. */ + + src = SET_SRC (pat); + + /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ + if (arith_operand (src, GET_MODE (src))) + { + if (TARGET_ARCH64) + return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); + else + return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); + } + + /* This matches "*return_di". */ + else if (arith_double_operand (src, GET_MODE (src))) + return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); + + /* This matches "*return_sf_no_fpu". */ + else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) + && register_operand (src, SFmode)) + return 1; + + /* This matches "*return_addsi". */ + else if (GET_CODE (src) == PLUS + && arith_operand (XEXP (src, 0), SImode) + && arith_operand (XEXP (src, 1), SImode) + && (register_operand (XEXP (src, 0), SImode) + || register_operand (XEXP (src, 1), SImode))) + return 1; + + /* This matches "*return_adddi". */ + else if (GET_CODE (src) == PLUS + && arith_double_operand (XEXP (src, 0), DImode) + && arith_double_operand (XEXP (src, 1), DImode) + && (register_operand (XEXP (src, 0), DImode) + || register_operand (XEXP (src, 1), DImode))) + return 1; + + return 0; +} + +static int +check_return_regs (x) + rtx x; +{ + switch (GET_CODE (x)) + { + case REG: + return IN_OR_GLOBAL_P (x); + + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + return 1; + + case SET: + case IOR: + case AND: + case XOR: + case PLUS: + case MINUS: + if (check_return_regs (XEXP (x, 1)) == 0) + return 0; + case NOT: + case NEG: + case MEM: + return check_return_regs (XEXP (x, 0)); + + default: + return 0; + } + +} + +/* Return 1 if TRIAL references only in and global registers. */ +int +eligible_for_return_delay (trial) + rtx trial; +{ + if (GET_CODE (PATTERN (trial)) != SET) + return 0; + + return check_return_regs (PATTERN (trial)); +} + +int +short_branch (uid1, uid2) + int uid1, uid2; +{ + unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2]; + if (delta + 1024 < 2048) + return 1; + /* warning ("long branch, distance %d", delta); */ + return 0; +} + +/* Return non-zero if REG is not used after INSN. + We assume REG is a reload reg, and therefore does + not live past labels or calls or jumps. */ +int +reg_unused_after (reg, insn) + rtx reg; + rtx insn; +{ + enum rtx_code code, prev_code = UNKNOWN; + + while ((insn = NEXT_INSN (insn))) + { + if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) + return 1; + + code = GET_CODE (insn); + if (GET_CODE (insn) == CODE_LABEL) + return 1; + + if (GET_RTX_CLASS (code) == 'i') + { + rtx set = single_set (insn); + int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); + if (set && in_src) + return 0; + if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) + return 1; + if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) + return 0; + } + prev_code = code; + } + return 1; +} + +/* The table we use to reference PIC data. */ +static rtx global_offset_table; + +/* The function we use to get at it. */ +static rtx get_pc_symbol; +static char get_pc_symbol_name[256]; + +/* Ensure that we are not using patterns that are not OK with PIC. */ + +int +check_pic (i) + int i; +{ + switch (flag_pic) + { + case 1: + if (GET_CODE (recog_operand[i]) == SYMBOL_REF + || (GET_CODE (recog_operand[i]) == CONST + && ! (GET_CODE (XEXP (recog_operand[i], 0)) == MINUS + && (XEXP (XEXP (recog_operand[i], 0), 0) + == global_offset_table) + && (GET_CODE (XEXP (XEXP (recog_operand[i], 0), 1)) + == CONST)))) + abort (); + case 2: + default: + return 1; + } +} + +/* Return true if X is an address which needs a temporary register when + reloaded while generating PIC code. */ + +int +pic_address_needs_scratch (x) + rtx x; +{ + /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ + if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) + return 1; + + return 0; +} + +/* Legitimize PIC addresses. If the address is already position-independent, + we return ORIG. Newly generated position-independent addresses go into a + reg. This is REG if non zero, otherwise we allocate register(s) as + necessary. */ + +rtx +legitimize_pic_address (orig, mode, reg) + rtx orig; + enum machine_mode mode ATTRIBUTE_UNUSED; + rtx reg; +{ + if (GET_CODE (orig) == SYMBOL_REF) + { + rtx pic_ref, address; + rtx insn; + + if (reg == 0) + { + if (reload_in_progress || reload_completed) + abort (); + else + reg = gen_reg_rtx (Pmode); + } + + if (flag_pic == 2) + { + /* If not during reload, allocate another temp reg here for loading + in the address, so that these instructions can be optimized + properly. */ + rtx temp_reg = ((reload_in_progress || reload_completed) + ? reg : gen_reg_rtx (Pmode)); + + /* Must put the SYMBOL_REF inside an UNSPEC here so that cse + won't get confused into thinking that these two instructions + are loading in the true address of the symbol. If in the + future a PIC rtx exists, that should be used instead. */ + if (Pmode == SImode) + { + emit_insn (gen_movsi_high_pic (temp_reg, orig)); + emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); + } + else + { + emit_insn (gen_movdi_high_pic (temp_reg, orig)); + emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); + } + address = temp_reg; + } + else + address = orig; + + pic_ref = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, + pic_offset_table_rtx, address)); + current_function_uses_pic_offset_table = 1; + RTX_UNCHANGING_P (pic_ref) = 1; + insn = emit_move_insn (reg, pic_ref); + /* Put a REG_EQUAL note on this insn, so that it can be optimized + by loop. */ + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, + REG_NOTES (insn)); + return reg; + } + else if (GET_CODE (orig) == CONST) + { + rtx base, offset; + + if (GET_CODE (XEXP (orig, 0)) == PLUS + && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) + return orig; + + if (reg == 0) + { + if (reload_in_progress || reload_completed) + abort (); + else + reg = gen_reg_rtx (Pmode); + } + + if (GET_CODE (XEXP (orig, 0)) == PLUS) + { + base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); + offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, + base == reg ? 0 : reg); + } + else + abort (); + + if (GET_CODE (offset) == CONST_INT) + { + if (SMALL_INT (offset)) + return plus_constant_for_output (base, INTVAL (offset)); + else if (! reload_in_progress && ! reload_completed) + offset = force_reg (Pmode, offset); + else + /* If we reach here, then something is seriously wrong. */ + abort (); + } + return gen_rtx_PLUS (Pmode, base, offset); + } + else if (GET_CODE (orig) == LABEL_REF) + /* ??? Why do we do this? */ + /* Now movsi_pic_label_ref uses it, but we ought to be checking that + the register is live instead, in case it is eliminated. */ + current_function_uses_pic_offset_table = 1; + + return orig; +} + +/* Return the RTX for insns to set the PIC register. */ + +static rtx +pic_setup_code () +{ + rtx seq; + + start_sequence (); + emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, + get_pc_symbol)); + seq = gen_sequence (); + end_sequence (); + + return seq; +} + +/* Emit special PIC prologues and epilogues. */ + +void +finalize_pic () +{ + /* Labels to get the PC in the prologue of this function. */ + int orig_flag_pic = flag_pic; + rtx insn; + + if (current_function_uses_pic_offset_table == 0) + return; + + if (! flag_pic) + abort (); + + /* If we havn't emitted the special get_pc helper function, do so now. */ + if (get_pc_symbol_name[0] == 0) + { + int align; + + ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); + text_section (); + + align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); + if (align > 0) + ASM_OUTPUT_ALIGN (asm_out_file, align); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); + fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file); + } + + /* Initialize every time through, since we can't easily + know this to be permanent. */ + global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); + get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); + flag_pic = 0; + + emit_insn_after (pic_setup_code (), get_insns ()); + + /* Insert the code in each nonlocal goto receiver. + If you make changes here or to the nonlocal_goto_receiver + pattern, make sure the unspec_volatile numbers still + match. */ + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE + && XINT (PATTERN (insn), 1) == 5) + emit_insn_after (pic_setup_code (), insn); + + flag_pic = orig_flag_pic; + + /* Need to emit this whether or not we obey regdecls, + since setjmp/longjmp can cause life info to screw up. + ??? In the case where we don't obey regdecls, this is not sufficient + since we may not fall out the bottom. */ + emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); +} + +/* Return 1 if RTX is a MEM which is known to be aligned to at + least an 8 byte boundary. */ + +int +mem_min_alignment (mem, desired) + rtx mem; + int desired; +{ + rtx addr, base, offset; + + /* If it's not a MEM we can't accept it. */ + if (GET_CODE (mem) != MEM) + return 0; + + addr = XEXP (mem, 0); + base = offset = NULL_RTX; + if (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == REG) + { + base = XEXP (addr, 0); + + /* What we are saying here is that if the base + REG is aligned properly, the compiler will make + sure any REG based index upon it will be so + as well. */ + if (GET_CODE (XEXP (addr, 1)) == CONST_INT) + offset = XEXP (addr, 1); + else + offset = const0_rtx; + } + } + else if (GET_CODE (addr) == REG) + { + base = addr; + offset = const0_rtx; + } + + if (base != NULL_RTX) + { + int regno = REGNO (base); + + if (regno != FRAME_POINTER_REGNUM + && regno != STACK_POINTER_REGNUM) + { + /* Check if the compiler has recorded some information + about the alignment of the base REG. If reload has + completed, we already matched with proper alignments. */ + if (((regno_pointer_align != NULL + && REGNO_POINTER_ALIGN (regno) >= desired) + || reload_completed) + && ((INTVAL (offset) & (desired - 1)) == 0)) + return 1; + } + else + { + if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) + return 1; + } + } + else if (! TARGET_UNALIGNED_DOUBLES + || CONSTANT_P (addr) + || GET_CODE (addr) == LO_SUM) + { + /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES + is true, in which case we can only assume that an access is aligned if + it is to a constant address, or the address involves a LO_SUM. */ + return 1; + } + + /* An obviously unaligned address. */ + return 0; +} + + +/* Vectors to keep interesting information about registers where it can easily + be got. We use to use the actual mode value as the bit number, but there + are more than 32 modes now. Instead we use two tables: one indexed by + hard register number, and one indexed by mode. */ + +/* The purpose of sparc_mode_class is to shrink the range of modes so that + they all fit (as bit numbers) in a 32 bit word (again). Each real mode is + mapped into one sparc_mode_class mode. */ + +enum sparc_mode_class { + S_MODE, D_MODE, T_MODE, O_MODE, + SF_MODE, DF_MODE, TF_MODE, OF_MODE, + CC_MODE, CCFP_MODE +}; + +/* Modes for single-word and smaller quantities. */ +#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) + +/* Modes for double-word and smaller quantities. */ +#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) + +/* Modes for quad-word and smaller quantities. */ +#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) + +/* Modes for single-float quantities. We must allow any single word or + smaller quantity. This is because the fix/float conversion instructions + take integer inputs/outputs from the float registers. */ +#define SF_MODES (S_MODES) + +/* Modes for double-float and smaller quantities. */ +#define DF_MODES (S_MODES | D_MODES) + +#define DF_MODES64 DF_MODES + +/* Modes for double-float only quantities. */ +#define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE)) + +/* Modes for double-float and larger quantities. */ +#define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES) + +/* Modes for quad-float only quantities. */ +#define TF_ONLY_MODES (1 << (int) TF_MODE) + +/* Modes for quad-float and smaller quantities. */ +#define TF_MODES (DF_MODES | TF_ONLY_MODES) + +#define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES) + +/* Modes for condition codes. */ +#define CC_MODES (1 << (int) CC_MODE) +#define CCFP_MODES (1 << (int) CCFP_MODE) + +/* Value is 1 if register/mode pair is acceptable on sparc. + The funny mixture of D and T modes is because integer operations + do not specially operate on tetra quantities, so non-quad-aligned + registers can hold quadword quantities (except %o4 and %i4 because + they cross fixed registers). */ + +/* This points to either the 32 bit or the 64 bit version. */ +int *hard_regno_mode_classes; + +static int hard_32bit_mode_classes[] = { + S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, + T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, + T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, + T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, + + TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, + TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, + TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, + TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, + + /* FP regs f32 to f63. Only the even numbered registers actually exist, + and none can hold SFmode/SImode values. */ + DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, + DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, + DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, + DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, + + /* %fcc[0123] */ + CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, + + /* %icc */ + CC_MODES +}; + +static int hard_64bit_mode_classes[] = { + D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, + T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, + T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, + T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, + + TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, + TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, + TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, + TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, + + /* FP regs f32 to f63. Only the even numbered registers actually exist, + and none can hold SFmode/SImode values. */ + DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, + DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, + DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, + DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, + + /* %fcc[0123] */ + CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, + + /* %icc */ + CC_MODES +}; + +int sparc_mode_class [NUM_MACHINE_MODES]; + +enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; + +static void +sparc_init_modes () +{ + int i; + + for (i = 0; i < NUM_MACHINE_MODES; i++) + { + switch (GET_MODE_CLASS (i)) + { + case MODE_INT: + case MODE_PARTIAL_INT: + case MODE_COMPLEX_INT: + if (GET_MODE_SIZE (i) <= 4) + sparc_mode_class[i] = 1 << (int) S_MODE; + else if (GET_MODE_SIZE (i) == 8) + sparc_mode_class[i] = 1 << (int) D_MODE; + else if (GET_MODE_SIZE (i) == 16) + sparc_mode_class[i] = 1 << (int) T_MODE; + else if (GET_MODE_SIZE (i) == 32) + sparc_mode_class[i] = 1 << (int) O_MODE; + else + sparc_mode_class[i] = 0; + break; + case MODE_FLOAT: + case MODE_COMPLEX_FLOAT: + if (GET_MODE_SIZE (i) <= 4) + sparc_mode_class[i] = 1 << (int) SF_MODE; + else if (GET_MODE_SIZE (i) == 8) + sparc_mode_class[i] = 1 << (int) DF_MODE; + else if (GET_MODE_SIZE (i) == 16) + sparc_mode_class[i] = 1 << (int) TF_MODE; + else if (GET_MODE_SIZE (i) == 32) + sparc_mode_class[i] = 1 << (int) OF_MODE; + else + sparc_mode_class[i] = 0; + break; + case MODE_CC: + default: + /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so + we must explicitly check for them here. */ + if (i == (int) CCFPmode || i == (int) CCFPEmode) + sparc_mode_class[i] = 1 << (int) CCFP_MODE; + else if (i == (int) CCmode || i == (int) CC_NOOVmode + || i == (int) CCXmode || i == (int) CCX_NOOVmode) + sparc_mode_class[i] = 1 << (int) CC_MODE; + else + sparc_mode_class[i] = 0; + break; + } + } + + if (TARGET_ARCH64) + hard_regno_mode_classes = hard_64bit_mode_classes; + else + hard_regno_mode_classes = hard_32bit_mode_classes; + + /* Initialize the array used by REGNO_REG_CLASS. */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (i < 16 && TARGET_V8PLUS) + sparc_regno_reg_class[i] = I64_REGS; + else if (i < 32) + sparc_regno_reg_class[i] = GENERAL_REGS; + else if (i < 64) + sparc_regno_reg_class[i] = FP_REGS; + else if (i < 96) + sparc_regno_reg_class[i] = EXTRA_FP_REGS; + else if (i < 100) + sparc_regno_reg_class[i] = FPCC_REGS; + else + sparc_regno_reg_class[i] = NO_REGS; + } +} + +/* Save non call used registers from LOW to HIGH at BASE+OFFSET. + N_REGS is the number of 4-byte regs saved thus far. This applies even to + v9 int regs as it simplifies the code. */ + +static int +save_regs (file, low, high, base, offset, n_regs, real_offset) + FILE *file; + int low, high; + const char *base; + int offset; + int n_regs; + int real_offset; +{ + int i; + + if (TARGET_ARCH64 && high <= 32) + { + for (i = low; i < high; i++) + { + if (regs_ever_live[i] && ! call_used_regs[i]) + { + fprintf (file, "\tstx\t%s, [%s+%d]\n", + reg_names[i], base, offset + 4 * n_regs); + if (dwarf2out_do_frame ()) + dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); + n_regs += 2; + } + } + } + else + { + for (i = low; i < high; i += 2) + { + if (regs_ever_live[i] && ! call_used_regs[i]) + { + if (regs_ever_live[i+1] && ! call_used_regs[i+1]) + { + fprintf (file, "\tstd\t%s, [%s+%d]\n", + reg_names[i], base, offset + 4 * n_regs); + if (dwarf2out_do_frame ()) + { + char *l = dwarf2out_cfi_label (); + dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); + dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); + } + n_regs += 2; + } + else + { + fprintf (file, "\tst\t%s, [%s+%d]\n", + reg_names[i], base, offset + 4 * n_regs); + if (dwarf2out_do_frame ()) + dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); + n_regs += 2; + } + } + else + { + if (regs_ever_live[i+1] && ! call_used_regs[i+1]) + { + fprintf (file, "\tst\t%s, [%s+%d]\n", + reg_names[i+1], base, offset + 4 * n_regs + 4); + if (dwarf2out_do_frame ()) + dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); + n_regs += 2; + } + } + } + } + return n_regs; +} + +/* Restore non call used registers from LOW to HIGH at BASE+OFFSET. + + N_REGS is the number of 4-byte regs saved thus far. This applies even to + v9 int regs as it simplifies the code. */ + +static int +restore_regs (file, low, high, base, offset, n_regs) + FILE *file; + int low, high; + const char *base; + int offset; + int n_regs; +{ + int i; + + if (TARGET_ARCH64 && high <= 32) + { + for (i = low; i < high; i++) + { + if (regs_ever_live[i] && ! call_used_regs[i]) + fprintf (file, "\tldx\t[%s+%d], %s\n", + base, offset + 4 * n_regs, reg_names[i]), + n_regs += 2; + } + } + else + { + for (i = low; i < high; i += 2) + { + if (regs_ever_live[i] && ! call_used_regs[i]) + if (regs_ever_live[i+1] && ! call_used_regs[i+1]) + fprintf (file, "\tldd\t[%s+%d], %s\n", + base, offset + 4 * n_regs, reg_names[i]), + n_regs += 2; + else + fprintf (file, "\tld\t[%s+%d],%s\n", + base, offset + 4 * n_regs, reg_names[i]), + n_regs += 2; + else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) + fprintf (file, "\tld\t[%s+%d],%s\n", + base, offset + 4 * n_regs + 4, reg_names[i+1]), + n_regs += 2; + } + } + return n_regs; +} + +/* Static variables we want to share between prologue and epilogue. */ + +/* Number of live general or floating point registers needed to be saved + (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */ +static int num_gfregs; + +/* Compute the frame size required by the function. This function is called + during the reload pass and also by output_function_prologue(). */ + +int +compute_frame_size (size, leaf_function) + int size; + int leaf_function; +{ + int n_regs = 0, i; + int outgoing_args_size = (current_function_outgoing_args_size + + REG_PARM_STACK_SPACE (current_function_decl)); + + if (TARGET_EPILOGUE) + { + /* N_REGS is the number of 4-byte regs saved thus far. This applies + even to v9 int regs to be consistent with save_regs/restore_regs. */ + + if (TARGET_ARCH64) + { + for (i = 0; i < 8; i++) + if (regs_ever_live[i] && ! call_used_regs[i]) + n_regs += 2; + } + else + { + for (i = 0; i < 8; i += 2) + if ((regs_ever_live[i] && ! call_used_regs[i]) + || (regs_ever_live[i+1] && ! call_used_regs[i+1])) + n_regs += 2; + } + + for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) + if ((regs_ever_live[i] && ! call_used_regs[i]) + || (regs_ever_live[i+1] && ! call_used_regs[i+1])) + n_regs += 2; + } + + /* Set up values for use in `function_epilogue'. */ + num_gfregs = n_regs; + + if (leaf_function && n_regs == 0 + && size == 0 && current_function_outgoing_args_size == 0) + { + actual_fsize = apparent_fsize = 0; + } + else + { + /* We subtract STARTING_FRAME_OFFSET, remember it's negative. + The stack bias (if any) is taken out to undo its effects. */ + apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8; + apparent_fsize += n_regs * 4; + actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); + } + + /* Make sure nothing can clobber our register windows. + If a SAVE must be done, or there is a stack-local variable, + the register window area must be allocated. + ??? For v8 we apparently need an additional 8 bytes of reserved space. */ + if (leaf_function == 0 || size > 0) + actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); + + return SPARC_STACK_ALIGN (actual_fsize); +} + +/* Build a (32 bit) big number in a register. */ +/* ??? We may be able to use the set macro here too. */ + +static void +build_big_number (file, num, reg) + FILE *file; + int num; + const char *reg; +{ + if (num >= 0 || ! TARGET_ARCH64) + { + fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); + if ((num & 0x3ff) != 0) + fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); + } + else /* num < 0 && TARGET_ARCH64 */ + { + /* Sethi does not sign extend, so we must use a little trickery + to use it for negative numbers. Invert the constant before + loading it in, then use xor immediate to invert the loaded bits + (along with the upper 32 bits) to the desired constant. This + works because the sethi and immediate fields overlap. */ + int asize = num; + int inv = ~asize; + int low = -0x400 + (asize & 0x3FF); + + fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", + inv, reg, reg, low, reg); + } +} + +/* Output code for the function prologue. */ + +void +output_function_prologue (file, size, leaf_function) + FILE *file; + int size; + int leaf_function; +{ + /* Need to use actual_fsize, since we are also allocating + space for our callee (and our own register save area). */ + actual_fsize = compute_frame_size (size, leaf_function); + + if (leaf_function) + { + frame_base_name = "%sp"; + frame_base_offset = actual_fsize + SPARC_STACK_BIAS; + } + else + { + frame_base_name = "%fp"; + frame_base_offset = SPARC_STACK_BIAS; + } + + /* This is only for the human reader. */ + fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); + + if (actual_fsize == 0) + /* do nothing. */ ; + else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE) + { + if (actual_fsize <= 4096) + fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); + else if (actual_fsize <= 8192) + { + fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); + fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); + } + else + { + build_big_number (file, -actual_fsize, "%g1"); + fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); + } + } + else if (! leaf_function && TARGET_BROKEN_SAVERESTORE) + { + /* We assume the environment will properly handle or otherwise avoid + trouble associated with an interrupt occurring after the `save' or + trap occurring during it. */ + fprintf (file, "\tsave\n"); + + if (actual_fsize <= 4096) + fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize); + else if (actual_fsize <= 8192) + { + fprintf (file, "\tadd\t%%fp, -4096, %%sp\n"); + fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096); + } + else + { + build_big_number (file, -actual_fsize, "%g1"); + fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n"); + } + } + else /* leaf function */ + { + if (actual_fsize <= 4096) + fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); + else if (actual_fsize <= 8192) + { + fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); + fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); + } + else + { + build_big_number (file, -actual_fsize, "%g1"); + fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); + } + } + + if (dwarf2out_do_frame () && actual_fsize) + { + char *label = dwarf2out_cfi_label (); + + /* The canonical frame address refers to the top of the frame. */ + dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM + : FRAME_POINTER_REGNUM), + frame_base_offset); + + if (! leaf_function) + { + /* Note the register window save. This tells the unwinder that + it needs to restore the window registers from the previous + frame's window save area at 0(cfa). */ + dwarf2out_window_save (label); + + /* The return address (-8) is now in %i7. */ + dwarf2out_return_reg (label, 31); + } + } + + /* If doing anything with PIC, do it now. */ + if (! flag_pic) + fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); + + /* Call saved registers are saved just above the outgoing argument area. */ + if (num_gfregs) + { + int offset, real_offset, n_regs; + const char *base; + + real_offset = -apparent_fsize; + offset = -apparent_fsize + frame_base_offset; + if (offset < -4096 || offset + num_gfregs * 4 > 4096) + { + /* ??? This might be optimized a little as %g1 might already have a + value close enough that a single add insn will do. */ + /* ??? Although, all of this is probably only a temporary fix + because if %g1 can hold a function result, then + output_function_epilogue will lose (the result will get + clobbered). */ + build_big_number (file, offset, "%g1"); + fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); + base = "%g1"; + offset = 0; + } + else + { + base = frame_base_name; + } + + n_regs = 0; + if (TARGET_EPILOGUE && ! leaf_function) + /* ??? Originally saved regs 0-15 here. */ + n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); + else if (leaf_function) + /* ??? Originally saved regs 0-31 here. */ + n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); + if (TARGET_EPILOGUE) + save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, + real_offset); + } + + leaf_label = 0; + if (leaf_function && actual_fsize != 0) + { + /* warning ("leaf procedure with frame size %d", actual_fsize); */ + if (! TARGET_EPILOGUE) + leaf_label = gen_label_rtx (); + } +} + +/* Output code for the function epilogue. */ + +void +output_function_epilogue (file, size, leaf_function) + FILE *file; + int size ATTRIBUTE_UNUSED; + int leaf_function; +{ + const char *ret; + + if (leaf_label) + { + emit_label_after (leaf_label, get_last_insn ()); + final_scan_insn (get_last_insn (), file, 0, 0, 1); + } + +#ifdef FUNCTION_BLOCK_PROFILER_EXIT + else if (profile_block_flag == 2) + { + FUNCTION_BLOCK_PROFILER_EXIT(file); + } +#endif + + else if (current_function_epilogue_delay_list == 0) + { + /* If code does not drop into the epilogue, we need + do nothing except output pending case vectors. */ + rtx insn = get_last_insn (); + if (GET_CODE (insn) == NOTE) + insn = prev_nonnote_insn (insn); + if (insn && GET_CODE (insn) == BARRIER) + goto output_vectors; + } + + /* Restore any call saved registers. */ + if (num_gfregs) + { + int offset, n_regs; + const char *base; + + offset = -apparent_fsize + frame_base_offset; + if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) + { + build_big_number (file, offset, "%g1"); + fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); + base = "%g1"; + offset = 0; + } + else + { + base = frame_base_name; + } + + n_regs = 0; + if (TARGET_EPILOGUE && ! leaf_function) + /* ??? Originally saved regs 0-15 here. */ + n_regs = restore_regs (file, 0, 8, base, offset, 0); + else if (leaf_function) + /* ??? Originally saved regs 0-31 here. */ + n_regs = restore_regs (file, 0, 8, base, offset, 0); + if (TARGET_EPILOGUE) + restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); + } + + /* Work out how to skip the caller's unimp instruction if required. */ + if (leaf_function) + ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); + else + ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); + + if (TARGET_EPILOGUE || leaf_label) + { + int old_target_epilogue = TARGET_EPILOGUE; + target_flags &= ~old_target_epilogue; + + if (! leaf_function) + { + /* If we wound up with things in our delay slot, flush them here. */ + if (current_function_epilogue_delay_list) + { + rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode), + get_last_insn ()); + PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, + PATTERN (XEXP (current_function_epilogue_delay_list, 0)), + PATTERN (insn))); + final_scan_insn (insn, file, 1, 0, 1); + } + else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) + fputs ("\treturn\t%i7+8\n\tnop\n", file); + else + fprintf (file, "\t%s\n\trestore\n", ret); + } + /* All of the following cases are for leaf functions. */ + else if (current_function_epilogue_delay_list) + { + /* eligible_for_epilogue_delay_slot ensures that if this is a + leaf function, then we will only have insn in the delay slot + if the frame size is zero, thus no adjust for the stack is + needed here. */ + if (actual_fsize != 0) + abort (); + fprintf (file, "\t%s\n", ret); + final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), + file, 1, 0, 1); + } + /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to + avoid generating confusing assembly language output. */ + else if (actual_fsize == 0) + fprintf (file, "\t%s\n\tnop\n", ret); + else if (actual_fsize <= 4096) + fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); + else if (actual_fsize <= 8192) + fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", + ret, actual_fsize - 4096); + else if ((actual_fsize & 0x3ff) == 0) + fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", + actual_fsize, ret); + else + fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", + actual_fsize, actual_fsize, ret); + target_flags |= old_target_epilogue; + } + + output_vectors: + sparc_output_deferred_case_vectors (); +} + +/* Functions for handling argument passing. + + For v8 the first six args are normally in registers and the rest are + pushed. Any arg that starts within the first 6 words is at least + partially passed in a register unless its data type forbids. + + For v9, the argument registers are laid out as an array of 16 elements + and arguments are added sequentially. The first 6 int args and up to the + first 16 fp args (depending on size) are passed in regs. + + Slot Stack Integral Float Float in structure Double Long Double + ---- ----- -------- ----- ------------------ ------ ----------- + 15 [SP+248] %f31 %f30,%f31 %d30 + 14 [SP+240] %f29 %f28,%f29 %d28 %q28 + 13 [SP+232] %f27 %f26,%f27 %d26 + 12 [SP+224] %f25 %f24,%f25 %d24 %q24 + 11 [SP+216] %f23 %f22,%f23 %d22 + 10 [SP+208] %f21 %f20,%f21 %d20 %q20 + 9 [SP+200] %f19 %f18,%f19 %d18 + 8 [SP+192] %f17 %f16,%f17 %d16 %q16 + 7 [SP+184] %f15 %f14,%f15 %d14 + 6 [SP+176] %f13 %f12,%f13 %d12 %q12 + 5 [SP+168] %o5 %f11 %f10,%f11 %d10 + 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 + 3 [SP+152] %o3 %f7 %f6,%f7 %d6 + 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 + 1 [SP+136] %o1 %f3 %f2,%f3 %d2 + 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 + + Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. + + Integral arguments are always passed as 64 bit quantities appropriately + extended. + + Passing of floating point values is handled as follows. + If a prototype is in scope: + If the value is in a named argument (i.e. not a stdarg function or a + value not part of the `...') then the value is passed in the appropriate + fp reg. + If the value is part of the `...' and is passed in one of the first 6 + slots then the value is passed in the appropriate int reg. + If the value is part of the `...' and is not passed in one of the first 6 + slots then the value is passed in memory. + If a prototype is not in scope: + If the value is one of the first 6 arguments the value is passed in the + appropriate integer reg and the appropriate fp reg. + If the value is not one of the first 6 arguments the value is passed in + the appropriate fp reg and in memory. + */ + +/* Maximum number of int regs for args. */ +#define SPARC_INT_ARG_MAX 6 +/* Maximum number of fp regs for args. */ +#define SPARC_FP_ARG_MAX 16 + +#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +/* Handle the INIT_CUMULATIVE_ARGS macro. + Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. */ + +void +init_cumulative_args (cum, fntype, libname, indirect) + CUMULATIVE_ARGS *cum; + tree fntype; + tree libname ATTRIBUTE_UNUSED; + int indirect ATTRIBUTE_UNUSED; +{ + cum->words = 0; + cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); + cum->libcall_p = fntype == 0; +} + +/* Compute the slot number to pass an argument in. + Returns the slot number or -1 if passing on the stack. + + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). + INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. + *PREGNO records the register number to use if scalar type. + *PPADDING records the amount of padding needed in words. */ + +static int +function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) + const CUMULATIVE_ARGS *cum; + enum machine_mode mode; + tree type; + int named; + int incoming_p; + int *pregno; + int *ppadding; +{ + int regbase = (incoming_p + ? SPARC_INCOMING_INT_ARG_FIRST + : SPARC_OUTGOING_INT_ARG_FIRST); + int slotno = cum->words; + int regno; + + *ppadding = 0; + + if (type != 0 && TREE_ADDRESSABLE (type)) + return -1; + if (TARGET_ARCH32 + && type != 0 && mode == BLKmode + && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) + return -1; + + switch (mode) + { + case VOIDmode : + /* MODE is VOIDmode when generating the actual call. + See emit_call_1. */ + return -1; + + case QImode : case CQImode : + case HImode : case CHImode : + case SImode : case CSImode : + case DImode : case CDImode : + if (slotno >= SPARC_INT_ARG_MAX) + return -1; + regno = regbase + slotno; + break; + + case SFmode : case SCmode : + case DFmode : case DCmode : + case TFmode : case TCmode : + if (TARGET_ARCH32) + { + if (slotno >= SPARC_INT_ARG_MAX) + return -1; + regno = regbase + slotno; + } + else + { + if ((mode == TFmode || mode == TCmode) + && (slotno & 1) != 0) + slotno++, *ppadding = 1; + if (TARGET_FPU && named) + { + if (slotno >= SPARC_FP_ARG_MAX) + return -1; + regno = SPARC_FP_ARG_FIRST + slotno * 2; + if (mode == SFmode) + regno++; + } + else + { + if (slotno >= SPARC_INT_ARG_MAX) + return -1; + regno = regbase + slotno; + } + } + break; + + case BLKmode : + /* For sparc64, objects requiring 16 byte alignment get it. */ + if (TARGET_ARCH64) + { + if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) + slotno++, *ppadding = 1; + } + + if (TARGET_ARCH32 + || (type && TREE_CODE (type) == UNION_TYPE)) + { + if (slotno >= SPARC_INT_ARG_MAX) + return -1; + regno = regbase + slotno; + } + else + { + tree field; + int intregs_p = 0, fpregs_p = 0; + /* The ABI obviously doesn't specify how packed + structures are passed. These are defined to be passed + in int regs if possible, otherwise memory. */ + int packed_p = 0; + + /* First see what kinds of registers we need. */ + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) == FIELD_DECL) + { + if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE + && TARGET_FPU) + fpregs_p = 1; + else + intregs_p = 1; + if (DECL_PACKED (field)) + packed_p = 1; + } + } + if (packed_p || !named) + fpregs_p = 0, intregs_p = 1; + + /* If all arg slots are filled, then must pass on stack. */ + if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) + return -1; + /* If there are only int args and all int arg slots are filled, + then must pass on stack. */ + if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) + return -1; + /* Note that even if all int arg slots are filled, fp members may + still be passed in regs if such regs are available. + *PREGNO isn't set because there may be more than one, it's up + to the caller to compute them. */ + return slotno; + } + break; + + default : + abort (); + } + + *pregno = regno; + return slotno; +} + +/* Handle recursive register counting for structure field layout. */ + +struct function_arg_record_value_parms +{ + rtx ret; + int slotno, named, regbase; + int nregs, intoffset; +}; + +static void function_arg_record_value_3 + PROTO((int, struct function_arg_record_value_parms *)); +static void function_arg_record_value_2 + PROTO((tree, int, struct function_arg_record_value_parms *)); +static rtx function_arg_record_value + PROTO((tree, enum machine_mode, int, int, int)); + +static void +function_arg_record_value_1 (type, startbitpos, parms) + tree type; + int startbitpos; + struct function_arg_record_value_parms *parms; +{ + tree field; + + /* The ABI obviously doesn't specify how packed structures are + passed. These are defined to be passed in int regs if possible, + otherwise memory. */ + int packed_p = 0; + + /* We need to compute how many registers are needed so we can + allocate the PARALLEL but before we can do that we need to know + whether there are any packed fields. If there are, int regs are + used regardless of whether there are fp values present. */ + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) + { + packed_p = 1; + break; + } + } + + /* Compute how many registers we need. */ + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) == FIELD_DECL) + { + int bitpos = startbitpos; + if (DECL_FIELD_BITPOS (field)) + bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); + /* ??? FIXME: else assume zero offset. */ + + if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) + { + function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); + } + else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE + && TARGET_FPU + && ! packed_p + && parms->named) + { + if (parms->intoffset != -1) + { + int intslots, this_slotno; + + intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) + / BITS_PER_WORD; + this_slotno = parms->slotno + parms->intoffset + / BITS_PER_WORD; + + intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); + intslots = MAX (intslots, 0); + parms->nregs += intslots; + parms->intoffset = -1; + } + + /* There's no need to check this_slotno < SPARC_FP_ARG MAX. + If it wasn't true we wouldn't be here. */ + parms->nregs += 1; + } + else + { + if (parms->intoffset == -1) + parms->intoffset = bitpos; + } + } + } +} + +/* Handle recursive structure field register assignment. */ + +static void +function_arg_record_value_3 (bitpos, parms) + int bitpos; + struct function_arg_record_value_parms *parms; +{ + enum machine_mode mode; + int regno, this_slotno, intslots, intoffset; + rtx reg; + + if (parms->intoffset == -1) + return; + intoffset = parms->intoffset; + parms->intoffset = -1; + + intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD; + this_slotno = parms->slotno + intoffset / BITS_PER_WORD; + + intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); + if (intslots <= 0) + return; + + /* If this is the trailing part of a word, only load that much into + the register. Otherwise load the whole register. Note that in + the latter case we may pick up unwanted bits. It's not a problem + at the moment but may wish to revisit. */ + + if (intoffset % BITS_PER_WORD != 0) + { + mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD, + MODE_INT, 0); + } + else + mode = word_mode; + + intoffset /= BITS_PER_UNIT; + do + { + regno = parms->regbase + this_slotno; + reg = gen_rtx_REG (mode, regno); + XVECEXP (parms->ret, 0, parms->nregs) + = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); + + this_slotno += 1; + intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; + parms->nregs += 1; + intslots -= 1; + } + while (intslots > 0); +} + +static void +function_arg_record_value_2 (type, startbitpos, parms) + tree type; + int startbitpos; + struct function_arg_record_value_parms *parms; +{ + tree field; + int packed_p = 0; + + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) + { + packed_p = 1; + break; + } + } + + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) == FIELD_DECL) + { + int bitpos = startbitpos; + if (DECL_FIELD_BITPOS (field)) + bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); + /* ??? FIXME: else assume zero offset. */ + + if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) + { + function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); + } + else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE + && TARGET_FPU + && ! packed_p + && parms->named) + { + int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; + rtx reg; + + function_arg_record_value_3 (bitpos, parms); + + reg = gen_rtx_REG (DECL_MODE (field), + (SPARC_FP_ARG_FIRST + this_slotno * 2 + + (DECL_MODE (field) == SFmode + && (bitpos & 32) != 0))); + XVECEXP (parms->ret, 0, parms->nregs) + = gen_rtx_EXPR_LIST (VOIDmode, reg, + GEN_INT (bitpos / BITS_PER_UNIT)); + parms->nregs += 1; + } + else + { + if (parms->intoffset == -1) + parms->intoffset = bitpos; + } + } + } +} + +static rtx +function_arg_record_value (type, mode, slotno, named, regbase) + tree type; + enum machine_mode mode; + int slotno, named, regbase; +{ + HOST_WIDE_INT typesize = int_size_in_bytes (type); + struct function_arg_record_value_parms parms; + int nregs; + + parms.ret = NULL_RTX; + parms.slotno = slotno; + parms.named = named; + parms.regbase = regbase; + + /* Compute how many registers we need. */ + parms.nregs = 0; + parms.intoffset = 0; + function_arg_record_value_1 (type, 0, &parms); + + if (parms.intoffset != -1) + { + int intslots, this_slotno; + + intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1) + / BITS_PER_WORD; + this_slotno = slotno + parms.intoffset / BITS_PER_WORD; + + intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); + intslots = MAX (intslots, 0); + + parms.nregs += intslots; + } + nregs = parms.nregs; + + /* Allocate the vector and handle some annoying special cases. */ + if (nregs == 0) + { + /* ??? Empty structure has no value? Duh? */ + if (typesize <= 0) + { + /* Though there's nothing really to store, return a word register + anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL + leads to breakage due to the fact that there are zero bytes to + load. */ + return gen_rtx_REG (mode, regbase); + } + else + { + /* ??? C++ has structures with no fields, and yet a size. Give up + for now and pass everything back in integer registers. */ + nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + } + if (nregs + slotno > SPARC_INT_ARG_MAX) + nregs = SPARC_INT_ARG_MAX - slotno; + } + if (nregs == 0) + abort (); + + parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); + + /* Fill in the entries. */ + parms.nregs = 0; + parms.intoffset = 0; + function_arg_record_value_2 (type, 0, &parms); + function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); + + if (parms.nregs != nregs) + abort (); + + return parms.ret; +} + +/* Handle the FUNCTION_ARG macro. + Determine where to put an argument to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). + INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ + +rtx +function_arg (cum, mode, type, named, incoming_p) + const CUMULATIVE_ARGS *cum; + enum machine_mode mode; + tree type; + int named; + int incoming_p; +{ + int regbase = (incoming_p + ? SPARC_INCOMING_INT_ARG_FIRST + : SPARC_OUTGOING_INT_ARG_FIRST); + int slotno, regno, padding; + rtx reg; + + slotno = function_arg_slotno (cum, mode, type, named, incoming_p, + ®no, &padding); + + if (slotno == -1) + return 0; + + if (TARGET_ARCH32) + { + reg = gen_rtx_REG (mode, regno); + return reg; + } + + /* v9 fp args in reg slots beyond the int reg slots get passed in regs + but also have the slot allocated for them. + If no prototype is in scope fp values in register slots get passed + in two places, either fp regs and int regs or fp regs and memory. */ + if ((GET_MODE_CLASS (mode) == MODE_FLOAT + || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) + && SPARC_FP_REG_P (regno)) + { + reg = gen_rtx_REG (mode, regno); + if (cum->prototype_p || cum->libcall_p) + { + /* "* 2" because fp reg numbers are recorded in 4 byte + quantities. */ +#if 0 + /* ??? This will cause the value to be passed in the fp reg and + in the stack. When a prototype exists we want to pass the + value in the reg but reserve space on the stack. That's an + optimization, and is deferred [for a bit]. */ + if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) + return gen_rtx_PARALLEL (mode, + gen_rtvec (2, + gen_rtx_EXPR_LIST (VOIDmode, + NULL_RTX, const0_rtx), + gen_rtx_EXPR_LIST (VOIDmode, + reg, const0_rtx))); + else +#else + /* ??? It seems that passing back a register even when past + the area declared by REG_PARM_STACK_SPACE will allocate + space appropriately, and will not copy the data onto the + stack, exactly as we desire. + + This is due to locate_and_pad_parm being called in + expand_call whenever reg_parm_stack_space > 0, which + while benefical to our example here, would seem to be + in error from what had been intended. Ho hum... -- r~ */ +#endif + return reg; + } + else + { + rtx v0, v1; + + if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) + { + int intreg; + + /* On incoming, we don't need to know that the value + is passed in %f0 and %i0, and it confuses other parts + causing needless spillage even on the simplest cases. */ + if (incoming_p) + return reg; + + intreg = (SPARC_OUTGOING_INT_ARG_FIRST + + (regno - SPARC_FP_ARG_FIRST) / 2); + + v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); + v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), + const0_rtx); + return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); + } + else + { + v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); + v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); + return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); + } + } + } + else if (type && TREE_CODE (type) == RECORD_TYPE) + { + /* Structures up to 16 bytes in size are passed in arg slots on the + stack and are promoted to registers where possible. */ + + if (int_size_in_bytes (type) > 16) + abort (); /* shouldn't get here */ + + return function_arg_record_value (type, mode, slotno, named, regbase); + } + else if (type && TREE_CODE (type) == UNION_TYPE) + { + enum machine_mode mode; + int bytes = int_size_in_bytes (type); + + if (bytes > 16) + abort (); + + mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); + reg = gen_rtx_REG (mode, regno); + } + else + { + /* Scalar or complex int. */ + reg = gen_rtx_REG (mode, regno); + } + + return reg; +} + +/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. + For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. + + Any arg that starts in the first 6 regs but won't entirely fit in them + needs partial registers on v8. On v9, structures with integer + values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp + values that begin in the last fp reg [where "last fp reg" varies with the + mode] will be split between that reg and memory. */ + +int +function_arg_partial_nregs (cum, mode, type, named) + const CUMULATIVE_ARGS *cum; + enum machine_mode mode; + tree type; + int named; +{ + int slotno, regno, padding; + + /* We pass 0 for incoming_p here, it doesn't matter. */ + slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); + + if (slotno == -1) + return 0; + + if (TARGET_ARCH32) + { + if ((slotno + (mode == BLKmode + ? ROUND_ADVANCE (int_size_in_bytes (type)) + : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) + > NPARM_REGS (SImode)) + return NPARM_REGS (SImode) - slotno; + return 0; + } + else + { + if (type && AGGREGATE_TYPE_P (type)) + { + int size = int_size_in_bytes (type); + int align = TYPE_ALIGN (type); + + if (align == 16) + slotno += slotno & 1; + if (size > 8 && size <= 16 + && slotno == SPARC_INT_ARG_MAX - 1) + return 1; + } + else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT + || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT + && ! TARGET_FPU)) + { + if (GET_MODE_ALIGNMENT (mode) == 128) + { + slotno += slotno & 1; + if (slotno == SPARC_INT_ARG_MAX - 2) + return 1; + } + else + { + if (slotno == SPARC_INT_ARG_MAX - 1) + return 1; + } + } + else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) + { + if (GET_MODE_ALIGNMENT (mode) == 128) + slotno += slotno & 1; + if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) + > SPARC_FP_ARG_MAX) + return 1; + } + return 0; + } +} + +/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. + !v9: The SPARC ABI stipulates passing struct arguments (of any size) and + quad-precision floats by invisible reference. + v9: Aggregates greater than 16 bytes are passed by reference. + For Pascal, also pass arrays by reference. */ + +int +function_arg_pass_by_reference (cum, mode, type, named) + const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; + enum machine_mode mode; + tree type; + int named ATTRIBUTE_UNUSED; +{ + if (TARGET_ARCH32) + { + return ((type && AGGREGATE_TYPE_P (type)) + || mode == TFmode || mode == TCmode); + } + else + { + return ((type && TREE_CODE (type) == ARRAY_TYPE) + /* Consider complex values as aggregates, so care for TCmode. */ + || GET_MODE_SIZE (mode) > 16 + || (type && AGGREGATE_TYPE_P (type) + && int_size_in_bytes (type) > 16)); + } +} + +/* Handle the FUNCTION_ARG_ADVANCE macro. + Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + TYPE is null for libcalls where that information may not be available. */ + +void +function_arg_advance (cum, mode, type, named) + CUMULATIVE_ARGS *cum; + enum machine_mode mode; + tree type; + int named; +{ + int slotno, regno, padding; + + /* We pass 0 for incoming_p here, it doesn't matter. */ + slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); + + /* If register required leading padding, add it. */ + if (slotno != -1) + cum->words += padding; + + if (TARGET_ARCH32) + { + cum->words += (mode != BLKmode + ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) + : ROUND_ADVANCE (int_size_in_bytes (type))); + } + else + { + if (type && AGGREGATE_TYPE_P (type)) + { + int size = int_size_in_bytes (type); + + if (size <= 8) + ++cum->words; + else if (size <= 16) + cum->words += 2; + else /* passed by reference */ + ++cum->words; + } + else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) + { + cum->words += 2; + } + else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) + { + cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; + } + else + { + cum->words += (mode != BLKmode + ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) + : ROUND_ADVANCE (int_size_in_bytes (type))); + } + } +} + +/* Handle the FUNCTION_ARG_PADDING macro. + For the 64 bit ABI structs are always stored left shifted in their + argument slot. */ + +enum direction +function_arg_padding (mode, type) + enum machine_mode mode; + tree type; +{ + if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) + return upward; + + /* This is the default definition. */ + return (! BYTES_BIG_ENDIAN + ? upward + : ((mode == BLKmode + ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST + && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) + : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) + ? downward : upward)); +} + +/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. + For v9, function return values are subject to the same rules as arguments, + except that up to 32-bytes may be returned in registers. */ + +rtx +function_value (type, mode, incoming_p) + tree type; + enum machine_mode mode; + int incoming_p; +{ + int regno; + int regbase = (incoming_p + ? SPARC_OUTGOING_INT_ARG_FIRST + : SPARC_INCOMING_INT_ARG_FIRST); + + if (TARGET_ARCH64 && type) + { + if (TREE_CODE (type) == RECORD_TYPE) + { + /* Structures up to 32 bytes in size are passed in registers, + promoted to fp registers where possible. */ + + if (int_size_in_bytes (type) > 32) + abort (); /* shouldn't get here */ + + return function_arg_record_value (type, mode, 0, 1, regbase); + } + else if (TREE_CODE (type) == UNION_TYPE) + { + int bytes = int_size_in_bytes (type); + + if (bytes > 32) + abort (); + + mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); + } + } + + if (TARGET_ARCH64 + && GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) < UNITS_PER_WORD + && type && TREE_CODE (type) != UNION_TYPE) + mode = DImode; + + if (incoming_p) + regno = BASE_RETURN_VALUE_REG (mode); + else + regno = BASE_OUTGOING_VALUE_REG (mode); + + return gen_rtx_REG (mode, regno); +} + +/* Do what is necessary for `va_start'. The argument is ignored. + + We look at the current function to determine if stdarg or varargs + is used and return the address of the first unnamed parameter. */ + +rtx +sparc_builtin_saveregs (arglist) + tree arglist ATTRIBUTE_UNUSED; +{ + int first_reg = current_function_args_info.words; + rtx address; + int regno; + + for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) + emit_move_insn (gen_rtx_MEM (word_mode, + gen_rtx_PLUS (Pmode, + frame_pointer_rtx, + GEN_INT (STACK_POINTER_OFFSET + + UNITS_PER_WORD * regno))), + gen_rtx_REG (word_mode, + BASE_INCOMING_ARG_REG (word_mode) + regno)); + + address = gen_rtx_PLUS (Pmode, + frame_pointer_rtx, + GEN_INT (STACK_POINTER_OFFSET + + UNITS_PER_WORD * first_reg)); + + if (current_function_check_memory_usage + && first_reg < NPARM_REGS (word_mode)) + emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, + address, ptr_mode, + GEN_INT (UNITS_PER_WORD + * (NPARM_REGS (word_mode) - first_reg)), + TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW), + TYPE_MODE (integer_type_node)); + + return address; +} + +/* Return the string to output a conditional branch to LABEL, which is + the operand number of the label. OP is the conditional expression. + XEXP (OP, 0) is assumed to be a condition code register (integer or + floating point) and its mode specifies what kind of comparison we made. + + REVERSED is non-zero if we should reverse the sense of the comparison. + + ANNUL is non-zero if we should generate an annulling branch. + + NOOP is non-zero if we have to follow this branch by a noop. + + INSN, if set, is the insn. */ + +char * +output_cbranch (op, label, reversed, annul, noop, insn) + rtx op; + int label; + int reversed, annul, noop; + rtx insn; +{ + static char string[32]; + enum rtx_code code = GET_CODE (op); + rtx cc_reg = XEXP (op, 0); + enum machine_mode mode = GET_MODE (cc_reg); + static char v8_labelno[] = "%lX"; + static char v9_icc_labelno[] = "%%icc, %lX"; + static char v9_xcc_labelno[] = "%%xcc, %lX"; + static char v9_fcc_labelno[] = "%%fccX, %lY"; + char *labelno; + int labeloff, spaces = 8; + + /* ??? !v9: FP branches cannot be preceded by another floating point insn. + Because there is currently no concept of pre-delay slots, we can fix + this only by always emitting a nop before a floating point branch. */ + + if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9) + strcpy (string, "nop\n\t"); + else + string[0] = '\0'; + + /* If not floating-point or if EQ or NE, we can just reverse the code. */ + if (reversed + && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE)) + code = reverse_condition (code), reversed = 0; + + /* Start by writing the branch condition. */ + switch (code) + { + case NE: + if (mode == CCFPmode || mode == CCFPEmode) + { + strcat (string, "fbne"); + spaces -= 4; + } + else + { + strcpy (string, "bne"); + spaces -= 3; + } + break; + + case EQ: + if (mode == CCFPmode || mode == CCFPEmode) + { + strcat (string, "fbe"); + spaces -= 3; + } + else + { + strcpy (string, "be"); + spaces -= 2; + } + break; + + case GE: + if (mode == CCFPmode || mode == CCFPEmode) + { + if (reversed) + strcat (string, "fbul"); + else + strcat (string, "fbge"); + spaces -= 4; + } + else if (mode == CC_NOOVmode) + { + strcpy (string, "bpos"); + spaces -= 4; + } + else + { + strcpy (string, "bge"); + spaces -= 3; + } + break; + + case GT: + if (mode == CCFPmode || mode == CCFPEmode) + { + if (reversed) + { + strcat (string, "fbule"); + spaces -= 5; + } + else + { + strcat (string, "fbg"); + spaces -= 3; + } + } + else + { + strcpy (string, "bg"); + spaces -= 2; + } + break; + + case LE: + if (mode == CCFPmode || mode == CCFPEmode) + { + if (reversed) + strcat (string, "fbug"); + else + strcat (string, "fble"); + spaces -= 4; + } + else + { + strcpy (string, "ble"); + spaces -= 3; + } + break; + + case LT: + if (mode == CCFPmode || mode == CCFPEmode) + { + if (reversed) + { + strcat (string, "fbuge"); + spaces -= 5; + } + else + { + strcat (string, "fbl"); + spaces -= 3; + } + } + else if (mode == CC_NOOVmode) + { + strcpy (string, "bneg"); + spaces -= 4; + } + else + { + strcpy (string, "bl"); + spaces -= 2; + } + break; + + case GEU: + strcpy (string, "bgeu"); + spaces -= 4; + break; + + case GTU: + strcpy (string, "bgu"); + spaces -= 3; + break; + + case LEU: + strcpy (string, "bleu"); + spaces -= 4; + break; + + case LTU: + strcpy (string, "blu"); + spaces -= 3; + break; + + default: + abort (); + } + + /* Now add the annulling, the label, and a possible noop. */ + if (annul) + { + strcat (string, ",a"); + spaces -= 2; + } + + if (! TARGET_V9) + { + labeloff = 2; + labelno = v8_labelno; + } + else + { + rtx note; + + if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) + { + strcat (string, + INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); + spaces -= 3; + } + + labeloff = 9; + if (mode == CCFPmode || mode == CCFPEmode) + { + labeloff = 10; + labelno = v9_fcc_labelno; + /* Set the char indicating the number of the fcc reg to use. */ + labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; + } + else if (mode == CCXmode || mode == CCX_NOOVmode) + labelno = v9_xcc_labelno; + else + labelno = v9_icc_labelno; + } + /* Set the char indicating the number of the operand containing the + label_ref. */ + labelno[labeloff] = label + '0'; + if (spaces > 0) + strcat (string, "\t"); + else + strcat (string, " "); + strcat (string, labelno); + + if (noop) + strcat (string, "\n\tnop"); + + return string; +} + +/* Return the string to output a conditional branch to LABEL, testing + register REG. LABEL is the operand number of the label; REG is the + operand number of the reg. OP is the conditional expression. The mode + of REG says what kind of comparison we made. + + REVERSED is non-zero if we should reverse the sense of the comparison. + + ANNUL is non-zero if we should generate an annulling branch. + + NOOP is non-zero if we have to follow this branch by a noop. */ + +char * +output_v9branch (op, reg, label, reversed, annul, noop, insn) + rtx op; + int reg, label; + int reversed, annul, noop; + rtx insn; +{ + static char string[20]; + enum rtx_code code = GET_CODE (op); + enum machine_mode mode = GET_MODE (XEXP (op, 0)); + static char labelno[] = "%X, %lX"; + rtx note; + int spaces = 8; + + /* If not floating-point or if EQ or NE, we can just reverse the code. */ + if (reversed) + code = reverse_condition (code), reversed = 0; + + /* Only 64 bit versions of these instructions exist. */ + if (mode != DImode) + abort (); + + /* Start by writing the branch condition. */ + + switch (code) + { + case NE: + strcpy (string, "brnz"); + spaces -= 4; + break; + + case EQ: + strcpy (string, "brz"); + spaces -= 3; + break; + + case GE: + strcpy (string, "brgez"); + spaces -= 5; + break; + + case LT: + strcpy (string, "brlz"); + spaces -= 4; + break; + + case LE: + strcpy (string, "brlez"); + spaces -= 5; + break; + + case GT: + strcpy (string, "brgz"); + spaces -= 4; + break; + + default: + abort (); + } + + /* Now add the annulling, reg, label, and nop. */ + if (annul) + { + strcat (string, ",a"); + spaces -= 2; + } + + if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) + { + strcat (string, + INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); + spaces -= 3; + } + + labelno[1] = reg + '0'; + labelno[6] = label + '0'; + if (spaces > 0) + strcat (string, "\t"); + else + strcat (string, " "); + strcat (string, labelno); + + if (noop) + strcat (string, "\n\tnop"); + + return string; +} + +/* Renumber registers in delay slot. Replace registers instead of + renumbering because they may be shared. + + This does not handle instructions other than move. */ + +static void +epilogue_renumber (where) + rtx *where; +{ + rtx x = *where; + enum rtx_code code = GET_CODE (x); + + switch (code) + { + case MEM: + *where = x = copy_rtx (x); + epilogue_renumber (&XEXP (x, 0)); + return; + + case REG: + { + int regno = REGNO (x); + if (regno > 8 && regno < 24) + abort (); + if (regno >= 24 && regno < 32) + *where = gen_rtx_REG (GET_MODE (x), regno - 16); + return; + } + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + return; + + case IOR: + case AND: + case XOR: + case PLUS: + case MINUS: + epilogue_renumber (&XEXP (x, 1)); + case NEG: + case NOT: + epilogue_renumber (&XEXP (x, 0)); + return; + + default: + debug_rtx (*where); + abort (); + } +} + +/* Output assembler code to return from a function. */ + +const char * +output_return (operands) + rtx *operands; +{ + rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0; + + if (leaf_label) + { + operands[0] = leaf_label; + return "b%* %l0%("; + } + else if (current_function_uses_only_leaf_regs) + { + /* No delay slot in a leaf function. */ + if (delay) + abort (); + + /* If we didn't allocate a frame pointer for the current function, + the stack pointer might have been adjusted. Output code to + restore it now. */ + + operands[0] = GEN_INT (actual_fsize); + + /* Use sub of negated value in first two cases instead of add to + allow actual_fsize == 4096. */ + + if (actual_fsize <= 4096) + { + if (SKIP_CALLERS_UNIMP_P) + return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; + else + return "retl\n\tsub\t%%sp, -%0, %%sp"; + } + else if (actual_fsize <= 8192) + { + operands[0] = GEN_INT (actual_fsize - 4096); + if (SKIP_CALLERS_UNIMP_P) + return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; + else + return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp"; + } + else if (SKIP_CALLERS_UNIMP_P) + { + if ((actual_fsize & 0x3ff) != 0) + return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; + else + return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; + } + else + { + if ((actual_fsize & 0x3ff) != 0) + return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; + else + return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; + } + } + else if (TARGET_V9) + { + if (delay) + { + epilogue_renumber (&SET_DEST (PATTERN (delay))); + epilogue_renumber (&SET_SRC (PATTERN (delay))); + } + if (SKIP_CALLERS_UNIMP_P) + return "return\t%%i7+12%#"; + else + return "return\t%%i7+8%#"; + } + else + { + if (delay) + abort (); + if (SKIP_CALLERS_UNIMP_P) + return "jmp\t%%i7+12\n\trestore"; + else + return "ret\n\trestore"; + } +} + +/* Leaf functions and non-leaf functions have different needs. */ + +static int +reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; + +static int +reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; + +static int *reg_alloc_orders[] = { + reg_leaf_alloc_order, + reg_nonleaf_alloc_order}; + +void +order_regs_for_local_alloc () +{ + static int last_order_nonleaf = 1; + + if (regs_ever_live[15] != last_order_nonleaf) + { + last_order_nonleaf = !last_order_nonleaf; + bcopy ((char *) reg_alloc_orders[last_order_nonleaf], + (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int)); + } +} + +/* Return 1 if REG and MEM are legitimate enough to allow the various + mem<-->reg splits to be run. */ + +int +sparc_splitdi_legitimate (reg, mem) + rtx reg; + rtx mem; +{ + /* Punt if we are here by mistake. */ + if (! reload_completed) + abort (); + + /* We must have an offsettable memory reference. */ + if (! offsettable_memref_p (mem)) + return 0; + + /* If we have legitimate args for ldd/std, we do not want + the split to happen. */ + if ((REGNO (reg) % 2) == 0 + && mem_min_alignment (mem, 8)) + return 0; + + /* Success. */ + return 1; +} + +/* Return 1 if x and y are some kind of REG and they refer to + different hard registers. This test is guarenteed to be + run after reload. */ + +int +sparc_absnegfloat_split_legitimate (x, y) + rtx x, y; +{ + if (GET_CODE (x) == SUBREG) + x = alter_subreg (x); + if (GET_CODE (x) != REG) + return 0; + if (GET_CODE (y) == SUBREG) + y = alter_subreg (y); + if (GET_CODE (y) != REG) + return 0; + if (REGNO (x) == REGNO (y)) + return 0; + return 1; +} + +/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. + This makes them candidates for using ldd and std insns. + + Note reg1 and reg2 *must* be hard registers. */ + +int +registers_ok_for_ldd_peep (reg1, reg2) + rtx reg1, reg2; +{ + /* We might have been passed a SUBREG. */ + if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) + return 0; + + if (REGNO (reg1) % 2 != 0) + return 0; + + /* Integer ldd is deprecated in SPARC V9 */ + if (TARGET_V9 && REGNO (reg1) < 32) + return 0; + + return (REGNO (reg1) == REGNO (reg2) - 1); +} + +/* Return 1 if addr1 and addr2 are suitable for use in an ldd or + std insn. + + This can only happen when addr1 and addr2 are consecutive memory + locations (addr1 + 4 == addr2). addr1 must also be aligned on a + 64 bit boundary (addr1 % 8 == 0). + + We know %sp and %fp are kept aligned on a 64 bit boundary. Other + registers are assumed to *never* be properly aligned and are + rejected. + + Knowing %sp and %fp are kept aligned on a 64 bit boundary, we + need only check that the offset for addr1 % 8 == 0. */ + +int +addrs_ok_for_ldd_peep (addr1, addr2) + rtx addr1, addr2; +{ + int reg1, offset1; + + /* Extract a register number and offset (if used) from the first addr. */ + if (GET_CODE (addr1) == PLUS) + { + /* If not a REG, return zero. */ + if (GET_CODE (XEXP (addr1, 0)) != REG) + return 0; + else + { + reg1 = REGNO (XEXP (addr1, 0)); + /* The offset must be constant! */ + if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) + return 0; + offset1 = INTVAL (XEXP (addr1, 1)); + } + } + else if (GET_CODE (addr1) != REG) + return 0; + else + { + reg1 = REGNO (addr1); + /* This was a simple (mem (reg)) expression. Offset is 0. */ + offset1 = 0; + } + + /* Make sure the second address is a (mem (plus (reg) (const_int). */ + if (GET_CODE (addr2) != PLUS) + return 0; + + if (GET_CODE (XEXP (addr2, 0)) != REG + || GET_CODE (XEXP (addr2, 1)) != CONST_INT) + return 0; + + /* Only %fp and %sp are allowed. Additionally both addresses must + use the same register. */ + if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) + return 0; + + if (reg1 != REGNO (XEXP (addr2, 0))) + return 0; + + /* The first offset must be evenly divisible by 8 to ensure the + address is 64 bit aligned. */ + if (offset1 % 8 != 0) + return 0; + + /* The offset for the second addr must be 4 more than the first addr. */ + if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) + return 0; + + /* All the tests passed. addr1 and addr2 are valid for ldd and std + instructions. */ + return 1; +} + +/* Return 1 if reg is a pseudo, or is the first register in + a hard register pair. This makes it a candidate for use in + ldd and std insns. */ + +int +register_ok_for_ldd (reg) + rtx reg; +{ + /* We might have been passed a SUBREG. */ + if (GET_CODE (reg) != REG) + return 0; + + if (REGNO (reg) < FIRST_PSEUDO_REGISTER) + return (REGNO (reg) % 2 == 0); + else + return 1; +} + +/* Print operand X (an rtx) in assembler syntax to file FILE. + CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. + For `%' followed by punctuation, CODE is the punctuation and X is null. */ + +void +print_operand (file, x, code) + FILE *file; + rtx x; + int code; +{ + switch (code) + { + case '#': + /* Output a 'nop' if there's nothing for the delay slot. */ + if (dbr_sequence_length () == 0) + fputs ("\n\t nop", file); + return; + case '*': + /* Output an annul flag if there's nothing for the delay slot and we + are optimizing. This is always used with '(' below. */ + /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; + this is a dbx bug. So, we only do this when optimizing. */ + /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. + Always emit a nop in case the next instruction is a branch. */ + if (dbr_sequence_length () == 0 + && (optimize && (int)sparc_cpu < PROCESSOR_V9)) + fputs (",a", file); + return; + case '(': + /* Output a 'nop' if there's nothing for the delay slot and we are + not optimizing. This is always used with '*' above. */ + if (dbr_sequence_length () == 0 + && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) + fputs ("\n\t nop", file); + return; + case '_': + /* Output the Embedded Medium/Anywhere code model base register. */ + fputs (EMBMEDANY_BASE_REG, file); + return; + case '@': + /* Print out what we are using as the frame pointer. This might + be %fp, or might be %sp+offset. */ + /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ + fprintf (file, "%s+%d", frame_base_name, frame_base_offset); + return; + case 'Y': + /* Adjust the operand to take into account a RESTORE operation. */ + if (GET_CODE (x) == CONST_INT) + break; + else if (GET_CODE (x) != REG) + output_operand_lossage ("Invalid %%Y operand"); + else if (REGNO (x) < 8) + fputs (reg_names[REGNO (x)], file); + else if (REGNO (x) >= 24 && REGNO (x) < 32) + fputs (reg_names[REGNO (x)-16], file); + else + output_operand_lossage ("Invalid %%Y operand"); + return; + case 'L': + /* Print out the low order register name of a register pair. */ + if (WORDS_BIG_ENDIAN) + fputs (reg_names[REGNO (x)+1], file); + else + fputs (reg_names[REGNO (x)], file); + return; + case 'H': + /* Print out the high order register name of a register pair. */ + if (WORDS_BIG_ENDIAN) + fputs (reg_names[REGNO (x)], file); + else + fputs (reg_names[REGNO (x)+1], file); + return; + case 'R': + /* Print out the second register name of a register pair or quad. + I.e., R (%o0) => %o1. */ + fputs (reg_names[REGNO (x)+1], file); + return; + case 'S': + /* Print out the third register name of a register quad. + I.e., S (%o0) => %o2. */ + fputs (reg_names[REGNO (x)+2], file); + return; + case 'T': + /* Print out the fourth register name of a register quad. + I.e., T (%o0) => %o3. */ + fputs (reg_names[REGNO (x)+3], file); + return; + case 'x': + /* Print a condition code register. */ + if (REGNO (x) == SPARC_ICC_REG) + { + /* We don't handle CC[X]_NOOVmode because they're not supposed + to occur here. */ + if (GET_MODE (x) == CCmode) + fputs ("%icc", file); + else if (GET_MODE (x) == CCXmode) + fputs ("%xcc", file); + else + abort (); + } + else + /* %fccN register */ + fputs (reg_names[REGNO (x)], file); + return; + case 'm': + /* Print the operand's address only. */ + output_address (XEXP (x, 0)); + return; + case 'r': + /* In this case we need a register. Use %g0 if the + operand is const0_rtx. */ + if (x == const0_rtx + || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) + { + fputs ("%g0", file); + return; + } + else + break; + + case 'A': + switch (GET_CODE (x)) + { + case IOR: fputs ("or", file); break; + case AND: fputs ("and", file); break; + case XOR: fputs ("xor", file); break; + default: output_operand_lossage ("Invalid %%A operand"); + } + return; + + case 'B': + switch (GET_CODE (x)) + { + case IOR: fputs ("orn", file); break; + case AND: fputs ("andn", file); break; + case XOR: fputs ("xnor", file); break; + default: output_operand_lossage ("Invalid %%B operand"); + } + return; + + /* These are used by the conditional move instructions. */ + case 'c' : + case 'C': + { + enum rtx_code rc = (code == 'c' + ? reverse_condition (GET_CODE (x)) + : GET_CODE (x)); + switch (rc) + { + case NE: fputs ("ne", file); break; + case EQ: fputs ("e", file); break; + case GE: fputs ("ge", file); break; + case GT: fputs ("g", file); break; + case LE: fputs ("le", file); break; + case LT: fputs ("l", file); break; + case GEU: fputs ("geu", file); break; + case GTU: fputs ("gu", file); break; + case LEU: fputs ("leu", file); break; + case LTU: fputs ("lu", file); break; + default: output_operand_lossage (code == 'c' + ? "Invalid %%c operand" + : "Invalid %%C operand"); + } + return; + } + + /* These are used by the movr instruction pattern. */ + case 'd': + case 'D': + { + enum rtx_code rc = (code == 'd' + ? reverse_condition (GET_CODE (x)) + : GET_CODE (x)); + switch (rc) + { + case NE: fputs ("ne", file); break; + case EQ: fputs ("e", file); break; + case GE: fputs ("gez", file); break; + case LT: fputs ("lz", file); break; + case LE: fputs ("lez", file); break; + case GT: fputs ("gz", file); break; + default: output_operand_lossage (code == 'd' + ? "Invalid %%d operand" + : "Invalid %%D operand"); + } + return; + } + + case 'b': + { + /* Print a sign-extended character. */ + int i = INTVAL (x) & 0xff; + if (i & 0x80) + i |= 0xffffff00; + fprintf (file, "%d", i); + return; + } + + case 'f': + /* Operand must be a MEM; write its address. */ + if (GET_CODE (x) != MEM) + output_operand_lossage ("Invalid %%f operand"); + output_address (XEXP (x, 0)); + return; + + case 0: + /* Do nothing special. */ + break; + + default: + /* Undocumented flag. */ + output_operand_lossage ("invalid operand output code"); + } + + if (GET_CODE (x) == REG) + fputs (reg_names[REGNO (x)], file); + else if (GET_CODE (x) == MEM) + { + fputc ('[', file); + /* Poor Sun assembler doesn't understand absolute addressing. */ + if (CONSTANT_P (XEXP (x, 0)) + && ! TARGET_LIVE_G0) + fputs ("%g0+", file); + output_address (XEXP (x, 0)); + fputc (']', file); + } + else if (GET_CODE (x) == HIGH) + { + fputs ("%hi(", file); + output_addr_const (file, XEXP (x, 0)); + fputc (')', file); + } + else if (GET_CODE (x) == LO_SUM) + { + print_operand (file, XEXP (x, 0), 0); + if (TARGET_CM_MEDMID) + fputs ("+%l44(", file); + else + fputs ("+%lo(", file); + output_addr_const (file, XEXP (x, 1)); + fputc (')', file); + } + else if (GET_CODE (x) == CONST_DOUBLE + && (GET_MODE (x) == VOIDmode + || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) + { + if (CONST_DOUBLE_HIGH (x) == 0) + fprintf (file, "%u", CONST_DOUBLE_LOW (x)); + else if (CONST_DOUBLE_HIGH (x) == -1 + && CONST_DOUBLE_LOW (x) < 0) + fprintf (file, "%d", CONST_DOUBLE_LOW (x)); + else + output_operand_lossage ("long long constant not a valid immediate operand"); + } + else if (GET_CODE (x) == CONST_DOUBLE) + output_operand_lossage ("floating point constant not a valid immediate operand"); + else { output_addr_const (file, x); } +} + +/* This function outputs assembler code for VALUE to FILE, where VALUE is + a 64 bit (DImode) value. */ + +/* ??? If there is a 64 bit counterpart to .word that the assembler + understands, then using that would simply this code greatly. */ +/* ??? We only output .xword's for symbols and only then in environments + where the assembler can handle them. */ + +void +output_double_int (file, value) + FILE *file; + rtx value; +{ + if (GET_CODE (value) == CONST_INT) + { + /* ??? This has endianness issues. */ +#if HOST_BITS_PER_WIDE_INT == 64 + HOST_WIDE_INT xword = INTVAL (value); + HOST_WIDE_INT high, low; + + high = (xword >> 32) & 0xffffffff; + low = xword & 0xffffffff; + ASM_OUTPUT_INT (file, GEN_INT (high)); + ASM_OUTPUT_INT (file, GEN_INT (low)); +#else + if (INTVAL (value) < 0) + ASM_OUTPUT_INT (file, constm1_rtx); + else + ASM_OUTPUT_INT (file, const0_rtx); + ASM_OUTPUT_INT (file, value); +#endif + } + else if (GET_CODE (value) == CONST_DOUBLE) + { + ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value))); + ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value))); + } + else if (GET_CODE (value) == SYMBOL_REF + || GET_CODE (value) == CONST + || GET_CODE (value) == PLUS + || (TARGET_ARCH64 && + (GET_CODE (value) == LABEL_REF + || GET_CODE (value) == CODE_LABEL + || GET_CODE (value) == MINUS))) + { + if (! TARGET_V9) + { + ASM_OUTPUT_INT (file, const0_rtx); + ASM_OUTPUT_INT (file, value); + } + else + { + fprintf (file, "\t%s\t", ASM_LONGLONG); + output_addr_const (file, value); + fprintf (file, "\n"); + } + } + else + abort (); +} + +/* Return the value of a code used in the .proc pseudo-op that says + what kind of result this function returns. For non-C types, we pick + the closest C type. */ + +#ifndef CHAR_TYPE_SIZE +#define CHAR_TYPE_SIZE BITS_PER_UNIT +#endif + +#ifndef SHORT_TYPE_SIZE +#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) +#endif + +#ifndef INT_TYPE_SIZE +#define INT_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef LONG_TYPE_SIZE +#define LONG_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef LONG_LONG_TYPE_SIZE +#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +#ifndef FLOAT_TYPE_SIZE +#define FLOAT_TYPE_SIZE BITS_PER_WORD +#endif + +#ifndef DOUBLE_TYPE_SIZE +#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +#ifndef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) +#endif + +unsigned long +sparc_type_code (type) + register tree type; +{ + register unsigned long qualifiers = 0; + register unsigned shift; + + /* Only the first 30 bits of the qualifier are valid. We must refrain from + setting more, since some assemblers will give an error for this. Also, + we must be careful to avoid shifts of 32 bits or more to avoid getting + unpredictable results. */ + + for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) + { + switch (TREE_CODE (type)) + { + case ERROR_MARK: + return qualifiers; + + case ARRAY_TYPE: + qualifiers |= (3 << shift); + break; + + case FUNCTION_TYPE: + case METHOD_TYPE: + qualifiers |= (2 << shift); + break; + + case POINTER_TYPE: + case REFERENCE_TYPE: + case OFFSET_TYPE: + qualifiers |= (1 << shift); + break; + + case RECORD_TYPE: + return (qualifiers | 8); + + case UNION_TYPE: + case QUAL_UNION_TYPE: + return (qualifiers | 9); + + case ENUMERAL_TYPE: + return (qualifiers | 10); + + case VOID_TYPE: + return (qualifiers | 16); + + case INTEGER_TYPE: + /* If this is a range type, consider it to be the underlying + type. */ + if (TREE_TYPE (type) != 0) + break; + + /* Carefully distinguish all the standard types of C, + without messing up if the language is not C. We do this by + testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to + look at both the names and the above fields, but that's redundant. + Any type whose size is between two C types will be considered + to be the wider of the two types. Also, we do not have a + special code to use for "long long", so anything wider than + long is treated the same. Note that we can't distinguish + between "int" and "long" in this code if they are the same + size, but that's fine, since neither can the assembler. */ + + if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) + return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); + + else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) + return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); + + else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) + return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); + + else + return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); + + case REAL_TYPE: + /* If this is a range type, consider it to be the underlying + type. */ + if (TREE_TYPE (type) != 0) + break; + + /* Carefully distinguish all the standard types of C, + without messing up if the language is not C. */ + + if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) + return (qualifiers | 6); + + else + return (qualifiers | 7); + + case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ + /* ??? We need to distinguish between double and float complex types, + but I don't know how yet because I can't reach this code from + existing front-ends. */ + return (qualifiers | 7); /* Who knows? */ + + case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ + case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ + case FILE_TYPE: /* GNU Pascal FILE type. */ + case SET_TYPE: /* GNU Pascal SET type. */ + case LANG_TYPE: /* ? */ + return qualifiers; + + default: + abort (); /* Not a type! */ + } + } + + return qualifiers; +} + +/* Nested function support. */ + +/* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. + + This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi + (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes + (to store insns). This is a bit excessive. Perhaps a different + mechanism would be better here. + + Emit enough FLUSH insns to synchronize the data and instruction caches. */ + +void +sparc_initialize_trampoline (tramp, fnaddr, cxt) + rtx tramp, fnaddr, cxt; +{ + /* SPARC 32 bit trampoline: + + sethi %hi(fn), %g1 + sethi %hi(static), %g2 + jmp %g1+%lo(fn) + or %g2, %lo(static), %g2 + + SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii + JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii + */ +#ifdef TRANSFER_FROM_TRAMPOLINE + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), + 0, VOIDmode, 1, tramp, Pmode); +#endif + + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), + expand_binop (SImode, ior_optab, + expand_shift (RSHIFT_EXPR, SImode, fnaddr, + size_int (10), 0, 1), + GEN_INT (0x03000000), + NULL_RTX, 1, OPTAB_DIRECT)); + + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), + expand_binop (SImode, ior_optab, + expand_shift (RSHIFT_EXPR, SImode, cxt, + size_int (10), 0, 1), + GEN_INT (0x05000000), + NULL_RTX, 1, OPTAB_DIRECT)); + + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), + expand_binop (SImode, ior_optab, + expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX), + GEN_INT (0x81c06000), + NULL_RTX, 1, OPTAB_DIRECT)); + + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), + expand_binop (SImode, ior_optab, + expand_and (cxt, GEN_INT (0x3ff), NULL_RTX), + GEN_INT (0x8410a000), + NULL_RTX, 1, OPTAB_DIRECT)); + + emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); + /* On UltraSPARC a flush flushes an entire cache line. The trampoline is + aligned on a 16 byte boundary so one flush clears it all. */ + if (sparc_cpu != PROCESSOR_ULTRASPARC) + emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, + plus_constant (tramp, 8))))); +} + +/* The 64 bit version is simpler because it makes more sense to load the + values as "immediate" data out of the trampoline. It's also easier since + we can read the PC without clobbering a register. */ + +void +sparc64_initialize_trampoline (tramp, fnaddr, cxt) + rtx tramp, fnaddr, cxt; +{ +#ifdef TRANSFER_FROM_TRAMPOLINE + emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), + 0, VOIDmode, 1, tramp, Pmode); +#endif + + /* + rd %pc, %g1 + ldx [%g1+24], %g5 + jmp %g5 + ldx [%g1+16], %g5 + +16 bytes data + */ + + emit_move_insn (gen_rtx_MEM (SImode, tramp), + GEN_INT (0x83414000)); + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), + GEN_INT (0xca586018)); + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), + GEN_INT (0x81c14000)); + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), + GEN_INT (0xca586010)); + emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); + emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); + emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp)))); + + if (sparc_cpu != PROCESSOR_ULTRASPARC) + emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); +} + +/* Subroutines to support a flat (single) register window calling + convention. */ + +/* Single-register window sparc stack frames look like: + + Before call After call + +-----------------------+ +-----------------------+ + high | | | | + mem | caller's temps. | | caller's temps. | + | | | | + +-----------------------+ +-----------------------+ + | | | | + | arguments on stack. | | arguments on stack. | + | | | | + +-----------------------+FP+92->+-----------------------+ + | 6 words to save | | 6 words to save | + | arguments passed | | arguments passed | + | in registers, even | | in registers, even | + | if not passed. | | if not passed. | + SP+68->+-----------------------+FP+68->+-----------------------+ + | 1 word struct addr | | 1 word struct addr | + +-----------------------+FP+64->+-----------------------+ + | | | | + | 16 word reg save area | | 16 word reg save area | + | | | | + SP->+-----------------------+ FP->+-----------------------+ + | 4 word area for | + | fp/alu reg moves | + FP-16->+-----------------------+ + | | + | local variables | + | | + +-----------------------+ + | | + | fp register save | + | | + +-----------------------+ + | | + | gp register save | + | | + +-----------------------+ + | | + | alloca allocations | + | | + +-----------------------+ + | | + | arguments on stack | + | | + SP+92->+-----------------------+ + | 6 words to save | + | arguments passed | + | in registers, even | + low | if not passed. | + memory SP+68->+-----------------------+ + | 1 word struct addr | + SP+64->+-----------------------+ + | | + I 16 word reg save area | + | | + SP->+-----------------------+ */ + +/* Structure to be filled in by sparc_flat_compute_frame_size with register + save masks, and offsets for the current function. */ + +struct sparc_frame_info +{ + unsigned long total_size; /* # bytes that the entire frame takes up. */ + unsigned long var_size; /* # bytes that variables take up. */ + unsigned long args_size; /* # bytes that outgoing arguments take up. */ + unsigned long extra_size; /* # bytes of extra gunk. */ + unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ + unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ + unsigned long gmask; /* Mask of saved gp registers. */ + unsigned long fmask; /* Mask of saved fp registers. */ + unsigned long reg_offset; /* Offset from new sp to store regs. */ + int initialized; /* Nonzero if frame size already calculated. */ +}; + +/* Current frame information calculated by sparc_flat_compute_frame_size. */ +struct sparc_frame_info current_frame_info; + +/* Zero structure to initialize current_frame_info. */ +struct sparc_frame_info zero_frame_info; + +/* Tell prologue and epilogue if register REGNO should be saved / restored. */ + +#define RETURN_ADDR_REGNUM 15 +#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) +#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) + +#define MUST_SAVE_REGISTER(regno) \ + ((regs_ever_live[regno] && !call_used_regs[regno]) \ + || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ + || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) + +/* Return the bytes needed to compute the frame pointer from the current + stack pointer. */ + +unsigned long +sparc_flat_compute_frame_size (size) + int size; /* # of var. bytes allocated. */ +{ + int regno; + unsigned long total_size; /* # bytes that the entire frame takes up. */ + unsigned long var_size; /* # bytes that variables take up. */ + unsigned long args_size; /* # bytes that outgoing arguments take up. */ + unsigned long extra_size; /* # extra bytes. */ + unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ + unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ + unsigned long gmask; /* Mask of saved gp registers. */ + unsigned long fmask; /* Mask of saved fp registers. */ + unsigned long reg_offset; /* Offset to register save area. */ + int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ + + /* This is the size of the 16 word reg save area, 1 word struct addr + area, and 4 word fp/alu register copy area. */ + extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); + var_size = size; + gp_reg_size = 0; + fp_reg_size = 0; + gmask = 0; + fmask = 0; + reg_offset = 0; + need_aligned_p = 0; + + args_size = 0; + if (!leaf_function_p ()) + { + /* Also include the size needed for the 6 parameter registers. */ + args_size = current_function_outgoing_args_size + 24; + } + total_size = var_size + args_size; + + /* Calculate space needed for gp registers. */ + for (regno = 1; regno <= 31; regno++) + { + if (MUST_SAVE_REGISTER (regno)) + { + /* If we need to save two regs in a row, ensure there's room to bump + up the address to align it to a doubleword boundary. */ + if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) + { + if (gp_reg_size % 8 != 0) + gp_reg_size += 4; + gp_reg_size += 2 * UNITS_PER_WORD; + gmask |= 3 << regno; + regno++; + need_aligned_p = 1; + } + else + { + gp_reg_size += UNITS_PER_WORD; + gmask |= 1 << regno; + } + } + } + + /* Calculate space needed for fp registers. */ + for (regno = 32; regno <= 63; regno++) + { + if (regs_ever_live[regno] && !call_used_regs[regno]) + { + fp_reg_size += UNITS_PER_WORD; + fmask |= 1 << (regno - 32); + } + } + + if (gmask || fmask) + { + int n; + reg_offset = FIRST_PARM_OFFSET(0) + args_size; + /* Ensure save area is 8 byte aligned if we need it. */ + n = reg_offset % 8; + if (need_aligned_p && n != 0) + { + total_size += 8 - n; + reg_offset += 8 - n; + } + total_size += gp_reg_size + fp_reg_size; + } + + /* If we must allocate a stack frame at all, we must also allocate + room for register window spillage, so as to be binary compatible + with libraries and operating systems that do not use -mflat. */ + if (total_size > 0) + total_size += extra_size; + else + extra_size = 0; + + total_size = SPARC_STACK_ALIGN (total_size); + + /* Save other computed information. */ + current_frame_info.total_size = total_size; + current_frame_info.var_size = var_size; + current_frame_info.args_size = args_size; + current_frame_info.extra_size = extra_size; + current_frame_info.gp_reg_size = gp_reg_size; + current_frame_info.fp_reg_size = fp_reg_size; + current_frame_info.gmask = gmask; + current_frame_info.fmask = fmask; + current_frame_info.reg_offset = reg_offset; + current_frame_info.initialized = reload_completed; + + /* Ok, we're done. */ + return total_size; +} + +/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset + OFFSET. + + BASE_REG must be 8 byte aligned. This allows us to test OFFSET for + appropriate alignment and use DOUBLEWORD_OP when we can. We assume + [BASE_REG+OFFSET] will always be a valid address. + + WORD_OP is either "st" for save, "ld" for restore. + DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ + +void +sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, + doubleword_op, base_offset) + FILE *file; + char *base_reg; + unsigned int offset; + unsigned long gmask; + unsigned long fmask; + char *word_op; + char *doubleword_op; + unsigned long base_offset; +{ + int regno; + + if (gmask == 0 && fmask == 0) + return; + + /* Save registers starting from high to low. We've already saved the + previous frame pointer and previous return address for the debugger's + sake. The debugger allows us to not need a nop in the epilog if at least + one register is reloaded in addition to return address. */ + + if (gmask) + { + for (regno = 1; regno <= 31; regno++) + { + if ((gmask & (1L << regno)) != 0) + { + if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) + { + /* We can save two registers in a row. If we're not at a + double word boundary, move to one. + sparc_flat_compute_frame_size ensures there's room to do + this. */ + if (offset % 8 != 0) + offset += UNITS_PER_WORD; + + if (word_op[0] == 's') + { + fprintf (file, "\t%s\t%s, [%s+%d]\n", + doubleword_op, reg_names[regno], + base_reg, offset); + if (dwarf2out_do_frame ()) + { + char *l = dwarf2out_cfi_label (); + dwarf2out_reg_save (l, regno, offset + base_offset); + dwarf2out_reg_save + (l, regno+1, offset+base_offset + UNITS_PER_WORD); + } + } + else + fprintf (file, "\t%s\t[%s+%d], %s\n", + doubleword_op, base_reg, offset, + reg_names[regno]); + + offset += 2 * UNITS_PER_WORD; + regno++; + } + else + { + if (word_op[0] == 's') + { + fprintf (file, "\t%s\t%s, [%s+%d]\n", + word_op, reg_names[regno], + base_reg, offset); + if (dwarf2out_do_frame ()) + dwarf2out_reg_save ("", regno, offset + base_offset); + } + else + fprintf (file, "\t%s\t[%s+%d], %s\n", + word_op, base_reg, offset, reg_names[regno]); + + offset += UNITS_PER_WORD; + } + } + } + } + + if (fmask) + { + for (regno = 32; regno <= 63; regno++) + { + if ((fmask & (1L << (regno - 32))) != 0) + { + if (word_op[0] == 's') + { + fprintf (file, "\t%s\t%s, [%s+%d]\n", + word_op, reg_names[regno], + base_reg, offset); + if (dwarf2out_do_frame ()) + dwarf2out_reg_save ("", regno, offset + base_offset); + } + else + fprintf (file, "\t%s\t[%s+%d], %s\n", + word_op, base_reg, offset, reg_names[regno]); + + offset += UNITS_PER_WORD; + } + } + } +} + +/* Set up the stack and frame (if desired) for the function. */ + +void +sparc_flat_output_function_prologue (file, size) + FILE *file; + int size; +{ + char *sp_str = reg_names[STACK_POINTER_REGNUM]; + unsigned long gmask = current_frame_info.gmask; + + /* This is only for the human reader. */ + fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); + fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", + ASM_COMMENT_START, + current_frame_info.var_size, + current_frame_info.gp_reg_size / 4, + current_frame_info.fp_reg_size / 4, + current_function_outgoing_args_size, + current_frame_info.extra_size); + + size = SPARC_STACK_ALIGN (size); + size = (! current_frame_info.initialized + ? sparc_flat_compute_frame_size (size) + : current_frame_info.total_size); + + /* These cases shouldn't happen. Catch them now. */ + if (size == 0 && (gmask || current_frame_info.fmask)) + abort (); + + /* Allocate our stack frame by decrementing %sp. + At present, the only algorithm gdb can use to determine if this is a + flat frame is if we always set %i7 if we set %sp. This can be optimized + in the future by putting in some sort of debugging information that says + this is a `flat' function. However, there is still the case of debugging + code without such debugging information (including cases where most fns + have such info, but there is one that doesn't). So, always do this now + so we don't get a lot of code out there that gdb can't handle. + If the frame pointer isn't needn't then that's ok - gdb won't be able to + distinguish us from a non-flat function but there won't (and shouldn't) + be any differences anyway. The return pc is saved (if necessary) right + after %i7 so gdb won't have to look too far to find it. */ + if (size > 0) + { + unsigned int reg_offset = current_frame_info.reg_offset; + char *fp_str = reg_names[FRAME_POINTER_REGNUM]; + const char *t1_str = "%g1"; + + /* Things get a little tricky if local variables take up more than ~4096 + bytes and outgoing arguments take up more than ~4096 bytes. When that + happens, the register save area can't be accessed from either end of + the frame. Handle this by decrementing %sp to the start of the gp + register save area, save the regs, update %i7, and then set %sp to its + final value. Given that we only have one scratch register to play + with it is the cheapest solution, and it helps gdb out as it won't + slow down recognition of flat functions. + Don't change the order of insns emitted here without checking with + the gdb folk first. */ + + /* Is the entire register save area offsettable from %sp? */ + if (reg_offset < 4096 - 64 * UNITS_PER_WORD) + { + if (size <= 4096) + { + fprintf (file, "\tadd\t%s, %d, %s\n", + sp_str, -size, sp_str); + if (gmask & FRAME_POINTER_MASK) + { + fprintf (file, "\tst\t%s, [%s+%d]\n", + fp_str, sp_str, reg_offset); + fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", + sp_str, -size, fp_str, ASM_COMMENT_START); + reg_offset += 4; + } + } + else + { + fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", + size, t1_str, sp_str, t1_str, sp_str); + if (gmask & FRAME_POINTER_MASK) + { + fprintf (file, "\tst\t%s, [%s+%d]\n", + fp_str, sp_str, reg_offset); + fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", + sp_str, t1_str, fp_str, ASM_COMMENT_START); + reg_offset += 4; + } + } + if (dwarf2out_do_frame ()) + { + char *l = dwarf2out_cfi_label (); + if (gmask & FRAME_POINTER_MASK) + { + dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, + reg_offset - 4 - size); + dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); + } + else + dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); + } + if (gmask & RETURN_ADDR_MASK) + { + fprintf (file, "\tst\t%s, [%s+%d]\n", + reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); + if (dwarf2out_do_frame ()) + dwarf2out_return_save ("", reg_offset - size); + reg_offset += 4; + } + sparc_flat_save_restore (file, sp_str, reg_offset, + gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), + current_frame_info.fmask, + "st", "std", -size); + } + else + { + /* Subtract %sp in two steps, but make sure there is always a + 64 byte register save area, and %sp is properly aligned. */ + /* Amount to decrement %sp by, the first time. */ + unsigned int size1 = ((size - reg_offset + 64) + 15) & -16; + /* Offset to register save area from %sp. */ + unsigned int offset = size1 - (size - reg_offset); + + if (size1 <= 4096) + { + fprintf (file, "\tadd\t%s, %d, %s\n", + sp_str, -size1, sp_str); + if (gmask & FRAME_POINTER_MASK) + { + fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", + fp_str, sp_str, offset, sp_str, -size1, fp_str, + ASM_COMMENT_START); + offset += 4; + } + } + else + { + fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", + size1, t1_str, sp_str, t1_str, sp_str); + if (gmask & FRAME_POINTER_MASK) + { + fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", + fp_str, sp_str, offset, sp_str, t1_str, fp_str, + ASM_COMMENT_START); + offset += 4; + } + } + if (dwarf2out_do_frame ()) + { + char *l = dwarf2out_cfi_label (); + if (gmask & FRAME_POINTER_MASK) + { + dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, + offset - 4 - size1); + dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); + } + else + dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); + } + if (gmask & RETURN_ADDR_MASK) + { + fprintf (file, "\tst\t%s, [%s+%d]\n", + reg_names[RETURN_ADDR_REGNUM], sp_str, offset); + if (dwarf2out_do_frame ()) + /* offset - size1 == reg_offset - size + if reg_offset were updated above like offset. */ + dwarf2out_return_save ("", offset - size1); + offset += 4; + } + sparc_flat_save_restore (file, sp_str, offset, + gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), + current_frame_info.fmask, + "st", "std", -size1); + fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", + size - size1, t1_str, sp_str, t1_str, sp_str); + if (dwarf2out_do_frame ()) + if (! (gmask & FRAME_POINTER_MASK)) + dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); + } + } + + fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); +} + +/* Do any necessary cleanup after a function to restore stack, frame, + and regs. */ + +void +sparc_flat_output_function_epilogue (file, size) + FILE *file; + int size; +{ + rtx epilogue_delay = current_function_epilogue_delay_list; + int noepilogue = FALSE; + + /* This is only for the human reader. */ + fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); + + /* The epilogue does not depend on any registers, but the stack + registers, so we assume that if we have 1 pending nop, it can be + ignored, and 2 it must be filled (2 nops occur for integer + multiply and divide). */ + + size = SPARC_STACK_ALIGN (size); + size = (!current_frame_info.initialized + ? sparc_flat_compute_frame_size (size) + : current_frame_info.total_size); + + if (size == 0 && epilogue_delay == 0) + { + rtx insn = get_last_insn (); + + /* If the last insn was a BARRIER, we don't have to write any code + because a jump (aka return) was put there. */ + if (GET_CODE (insn) == NOTE) + insn = prev_nonnote_insn (insn); + if (insn && GET_CODE (insn) == BARRIER) + noepilogue = TRUE; + } + + if (!noepilogue) + { + unsigned int reg_offset = current_frame_info.reg_offset; + unsigned int size1; + char *sp_str = reg_names[STACK_POINTER_REGNUM]; + char *fp_str = reg_names[FRAME_POINTER_REGNUM]; + const char *t1_str = "%g1"; + + /* In the reload sequence, we don't need to fill the load delay + slots for most of the loads, also see if we can fill the final + delay slot if not otherwise filled by the reload sequence. */ + + if (size > 4095) + fprintf (file, "\tset\t%d, %s\n", size, t1_str); + + if (frame_pointer_needed) + { + if (size > 4095) + fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", + fp_str, t1_str, sp_str, ASM_COMMENT_START); + else + fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", + fp_str, size, sp_str, ASM_COMMENT_START); + } + + /* Is the entire register save area offsettable from %sp? */ + if (reg_offset < 4096 - 64 * UNITS_PER_WORD) + { + size1 = 0; + } + else + { + /* Restore %sp in two steps, but make sure there is always a + 64 byte register save area, and %sp is properly aligned. */ + /* Amount to increment %sp by, the first time. */ + size1 = ((reg_offset - 64 - 16) + 15) & -16; + /* Offset to register save area from %sp. */ + reg_offset = size1 - reg_offset; + + fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n", + size1, t1_str, sp_str, t1_str, sp_str); + } + + /* We must restore the frame pointer and return address reg first + because they are treated specially by the prologue output code. */ + if (current_frame_info.gmask & FRAME_POINTER_MASK) + { + fprintf (file, "\tld\t[%s+%d], %s\n", + sp_str, reg_offset, fp_str); + reg_offset += 4; + } + if (current_frame_info.gmask & RETURN_ADDR_MASK) + { + fprintf (file, "\tld\t[%s+%d], %s\n", + sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); + reg_offset += 4; + } + + /* Restore any remaining saved registers. */ + sparc_flat_save_restore (file, sp_str, reg_offset, + current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), + current_frame_info.fmask, + "ld", "ldd", 0); + + /* If we had to increment %sp in two steps, record it so the second + restoration in the epilogue finishes up. */ + if (size1 > 0) + { + size -= size1; + if (size > 4095) + fprintf (file, "\tset\t%d, %s\n", + size, t1_str); + } + + if (current_function_returns_struct) + fprintf (file, "\tjmp\t%%o7+12\n"); + else + fprintf (file, "\tretl\n"); + + /* If the only register saved is the return address, we need a + nop, unless we have an instruction to put into it. Otherwise + we don't since reloading multiple registers doesn't reference + the register being loaded. */ + + if (epilogue_delay) + { + if (size) + abort (); + final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); + } + + else if (size > 4095) + fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); + + else if (size > 0) + fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str); + + else + fprintf (file, "\tnop\n"); + } + + /* Reset state info for each function. */ + current_frame_info = zero_frame_info; + + sparc_output_deferred_case_vectors (); +} + +/* Define the number of delay slots needed for the function epilogue. + + On the sparc, we need a slot if either no stack has been allocated, + or the only register saved is the return register. */ + +int +sparc_flat_epilogue_delay_slots () +{ + if (!current_frame_info.initialized) + (void) sparc_flat_compute_frame_size (get_frame_size ()); + + if (current_frame_info.total_size == 0) + return 1; + + return 0; +} + +/* Return true is TRIAL is a valid insn for the epilogue delay slot. + Any single length instruction which doesn't reference the stack or frame + pointer is OK. */ + +int +sparc_flat_eligible_for_epilogue_delay (trial, slot) + rtx trial; + int slot ATTRIBUTE_UNUSED; +{ + rtx pat = PATTERN (trial); + + if (get_attr_length (trial) != 1) + return 0; + + /* If %g0 is live, there are lots of things we can't handle. + Rather than trying to find them all now, let's punt and only + optimize things as necessary. */ + if (TARGET_LIVE_G0) + return 0; + + if (! reg_mentioned_p (stack_pointer_rtx, pat) + && ! reg_mentioned_p (frame_pointer_rtx, pat)) + return 1; + + return 0; +} + +/* Adjust the cost of a scheduling dependency. Return the new cost of + a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ + +static int +supersparc_adjust_cost (insn, link, dep_insn, cost) + rtx insn; + rtx link; + rtx dep_insn; + int cost; +{ + enum attr_type insn_type; + + if (! recog_memoized (insn)) + return 0; + + insn_type = get_attr_type (insn); + + if (REG_NOTE_KIND (link) == 0) + { + /* Data dependency; DEP_INSN writes a register that INSN reads some + cycles later. */ + + /* if a load, then the dependence must be on the memory address; + add an extra "cycle". Note that the cost could be two cycles + if the reg was written late in an instruction group; we ca not tell + here. */ + if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) + return cost + 3; + + /* Get the delay only if the address of the store is the dependence. */ + if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) + { + rtx pat = PATTERN(insn); + rtx dep_pat = PATTERN (dep_insn); + + if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) + return cost; /* This should not happen! */ + + /* The dependency between the two instructions was on the data that + is being stored. Assume that this implies that the address of the + store is not dependent. */ + if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) + return cost; + + return cost + 3; /* An approximation. */ + } + + /* A shift instruction cannot receive its data from an instruction + in the same cycle; add a one cycle penalty. */ + if (insn_type == TYPE_SHIFT) + return cost + 3; /* Split before cascade into shift. */ + } + else + { + /* Anti- or output- dependency; DEP_INSN reads/writes a register that + INSN writes some cycles later. */ + + /* These are only significant for the fpu unit; writing a fp reg before + the fpu has finished with it stalls the processor. */ + + /* Reusing an integer register causes no problems. */ + if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) + return 0; + } + + return cost; +} + +static int +hypersparc_adjust_cost (insn, link, dep_insn, cost) + rtx insn; + rtx link; + rtx dep_insn; + int cost; +{ + enum attr_type insn_type, dep_type; + rtx pat = PATTERN(insn); + rtx dep_pat = PATTERN (dep_insn); + + if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) + return cost; + + insn_type = get_attr_type (insn); + dep_type = get_attr_type (dep_insn); + + switch (REG_NOTE_KIND (link)) + { + case 0: + /* Data dependency; DEP_INSN writes a register that INSN reads some + cycles later. */ + + switch (insn_type) + { + case TYPE_STORE: + case TYPE_FPSTORE: + /* Get the delay iff the address of the store is the dependence. */ + if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) + return cost; + + if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) + return cost; + return cost + 3; + + case TYPE_LOAD: + case TYPE_SLOAD: + case TYPE_FPLOAD: + /* If a load, then the dependence must be on the memory address. If + the addresses aren't equal, then it might be a false dependency */ + if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) + { + if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET + || GET_CODE (SET_DEST (dep_pat)) != MEM + || GET_CODE (SET_SRC (pat)) != MEM + || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), + XEXP (SET_SRC (pat), 0))) + return cost + 2; + + return cost + 8; + } + break; + + case TYPE_BRANCH: + /* Compare to branch latency is 0. There is no benefit from + separating compare and branch. */ + if (dep_type == TYPE_COMPARE) + return 0; + /* Floating point compare to branch latency is less than + compare to conditional move. */ + if (dep_type == TYPE_FPCMP) + return cost - 1; + break; + default: + break; + } + break; + + case REG_DEP_ANTI: + /* Anti-dependencies only penalize the fpu unit. */ + if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) + return 0; + break; + + default: + break; + } + + return cost; +} + +static int +ultrasparc_adjust_cost (insn, link, dep_insn, cost) + rtx insn; + rtx link; + rtx dep_insn; + int cost; +{ + enum attr_type insn_type, dep_type; + rtx pat = PATTERN(insn); + rtx dep_pat = PATTERN (dep_insn); + + if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) + return cost; + + insn_type = get_attr_type (insn); + dep_type = get_attr_type (dep_insn); + + /* Nothing issues in parallel with integer multiplies, so + mark as zero cost since the scheduler can not do anything + about it. */ + if (insn_type == TYPE_IMUL) + return 0; + +#define SLOW_FP(dep_type) \ +(dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) + + switch (REG_NOTE_KIND (link)) + { + case 0: + /* Data dependency; DEP_INSN writes a register that INSN reads some + cycles later. */ + + if (dep_type == TYPE_CMOVE) + { + /* Instructions that read the result of conditional moves cannot + be in the same group or the following group. */ + return cost + 1; + } + + switch (insn_type) + { + /* UltraSPARC can dual issue a store and an instruction setting + the value stored, except for divide and square root. */ + case TYPE_FPSTORE: + if (! SLOW_FP (dep_type)) + return 0; + return cost; + + case TYPE_STORE: + if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) + return cost; + + if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) + /* The dependency between the two instructions is on the data + that is being stored. Assume that the address of the store + is not also dependent. */ + return 0; + return cost; + + case TYPE_LOAD: + case TYPE_SLOAD: + case TYPE_FPLOAD: + /* A load does not return data until at least 11 cycles after + a store to the same location. 3 cycles are accounted for + in the load latency; add the other 8 here. */ + if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) + { + /* If the addresses are not equal this may be a false + dependency because pointer aliasing could not be + determined. Add only 2 cycles in that case. 2 is + an arbitrary compromise between 8, which would cause + the scheduler to generate worse code elsewhere to + compensate for a dependency which might not really + exist, and 0. */ + if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET + || GET_CODE (SET_SRC (pat)) != MEM + || GET_CODE (SET_DEST (dep_pat)) != MEM + || ! rtx_equal_p (XEXP (SET_SRC (pat), 0), + XEXP (SET_DEST (dep_pat), 0))) + return cost + 2; + + return cost + 8; + } + return cost; + + case TYPE_BRANCH: + /* Compare to branch latency is 0. There is no benefit from + separating compare and branch. */ + if (dep_type == TYPE_COMPARE) + return 0; + /* Floating point compare to branch latency is less than + compare to conditional move. */ + if (dep_type == TYPE_FPCMP) + return cost - 1; + return cost; + + case TYPE_FPCMOVE: + /* FMOVR class instructions can not issue in the same cycle + or the cycle after an instruction which writes any + integer register. Model this as cost 2 for dependent + instructions. */ + if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY + || dep_type == TYPE_BINARY) + && cost < 2) + return 2; + /* Otherwise check as for integer conditional moves. */ + + case TYPE_CMOVE: + /* Conditional moves involving integer registers wait until + 3 cycles after loads return data. The interlock applies + to all loads, not just dependent loads, but that is hard + to model. */ + if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD) + return cost + 3; + return cost; + + default: + break; + } + break; + + case REG_DEP_ANTI: + /* Divide and square root lock destination registers for full latency. */ + if (! SLOW_FP (dep_type)) + return 0; + break; + + case REG_DEP_OUTPUT: + /* IEU and FPU instruction that have the same destination + register cannot be grouped together. */ + return cost + 1; + + default: + break; + } + + /* Other costs not accounted for: + - Single precision floating point loads lock the other half of + the even/odd register pair. + - Several hazards associated with ldd/std are ignored because these + instructions are rarely generated for V9. + - The floating point pipeline can not have both a single and double + precision operation active at the same time. Format conversions + and graphics instructions are given honorary double precision status. + - call and jmpl are always the first instruction in a group. */ + + return cost; + +#undef SLOW_FP +} + +int +sparc_adjust_cost(insn, link, dep, cost) + rtx insn; + rtx link; + rtx dep; + int cost; +{ + switch (sparc_cpu) + { + case PROCESSOR_SUPERSPARC: + cost = supersparc_adjust_cost (insn, link, dep, cost); + break; + case PROCESSOR_HYPERSPARC: + case PROCESSOR_SPARCLITE86X: + cost = hypersparc_adjust_cost (insn, link, dep, cost); + break; + case PROCESSOR_ULTRASPARC: + cost = ultrasparc_adjust_cost (insn, link, dep, cost); + break; + default: + break; + } + return cost; +} + +/* This describes the state of the UltraSPARC pipeline during + instruction scheduling. */ + +#define TMASK(__x) ((unsigned)1 << ((int)(__x))) +#define UMASK(__x) ((unsigned)1 << ((int)(__x))) + +enum ultra_code { NONE=0, /* no insn at all */ + IEU0, /* shifts and conditional moves */ + IEU1, /* condition code setting insns, calls+jumps */ + IEUN, /* all other single cycle ieu insns */ + LSU, /* loads and stores */ + CTI, /* branches */ + FPM, /* FPU pipeline 1, multiplies and divides */ + FPA, /* FPU pipeline 2, all other operations */ + SINGLE, /* single issue instructions */ + NUM_ULTRA_CODES }; + +static const char *ultra_code_names[NUM_ULTRA_CODES] = { + "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI", + "FPM", "FPA", "SINGLE" }; + +struct ultrasparc_pipeline_state { + /* The insns in this group. */ + rtx group[4]; + + /* The code for each insn. */ + enum ultra_code codes[4]; + + /* Which insns in this group have been committed by the + scheduler. This is how we determine how many more + can issue this cycle. */ + char commit[4]; + + /* How many insns in this group. */ + char group_size; + + /* Mask of free slots still in this group. */ + char free_slot_mask; + + /* The slotter uses the following to determine what other + insn types can still make their way into this group. */ + char contents [NUM_ULTRA_CODES]; + char num_ieu_insns; +}; + +#define ULTRA_NUM_HIST 8 +static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST]; +static int ultra_cur_hist; +static int ultra_cycles_elapsed; + +#define ultra_pipe (ultra_pipe_hist[ultra_cur_hist]) + +/* Given TYPE_MASK compute the ultra_code it has. */ +static enum ultra_code +ultra_code_from_mask (type_mask) + int type_mask; +{ + if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE))) + return IEU0; + else if (type_mask & (TMASK (TYPE_COMPARE) | + TMASK (TYPE_CALL) | + TMASK (TYPE_UNCOND_BRANCH))) + return IEU1; + else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | + TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY))) + return IEUN; + else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | + TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | + TMASK (TYPE_FPSTORE))) + return LSU; + else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) | + TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT))) + return FPM; + else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | + TMASK (TYPE_FP) | TMASK (TYPE_FPCMP))) + return FPA; + else if (type_mask & TMASK (TYPE_BRANCH)) + return CTI; + + return SINGLE; +} + +/* Check INSN (a conditional move) and make sure that it's + results are available at this cycle. Return 1 if the + results are in fact ready. */ +static int +ultra_cmove_results_ready_p (insn) + rtx insn; +{ + struct ultrasparc_pipeline_state *up; + int entry, slot; + + /* If this got dispatched in the previous + group, the results are not ready. */ + entry = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1); + up = &ultra_pipe_hist[entry]; + slot = 4; + while (--slot >= 0) + if (up->group[slot] == insn) + return 0; + + return 1; +} + +/* Walk backwards in pipeline history looking for FPU + operations which use a mode different than FPMODE and + will create a stall if an insn using FPMODE were to be + dispatched this cycle. */ +static int +ultra_fpmode_conflict_exists (fpmode) + enum machine_mode fpmode; +{ + int hist_ent; + int hist_lim; + + hist_ent = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1); + if (ultra_cycles_elapsed < 4) + hist_lim = ultra_cycles_elapsed; + else + hist_lim = 4; + while (hist_lim > 0) + { + struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent]; + int slot = 4; + + while (--slot >= 0) + { + rtx insn = up->group[slot]; + enum machine_mode this_mode; + rtx pat; + + if (! insn + || GET_CODE (insn) != INSN + || (pat = PATTERN (insn)) == 0 + || GET_CODE (pat) != SET) + continue; + + this_mode = GET_MODE (SET_DEST (pat)); + if ((this_mode != SFmode + && this_mode != DFmode) + || this_mode == fpmode) + continue; + + /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then + we will get a stall. Loads and stores are independant + of these rules. */ + if (GET_CODE (SET_SRC (pat)) != ABS + && GET_CODE (SET_SRC (pat)) != NEG + && ((TMASK (get_attr_type (insn)) & + (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | + TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) | + TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0)) + return 1; + } + hist_lim--; + hist_ent = (hist_ent - 1) % (ULTRA_NUM_HIST - 1); + } + + /* No conflicts, safe to dispatch. */ + return 0; +} + +/* Find an instruction in LIST which has one of the + type attributes enumerated in TYPE_MASK. START + says where to begin the search. + + NOTE: This scheme depends upon the fact that we + have less than 32 distinct type attributes. */ + +static int ultra_types_avail; + +static rtx * +ultra_find_type (type_mask, list, start) + int type_mask; + rtx *list; + int start; +{ + int i; + + /* Short circuit if no such insn exists in the ready + at the moment. */ + if ((type_mask & ultra_types_avail) == 0) + return 0; + + for (i = start; i >= 0; i--) + { + rtx insn = list[i]; + + if (recog_memoized (insn) >= 0 + && (TMASK(get_attr_type (insn)) & type_mask)) + { + enum machine_mode fpmode = SFmode; + rtx pat = 0; + int slot; + int check_depend = 0; + int check_fpmode_conflict = 0; + + if (GET_CODE (insn) == INSN + && (pat = PATTERN(insn)) != 0 + && GET_CODE (pat) == SET + && !(type_mask & (TMASK (TYPE_STORE) | + TMASK (TYPE_FPSTORE)))) + { + check_depend = 1; + if (GET_MODE (SET_DEST (pat)) == SFmode + || GET_MODE (SET_DEST (pat)) == DFmode) + { + fpmode = GET_MODE (SET_DEST (pat)); + check_fpmode_conflict = 1; + } + } + + slot = 4; + while(--slot >= 0) + { + rtx slot_insn = ultra_pipe.group[slot]; + rtx slot_pat; + + /* Already issued, bad dependency, or FPU + mode conflict. */ + if (slot_insn != 0 + && (slot_pat = PATTERN (slot_insn)) != 0 + && ((insn == slot_insn) + || (check_depend == 1 + && GET_CODE (slot_insn) == INSN + && GET_CODE (slot_pat) == SET + && ((GET_CODE (SET_DEST (slot_pat)) == REG + && GET_CODE (SET_SRC (pat)) == REG + && REGNO (SET_DEST (slot_pat)) == + REGNO (SET_SRC (pat))) + || (GET_CODE (SET_DEST (slot_pat)) == SUBREG + && GET_CODE (SET_SRC (pat)) == SUBREG + && REGNO (SUBREG_REG (SET_DEST (slot_pat))) == + REGNO (SUBREG_REG (SET_SRC (pat))) + && SUBREG_WORD (SET_DEST (slot_pat)) == + SUBREG_WORD (SET_SRC (pat))))) + || (check_fpmode_conflict == 1 + && GET_CODE (slot_insn) == INSN + && GET_CODE (slot_pat) == SET + && (GET_MODE (SET_DEST (slot_pat)) == SFmode + || GET_MODE (SET_DEST (slot_pat)) == DFmode) + && GET_MODE (SET_DEST (slot_pat)) != fpmode))) + goto next; + } + + /* Check for peculiar result availability and dispatch + interference situations. */ + if (pat != 0 + && ultra_cycles_elapsed > 0) + { + rtx link; + + for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) + { + rtx link_insn = XEXP (link, 0); + if (GET_CODE (link_insn) == INSN + && recog_memoized (link_insn) >= 0 + && (TMASK (get_attr_type (link_insn)) & + (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE))) + && ! ultra_cmove_results_ready_p (link_insn)) + goto next; + } + + if (check_fpmode_conflict + && ultra_fpmode_conflict_exists (fpmode)) + goto next; + } + + return &list[i]; + } + next: + ; + } + return 0; +} + +static void +ultra_build_types_avail (ready, n_ready) + rtx *ready; + int n_ready; +{ + int i = n_ready - 1; + + ultra_types_avail = 0; + while(i >= 0) + { + rtx insn = ready[i]; + + if (recog_memoized (insn) >= 0) + ultra_types_avail |= TMASK (get_attr_type (insn)); + + i -= 1; + } +} + +/* Place insn pointed to my IP into the pipeline. + Make element THIS of READY be that insn if it + is not already. TYPE indicates the pipeline class + this insn falls into. */ +static void +ultra_schedule_insn (ip, ready, this, type) + rtx *ip; + rtx *ready; + int this; + enum ultra_code type; +{ + int pipe_slot; + char mask = ultra_pipe.free_slot_mask; + + /* Obtain free slot. */ + for (pipe_slot = 0; pipe_slot < 4; pipe_slot++) + if ((mask & (1 << pipe_slot)) != 0) + break; + if (pipe_slot == 4) + abort (); + + /* In it goes, and it hasn't been committed yet. */ + ultra_pipe.group[pipe_slot] = *ip; + ultra_pipe.codes[pipe_slot] = type; + ultra_pipe.contents[type] = 1; + if (UMASK (type) & + (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) + ultra_pipe.num_ieu_insns += 1; + + ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot)); + ultra_pipe.group_size += 1; + ultra_pipe.commit[pipe_slot] = 0; + + /* Update ready list. */ + if (ip != &ready[this]) + { + rtx temp = *ip; + + *ip = ready[this]; + ready[this] = temp; + } +} + +/* Advance to the next pipeline group. */ +static void +ultra_flush_pipeline () +{ + ultra_cur_hist = (ultra_cur_hist + 1) % (ULTRA_NUM_HIST - 1); + ultra_cycles_elapsed += 1; + bzero ((char *) &ultra_pipe, sizeof ultra_pipe); + ultra_pipe.free_slot_mask = 0xf; +} + +static int ultra_reorder_called_this_block; + +/* Init our data structures for this current block. */ +void +ultrasparc_sched_init (dump, sched_verbose) + FILE *dump ATTRIBUTE_UNUSED; + int sched_verbose ATTRIBUTE_UNUSED; +{ + bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist); + ultra_cur_hist = 0; + ultra_cycles_elapsed = 0; + ultra_reorder_called_this_block = 0; + ultra_pipe.free_slot_mask = 0xf; +} + +/* INSN has been scheduled, update pipeline commit state + and return how many instructions are still to be + scheduled in this group. */ +int +ultrasparc_variable_issue (insn) + rtx insn; +{ + struct ultrasparc_pipeline_state *up = &ultra_pipe; + int i, left_to_fire; + + left_to_fire = 0; + for (i = 0; i < 4; i++) + { + if (up->group[i] == 0) + continue; + + if (up->group[i] == insn) + { + up->commit[i] = 1; + } + else if (! up->commit[i]) + left_to_fire++; + } + + return left_to_fire; +} + +/* In actual_hazard_this_instance, we may have yanked some + instructions from the ready list due to conflict cost + adjustments. If so, and such an insn was in our pipeline + group, remove it and update state. */ +static void +ultra_rescan_pipeline_state (ready, n_ready) + rtx *ready; + int n_ready; +{ + struct ultrasparc_pipeline_state *up = &ultra_pipe; + int i; + + for (i = 0; i < 4; i++) + { + rtx insn = up->group[i]; + int j; + + if (! insn) + continue; + + /* If it has been committed, then it was removed from + the ready list because it was actually scheduled, + and that is not the case we are searching for here. */ + if (up->commit[i] != 0) + continue; + + for (j = n_ready - 1; j >= 0; j--) + if (ready[j] == insn) + break; + + /* If we didn't find it, toss it. */ + if (j < 0) + { + enum ultra_code ucode = up->codes[i]; + + up->group[i] = 0; + up->codes[i] = NONE; + up->contents[ucode] = 0; + if (UMASK (ucode) & + (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) + up->num_ieu_insns -= 1; + + up->free_slot_mask |= (1 << i); + up->group_size -= 1; + up->commit[i] = 0; + } + } +} + +void +ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) + FILE *dump; + int sched_verbose; + rtx *ready; + int n_ready; +{ + struct ultrasparc_pipeline_state *up = &ultra_pipe; + int i, this_insn; + + /* We get called once unnecessarily per block of insns + scheduled. */ + if (ultra_reorder_called_this_block == 0) + { + ultra_reorder_called_this_block = 1; + return; + } + + if (sched_verbose) + { + int n; + + fprintf (dump, "\n;;\tUltraSPARC Looking at ["); + for (n = n_ready - 1; n >= 0; n--) + { + rtx insn = ready[n]; + enum ultra_code ucode; + + if (recog_memoized (insn) < 0) + continue; + ucode = ultra_code_from_mask (TMASK (get_attr_type (insn))); + if (n != 0) + fprintf (dump, "%s(%d) ", + ultra_code_names[ucode], + INSN_UID (insn)); + else + fprintf (dump, "%s(%d)", + ultra_code_names[ucode], + INSN_UID (insn)); + } + fprintf (dump, "]\n"); + } + + this_insn = n_ready - 1; + + /* Skip over junk we don't understand. */ + while ((this_insn >= 0) + && recog_memoized (ready[this_insn]) < 0) + this_insn--; + + ultra_build_types_avail (ready, this_insn + 1); + + while (this_insn >= 0) { + int old_group_size = up->group_size; + + if (up->group_size != 0) + { + int num_committed; + + num_committed = (up->commit[0] + up->commit[1] + + up->commit[2] + up->commit[3]); + /* If nothing has been commited from our group, or all of + them have. Clear out the (current cycle's) pipeline + state and start afresh. */ + if (num_committed == 0 + || num_committed == up->group_size) + { + ultra_flush_pipeline (); + up = &ultra_pipe; + old_group_size = 0; + } + else + { + /* OK, some ready list insns got requeued and thus removed + from the ready list. Account for this fact. */ + ultra_rescan_pipeline_state (ready, n_ready); + + /* Something "changed", make this look like a newly + formed group so the code at the end of the loop + knows that progress was in fact made. */ + if (up->group_size != old_group_size) + old_group_size = 0; + } + } + + if (up->group_size == 0) + { + /* If the pipeline is (still) empty and we have any single + group insns, get them out now as this is a good time. */ + rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) | + TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) | + TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)), + ready, this_insn); + if (ip) + { + ultra_schedule_insn (ip, ready, this_insn, SINGLE); + break; + } + + /* If we are not in the process of emptying out the pipe, try to + obtain an instruction which must be the first in it's group. */ + ip = ultra_find_type ((TMASK (TYPE_CALL) | + TMASK (TYPE_CALL_NO_DELAY_SLOT) | + TMASK (TYPE_UNCOND_BRANCH)), + ready, this_insn); + if (ip) + { + ultra_schedule_insn (ip, ready, this_insn, IEU1); + this_insn--; + } + else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) | + TMASK (TYPE_FPDIVD) | + TMASK (TYPE_FPSQRT)), + ready, this_insn)) != 0) + { + ultra_schedule_insn (ip, ready, this_insn, FPM); + this_insn--; + } + } + + /* Try to fill the integer pipeline. First, look for an IEU0 specific + operation. We can't do more IEU operations if the first 3 slots are + all full or we have dispatched two IEU insns already. */ + if ((up->free_slot_mask & 0x7) != 0 + && up->num_ieu_insns < 2 + && up->contents[IEU0] == 0 + && up->contents[IEUN] == 0) + { + rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn); + if (ip) + { + ultra_schedule_insn (ip, ready, this_insn, IEU0); + this_insn--; + } + } + + /* If we can, try to find an IEU1 specific or an unnamed + IEU instruction. */ + if ((up->free_slot_mask & 0x7) != 0 + && up->num_ieu_insns < 2) + { + rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | + TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) | + (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)), + ready, this_insn); + if (ip) + { + rtx insn = *ip; + + ultra_schedule_insn (ip, ready, this_insn, + (!up->contents[IEU1] + && get_attr_type (insn) == TYPE_COMPARE) + ? IEU1 : IEUN); + this_insn--; + } + } + + /* If only one IEU insn has been found, try to find another unnamed + IEU operation or an IEU1 specific one. */ + if ((up->free_slot_mask & 0x7) != 0 + && up->num_ieu_insns < 2) + { + rtx *ip; + int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | + TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)); + + if (!up->contents[IEU1]) + tmask |= TMASK (TYPE_COMPARE); + ip = ultra_find_type (tmask, ready, this_insn); + if (ip) + { + rtx insn = *ip; + + ultra_schedule_insn (ip, ready, this_insn, + (!up->contents[IEU1] + && get_attr_type (insn) == TYPE_COMPARE) + ? IEU1 : IEUN); + this_insn--; + } + } + + /* Try for a load or store, but such an insn can only be issued + if it is within' one of the first 3 slots. */ + if ((up->free_slot_mask & 0x7) != 0 + && up->contents[LSU] == 0) + { + rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | + TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | + TMASK (TYPE_FPSTORE)), ready, this_insn); + if (ip) + { + ultra_schedule_insn (ip, ready, this_insn, LSU); + this_insn--; + } + } + + /* Now find FPU operations, first FPM class. But not divisions or + square-roots because those will break the group up. Unlike all + the previous types, these can go in any slot. */ + if (up->free_slot_mask != 0 + && up->contents[FPM] == 0) + { + rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn); + if (ip) + { + ultra_schedule_insn (ip, ready, this_insn, FPM); + this_insn--; + } + } + + /* Continue on with FPA class if we have not filled the group already. */ + if (up->free_slot_mask != 0 + && up->contents[FPA] == 0) + { + rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | + TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)), + ready, this_insn); + if (ip) + { + ultra_schedule_insn (ip, ready, this_insn, FPA); + this_insn--; + } + } + + /* Finally, maybe stick a branch in here. */ + if (up->free_slot_mask != 0 + && up->contents[CTI] == 0) + { + rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn); + + /* Try to slip in a branch only if it is one of the + next 2 in the ready list. */ + if (ip && ((&ready[this_insn] - ip) < 2)) + { + ultra_schedule_insn (ip, ready, this_insn, CTI); + this_insn--; + } + } + + up->group_size = 0; + for (i = 0; i < 4; i++) + if ((up->free_slot_mask & (1 << i)) == 0) + up->group_size++; + + /* See if we made any progress... */ + if (old_group_size != up->group_size) + break; + + /* Clean out the (current cycle's) pipeline state + and try once more. If we placed no instructions + into the pipeline at all, it means a real hard + conflict exists with some earlier issued instruction + so we must advance to the next cycle to clear it up. */ + if (up->group_size == 0) + { + ultra_flush_pipeline (); + up = &ultra_pipe; + } + else + { + bzero ((char *) &ultra_pipe, sizeof ultra_pipe); + ultra_pipe.free_slot_mask = 0xf; + } + } + + if (sched_verbose) + { + int n, gsize; + + fprintf (dump, ";;\tUltraSPARC Launched ["); + gsize = up->group_size; + for (n = 0; n < 4; n++) + { + rtx insn = up->group[n]; + + if (! insn) + continue; + + gsize -= 1; + if (gsize != 0) + fprintf (dump, "%s(%d) ", + ultra_code_names[up->codes[n]], + INSN_UID (insn)); + else + fprintf (dump, "%s(%d)", + ultra_code_names[up->codes[n]], + INSN_UID (insn)); + } + fprintf (dump, "]\n"); + } +} + +int +sparc_issue_rate () +{ + switch (sparc_cpu) + { + default: + return 1; + case PROCESSOR_V9: + /* Assume V9 processors are capable of at least dual-issue. */ + return 2; + case PROCESSOR_SUPERSPARC: + return 3; + case PROCESSOR_HYPERSPARC: + case PROCESSOR_SPARCLITE86X: + return 2; + case PROCESSOR_ULTRASPARC: + return 4; + } +} + +static int +set_extends(x, insn) + rtx x, insn; +{ + register rtx pat = PATTERN (insn); + + switch (GET_CODE (SET_SRC (pat))) + { + /* Load and some shift instructions zero extend. */ + case MEM: + case ZERO_EXTEND: + /* sethi clears the high bits */ + case HIGH: + /* LO_SUM is used with sethi. sethi cleared the high + bits and the values used with lo_sum are positive */ + case LO_SUM: + /* Store flag stores 0 or 1 */ + case LT: case LTU: + case GT: case GTU: + case LE: case LEU: + case GE: case GEU: + case EQ: + case NE: + return 1; + case AND: + { + rtx op1 = XEXP (SET_SRC (pat), 1); + if (GET_CODE (op1) == CONST_INT) + return INTVAL (op1) >= 0; + if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG + && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1) + return 1; + if (GET_CODE (op1) == REG + && sparc_check_64 ((op1), insn) == 1) + return 1; + } + case ASHIFT: + case LSHIFTRT: + return GET_MODE (SET_SRC (pat)) == SImode; + /* Positive integers leave the high bits zero. */ + case CONST_DOUBLE: + return ! (CONST_DOUBLE_LOW (x) & 0x80000000); + case CONST_INT: + return ! (INTVAL (x) & 0x80000000); + case ASHIFTRT: + case SIGN_EXTEND: + return - (GET_MODE (SET_SRC (pat)) == SImode); + default: + return 0; + } +} + +/* We _ought_ to have only one kind per function, but... */ +static rtx sparc_addr_diff_list; +static rtx sparc_addr_list; + +void +sparc_defer_case_vector (lab, vec, diff) + rtx lab, vec; + int diff; +{ + vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); + if (diff) + sparc_addr_diff_list + = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); + else + sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); +} + +static void +sparc_output_addr_vec (vec) + rtx vec; +{ + rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); + int idx, vlen = XVECLEN (body, 0); + +#ifdef ASM_OUTPUT_ADDR_VEC_START + ASM_OUTPUT_ADDR_VEC_START (asm_out_file); +#endif + +#ifdef ASM_OUTPUT_CASE_LABEL + ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), + NEXT_INSN (lab)); +#else + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); +#endif + + for (idx = 0; idx < vlen; idx++) + { + ASM_OUTPUT_ADDR_VEC_ELT + (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); + } + +#ifdef ASM_OUTPUT_ADDR_VEC_END + ASM_OUTPUT_ADDR_VEC_END (asm_out_file); +#endif +} + +static void +sparc_output_addr_diff_vec (vec) + rtx vec; +{ + rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); + rtx base = XEXP (XEXP (body, 0), 0); + int idx, vlen = XVECLEN (body, 1); + +#ifdef ASM_OUTPUT_ADDR_VEC_START + ASM_OUTPUT_ADDR_VEC_START (asm_out_file); +#endif + +#ifdef ASM_OUTPUT_CASE_LABEL + ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), + NEXT_INSN (lab)); +#else + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); +#endif + + for (idx = 0; idx < vlen; idx++) + { + ASM_OUTPUT_ADDR_DIFF_ELT + (asm_out_file, + body, + CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), + CODE_LABEL_NUMBER (base)); + } + +#ifdef ASM_OUTPUT_ADDR_VEC_END + ASM_OUTPUT_ADDR_VEC_END (asm_out_file); +#endif +} + +static void +sparc_output_deferred_case_vectors () +{ + rtx t; + int align; + + if (sparc_addr_list == NULL_RTX + && sparc_addr_diff_list == NULL_RTX) + return; + + /* Align to cache line in the function's code section. */ + function_section (current_function_decl); + + align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); + if (align > 0) + ASM_OUTPUT_ALIGN (asm_out_file, align); + + for (t = sparc_addr_list; t ; t = XEXP (t, 1)) + sparc_output_addr_vec (XEXP (t, 0)); + for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) + sparc_output_addr_diff_vec (XEXP (t, 0)); + + sparc_addr_list = sparc_addr_diff_list = NULL_RTX; +} + +/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are + unknown. Return 1 if the high bits are zero, -1 if the register is + sign extended. */ +int +sparc_check_64 (x, insn) + rtx x, insn; +{ + /* If a register is set only once it is safe to ignore insns this + code does not know how to handle. The loop will either recognize + the single set and return the correct value or fail to recognize + it and return 0. */ + int set_once = 0; + + if (GET_CODE (x) == REG + && flag_expensive_optimizations + && REG_N_SETS (REGNO (x)) == 1) + set_once = 1; + + if (insn == 0) + { + if (set_once) + insn = get_last_insn_anywhere (); + else + return 0; + } + + while ((insn = PREV_INSN (insn))) + { + switch (GET_CODE (insn)) + { + case JUMP_INSN: + case NOTE: + break; + case CODE_LABEL: + case CALL_INSN: + default: + if (! set_once) + return 0; + break; + case INSN: + { + rtx pat = PATTERN (insn); + if (GET_CODE (pat) != SET) + return 0; + if (rtx_equal_p (x, SET_DEST (pat))) + return set_extends (x, insn); + if (reg_overlap_mentioned_p (SET_DEST (pat), x)) + return 0; + } + } + } + return 0; +} + +char * +sparc_v8plus_shift (operands, insn, opcode) + rtx *operands; + rtx insn; + char *opcode; +{ + static char asm_code[60]; + + if (GET_CODE (operands[3]) == SCRATCH) + operands[3] = operands[0]; + if (GET_CODE (operands[1]) == CONST_INT) + { + output_asm_insn ("mov %1,%3", operands); + } + else + { + output_asm_insn ("sllx %H1,32,%3", operands); + if (sparc_check_64 (operands[1], insn) <= 0) + output_asm_insn ("srl %L1,0,%L1", operands); + output_asm_insn ("or %L1,%3,%3", operands); + } + + strcpy(asm_code, opcode); + if (which_alternative != 2) + return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0"); + else + return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0"); +} + + +/* Return 1 if DEST and SRC reference only global and in registers. */ + +int +sparc_return_peephole_ok (dest, src) + rtx dest, src; +{ + if (! TARGET_V9) + return 0; + if (current_function_uses_only_leaf_regs) + return 0; + if (GET_CODE (src) != CONST_INT + && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src))) + return 0; + return IN_OR_GLOBAL_P (dest); +} + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. + + 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered + during profiling so we need to save/restore it around the call to mcount. + We're guaranteed that a save has just been done, and we use the space + allocated for intreg/fpreg value passing. */ + +void +sparc_function_profiler (file, labelno) + FILE *file; + int labelno; +{ + char buf[32]; + ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); + + if (! TARGET_ARCH64) + fputs ("\tst\t%g2,[%fp-4]\n", file); + + fputs ("\tsethi\t%hi(", file); + assemble_name (file, buf); + fputs ("),%o0\n", file); + + fputs ("\tcall\t", file); + assemble_name (file, MCOUNT_FUNCTION); + putc ('\n', file); + + fputs ("\t or\t%o0,%lo(", file); + assemble_name (file, buf); + fputs ("),%o0\n", file); + + if (! TARGET_ARCH64) + fputs ("\tld\t[%fp-4],%g2\n", file); +} + + +/* The following macro shall output assembler code to FILE + to initialize basic-block profiling. + + If profile_block_flag == 2 + + Output code to call the subroutine `__bb_init_trace_func' + and pass two parameters to it. The first parameter is + the address of a block allocated in the object module. + The second parameter is the number of the first basic block + of the function. + + The name of the block is a local symbol made with this statement: + + ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); + + Of course, since you are writing the definition of + `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you + can take a short cut in the definition of this macro and use the + name that you know will result. + + The number of the first basic block of the function is + passed to the macro in BLOCK_OR_LABEL. + + If described in a virtual assembler language the code to be + output looks like: + + parameter1 <- LPBX0 + parameter2 <- BLOCK_OR_LABEL + call __bb_init_trace_func + + else if profile_block_flag != 0 + + Output code to call the subroutine `__bb_init_func' + and pass one single parameter to it, which is the same + as the first parameter to `__bb_init_trace_func'. + + The first word of this parameter is a flag which will be nonzero if + the object module has already been initialized. So test this word + first, and do not call `__bb_init_func' if the flag is nonzero. + Note: When profile_block_flag == 2 the test need not be done + but `__bb_init_trace_func' *must* be called. + + BLOCK_OR_LABEL may be used to generate a label number as a + branch destination in case `__bb_init_func' will not be called. + + If described in a virtual assembler language the code to be + output looks like: + + cmp (LPBX0),0 + jne local_label + parameter1 <- LPBX0 + call __bb_init_func + local_label: + +*/ + +void +sparc_function_block_profiler(file, block_or_label) + FILE *file; + int block_or_label; +{ + char LPBX[32]; + ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0); + + if (profile_block_flag == 2) + { + fputs ("\tsethi\t%hi(", file); + assemble_name (file, LPBX); + fputs ("),%o0\n", file); + + fprintf (file, "\tsethi\t%%hi(%d),%%o1\n", block_or_label); + + fputs ("\tor\t%o0,%lo(", file); + assemble_name (file, LPBX); + fputs ("),%o0\n", file); + + fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix); + + fprintf (file, "\t or\t%%o1,%%lo(%d),%%o1\n", block_or_label); + } + else if (profile_block_flag != 0) + { + char LPBY[32]; + ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label); + + fputs ("\tsethi\t%hi(", file); + assemble_name (file, LPBX); + fputs ("),%o0\n", file); + + fputs ("\tld\t[%lo(", file); + assemble_name (file, LPBX); + fputs (")+%o0],%o1\n", file); + + fputs ("\ttst\t%o1\n", file); + + if (TARGET_V9) + { + fputs ("\tbne,pn\t%icc,", file); + assemble_name (file, LPBY); + putc ('\n', file); + } + else + { + fputs ("\tbne\t", file); + assemble_name (file, LPBY); + putc ('\n', file); + } + + fputs ("\t or\t%o0,%lo(", file); + assemble_name (file, LPBX); + fputs ("),%o0\n", file); + + fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix); + + ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label); + } +} + +/* The following macro shall output assembler code to FILE + to increment a counter associated with basic block number BLOCKNO. + + If profile_block_flag == 2 + + Output code to initialize the global structure `__bb' and + call the function `__bb_trace_func' which will increment the + counter. + + `__bb' consists of two words. In the first word the number + of the basic block has to be stored. In the second word + the address of a block allocated in the object module + has to be stored. + + The basic block number is given by BLOCKNO. + + The address of the block is given by the label created with + + ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); + + by FUNCTION_BLOCK_PROFILER. + + Of course, since you are writing the definition of + `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you + can take a short cut in the definition of this macro and use the + name that you know will result. + + If described in a virtual assembler language the code to be + output looks like: + + move BLOCKNO -> (__bb) + move LPBX0 -> (__bb+4) + call __bb_trace_func + + Note that function `__bb_trace_func' must not change the + machine state, especially the flag register. To grant + this, you must output code to save and restore registers + either in this macro or in the macros MACHINE_STATE_SAVE + and MACHINE_STATE_RESTORE. The last two macros will be + used in the function `__bb_trace_func', so you must make + sure that the function prologue does not change any + register prior to saving it with MACHINE_STATE_SAVE. + + else if profile_block_flag != 0 + + Output code to increment the counter directly. + Basic blocks are numbered separately from zero within each + compiled object module. The count associated with block number + BLOCKNO is at index BLOCKNO in an array of words; the name of + this array is a local symbol made with this statement: + + ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); + + Of course, since you are writing the definition of + `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you + can take a short cut in the definition of this macro and use the + name that you know will result. + + If described in a virtual assembler language, the code to be + output looks like: + + inc (LPBX2+4*BLOCKNO) + +*/ + +void +sparc_block_profiler(file, blockno) + FILE *file; + int blockno; +{ + char LPBX[32]; + + if (profile_block_flag == 2) + { + ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0); + + fprintf (file, "\tsethi\t%%hi(%s__bb),%%g1\n", user_label_prefix); + fprintf (file, "\tsethi\t%%hi(%d),%%g2\n", blockno); + fprintf (file, "\tor\t%%g1,%%lo(%s__bb),%%g1\n", user_label_prefix); + fprintf (file, "\tor\t%%g2,%%lo(%d),%%g2\n", blockno); + + fputs ("\tst\t%g2,[%g1]\n", file); + + fputs ("\tsethi\t%hi(", file); + assemble_name (file, LPBX); + fputs ("),%g2\n", file); + + fputs ("\tor\t%g2,%lo(", file); + assemble_name (file, LPBX); + fputs ("),%g2\n", file); + + fputs ("\tst\t%g2,[%g1+4]\n", file); + fputs ("\tmov\t%o7,%g2\n", file); + + fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix); + + fputs ("\tmov\t%g2,%o7\n", file); + } + else if (profile_block_flag != 0) + { + ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2); + + fputs ("\tsethi\t%hi(", file); + assemble_name (file, LPBX); + fprintf (file, "+%d),%%g1\n", blockno*4); + + fputs ("\tld\t[%g1+%lo(", file); + assemble_name (file, LPBX); + fprintf (file, "+%d)],%%g2\n", blockno*4); + + fputs ("\tadd\t%g2,1,%g2\n", file); + + fputs ("\tst\t%g2,[%g1+%lo(", file); + assemble_name (file, LPBX); + fprintf (file, "+%d)]\n", blockno*4); + } +} + +/* The following macro shall output assembler code to FILE + to indicate a return from function during basic-block profiling. + + If profile_block_flag == 2: + + Output assembler code to call function `__bb_trace_ret'. + + Note that function `__bb_trace_ret' must not change the + machine state, especially the flag register. To grant + this, you must output code to save and restore registers + either in this macro or in the macros MACHINE_STATE_SAVE_RET + and MACHINE_STATE_RESTORE_RET. The last two macros will be + used in the function `__bb_trace_ret', so you must make + sure that the function prologue does not change any + register prior to saving it with MACHINE_STATE_SAVE_RET. + + else if profile_block_flag != 0: + + The macro will not be used, so it need not distinguish + these cases. +*/ + +void +sparc_function_block_profiler_exit(file) + FILE *file; +{ + if (profile_block_flag == 2) + fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix); + else + abort (); +} diff --git a/contrib/gcc/config/sparc/sparc.h b/contrib/gcc/config/sparc/sparc.h new file mode 100644 index 000000000000..ad11d74afc14 --- /dev/null +++ b/contrib/gcc/config/sparc/sparc.h @@ -0,0 +1,3309 @@ +/* Definitions of target machine for GNU compiler, for Sun SPARC. + Copyright (C) 1987, 88, 89, 92, 94-98, 1999 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com). + 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, + at Cygnus Support. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Note that some other tm.h files include this one and then override + whatever definitions are necessary. */ + +/* Specify this in a cover file to provide bi-architecture (32/64) support. */ +/* #define SPARC_BI_ARCH */ + +/* Macro used later in this file to determine default architecture. */ +#define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) + +/* TARGET_ARCH{32,64} are the main macros to decide which of the two + architectures to compile for. We allow targets to choose compile time or + runtime selection. */ +#ifdef SPARC_BI_ARCH +#ifdef IN_LIBGCC2 +#if defined(__sparcv9) || defined(__sparcv_v9) || defined(__arch64__) +#define TARGET_ARCH32 0 +#else +#define TARGET_ARCH32 1 +#endif /* V9 sparc */ +#else +#define TARGET_ARCH32 (! TARGET_64BIT) +#endif /* IN_LIBGCC2 */ +#else +#define TARGET_ARCH32 (DEFAULT_ARCH32_P) +#endif /* SPARC_BI_ARCH */ +#define TARGET_ARCH64 (! TARGET_ARCH32) + +/* Code model selection. + -mcmodel is used to select the v9 code model. + Different code models aren't supported for v8 code. + + TARGET_CM_32: 32 bit address space, top 32 bits = 0, + pointers are 32 bits. Note that this isn't intended + to imply a v8 abi. + + TARGET_CM_MEDLOW: 32 bit address space, top 32 bits = 0, + avoid generating %uhi and %ulo terms, + pointers are 64 bits. + + TARGET_CM_MEDMID: 64 bit address space. + The executable must be in the low 16 TB of memory. + This corresponds to the low 44 bits, and the %[hml]44 + relocs are used. The text segment has a maximum size + of 31 bits. + + TARGET_CM_MEDANY: 64 bit address space. + The text and data segments have a maximum size of 31 + bits and may be located anywhere. The maximum offset + from any instruction to the label _GLOBAL_OFFSET_TABLE_ + is 31 bits. + + TARGET_CM_EMBMEDANY: 64 bit address space. + The text and data segments have a maximum size of 31 bits + and may be located anywhere. Register %g4 contains + the start address of the data segment. +*/ + +enum cmodel { + CM_32, + CM_MEDLOW, + CM_MEDMID, + CM_MEDANY, + CM_EMBMEDANY +}; + +/* Value of -mcmodel specified by user. */ +extern const char *sparc_cmodel_string; +/* One of CM_FOO. */ +extern enum cmodel sparc_cmodel; + +/* V9 code model selection. */ +#define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) +#define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) +#define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) +#define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) + +#define SPARC_DEFAULT_CMODEL CM_MEDLOW + +/* This is call-clobbered in the normal ABI, but is reserved in the + home grown (aka upward compatible) embedded ABI. */ +#define EMBMEDANY_BASE_REG "%g4" + +/* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, + and specified by the user via --with-cpu=foo. + This specifies the cpu implementation, not the architecture size. */ +/* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit + capable cpu's. */ +#define TARGET_CPU_sparc 0 +#define TARGET_CPU_v7 0 /* alias for previous */ +#define TARGET_CPU_sparclet 1 +#define TARGET_CPU_sparclite 2 +#define TARGET_CPU_v8 3 /* generic v8 implementation */ +#define TARGET_CPU_supersparc 4 +#define TARGET_CPU_hypersparc 5 +#define TARGET_CPU_sparc86x 6 +#define TARGET_CPU_sparclite86x 6 +#define TARGET_CPU_v9 7 /* generic v9 implementation */ +#define TARGET_CPU_sparcv9 7 /* alias */ +#define TARGET_CPU_sparc64 7 /* alias */ +#define TARGET_CPU_ultrasparc 8 + +#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc + +#define CPP_CPU32_DEFAULT_SPEC "" +#define ASM_CPU32_DEFAULT_SPEC "" + +#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 +/* ??? What does Sun's CC pass? */ +#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" +/* ??? It's not clear how other assemblers will handle this, so by default + use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case + is handled in sol2.h. */ +#define ASM_CPU64_DEFAULT_SPEC "-Av9" +#endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc +#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" +#define ASM_CPU64_DEFAULT_SPEC "-Av9a" +#endif + +#else + +#define CPP_CPU64_DEFAULT_SPEC "" +#define ASM_CPU64_DEFAULT_SPEC "" + +#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ + || TARGET_CPU_DEFAULT == TARGET_CPU_v8 +#define CPP_CPU32_DEFAULT_SPEC "" +#define ASM_CPU32_DEFAULT_SPEC "" +#endif + +#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet +#define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" +#define ASM_CPU32_DEFAULT_SPEC "-Asparclet" +#endif + +#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite +#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" +#define ASM_CPU32_DEFAULT_SPEC "-Asparclite" +#endif + +#if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc +#define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" +#define ASM_CPU32_DEFAULT_SPEC "" +#endif + +#if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc +#define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" +#define ASM_CPU32_DEFAULT_SPEC "" +#endif + +#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x +#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__ -D__sparc_v8__" +#define ASM_CPU32_DEFAULT_SPEC "-Av8" +#endif + +#endif + +#if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) +Unrecognized value in TARGET_CPU_DEFAULT. +#endif + +#ifdef SPARC_BI_ARCH + +#define CPP_CPU_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? "\ +%{m64:" CPP_CPU64_DEFAULT_SPEC "} \ +%{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ +" : "\ +%{m32:" CPP_CPU32_DEFAULT_SPEC "} \ +%{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ +") +#define ASM_CPU_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? "\ +%{m64:" ASM_CPU64_DEFAULT_SPEC "} \ +%{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ +" : "\ +%{m32:" ASM_CPU32_DEFAULT_SPEC "} \ +%{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ +") + +#else /* !SPARC_BI_ARCH */ + +#define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) +#define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) + +#endif /* !SPARC_BI_ARCH */ + +/* Names to predefine in the preprocessor for this target machine. + ??? It would be nice to not include any subtarget specific values here, + however there's no way to portably provide subtarget values to + CPP_PREFINES. Also, -D values in CPP_SUBTARGET_SPEC don't get turned into + foo, __foo and __foo__. */ + +#define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -Asystem(unix) -Asystem(bsd)" + +/* Define macros to distinguish architectures. */ + +/* Common CPP definitions used by CPP_SPEC amongst the various targets + for handling -mcpu=xxx switches. */ +#define CPP_CPU_SPEC "\ +%{mcypress:} \ +%{msparclite:-D__sparclite__} \ +%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ +%{mv8:-D__sparc_v8__} \ +%{msupersparc:-D__supersparc__ -D__sparc_v8__} \ +%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ +%{mcpu=sparclite:-D__sparclite__} \ +%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ +%{mcpu=v8:-D__sparc_v8__} \ +%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ +%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ +%{mcpu=sparclite86x:-D__sparclite86x__ -D__sparc_v8__} \ +%{mcpu=v9:-D__sparc_v9__} \ +%{mcpu=ultrasparc:-D__sparc_v9__} \ +%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ +" + +/* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses + the right varags.h file when bootstrapping. */ +/* ??? It's not clear what value we want to use for -Acpu/machine for + sparc64 in 32 bit environments, so for now we only use `sparc64' in + 64 bit environments. */ + +#ifdef SPARC_BI_ARCH + +#define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \ +-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)" +#define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \ +-D__arch64__ -Acpu(sparc64) -Amachine(sparc64)" + +#else + +#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu(sparc) -Amachine(sparc)" +#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu(sparc64) -Amachine(sparc64)" + +#endif + +#define CPP_ARCH_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) + +#define CPP_ARCH_SPEC "\ +%{m32:%(cpp_arch32)} \ +%{m64:%(cpp_arch64)} \ +%{!m32:%{!m64:%(cpp_arch_default)}} \ +" + +/* Macros to distinguish endianness. */ +#define CPP_ENDIAN_SPEC "\ +%{mlittle-endian:-D__LITTLE_ENDIAN__} \ +%{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" + +/* Macros to distinguish the particular subtarget. */ +#define CPP_SUBTARGET_SPEC "" + +#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" + +/* Prevent error on `-sun4' and `-target sun4' options. */ +/* This used to translate -dalign to -malign, but that is no good + because it can't turn off the usual meaning of making debugging dumps. */ +/* Translate old style -m<cpu> into new style -mcpu=<cpu>. + ??? Delete support for -m<cpu> for 2.9. */ + +#define CC1_SPEC "\ +%{sun4:} %{target:} \ +%{mcypress:-mcpu=cypress} \ +%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ +%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ +" + +/* Override in target specific files. */ +#define ASM_CPU_SPEC "\ +%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ +%{msparclite:-Asparclite} \ +%{mf930:-Asparclite} %{mf934:-Asparclite} \ +%{mcpu=sparclite:-Asparclite} \ +%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ +%{mv8plus:-Av8plus} \ +%{mcpu=v9:-Av9} \ +%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ +%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ +" + +/* Word size selection, among other things. + This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ + +#define ASM_ARCH32_SPEC "-32" +#define ASM_ARCH64_SPEC "-64" +#define ASM_ARCH_DEFAULT_SPEC \ +(DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) + +#define ASM_ARCH_SPEC "\ +%{m32:%(asm_arch32)} \ +%{m64:%(asm_arch64)} \ +%{!m32:%{!m64:%(asm_arch_default)}} \ +" + +/* Special flags to the Sun-4 assembler when using pipe for input. */ + +#define ASM_SPEC "\ +%| %{R} %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}} %{keep-local-as-symbols:-L} \ +%(asm_cpu) \ +" + +#define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" + +/* Provide required defaults for linker -e and -d switches. */ + +#define LINK_SPEC \ + "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ + %{assert*} %{shared:%{!mimpure-text:-assert pure-text}}" + +/* This macro defines names of additional specifications to put in the specs + that can be used in various specifications like CC1_SPEC. Its definition + is an initializer with a subgrouping for each command option. + + Each subgrouping contains a string constant, that defines the + specification name, and a string constant that used by the GNU CC driver + program. + + Do not define this macro if it does not need to do anything. */ + +#define EXTRA_SPECS \ + { "cpp_cpu", CPP_CPU_SPEC }, \ + { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ + { "cpp_arch32", CPP_ARCH32_SPEC }, \ + { "cpp_arch64", CPP_ARCH64_SPEC }, \ + { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ + { "cpp_arch", CPP_ARCH_SPEC }, \ + { "cpp_endian", CPP_ENDIAN_SPEC }, \ + { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ + { "asm_cpu", ASM_CPU_SPEC }, \ + { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ + { "asm_arch32", ASM_ARCH32_SPEC }, \ + { "asm_arch64", ASM_ARCH64_SPEC }, \ + { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ + { "asm_arch", ASM_ARCH_SPEC }, \ + SUBTARGET_EXTRA_SPECS + +#define SUBTARGET_EXTRA_SPECS + +#ifdef SPARC_BI_ARCH +#define NO_BUILTIN_PTRDIFF_TYPE +#define NO_BUILTIN_SIZE_TYPE +#endif +#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") +#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") + +/* ??? This should be 32 bits for v9 but what can we do? */ +#define WCHAR_TYPE "short unsigned int" +#define WCHAR_TYPE_SIZE 16 +#define MAX_WCHAR_TYPE_SIZE 16 + +/* Show we can debug even without a frame pointer. */ +#define CAN_DEBUG_WITHOUT_FP + +/* To make profiling work with -f{pic,PIC}, we need to emit the profiling + code into the rtl. Also, if we are profiling, we cannot eliminate + the frame pointer (because the return address will get smashed). */ + +void sparc_override_options (); + +#define OVERRIDE_OPTIONS \ + do { \ + if (profile_flag || profile_block_flag || profile_arc_flag) \ + { \ + if (flag_pic) \ + { \ + const char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC";\ + warning ("%s and profiling conflict: disabling %s", \ + pic_string, pic_string); \ + flag_pic = 0; \ + } \ + flag_omit_frame_pointer = 0; \ + } \ + sparc_override_options (); \ + SUBTARGET_OVERRIDE_OPTIONS; \ + } while (0) + +/* This is meant to be redefined in the host dependent files. */ +#define SUBTARGET_OVERRIDE_OPTIONS + +/* These compiler options take an argument. We ignore -target for now. */ + +#define WORD_SWITCH_TAKES_ARG(STR) \ + (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ + || !strcmp (STR, "target") || !strcmp (STR, "assert")) + +/* Print subsidiary information on the compiler version in use. */ + +#define TARGET_VERSION fprintf (stderr, " (sparc)"); + +/* Generate DBX debugging information. */ + +#define DBX_DEBUGGING_INFO + +/* Run-time compilation parameters selecting different hardware subsets. */ + +extern int target_flags; + +/* Nonzero if we should generate code to use the fpu. */ +#define MASK_FPU 1 +#define TARGET_FPU (target_flags & MASK_FPU) + +/* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we + use fast return insns, but lose some generality. */ +#define MASK_EPILOGUE 2 +#define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE) + +/* Nonzero if we should assume that double pointers might be unaligned. + This can happen when linking gcc compiled code with other compilers, + because the ABI only guarantees 4 byte alignment. */ +#define MASK_UNALIGNED_DOUBLES 4 +#define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) + +/* Nonzero means that we should generate code for a v8 sparc. */ +#define MASK_V8 0x8 +#define TARGET_V8 (target_flags & MASK_V8) + +/* Nonzero means that we should generate code for a sparclite. + This enables the sparclite specific instructions, but does not affect + whether FPU instructions are emitted. */ +#define MASK_SPARCLITE 0x10 +#define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) + +/* Nonzero if we're compiling for the sparclet. */ +#define MASK_SPARCLET 0x20 +#define TARGET_SPARCLET (target_flags & MASK_SPARCLET) + +/* Nonzero if we're compiling for v9 sparc. + Note that v9's can run in 32 bit mode so this doesn't necessarily mean + the word size is 64. */ +#define MASK_V9 0x40 +#define TARGET_V9 (target_flags & MASK_V9) + +/* Non-zero to generate code that uses the instructions deprecated in + the v9 architecture. This option only applies to v9 systems. */ +/* ??? This isn't user selectable yet. It's used to enable such insns + on 32 bit v9 systems and for the moment they're permanently disabled + on 64 bit v9 systems. */ +#define MASK_DEPRECATED_V8_INSNS 0x80 +#define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS) + +/* Mask of all CPU selection flags. */ +#define MASK_ISA \ +(MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) + +/* Non-zero means don't pass `-assert pure-text' to the linker. */ +#define MASK_IMPURE_TEXT 0x100 +#define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT) + +/* Nonzero means that we should generate code using a flat register window + model, i.e. no save/restore instructions are generated, which is + compatible with normal sparc code. + The frame pointer is %i7 instead of %fp. */ +#define MASK_FLAT 0x200 +#define TARGET_FLAT (target_flags & MASK_FLAT) + +/* Nonzero means use the registers that the Sparc ABI reserves for + application software. This must be the default to coincide with the + setting in FIXED_REGISTERS. */ +#define MASK_APP_REGS 0x400 +#define TARGET_APP_REGS (target_flags & MASK_APP_REGS) + +/* Option to select how quad word floating point is implemented. + When TARGET_HARD_QUAD is true, we use the hardware quad instructions. + Otherwise, we use the SPARC ABI quad library functions. */ +#define MASK_HARD_QUAD 0x800 +#define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) + +/* Non-zero on little-endian machines. */ +/* ??? Little endian support currently only exists for sparclet-aout and + sparc64-elf configurations. May eventually want to expand the support + to all targets, but for now it's kept local to only those two. */ +#define MASK_LITTLE_ENDIAN 0x1000 +#define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN) + +/* 0x2000, 0x4000 are unused */ + +/* Nonzero if pointers are 64 bits. + At the moment it must follow architecture size flag. */ +#define MASK_PTR64 0x8000 +#define TARGET_PTR64 (target_flags & MASK_PTR64) + +/* Nonzero if generating code to run in a 64 bit environment. + This is intended to only be used by TARGET_ARCH{32,64} as they are the + mechanism used to control compile time or run time selection. */ +#define MASK_64BIT 0x10000 +#define TARGET_64BIT (target_flags & MASK_64BIT) + +/* 0x20000,0x40000 unused */ + +/* Non-zero means use a stack bias of 2047. Stack offsets are obtained by + adding 2047 to %sp. This option is for v9 only and is the default. */ +#define MASK_STACK_BIAS 0x80000 +#define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) + +/* Non-zero means %g0 is a normal register. + We still clobber it as necessary, but we can't rely on it always having + a zero value. + We don't bother to support this in true 64 bit mode. */ +#define MASK_LIVE_G0 0x100000 +#define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0) + +/* Non-zero means the cpu has broken `save' and `restore' insns, only + the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0). + We assume the environment will properly handle or otherwise avoid + trouble associated with an interrupt occurring after the `save' or trap + occurring during it. */ +#define MASK_BROKEN_SAVERESTORE 0x200000 +#define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE) + +/* Non-zero means -m{,no-}fpu was passed on the command line. */ +#define MASK_FPU_SET 0x400000 +#define TARGET_FPU_SET (target_flags & MASK_FPU_SET) + +/* Use the UltraSPARC Visual Instruction Set extensions. */ +#define MASK_VIS 0x1000000 +#define TARGET_VIS (target_flags & MASK_VIS) + +/* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of + the current out and global registers. Linux saves the high bits on + context switches but not signals. */ +#define MASK_V8PLUS 0x2000000 +#define TARGET_V8PLUS (target_flags & MASK_V8PLUS) + +/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. + TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y + to get high 32 bits. False in V8+ or V9 because multiply stores + a 64 bit result in a register. */ + +#define TARGET_HARD_MUL32 \ + ((TARGET_V8 || TARGET_SPARCLITE \ + || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ + && ! TARGET_V8PLUS) + +#define TARGET_HARD_MUL \ + (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ + || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) + + +/* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + +#define TARGET_SWITCHES \ + { {"fpu", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \ + {"no-fpu", -MASK_FPU, "Do not use hardware fp" }, \ + {"no-fpu", MASK_FPU_SET, "Do not use hardware fp" }, \ + {"hard-float", MASK_FPU | MASK_FPU_SET, "Use hardware fp" }, \ + {"soft-float", -MASK_FPU, "Do not use hardware fp" }, \ + {"soft-float", MASK_FPU_SET, "Do not use hardware fp" }, \ + {"epilogue", MASK_EPILOGUE, "Use FUNCTION_EPILOGUE" }, \ + {"no-epilogue", -MASK_EPILOGUE, "Do not use FUNCTION_EPILOGUE" }, \ + {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, "Assume possible double misalignment" },\ + {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, "Assume all doubles are aligned" }, \ + {"impure-text", MASK_IMPURE_TEXT, "Pass -assert pure-text to linker" }, \ + {"no-impure-text", -MASK_IMPURE_TEXT, "Do not pass -assert pure-text to linker" }, \ + {"flat", MASK_FLAT, "Use flat register window model" }, \ + {"no-flat", -MASK_FLAT, "Do not use flat register window model" }, \ + {"app-regs", MASK_APP_REGS, "Use ABI reserved registers" }, \ + {"no-app-regs", -MASK_APP_REGS, "Do not use ABI reserved registers" }, \ + {"hard-quad-float", MASK_HARD_QUAD, "Use hardware quad fp instructions" }, \ + {"soft-quad-float", -MASK_HARD_QUAD, "Do not use hardware quad fp instructions" }, \ + {"v8plus", MASK_V8PLUS, "Compile for v8plus ABI" }, \ + {"no-v8plus", -MASK_V8PLUS, "Do not compile for v8plus ABI" }, \ + {"vis", MASK_VIS, "Utilize Visual Instruction Set" }, \ + {"no-vis", -MASK_VIS, "Do not utilize Visual Instruction Set" }, \ + /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \ + {"cypress", 0, "Optimize for Cypress processors" }, \ + {"sparclite", 0, "Optimize for SparcLite processors" }, \ + {"f930", 0, "Optimize for F930 processors" }, \ + {"f934", 0, "Optimize for F934 processors" }, \ + {"v8", 0, "Use V8 Sparc ISA" }, \ + {"supersparc", 0, "Optimize for SuperSparc processors" }, \ + /* End of deprecated options. */ \ + {"ptr64", MASK_PTR64, "Pointers are 64-bit" }, \ + {"ptr32", -MASK_PTR64, "Pointers are 32-bit" }, \ + {"32", -MASK_64BIT, "Use 32-bit ABI" }, \ + {"64", MASK_64BIT, "Use 64-bit ABI" }, \ + {"stack-bias", MASK_STACK_BIAS, "Use stack bias" }, \ + {"no-stack-bias", -MASK_STACK_BIAS, "Do not use stack bias" }, \ + SUBTARGET_SWITCHES \ + { "", TARGET_DEFAULT, ""}} + +/* MASK_APP_REGS must always be the default because that's what + FIXED_REGISTERS is set to and -ffixed- is processed before + CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ +#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) + +/* This is meant to be redefined in target specific files. */ +#define SUBTARGET_SWITCHES + +/* Processor type. + These must match the values for the cpu attribute in sparc.md. */ +enum processor_type { + PROCESSOR_V7, + PROCESSOR_CYPRESS, + PROCESSOR_V8, + PROCESSOR_SUPERSPARC, + PROCESSOR_SPARCLITE, + PROCESSOR_F930, + PROCESSOR_F934, + PROCESSOR_HYPERSPARC, + PROCESSOR_SPARCLITE86X, + PROCESSOR_SPARCLET, + PROCESSOR_TSC701, + PROCESSOR_V9, + PROCESSOR_ULTRASPARC +}; + +/* This is set from -m{cpu,tune}=xxx. */ +extern enum processor_type sparc_cpu; + +/* Recast the cpu class to be the cpu attribute. + Every file includes us, but not every file includes insn-attr.h. */ +#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) + +/* This macro is similar to `TARGET_SWITCHES' but defines names of + command options that have values. Its definition is an + initializer with a subgrouping for each command option. + + Each subgrouping contains a string constant, that defines the + fixed part of the option name, and the address of a variable. + The variable, type `char *', is set to the variable part of the + given option if the fixed part matches. The actual option name + is made by appending `-m' to the specified name. + + Here is an example which defines `-mshort-data-NUMBER'. If the + given option is `-mshort-data-512', the variable `m88k_short_data' + will be set to the string `"512"'. + + extern char *m88k_short_data; + #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ + +#define TARGET_OPTIONS \ +{ \ + { "cpu=", &sparc_select[1].string, "Use features of and schedule code for given CPU" }, \ + { "tune=", &sparc_select[2].string, "Schedule code for given CPU" }, \ + { "cmodel=", &sparc_cmodel_string, "Use given Sparc code model" }, \ + { "align-loops=", &sparc_align_loops_string, "Loop code aligned to this power of 2" }, \ + { "align-jumps=", &sparc_align_jumps_string, "Jump targets are aligned to this power of 2" }, \ + { "align-functions=", &sparc_align_funcs_string, "Function starts are aligned to this power of 2" }, \ + SUBTARGET_OPTIONS \ +} + +/* This is meant to be redefined in target specific files. */ +#define SUBTARGET_OPTIONS + +/* sparc_select[0] is reserved for the default cpu. */ +struct sparc_cpu_select +{ + const char *string; + const char *name; + int set_tune_p; + int set_arch_p; +}; + +extern struct sparc_cpu_select sparc_select[]; + +/* Variables to record values the user passes. */ +extern const char *sparc_align_loops_string; +extern const char *sparc_align_jumps_string; +extern const char *sparc_align_funcs_string; +/* Parsed values as a power of two. */ +extern int sparc_align_loops; +extern int sparc_align_jumps; +extern int sparc_align_funcs; + +#define DEFAULT_SPARC_ALIGN_FUNCS \ +(sparc_cpu == PROCESSOR_ULTRASPARC ? 5 : 2) + +/* target machine storage layout */ + +/* Define for cross-compilation to a sparc target with no TFmode from a host + with a different float format (e.g. VAX). */ +#define REAL_ARITHMETIC + +/* Define this if most significant bit is lowest numbered + in instructions that operate on numbered bit-fields. */ +#define BITS_BIG_ENDIAN 1 + +/* Define this if most significant byte of a word is the lowest numbered. */ +#define BYTES_BIG_ENDIAN 1 + +/* Define this if most significant word of a multiword number is the lowest + numbered. */ +#define WORDS_BIG_ENDIAN 1 + +/* Define this to set the endianness to use in libgcc2.c, which can + not depend on target_flags. */ +#if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) +#define LIBGCC2_WORDS_BIG_ENDIAN 0 +#else +#define LIBGCC2_WORDS_BIG_ENDIAN 1 +#endif + +/* number of bits in an addressable storage unit */ +#define BITS_PER_UNIT 8 + +/* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 68000, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ +#define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32) +#define MAX_BITS_PER_WORD 64 + +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) +#define MIN_UNITS_PER_WORD 4 + +/* Now define the sizes of the C data types. */ + +#define SHORT_TYPE_SIZE 16 +#define INT_TYPE_SIZE 32 +#define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) +#define LONG_LONG_TYPE_SIZE 64 +#define FLOAT_TYPE_SIZE 32 +#define DOUBLE_TYPE_SIZE 64 + +#if defined (SPARC_BI_ARCH) +#define MAX_LONG_TYPE_SIZE 64 +#endif + +#if 0 +/* ??? This does not work in SunOS 4.x, so it is not enabled here. + Instead, it is enabled in sol2.h, because it does work under Solaris. */ +/* Define for support of TFmode long double and REAL_ARITHMETIC. + Sparc ABI says that long double is 4 words. */ +#define LONG_DOUBLE_TYPE_SIZE 128 +#endif + +/* Width in bits of a pointer. + See also the macro `Pmode' defined below. */ +#define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) + +/* A macro to update MODE and UNSIGNEDP when an object whose type + is TYPE and which has the specified mode and signedness is to be + stored in a register. This macro is only called when TYPE is a + scalar type. */ +#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ +if (TARGET_ARCH64 \ + && GET_MODE_CLASS (MODE) == MODE_INT \ + && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ +{ \ + (MODE) = DImode; \ +} + +/* Define this macro if the promotion described by PROMOTE_MODE + should also be done for outgoing function arguments. */ +/* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op + for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test + for this value. */ +#define PROMOTE_FUNCTION_ARGS + +/* Define this macro if the promotion described by PROMOTE_MODE + should also be done for the return value of functions. + If this macro is defined, FUNCTION_VALUE must perform the same + promotions done by PROMOTE_MODE. */ +/* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op + for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test + for this value. */ +#define PROMOTE_FUNCTION_RETURN + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) + +/* Boundary (in *bits*) on which stack pointer should be aligned. */ +#define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) + +/* ALIGN FRAMES on double word boundaries */ + +#define SPARC_STACK_ALIGN(LOC) \ + (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) + +/* Allocation boundary (in *bits*) for the code of a function. */ +#define FUNCTION_BOUNDARY (1 << (sparc_align_funcs + 3)) + +/* Alignment of field after `int : 0' in a structure. */ +#define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) + +/* Every structure's size must be a multiple of this. */ +#define STRUCTURE_SIZE_BOUNDARY 8 + +/* A bitfield declared as `int' forces `int' alignment for the struct. */ +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* No data type wants to be aligned rounder than this. */ +#define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) + +/* The best alignment to use in cases where we have a choice. */ +#define FASTEST_ALIGNMENT 64 + +/* Make strings word-aligned so strcpy from constants will be faster. */ +#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ + ((TREE_CODE (EXP) == STRING_CST \ + && (ALIGN) < FASTEST_ALIGNMENT) \ + ? FASTEST_ALIGNMENT : (ALIGN)) + +/* Make arrays of chars word-aligned for the same reasons. */ +#define DATA_ALIGNMENT(TYPE, ALIGN) \ + (TREE_CODE (TYPE) == ARRAY_TYPE \ + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ + && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) + +/* Set this nonzero if move instructions will actually fail to work + when given unaligned data. */ +#define STRICT_ALIGNMENT 1 + +/* Things that must be doubleword aligned cannot go in the text section, + because the linker fails to align the text section enough! + Put them in the data section. This macro is only used in this file. */ +#define MAX_TEXT_ALIGN 32 + +/* This forces all variables and constants to the data section when PIC. + This is because the SunOS 4 shared library scheme thinks everything in + text is a function, and patches the address to point to a loader stub. */ +/* This is defined to zero for every system which doesn't use the a.out object + file format. */ +#ifndef SUNOS4_SHARED_LIBRARIES +#define SUNOS4_SHARED_LIBRARIES 0 +#endif + +/* This is defined differently for v9 in a cover file. */ +#define SELECT_SECTION(T,RELOC) \ +{ \ + if (TREE_CODE (T) == VAR_DECL) \ + { \ + if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ + && DECL_INITIAL (T) \ + && (DECL_INITIAL (T) == error_mark_node \ + || TREE_CONSTANT (DECL_INITIAL (T))) \ + && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ + && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ + text_section (); \ + else \ + data_section (); \ + } \ + else if (TREE_CODE (T) == CONSTRUCTOR) \ + { \ + if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \ + data_section (); \ + } \ + else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \ + { \ + if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ + || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \ + || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ + data_section (); \ + else \ + text_section (); \ + } \ +} + +/* Use text section for a constant + unless we need more alignment than that offers. */ +/* This is defined differently for v9 in a cover file. */ +#define SELECT_RTX_SECTION(MODE, X) \ +{ \ + if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ + && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \ + text_section (); \ + else \ + data_section (); \ +} + +/* Standard register usage. */ + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. + + SPARC has 32 integer registers and 32 floating point registers. + 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not + accessible. We still account for them to simplify register computations + (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so + 32+32+32+4 == 100. + Register 100 is used as the integer condition code register. */ + +#define FIRST_PSEUDO_REGISTER 101 + +#define SPARC_FIRST_FP_REG 32 +/* Additional V9 fp regs. */ +#define SPARC_FIRST_V9_FP_REG 64 +#define SPARC_LAST_V9_FP_REG 95 +/* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ +#define SPARC_FIRST_V9_FCC_REG 96 +#define SPARC_LAST_V9_FCC_REG 99 +/* V8 fcc reg. */ +#define SPARC_FCC_REG 96 +/* Integer CC reg. We don't distinguish %icc from %xcc. */ +#define SPARC_ICC_REG 100 + +/* Nonzero if REGNO is an fp reg. */ +#define SPARC_FP_REG_P(REGNO) \ +((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) + +/* Argument passing regs. */ +#define SPARC_OUTGOING_INT_ARG_FIRST 8 +#define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) +#define SPARC_FP_ARG_FIRST 32 + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + + On non-v9 systems: + g1 is free to use as temporary. + g2-g4 are reserved for applications. Gcc normally uses them as + temporaries, but this can be disabled via the -mno-app-regs option. + g5 through g7 are reserved for the operating system. + + On v9 systems: + g1,g5 are free to use as temporaries, and are free to use between calls + if the call is to an external function via the PLT. + g4 is free to use as a temporary in the non-embedded case. + g4 is reserved in the embedded case. + g2-g3 are reserved for applications. Gcc normally uses them as + temporaries, but this can be disabled via the -mno-app-regs option. + g6-g7 are reserved for the operating system (or application in + embedded case). + ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must + currently be a fixed register until this pattern is rewritten. + Register 1 is also used when restoring call-preserved registers in large + stack frames. + + Registers fixed in arch32 and not arch64 (or vice-versa) are marked in + CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. +*/ + +#define FIXED_REGISTERS \ + {1, 0, 0, 0, 0, 0, 1, 1, \ + 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 1, \ + \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + \ + 0, 0, 0, 0, 0} + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ + +#define CALL_USED_REGISTERS \ + {1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 1, 1, \ + \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + \ + 1, 1, 1, 1, 1} + +/* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that + they won't be allocated. */ + +#define CONDITIONAL_REGISTER_USAGE \ +do \ + { \ + if (flag_pic) \ + { \ + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + } \ + if (TARGET_ARCH32) \ + { \ + fixed_regs[5] = 1; \ + } \ + if (TARGET_LIVE_G0) \ + fixed_regs[0] = 0; \ + if (! TARGET_V9) \ + { \ + int regno; \ + for (regno = SPARC_FIRST_V9_FP_REG; \ + regno <= SPARC_LAST_V9_FP_REG; \ + regno++) \ + fixed_regs[regno] = 1; \ + /* %fcc0 is used by v8 and v9. */ \ + for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ + regno <= SPARC_LAST_V9_FCC_REG; \ + regno++) \ + fixed_regs[regno] = 1; \ + } \ + if (! TARGET_FPU) \ + { \ + int regno; \ + for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ + fixed_regs[regno] = 1; \ + } \ + /* Don't unfix g2-g4 if they were fixed with -ffixed-. */ \ + fixed_regs[2] |= ! TARGET_APP_REGS; \ + fixed_regs[3] |= ! TARGET_APP_REGS; \ + fixed_regs[4] |= ! TARGET_APP_REGS || TARGET_CM_EMBMEDANY; \ + if (TARGET_FLAT) \ + { \ + /* Let the compiler believe the frame pointer is still \ + %fp, but output it as %i7. */ \ + fixed_regs[31] = 1; \ + reg_names[FRAME_POINTER_REGNUM] = "%i7"; \ + /* ??? This is a hack to disable leaf functions. */ \ + global_regs[7] = 1; \ + } \ + if (profile_block_flag) \ + { \ + /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \ + uses them. */ \ + fixed_regs[1] = 1; \ + fixed_regs[2] = 1; \ + } \ + } \ +while (0) + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + + On SPARC, ordinary registers hold 32 bits worth; + this means both integer and floating point registers. + On v9, integer regs hold 64 bits worth; floating point regs hold + 32 bits worth (this includes the new fp regs as even the odd ones are + included in the hard register count). */ + +#define HARD_REGNO_NREGS(REGNO, MODE) \ + (TARGET_ARCH64 \ + ? ((REGNO) < 32 \ + ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ + : (GET_MODE_SIZE (MODE) + 3) / 4) \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* A subreg in 64 bit mode will have the wrong offset for a floating point + register. The least significant part is at offset 1, compared to 0 for + integer registers. This only applies when FMODE is a larger mode. + We also need to handle a special case of TF-->DF conversions. */ +#define ALTER_HARD_SUBREG(TMODE, WORD, FMODE, REGNO) \ + (TARGET_ARCH64 \ + && (REGNO) >= SPARC_FIRST_FP_REG \ + && (REGNO) <= SPARC_LAST_V9_FP_REG \ + && (TMODE) == SImode \ + && !((FMODE) == QImode || (FMODE) == HImode) \ + ? ((REGNO) + 1) \ + : ((TMODE) == DFmode && (FMODE) == TFmode) \ + ? ((REGNO) + ((WORD) * 2)) \ + : ((REGNO) + (WORD))) + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + See sparc.c for how we initialize this. */ +extern int *hard_regno_mode_classes; +extern int sparc_mode_class[]; +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. + + For V9: SFmode can't be combined with other float modes, because they can't + be allocated to the %d registers. Also, DFmode won't fit in odd %f + registers, but SFmode will. */ +#define MODES_TIEABLE_P(MODE1, MODE2) \ + ((MODE1) == (MODE2) \ + || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ + && (! TARGET_V9 \ + || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ + || (MODE1 != SFmode && MODE2 != SFmode))))) + +/* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + +/* SPARC pc isn't overloaded on a register that the compiler knows about. */ +/* #define PC_REGNUM */ + +/* Register to use for pushing function arguments. */ +#define STACK_POINTER_REGNUM 14 + +/* Actual top-of-stack address is 92/176 greater than the contents of the + stack pointer register for !v9/v9. That is: + - !v9: 64 bytes for the in and local registers, 4 bytes for structure return + address, and 6*4 bytes for the 6 register parameters. + - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer + parameter regs. */ +#define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) + +/* The stack bias (amount by which the hardware register is offset by). */ +#define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) + +/* Is stack biased? */ +#define STACK_BIAS SPARC_STACK_BIAS + +/* Base register for access to local variables of the function. */ +#define FRAME_POINTER_REGNUM 30 + +#if 0 +/* Register that is used for the return address for the flat model. */ +#define RETURN_ADDR_REGNUM 15 +#endif + +/* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. + Used in flow.c, global.c, and reload1.c. + + Being a non-leaf function does not mean a frame pointer is needed in the + flat window model. However, the debugger won't be able to backtrace through + us with out it. */ +#define FRAME_POINTER_REQUIRED \ + (TARGET_FLAT ? (current_function_calls_alloca || current_function_varargs \ + || !leaf_function_p ()) \ + : ! (leaf_function_p () && only_leaf_regs_used ())) + +/* C statement to store the difference between the frame pointer + and the stack pointer values immediately after the function prologue. + + Note, we always pretend that this is a leaf function because if + it's not, there's no point in trying to eliminate the + frame pointer. If it is a leaf function, we guessed right! */ +#define INITIAL_FRAME_POINTER_OFFSET(VAR) \ + ((VAR) = (TARGET_FLAT ? sparc_flat_compute_frame_size (get_frame_size ()) \ + : compute_frame_size (get_frame_size (), 1))) + +/* Base register for access to arguments of the function. */ +#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM + +/* Register in which static-chain is passed to a function. This must + not be a register used by the prologue. */ +#define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) + +/* Register which holds offset table for position-independent + data references. */ + +#define PIC_OFFSET_TABLE_REGNUM 23 + +#define FINALIZE_PIC finalize_pic () + +/* Pick a default value we can notice from override_options: + !v9: Default is on. + v9: Default is off. */ + +#define DEFAULT_PCC_STRUCT_RETURN -1 + +/* Sparc ABI says that quad-precision floats and all structures are returned + in memory. + For v9: unions <= 32 bytes in size are returned in int regs, + structures up to 32 bytes are returned in int and fp regs. */ + +#define RETURN_IN_MEMORY(TYPE) \ +(TARGET_ARCH32 \ + ? (TYPE_MODE (TYPE) == BLKmode \ + || TYPE_MODE (TYPE) == TFmode \ + || TYPE_MODE (TYPE) == TCmode) \ + : (TYPE_MODE (TYPE) == BLKmode \ + && int_size_in_bytes (TYPE) > 32)) + +/* Functions which return large structures get the address + to place the wanted value at offset 64 from the frame. + Must reserve 64 bytes for the in and local registers. + v9: Functions which return large structures get the address to place the + wanted value from an invisible first argument. */ +/* Used only in other #defines in this file. */ +#define STRUCT_VALUE_OFFSET 64 + +#define STRUCT_VALUE \ + (TARGET_ARCH64 \ + ? 0 \ + : gen_rtx_MEM (Pmode, \ + gen_rtx_PLUS (Pmode, stack_pointer_rtx, \ + GEN_INT (STRUCT_VALUE_OFFSET)))) +#define STRUCT_VALUE_INCOMING \ + (TARGET_ARCH64 \ + ? 0 \ + : gen_rtx_MEM (Pmode, \ + gen_rtx_PLUS (Pmode, frame_pointer_rtx, \ + GEN_INT (STRUCT_VALUE_OFFSET)))) + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. */ + +/* The SPARC has various kinds of registers: general, floating point, + and condition codes [well, it has others as well, but none that we + care directly about]. + + For v9 we must distinguish between the upper and lower floating point + registers because the upper ones can't hold SFmode values. + HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) + satisfying a group need for a class will also satisfy a single need for + that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp + regs. + + It is important that one class contains all the general and all the standard + fp regs. Otherwise find_reg() won't properly allocate int regs for moves, + because reg_class_record() will bias the selection in favor of fp regs, + because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, + because FP_REGS > GENERAL_REGS. + + It is also important that one class contain all the general and all the + fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS + but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause + allocate_reload_reg() to bypass it causing an abort because the compiler + thinks it doesn't have a spill reg when in fact it does. + + v9 also has 4 floating point condition code registers. Since we don't + have a class that is the union of FPCC_REGS with either of the others, + it is important that it appear first. Otherwise the compiler will die + trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its + constraints. + + It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine + may try to use it to hold an SImode value. See register_operand. + ??? Should %fcc[0123] be handled similarly? +*/ + +enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, + EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, + ALL_REGS, LIM_REG_CLASSES }; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES \ + { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ + "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ + "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS \ + {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {0xffff, 0, 0, 0}, \ + {-1, 0, 0, 0}, {0, -1, 0, 0}, {0, -1, -1, 0}, \ + {-1, -1, 0, 0}, {-1, -1, -1, 0}, {-1, -1, -1, 0x1f}} + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +extern enum reg_class sparc_regno_reg_class[]; + +#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] + +/* This is the order in which to allocate registers normally. + + We put %f0/%f1 last among the float registers, so as to make it more + likely that a pseudo-register which dies in the float return register + will get allocated to the float return register, thus saving a move + instruction at the end of the function. */ + +#define REG_ALLOC_ORDER \ +{ 8, 9, 10, 11, 12, 13, 2, 3, \ + 15, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 29, 31, \ + 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \ + 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ + 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ + 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ + 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ + 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ + 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ + 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ + 32, 33, /* %f0,%f1 */ \ + 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \ + 1, 4, 5, 6, 7, 0, 14, 30} + +/* This is the order in which to allocate registers for + leaf functions. If all registers can fit in the "i" registers, + then we have the possibility of having a leaf function. */ + +#define REG_LEAF_ALLOC_ORDER \ +{ 2, 3, 24, 25, 26, 27, 28, 29, \ + 15, 8, 9, 10, 11, 12, 13, \ + 16, 17, 18, 19, 20, 21, 22, 23, \ + 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, \ + 64, 65, 66, 67, 68, 69, 70, 71, \ + 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, \ + 88, 89, 90, 91, 92, 93, 94, 95, \ + 32, 33, \ + 96, 97, 98, 99, 100, \ + 1, 4, 5, 6, 7, 0, 14, 30, 31} + +#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () + +/* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when + -mflat is used. Function only_leaf_regs_used will return 0 if a global + register is used and is not permitted in a leaf function. We make %g7 + a global reg if -mflat and voila. Since %g7 is a system register and is + fixed it won't be used by gcc anyway. */ + +#define LEAF_REGISTERS \ +{ 1, 1, 1, 1, 1, 1, 1, 0, \ + 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1, 1, 1, 0, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1} + +extern char leaf_reg_remap[]; +#define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) + +/* The class value for index registers, and the one for base regs. */ +#define INDEX_REG_CLASS GENERAL_REGS +#define BASE_REG_CLASS GENERAL_REGS + +/* Local macro to handle the two v9 classes of FP regs. */ +#define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) + +/* Get reg_class from a letter such as appears in the machine description. + In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the + .md file for v8 and v9. + 'd' and 'b' are used for single and double precision VIS operations, + if TARGET_VIS. + 'h' is used for V8+ 64 bit global and out registers. */ + +#define REG_CLASS_FROM_LETTER(C) \ +(TARGET_V9 \ + ? ((C) == 'f' ? FP_REGS \ + : (C) == 'e' ? EXTRA_FP_REGS \ + : (C) == 'c' ? FPCC_REGS \ + : ((C) == 'd' && TARGET_VIS) ? FP_REGS\ + : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\ + : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\ + : NO_REGS) \ + : ((C) == 'f' ? FP_REGS \ + : (C) == 'e' ? FP_REGS \ + : (C) == 'c' ? FPCC_REGS \ + : NO_REGS)) + +/* The letters I, J, K, L and M in a register constraint string + can be used to stand for particular ranges of immediate operands. + This macro defines what the ranges are. + C is the letter, and VALUE is a constant value. + Return 1 if VALUE is in the range specified by C. + + `I' is used for the range of constants an insn can actually contain. + `J' is used for the range which is just zero (since that is R0). + `K' is used for constants which can be loaded with a single sethi insn. + `L' is used for the range of constants supported by the movcc insns. + `M' is used for the range of constants supported by the movrcc insns. */ + +#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) +#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) +#define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) +/* 10 and 11 bit immediates are only used for a few specific insns. + SMALL_INT is used throughout the port so we continue to use it. */ +#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) +/* 13 bit immediate, considering only the low 32 bits */ +#define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff)) +#define SPARC_SETHI_P(X) \ +(((unsigned HOST_WIDE_INT) (X) & ~(unsigned HOST_WIDE_INT) 0xfffffc00) == 0) + +#define CONST_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \ + : (C) == 'J' ? (VALUE) == 0 \ + : (C) == 'K' ? SPARC_SETHI_P (VALUE) \ + : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ + : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ + : 0) + +/* Similar, but for floating constants, and defining letters G and H. + Here VALUE is the CONST_DOUBLE rtx itself. */ + +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'G' ? fp_zero_operand (VALUE) \ + : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ + : 0) + +/* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. */ +/* - We can't load constants into FP registers. We can't load any FP + constant if an 'E' constraint fails to match it. + - Try and reload integer constants (symbolic or otherwise) back into + registers directly, rather than having them dumped to memory. */ + +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + (CONSTANT_P (X) \ + ? ((FP_REG_CLASS_P (CLASS) \ + || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ + || HOST_BITS_PER_INT != BITS_PER_WORD))) \ + ? NO_REGS \ + : (!FP_REG_CLASS_P (CLASS) \ + && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ + ? GENERAL_REGS \ + : (CLASS)) \ + : (CLASS)) + +/* Return the register class of a scratch register needed to load IN into + a register of class CLASS in MODE. + + We need a temporary when loading/storing a HImode/QImode value + between memory and the FPU registers. This can happen when combine puts + a paradoxical subreg in a float/fix conversion insn. */ + +#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ + ((FP_REG_CLASS_P (CLASS) \ + && ((MODE) == HImode || (MODE) == QImode) \ + && (GET_CODE (IN) == MEM \ + || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ + && true_regnum (IN) == -1))) \ + ? GENERAL_REGS \ + : (((TARGET_CM_MEDANY \ + && symbolic_operand ((IN), (MODE))) \ + || (TARGET_CM_EMBMEDANY \ + && text_segment_operand ((IN), (MODE)))) \ + && !flag_pic) \ + ? GENERAL_REGS \ + : NO_REGS) + +#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ + ((FP_REG_CLASS_P (CLASS) \ + && ((MODE) == HImode || (MODE) == QImode) \ + && (GET_CODE (IN) == MEM \ + || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ + && true_regnum (IN) == -1))) \ + ? GENERAL_REGS \ + : (((TARGET_CM_MEDANY \ + && symbolic_operand ((IN), (MODE))) \ + || (TARGET_CM_EMBMEDANY \ + && text_segment_operand ((IN), (MODE)))) \ + && !flag_pic) \ + ? GENERAL_REGS \ + : NO_REGS) + +/* On SPARC it is not possible to directly move data between + GENERAL_REGS and FP_REGS. */ +#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ + (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) + +/* Return the stack location to use for secondary memory needed reloads. + We want to use the reserved location just below the frame pointer. + However, we must ensure that there is a frame, so use assign_stack_local + if the frame size is zero. */ +#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ + (get_frame_size () == 0 \ + ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ + : gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, frame_pointer_rtx, \ + GEN_INT (STARTING_FRAME_OFFSET)))) + +/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 + because the movsi and movsf patterns don't handle r/f moves. + For v8 we copy the default definition. */ +#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ + (TARGET_ARCH64 \ + ? (GET_MODE_BITSIZE (MODE) < 32 \ + ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ + : MODE) \ + : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ + ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ + : MODE)) + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ +/* On SPARC, this is the size of MODE in words. */ +#define CLASS_MAX_NREGS(CLASS, MODE) \ + (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ + : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +/* Stack layout; function entry, exit and calling. */ + +/* Define the number of register that can hold parameters. + This macro is only used in other macro definitions below and in sparc.c. + MODE is the mode of the argument. + !v9: All args are passed in %o0-%o5. + v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values. + See the description in sparc.c. */ +#define NPARM_REGS(MODE) \ +(TARGET_ARCH64 \ + ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \ + : 6) + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ +#define FRAME_GROWS_DOWNWARD + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +/* This allows space for one TFmode floating point value. */ +#define STARTING_FRAME_OFFSET \ + (TARGET_ARCH64 ? (SPARC_STACK_BIAS - 16) \ + : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On SPARC, don't define this because there are no push insns. */ +/* #define PUSH_ROUNDING(BYTES) */ + +/* Offset of first parameter from the argument pointer register value. + !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg + even if this function isn't going to use it. + v9: This is 128 for the ins and locals. */ +#define FIRST_PARM_OFFSET(FNDECL) \ + (TARGET_ARCH64 ? (SPARC_STACK_BIAS + 16 * UNITS_PER_WORD) \ + : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)) + +/* Offset from the argument pointer register value to the CFA. */ + +#define ARG_POINTER_CFA_OFFSET SPARC_STACK_BIAS + +/* When a parameter is passed in a register, stack space is still + allocated for it. + !v9: All 6 possible integer registers have backing store allocated. + v9: Only space for the arguments passed is allocated. */ +/* ??? Ideally, we'd use zero here (as the minimum), but zero has special + meaning to the backend. Further, we need to be able to detect if a + varargs/unprototyped function is called, as they may want to spill more + registers than we've provided space. Ugly, ugly. So for now we retain + all 6 slots even for v9. */ +#define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) + +/* Keep the stack pointer constant throughout the function. + This is both an optimization and a necessity: longjmp + doesn't behave itself when the stack pointer moves within + the function! */ +#define ACCUMULATE_OUTGOING_ARGS + +/* Value is the number of bytes of arguments automatically + popped when returning from a subroutine call. + FUNDECL is the declaration node of the function (as a tree), + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. + SIZE is the number of bytes of arguments passed on the stack. */ + +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 + +/* Some subroutine macros specific to this machine. + When !TARGET_FPU, put float return values in the general registers, + since we don't have any fp registers. */ +#define BASE_RETURN_VALUE_REG(MODE) \ + (TARGET_ARCH64 \ + ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ + : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) + +#define BASE_OUTGOING_VALUE_REG(MODE) \ + (TARGET_ARCH64 \ + ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ + : TARGET_FLAT ? 8 : 24) \ + : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ + : (TARGET_FLAT ? 8 : 24))) + +#define BASE_PASSING_ARG_REG(MODE) \ + (TARGET_ARCH64 \ + ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ + : 8) + +/* ??? FIXME -- seems wrong for v9 structure passing... */ +#define BASE_INCOMING_ARG_REG(MODE) \ + (TARGET_ARCH64 \ + ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ + : TARGET_FLAT ? 8 : 24) \ + : (TARGET_FLAT ? 8 : 24)) + +/* Define this macro if the target machine has "register windows". This + C expression returns the register number as seen by the called function + corresponding to register number OUT as seen by the calling function. + Return OUT if register number OUT is not an outbound register. */ + +#define INCOMING_REGNO(OUT) \ + ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) + +/* Define this macro if the target machine has "register windows". This + C expression returns the register number as seen by the calling function + corresponding to register number IN as seen by the called function. + Return IN if register number IN is not an inbound register. */ + +#define OUTGOING_REGNO(IN) \ + ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ + +/* On SPARC the value is found in the first "output" register. */ + +extern struct rtx_def *function_value (); +#define FUNCTION_VALUE(VALTYPE, FUNC) \ + function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) + +/* But the called function leaves it in the first "input" register. */ + +#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ + function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) + +/* Define how to find the value returned by a library function + assuming the value has mode MODE. */ + +#define LIBCALL_VALUE(MODE) \ + function_value (NULL_TREE, (MODE), 1) + +/* 1 if N is a possible register number for a function value + as seen by the caller. + On SPARC, the first "output" reg is used for integer values, + and the first floating point register is used for floating point values. */ + +#define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) + +/* Define the size of space to allocate for the return value of an + untyped_call. */ + +#define APPLY_RESULT_SIZE 16 + +/* 1 if N is a possible register number for function argument passing. + On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ + +#define FUNCTION_ARG_REGNO_P(N) \ +(TARGET_ARCH64 \ + ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ + : ((N) >= 8 && (N) <= 13)) + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + + On SPARC (!v9), this is a single integer, which is a number of words + of arguments scanned so far (including the invisible argument, + if any, which holds the structure-value-address). + Thus 7 or more means all following args should go on the stack. + + For v9, we also need to know whether a prototype is present. */ + +struct sparc_args { + int words; /* number of words passed so far */ + int prototype_p; /* non-zero if a prototype is present */ + int libcall_p; /* non-zero if a library call */ +}; +#define CUMULATIVE_ARGS struct sparc_args + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. */ + +extern void init_cumulative_args (); +#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ +init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (INDIRECT)); + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + TYPE is null for libcalls where that information may not be available. */ + +extern void function_arg_advance (); +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ +function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) + +/* Determine where to put an argument to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + +extern struct rtx_def *function_arg (); +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ +function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) + +/* Define where a function finds its arguments. + This is different from FUNCTION_ARG because of register windows. */ + +#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ +function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. */ + +extern int function_arg_partial_nregs (); +#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ +function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED)) + +/* A C expression that indicates when an argument must be passed by reference. + If nonzero for an argument, a copy of that argument is made in memory and a + pointer to the argument is passed instead of the argument itself. + The pointer is passed in whatever way is appropriate for passing a pointer + to that type. */ + +extern int function_arg_pass_by_reference (); +#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ +function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED)) + +/* If defined, a C expression which determines whether, and in which direction, + to pad out an argument with extra space. The value should be of type + `enum direction': either `upward' to pad above the argument, + `downward' to pad below, or `none' to inhibit padding. */ + +#define FUNCTION_ARG_PADDING(MODE, TYPE) \ +function_arg_padding ((MODE), (TYPE)) + +/* If defined, a C expression that gives the alignment boundary, in bits, + of an argument with the specified mode and type. If it is not defined, + PARM_BOUNDARY is used for all arguments. + For sparc64, objects requiring 16 byte alignment are passed that way. */ + +#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ +((TARGET_ARCH64 \ + && (GET_MODE_ALIGNMENT (MODE) == 128 \ + || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ + ? 128 : PARM_BOUNDARY) + +/* Define the information needed to generate branch and scc insns. This is + stored from the compare operation. Note that we can't use "rtx" here + since it hasn't been defined! */ + +extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; + +/* Define the function that build the compare insn for scc and bcc. */ + +extern struct rtx_def *gen_compare_reg (); + +/* This function handles all v9 scc insns */ + +extern int gen_v9_scc (); + +/* Generate the special assembly code needed to tell the assembler whatever + it might need to know about the return value of a function. + + For Sparc assemblers, we need to output a .proc pseudo-op which conveys + information to the assembler relating to peephole optimization (done in + the assembler). */ + +#define ASM_DECLARE_RESULT(FILE, RESULT) \ + fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) + +/* Output the label for a function definition. */ + +#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ +do { \ + ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ + ASM_OUTPUT_LABEL (FILE, NAME); \ +} while (0) + +/* This macro generates the assembly code for function entry. + FILE is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. */ + +/* On SPARC, move-double insns between fpu and cpu need an 8-byte block + of memory. If any fpu reg is used in the function, we allocate + such a block here, at the bottom of the frame, just in case it's needed. + + If this function is a leaf procedure, then we may choose not + to do a "save" insn. The decision about whether or not + to do this is made in regclass.c. */ + +#define FUNCTION_PROLOGUE(FILE, SIZE) \ + (TARGET_FLAT ? sparc_flat_output_function_prologue (FILE, (int)SIZE) \ + : output_function_prologue (FILE, (int)SIZE, \ + current_function_uses_only_leaf_regs)) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) \ + sparc_function_profiler(FILE, LABELNO) + +/* Set the name of the mcount function for the system. */ + +#define MCOUNT_FUNCTION "*mcount" + +/* The following macro shall output assembler code to FILE + to initialize basic-block profiling. */ + +#define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \ + sparc_function_block_profiler(FILE, BLOCK_OR_LABEL) + +/* The following macro shall output assembler code to FILE + to increment a counter associated with basic block number BLOCKNO. */ + +#define BLOCK_PROFILER(FILE, BLOCKNO) \ + sparc_block_profiler (FILE, BLOCKNO) + +/* The following macro shall output assembler code to FILE + to indicate a return from function during basic-block profiling. */ + +#define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \ + sparc_function_block_profiler_exit(FILE) + +/* The function `__bb_trace_func' is called in every basic block + and is not allowed to change the machine state. Saving (restoring) + the state can either be done in the BLOCK_PROFILER macro, + before calling function (rsp. after returning from function) + `__bb_trace_func', or it can be done inside the function by + defining the macros: + + MACHINE_STATE_SAVE(ID) + MACHINE_STATE_RESTORE(ID) + + In the latter case care must be taken, that the prologue code + of function `__bb_trace_func' does not already change the + state prior to saving it with MACHINE_STATE_SAVE. + + The parameter `ID' is a string identifying a unique macro use. + + On sparc it is sufficient to save the psw register to memory. + Unfortunately the psw register can be read in supervisor mode only, + so we read only the condition codes by using branch instructions + and hope that this is enough. */ + +#define MACHINE_STATE_SAVE(ID) \ + int ms_flags, ms_saveret; \ + asm volatile( \ + "mov %%g0,%0\n\ + be,a LFLGNZ"ID"\n\ + or %0,4,%0\n\ +LFLGNZ"ID":\n\ + bcs,a LFLGNC"ID"\n\ + or %0,1,%0\n\ +LFLGNC"ID":\n\ + bvs,a LFLGNV"ID"\n\ + or %0,2,%0\n\ +LFLGNV"ID":\n\ + bneg,a LFLGNN"ID"\n\ + or %0,8,%0\n\ +LFLGNN"ID":\n\ + mov %%g2,%1" \ + : "=r"(ms_flags), "=r"(ms_saveret)); + +/* On sparc MACHINE_STATE_RESTORE restores the psw register from memory. + The psw register can be written in supervisor mode only, + which is true even for simple condition codes. + We use some combination of instructions to produce the + proper condition codes, but some flag combinations can not + be generated in this way. If this happens an unimplemented + instruction will be executed to abort the program. */ + +#define MACHINE_STATE_RESTORE(ID) \ +{ extern char flgtab[] __asm__("LFLGTAB"ID); \ + int scratch; \ + asm volatile ( \ + "jmpl %2+%1,%%g0\n\ + ! Do part of VC in the delay slot here, as it needs 3 insns.\n\ + addcc 2,%3,%%g0\n\ +LFLGTAB" ID ":\n\ + ! 0\n\ + ba LFLGRET"ID"\n\ + orcc 1,%%g0,%%g0\n\ + ! C\n\ + ba LFLGRET"ID"\n\ + addcc 2,%3,%%g0\n\ + ! V\n\ + unimp\n\ + nop\n\ + ! VC\n\ + ba LFLGRET"ID"\n\ + addxcc %4,%4,%0\n\ + ! Z\n\ + ba LFLGRET"ID"\n\ + subcc %%g0,%%g0,%%g0\n\ + ! ZC\n\ + ba LFLGRET"ID"\n\ + addcc 1,%3,%0\n\ + ! ZVC\n\ + ba LFLGRET"ID"\n\ + addcc %4,%4,%0\n\ + ! N\n\ + ba LFLGRET"ID"\n\ + orcc %%g0,-1,%%g0\n\ + ! NC\n\ + ba LFLGRET"ID"\n\ + addcc %%g0,%3,%%g0\n\ + ! NV\n\ + unimp\n\ + nop\n\ + ! NVC\n\ + unimp\n\ + nop\n\ + ! NZ\n\ + unimp\n\ + nop\n\ + ! NZC\n\ + unimp\n\ + nop\n\ + ! NZV\n\ + unimp\n\ + nop\n\ + ! NZVC\n\ + unimp\n\ + nop\n\ +LFLGRET"ID":\n\ + mov %5,%%g2" \ + : "=r"(scratch) \ + : "r"(ms_flags*8), "r"(flgtab), "r"(-1), \ + "r"(0x80000000), "r"(ms_saveret) \ + : "cc", "%g2"); } + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ + +extern int current_function_calls_alloca; +extern int current_function_outgoing_args_size; + +#define EXIT_IGNORE_STACK \ + (get_frame_size () != 0 \ + || current_function_calls_alloca || current_function_outgoing_args_size) + +/* This macro generates the assembly code for function exit, + on machines that need it. If FUNCTION_EPILOGUE is not defined + then individual return instructions are generated for each + return statement. Args are same as for FUNCTION_PROLOGUE. + + The function epilogue should not depend on the current stack pointer! + It should use the frame pointer only. This is mandatory because + of alloca; we also take advantage of it to omit stack adjustments + before returning. */ + +/* This declaration is needed due to traditional/ANSI + incompatibilities which cannot be #ifdefed away + because they occur inside of macros. Sigh. */ +extern union tree_node *current_function_decl; + +#define FUNCTION_EPILOGUE(FILE, SIZE) \ + (TARGET_FLAT ? sparc_flat_output_function_epilogue (FILE, (int)SIZE) \ + : output_function_epilogue (FILE, (int)SIZE, \ + current_function_uses_only_leaf_regs)) + +#define DELAY_SLOTS_FOR_EPILOGUE \ + (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1) +#define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ + (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ + : eligible_for_epilogue_delay (trial, slots_filled)) + +/* Define registers used by the epilogue and return instruction. */ +#define EPILOGUE_USES(REGNO) \ + (!TARGET_FLAT && REGNO == 31) + +/* Length in units of the trampoline for entering a nested function. */ + +#define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) + +#define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ + +/* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. */ + +void sparc_initialize_trampoline (); +void sparc64_initialize_trampoline (); +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ + if (TARGET_ARCH64) \ + sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ + else \ + sparc_initialize_trampoline (TRAMP, FNADDR, CXT) + +/* Generate necessary RTL for __builtin_saveregs(). + ARGLIST is the argument list; see expr.c. */ + +extern struct rtx_def *sparc_builtin_saveregs (); +#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST) + +/* Define this macro if the location where a function argument is passed + depends on whether or not it is a named argument. + + This macro controls how the NAMED argument to FUNCTION_ARG + is set for varargs and stdarg functions. With this macro defined, + the NAMED argument is always true for named arguments, and false for + unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS + is defined, then all arguments are treated as named. Otherwise, all named + arguments except the last are treated as named. + For the v9 we want NAMED to mean what it says it means. */ + +#define STRICT_ARGUMENT_NAMING TARGET_V9 + +/* Generate RTL to flush the register windows so as to make arbitrary frames + available. */ +#define SETUP_FRAME_ADDRESSES() \ + emit_insn (gen_flush_register_windows ()) + +/* Given an rtx for the address of a frame, + return an rtx for the address of the word in the frame + that holds the dynamic chain--the previous frame's address. + ??? -mflat support? */ +#define DYNAMIC_CHAIN_ADDRESS(frame) \ + gen_rtx_PLUS (Pmode, frame, GEN_INT (14 * UNITS_PER_WORD)) + +/* The return address isn't on the stack, it is in a register, so we can't + access it from the current frame pointer. We can access it from the + previous frame pointer though by reading a value from the register window + save area. */ +#define RETURN_ADDR_IN_PREVIOUS_FRAME + +/* This is the offset of the return address to the true next instruction to be + executed for the current function. */ +#define RETURN_ADDR_OFFSET \ + (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct)) + +/* The current return address is in %i7. The return address of anything + farther back is in the register window save area at [%fp+60]. */ +/* ??? This ignores the fact that the actual return address is +8 for normal + returns, and +12 for structure returns. */ +#define RETURN_ADDR_RTX(count, frame) \ + ((count == -1) \ + ? gen_rtx_REG (Pmode, 31) \ + : gen_rtx_MEM (Pmode, \ + memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD)))) + +/* Before the prologue, the return address is %o7 + 8. OK, sometimes it's + +12, but always using +8 is close enough for frame unwind purposes. + Actually, just using %o7 is close enough for unwinding, but %o7+8 + is something you can return to. */ +#define INCOMING_RETURN_ADDR_RTX \ + gen_rtx_PLUS (word_mode, gen_rtx_REG (word_mode, 15), GEN_INT (8)) + +/* The offset from the incoming value of %sp to the top of the stack frame + for the current function. On sparc64, we have to account for the stack + bias if present. */ +#define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS + +#define DOESNT_NEED_UNWINDER (! TARGET_FLAT) + +/* Addressing modes, and classification of registers for them. */ + +/* #define HAVE_POST_INCREMENT 0 */ +/* #define HAVE_POST_DECREMENT 0 */ + +/* #define HAVE_PRE_DECREMENT 0 */ +/* #define HAVE_PRE_INCREMENT 0 */ + +/* Macros to check register numbers against specific register classes. */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + +#define REGNO_OK_FOR_INDEX_P(REGNO) \ +((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32) +#define REGNO_OK_FOR_BASE_P(REGNO) \ +((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32) +#define REGNO_OK_FOR_FP_P(REGNO) \ + (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ + || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) +#define REGNO_OK_FOR_CCFP_P(REGNO) \ + (TARGET_V9 \ + && (((unsigned) (REGNO) - 96 < (unsigned)4) \ + || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) + +/* Now macros that check whether X is a register and also, + strictly, whether it is in a specified class. + + These macros are specific to the SPARC, and may be used only + in code for printing assembler insns and in conditions for + define_optimization. */ + +/* 1 if X is an fp register. */ + +#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) + +/* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ +#define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) + +/* Maximum number of registers that can appear in a valid memory address. */ + +#define MAX_REGS_PER_ADDRESS 2 + +/* Recognize any constant value that is a valid address. + When PIC, we do not accept an address that would require a scratch reg + to load into a register. */ + +#define CONSTANT_ADDRESS_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ + || (GET_CODE (X) == CONST \ + && ! (flag_pic && pic_address_needs_scratch (X)))) + +/* Define this, so that when PIC, reload won't try to reload invalid + addresses which require two reload registers. */ + +#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) + +/* Nonzero if the constant value X is a legitimate general operand. + Anything can be made to work except floating point constants. + If TARGET_VIS, 0.0 can be made to work as well. */ + +#define LEGITIMATE_CONSTANT_P(X) \ + (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || \ + (TARGET_VIS && (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode) && \ + fp_zero_operand (X))) + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + +/* Optional extra constraints for this machine. + + 'T' handles memory addresses where the alignment is known to + be at least 8 bytes. + + `U' handles all pseudo registers or a hard even numbered + integer register, needed for ldd/std instructions. */ + +#ifndef REG_OK_STRICT + +/* Nonzero if X is a hard reg that can be used as an index + or if it is a pseudo reg. */ +#define REG_OK_FOR_INDEX_P(X) \ + (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32)) +/* Nonzero if X is a hard reg that can be used as a base reg + or if it is a pseudo reg. */ +#define REG_OK_FOR_BASE_P(X) \ + (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32)) + +/* 'T', 'U' are for aligned memory loads which aren't needed for v9. */ + +#define EXTRA_CONSTRAINT(OP, C) \ + ((! TARGET_ARCH64 && (C) == 'T') \ + ? (mem_min_alignment (OP, 8)) \ + : ((! TARGET_ARCH64 && (C) == 'U') \ + ? (register_ok_for_ldd (OP)) \ + : 0)) + +#else + +/* Nonzero if X is a hard reg that can be used as an index. */ +#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) + +#define EXTRA_CONSTRAINT(OP, C) \ + ((! TARGET_ARCH64 && (C) == 'T') \ + ? mem_min_alignment (OP, 8) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \ + : ((! TARGET_ARCH64 && (C) == 'U') \ + ? (GET_CODE (OP) == REG \ + && (REGNO (OP) < FIRST_PSEUDO_REGISTER \ + || reg_renumber[REGNO (OP)] >= 0) \ + && register_ok_for_ldd (OP)) \ + : 0)) +#endif + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT + ordinarily. This changes a bit when generating PIC. + + If you change this, execute "rm explow.o recog.o reload.o". */ + +#define RTX_OK_FOR_BASE_P(X) \ + ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ + || (GET_CODE (X) == SUBREG \ + && GET_CODE (SUBREG_REG (X)) == REG \ + && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) + +#define RTX_OK_FOR_INDEX_P(X) \ + ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ + || (GET_CODE (X) == SUBREG \ + && GET_CODE (SUBREG_REG (X)) == REG \ + && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) + +#define RTX_OK_FOR_OFFSET_P(X) \ + (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) + +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ if (RTX_OK_FOR_BASE_P (X)) \ + goto ADDR; \ + else if (GET_CODE (X) == PLUS) \ + { \ + register rtx op0 = XEXP (X, 0); \ + register rtx op1 = XEXP (X, 1); \ + if (flag_pic && op0 == pic_offset_table_rtx) \ + { \ + if (RTX_OK_FOR_BASE_P (op1)) \ + goto ADDR; \ + else if (flag_pic == 1 \ + && GET_CODE (op1) != REG \ + && GET_CODE (op1) != LO_SUM \ + && GET_CODE (op1) != MEM \ + && (GET_CODE (op1) != CONST_INT \ + || SMALL_INT (op1))) \ + goto ADDR; \ + } \ + else if (RTX_OK_FOR_BASE_P (op0)) \ + { \ + if ((RTX_OK_FOR_INDEX_P (op1) \ + /* We prohibit REG + REG for TFmode when \ + there are no instructions which accept \ + REG+REG instructions. We do this \ + because REG+REG is not an offsetable \ + address. If we get the situation \ + in reload where source and destination \ + of a movtf pattern are both MEMs with \ + REG+REG address, then only one of them \ + gets converted to an offsetable \ + address. */ \ + && (MODE != TFmode \ + || (TARGET_FPU && TARGET_ARCH64 \ + && TARGET_V9 \ + && TARGET_HARD_QUAD))) \ + || RTX_OK_FOR_OFFSET_P (op1)) \ + goto ADDR; \ + } \ + else if (RTX_OK_FOR_BASE_P (op1)) \ + { \ + if ((RTX_OK_FOR_INDEX_P (op0) \ + /* See the previous comment. */ \ + && (MODE != TFmode \ + || (TARGET_FPU && TARGET_ARCH64 \ + && TARGET_V9 \ + && TARGET_HARD_QUAD))) \ + || RTX_OK_FOR_OFFSET_P (op0)) \ + goto ADDR; \ + } \ + } \ + else if (GET_CODE (X) == LO_SUM) \ + { \ + register rtx op0 = XEXP (X, 0); \ + register rtx op1 = XEXP (X, 1); \ + if (RTX_OK_FOR_BASE_P (op0) \ + && CONSTANT_P (op1) \ + /* We can't allow TFmode, because an offset \ + greater than or equal to the alignment (8) \ + may cause the LO_SUM to overflow if !v9. */\ + && (MODE != TFmode || TARGET_V9)) \ + goto ADDR; \ + } \ + else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ + goto ADDR; \ +} + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. */ + +/* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ +extern struct rtx_def *legitimize_pic_address (); +#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ +{ rtx sparc_x = (X); \ + if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ + (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \ + force_operand (XEXP (X, 0), NULL_RTX)); \ + if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ + (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ + force_operand (XEXP (X, 1), NULL_RTX)); \ + if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ + (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ + XEXP (X, 1)); \ + if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ + (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ + force_operand (XEXP (X, 1), NULL_RTX)); \ + if (sparc_x != (X) && memory_address_p (MODE, X)) \ + goto WIN; \ + if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ + else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ + (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0), \ + copy_to_mode_reg (Pmode, XEXP (X, 1))); \ + else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ + (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1), \ + copy_to_mode_reg (Pmode, XEXP (X, 0))); \ + else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ + || GET_CODE (X) == LABEL_REF) \ + (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); \ + if (memory_address_p (MODE, X)) \ + goto WIN; } + +/* Try a machine-dependent way of reloading an illegitimate address + operand. If we find one, push the reload and jump to WIN. This + macro is used in only one place: `find_reloads_address' in reload.c. + + For Sparc 32, we wish to handle addresses by splitting them into + HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. + This cuts the number of extra insns by one. + + Do nothing when generating PIC code and the address is a + symbolic operand or requires a scratch register. */ + +#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ +do { \ + /* Decompose SImode constants into hi+lo_sum. We do have to \ + rerecognize what we produce, so be careful. */ \ + if (CONSTANT_P (X) \ + && (MODE != TFmode || TARGET_V9) \ + && GET_MODE (X) == SImode \ + && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ + && ! (flag_pic \ + && (symbolic_operand (X, Pmode) \ + || pic_address_needs_scratch (X)))) \ + { \ + X = gen_rtx_LO_SUM (GET_MODE (X), \ + gen_rtx_HIGH (GET_MODE (X), X), X); \ + push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \ + BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ + OPNUM, TYPE); \ + goto WIN; \ + } \ + /* ??? 64-bit reloads. */ \ +} while (0) + +/* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. + On the SPARC this is never true. */ + +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) + +/* If we are referencing a function make the SYMBOL_REF special. + In the Embedded Medium/Anywhere code model, %g4 points to the data segment + so we must not add it to function addresses. */ + +#define ENCODE_SECTION_INFO(DECL) \ + do { \ + if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ + SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ + } while (0) + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. */ +/* If we ever implement any of the full models (such as CM_FULLANY), + this has to be DImode in that case */ +#ifdef HAVE_GAS_SUBSECTION_ORDERING +#define CASE_VECTOR_MODE \ +(! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) +#else +/* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise + we have to sign extend which slows things down. */ +#define CASE_VECTOR_MODE \ +(! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) +#endif + +/* Define as C expression which evaluates to nonzero if the tablejump + instruction expects the table to contain offsets from the address of the + table. + Do not define this if the table should contain absolute addresses. */ +/* #define CASE_VECTOR_PC_RELATIVE 1 */ + +/* Specify the tree operation to be used to convert reals to integers. */ +#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + +/* This is the kind of divide that is easiest to do in the general case. */ +#define EASY_DIV_EXPR TRUNC_DIV_EXPR + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#define DEFAULT_SIGNED_CHAR 1 + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ +#define MOVE_MAX 8 + +#if 0 /* Sun 4 has matherr, so this is no good. */ +/* This is the value of the error code EDOM for this machine, + used by the sqrt instruction. */ +#define TARGET_EDOM 33 + +/* This is how to refer to the variable errno. */ +#define GEN_ERRNO_RTX \ + gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno")) +#endif /* 0 */ + +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND + +/* Nonzero if access to memory by bytes is slow and undesirable. + For RISC chips, it means that access to memory by bytes is no + better than access by words when possible, so grab a whole word + and maybe make use of that. */ +#define SLOW_BYTE_ACCESS 1 + +/* We assume that the store-condition-codes instructions store 0 for false + and some other value for true. This is the value stored for true. */ + +#define STORE_FLAG_VALUE 1 + +/* When a prototype says `char' or `short', really pass an `int'. */ +#define PROMOTE_PROTOTYPES + +/* Define this to be nonzero if shift instructions ignore all but the low-order + few bits. */ +#define SHIFT_COUNT_TRUNCATED 1 + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode (TARGET_PTR64 ? DImode : SImode) + +/* Generate calls to memcpy, memcmp and memset. */ +#define TARGET_MEM_FUNCTIONS + +/* Add any extra modes needed to represent the condition code. + + On the Sparc, we have a "no-overflow" mode which is used when an add or + subtract insn is used to set the condition code. Different branches are + used in this case for some operations. + + We also have two modes to indicate that the relevant condition code is + in the floating-point condition code register. One for comparisons which + will generate an exception if the result is unordered (CCFPEmode) and + one for comparisons which will never trap (CCFPmode). + + CCXmode and CCX_NOOVmode are only used by v9. */ + +#define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode + +/* Define the names for the modes specified above. */ + +#define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE" + +/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, + return the mode to be used for the comparison. For floating-point, + CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a + PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special + processing is needed. */ +#define SELECT_CC_MODE(OP,X,Y) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ + : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ + || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \ + ? (TARGET_ARCH64 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \ + : ((TARGET_ARCH64 || TARGET_V8PLUS) && GET_MODE (X) == DImode ? CCXmode : CCmode))) + +/* Return non-zero if SELECT_CC_MODE will never return MODE for a + floating point inequality comparison. */ + +#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) + +/* A function address in a call instruction + is a byte address (for indexing purposes) + so give the MEM rtx a byte's mode. */ +#define FUNCTION_MODE SImode + +/* Define this if addresses of constant functions + shouldn't be put through pseudo regs where they can be cse'd. + Desirable on machines where ordinary constants are expensive + but a CALL with constant address is cheap. */ +#define NO_FUNCTION_CSE + +/* alloca should avoid clobbering the old register save area. */ +#define SETJMP_VIA_SAVE_AREA + +/* Define subroutines to call to handle multiply and divide. + Use the subroutines that Sun's library provides. + The `*' prevents an underscore from being prepended by the compiler. */ + +#define DIVSI3_LIBCALL "*.div" +#define UDIVSI3_LIBCALL "*.udiv" +#define MODSI3_LIBCALL "*.rem" +#define UMODSI3_LIBCALL "*.urem" +/* .umul is a little faster than .mul. */ +#define MULSI3_LIBCALL "*.umul" + +/* Define library calls for quad FP operations. These are all part of the + SPARC ABI. + ??? ARCH64 still does not work as the _Qp_* routines take pointers. */ +#define ADDTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_add" : "_Q_add") +#define SUBTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_sub" : "_Q_sub") +#define NEGTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_neg" : "_Q_neg") +#define MULTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_mul" : "_Q_mul") +#define DIVTF3_LIBCALL (TARGET_ARCH64 ? "_Qp_div" : "_Q_div") +#define FLOATSITF2_LIBCALL (TARGET_ARCH64 ? "_Qp_itoq" : "_Q_itoq") +#define FIX_TRUNCTFSI2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtoi" : "_Q_qtoi") +#define FIXUNS_TRUNCTFSI2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtoui" : "_Q_qtou") +#define EXTENDSFTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_stoq" : "_Q_stoq") +#define TRUNCTFSF2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtos" : "_Q_qtos") +#define EXTENDDFTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_dtoq" : "_Q_dtoq") +#define TRUNCTFDF2_LIBCALL (TARGET_ARCH64 ? "_Qp_qtod" : "_Q_qtod") +#define EQTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq") +#define NETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne") +#define GTTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt") +#define GETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge") +#define LTTF2_LIBCALL (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt") +#define LETF2_LIBCALL (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle") + +/* We can define the TFmode sqrt optab only if TARGET_FPU. This is because + with soft-float, the SFmode and DFmode sqrt instructions will be absent, + and the compiler will notice and try to use the TFmode sqrt instruction + for calls to the builtin function sqrt, but this fails. */ +#define INIT_TARGET_OPTABS \ + do { \ + add_optab->handlers[(int) TFmode].libfunc \ + = gen_rtx_SYMBOL_REF (Pmode, ADDTF3_LIBCALL); \ + sub_optab->handlers[(int) TFmode].libfunc \ + = gen_rtx_SYMBOL_REF (Pmode, SUBTF3_LIBCALL); \ + neg_optab->handlers[(int) TFmode].libfunc \ + = gen_rtx_SYMBOL_REF (Pmode, NEGTF2_LIBCALL); \ + smul_optab->handlers[(int) TFmode].libfunc \ + = gen_rtx_SYMBOL_REF (Pmode, MULTF3_LIBCALL); \ + flodiv_optab->handlers[(int) TFmode].libfunc \ + = gen_rtx_SYMBOL_REF (Pmode, DIVTF3_LIBCALL); \ + eqtf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EQTF2_LIBCALL); \ + netf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, NETF2_LIBCALL); \ + gttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GTTF2_LIBCALL); \ + getf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, GETF2_LIBCALL); \ + lttf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LTTF2_LIBCALL); \ + letf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, LETF2_LIBCALL); \ + trunctfsf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFSF2_LIBCALL); \ + trunctfdf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, TRUNCTFDF2_LIBCALL); \ + extendsftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDSFTF2_LIBCALL); \ + extenddftf2_libfunc = gen_rtx_SYMBOL_REF (Pmode, EXTENDDFTF2_LIBCALL); \ + floatsitf_libfunc = gen_rtx_SYMBOL_REF (Pmode, FLOATSITF2_LIBCALL); \ + fixtfsi_libfunc = gen_rtx_SYMBOL_REF (Pmode, FIX_TRUNCTFSI2_LIBCALL); \ + fixunstfsi_libfunc \ + = gen_rtx_SYMBOL_REF (Pmode, FIXUNS_TRUNCTFSI2_LIBCALL); \ + if (TARGET_FPU) \ + sqrt_optab->handlers[(int) TFmode].libfunc \ + = gen_rtx_SYMBOL_REF (Pmode, "_Q_sqrt"); \ + INIT_SUBTARGET_OPTABS; \ + } while (0) + +/* This is meant to be redefined in the host dependent files */ +#define INIT_SUBTARGET_OPTABS + +/* Compute the cost of computing a constant rtl expression RTX + whose rtx-code is CODE. The body of this macro is a portion + of a switch statement. If the code is computed here, + return it with a return statement. Otherwise, break from the switch. */ + +#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ + case CONST_INT: \ + if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ + return 0; \ + case HIGH: \ + return 2; \ + case CONST: \ + case LABEL_REF: \ + case SYMBOL_REF: \ + return 4; \ + case CONST_DOUBLE: \ + if (GET_MODE (RTX) == DImode) \ + if ((XINT (RTX, 3) == 0 \ + && (unsigned) XINT (RTX, 2) < 0x1000) \ + || (XINT (RTX, 3) == -1 \ + && XINT (RTX, 2) < 0 \ + && XINT (RTX, 2) >= -0x1000)) \ + return 0; \ + return 8; + +#define ADDRESS_COST(RTX) 1 + +/* Compute extra cost of moving data between one register class + and another. */ +#define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) +#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ + (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ + || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ + || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ + ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2) + +/* Provide the costs of a rtl expression. This is in the body of a + switch on CODE. The purpose for the cost of MULT is to encourage + `synth_mult' to find a synthetic multiply when reasonable. + + If we need more than 12 insns to do a multiply, then go out-of-line, + since the call overhead will be < 10% of the cost of the multiply. */ + +#define RTX_COSTS(X,CODE,OUTER_CODE) \ + case MULT: \ + if (sparc_cpu == PROCESSOR_ULTRASPARC) \ + return (GET_MODE (X) == DImode ? \ + COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \ + return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ + case DIV: \ + case UDIV: \ + case MOD: \ + case UMOD: \ + if (sparc_cpu == PROCESSOR_ULTRASPARC) \ + return (GET_MODE (X) == DImode ? \ + COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \ + return COSTS_N_INSNS (25); \ + /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ + so that cse will favor the latter. */ \ + case FLOAT: \ + case FIX: \ + return 19; + +#define ISSUE_RATE sparc_issue_rate() + +/* Adjust the cost of dependencies. */ +#define ADJUST_COST(INSN,LINK,DEP,COST) \ + sparc_adjust_cost(INSN, LINK, DEP, COST) + +extern void ultrasparc_sched_reorder (); +extern void ultrasparc_sched_init (); +extern int ultrasparc_variable_issue (); + +#define MD_SCHED_INIT(DUMP, SCHED_VERBOSE) \ + if (sparc_cpu == PROCESSOR_ULTRASPARC) \ + ultrasparc_sched_init (DUMP, SCHED_VERBOSE) + +#define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY) \ + if (sparc_cpu == PROCESSOR_ULTRASPARC) \ + ultrasparc_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY) + +#define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \ + if (sparc_cpu == PROCESSOR_ULTRASPARC) \ + (CAN_ISSUE_MORE) = ultrasparc_variable_issue (INSN); \ + else \ + (CAN_ISSUE_MORE)-- + +/* Conditional branches with empty delay slots have a length of two. */ +#define ADJUST_INSN_LENGTH(INSN, LENGTH) \ + if (GET_CODE (INSN) == CALL_INSN \ + || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ + LENGTH += 1; else + +/* Control the assembler format that we output. */ + +/* Output at beginning of assembler file. */ + +#define ASM_FILE_START(file) + +/* A C string constant describing how to begin a comment in the target + assembler language. The compiler assumes that the comment will end at + the end of the line. */ + +#define ASM_COMMENT_START "!" + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON "" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF "" + +/* ??? Try to make the style consistent here (_OP?). */ + +#define ASM_LONGLONG ".xword" +#define ASM_LONG ".word" +#define ASM_SHORT ".half" +#define ASM_BYTE_OP ".byte" +#define ASM_FLOAT ".single" +#define ASM_DOUBLE ".double" +#define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ + +/* Output before read-only data. */ + +#define TEXT_SECTION_ASM_OP ".text" + +/* Output before writable data. */ + +#define DATA_SECTION_ASM_OP ".data" + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + +#define REGISTER_NAMES \ +{"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ + "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ + "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ + "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ + "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ + "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ + "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ + "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ + "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ + "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ + "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ + "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ + "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc"} + +/* Define additional names for use in asm clobbers and asm declarations. */ + +#define ADDITIONAL_REGISTER_NAMES \ +{{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} + +/* How to renumber registers for dbx and gdb. In the flat model, the frame + pointer is really %i7. */ + +#define DBX_REGISTER_NUMBER(REGNO) \ + (TARGET_FLAT && REGNO == FRAME_POINTER_REGNUM ? 31 : REGNO) + +/* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length + can run past this up to a continuation point. Once we used 1500, but + a single entry in C++ can run more than 500 bytes, due to the length of + mangled symbol names. dbxout.c should really be fixed to do + continuations when they are actually needed instead of trying to + guess... */ +#define DBX_CONTIN_LENGTH 1000 + +/* This is how to output a note to DBX telling it the line number + to which the following sequence of instructions corresponds. + + This is needed for SunOS 4.0, and should not hurt for 3.2 + versions either. */ +#define ASM_OUTPUT_SOURCE_LINE(file, line) \ + { static int sym_lineno = 1; \ + fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ + line, sym_lineno, sym_lineno); \ + sym_lineno += 1; } + +/* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. */ + +#define ASM_OUTPUT_LABEL(FILE,NAME) \ + do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) + +/* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + +#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ + do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) + +/* The prefix to add to user-visible assembler symbols. */ + +#define USER_LABEL_PREFIX "_" + +/* This is how to output a definition of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, "%s%d:\n", PREFIX, NUM) + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) + +/* This is how to output an assembler line defining a `float' constant. + We always have to use a .long pseudo-op to do this because the native + SVR4 ELF assembler is buggy and it generates incorrect values when we + try to use the .float pseudo-op instead. */ + +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ + { \ + long t; \ + char str[30]; \ + REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ + REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ + fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t, \ + ASM_COMMENT_START, str); \ + } \ + +/* This is how to output an assembler line defining a `double' constant. + We always have to use a .long pseudo-op to do this because the native + SVR4 ELF assembler is buggy and it generates incorrect values when we + try to use the .float pseudo-op instead. */ + +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + { \ + long t[2]; \ + char str[30]; \ + REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ + REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ + fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \ + ASM_COMMENT_START, str); \ + fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \ + } + +/* This is how to output an assembler line defining a `long double' + constant. */ + +#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ + { \ + long t[4]; \ + char str[30]; \ + REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ + REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ + fprintf (FILE, "\t%s\t0x%lx %s ~%s\n", ASM_LONG, t[0], \ + ASM_COMMENT_START, str); \ + fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[1]); \ + fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[2]); \ + fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t[3]); \ + } + +/* This is how to output an assembler line defining an `int' constant. */ + +#define ASM_OUTPUT_INT(FILE,VALUE) \ +( fprintf (FILE, "\t%s\t", ASM_LONG), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +/* This is how to output an assembler line defining a DImode constant. */ +#define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ + output_double_int (FILE, VALUE) + +/* Likewise for `char' and `short' constants. */ + +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "\t%s\t", ASM_SHORT), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +#define ASM_OUTPUT_CHAR(FILE,VALUE) \ +( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +/* This is how to output an assembler line for a numeric constant byte. */ + +#define ASM_OUTPUT_BYTE(FILE,VALUE) \ + fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) + +/* This is how we hook in and defer the case-vector until the end of + the function. */ +extern void sparc_defer_case_vector (); + +#define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ + sparc_defer_case_vector ((LAB),(VEC), 0) + +#define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ + sparc_defer_case_vector ((LAB),(VEC), 1) + +/* This is how to output an element of a case-vector that is absolute. */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ +do { \ + char label[30]; \ + ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ + if (CASE_VECTOR_MODE == SImode) \ + fprintf (FILE, "\t.word\t"); \ + else \ + fprintf (FILE, "\t.xword\t"); \ + assemble_name (FILE, label); \ + fputc ('\n', FILE); \ +} while (0) + +/* This is how to output an element of a case-vector that is relative. + (SPARC uses such vectors only when generating PIC.) */ + +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ +do { \ + char label[30]; \ + ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ + if (CASE_VECTOR_MODE == SImode) \ + fprintf (FILE, "\t.word\t"); \ + else \ + fprintf (FILE, "\t.xword\t"); \ + assemble_name (FILE, label); \ + ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ + fputc ('-', FILE); \ + assemble_name (FILE, label); \ + fputc ('\n', FILE); \ +} while (0) + +/* This is what to output before and after case-vector (both + relative and absolute). If .subsection -1 works, we put case-vectors + at the beginning of the current section. */ + +#ifdef HAVE_GAS_SUBSECTION_ORDERING + +#define ASM_OUTPUT_ADDR_VEC_START(FILE) \ + fprintf(FILE, "\t.subsection\t-1\n") + +#define ASM_OUTPUT_ADDR_VEC_END(FILE) \ + fprintf(FILE, "\t.previous\n") + +#endif + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG) != 0) \ + fprintf (FILE, "\t.align %d\n", (1<<(LOG))) + +#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (sparc_align_jumps) + +#define LOOP_ALIGN(LABEL) (sparc_align_loops) + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.skip %u\n", (SIZE)) + +/* This says how to output an assembler line + to define a global common symbol. */ + +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ +( fputs ("\t.common ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u,\"bss\"\n", (SIZE))) + +/* This says how to output an assembler line to define a local common + symbol. */ + +#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ +( fputs ("\t.reserve ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u,\"bss\",%u\n", \ + (SIZE), ((ALIGNED) / BITS_PER_UNIT))) + +/* A C statement (sans semicolon) to output to the stdio stream + FILE the assembler definition of uninitialized global DECL named + NAME whose size is SIZE bytes and alignment is ALIGN bytes. + Try to use asm_output_aligned_bss to implement this macro. */ + +#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ + do { \ + fputs (".globl ", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + fputs ("\n", (FILE)); \ + ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ + } while (0) + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + +#define IDENT_ASM_OP ".ident" + +/* Output #ident as a .ident. */ + +#define ASM_OUTPUT_IDENT(FILE, NAME) \ + fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME); + +/* Output code to add DELTA to the first argument, and then jump to FUNCTION. + Used for C++ multiple inheritance. */ +#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ +do { \ + int big_delta = (DELTA) >= 4096 || (DELTA) < -4096; \ + if (big_delta) \ + fprintf (FILE, "\tset %d,%%g1\n\tadd %%o0,%%g1,%%o0\n", (DELTA)); \ + /* Don't use the jmp solution unless we know the target is local to \ + the application or shared object. \ + XXX: Wimp out and don't actually check anything except if this is \ + an embedded target where we assume there are no shared libs. */ \ + if (!TARGET_CM_EMBMEDANY || flag_pic) \ + { \ + if (! big_delta) \ + fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \ + fprintf (FILE, "\tmov %%o7,%%g1\n"); \ + fprintf (FILE, "\tcall "); \ + assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ + fprintf (FILE, ",0\n"); \ + } \ + else if (TARGET_CM_EMBMEDANY) \ + { \ + fprintf (FILE, "\tsetx "); \ + assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ + fprintf (FILE, ",%%g5,%%g1\n\tjmp %%g1\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tsethi %%hi("); \ + assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ + fprintf (FILE, "),%%g1\n\tjmp %%g1+%%lo("); \ + assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ + fprintf (FILE, ")\n"); \ + } \ + if (!TARGET_CM_EMBMEDANY || flag_pic) \ + fprintf (FILE, "\tmov %%g1,%%o7\n"); \ + else if (big_delta) \ + fprintf (FILE, "\tnop\n"); \ + else \ + fprintf (FILE, "\tadd %%o0,%d,%%o0\n", DELTA); \ +} while (0) + +/* Define the parentheses used to group arithmetic operations + in assembler code. */ + +#define ASM_OPEN_PAREN "(" +#define ASM_CLOSE_PAREN ")" + +/* Define results of standard character escape sequences. */ +#define TARGET_BELL 007 +#define TARGET_BS 010 +#define TARGET_TAB 011 +#define TARGET_NEWLINE 012 +#define TARGET_VT 013 +#define TARGET_FF 014 +#define TARGET_CR 015 + +#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ + ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_') + +/* Print operand X (an rtx) in assembler syntax to file FILE. + CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. + For `%' followed by punctuation, CODE is the punctuation and X is null. */ + +#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) + +/* Print a memory address as an operand to reference that memory location. */ + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ +{ register rtx base, index = 0; \ + int offset = 0; \ + register rtx addr = ADDR; \ + if (GET_CODE (addr) == REG) \ + fputs (reg_names[REGNO (addr)], FILE); \ + else if (GET_CODE (addr) == PLUS) \ + { \ + if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ + offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ + else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ + offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ + else \ + base = XEXP (addr, 0), index = XEXP (addr, 1); \ + fputs (reg_names[REGNO (base)], FILE); \ + if (index == 0) \ + fprintf (FILE, "%+d", offset); \ + else if (GET_CODE (index) == REG) \ + fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ + else if (GET_CODE (index) == SYMBOL_REF \ + || GET_CODE (index) == CONST) \ + fputc ('+', FILE), output_addr_const (FILE, index); \ + else abort (); \ + } \ + else if (GET_CODE (addr) == MINUS \ + && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ + { \ + output_addr_const (FILE, XEXP (addr, 0)); \ + fputs ("-(", FILE); \ + output_addr_const (FILE, XEXP (addr, 1)); \ + fputs ("-.)", FILE); \ + } \ + else if (GET_CODE (addr) == LO_SUM) \ + { \ + output_operand (XEXP (addr, 0), 0); \ + if (TARGET_CM_MEDMID) \ + fputs ("+%l44(", FILE); \ + else \ + fputs ("+%lo(", FILE); \ + output_address (XEXP (addr, 1)); \ + fputc (')', FILE); \ + } \ + else if (flag_pic && GET_CODE (addr) == CONST \ + && GET_CODE (XEXP (addr, 0)) == MINUS \ + && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ + && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ + && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ + { \ + addr = XEXP (addr, 0); \ + output_addr_const (FILE, XEXP (addr, 0)); \ + /* Group the args of the second CONST in parenthesis. */ \ + fputs ("-(", FILE); \ + /* Skip past the second CONST--it does nothing for us. */\ + output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ + /* Close the parenthesis. */ \ + fputc (')', FILE); \ + } \ + else \ + { \ + output_addr_const (FILE, addr); \ + } \ +} + +/* Define the codes that are matched by predicates in sparc.c. */ + +#define PREDICATE_CODES \ +{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ +{"fp_zero_operand", {CONST_DOUBLE}}, \ +{"intreg_operand", {SUBREG, REG}}, \ +{"fcc_reg_operand", {REG}}, \ +{"icc_or_fcc_reg_operand", {REG}}, \ +{"restore_operand", {REG}}, \ +{"call_operand", {MEM}}, \ +{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \ + ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \ +{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE}}, \ +{"symbolic_memory_operand", {SUBREG, MEM}}, \ +{"label_ref_operand", {LABEL_REF}}, \ +{"sp64_medium_pic_operand", {CONST}}, \ +{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \ +{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \ +{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \ +{"splittable_symbolic_memory_operand", {MEM}}, \ +{"splittable_immediate_memory_operand", {MEM}}, \ +{"eq_or_neq", {EQ, NE}}, \ +{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \ +{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \ +{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \ +{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \ +{"cc_arithop", {AND, IOR, XOR}}, \ +{"cc_arithopn", {AND, IOR}}, \ +{"arith_operand", {SUBREG, REG, CONST_INT}}, \ +{"arith_add_operand", {SUBREG, REG, CONST_INT}}, \ +{"arith11_operand", {SUBREG, REG, CONST_INT}}, \ +{"arith10_operand", {SUBREG, REG, CONST_INT}}, \ +{"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ +{"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ +{"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ +{"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ +{"small_int", {CONST_INT}}, \ +{"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \ +{"uns_small_int", {CONST_INT}}, \ +{"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \ +{"clobbered_register", {REG}}, \ +{"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \ +{"zero_operand", {CONST_INT}}, \ +{"const64_operand", {CONST_INT, CONST_DOUBLE}}, \ +{"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, + +/* The number of Pmode words for the setjmp buffer. */ +#define JMP_BUF_SIZE 12 + +#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic) + +/* Declare functions defined in sparc.c and used in templates. */ + +extern void sparc_emit_set_const32 (); +extern void sparc_emit_set_const64 (); +extern void sparc_emit_set_symbolic_const64 (); +extern int sparc_splitdi_legitimate (); +extern int sparc_absnegfloat_split_legitimate (); + +extern char *output_cbranch (); +extern const char *output_return (); +extern char *output_v9branch (); + +extern void emit_v9_brxx_insn (); +extern void finalize_pic (); +extern void order_regs_for_local_alloc (); +extern void output_double_int (); +extern void output_function_epilogue (); +extern void output_function_prologue (); +extern void print_operand (); +extern void sparc_flat_output_function_epilogue (); +extern void sparc_flat_output_function_prologue (); + +extern int addrs_ok_for_ldd_peep (); +extern int arith10_double_operand (); +extern int arith10_operand (); +extern int arith11_double_operand (); +extern int arith11_operand (); +extern int arith_double_operand (); +extern int arith_double_4096_operand (); +extern int arith_double_add_operand (); +extern int arith_operand (); +extern int arith_4096_operand (); +extern int arith_add_operand (); +extern int call_operand_address (); +extern int input_operand (); +extern int zero_operand (); +extern int const64_operand (); +extern int const64_high_operand (); +extern int cc_arithop (); +extern int cc_arithopn (); +extern int check_pic (); +extern int compute_frame_size (); +extern int data_segment_operand (); +extern int eligible_for_epilogue_delay (); +extern int eligible_for_return_delay (); +extern int emit_move_sequence (); +extern int extend_op (); +extern int fcc_reg_operand (); +extern int fp_zero_operand (); +extern int icc_or_fcc_reg_operand (); +extern int label_ref_operand (); +extern int mem_min_alignment (); +extern int noov_compare_op (); +extern int pic_address_needs_scratch (); +extern int reg_or_0_operand (); +extern int reg_or_nonsymb_mem_operand (); +extern int reg_unused_after (); +extern int register_ok_for_ldd (); +extern int registers_ok_for_ldd_peep (); +extern int restore_operand (); +extern int short_branch (); +extern int small_int (); +extern int small_int_or_double (); +extern int sp64_medium_pic_operand (); +extern int sparc_flat_eligible_for_epilogue_delay (); +extern int sparc_flat_epilogue_delay_slots (); +extern int sparc_issue_rate (); +extern int splittable_immediate_memory_operand (); +extern int splittable_symbolic_memory_operand (); +extern int sparc_adjust_cost (); +extern int symbolic_memory_operand (); +extern int symbolic_operand (); +extern int text_segment_operand (); +extern int uns_small_int (); +extern int v9_regcmp_op (); +extern int v9_regcmp_p (); + +extern unsigned long sparc_flat_compute_frame_size (); +extern unsigned long sparc_type_code (); + +extern void sparc_function_profiler (); +extern void sparc_function_block_profiler (); +extern void sparc_block_profiler (); +extern void sparc_function_block_profiler_exit (); + +extern char *sparc_v8plus_shift (); + +#ifdef __STDC__ +/* Function used for V8+ code generation. Returns 1 if the high + 32 bits of REG are 0 before INSN. */ +extern int sparc_check_64 (struct rtx_def *, struct rtx_def *); +extern int sparc_return_peephole_ok (struct rtx_def *, struct rtx_def *); +extern int compute_frame_size (int, int); +#endif + +/* Defined in flags.h, but insn-emit.c does not include flags.h. */ + +extern int flag_pic; diff --git a/contrib/gcc/config/sparc/sparc.md b/contrib/gcc/config/sparc/sparc.md new file mode 100644 index 000000000000..aafb7a63ea41 --- /dev/null +++ b/contrib/gcc/config/sparc/sparc.md @@ -0,0 +1,8236 @@ +;;- Machine description for SPARC chip for GNU C compiler +;; Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc. +;; Contributed by Michael Tiemann (tiemann@cygnus.com) +;; 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, +;; at Cygnus Support. + +;; This file is part of GNU CC. + +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. + +;; Uses of UNSPEC and UNSPEC_VOLATILE in this file: +;; +;; UNSPEC: 0 movsi_{lo_sum,high}_pic +;; pic_lo_sum_di +;; pic_sethi_di +;; 1 update_return +;; 2 get_pc +;; 5 movsi_{,lo_sum_,high_}pic_label_ref +;; 6 seth44 +;; 7 setm44 +;; 8 setl44 +;; 9 sethh +;; 10 setlm +;; 11 embmedany_sethi, embmedany_brsum +;; 12 movsf_const_high +;; 13 embmedany_textuhi +;; 14 embmedany_texthi +;; 15 embmedany_textulo +;; 16 embmedany_textlo +;; 17 movsf_const_lo +;; 18 sethm +;; 19 setlo +;; +;; UNSPEC_VOLATILE: 0 blockage +;; 1 flush_register_windows +;; 2 goto_handler_and_restore +;; 3 goto_handler_and_restore_v9* +;; 4 flush +;; 5 nonlocal_goto_receiver +;; + +;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this +;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name +;; is a bit of a misnomer as it covers all 64 fp regs. The corresponding +;; constraint letter is 'e'. To avoid any confusion, 'e' is used instead of +;; 'f' for all DF/TFmode values, including those that are specific to the v8. +;; +;; -mlive-g0 is *not* supported for TARGET_ARCH64, so we don't bother to +;; test TARGET_LIVE_G0 if we have TARGET_ARCH64. + +;; Attribute for cpu type. +;; These must match the values for enum processor_type in sparc.h. +(define_attr "cpu" "v7,cypress,v8,supersparc,sparclite,f930,f934,hypersparc,sparclite86x,sparclet,tsc701,v9,ultrasparc" + (const (symbol_ref "sparc_cpu_attr"))) + +;; Attribute for the instruction set. +;; At present we only need to distinguish v9/!v9, but for clarity we +;; test TARGET_V8 too. +(define_attr "isa" "v6,v8,v9,sparclet" + (const + (cond [(symbol_ref "TARGET_V9") (const_string "v9") + (symbol_ref "TARGET_V8") (const_string "v8") + (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")] + (const_string "v6")))) + +;; Architecture size. +(define_attr "arch" "arch32bit,arch64bit" + (const + (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")] + (const_string "arch32bit")))) + +;; Whether -mlive-g0 is in effect. +(define_attr "live_g0" "no,yes" + (const + (cond [(symbol_ref "TARGET_LIVE_G0") (const_string "yes")] + (const_string "no")))) + +;; Insn type. Used to default other attribute values. + +;; type "unary" insns have one input operand (1) and one output operand (0) +;; type "binary" insns have two input operands (1,2) and one output (0) +;; type "compare" insns have one or two input operands (0,1) and no output +;; type "call_no_delay_slot" is a call followed by an unimp instruction. + +(define_attr "type" + "move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrt,cmove,multi,misc" + (const_string "binary")) + +;; Set true if insn uses call-clobbered intermediate register. +(define_attr "use_clobbered" "false,true" + (if_then_else (and (eq_attr "type" "address") + (match_operand 0 "clobbered_register" "")) + (const_string "true") + (const_string "false"))) + +;; Length (in # of insns). +(define_attr "length" "" + (cond [(eq_attr "type" "load,sload,fpload") + (if_then_else (match_operand 1 "symbolic_memory_operand" "") + (const_int 2) (const_int 1)) + + (eq_attr "type" "store,fpstore") + (if_then_else (match_operand 0 "symbolic_memory_operand" "") + (const_int 2) (const_int 1)) + + (eq_attr "type" "address") (const_int 2) + + (eq_attr "type" "binary") + (if_then_else (ior (match_operand 2 "arith_operand" "") + (match_operand 2 "arith_double_operand" "")) + (const_int 1) (const_int 3)) + + (eq_attr "type" "multi") (const_int 2) + + (eq_attr "type" "move,unary") + (if_then_else (ior (match_operand 1 "arith_operand" "") + (match_operand 1 "arith_double_operand" "")) + (const_int 1) (const_int 2))] + + (const_int 1))) + +(define_asm_attributes + [(set_attr "length" "1") + (set_attr "type" "multi")]) + +;; Attributes for instruction and branch scheduling + +(define_attr "in_call_delay" "false,true" + (cond [(eq_attr "type" "uncond_branch,branch,call,call_no_delay_slot,return,multi") + (const_string "false") + (eq_attr "type" "load,fpload,store,fpstore") + (if_then_else (eq_attr "length" "1") + (const_string "true") + (const_string "false")) + (eq_attr "type" "address") + (if_then_else (eq_attr "use_clobbered" "false") + (const_string "true") + (const_string "false"))] + (if_then_else (eq_attr "length" "1") + (const_string "true") + (const_string "false")))) + +(define_delay (eq_attr "type" "call") + [(eq_attr "in_call_delay" "true") (nil) (nil)]) + +(define_attr "leaf_function" "false,true" + (const (symbol_ref "current_function_uses_only_leaf_regs"))) + +(define_attr "in_return_delay" "false,true" + (if_then_else (and (and (and (eq_attr "type" "move,load,sload,store,binary,ialu") + (eq_attr "length" "1")) + (eq_attr "leaf_function" "false")) + (match_insn "eligible_for_return_delay")) + (const_string "true") + (const_string "false"))) + +(define_delay (and (eq_attr "type" "return") + (eq_attr "isa" "v9")) + [(eq_attr "in_return_delay" "true") (nil) (nil)]) + +;; ??? Should implement the notion of predelay slots for floating point +;; branches. This would allow us to remove the nop always inserted before +;; a floating point branch. + +;; ??? It is OK for fill_simple_delay_slots to put load/store instructions +;; in a delay slot, but it is not OK for fill_eager_delay_slots to do so. +;; This is because doing so will add several pipeline stalls to the path +;; that the load/store did not come from. Unfortunately, there is no way +;; to prevent fill_eager_delay_slots from using load/store without completely +;; disabling them. For the SPEC benchmark set, this is a serious lose, +;; because it prevents us from moving back the final store of inner loops. + +(define_attr "in_branch_delay" "false,true" + (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi") + (eq_attr "length" "1")) + (const_string "true") + (const_string "false"))) + +(define_attr "in_uncond_branch_delay" "false,true" + (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi") + (eq_attr "length" "1")) + (const_string "true") + (const_string "false"))) + +(define_attr "in_annul_branch_delay" "false,true" + (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,call_no_delay_slot,multi") + (eq_attr "length" "1")) + (const_string "true") + (const_string "false"))) + +(define_delay (eq_attr "type" "branch") + [(eq_attr "in_branch_delay" "true") + (nil) (eq_attr "in_annul_branch_delay" "true")]) + +(define_delay (eq_attr "type" "uncond_branch") + [(eq_attr "in_uncond_branch_delay" "true") + (nil) (nil)]) + +;; Function units of the SPARC + +;; (define_function_unit {name} {num-units} {n-users} {test} +;; {ready-delay} {issue-delay} [{conflict-list}]) + +;; The integer ALU. +;; (Noted only for documentation; units that take one cycle do not need to +;; be specified.) + +;; On the sparclite, integer multiply takes 1, 3, or 5 cycles depending on +;; the inputs. + +;; (define_function_unit "alu" 1 0 +;; (eq_attr "type" "unary,binary,move,address") 1 0) + +;; ---- cypress CY7C602 scheduling: +;; Memory with load-delay of 1 (i.e., 2 cycle load). + +(define_function_unit "memory" 1 0 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "load,sload,fpload")) + 2 2) + +;; SPARC has two floating-point units: the FP ALU, +;; and the FP MUL/DIV/SQRT unit. +;; Instruction timings on the CY7C602 are as follows +;; FABSs 4 +;; FADDs/d 5/5 +;; FCMPs/d 4/4 +;; FDIVs/d 23/37 +;; FMOVs 4 +;; FMULs/d 5/7 +;; FNEGs 4 +;; FSQRTs/d 34/63 +;; FSUBs/d 5/5 +;; FdTOi/s 5/5 +;; FsTOi/d 5/5 +;; FiTOs/d 9/5 + +;; The CY7C602 can only support 2 fp isnsn simultaneously. +;; More insns cause the chip to stall. + +(define_function_unit "fp_alu" 1 0 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "fp,fpmove")) + 5 5) + +(define_function_unit "fp_mds" 1 0 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "fpmul")) + 7 7) + +(define_function_unit "fp_mds" 1 0 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "fpdivs,fpdivd")) + 37 37) + +(define_function_unit "fp_mds" 1 0 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "fpsqrt")) + 63 63) + +;; ----- The TMS390Z55 scheduling +;; The Supersparc can issue 1 - 3 insns per cycle: up to two integer, +;; one ld/st, one fp. +;; Memory delivers its result in one cycle to IU, zero cycles to FP + +(define_function_unit "memory" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "load,sload")) + 1 1) + +(define_function_unit "memory" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpload")) + 0 1) + +(define_function_unit "memory" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "store,fpstore")) + 1 1) + +(define_function_unit "shift" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "shift")) + 1 1) + +;; There are only two write ports to the integer register file +;; A store also uses a write port + +(define_function_unit "iwport" 2 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "load,sload,store,shift,ialu")) + 1 1) + +;; Timings; throughput/latency +;; FADD 1/3 add/sub, format conv, compar, abs, neg +;; FMUL 1/3 +;; FDIVs 4/6 +;; FDIVd 7/9 +;; FSQRTs 6/8 +;; FSQRTd 10/12 +;; IMUL 4/4 + +(define_function_unit "fp_alu" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fp,fpmove,fpcmp")) + 3 1) + +(define_function_unit "fp_mds" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpmul")) + 3 1) + +(define_function_unit "fp_mds" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpdivs")) + 6 4) + +(define_function_unit "fp_mds" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpdivd")) + 9 7) + +(define_function_unit "fp_mds" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpsqrt")) + 12 10) + +(define_function_unit "fp_mds" 1 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "imul")) + 4 4) + +;; ----- hypersparc/sparclite86x scheduling +;; The Hypersparc can issue 1 - 2 insns per cycle. The dual issue cases are: +;; L-Ld/St I-Int F-Float B-Branch LI/LF/LB/II/IF/IB/FF/FB +;; II/FF case is only when loading a 32 bit hi/lo constant +;; Single issue insns include call, jmpl, u/smul, u/sdiv, lda, sta, fcmp +;; Memory delivers its result in one cycle to IU + +(define_function_unit "memory" 1 0 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "load,sload,fpload")) + 1 1) + +(define_function_unit "memory" 1 0 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "store,fpstore")) + 2 1) + +(define_function_unit "fp_alu" 1 0 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fp,fpmove,fpcmp")) + 1 1) + +(define_function_unit "fp_mds" 1 0 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fpmul")) + 1 1) + +(define_function_unit "fp_mds" 1 0 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fpdivs")) + 8 6) + +(define_function_unit "fp_mds" 1 0 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fpdivd")) + 12 10) + +(define_function_unit "fp_mds" 1 0 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fpsqrt")) + 17 15) + +(define_function_unit "fp_mds" 1 0 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "imul")) + 17 15) + +;; ----- sparclet tsc701 scheduling +;; The tsc701 issues 1 insn per cycle. +;; Results may be written back out of order. + +;; Loads take 2 extra cycles to complete and 4 can be buffered at a time. + +(define_function_unit "tsc701_load" 4 1 + (and (eq_attr "cpu" "tsc701") + (eq_attr "type" "load,sload")) + 3 1) + +;; Stores take 2(?) extra cycles to complete. +;; It is desirable to not have any memory operation in the following 2 cycles. +;; (??? or 2 memory ops in the case of std). + +(define_function_unit "tsc701_store" 1 0 + (and (eq_attr "cpu" "tsc701") + (eq_attr "type" "store")) + 3 3 + [(eq_attr "type" "load,sload,store")]) + +;; The multiply unit has a latency of 5. +(define_function_unit "tsc701_mul" 1 0 + (and (eq_attr "cpu" "tsc701") + (eq_attr "type" "imul")) + 5 5) + +;; ----- The UltraSPARC-1 scheduling +;; UltraSPARC has two integer units. Shift instructions can only execute +;; on IE0. Condition code setting instructions, call, and jmpl (including +;; the ret and retl pseudo-instructions) can only execute on IE1. +;; Branch on register uses IE1, but branch on condition code does not. +;; Conditional moves take 2 cycles. No other instruction can issue in the +;; same cycle as a conditional move. +;; Multiply and divide take many cycles during which no other instructions +;; can issue. +;; Memory delivers its result in two cycles (except for signed loads, +;; which take one cycle more). One memory instruction can be issued per +;; cycle. + +(define_function_unit "memory" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "load,fpload")) + 2 1) + +(define_function_unit "memory" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "sload")) + 3 1) + +(define_function_unit "memory" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "store,fpstore")) + 1 1) + +(define_function_unit "ieuN" 2 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "ialu,binary,move,unary,shift,compare,call,call_no_delay_slot,uncond_branch")) + 1 1) + +(define_function_unit "ieu0" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "shift")) + 1 1) + +(define_function_unit "ieu0" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "cmove")) + 2 1) + +(define_function_unit "ieu1" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "compare,call,call_no_delay_slot,uncond_branch")) + 1 1) + +(define_function_unit "cti" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "branch")) + 1 1) + +;; Timings; throughput/latency +;; FMOV 1/1 fmov, fabs, fneg +;; FMOVcc 1/2 +;; FADD 1/4 add/sub, format conv, compar +;; FMUL 1/4 +;; FDIVs 12/12 +;; FDIVd 22/22 +;; FSQRTs 12/12 +;; FSQRTd 22/22 +;; FCMP takes 1 cycle to branch, 2 cycles to conditional move. +;; +;; ??? This is really bogus because the timings really depend upon +;; who uses the result. We should record who the user is with +;; more descriptive 'type' attribute names and account for these +;; issues in ultrasparc_adjust_cost. + +(define_function_unit "fadd" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmove")) + 1 1) + +(define_function_unit "fadd" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmove")) + 2 1) + +(define_function_unit "fadd" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fp")) + 4 1) + +(define_function_unit "fadd" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmp")) + 2 1) + +(define_function_unit "fmul" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmul")) + 4 1) + +(define_function_unit "fadd" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmove")) + 2 1) + +(define_function_unit "fmul" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpdivs")) + 12 12) + +(define_function_unit "fmul" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpdivd")) + 22 22) + +(define_function_unit "fmul" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpsqrt")) + 12 12) + +;; Compare instructions. +;; This controls RTL generation and register allocation. + +;; We generate RTL for comparisons and branches by having the cmpxx +;; patterns store away the operands. Then, the scc and bcc patterns +;; emit RTL for both the compare and the branch. +;; +;; We do this because we want to generate different code for an sne and +;; seq insn. In those cases, if the second operand of the compare is not +;; const0_rtx, we want to compute the xor of the two operands and test +;; it against zero. +;; +;; We start with the DEFINE_EXPANDs, then the DEFINE_INSNs to match +;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc +;; insns that actually require more than one machine instruction. + +;; Put cmpsi first among compare insns so it matches two CONST_INT operands. + +(define_expand "cmpsi" + [(set (reg:CC 100) + (compare:CC (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "arith_operand" "")))] + "" + " +{ + sparc_compare_op0 = operands[0]; + sparc_compare_op1 = operands[1]; + DONE; +}") + +(define_expand "cmpdi" + [(set (reg:CCX 100) + (compare:CCX (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "arith_double_operand" "")))] + "TARGET_ARCH64" + " +{ + sparc_compare_op0 = operands[0]; + sparc_compare_op1 = operands[1]; + DONE; +}") + +(define_expand "cmpsf" + ;; The 96 here isn't ever used by anyone. + [(set (reg:CCFP 96) + (compare:CCFP (match_operand:SF 0 "register_operand" "") + (match_operand:SF 1 "register_operand" "")))] + "TARGET_FPU" + " +{ + sparc_compare_op0 = operands[0]; + sparc_compare_op1 = operands[1]; + DONE; +}") + +(define_expand "cmpdf" + ;; The 96 here isn't ever used by anyone. + [(set (reg:CCFP 96) + (compare:CCFP (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "register_operand" "")))] + "TARGET_FPU" + " +{ + sparc_compare_op0 = operands[0]; + sparc_compare_op1 = operands[1]; + DONE; +}") + +(define_expand "cmptf" + ;; The 96 here isn't ever used by anyone. + [(set (reg:CCFP 96) + (compare:CCFP (match_operand:TF 0 "register_operand" "") + (match_operand:TF 1 "register_operand" "")))] + "TARGET_FPU" + " +{ + sparc_compare_op0 = operands[0]; + sparc_compare_op1 = operands[1]; + DONE; +}") + +;; Now the compare DEFINE_INSNs. + +(define_insn "*cmpsi_insn" + [(set (reg:CC 100) + (compare:CC (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "arith_operand" "rI")))] + "" + "cmp\\t%0, %1" + [(set_attr "type" "compare")]) + +(define_insn "*cmpdi_sp64" + [(set (reg:CCX 100) + (compare:CCX (match_operand:DI 0 "register_operand" "r") + (match_operand:DI 1 "arith_double_operand" "rHI")))] + "TARGET_ARCH64" + "cmp\\t%0, %1" + [(set_attr "type" "compare")]) + +(define_insn "*cmpsf_fpe" + [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c") + (compare:CCFPE (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_FPU" + "* +{ + if (TARGET_V9) + return \"fcmpes\\t%0, %1, %2\"; + return \"fcmpes\\t%1, %2\"; +}" + [(set_attr "type" "fpcmp")]) + +(define_insn "*cmpdf_fpe" + [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c") + (compare:CCFPE (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU" + "* +{ + if (TARGET_V9) + return \"fcmped\\t%0, %1, %2\"; + return \"fcmped\\t%1, %2\"; +}" + [(set_attr "type" "fpcmp")]) + +(define_insn "*cmptf_fpe" + [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c") + (compare:CCFPE (match_operand:TF 1 "register_operand" "e") + (match_operand:TF 2 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "* +{ + if (TARGET_V9) + return \"fcmpeq\\t%0, %1, %2\"; + return \"fcmpeq\\t%1, %2\"; +}" + [(set_attr "type" "fpcmp")]) + +(define_insn "*cmpsf_fp" + [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c") + (compare:CCFP (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_FPU" + "* +{ + if (TARGET_V9) + return \"fcmps\\t%0, %1, %2\"; + return \"fcmps\\t%1, %2\"; +}" + [(set_attr "type" "fpcmp")]) + +(define_insn "*cmpdf_fp" + [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c") + (compare:CCFP (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU" + "* +{ + if (TARGET_V9) + return \"fcmpd\\t%0, %1, %2\"; + return \"fcmpd\\t%1, %2\"; +}" + [(set_attr "type" "fpcmp")]) + +(define_insn "*cmptf_fp" + [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c") + (compare:CCFP (match_operand:TF 1 "register_operand" "e") + (match_operand:TF 2 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "* +{ + if (TARGET_V9) + return \"fcmpq\\t%0, %1, %2\"; + return \"fcmpq\\t%1, %2\"; +}" + [(set_attr "type" "fpcmp")]) + +;; Next come the scc insns. For seq, sne, sgeu, and sltu, we can do this +;; without jumps using the addx/subx instructions. For seq/sne on v9 we use +;; the same code as v8 (the addx/subx method has more applications). The +;; exception to this is "reg != 0" which can be done in one instruction on v9 +;; (so we do it). For the rest, on v9 we use conditional moves; on v8, we do +;; branches. + +;; Seq_special[_xxx] and sne_special[_xxx] clobber the CC reg, because they +;; generate addcc/subcc instructions. + +(define_expand "seqsi_special" + [(set (match_dup 3) + (xor:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "register_operand" ""))) + (parallel [(set (match_operand:SI 0 "register_operand" "") + (eq:SI (match_dup 3) (const_int 0))) + (clobber (reg:CC 100))])] + "! TARGET_LIVE_G0" + "{ operands[3] = gen_reg_rtx (SImode); }") + +(define_expand "seqdi_special" + [(set (match_dup 3) + (xor:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (set (match_operand:DI 0 "register_operand" "") + (eq:DI (match_dup 3) (const_int 0)))] + "TARGET_ARCH64" + "{ operands[3] = gen_reg_rtx (DImode); }") + +(define_expand "snesi_special" + [(set (match_dup 3) + (xor:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "register_operand" ""))) + (parallel [(set (match_operand:SI 0 "register_operand" "") + (ne:SI (match_dup 3) (const_int 0))) + (clobber (reg:CC 100))])] + "! TARGET_LIVE_G0" + "{ operands[3] = gen_reg_rtx (SImode); }") + +(define_expand "snedi_special" + [(set (match_dup 3) + (xor:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (set (match_operand:DI 0 "register_operand" "") + (ne:DI (match_dup 3) (const_int 0)))] + "TARGET_ARCH64" + "{ operands[3] = gen_reg_rtx (DImode); }") + +(define_expand "seqdi_special_trunc" + [(set (match_dup 3) + (xor:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (set (match_operand:SI 0 "register_operand" "") + (eq:SI (match_dup 3) (const_int 0)))] + "TARGET_ARCH64" + "{ operands[3] = gen_reg_rtx (DImode); }") + +(define_expand "snedi_special_trunc" + [(set (match_dup 3) + (xor:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (set (match_operand:SI 0 "register_operand" "") + (ne:SI (match_dup 3) (const_int 0)))] + "TARGET_ARCH64" + "{ operands[3] = gen_reg_rtx (DImode); }") + +(define_expand "seqsi_special_extend" + [(set (match_dup 3) + (xor:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "register_operand" ""))) + (parallel [(set (match_operand:DI 0 "register_operand" "") + (eq:DI (match_dup 3) (const_int 0))) + (clobber (reg:CC 100))])] + "TARGET_ARCH64" + "{ operands[3] = gen_reg_rtx (SImode); }") + +(define_expand "snesi_special_extend" + [(set (match_dup 3) + (xor:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "register_operand" ""))) + (parallel [(set (match_operand:DI 0 "register_operand" "") + (ne:DI (match_dup 3) (const_int 0))) + (clobber (reg:CC 100))])] + "TARGET_ARCH64" + "{ operands[3] = gen_reg_rtx (SImode); }") + +;; ??? v9: Operand 0 needs a mode, so SImode was chosen. +;; However, the code handles both SImode and DImode. +(define_expand "seq" + [(set (match_operand:SI 0 "intreg_operand" "") + (eq:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (GET_MODE (sparc_compare_op0) == SImode) + { + rtx pat; + + if (GET_MODE (operands[0]) == SImode) + pat = gen_seqsi_special (operands[0], sparc_compare_op0, + sparc_compare_op1); + else if (! TARGET_ARCH64) + FAIL; + else + pat = gen_seqsi_special_extend (operands[0], sparc_compare_op0, + sparc_compare_op1); + emit_insn (pat); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == DImode) + { + rtx pat; + + if (! TARGET_ARCH64) + FAIL; + else if (GET_MODE (operands[0]) == SImode) + pat = gen_seqdi_special_trunc (operands[0], sparc_compare_op0, + sparc_compare_op1); + else + pat = gen_seqdi_special (operands[0], sparc_compare_op0, + sparc_compare_op1); + emit_insn (pat); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ); + emit_insn (gen_sne (operands[0])); + DONE; + } + else if (TARGET_V9) + { + if (gen_v9_scc (EQ, operands)) + DONE; + /* fall through */ + } + FAIL; +}") + +;; ??? v9: Operand 0 needs a mode, so SImode was chosen. +;; However, the code handles both SImode and DImode. +(define_expand "sne" + [(set (match_operand:SI 0 "intreg_operand" "") + (ne:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (GET_MODE (sparc_compare_op0) == SImode) + { + rtx pat; + + if (GET_MODE (operands[0]) == SImode) + pat = gen_snesi_special (operands[0], sparc_compare_op0, + sparc_compare_op1); + else if (! TARGET_ARCH64) + FAIL; + else + pat = gen_snesi_special_extend (operands[0], sparc_compare_op0, + sparc_compare_op1); + emit_insn (pat); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == DImode) + { + rtx pat; + + if (! TARGET_ARCH64) + FAIL; + else if (GET_MODE (operands[0]) == SImode) + pat = gen_snedi_special_trunc (operands[0], sparc_compare_op0, + sparc_compare_op1); + else + pat = gen_snedi_special (operands[0], sparc_compare_op0, + sparc_compare_op1); + emit_insn (pat); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE); + emit_insn (gen_sne (operands[0])); + DONE; + } + else if (TARGET_V9) + { + if (gen_v9_scc (NE, operands)) + DONE; + /* fall through */ + } + FAIL; +}") + +(define_expand "sgt" + [(set (match_operand:SI 0 "intreg_operand" "") + (gt:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT); + emit_insn (gen_sne (operands[0])); + DONE; + } + else if (TARGET_V9) + { + if (gen_v9_scc (GT, operands)) + DONE; + /* fall through */ + } + FAIL; +}") + +(define_expand "slt" + [(set (match_operand:SI 0 "intreg_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT); + emit_insn (gen_sne (operands[0])); + DONE; + } + else if (TARGET_V9) + { + if (gen_v9_scc (LT, operands)) + DONE; + /* fall through */ + } + FAIL; +}") + +(define_expand "sge" + [(set (match_operand:SI 0 "intreg_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE); + emit_insn (gen_sne (operands[0])); + DONE; + } + else if (TARGET_V9) + { + if (gen_v9_scc (GE, operands)) + DONE; + /* fall through */ + } + FAIL; +}") + +(define_expand "sle" + [(set (match_operand:SI 0 "intreg_operand" "") + (le:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE); + emit_insn (gen_sne (operands[0])); + DONE; + } + else if (TARGET_V9) + { + if (gen_v9_scc (LE, operands)) + DONE; + /* fall through */ + } + FAIL; +}") + +(define_expand "sgtu" + [(set (match_operand:SI 0 "intreg_operand" "") + (gtu:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (! TARGET_V9) + { + rtx tem, pat; + + /* We can do ltu easily, so if both operands are registers, swap them and + do a LTU. */ + if ((GET_CODE (sparc_compare_op0) == REG + || GET_CODE (sparc_compare_op0) == SUBREG) + && (GET_CODE (sparc_compare_op1) == REG + || GET_CODE (sparc_compare_op1) == SUBREG)) + { + tem = sparc_compare_op0; + sparc_compare_op0 = sparc_compare_op1; + sparc_compare_op1 = tem; + pat = gen_sltu (operands[0]); + if (pat == NULL_RTX) + FAIL; + emit_insn (pat); + DONE; + } + } + else + { + if (gen_v9_scc (GTU, operands)) + DONE; + } + FAIL; +}") + +(define_expand "sltu" + [(set (match_operand:SI 0 "intreg_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (TARGET_V9) + { + if (gen_v9_scc (LTU, operands)) + DONE; + } + operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "sgeu" + [(set (match_operand:SI 0 "intreg_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (TARGET_V9) + { + if (gen_v9_scc (GEU, operands)) + DONE; + } + operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "sleu" + [(set (match_operand:SI 0 "intreg_operand" "") + (leu:SI (match_dup 1) (const_int 0)))] + "! TARGET_LIVE_G0" + " +{ + if (! TARGET_V9) + { + rtx tem, pat; + + /* We can do geu easily, so if both operands are registers, swap them and + do a GEU. */ + if ((GET_CODE (sparc_compare_op0) == REG + || GET_CODE (sparc_compare_op0) == SUBREG) + && (GET_CODE (sparc_compare_op1) == REG + || GET_CODE (sparc_compare_op1) == SUBREG)) + { + tem = sparc_compare_op0; + sparc_compare_op0 = sparc_compare_op1; + sparc_compare_op1 = tem; + pat = gen_sgeu (operands[0]); + if (pat == NULL_RTX) + FAIL; + emit_insn (pat); + DONE; + } + } + else + { + if (gen_v9_scc (LEU, operands)) + DONE; + } + FAIL; +}") + +;; Now the DEFINE_INSNs for the scc cases. + +;; The SEQ and SNE patterns are special because they can be done +;; without any branching and do not involve a COMPARE. We want +;; them to always use the splitz below so the results can be +;; scheduled. + +(define_insn "*snesi_zero" + [(set (match_operand:SI 0 "register_operand" "=r") + (ne:SI (match_operand:SI 1 "register_operand" "r") + (const_int 0))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (ne:SI (match_operand:SI 1 "register_operand" "") + (const_int 0))) + (clobber (reg:CC 100))] + "" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))] + "") + +(define_insn "*neg_snesi_zero" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r") + (const_int 0)))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "") + (const_int 0)))) + (clobber (reg:CC 100))] + "" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] + "") + +(define_insn "*snesi_zero_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (ne:DI (match_operand:SI 1 "register_operand" "r") + (const_int 0))) + (clobber (reg:CC 100))] + "TARGET_ARCH64" + "#" + [(set_attr "type" "unary") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ne:DI (match_operand:SI 1 "register_operand" "") + (const_int 0))) + (clobber (reg:CC 100))] + "TARGET_ARCH64" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0) + (const_int 0)) + (ltu:SI (reg:CC_NOOV 100) + (const_int 0)))))] + "") + +(define_insn "*snedi_zero" + [(set (match_operand:DI 0 "register_operand" "=&r") + (ne:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] + "TARGET_ARCH64" + "#" + [(set_attr "type" "cmove") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ne:DI (match_operand:DI 1 "register_operand" "") + (const_int 0)))] + "TARGET_ARCH64" + [(set (match_dup 0) (const_int 0)) + (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1) + (const_int 0)) + (const_int 1) + (match_dup 0)))] + "") + +(define_insn "*neg_snedi_zero" + [(set (match_operand:DI 0 "register_operand" "=&r") + (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0))))] + "TARGET_ARCH64" + "#" + [(set_attr "type" "cmove") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "") + (const_int 0))))] + "TARGET_ARCH64" + [(set (match_dup 0) (const_int 0)) + (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1) + (const_int 0)) + (const_int -1) + (match_dup 0)))] + "") + +(define_insn "*snedi_zero_trunc" + [(set (match_operand:SI 0 "register_operand" "=&r") + (ne:SI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] + "TARGET_ARCH64" + "#" + [(set_attr "type" "cmove") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (ne:SI (match_operand:DI 1 "register_operand" "") + (const_int 0)))] + "TARGET_ARCH64" + [(set (match_dup 0) (const_int 0)) + (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1) + (const_int 0)) + (const_int 1) + (match_dup 0)))] + "") + +(define_insn "*seqsi_zero" + [(set (match_operand:SI 0 "register_operand" "=r") + (eq:SI (match_operand:SI 1 "register_operand" "r") + (const_int 0))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (eq:SI (match_operand:SI 1 "register_operand" "") + (const_int 0))) + (clobber (reg:CC 100))] + "" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))] + "") + +(define_insn "*neg_seqsi_zero" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r") + (const_int 0)))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "") + (const_int 0)))) + (clobber (reg:CC 100))] + "" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))] + "") + +(define_insn "*seqsi_zero_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (eq:DI (match_operand:SI 1 "register_operand" "r") + (const_int 0))) + (clobber (reg:CC 100))] + "TARGET_ARCH64" + "#" + [(set_attr "type" "unary") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (eq:DI (match_operand:SI 1 "register_operand" "") + (const_int 0))) + (clobber (reg:CC 100))] + "TARGET_ARCH64" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0) + (const_int -1)) + (ltu:SI (reg:CC_NOOV 100) + (const_int 0)))))] + "") + +(define_insn "*seqdi_zero" + [(set (match_operand:DI 0 "register_operand" "=&r") + (eq:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] + "TARGET_ARCH64" + "#" + [(set_attr "type" "cmove") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (eq:DI (match_operand:DI 1 "register_operand" "") + (const_int 0)))] + "TARGET_ARCH64" + [(set (match_dup 0) (const_int 0)) + (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1) + (const_int 0)) + (const_int 1) + (match_dup 0)))] + "") + +(define_insn "*neg_seqdi_zero" + [(set (match_operand:DI 0 "register_operand" "=&r") + (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0))))] + "TARGET_ARCH64" + "#" + [(set_attr "type" "cmove") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "") + (const_int 0))))] + "TARGET_ARCH64" + [(set (match_dup 0) (const_int 0)) + (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1) + (const_int 0)) + (const_int -1) + (match_dup 0)))] + "") + +(define_insn "*seqdi_zero_trunc" + [(set (match_operand:SI 0 "register_operand" "=&r") + (eq:SI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] + "TARGET_ARCH64" + "#" + [(set_attr "type" "cmove") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (eq:SI (match_operand:DI 1 "register_operand" "") + (const_int 0)))] + "TARGET_ARCH64" + [(set (match_dup 0) (const_int 0)) + (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1) + (const_int 0)) + (const_int 1) + (match_dup 0)))] + "") + +;; We can also do (x + (i == 0)) and related, so put them in. +;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode +;; versions for v9. + +(define_insn "*x_plus_i_ne_0" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r") + (const_int 0)) + (match_operand:SI 2 "register_operand" "r"))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "") + (const_int 0)) + (match_operand:SI 2 "register_operand" ""))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) + (match_dup 2)))] + "") + +(define_insn "*x_minus_i_ne_0" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 2 "register_operand" "r") + (ne:SI (match_operand:SI 1 "register_operand" "r") + (const_int 0)))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_operand:SI 2 "register_operand" "") + (ne:SI (match_operand:SI 1 "register_operand" "") + (const_int 0)))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (minus:SI (match_dup 2) + (ltu:SI (reg:CC 100) (const_int 0))))] + "") + +(define_insn "*x_plus_i_eq_0" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r") + (const_int 0)) + (match_operand:SI 2 "register_operand" "r"))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "") + (const_int 0)) + (match_operand:SI 2 "register_operand" ""))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0)) + (match_dup 2)))] + "") + +(define_insn "*x_minus_i_eq_0" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 2 "register_operand" "r") + (eq:SI (match_operand:SI 1 "register_operand" "r") + (const_int 0)))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_operand:SI 2 "register_operand" "") + (eq:SI (match_operand:SI 1 "register_operand" "") + (const_int 0)))) + (clobber (reg:CC 100))] + "! TARGET_LIVE_G0" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) + (const_int 0))) + (set (match_dup 0) (minus:SI (match_dup 2) + (geu:SI (reg:CC 100) (const_int 0))))] + "") + +;; We can also do GEU and LTU directly, but these operate after a compare. +;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode +;; versions for v9. + +(define_insn "*sltu_insn" + [(set (match_operand:SI 0 "register_operand" "=r") + (ltu:SI (reg:CC 100) (const_int 0)))] + "! TARGET_LIVE_G0" + "addx\\t%%g0, 0, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*neg_sltu_insn" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] + "! TARGET_LIVE_G0" + "subx\\t%%g0, 0, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +;; ??? Combine should canonicalize these next two to the same pattern. +(define_insn "*neg_sltu_minus_x" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0))) + (match_operand:SI 1 "arith_operand" "rI")))] + "! TARGET_LIVE_G0" + "subx\\t%%g0, %1, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*neg_sltu_plus_x" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) + (match_operand:SI 1 "arith_operand" "rI"))))] + "! TARGET_LIVE_G0" + "subx\\t%%g0, %1, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*sgeu_insn" + [(set (match_operand:SI 0 "register_operand" "=r") + (geu:SI (reg:CC 100) (const_int 0)))] + "! TARGET_LIVE_G0" + "subx\\t%%g0, -1, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*neg_sgeu_insn" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (geu:SI (reg:CC 100) (const_int 0))))] + "! TARGET_LIVE_G0" + "addx\\t%%g0, -1, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in. +;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode +;; versions for v9. + +(define_insn "*sltu_plus_x" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) + (match_operand:SI 1 "arith_operand" "rI")))] + "! TARGET_LIVE_G0" + "addx\\t%%g0, %1, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*sltu_plus_x_plus_y" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) + (plus:SI (match_operand:SI 1 "arith_operand" "%r") + (match_operand:SI 2 "arith_operand" "rI"))))] + "" + "addx\\t%1, %2, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*x_minus_sltu" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 1 "register_operand" "r") + (ltu:SI (reg:CC 100) (const_int 0))))] + "" + "subx\\t%1, 0, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +;; ??? Combine should canonicalize these next two to the same pattern. +(define_insn "*x_minus_y_minus_sltu" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC 100) (const_int 0))))] + "" + "subx\\t%r1, %2, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*x_minus_sltu_plus_y" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) + (match_operand:SI 2 "arith_operand" "rI"))))] + "" + "subx\\t%r1, %2, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*sgeu_plus_x" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (geu:SI (reg:CC 100) (const_int 0)) + (match_operand:SI 1 "register_operand" "r")))] + "" + "subx\\t%1, -1, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*x_minus_sgeu" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 1 "register_operand" "r") + (geu:SI (reg:CC 100) (const_int 0))))] + "" + "addx\\t%1, -1, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operator:SI 2 "noov_compare_op" + [(match_operand 1 "icc_or_fcc_reg_operand" "") + (const_int 0)]))] + ;; 32 bit LTU/GEU are better implemented using addx/subx + "TARGET_V9 && REGNO (operands[1]) == SPARC_ICC_REG + && (GET_MODE (operands[1]) == CCXmode + || (GET_CODE (operands[2]) != LTU && GET_CODE (operands[2]) != GEU))" + [(set (match_dup 0) (const_int 0)) + (set (match_dup 0) + (if_then_else:SI (match_op_dup:SI 2 [(match_dup 1) (const_int 0)]) + (const_int 1) + (match_dup 0)))] + "") + + +;; These control RTL generation for conditional jump insns + +;; The quad-word fp compare library routines all return nonzero to indicate +;; true, which is different from the equivalent libgcc routines, so we must +;; handle them specially here. + +(define_expand "beq" + [(set (pc) + (if_then_else (eq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode) + { + emit_v9_brxx_insn (EQ, sparc_compare_op0, operands[0]); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ); + emit_jump_insn (gen_bne (operands[0])); + DONE; + } + operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "bne" + [(set (pc) + (if_then_else (ne (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode) + { + emit_v9_brxx_insn (NE, sparc_compare_op0, operands[0]); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE); + emit_jump_insn (gen_bne (operands[0])); + DONE; + } + operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "bgt" + [(set (pc) + (if_then_else (gt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode) + { + emit_v9_brxx_insn (GT, sparc_compare_op0, operands[0]); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT); + emit_jump_insn (gen_bne (operands[0])); + DONE; + } + operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "bgtu" + [(set (pc) + (if_then_else (gtu (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "blt" + [(set (pc) + (if_then_else (lt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode) + { + emit_v9_brxx_insn (LT, sparc_compare_op0, operands[0]); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT); + emit_jump_insn (gen_bne (operands[0])); + DONE; + } + operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "bltu" + [(set (pc) + (if_then_else (ltu (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode) + { + emit_v9_brxx_insn (GE, sparc_compare_op0, operands[0]); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE); + emit_jump_insn (gen_bne (operands[0])); + DONE; + } + operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "ble" + [(set (pc) + (if_then_else (le (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode) + { + emit_v9_brxx_insn (LE, sparc_compare_op0, operands[0]); + DONE; + } + else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) + { + emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE); + emit_jump_insn (gen_bne (operands[0])); + DONE; + } + operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1); +}") + +(define_expand "bleu" + [(set (pc) + (if_then_else (leu (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1); +}") + +;; Now match both normal and inverted jump. + +;; XXX fpcmp nop braindamage +(define_insn "*normal_branch" + [(set (pc) + (if_then_else (match_operator 0 "noov_compare_op" + [(reg 100) (const_int 0)]) + (label_ref (match_operand 1 "" "")) + (pc)))] + "" + "* +{ + return output_cbranch (operands[0], 1, 0, + final_sequence && INSN_ANNULLED_BRANCH_P (insn), + ! final_sequence, insn); +}" + [(set_attr "type" "branch")]) + +;; XXX fpcmp nop braindamage +(define_insn "*inverted_branch" + [(set (pc) + (if_then_else (match_operator 0 "noov_compare_op" + [(reg 100) (const_int 0)]) + (pc) + (label_ref (match_operand 1 "" ""))))] + "" + "* +{ + return output_cbranch (operands[0], 1, 1, + final_sequence && INSN_ANNULLED_BRANCH_P (insn), + ! final_sequence, insn); +}" + [(set_attr "type" "branch")]) + +;; XXX fpcmp nop braindamage +(define_insn "*normal_fp_branch" + [(set (pc) + (if_then_else (match_operator 1 "comparison_operator" + [(match_operand:CCFP 0 "fcc_reg_operand" "c") + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "" + "* +{ + return output_cbranch (operands[1], 2, 0, + final_sequence && INSN_ANNULLED_BRANCH_P (insn), + ! final_sequence, insn); +}" + [(set_attr "type" "branch")]) + +;; XXX fpcmp nop braindamage +(define_insn "*inverted_fp_branch" + [(set (pc) + (if_then_else (match_operator 1 "comparison_operator" + [(match_operand:CCFP 0 "fcc_reg_operand" "c") + (const_int 0)]) + (pc) + (label_ref (match_operand 2 "" ""))))] + "" + "* +{ + return output_cbranch (operands[1], 2, 1, + final_sequence && INSN_ANNULLED_BRANCH_P (insn), + ! final_sequence, insn); +}" + [(set_attr "type" "branch")]) + +;; XXX fpcmp nop braindamage +(define_insn "*normal_fpe_branch" + [(set (pc) + (if_then_else (match_operator 1 "comparison_operator" + [(match_operand:CCFPE 0 "fcc_reg_operand" "c") + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "" + "* +{ + return output_cbranch (operands[1], 2, 0, + final_sequence && INSN_ANNULLED_BRANCH_P (insn), + ! final_sequence, insn); +}" + [(set_attr "type" "branch")]) + +;; XXX fpcmp nop braindamage +(define_insn "*inverted_fpe_branch" + [(set (pc) + (if_then_else (match_operator 1 "comparison_operator" + [(match_operand:CCFPE 0 "fcc_reg_operand" "c") + (const_int 0)]) + (pc) + (label_ref (match_operand 2 "" ""))))] + "" + "* +{ + return output_cbranch (operands[1], 2, 1, + final_sequence && INSN_ANNULLED_BRANCH_P (insn), + ! final_sequence, insn); +}" + [(set_attr "type" "branch")]) + +;; Sparc V9-specific jump insns. None of these are guaranteed to be +;; in the architecture. + +;; There are no 32 bit brreg insns. + +;; XXX +(define_insn "*normal_int_branch_sp64" + [(set (pc) + (if_then_else (match_operator 0 "v9_regcmp_op" + [(match_operand:DI 1 "register_operand" "r") + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "TARGET_ARCH64" + "* +{ + return output_v9branch (operands[0], 1, 2, 0, + final_sequence && INSN_ANNULLED_BRANCH_P (insn), + ! final_sequence, insn); +}" + [(set_attr "type" "branch")]) + +;; XXX +(define_insn "*inverted_int_branch_sp64" + [(set (pc) + (if_then_else (match_operator 0 "v9_regcmp_op" + [(match_operand:DI 1 "register_operand" "r") + (const_int 0)]) + (pc) + (label_ref (match_operand 2 "" ""))))] + "TARGET_ARCH64" + "* +{ + return output_v9branch (operands[0], 1, 2, 1, + final_sequence && INSN_ANNULLED_BRANCH_P (insn), + ! final_sequence, insn); +}" + [(set_attr "type" "branch")]) + +;; Load program counter insns. + +(define_insn "get_pc" + [(clobber (reg:SI 15)) + (set (match_operand 0 "register_operand" "=r") + (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))] + "flag_pic && REGNO (operands[0]) == 23" + "sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0" + [(set_attr "length" "3")]) + +;; Currently unused... +;; (define_insn "get_pc_via_rdpc" +;; [(set (match_operand 0 "register_operand" "=r") (pc))] +;; "TARGET_V9" +;; "rd\\t%%pc, %0" +;; [(set_attr "type" "move")]) + + +;; Move instructions + +(define_expand "movqi" + [(set (match_operand:QI 0 "general_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + /* Working with CONST_INTs is easier, so convert + a double if needed. */ + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xff); + } + else if (GET_CODE (operands[1]) == CONST_INT) + { + /* And further, we know for all QI cases that only the + low byte is significant, which we can always process + in a single insn. So mask it now. */ + operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); + } + + /* Handle sets of MEM first. */ + if (GET_CODE (operands[0]) == MEM) + { + /* This checks TARGET_LIVE_G0 for us. */ + if (reg_or_0_operand (operands[1], QImode)) + goto movqi_is_ok; + + if (! reload_in_progress) + { + operands[0] = validize_mem (operands[0]); + operands[1] = force_reg (QImode, operands[1]); + } + } + + /* Fixup PIC cases. */ + if (flag_pic) + { + if (CONSTANT_P (operands[1]) + && pic_address_needs_scratch (operands[1])) + operands[1] = legitimize_pic_address (operands[1], QImode, 0); + + if (symbolic_operand (operands[1], QImode)) + { + operands[1] = legitimize_pic_address (operands[1], + QImode, + (reload_in_progress ? + operands[0] : + NULL_RTX)); + goto movqi_is_ok; + } + } + + /* All QI constants require only one insn, so proceed. */ + + movqi_is_ok: + ; +}") + +(define_insn "*movqi_insn" + [(set (match_operand:QI 0 "general_operand" "=r,r,m") + (match_operand:QI 1 "input_operand" "rI,m,rJ"))] + "(register_operand (operands[0], QImode) + || reg_or_0_operand (operands[1], QImode))" + "@ + mov\\t%1, %0 + ldub\\t%1, %0 + stb\\t%r1, %0" + [(set_attr "type" "move,load,store") + (set_attr "length" "1")]) + +(define_expand "movhi" + [(set (match_operand:HI 0 "general_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" + " +{ + /* Working with CONST_INTs is easier, so convert + a double if needed. */ + if (GET_CODE (operands[1]) == CONST_DOUBLE) + operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); + + /* Handle sets of MEM first. */ + if (GET_CODE (operands[0]) == MEM) + { + /* This checks TARGET_LIVE_G0 for us. */ + if (reg_or_0_operand (operands[1], HImode)) + goto movhi_is_ok; + + if (! reload_in_progress) + { + operands[0] = validize_mem (operands[0]); + operands[1] = force_reg (HImode, operands[1]); + } + } + + /* Fixup PIC cases. */ + if (flag_pic) + { + if (CONSTANT_P (operands[1]) + && pic_address_needs_scratch (operands[1])) + operands[1] = legitimize_pic_address (operands[1], HImode, 0); + + if (symbolic_operand (operands[1], HImode)) + { + operands[1] = legitimize_pic_address (operands[1], + HImode, + (reload_in_progress ? + operands[0] : + NULL_RTX)); + goto movhi_is_ok; + } + } + + /* This makes sure we will not get rematched due to splittage. */ + if (! CONSTANT_P (operands[1]) || input_operand (operands[1], HImode)) + ; + else if (CONSTANT_P (operands[1]) + && GET_CODE (operands[1]) != HIGH + && GET_CODE (operands[1]) != LO_SUM) + { + sparc_emit_set_const32 (operands[0], operands[1]); + DONE; + } + movhi_is_ok: + ; +}") + +(define_insn "*movhi_const64_special" + [(set (match_operand:HI 0 "register_operand" "=r") + (match_operand:HI 1 "const64_high_operand" ""))] + "TARGET_ARCH64" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*movhi_insn" + [(set (match_operand:HI 0 "general_operand" "=r,r,r,m") + (match_operand:HI 1 "input_operand" "rI,K,m,rJ"))] + "(register_operand (operands[0], HImode) + || reg_or_0_operand (operands[1], HImode))" + "@ + mov\\t%1, %0 + sethi\\t%%hi(%a1), %0 + lduh\\t%1, %0 + sth\\t%r1, %0" + [(set_attr "type" "move,move,load,store") + (set_attr "length" "1")]) + +;; We always work with constants here. +(define_insn "*movhi_lo_sum" + [(set (match_operand:HI 0 "register_operand" "=r") + (ior:HI (match_operand:HI 1 "arith_operand" "%r") + (match_operand:HI 2 "arith_operand" "I")))] + "" + "or\\t%1, %2, %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_expand "movsi" + [(set (match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "general_operand" ""))] + "" + " +{ + /* Working with CONST_INTs is easier, so convert + a double if needed. */ + if (GET_CODE (operands[1]) == CONST_DOUBLE) + operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); + + /* Handle sets of MEM first. */ + if (GET_CODE (operands[0]) == MEM) + { + /* This checks TARGET_LIVE_G0 for us. */ + if (reg_or_0_operand (operands[1], SImode)) + goto movsi_is_ok; + + if (! reload_in_progress) + { + operands[0] = validize_mem (operands[0]); + operands[1] = force_reg (SImode, operands[1]); + } + } + + /* Fixup PIC cases. */ + if (flag_pic) + { + if (CONSTANT_P (operands[1]) + && pic_address_needs_scratch (operands[1])) + operands[1] = legitimize_pic_address (operands[1], SImode, 0); + + if (GET_CODE (operands[1]) == LABEL_REF) + { + /* shit */ + emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1])); + DONE; + } + + if (symbolic_operand (operands[1], SImode)) + { + operands[1] = legitimize_pic_address (operands[1], + SImode, + (reload_in_progress ? + operands[0] : + NULL_RTX)); + goto movsi_is_ok; + } + } + + /* If we are trying to toss an integer constant into the + FPU registers, force it into memory. */ + if (GET_CODE (operands[0]) == REG + && REGNO (operands[0]) >= SPARC_FIRST_FP_REG + && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG + && CONSTANT_P (operands[1])) + operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]), + operands[1])); + + /* This makes sure we will not get rematched due to splittage. */ + if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode)) + ; + else if (CONSTANT_P (operands[1]) + && GET_CODE (operands[1]) != HIGH + && GET_CODE (operands[1]) != LO_SUM) + { + sparc_emit_set_const32 (operands[0], operands[1]); + DONE; + } + movsi_is_ok: + ; +}") + +;; Special LIVE_G0 pattern to obtain zero in a register. +(define_insn "*movsi_zero_liveg0" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "zero_operand" "J"))] + "TARGET_LIVE_G0" + "and\\t%0, 0, %0" + [(set_attr "type" "binary") + (set_attr "length" "1")]) + +;; This is needed to show CSE exactly which bits are set +;; in a 64-bit register by sethi instructions. +(define_insn "*movsi_const64_special" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "const64_high_operand" ""))] + "TARGET_ARCH64" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*movsi_insn" + [(set (match_operand:SI 0 "general_operand" "=r,f,r,r,r,f,m,m,d") + (match_operand:SI 1 "input_operand" "rI,!f,K,J,m,!m,rJ,!f,J"))] + "(register_operand (operands[0], SImode) + || reg_or_0_operand (operands[1], SImode))" + "@ + mov\\t%1, %0 + fmovs\\t%1, %0 + sethi\\t%%hi(%a1), %0 + clr\\t%0 + ld\\t%1, %0 + ld\\t%1, %0 + st\\t%r1, %0 + st\\t%1, %0 + fzeros\\t%0" + [(set_attr "type" "move,fpmove,move,move,load,fpload,store,fpstore,fpmove") + (set_attr "length" "1")]) + +(define_insn "*movsi_lo_sum" + [(set (match_operand:SI 0 "register_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "in")))] + "" + "or\\t%1, %%lo(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "*movsi_high" + [(set (match_operand:SI 0 "register_operand" "=r") + (high:SI (match_operand:SI 1 "immediate_operand" "in")))] + "" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC +;; so that CSE won't optimize the address computation away. +(define_insn "movsi_lo_sum_pic" + [(set (match_operand:SI 0 "register_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "register_operand" "r") + (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))] + "flag_pic" + "or\\t%1, %%lo(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "movsi_high_pic" + [(set (match_operand:SI 0 "register_operand" "=r") + (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))] + "flag_pic && check_pic (1)" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_expand "movsi_pic_label_ref" + [(set (match_dup 3) (high:SI + (unspec:SI [(match_operand:SI 1 "label_ref_operand" "") + (match_dup 2)] 5))) + (set (match_dup 4) (lo_sum:SI (match_dup 3) + (unspec:SI [(match_dup 1) (match_dup 2)] 5))) + (set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_dup 5) (match_dup 4)))] + "flag_pic" + " +{ + current_function_uses_pic_offset_table = 1; + operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); + operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_reg_rtx (SImode); + operands[5] = pic_offset_table_rtx; +}") + +(define_insn "*movsi_high_pic_label_ref" + [(set (match_operand:SI 0 "register_operand" "=r") + (high:SI + (unspec:SI [(match_operand:SI 1 "label_ref_operand" "") + (match_operand:SI 2 "" "")] 5)))] + "flag_pic" + "sethi\\t%%hi(%a2-(%a1-.)), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*movsi_lo_sum_pic_label_ref" + [(set (match_operand:SI 0 "register_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "register_operand" "r") + (unspec:SI [(match_operand:SI 2 "label_ref_operand" "") + (match_operand:SI 3 "" "")] 5)))] + "flag_pic" + "or\\t%1, %%lo(%a3-(%a2-.)), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_expand "movdi" + [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + " +{ + /* Where possible, convert CONST_DOUBLE into a CONST_INT. */ + if (GET_CODE (operands[1]) == CONST_DOUBLE +#if HOST_BITS_PER_WIDE_INT == 32 + && ((CONST_DOUBLE_HIGH (operands[1]) == 0 + && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) + || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff + && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0)) +#endif + ) + operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); + + /* Handle MEM cases first. */ + if (GET_CODE (operands[0]) == MEM) + { + /* If it's a REG, we can always do it. + The const zero case is more complex, on v9 + we can always perform it. */ + if (register_operand (operands[1], DImode) + || (TARGET_ARCH64 + && (operands[1] == const0_rtx))) + goto movdi_is_ok; + + if (! reload_in_progress) + { + operands[0] = validize_mem (operands[0]); + operands[1] = force_reg (DImode, operands[1]); + } + } + + if (flag_pic) + { + if (CONSTANT_P (operands[1]) + && pic_address_needs_scratch (operands[1])) + operands[1] = legitimize_pic_address (operands[1], DImode, 0); + + if (GET_CODE (operands[1]) == LABEL_REF) + { + if (! TARGET_ARCH64) + abort (); + emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1])); + DONE; + } + + if (symbolic_operand (operands[1], DImode)) + { + operands[1] = legitimize_pic_address (operands[1], + DImode, + (reload_in_progress ? + operands[0] : + NULL_RTX)); + goto movdi_is_ok; + } + } + + /* If we are trying to toss an integer constant into the + FPU registers, force it into memory. */ + if (GET_CODE (operands[0]) == REG + && REGNO (operands[0]) >= SPARC_FIRST_FP_REG + && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG + && CONSTANT_P (operands[1])) + operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]), + operands[1])); + + /* This makes sure we will not get rematched due to splittage. */ + if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode)) + ; + else if (TARGET_ARCH64 + && CONSTANT_P (operands[1]) + && GET_CODE (operands[1]) != HIGH + && GET_CODE (operands[1]) != LO_SUM) + { + sparc_emit_set_const64 (operands[0], operands[1]); + DONE; + } + + movdi_is_ok: + ; +}") + +;; Be careful, fmovd does not exist when !arch64. +;; We match MEM moves directly when we have correct even +;; numbered registers, but fall into splits otherwise. +;; The constraint ordering here is really important to +;; avoid insane problems in reload, especially for patterns +;; of the form: +;; +;; (set (mem:DI (plus:SI (reg:SI 30 %fp) +;; (const_int -5016))) +;; (reg:DI 2 %g2)) +;; +(define_insn "*movdi_insn_sp32" + [(set (match_operand:DI 0 "general_operand" "=T,U,o,r,r,r,?T,?f,?f,?o,?f") + (match_operand:DI 1 "input_operand" "U,T,r,o,i,r,f,T,o,f,f"))] + "! TARGET_ARCH64 && + (register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "@ + std\\t%1, %0 + ldd\\t%1, %0 + # + # + # + # + std\\t%1, %0 + ldd\\t%1, %0 + # + # + #" + [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*") + (set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")]) + +;; The following are generated by sparc_emit_set_const64 +(define_insn "*movdi_sp64_dbl" + [(set (match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "const64_operand" ""))] + "(TARGET_ARCH64 + && HOST_BITS_PER_WIDE_INT != 64)" + "mov\\t%1, %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +;; This is needed to show CSE exactly which bits are set +;; in a 64-bit register by sethi instructions. +(define_insn "*movdi_const64_special" + [(set (match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "const64_high_operand" ""))] + "TARGET_ARCH64" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*movdi_insn_sp64" + [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,m,?e,?e,?m,b") + (match_operand:DI 1 "input_operand" "rI,K,J,m,rJ,e,m,e,J"))] + "TARGET_ARCH64 && + (register_operand (operands[0], DImode) + || reg_or_0_operand (operands[1], DImode))" + "@ + mov\\t%1, %0 + sethi\\t%%hi(%a1), %0 + clr\\t%0 + ldx\\t%1, %0 + stx\\t%r1, %0 + fmovd\\t%1, %0 + ldd\\t%1, %0 + std\\t%1, %0 + fzero\\t%0" + [(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore,fpmove") + (set_attr "length" "1")]) + +(define_expand "movdi_pic_label_ref" + [(set (match_dup 3) (high:DI + (unspec:DI [(match_operand:DI 1 "label_ref_operand" "") + (match_dup 2)] 5))) + (set (match_dup 4) (lo_sum:DI (match_dup 3) + (unspec:DI [(match_dup 1) (match_dup 2)] 5))) + (set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_dup 5) (match_dup 4)))] + "TARGET_ARCH64 && flag_pic" + " +{ + current_function_uses_pic_offset_table = 1; + operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); + operands[3] = gen_reg_rtx (DImode); + operands[4] = gen_reg_rtx (DImode); + operands[5] = pic_offset_table_rtx; +}") + +(define_insn "*movdi_high_pic_label_ref" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI + (unspec:DI [(match_operand:DI 1 "label_ref_operand" "") + (match_operand:DI 2 "" "")] 5)))] + "TARGET_ARCH64 && flag_pic" + "sethi\\t%%hi(%a2-(%a1-.)), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*movdi_lo_sum_pic_label_ref" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (unspec:DI [(match_operand:DI 2 "label_ref_operand" "") + (match_operand:DI 3 "" "")] 5)))] + "TARGET_ARCH64 && flag_pic" + "or\\t%1, %%lo(%a3-(%a2-.)), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +;; Sparc-v9 code model support insns. See sparc_emit_set_symbolic_const64 +;; in sparc.c to see what is going on here... PIC stuff comes first. + +(define_insn "movdi_lo_sum_pic" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))] + "TARGET_ARCH64 && flag_pic" + "or\\t%1, %%lo(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "movdi_high_pic" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))] + "TARGET_ARCH64 && flag_pic && check_pic (1)" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*sethi_di_medlow_embmedany_pic" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))] + "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)" + "sethi\\t%%lo(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*sethi_di_medlow" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (match_operand:DI 1 "symbolic_operand" "")))] + "TARGET_CM_MEDLOW && check_pic (1)" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*losum_di_medlow" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "symbolic_operand" "")))] + "TARGET_CM_MEDLOW" + "or\\t%1, %%lo(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "seth44" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))] + "TARGET_CM_MEDMID" + "sethi\\t%%h44(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "setm44" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))] + "TARGET_CM_MEDMID" + "or\\t%1, %%m44(%a2), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "setl44" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "symbolic_operand" "")))] + "TARGET_CM_MEDMID" + "or\\t%1, %%l44(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "sethh" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))] + "TARGET_CM_MEDANY" + "sethi\\t%%hh(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "setlm" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))] + "TARGET_CM_MEDANY" + "sethi\\t%%lm(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "sethm" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))] + "TARGET_CM_MEDANY" + "or\\t%1, %%hm(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "setlo" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "symbolic_operand" "")))] + "TARGET_CM_MEDANY" + "or\\t%1, %%lo(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "embmedany_sethi" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))] + "TARGET_CM_EMBMEDANY && check_pic (1)" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "embmedany_losum" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "data_segment_operand" "")))] + "TARGET_CM_EMBMEDANY" + "add\\t%1, %%lo(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "embmedany_brsum" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))] + "TARGET_CM_EMBMEDANY" + "add\\t%1, %_, %0" + [(set_attr "length" "1")]) + +(define_insn "embmedany_textuhi" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))] + "TARGET_CM_EMBMEDANY && check_pic (1)" + "sethi\\t%%uhi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "embmedany_texthi" + [(set (match_operand:DI 0 "register_operand" "=r") + (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))] + "TARGET_CM_EMBMEDANY && check_pic (1)" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "embmedany_textulo" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))] + "TARGET_CM_EMBMEDANY" + "or\\t%1, %%ulo(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "embmedany_textlo" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "text_segment_operand" "")))] + "TARGET_CM_EMBMEDANY" + "or\\t%1, %%lo(%a2), %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +;; Now some patterns to help reload out a bit. +(define_expand "reload_indi" + [(parallel [(match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "immediate_operand" "") + (match_operand:TI 2 "register_operand" "=&r")])] + "(TARGET_CM_MEDANY + || TARGET_CM_EMBMEDANY) + && ! flag_pic" + " +{ + sparc_emit_set_symbolic_const64 (operands[0], operands[1], + gen_rtx_REG (DImode, REGNO (operands[2]))); + DONE; +}") + +(define_expand "reload_outdi" + [(parallel [(match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "immediate_operand" "") + (match_operand:TI 2 "register_operand" "=&r")])] + "(TARGET_CM_MEDANY + || TARGET_CM_EMBMEDANY) + && ! flag_pic" + " +{ + sparc_emit_set_symbolic_const64 (operands[0], operands[1], + gen_rtx_REG (DImode, REGNO (operands[2]))); + DONE; +}") + +;; Split up putting CONSTs and REGs into DI regs when !arch64 +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "const_int_operand" ""))] + "! TARGET_ARCH64 && reload_completed" + [(clobber (const_int 0))] + " +{ + emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), + (INTVAL (operands[1]) < 0) ? + constm1_rtx : + const0_rtx)); + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), + operands[1])); + DONE; +}") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "const_double_operand" ""))] + "! TARGET_ARCH64 && reload_completed" + [(clobber (const_int 0))] + " +{ + emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), + GEN_INT (CONST_DOUBLE_HIGH (operands[1])))); + + /* Slick... but this trick loses if this subreg constant part + can be done in one insn. */ + if (CONST_DOUBLE_LOW (operands[1]) == CONST_DOUBLE_HIGH (operands[1]) + && !(SPARC_SETHI_P (CONST_DOUBLE_HIGH (operands[1])) + || SPARC_SIMM13_P (CONST_DOUBLE_HIGH (operands[1])))) + { + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), + gen_highpart (SImode, operands[0]))); + } + else + { + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), + GEN_INT (CONST_DOUBLE_LOW (operands[1])))); + } + DONE; +}") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" ""))] + "! TARGET_ARCH64 && reload_completed" + [(clobber (const_int 0))] + " +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + if (GET_CODE (set_dest) == SUBREG) + set_dest = alter_subreg (set_dest); + if (GET_CODE (set_src) == SUBREG) + set_src = alter_subreg (set_src); + + dest1 = gen_highpart (SImode, set_dest); + dest2 = gen_lowpart (SImode, set_dest); + src1 = gen_highpart (SImode, set_src); + src2 = gen_lowpart (SImode, set_src); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movsi (dest2, src2)); + emit_insn (gen_movsi (dest1, src1)); + } + else + { + emit_insn (gen_movsi (dest1, src1)); + emit_insn (gen_movsi (dest2, src2)); + } + DONE; +}") + +;; Now handle the cases of memory moves from/to non-even +;; DI mode register pairs. +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "memory_operand" ""))] + "(! TARGET_ARCH64 + && reload_completed + && sparc_splitdi_legitimate (operands[0], operands[1]))" + [(clobber (const_int 0))] + " +{ + rtx word0 = change_address (operands[1], SImode, NULL_RTX); + rtx word1 = change_address (operands[1], SImode, + plus_constant_for_output (XEXP (word0, 0), 4)); + rtx high_part = gen_highpart (SImode, operands[0]); + rtx low_part = gen_lowpart (SImode, operands[0]); + + if (reg_overlap_mentioned_p (high_part, word1)) + { + emit_insn (gen_movsi (low_part, word1)); + emit_insn (gen_movsi (high_part, word0)); + } + else + { + emit_insn (gen_movsi (high_part, word0)); + emit_insn (gen_movsi (low_part, word1)); + } + DONE; +}") + +(define_split + [(set (match_operand:DI 0 "memory_operand" "") + (match_operand:DI 1 "register_operand" ""))] + "(! TARGET_ARCH64 + && reload_completed + && sparc_splitdi_legitimate (operands[1], operands[0]))" + [(clobber (const_int 0))] + " +{ + rtx word0 = change_address (operands[0], SImode, NULL_RTX); + rtx word1 = change_address (operands[0], SImode, + plus_constant_for_output (XEXP (word0, 0), 4)); + rtx high_part = gen_highpart (SImode, operands[1]); + rtx low_part = gen_lowpart (SImode, operands[1]); + + emit_insn (gen_movsi (word0, high_part)); + emit_insn (gen_movsi (word1, low_part)); + DONE; +}") + + +;; Floating point move insns + +(define_insn "*clear_sf" + [(set (match_operand:SF 0 "general_operand" "=f") + (match_operand:SF 1 "" ""))] + "TARGET_VIS + && GET_CODE (operands[1]) == CONST_DOUBLE + && GET_CODE (operands[0]) == REG + && fp_zero_operand (operands[1])" + "fzeros\\t%0" + [(set_attr "type" "fpmove") + (set_attr "length" "1")]) + +(define_insn "*movsf_const_intreg" + [(set (match_operand:SF 0 "general_operand" "=f,r") + (match_operand:SF 1 "" "m,F"))] + "TARGET_FPU + && GET_CODE (operands[1]) == CONST_DOUBLE + && GET_CODE (operands[0]) == REG" + "* +{ + REAL_VALUE_TYPE r; + long i; + + if (which_alternative == 0) + return \"ld\\t%1, %0\"; + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_SINGLE (r, i); + if (SPARC_SIMM13_P (i) || SPARC_SETHI_P (i)) + { + operands[1] = GEN_INT (i); + if (SPARC_SIMM13_P (INTVAL (operands[1]))) + return \"mov\\t%1, %0\"; + else if (SPARC_SETHI_P (INTVAL (operands[1]))) + return \"sethi\\t%%hi(%a1), %0\"; + else + abort (); + } + else + return \"#\"; +}" + [(set_attr "type" "move") + (set_attr "length" "1,2")]) + +;; There isn't much I can do about this, if I change the +;; mode then flow info gets really confused because the +;; destination no longer looks the same. Ho hum... +(define_insn "*movsf_const_high" + [(set (match_operand:SF 0 "register_operand" "=r") + (unspec:SF [(match_operand 1 "const_int_operand" "")] 12))] + "" + "sethi\\t%%hi(%a1), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_insn "*movsf_const_lo" + [(set (match_operand:SF 0 "register_operand" "=r") + (unspec:SF [(match_operand 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "")] 17))] + "" + "or\\t%1, %%lo(%a2), %0" + [(set_attr "type" "move") + (set_attr "length" "1")]) + +(define_split + [(set (match_operand:SF 0 "register_operand" "") + (match_operand:SF 1 "const_double_operand" ""))] + "TARGET_FPU + && (GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32)" + [(set (match_dup 0) (unspec:SF [(match_dup 1)] 12)) + (set (match_dup 0) (unspec:SF [(match_dup 0) (match_dup 1)] 17))] + " +{ + REAL_VALUE_TYPE r; + long i; + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_SINGLE (r, i); + operands[1] = GEN_INT (i); +}") + +(define_expand "movsf" + [(set (match_operand:SF 0 "general_operand" "") + (match_operand:SF 1 "general_operand" ""))] + "" + " +{ + /* Force SFmode constants into memory. */ + if (GET_CODE (operands[0]) == REG + && CONSTANT_P (operands[1])) + { + if (TARGET_VIS + && GET_CODE (operands[1]) == CONST_DOUBLE + && fp_zero_operand (operands[1])) + goto movsf_is_ok; + + /* emit_group_store will send such bogosity to us when it is + not storing directly into memory. So fix this up to avoid + crashes in output_constant_pool. */ + if (operands [1] == const0_rtx) + operands[1] = CONST0_RTX (SFmode); + operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]), + operands[1])); + } + + /* Handle sets of MEM first. */ + if (GET_CODE (operands[0]) == MEM) + { + if (register_operand (operands[1], SFmode)) + goto movsf_is_ok; + + if (! reload_in_progress) + { + operands[0] = validize_mem (operands[0]); + operands[1] = force_reg (SFmode, operands[1]); + } + } + + /* Fixup PIC cases. */ + if (flag_pic) + { + if (CONSTANT_P (operands[1]) + && pic_address_needs_scratch (operands[1])) + operands[1] = legitimize_pic_address (operands[1], SFmode, 0); + + if (symbolic_operand (operands[1], SFmode)) + { + operands[1] = legitimize_pic_address (operands[1], + SFmode, + (reload_in_progress ? + operands[0] : + NULL_RTX)); + } + } + + movsf_is_ok: + ; +}") + +(define_insn "*movsf_insn" + [(set (match_operand:SF 0 "general_operand" "=f,f,m,r,r,m") + (match_operand:SF 1 "input_operand" "f,m,f,r,m,r"))] + "TARGET_FPU + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode))" + "@ + fmovs\\t%1, %0 + ld\\t%1, %0 + st\\t%1, %0 + mov\\t%1, %0 + ld\\t%1, %0 + st\\t%1, %0" + [(set_attr "type" "fpmove,fpload,fpstore,move,load,store") + (set_attr "length" "1")]) + +;; Exactly the same as above, except that all `f' cases are deleted. +;; This is necessary to prevent reload from ever trying to use a `f' reg +;; when -mno-fpu. + +(define_insn "*movsf_no_f_insn" + [(set (match_operand:SF 0 "general_operand" "=r,r,m") + (match_operand:SF 1 "input_operand" "r,m,r"))] + "! TARGET_FPU + && (register_operand (operands[0], SFmode) + || register_operand (operands[1], SFmode))" + "@ + mov\\t%1, %0 + ld\\t%1, %0 + st\\t%1, %0" + [(set_attr "type" "move,load,store") + (set_attr "length" "1")]) + +(define_insn "*clear_df" + [(set (match_operand:DF 0 "general_operand" "=e") + (match_operand:DF 1 "" ""))] + "TARGET_VIS + && GET_CODE (operands[1]) == CONST_DOUBLE + && GET_CODE (operands[0]) == REG + && fp_zero_operand (operands[1])" + "fzero\\t%0" + [(set_attr "type" "fpmove") + (set_attr "length" "1")]) + +(define_insn "*movdf_const_intreg_sp32" + [(set (match_operand:DF 0 "general_operand" "=e,e,r") + (match_operand:DF 1 "" "T,o,F"))] + "TARGET_FPU && ! TARGET_ARCH64 + && GET_CODE (operands[1]) == CONST_DOUBLE + && GET_CODE (operands[0]) == REG" + "* +{ + if (which_alternative == 0) + return \"ldd\\t%1, %0\"; + else + return \"#\"; +}" + [(set_attr "type" "move") + (set_attr "length" "1,2,2")]) + +;; Now that we redo life analysis with a clean slate after +;; instruction splitting for sched2 this can work. +(define_insn "*movdf_const_intreg_sp64" + [(set (match_operand:DF 0 "general_operand" "=e,e,r") + (match_operand:DF 1 "" "m,o,F"))] + "TARGET_FPU + && TARGET_ARCH64 + && GET_CODE (operands[1]) == CONST_DOUBLE + && GET_CODE (operands[0]) == REG" + "* +{ + if (which_alternative == 0) + return \"ldd\\t%1, %0\"; + else + return \"#\"; +}" + [(set_attr "type" "move") + (set_attr "length" "1,2,2")]) + +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "const_double_operand" ""))] + "TARGET_FPU + && GET_CODE (operands[1]) == CONST_DOUBLE + && (GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + && reload_completed" + [(clobber (const_int 0))] + " +{ + REAL_VALUE_TYPE r; + long l[2]; + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_DOUBLE (r, l); + if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0])); + + if (TARGET_ARCH64) + { +#if HOST_BITS_PER_WIDE_INT == 64 + HOST_WIDE_INT val; + + val = ((HOST_WIDE_INT)l[1] | + ((HOST_WIDE_INT)l[0] << 32)); + emit_insn (gen_movdi (operands[0], GEN_INT (val))); +#else + emit_insn (gen_movdi (operands[0], + gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, + l[1], l[0]))); +#endif + } + else + { + emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), + GEN_INT (l[0]))); + + /* Slick... but this trick loses if this subreg constant part + can be done in one insn. */ + if (l[1] == l[0] + && !(SPARC_SETHI_P (l[0]) + || SPARC_SIMM13_P (l[0]))) + { + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), + gen_highpart (SImode, operands[0]))); + } + else + { + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), + GEN_INT (l[1]))); + } + } + DONE; +}") + +(define_expand "movdf" + [(set (match_operand:DF 0 "general_operand" "") + (match_operand:DF 1 "general_operand" ""))] + "" + " +{ + /* Force DFmode constants into memory. */ + if (GET_CODE (operands[0]) == REG + && CONSTANT_P (operands[1])) + { + if (TARGET_VIS + && GET_CODE (operands[1]) == CONST_DOUBLE + && fp_zero_operand (operands[1])) + goto movdf_is_ok; + + /* emit_group_store will send such bogosity to us when it is + not storing directly into memory. So fix this up to avoid + crashes in output_constant_pool. */ + if (operands [1] == const0_rtx) + operands[1] = CONST0_RTX (DFmode); + operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]), + operands[1])); + } + + /* Handle MEM cases first. */ + if (GET_CODE (operands[0]) == MEM) + { + if (register_operand (operands[1], DFmode)) + goto movdf_is_ok; + + if (! reload_in_progress) + { + operands[0] = validize_mem (operands[0]); + operands[1] = force_reg (DFmode, operands[1]); + } + } + + /* Fixup PIC cases. */ + if (flag_pic) + { + if (CONSTANT_P (operands[1]) + && pic_address_needs_scratch (operands[1])) + operands[1] = legitimize_pic_address (operands[1], DFmode, 0); + + if (symbolic_operand (operands[1], DFmode)) + { + operands[1] = legitimize_pic_address (operands[1], + DFmode, + (reload_in_progress ? + operands[0] : + NULL_RTX)); + } + } + + movdf_is_ok: + ; +}") + +;; Be careful, fmovd does not exist when !v9. +(define_insn "*movdf_insn_sp32" + [(set (match_operand:DF 0 "general_operand" "=e,T,U,T,e,r,r,o,e,o") + (match_operand:DF 1 "input_operand" "T,e,T,U,e,r,o,r,o,e"))] + "TARGET_FPU + && ! TARGET_V9 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "@ + ldd\\t%1, %0 + std\\t%1, %0 + ldd\\t%1, %0 + std\\t%1, %0 + # + # + # + # + # + #" + [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*") + (set_attr "length" "1,1,1,1,2,2,2,2,2,2")]) + +(define_insn "*movdf_no_e_insn_sp32" + [(set (match_operand:DF 0 "general_operand" "=U,T,r,r,o") + (match_operand:DF 1 "input_operand" "T,U,r,o,r"))] + "! TARGET_FPU + && ! TARGET_ARCH64 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "@ + ldd\\t%1, %0 + std\\t%1, %0 + # + # + #" + [(set_attr "type" "load,store,*,*,*") + (set_attr "length" "1,1,2,2,2")]) + +;; We have available v9 double floats but not 64-bit +;; integer registers. +(define_insn "*movdf_insn_v9only" + [(set (match_operand:DF 0 "general_operand" "=e,e,m,U,T,r,r,o") + (match_operand:DF 1 "input_operand" "e,m,e,T,U,r,o,r"))] + "TARGET_FPU + && TARGET_V9 + && ! TARGET_ARCH64 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "@ + fmovd\\t%1, %0 + ldd\\t%1, %0 + std\\t%1, %0 + ldd\\t%1, %0 + std\\t%1, %0 + # + # + #" + [(set_attr "type" "fpmove,load,store,load,store,*,*,*") + (set_attr "length" "1,1,1,1,1,2,2,2")]) + +;; We have available both v9 double floats and 64-bit +;; integer registers. +(define_insn "*movdf_insn_sp64" + [(set (match_operand:DF 0 "general_operand" "=e,e,m,r,r,m") + (match_operand:DF 1 "input_operand" "e,m,e,r,m,r"))] + "TARGET_FPU + && TARGET_V9 + && TARGET_ARCH64 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "@ + fmovd\\t%1, %0 + ldd\\t%1, %0 + std\\t%1, %0 + mov\\t%1, %0 + ldx\\t%1, %0 + stx\\t%1, %0" + [(set_attr "type" "fpmove,load,store,move,load,store") + (set_attr "length" "1")]) + +(define_insn "*movdf_no_e_insn_sp64" + [(set (match_operand:DF 0 "general_operand" "=r,r,m") + (match_operand:DF 1 "input_operand" "r,m,r"))] + "! TARGET_FPU + && TARGET_ARCH64 + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "@ + mov\\t%1, %0 + ldx\\t%1, %0 + stx\\t%1, %0" + [(set_attr "type" "move,load,store") + (set_attr "length" "1")]) + +;; Ok, now the splits to handle all the multi insn and +;; mis-aligned memory address cases. +;; In these splits please take note that we must be +;; careful when V9 but not ARCH64 because the integer +;; register DFmode cases must be handled. +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "register_operand" ""))] + "(! TARGET_V9 + || (! TARGET_ARCH64 + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32)))) + && reload_completed" + [(clobber (const_int 0))] + " +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + if (GET_CODE (set_dest) == SUBREG) + set_dest = alter_subreg (set_dest); + if (GET_CODE (set_src) == SUBREG) + set_src = alter_subreg (set_src); + + dest1 = gen_highpart (SFmode, set_dest); + dest2 = gen_lowpart (SFmode, set_dest); + src1 = gen_highpart (SFmode, set_src); + src2 = gen_lowpart (SFmode, set_src); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movsf (dest2, src2)); + emit_insn (gen_movsf (dest1, src1)); + } + else + { + emit_insn (gen_movsf (dest1, src1)); + emit_insn (gen_movsf (dest2, src2)); + } + DONE; +}") + +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "memory_operand" ""))] + "((! TARGET_V9 + || (! TARGET_ARCH64 + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32)))) + && (reload_completed + && (((REGNO (operands[0])) % 2) != 0 + || ! mem_min_alignment (operands[1], 8)) + && offsettable_memref_p (operands[1])))" + [(clobber (const_int 0))] + " +{ + rtx word0 = change_address (operands[1], SFmode, NULL_RTX); + rtx word1 = change_address (operands[1], SFmode, + plus_constant_for_output (XEXP (word0, 0), 4)); + + if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + + if (reg_overlap_mentioned_p (gen_highpart (SFmode, operands[0]), word1)) + { + emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]), + word1)); + emit_insn (gen_movsf (gen_highpart (SFmode, operands[0]), + word0)); + } + else + { + emit_insn (gen_movsf (gen_highpart (SFmode, operands[0]), + word0)); + emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]), + word1)); + } + DONE; +}") + +(define_split + [(set (match_operand:DF 0 "memory_operand" "") + (match_operand:DF 1 "register_operand" ""))] + "((! TARGET_V9 + || (! TARGET_ARCH64 + && ((GET_CODE (operands[1]) == REG + && REGNO (operands[1]) < 32) + || (GET_CODE (operands[1]) == SUBREG + && GET_CODE (SUBREG_REG (operands[1])) == REG + && REGNO (SUBREG_REG (operands[1])) < 32)))) + && (reload_completed + && (((REGNO (operands[1])) % 2) != 0 + || ! mem_min_alignment (operands[0], 8)) + && offsettable_memref_p (operands[0])))" + [(clobber (const_int 0))] + " +{ + rtx word0 = change_address (operands[0], SFmode, NULL_RTX); + rtx word1 = change_address (operands[0], SFmode, + plus_constant_for_output (XEXP (word0, 0), 4)); + + if (GET_CODE (operands[1]) == SUBREG) + operands[1] = alter_subreg (operands[1]); + emit_insn (gen_movsf (word0, + gen_highpart (SFmode, operands[1]))); + emit_insn (gen_movsf (word1, + gen_lowpart (SFmode, operands[1]))); + DONE; +}") + +(define_expand "movtf" + [(set (match_operand:TF 0 "general_operand" "") + (match_operand:TF 1 "general_operand" ""))] + "" + " +{ + /* Force TFmode constants into memory. */ + if (GET_CODE (operands[0]) == REG + && CONSTANT_P (operands[1])) + { + /* emit_group_store will send such bogosity to us when it is + not storing directly into memory. So fix this up to avoid + crashes in output_constant_pool. */ + if (operands [1] == const0_rtx) + operands[1] = CONST0_RTX (TFmode); + operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]), + operands[1])); + } + + /* Handle MEM cases first, note that only v9 guarentees + full 16-byte alignment for quads. */ + if (GET_CODE (operands[0]) == MEM) + { + if (register_operand (operands[1], TFmode)) + goto movtf_is_ok; + + if (! reload_in_progress) + { + operands[0] = validize_mem (operands[0]); + operands[1] = force_reg (TFmode, operands[1]); + } + } + + /* Fixup PIC cases. */ + if (flag_pic) + { + if (CONSTANT_P (operands[1]) + && pic_address_needs_scratch (operands[1])) + operands[1] = legitimize_pic_address (operands[1], TFmode, 0); + + if (symbolic_operand (operands[1], TFmode)) + { + operands[1] = legitimize_pic_address (operands[1], + TFmode, + (reload_in_progress ? + operands[0] : + NULL_RTX)); + } + } + + movtf_is_ok: + ; +}") + +;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so +;; we must split them all. :-( +(define_insn "*movtf_insn_sp32" + [(set (match_operand:TF 0 "general_operand" "=e,o,U,o,e,r,r,o") + (match_operand:TF 1 "input_operand" "o,e,o,U,e,r,o,r"))] + "TARGET_FPU + && ! TARGET_ARCH64 + && (register_operand (operands[0], TFmode) + || register_operand (operands[1], TFmode))" + "#" + [(set_attr "length" "4")]) + +;; Exactly the same as above, except that all `e' cases are deleted. +;; This is necessary to prevent reload from ever trying to use a `e' reg +;; when -mno-fpu. + +(define_insn "*movtf_no_e_insn_sp32" + [(set (match_operand:TF 0 "general_operand" "=U,o,r,r,o") + (match_operand:TF 1 "input_operand" "o,U,r,o,r"))] + "! TARGET_FPU + && ! TARGET_ARCH64 + && (register_operand (operands[0], TFmode) + || register_operand (operands[1], TFmode))" + "#" + [(set_attr "length" "4")]) + +;; Now handle the float reg cases directly when arch64, +;; hard_quad, and proper reg number alignment are all true. +(define_insn "*movtf_insn_hq_sp64" + [(set (match_operand:TF 0 "general_operand" "=e,e,m,r,r,o") + (match_operand:TF 1 "input_operand" "e,m,e,r,o,r"))] + "TARGET_FPU + && TARGET_ARCH64 + && TARGET_V9 + && TARGET_HARD_QUAD + && (register_operand (operands[0], TFmode) + || register_operand (operands[1], TFmode))" + "@ + fmovq\\t%1, %0 + ldq\\t%1, %0 + stq\\t%1, %0 + # + # + #" + [(set_attr "type" "fpmove,fpload,fpstore,*,*,*") + (set_attr "length" "1,1,1,2,2,2")]) + +;; Now we allow the integer register cases even when +;; only arch64 is true. +(define_insn "*movtf_insn_sp64" + [(set (match_operand:TF 0 "general_operand" "=e,o,r,o,e,r") + (match_operand:TF 1 "input_operand" "o,e,o,r,e,r"))] + "TARGET_FPU + && TARGET_ARCH64 + && ! TARGET_HARD_QUAD + && (register_operand (operands[0], TFmode) + || register_operand (operands[1], TFmode))" + "#" + [(set_attr "length" "2")]) + +(define_insn "*movtf_no_e_insn_sp64" + [(set (match_operand:TF 0 "general_operand" "=r,o,r") + (match_operand:TF 1 "input_operand" "o,r,r"))] + "! TARGET_FPU + && TARGET_ARCH64 + && (register_operand (operands[0], TFmode) + || register_operand (operands[1], TFmode))" + "#" + [(set_attr "length" "2")]) + +;; Now all the splits to handle multi-insn TF mode moves. +(define_split + [(set (match_operand:TF 0 "register_operand" "") + (match_operand:TF 1 "register_operand" ""))] + "reload_completed + && (! TARGET_ARCH64 + || (TARGET_FPU + && ! TARGET_HARD_QUAD))" + [(clobber (const_int 0))] + " +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + if (GET_CODE (set_dest) == SUBREG) + set_dest = alter_subreg (set_dest); + if (GET_CODE (set_src) == SUBREG) + set_src = alter_subreg (set_src); + + /* Ugly, but gen_highpart will crap out here for 32-bit targets. */ + dest1 = gen_rtx_SUBREG (DFmode, set_dest, WORDS_BIG_ENDIAN == 0); + dest2 = gen_rtx_SUBREG (DFmode, set_dest, WORDS_BIG_ENDIAN != 0); + src1 = gen_rtx_SUBREG (DFmode, set_src, WORDS_BIG_ENDIAN == 0); + src2 = gen_rtx_SUBREG (DFmode, set_src, WORDS_BIG_ENDIAN != 0); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movdf (dest2, src2)); + emit_insn (gen_movdf (dest1, src1)); + } + else + { + emit_insn (gen_movdf (dest1, src1)); + emit_insn (gen_movdf (dest2, src2)); + } + DONE; +}") + +(define_split + [(set (match_operand:TF 0 "register_operand" "") + (match_operand:TF 1 "memory_operand" ""))] + "(reload_completed + && offsettable_memref_p (operands[1]))" + [(clobber (const_int 0))] + " +{ + rtx word0 = change_address (operands[1], DFmode, NULL_RTX); + rtx word1 = change_address (operands[1], DFmode, + plus_constant_for_output (XEXP (word0, 0), 8)); + rtx dest1, dest2; + + /* Ugly, but gen_highpart will crap out here for 32-bit targets. */ + dest1 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN == 0); + dest2 = gen_rtx_SUBREG (DFmode, operands[0], WORDS_BIG_ENDIAN != 0); + + /* Now output, ordering such that we don't clobber any registers + mentioned in the address. */ + if (reg_overlap_mentioned_p (dest1, word1)) + + { + emit_insn (gen_movdf (dest2, word1)); + emit_insn (gen_movdf (dest1, word0)); + } + else + { + emit_insn (gen_movdf (dest1, word0)); + emit_insn (gen_movdf (dest2, word1)); + } + DONE; +}") + +(define_split + [(set (match_operand:TF 0 "memory_operand" "") + (match_operand:TF 1 "register_operand" ""))] + "(reload_completed + && offsettable_memref_p (operands[0]))" + [(clobber (const_int 0))] + " +{ + rtx word0 = change_address (operands[0], DFmode, NULL_RTX); + rtx word1 = change_address (operands[0], DFmode, + plus_constant_for_output (XEXP (word0, 0), 8)); + rtx src1, src2; + + /* Ugly, but gen_highpart will crap out here for 32-bit targets. */ + src1 = gen_rtx_SUBREG (DFmode, operands[1], WORDS_BIG_ENDIAN == 0); + src2 = gen_rtx_SUBREG (DFmode, operands[1], WORDS_BIG_ENDIAN != 0); + emit_insn (gen_movdf (word0, src1)); + emit_insn (gen_movdf (word1, src2)); + DONE; +}") + +;; Sparc V9 conditional move instructions. + +;; We can handle larger constants here for some flavors, but for now we keep +;; it simple and only allow those constants supported by all flavours. +;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand +;; 3 contains the constant if one is present, but we handle either for +;; generality (sparc.c puts a constant in operand 2). + +(define_expand "movqicc" + [(set (match_operand:QI 0 "register_operand" "") + (if_then_else:QI (match_operand 1 "comparison_operator" "") + (match_operand:QI 2 "arith10_operand" "") + (match_operand:QI 3 "arith10_operand" "")))] + "TARGET_V9" + " +{ + enum rtx_code code = GET_CODE (operands[1]); + + if (GET_MODE (sparc_compare_op0) == DImode + && ! TARGET_ARCH64) + FAIL; + + if (sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode + && v9_regcmp_p (code)) + { + operands[1] = gen_rtx_fmt_ee (code, DImode, + sparc_compare_op0, sparc_compare_op1); + } + else + { + rtx cc_reg = gen_compare_reg (code, + sparc_compare_op0, sparc_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + } +}") + +(define_expand "movhicc" + [(set (match_operand:HI 0 "register_operand" "") + (if_then_else:HI (match_operand 1 "comparison_operator" "") + (match_operand:HI 2 "arith10_operand" "") + (match_operand:HI 3 "arith10_operand" "")))] + "TARGET_V9" + " +{ + enum rtx_code code = GET_CODE (operands[1]); + + if (GET_MODE (sparc_compare_op0) == DImode + && ! TARGET_ARCH64) + FAIL; + + if (sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode + && v9_regcmp_p (code)) + { + operands[1] = gen_rtx_fmt_ee (code, DImode, + sparc_compare_op0, sparc_compare_op1); + } + else + { + rtx cc_reg = gen_compare_reg (code, + sparc_compare_op0, sparc_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + } +}") + +(define_expand "movsicc" + [(set (match_operand:SI 0 "register_operand" "") + (if_then_else:SI (match_operand 1 "comparison_operator" "") + (match_operand:SI 2 "arith10_operand" "") + (match_operand:SI 3 "arith10_operand" "")))] + "TARGET_V9" + " +{ + enum rtx_code code = GET_CODE (operands[1]); + enum machine_mode op0_mode = GET_MODE (sparc_compare_op0); + + if (sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && (TARGET_ARCH64 && op0_mode == DImode && v9_regcmp_p (code))) + { + operands[1] = gen_rtx_fmt_ee (code, op0_mode, + sparc_compare_op0, sparc_compare_op1); + } + else + { + rtx cc_reg = gen_compare_reg (code, + sparc_compare_op0, sparc_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), + cc_reg, const0_rtx); + } +}") + +(define_expand "movdicc" + [(set (match_operand:DI 0 "register_operand" "") + (if_then_else:DI (match_operand 1 "comparison_operator" "") + (match_operand:DI 2 "arith10_double_operand" "") + (match_operand:DI 3 "arith10_double_operand" "")))] + "TARGET_ARCH64" + " +{ + enum rtx_code code = GET_CODE (operands[1]); + + if (sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode + && v9_regcmp_p (code)) + { + operands[1] = gen_rtx_fmt_ee (code, DImode, + sparc_compare_op0, sparc_compare_op1); + } + else + { + rtx cc_reg = gen_compare_reg (code, + sparc_compare_op0, sparc_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), + cc_reg, const0_rtx); + } +}") + +(define_expand "movsfcc" + [(set (match_operand:SF 0 "register_operand" "") + (if_then_else:SF (match_operand 1 "comparison_operator" "") + (match_operand:SF 2 "register_operand" "") + (match_operand:SF 3 "register_operand" "")))] + "TARGET_V9 && TARGET_FPU" + " +{ + enum rtx_code code = GET_CODE (operands[1]); + + if (GET_MODE (sparc_compare_op0) == DImode + && ! TARGET_ARCH64) + FAIL; + + if (sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode + && v9_regcmp_p (code)) + { + operands[1] = gen_rtx_fmt_ee (code, DImode, + sparc_compare_op0, sparc_compare_op1); + } + else + { + rtx cc_reg = gen_compare_reg (code, + sparc_compare_op0, sparc_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + } +}") + +(define_expand "movdfcc" + [(set (match_operand:DF 0 "register_operand" "") + (if_then_else:DF (match_operand 1 "comparison_operator" "") + (match_operand:DF 2 "register_operand" "") + (match_operand:DF 3 "register_operand" "")))] + "TARGET_V9 && TARGET_FPU" + " +{ + enum rtx_code code = GET_CODE (operands[1]); + + if (GET_MODE (sparc_compare_op0) == DImode + && ! TARGET_ARCH64) + FAIL; + + if (sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode + && v9_regcmp_p (code)) + { + operands[1] = gen_rtx_fmt_ee (code, DImode, + sparc_compare_op0, sparc_compare_op1); + } + else + { + rtx cc_reg = gen_compare_reg (code, + sparc_compare_op0, sparc_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + } +}") + +(define_expand "movtfcc" + [(set (match_operand:TF 0 "register_operand" "") + (if_then_else:TF (match_operand 1 "comparison_operator" "") + (match_operand:TF 2 "register_operand" "") + (match_operand:TF 3 "register_operand" "")))] + "TARGET_V9 && TARGET_FPU" + " +{ + enum rtx_code code = GET_CODE (operands[1]); + + if (GET_MODE (sparc_compare_op0) == DImode + && ! TARGET_ARCH64) + FAIL; + + if (sparc_compare_op1 == const0_rtx + && GET_CODE (sparc_compare_op0) == REG + && GET_MODE (sparc_compare_op0) == DImode + && v9_regcmp_p (code)) + { + operands[1] = gen_rtx_fmt_ee (code, DImode, + sparc_compare_op0, sparc_compare_op1); + } + else + { + rtx cc_reg = gen_compare_reg (code, + sparc_compare_op0, sparc_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + } +}") + +;; Conditional move define_insns. + +(define_insn "*movqi_cc_sp64" + [(set (match_operand:QI 0 "register_operand" "=r,r") + (if_then_else:QI (match_operator 1 "comparison_operator" + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) + (match_operand:QI 3 "arith11_operand" "rL,0") + (match_operand:QI 4 "arith11_operand" "0,rL")))] + "TARGET_V9" + "@ + mov%C1\\t%x2, %3, %0 + mov%c1\\t%x2, %4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +(define_insn "*movhi_cc_sp64" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (if_then_else:HI (match_operator 1 "comparison_operator" + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) + (match_operand:HI 3 "arith11_operand" "rL,0") + (match_operand:HI 4 "arith11_operand" "0,rL")))] + "TARGET_V9" + "@ + mov%C1\\t%x2, %3, %0 + mov%c1\\t%x2, %4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +(define_insn "*movsi_cc_sp64" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (if_then_else:SI (match_operator 1 "comparison_operator" + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) + (match_operand:SI 3 "arith11_operand" "rL,0") + (match_operand:SI 4 "arith11_operand" "0,rL")))] + "TARGET_V9" + "@ + mov%C1\\t%x2, %3, %0 + mov%c1\\t%x2, %4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +;; ??? The constraints of operands 3,4 need work. +(define_insn "*movdi_cc_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (if_then_else:DI (match_operator 1 "comparison_operator" + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) + (match_operand:DI 3 "arith11_double_operand" "rLH,0") + (match_operand:DI 4 "arith11_double_operand" "0,rLH")))] + "TARGET_ARCH64" + "@ + mov%C1\\t%x2, %3, %0 + mov%c1\\t%x2, %4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +(define_insn "*movdi_cc_sp64_trunc" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (if_then_else:SI (match_operator 1 "comparison_operator" + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) + (match_operand:SI 3 "arith11_double_operand" "rLH,0") + (match_operand:SI 4 "arith11_double_operand" "0,rLH")))] + "TARGET_ARCH64" + "@ + mov%C1\\t%x2, %3, %0 + mov%c1\\t%x2, %4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +(define_insn "*movsf_cc_sp64" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (if_then_else:SF (match_operator 1 "comparison_operator" + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) + (match_operand:SF 3 "register_operand" "f,0") + (match_operand:SF 4 "register_operand" "0,f")))] + "TARGET_V9 && TARGET_FPU" + "@ + fmovs%C1\\t%x2, %3, %0 + fmovs%c1\\t%x2, %4, %0" + [(set_attr "type" "fpcmove") + (set_attr "length" "1")]) + +(define_insn "*movdf_cc_sp64" + [(set (match_operand:DF 0 "register_operand" "=e,e") + (if_then_else:DF (match_operator 1 "comparison_operator" + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) + (match_operand:DF 3 "register_operand" "e,0") + (match_operand:DF 4 "register_operand" "0,e")))] + "TARGET_V9 && TARGET_FPU" + "@ + fmovd%C1\\t%x2, %3, %0 + fmovd%c1\\t%x2, %4, %0" + [(set_attr "type" "fpcmove") + (set_attr "length" "1")]) + +(define_insn "*movtf_cc_sp64" + [(set (match_operand:TF 0 "register_operand" "=e,e") + (if_then_else:TF (match_operator 1 "comparison_operator" + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) + (match_operand:TF 3 "register_operand" "e,0") + (match_operand:TF 4 "register_operand" "0,e")))] + "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" + "@ + fmovq%C1\\t%x2, %3, %0 + fmovq%c1\\t%x2, %4, %0" + [(set_attr "type" "fpcmove") + (set_attr "length" "1")]) + +(define_insn "*movqi_cc_reg_sp64" + [(set (match_operand:QI 0 "register_operand" "=r,r") + (if_then_else:QI (match_operator 1 "v9_regcmp_op" + [(match_operand:DI 2 "register_operand" "r,r") + (const_int 0)]) + (match_operand:QI 3 "arith10_operand" "rM,0") + (match_operand:QI 4 "arith10_operand" "0,rM")))] + "TARGET_ARCH64" + "@ + movr%D1\\t%2, %r3, %0 + movr%d1\\t%2, %r4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +(define_insn "*movhi_cc_reg_sp64" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (if_then_else:HI (match_operator 1 "v9_regcmp_op" + [(match_operand:DI 2 "register_operand" "r,r") + (const_int 0)]) + (match_operand:HI 3 "arith10_operand" "rM,0") + (match_operand:HI 4 "arith10_operand" "0,rM")))] + "TARGET_ARCH64" + "@ + movr%D1\\t%2, %r3, %0 + movr%d1\\t%2, %r4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +(define_insn "*movsi_cc_reg_sp64" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (if_then_else:SI (match_operator 1 "v9_regcmp_op" + [(match_operand:DI 2 "register_operand" "r,r") + (const_int 0)]) + (match_operand:SI 3 "arith10_operand" "rM,0") + (match_operand:SI 4 "arith10_operand" "0,rM")))] + "TARGET_ARCH64" + "@ + movr%D1\\t%2, %r3, %0 + movr%d1\\t%2, %r4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +;; ??? The constraints of operands 3,4 need work. +(define_insn "*movdi_cc_reg_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (if_then_else:DI (match_operator 1 "v9_regcmp_op" + [(match_operand:DI 2 "register_operand" "r,r") + (const_int 0)]) + (match_operand:DI 3 "arith10_double_operand" "rMH,0") + (match_operand:DI 4 "arith10_double_operand" "0,rMH")))] + "TARGET_ARCH64" + "@ + movr%D1\\t%2, %r3, %0 + movr%d1\\t%2, %r4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +(define_insn "*movdi_cc_reg_sp64_trunc" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (if_then_else:SI (match_operator 1 "v9_regcmp_op" + [(match_operand:DI 2 "register_operand" "r,r") + (const_int 0)]) + (match_operand:SI 3 "arith10_double_operand" "rMH,0") + (match_operand:SI 4 "arith10_double_operand" "0,rMH")))] + "TARGET_ARCH64" + "@ + movr%D1\\t%2, %r3, %0 + movr%d1\\t%2, %r4, %0" + [(set_attr "type" "cmove") + (set_attr "length" "1")]) + +(define_insn "*movsf_cc_reg_sp64" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (if_then_else:SF (match_operator 1 "v9_regcmp_op" + [(match_operand:DI 2 "register_operand" "r,r") + (const_int 0)]) + (match_operand:SF 3 "register_operand" "f,0") + (match_operand:SF 4 "register_operand" "0,f")))] + "TARGET_ARCH64 && TARGET_FPU" + "@ + fmovrs%D1\\t%2, %3, %0 + fmovrs%d1\\t%2, %4, %0" + [(set_attr "type" "fpcmove") + (set_attr "length" "1")]) + +(define_insn "*movdf_cc_reg_sp64" + [(set (match_operand:DF 0 "register_operand" "=e,e") + (if_then_else:DF (match_operator 1 "v9_regcmp_op" + [(match_operand:DI 2 "register_operand" "r,r") + (const_int 0)]) + (match_operand:DF 3 "register_operand" "e,0") + (match_operand:DF 4 "register_operand" "0,e")))] + "TARGET_ARCH64 && TARGET_FPU" + "@ + fmovrd%D1\\t%2, %3, %0 + fmovrd%d1\\t%2, %4, %0" + [(set_attr "type" "fpcmove") + (set_attr "length" "1")]) + +(define_insn "*movtf_cc_reg_sp64" + [(set (match_operand:TF 0 "register_operand" "=e,e") + (if_then_else:TF (match_operator 1 "v9_regcmp_op" + [(match_operand:DI 2 "register_operand" "r,r") + (const_int 0)]) + (match_operand:TF 3 "register_operand" "e,0") + (match_operand:TF 4 "register_operand" "0,e")))] + "TARGET_ARCH64 && TARGET_FPU" + "@ + fmovrq%D1\\t%2, %3, %0 + fmovrq%d1\\t%2, %4, %0" + [(set_attr "type" "fpcmove") + (set_attr "length" "1")]) + +;;- zero extension instructions + +;; These patterns originally accepted general_operands, however, slightly +;; better code is generated by only accepting register_operands, and then +;; letting combine generate the ldu[hb] insns. + +(define_expand "zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "") + (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] + "" + " +{ + rtx temp = gen_reg_rtx (SImode); + rtx shift_16 = GEN_INT (16); + int op1_subword = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subword = SUBREG_WORD (operand1); + operand1 = XEXP (operand1, 0); + } + + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, + op1_subword), + shift_16)); + emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); + DONE; +}") + +(define_insn "*zero_extendhisi2_insn" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] + "" + "lduh\\t%1, %0" + [(set_attr "type" "load") + (set_attr "length" "1")]) + +(define_expand "zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand" "") + (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] + "" + "") + +(define_insn "*zero_extendqihi2_insn" + [(set (match_operand:HI 0 "register_operand" "=r,r") + (zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))] + "GET_CODE (operands[1]) != CONST_INT" + "@ + and\\t%1, 0xff, %0 + ldub\\t%1, %0" + [(set_attr "type" "unary,load") + (set_attr "length" "1")]) + +(define_expand "zero_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "") + (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] + "" + "") + +(define_insn "*zero_extendqisi2_insn" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))] + "GET_CODE (operands[1]) != CONST_INT" + "@ + and\\t%1, 0xff, %0 + ldub\\t%1, %0" + [(set_attr "type" "unary,load") + (set_attr "length" "1")]) + +(define_expand "zero_extendqidi2" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] + "TARGET_ARCH64" + "") + +(define_insn "*zero_extendqidi2_insn" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))] + "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT" + "@ + and\\t%1, 0xff, %0 + ldub\\t%1, %0" + [(set_attr "type" "unary,load") + (set_attr "length" "1")]) + +(define_expand "zero_extendhidi2" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] + "TARGET_ARCH64" + " +{ + rtx temp = gen_reg_rtx (DImode); + rtx shift_48 = GEN_INT (48); + int op1_subword = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subword = SUBREG_WORD (operand1); + operand1 = XEXP (operand1, 0); + } + + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, + op1_subword), + shift_48)); + emit_insn (gen_lshrdi3 (operand0, temp, shift_48)); + DONE; +}") + +(define_insn "*zero_extendhidi2_insn" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] + "TARGET_ARCH64" + "lduh\\t%1, %0" + [(set_attr "type" "load") + (set_attr "length" "1")]) + + +;; ??? Write truncdisi pattern using sra? + +(define_expand "zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:SI 1 "register_operand" "")))] + "" + "") + +(define_insn "*zero_extendsidi2_insn_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (match_operand:SI 1 "input_operand" "r,m")))] + "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT" + "@ + srl\\t%1, 0, %0 + lduw\\t%1, %0" + [(set_attr "type" "shift,load") + (set_attr "length" "1")]) + +(define_insn "*zero_extendsidi2_insn_sp32" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] + "! TARGET_ARCH64" + "#" + [(set_attr "type" "unary") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:SI 1 "register_operand" "")))] + "! TARGET_ARCH64 && reload_completed" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 5))] + " +{ + rtx dest1, dest2; + + if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + + dest1 = gen_highpart (SImode, operands[0]); + dest2 = gen_lowpart (SImode, operands[0]); + + /* Swap the order in case of overlap. */ + if (REGNO (dest1) == REGNO (operands[1])) + { + operands[2] = dest2; + operands[3] = operands[1]; + operands[4] = dest1; + operands[5] = const0_rtx; + } + else + { + operands[2] = dest1; + operands[3] = const0_rtx; + operands[4] = dest2; + operands[5] = operands[1]; + } +}") + +;; Simplify comparisons of extended values. + +(define_insn "*cmp_zero_extendqisi2" + [(set (reg:CC 100) + (compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r")) + (const_int 0)))] + "! TARGET_LIVE_G0" + "andcc\\t%0, 0xff, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_zero_extendqisi2_set" + [(set (reg:CC 100) + (compare:CC (zero_extend:SI (match_operand:QI 1 "register_operand" "r")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (match_dup 1)))] + "" + "andcc\\t%1, 0xff, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_zero_extendqidi2" + [(set (reg:CCX 100) + (compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r")) + (const_int 0)))] + "TARGET_ARCH64" + "andcc\\t%0, 0xff, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_zero_extendqidi2_set" + [(set (reg:CCX 100) + (compare:CCX (zero_extend:DI (match_operand:QI 1 "register_operand" "r")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (match_dup 1)))] + "TARGET_ARCH64" + "andcc\\t%1, 0xff, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare. + +(define_insn "*cmp_siqi_trunc" + [(set (reg:CC 100) + (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0) + (const_int 0)))] + "! TARGET_LIVE_G0" + "andcc\\t%0, 0xff, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_siqi_trunc_set" + [(set (reg:CC 100) + (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 0) + (const_int 0))) + (set (match_operand:QI 0 "register_operand" "=r") + (subreg:QI (match_dup 1) 0))] + "" + "andcc\\t%1, 0xff, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_diqi_trunc" + [(set (reg:CC 100) + (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 0) + (const_int 0)))] + "TARGET_ARCH64" + "andcc\\t%0, 0xff, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_diqi_trunc_set" + [(set (reg:CC 100) + (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 0) + (const_int 0))) + (set (match_operand:QI 0 "register_operand" "=r") + (subreg:QI (match_dup 1) 0))] + "TARGET_ARCH64" + "andcc\\t%1, 0xff, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +;;- sign extension instructions + +;; These patterns originally accepted general_operands, however, slightly +;; better code is generated by only accepting register_operands, and then +;; letting combine generate the lds[hb] insns. + +(define_expand "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] + "" + " +{ + rtx temp = gen_reg_rtx (SImode); + rtx shift_16 = GEN_INT (16); + int op1_subword = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subword = SUBREG_WORD (operand1); + operand1 = XEXP (operand1, 0); + } + + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, + op1_subword), + shift_16)); + emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); + DONE; +}") + +(define_insn "*sign_extendhisi2_insn" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] + "" + "ldsh\\t%1, %0" + [(set_attr "type" "sload") + (set_attr "length" "1")]) + +(define_expand "extendqihi2" + [(set (match_operand:HI 0 "register_operand" "") + (sign_extend:HI (match_operand:QI 1 "register_operand" "")))] + "" + " +{ + rtx temp = gen_reg_rtx (SImode); + rtx shift_24 = GEN_INT (24); + int op1_subword = 0; + int op0_subword = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subword = SUBREG_WORD (operand1); + operand1 = XEXP (operand1, 0); + } + if (GET_CODE (operand0) == SUBREG) + { + op0_subword = SUBREG_WORD (operand0); + operand0 = XEXP (operand0, 0); + } + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, + op1_subword), + shift_24)); + if (GET_MODE (operand0) != SImode) + operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subword); + emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); + DONE; +}") + +(define_insn "*sign_extendqihi2_insn" + [(set (match_operand:HI 0 "register_operand" "=r") + (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] + "" + "ldsb\\t%1, %0" + [(set_attr "type" "sload") + (set_attr "length" "1")]) + +(define_expand "extendqisi2" + [(set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] + "" + " +{ + rtx temp = gen_reg_rtx (SImode); + rtx shift_24 = GEN_INT (24); + int op1_subword = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subword = SUBREG_WORD (operand1); + operand1 = XEXP (operand1, 0); + } + + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, + op1_subword), + shift_24)); + emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); + DONE; +}") + +(define_insn "*sign_extendqisi2_insn" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] + "" + "ldsb\\t%1, %0" + [(set_attr "type" "sload") + (set_attr "length" "1")]) + +(define_expand "extendqidi2" + [(set (match_operand:DI 0 "register_operand" "") + (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] + "TARGET_ARCH64" + " +{ + rtx temp = gen_reg_rtx (DImode); + rtx shift_56 = GEN_INT (56); + int op1_subword = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subword = SUBREG_WORD (operand1); + operand1 = XEXP (operand1, 0); + } + + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, + op1_subword), + shift_56)); + emit_insn (gen_ashrdi3 (operand0, temp, shift_56)); + DONE; +}") + +(define_insn "*sign_extendqidi2_insn" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] + "TARGET_ARCH64" + "ldsb\\t%1, %0" + [(set_attr "type" "sload") + (set_attr "length" "1")]) + +(define_expand "extendhidi2" + [(set (match_operand:DI 0 "register_operand" "") + (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] + "TARGET_ARCH64" + " +{ + rtx temp = gen_reg_rtx (DImode); + rtx shift_48 = GEN_INT (48); + int op1_subword = 0; + + if (GET_CODE (operand1) == SUBREG) + { + op1_subword = SUBREG_WORD (operand1); + operand1 = XEXP (operand1, 0); + } + + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, + op1_subword), + shift_48)); + emit_insn (gen_ashrdi3 (operand0, temp, shift_48)); + DONE; +}") + +(define_insn "*sign_extendhidi2_insn" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] + "TARGET_ARCH64" + "ldsh\\t%1, %0" + [(set_attr "type" "sload") + (set_attr "length" "1")]) + +(define_expand "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "") + (sign_extend:DI (match_operand:SI 1 "register_operand" "")))] + "TARGET_ARCH64" + "") + +(define_insn "*sign_extendsidi2_insn" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (sign_extend:DI (match_operand:SI 1 "input_operand" "r,m")))] + "TARGET_ARCH64" + "@ + sra\\t%1, 0, %0 + ldsw\\t%1, %0" + [(set_attr "type" "shift,sload") + (set_attr "length" "1")]) + +;; Special pattern for optimizing bit-field compares. This is needed +;; because combine uses this as a canonical form. + +(define_insn "*cmp_zero_extract" + [(set (reg:CC 100) + (compare:CC + (zero_extract:SI (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "small_int_or_double" "n") + (match_operand:SI 2 "small_int_or_double" "n")) + (const_int 0)))] + "! TARGET_LIVE_G0 + && ((GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 19) + || (GET_CODE (operands[2]) == CONST_DOUBLE + && CONST_DOUBLE_LOW (operands[2]) > 19))" + "* +{ + int len = (GET_CODE (operands[1]) == CONST_INT + ? INTVAL (operands[1]) + : CONST_DOUBLE_LOW (operands[1])); + int pos = 32 - + (GET_CODE (operands[2]) == CONST_INT + ? INTVAL (operands[2]) + : CONST_DOUBLE_LOW (operands[2])) - len; + HOST_WIDE_INT mask = ((1 << len) - 1) << pos; + + operands[1] = GEN_INT (mask); + return \"andcc\\t%0, %1, %%g0\"; +}" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_zero_extract_sp64" + [(set (reg:CCX 100) + (compare:CCX + (zero_extract:DI (match_operand:DI 0 "register_operand" "r") + (match_operand:SI 1 "small_int_or_double" "n") + (match_operand:SI 2 "small_int_or_double" "n")) + (const_int 0)))] + "TARGET_ARCH64 + && ((GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 51) + || (GET_CODE (operands[2]) == CONST_DOUBLE + && CONST_DOUBLE_LOW (operands[2]) > 51))" + "* +{ + int len = (GET_CODE (operands[1]) == CONST_INT + ? INTVAL (operands[1]) + : CONST_DOUBLE_LOW (operands[1])); + int pos = 64 - + (GET_CODE (operands[2]) == CONST_INT + ? INTVAL (operands[2]) + : CONST_DOUBLE_LOW (operands[2])) - len; + HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos; + + operands[1] = GEN_INT (mask); + return \"andcc\\t%0, %1, %%g0\"; +}" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +;; Conversions between float, double and long double. + +(define_insn "extendsfdf2" + [(set (match_operand:DF 0 "register_operand" "=e") + (float_extend:DF + (match_operand:SF 1 "register_operand" "f")))] + "TARGET_FPU" + "fstod\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "extendsftf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (float_extend:TF + (match_operand:SF 1 "register_operand" "f")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fstoq\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "extenddftf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (float_extend:TF + (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fdtoq\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "truncdfsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (float_truncate:SF + (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU" + "fdtos\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "trunctfsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (float_truncate:SF + (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fqtos\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "trunctfdf2" + [(set (match_operand:DF 0 "register_operand" "=e") + (float_truncate:DF + (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fqtod\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +;; Conversion between fixed point and floating point. + +(define_insn "floatsisf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (float:SF (match_operand:SI 1 "register_operand" "f")))] + "TARGET_FPU" + "fitos\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "floatsidf2" + [(set (match_operand:DF 0 "register_operand" "=e") + (float:DF (match_operand:SI 1 "register_operand" "f")))] + "TARGET_FPU" + "fitod\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "floatsitf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (float:TF (match_operand:SI 1 "register_operand" "f")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fitoq\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +;; Now the same for 64 bit sources. + +(define_insn "floatdisf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (float:SF (match_operand:DI 1 "register_operand" "e")))] + "TARGET_V9 && TARGET_FPU" + "fxtos\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=e") + (float:DF (match_operand:DI 1 "register_operand" "e")))] + "TARGET_V9 && TARGET_FPU" + "fxtod\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "floatditf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (float:TF (match_operand:DI 1 "register_operand" "e")))] + "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" + "fxtoq\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +;; Convert a float to an actual integer. +;; Truncation is performed as part of the conversion. + +(define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=f") + (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] + "TARGET_FPU" + "fstoi\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "fix_truncdfsi2" + [(set (match_operand:SI 0 "register_operand" "=f") + (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "e"))))] + "TARGET_FPU" + "fdtoi\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "fix_trunctfsi2" + [(set (match_operand:SI 0 "register_operand" "=f") + (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fqtoi\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +;; Now the same, for V9 targets + +(define_insn "fix_truncsfdi2" + [(set (match_operand:DI 0 "register_operand" "=e") + (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] + "TARGET_V9 && TARGET_FPU" + "fstox\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=e") + (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))] + "TARGET_V9 && TARGET_FPU" + "fdtox\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "fix_trunctfdi2" + [(set (match_operand:DI 0 "register_operand" "=e") + (fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))] + "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" + "fqtox\\t%1, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +;;- arithmetic instructions + +(define_expand "adddi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") + (match_operand:DI 2 "arith_double_add_operand" "rHI")))] + "" + " +{ + if (! TARGET_ARCH64) + { + emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, + gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_PLUS (DImode, operands[1], + operands[2])), + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (CCmode, SPARC_ICC_REG))))); + DONE; + } + if (arith_double_4096_operand(operands[2], DImode)) + { + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_MINUS (DImode, operands[1], + GEN_INT(-4096)))); + DONE; + } +}") + +(define_insn "adddi3_insn_sp32" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") + (match_operand:DI 2 "arith_double_operand" "rHI"))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") + (match_operand:DI 2 "arith_double_operand" "rHI"))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64 && reload_completed" + [(parallel [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (plus:SI (match_dup 4) + (match_dup 5)) + (const_int 0))) + (set (match_dup 3) + (plus:SI (match_dup 4) (match_dup 5)))]) + (set (match_dup 6) + (plus:SI (plus:SI (match_dup 7) + (match_dup 8)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + " +{ + operands[3] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_lowpart (SImode, operands[1]); + operands[5] = gen_lowpart (SImode, operands[2]); + operands[6] = gen_highpart (SImode, operands[0]); + operands[7] = gen_highpart (SImode, operands[1]); + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) < 0) + operands[8] = constm1_rtx; + else + operands[8] = const0_rtx; + } + else + operands[8] = gen_highpart (SImode, operands[2]); +}") + +(define_split + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_operand:DI 1 "arith_double_operand" "r") + (match_operand:DI 2 "arith_double_operand" "rHI"))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64 && reload_completed" + [(parallel [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (minus:SI (match_dup 4) + (match_dup 5)) + (const_int 0))) + (set (match_dup 3) + (minus:SI (match_dup 4) (match_dup 5)))]) + (set (match_dup 6) + (minus:SI (minus:SI (match_dup 7) + (match_dup 8)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + " +{ + operands[3] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_lowpart (SImode, operands[1]); + operands[5] = gen_lowpart (SImode, operands[2]); + operands[6] = gen_highpart (SImode, operands[0]); + operands[7] = gen_highpart (SImode, operands[1]); + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) < 0) + operands[8] = constm1_rtx; + else + operands[8] = const0_rtx; + } + else + operands[8] = gen_highpart (SImode, operands[2]); +}") + +;; LTU here means "carry set" +(define_insn "addx" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (plus:SI (match_operand:SI 1 "arith_operand" "%r") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + "" + "addx\\t%1, %2, %0" + [(set_attr "type" "unary") + (set_attr "length" "1")]) + +(define_insn "*addx_extend_sp32" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] + "! TARGET_ARCH64" + "#" + [(set_attr "type" "unary") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") + (match_operand:SI 2 "arith_operand" "")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] + "! TARGET_ARCH64 && reload_completed" + [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) + (set (match_dup 4) (const_int 0))] + "operands[3] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[1]);") + +(define_insn "*addx_extend_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] + "TARGET_ARCH64" + "addx\\t%r1, %2, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "subx" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + "" + "subx\\t%r1, %2, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*subx_extend_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] + "TARGET_ARCH64" + "subx\\t%r1, %2, %0" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "*subx_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] + "! TARGET_ARCH64" + "#" + [(set_attr "type" "unary") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] + "! TARGET_ARCH64 && reload_completed" + [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) + (set (match_dup 4) (const_int 0))] + "operands[3] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[0]);") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "register_operand" "r"))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64" + "#" + [(set_attr "type" "multi") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) + (match_operand:DI 2 "register_operand" ""))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64 && reload_completed" + [(parallel [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1)) + (const_int 0))) + (set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))]) + (set (match_dup 6) + (plus:SI (plus:SI (match_dup 4) (const_int 0)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + "operands[3] = gen_lowpart (SImode, operands[2]); + operands[4] = gen_highpart (SImode, operands[2]); + operands[5] = gen_lowpart (SImode, operands[0]); + operands[6] = gen_highpart (SImode, operands[0]);") + +(define_insn "*adddi3_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") + (match_operand:DI 2 "arith_double_operand" "rHI")))] + "TARGET_ARCH64" + "add\\t%1, %2, %0" + [(set_attr "type" "binary") + (set_attr "length" "1")]) + +(define_expand "addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (plus:SI (match_operand:SI 1 "arith_operand" "%r,d") + (match_operand:SI 2 "arith_add_operand" "rI,d")))] + "" + " +{ + if (arith_4096_operand(operands[2], DImode)) + { + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_MINUS (SImode, operands[1], + GEN_INT(-4096)))); + DONE; + } +}") + +(define_insn "*addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (plus:SI (match_operand:SI 1 "arith_operand" "%r,d") + (match_operand:SI 2 "arith_operand" "rI,d")))] + "" + "@ + add\\t%1, %2, %0 + fpadd32s\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_plus" + [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r") + (match_operand:SI 1 "arith_operand" "rI")) + (const_int 0)))] + "! TARGET_LIVE_G0" + "addcc\\t%0, %1, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_plus" + [(set (reg:CCX_NOOV 100) + (compare:CCX_NOOV (plus:DI (match_operand:DI 0 "arith_double_operand" "%r") + (match_operand:DI 1 "arith_double_operand" "rHI")) + (const_int 0)))] + "TARGET_ARCH64" + "addcc\\t%0, %1, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_plus_set" + [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (plus:SI (match_operand:SI 1 "arith_operand" "%r") + (match_operand:SI 2 "arith_operand" "rI")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (match_dup 1) (match_dup 2)))] + "" + "addcc\\t%1, %2, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_plus_set" + [(set (reg:CCX_NOOV 100) + (compare:CCX_NOOV (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") + (match_operand:DI 2 "arith_double_operand" "rHI")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_dup 1) (match_dup 2)))] + "TARGET_ARCH64" + "addcc\\t%1, %2, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_expand "subdi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "arith_double_add_operand" "rHI")))] + "" + " +{ + if (! TARGET_ARCH64) + { + emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, + gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_MINUS (DImode, operands[1], + operands[2])), + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (CCmode, SPARC_ICC_REG))))); + DONE; + } + if (arith_double_4096_operand(operands[2], DImode)) + { + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_PLUS (DImode, operands[1], + GEN_INT(-4096)))); + DONE; + } +}") + +(define_insn "*subdi3_sp32" + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "arith_double_operand" "rHI"))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64" + "#" + [(set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "arith_double_operand" ""))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64 + && reload_completed + && (GET_CODE (operands[2]) == CONST_INT + || GET_CODE (operands[2]) == CONST_DOUBLE)" + [(clobber (const_int 0))] + " +{ + rtx highp, lowp; + + highp = gen_highpart (SImode, operands[2]); + lowp = gen_lowpart (SImode, operands[2]); + if ((lowp == const0_rtx) + && (operands[0] == operands[1])) + { + emit_insn (gen_rtx_SET (VOIDmode, + gen_highpart (SImode, operands[0]), + gen_rtx_MINUS (SImode, + gen_highpart (SImode, operands[1]), + highp))); + } + else + { + emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]), + gen_lowpart (SImode, operands[1]), + lowp)); + emit_insn (gen_subx (gen_highpart (SImode, operands[0]), + gen_highpart (SImode, operands[1]), + highp)); + } + DONE; +}") + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64 + && reload_completed" + [(clobber (const_int 0))] + " +{ + emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]), + gen_lowpart (SImode, operands[1]), + gen_lowpart (SImode, operands[2]))); + emit_insn (gen_subx (gen_highpart (SImode, operands[0]), + gen_highpart (SImode, operands[1]), + gen_highpart (SImode, operands[2]))); + DONE; +}") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_operand:DI 1 "register_operand" "r") + (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64" + "#" + [(set_attr "type" "multi") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (zero_extend:DI (match_operand:SI 2 "register_operand" "")))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64 && reload_completed" + [(parallel [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2)) + (const_int 0))) + (set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))]) + (set (match_dup 6) + (minus:SI (minus:SI (match_dup 4) (const_int 0)) + (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] + "operands[3] = gen_lowpart (SImode, operands[1]); + operands[4] = gen_highpart (SImode, operands[1]); + operands[5] = gen_lowpart (SImode, operands[0]); + operands[6] = gen_highpart (SImode, operands[0]);") + +(define_insn "*subdi3_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "arith_double_operand" "rHI")))] + "TARGET_ARCH64" + "sub\\t%1, %2, %0" + [(set_attr "type" "binary") + (set_attr "length" "1")]) + +(define_expand "subsi3" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (minus:SI (match_operand:SI 1 "register_operand" "r,d") + (match_operand:SI 2 "arith_add_operand" "rI,d")))] + "" + " +{ + if (arith_4096_operand(operands[2], DImode)) + { + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_PLUS (SImode, operands[1], + GEN_INT(-4096)))); + DONE; + } +}") + +(define_insn "*subsi3" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (minus:SI (match_operand:SI 1 "register_operand" "r,d") + (match_operand:SI 2 "arith_operand" "rI,d")))] + "" + "@ + sub\\t%1, %2, %0 + fpsub32s\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1")]) + +(define_insn "*cmp_minus_cc" + [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (minus:SI (match_operand:SI 0 "reg_or_0_operand" "rJ") + (match_operand:SI 1 "arith_operand" "rI")) + (const_int 0)))] + "! TARGET_LIVE_G0" + "subcc\\t%r0, %1, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_minus_ccx" + [(set (reg:CCX_NOOV 100) + (compare:CCX_NOOV (minus:DI (match_operand:DI 0 "register_operand" "r") + (match_operand:DI 1 "arith_double_operand" "rHI")) + (const_int 0)))] + "TARGET_ARCH64" + "subcc\\t%0, %1, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "cmp_minus_cc_set" + [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_dup 1) (match_dup 2)))] + "" + "subcc\\t%r1, %2, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_minus_ccx_set" + [(set (reg:CCX_NOOV 100) + (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "arith_double_operand" "rHI")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_dup 1) (match_dup 2)))] + "TARGET_ARCH64" + "subcc\\t%1, %2, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +;; Integer Multiply/Divide. + +;; The 32 bit multiply/divide instructions are deprecated on v9 and shouldn't +;; we used. We still use them in 32 bit v9 compilers. +;; The 64 bit v9 compiler will (/should) widen the args and use muldi3. + +(define_insn "mulsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (mult:SI (match_operand:SI 1 "arith_operand" "%r") + (match_operand:SI 2 "arith_operand" "rI")))] + "TARGET_HARD_MUL" + "smul\\t%1, %2, %0" + [(set_attr "type" "imul") + (set_attr "length" "1")]) + +(define_expand "muldi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (match_operand:DI 1 "arith_double_operand" "%r") + (match_operand:DI 2 "arith_double_operand" "rHI")))] + "TARGET_ARCH64 || TARGET_V8PLUS" + " +{ + if (TARGET_V8PLUS) + { + emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}") + +(define_insn "*muldi3_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (match_operand:DI 1 "arith_double_operand" "%r") + (match_operand:DI 2 "arith_double_operand" "rHI")))] + "TARGET_ARCH64" + "mulx\\t%1, %2, %0" + [(set_attr "type" "imul") + (set_attr "length" "1")]) + +;; V8plus wide multiply. +;; XXX +(define_insn "muldi3_v8plus" + [(set (match_operand:DI 0 "register_operand" "=r,h") + (mult:DI (match_operand:DI 1 "arith_double_operand" "%r,0") + (match_operand:DI 2 "arith_double_operand" "rHI,rHI"))) + (clobber (match_scratch:SI 3 "=&h,X")) + (clobber (match_scratch:SI 4 "=&h,X"))] + "TARGET_V8PLUS" + "* +{ + if (sparc_check_64 (operands[1], insn) <= 0) + output_asm_insn (\"srl\\t%L1, 0, %L1\", operands); + if (which_alternative == 1) + output_asm_insn (\"sllx\\t%H1, 32, %H1\", operands); + if (sparc_check_64 (operands[2], insn) <= 0) + output_asm_insn (\"srl\\t%L2, 0, %L2\", operands); + if (which_alternative == 1) + return \"or\\t%L1, %H1, %H1\\n\\tsllx\\t%H2, 32, %L1\\n\\tor\\t%L2, %L1, %L1\\n\\tmulx\\t%H1, %L1, %L0\;srlx\\t%L0, 32, %H0\"; + else + return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; +}" + [(set_attr "length" "9,8")]) + +;; It is not known whether this will match. + +(define_insn "*cmp_mul_set" + [(set (match_operand:SI 0 "register_operand" "=r") + (mult:SI (match_operand:SI 1 "arith_operand" "%r") + (match_operand:SI 2 "arith_operand" "rI"))) + (set (reg:CC_NOOV 100) + (compare:CC_NOOV (mult:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS" + "smulcc\\t%1, %2, %0" + [(set_attr "type" "imul") + (set_attr "length" "1")]) + +(define_expand "mulsidi3" + [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) + (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))] + "TARGET_HARD_MUL" + " +{ + if (CONSTANT_P (operands[2])) + { + if (TARGET_V8PLUS) + { + emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1], + operands[2])); + DONE; + } + emit_insn (gen_const_mulsidi3 (operands[0], operands[1], operands[2])); + DONE; + } + if (TARGET_V8PLUS) + { + emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}") + +;; V9 puts the 64 bit product in a 64 bit register. Only out or global +;; registers can hold 64 bit values in the V8plus environment. +;; XXX +(define_insn "mulsidi3_v8plus" + [(set (match_operand:DI 0 "register_operand" "=h,r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))) + (clobber (match_scratch:SI 3 "=X,&h"))] + "TARGET_V8PLUS" + "@ + smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 + smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + [(set_attr "length" "2,3")]) + +;; XXX +(define_insn "const_mulsidi3_v8plus" + [(set (match_operand:DI 0 "register_operand" "=h,r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (match_operand:SI 2 "small_int" "I,I"))) + (clobber (match_scratch:SI 3 "=X,&h"))] + "TARGET_V8PLUS" + "@ + smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 + smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + [(set_attr "length" "2,3")]) + +;; XXX +(define_insn "*mulsidi3_sp32" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_HARD_MUL32" + "* +{ + return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; +}" + [(set (attr "length") + (if_then_else (eq_attr "isa" "sparclet") + (const_int 1) (const_int 2)))]) + +;; Extra pattern, because sign_extend of a constant isn't valid. + +;; XXX +(define_insn "const_mulsidi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "small_int" "I")))] + "TARGET_HARD_MUL" + "* +{ + return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; +}" + [(set (attr "length") + (if_then_else (eq_attr "isa" "sparclet") + (const_int 1) (const_int 2)))]) + +(define_expand "smulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) + (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))) + (const_int 32))))] + "TARGET_HARD_MUL" + " +{ + if (CONSTANT_P (operands[2])) + { + if (TARGET_V8PLUS) + { + emit_insn (gen_const_smulsi3_highpart_v8plus (operands[0], + operands[1], + operands[2], + GEN_INT (32))); + DONE; + } + emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2])); + DONE; + } + if (TARGET_V8PLUS) + { + emit_insn (gen_smulsi3_highpart_v8plus (operands[0], operands[1], + operands[2], GEN_INT (32))); + DONE; + } +}") + +;; XXX +(define_insn "smulsi3_highpart_v8plus" + [(set (match_operand:SI 0 "register_operand" "=h,r") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) + (match_operand:SI 3 "const_int_operand" "i,i")))) + (clobber (match_scratch:SI 4 "=X,&h"))] + "TARGET_V8PLUS" + "@ + smul %1,%2,%0\;srlx %0,%3,%0 + smul %1,%2,%4\;srlx %4,%3,%0" + [(set_attr "length" "2")]) + +;; The combiner changes TRUNCATE in the previous pattern to SUBREG. +;; XXX +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=h,r") + (subreg:SI + (lshiftrt:DI + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) + (match_operand:SI 3 "const_int_operand" "i,i")) + 1)) + (clobber (match_scratch:SI 4 "=X,&h"))] + "TARGET_V8PLUS" + "@ + smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 + smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + [(set_attr "length" "2")]) + +;; XXX +(define_insn "const_smulsi3_highpart_v8plus" + [(set (match_operand:SI 0 "register_operand" "=h,r") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (match_operand 2 "small_int" "i,i")) + (match_operand:SI 3 "const_int_operand" "i,i")))) + (clobber (match_scratch:SI 4 "=X,&h"))] + "TARGET_V8PLUS" + "@ + smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 + smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + [(set_attr "length" "2")]) + +;; XXX +(define_insn "*smulsi3_highpart_sp32" + [(set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) + (const_int 32))))] + "TARGET_HARD_MUL32 + && ! TARGET_LIVE_G0" + "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + [(set_attr "length" "2")]) + +;; XXX +(define_insn "const_smulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "r")) + (const_int 32))))] + "TARGET_HARD_MUL32 + && ! TARGET_LIVE_G0" + "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + [(set_attr "length" "2")]) + +(define_expand "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) + (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))] + "TARGET_HARD_MUL" + " +{ + if (CONSTANT_P (operands[2])) + { + if (TARGET_V8PLUS) + { + emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1], + operands[2])); + DONE; + } + emit_insn (gen_const_umulsidi3 (operands[0], operands[1], operands[2])); + DONE; + } + if (TARGET_V8PLUS) + { + emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}") + +;; XXX +(define_insn "umulsidi3_v8plus" + [(set (match_operand:DI 0 "register_operand" "=h,r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r")))) + (clobber (match_scratch:SI 3 "=X,&h"))] + "TARGET_V8PLUS" + "@ + umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 + umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + [(set_attr "length" "2,3")]) + +;; XXX +(define_insn "*umulsidi3_sp32" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_HARD_MUL32" + "* +{ + return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; +}" + [(set (attr "length") + (if_then_else (eq_attr "isa" "sparclet") + (const_int 1) (const_int 2)))]) + +;; Extra pattern, because sign_extend of a constant isn't valid. + +;; XXX +(define_insn "const_umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "uns_small_int" "")))] + "TARGET_HARD_MUL32" + "* +{ + return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; +}" + [(set (attr "length") + (if_then_else (eq_attr "isa" "sparclet") + (const_int 1) (const_int 2)))]) + +;; XXX +(define_insn "const_umulsidi3_v8plus" + [(set (match_operand:DI 0 "register_operand" "=h,r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (match_operand:SI 2 "uns_small_int" ""))) + (clobber (match_scratch:SI 3 "=X,h"))] + "TARGET_V8PLUS" + "@ + umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 + umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + [(set_attr "length" "2,3")]) + +(define_expand "umulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) + (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))) + (const_int 32))))] + "TARGET_HARD_MUL" + " +{ + if (CONSTANT_P (operands[2])) + { + if (TARGET_V8PLUS) + { + emit_insn (gen_const_umulsi3_highpart_v8plus (operands[0], + operands[1], + operands[2], + GEN_INT (32))); + DONE; + } + emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2])); + DONE; + } + if (TARGET_V8PLUS) + { + emit_insn (gen_umulsi3_highpart_v8plus (operands[0], operands[1], + operands[2], GEN_INT (32))); + DONE; + } +}") + +;; XXX +(define_insn "umulsi3_highpart_v8plus" + [(set (match_operand:SI 0 "register_operand" "=h,r") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) + (match_operand:SI 3 "const_int_operand" "i,i")))) + (clobber (match_scratch:SI 4 "=X,h"))] + "TARGET_V8PLUS" + "@ + umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 + umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + [(set_attr "length" "2")]) + +;; XXX +(define_insn "const_umulsi3_highpart_v8plus" + [(set (match_operand:SI 0 "register_operand" "=h,r") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (match_operand:SI 2 "uns_small_int" "")) + (match_operand:SI 3 "const_int_operand" "i,i")))) + (clobber (match_scratch:SI 4 "=X,h"))] + "TARGET_V8PLUS" + "@ + umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 + umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + [(set_attr "length" "2")]) + +;; XXX +(define_insn "*umulsi3_highpart_sp32" + [(set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))) + (const_int 32))))] + "TARGET_HARD_MUL32 + && ! TARGET_LIVE_G0" + "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + [(set_attr "length" "2")]) + +;; XXX +(define_insn "const_umulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=r") + (truncate:SI + (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "uns_small_int" "")) + (const_int 32))))] + "TARGET_HARD_MUL32 + && ! TARGET_LIVE_G0" + "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + [(set_attr "length" "2")]) + +;; The v8 architecture specifies that there must be 3 instructions between +;; a y register write and a use of it for correct results. + +;; XXX SHEESH +(define_insn "divsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (div:SI (match_operand:SI 1 "register_operand" "r,r") + (match_operand:SI 2 "input_operand" "rI,m"))) + (clobber (match_scratch:SI 3 "=&r,&r"))] + "(TARGET_V8 + || TARGET_DEPRECATED_V8_INSNS) + && ! TARGET_LIVE_G0" + "* +{ + if (which_alternative == 0) + if (TARGET_V9) + return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0\"; + else + return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %2, %0\"; + else + if (TARGET_V9) + return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tld\\t%2, %3\\n\\tsdiv\\t%1, %3, %0\"; + else + return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\"; +}" + [(set (attr "length") + (if_then_else (eq_attr "isa" "v9") + (const_int 4) (const_int 7)))]) + +(define_insn "divdi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (div:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "arith_double_operand" "rHI")))] + "TARGET_ARCH64" + "sdivx\\t%1, %2, %0") + +;; It is not known whether this will match. + +;; XXX I hope it doesn't fucking match... +(define_insn "*cmp_sdiv_cc_set" + [(set (match_operand:SI 0 "register_operand" "=r") + (div:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI"))) + (set (reg:CC 100) + (compare:CC (div:SI (match_dup 1) (match_dup 2)) + (const_int 0))) + (clobber (match_scratch:SI 3 "=&r"))] + "(TARGET_V8 + || TARGET_DEPRECATED_V8_INSNS) + && ! TARGET_LIVE_G0" + "* +{ + if (TARGET_V9) + return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tsdivcc\\t%1, %2, %0\"; + else + return \"sra\\t%1, 31, %3\\n\\twr\\t%%g0, %3, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\"; +}" + [(set (attr "length") + (if_then_else (eq_attr "isa" "v9") + (const_int 3) (const_int 6)))]) + +;; XXX +(define_insn "udivsi3" + [(set (match_operand:SI 0 "register_operand" "=r,&r,&r") + (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r,r,m") + (match_operand:SI 2 "input_operand" "rI,m,r")))] + "(TARGET_V8 + || TARGET_DEPRECATED_V8_INSNS) + && ! TARGET_LIVE_G0" + "* +{ + output_asm_insn (\"wr\\t%%g0, %%g0, %%y\", operands); + switch (which_alternative) + { + default: + if (TARGET_V9) + return \"udiv\\t%1, %2, %0\"; + return \"nop\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %2, %0\"; + case 1: + return \"ld\\t%2, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %0, %0\"; + case 2: + return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\"; + } +}" + [(set (attr "length") + (if_then_else (and (eq_attr "isa" "v9") + (eq_attr "alternative" "0")) + (const_int 2) (const_int 5)))]) + +(define_insn "udivdi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (udiv:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "arith_double_operand" "rHI")))] + "TARGET_ARCH64" + "udivx\\t%1, %2, %0") + +;; It is not known whether this will match. + +;; XXX I hope it doesn't fucking match... +(define_insn "*cmp_udiv_cc_set" + [(set (match_operand:SI 0 "register_operand" "=r") + (udiv:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI"))) + (set (reg:CC 100) + (compare:CC (udiv:SI (match_dup 1) (match_dup 2)) + (const_int 0)))] + "(TARGET_V8 + || TARGET_DEPRECATED_V8_INSNS) + && ! TARGET_LIVE_G0" + "* +{ + if (TARGET_V9) + return \"wr\\t%%g0, %%g0, %%y\\n\\tudivcc\\t%1, %2, %0\"; + else + return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\"; +}" + [(set (attr "length") + (if_then_else (eq_attr "isa" "v9") + (const_int 2) (const_int 5)))]) + +; sparclet multiply/accumulate insns + +(define_insn "*smacsi" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r") + (match_operand:SI 2 "arith_operand" "rI")) + (match_operand:SI 3 "register_operand" "0")))] + "TARGET_SPARCLET" + "smac\\t%1, %2, %0" + [(set_attr "type" "imul") + (set_attr "length" "1")]) + +(define_insn "*smacdi" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (mult:DI (sign_extend:DI + (match_operand:SI 1 "register_operand" "%r")) + (sign_extend:DI + (match_operand:SI 2 "register_operand" "r"))) + (match_operand:DI 3 "register_operand" "0")))] + "TARGET_SPARCLET" + "smacd\\t%1, %2, %L0" + [(set_attr "type" "imul") + (set_attr "length" "1")]) + +(define_insn "*umacdi" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (mult:DI (zero_extend:DI + (match_operand:SI 1 "register_operand" "%r")) + (zero_extend:DI + (match_operand:SI 2 "register_operand" "r"))) + (match_operand:DI 3 "register_operand" "0")))] + "TARGET_SPARCLET" + "umacd\\t%1, %2, %L0" + [(set_attr "type" "imul") + (set_attr "length" "1")]) + +;;- Boolean instructions +;; We define DImode `and' so with DImode `not' we can get +;; DImode `andn'. Other combinations are possible. + +(define_expand "anddi3" + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (match_operand:DI 1 "arith_double_operand" "") + (match_operand:DI 2 "arith_double_operand" "")))] + "" + "") + +(define_insn "*anddi3_sp32" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (and:DI (match_operand:DI 1 "arith_double_operand" "%r,b") + (match_operand:DI 2 "arith_double_operand" "rHI,b")))] + "! TARGET_ARCH64" + "@ + # + fand\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "2,1")]) + +(define_insn "*anddi3_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (and:DI (match_operand:DI 1 "arith_double_operand" "%r,b") + (match_operand:DI 2 "arith_double_operand" "rHI,b")))] + "TARGET_ARCH64" + "@ + and\\t%1, %2, %0 + fand\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (and:SI (match_operand:SI 1 "arith_operand" "%r,d") + (match_operand:SI 2 "arith_operand" "rI,d")))] + "" + "@ + and\\t%1, %2, %0 + fands\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (and:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "GET_CODE (operands[2]) == CONST_INT + && !SMALL_INT32 (operands[2]) + && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" + [(set (match_dup 3) (match_dup 4)) + (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))] + " +{ + operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff); +}") + +;; Split DImode logical operations requiring two instructions. +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operator:DI 1 "cc_arithop" ; AND, IOR, XOR + [(match_operand:DI 2 "register_operand" "") + (match_operand:DI 3 "arith_double_operand" "")]))] + "! TARGET_ARCH64 + && reload_completed + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32))" + [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)])) + (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))] + " +{ + if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + operands[4] = gen_highpart (SImode, operands[0]); + operands[5] = gen_lowpart (SImode, operands[0]); + operands[6] = gen_highpart (SImode, operands[2]); + operands[7] = gen_lowpart (SImode, operands[2]); + if (GET_CODE (operands[3]) == CONST_INT) + { + if (INTVAL (operands[3]) < 0) + operands[8] = constm1_rtx; + else + operands[8] = const0_rtx; + } + else + operands[8] = gen_highpart (SImode, operands[3]); + operands[9] = gen_lowpart (SImode, operands[3]); +}") + +(define_insn "*and_not_di_sp32" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b")) + (match_operand:DI 2 "register_operand" "r,b")))] + "! TARGET_ARCH64" + "@ + # + fandnot1\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "2,1")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (not:DI (match_operand:DI 1 "register_operand" "")) + (match_operand:DI 2 "register_operand" "")))] + "! TARGET_ARCH64 + && reload_completed + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32))" + [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5))) + (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + operands[3] = gen_highpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[1]); + operands[5] = gen_highpart (SImode, operands[2]); + operands[6] = gen_lowpart (SImode, operands[0]); + operands[7] = gen_lowpart (SImode, operands[1]); + operands[8] = gen_lowpart (SImode, operands[2]);") + +(define_insn "*and_not_di_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b")) + (match_operand:DI 2 "register_operand" "r,b")))] + "TARGET_ARCH64" + "@ + andn\\t%2, %1, %0 + fandnot1\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_insn "*and_not_si" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (and:SI (not:SI (match_operand:SI 1 "register_operand" "r,d")) + (match_operand:SI 2 "register_operand" "r,d")))] + "" + "@ + andn\\t%2, %1, %0 + fandnot1s\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_expand "iordi3" + [(set (match_operand:DI 0 "register_operand" "") + (ior:DI (match_operand:DI 1 "arith_double_operand" "") + (match_operand:DI 2 "arith_double_operand" "")))] + "" + "") + +(define_insn "*iordi3_sp32" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b") + (match_operand:DI 2 "arith_double_operand" "rHI,b")))] + "! TARGET_ARCH64" + "@ + # + for\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "2,1")]) + +(define_insn "*iordi3_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b") + (match_operand:DI 2 "arith_double_operand" "rHI,b")))] + "TARGET_ARCH64" + "@ + or\\t%1, %2, %0 + for\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_insn "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (ior:SI (match_operand:SI 1 "arith_operand" "%r,d") + (match_operand:SI 2 "arith_operand" "rI,d")))] + "" + "@ + or\\t%1, %2, %0 + fors\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (ior:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "GET_CODE (operands[2]) == CONST_INT + && !SMALL_INT32 (operands[2]) + && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" + [(set (match_dup 3) (match_dup 4)) + (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))] + " +{ + operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff); +}") + +(define_insn "*or_not_di_sp32" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b")) + (match_operand:DI 2 "register_operand" "r,b")))] + "! TARGET_ARCH64" + "@ + # + fornot1\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "2,1")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (ior:DI (not:DI (match_operand:DI 1 "register_operand" "")) + (match_operand:DI 2 "register_operand" "")))] + "! TARGET_ARCH64 + && reload_completed + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32))" + [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5))) + (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + operands[3] = gen_highpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[1]); + operands[5] = gen_highpart (SImode, operands[2]); + operands[6] = gen_lowpart (SImode, operands[0]); + operands[7] = gen_lowpart (SImode, operands[1]); + operands[8] = gen_lowpart (SImode, operands[2]);") + +(define_insn "*or_not_di_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b")) + (match_operand:DI 2 "register_operand" "r,b")))] + "TARGET_ARCH64" + "@ + orn\\t%2, %1, %0 + fornot1\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_insn "*or_not_si" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (ior:SI (not:SI (match_operand:SI 1 "register_operand" "r,d")) + (match_operand:SI 2 "register_operand" "r,d")))] + "" + "@ + orn\\t%2, %1, %0 + fornot1s\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_expand "xordi3" + [(set (match_operand:DI 0 "register_operand" "") + (xor:DI (match_operand:DI 1 "arith_double_operand" "") + (match_operand:DI 2 "arith_double_operand" "")))] + "" + "") + +(define_insn "*xordi3_sp32" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (xor:DI (match_operand:DI 1 "arith_double_operand" "%r,b") + (match_operand:DI 2 "arith_double_operand" "rHI,b")))] + "! TARGET_ARCH64" + "@ + # + fxor\\t%1, %2, %0" + [(set_attr "length" "2,1") + (set_attr "type" "ialu,fp")]) + +(define_insn "*xordi3_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (xor:DI (match_operand:DI 1 "arith_double_operand" "%rJ,b") + (match_operand:DI 2 "arith_double_operand" "rHI,b")))] + "TARGET_ARCH64" + "@ + xor\\t%r1, %2, %0 + fxor\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_insn "*xordi3_sp64_dbl" + [(set (match_operand:DI 0 "register_operand" "=r") + (xor:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "const64_operand" "")))] + "(TARGET_ARCH64 + && HOST_BITS_PER_WIDE_INT != 64)" + "xor\\t%1, %2, %0" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_insn "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (xor:SI (match_operand:SI 1 "arith_operand" "%rJ,d") + (match_operand:SI 2 "arith_operand" "rI,d")))] + "" + "@ + xor\\t%r1, %2, %0 + fxors\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (xor:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "" ""))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "GET_CODE (operands[2]) == CONST_INT + && !SMALL_INT32 (operands[2]) + && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" + [(set (match_dup 3) (match_dup 4)) + (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))] + " +{ + operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff); +}") + +(define_split + [(set (match_operand:SI 0 "register_operand" "") + (not:SI (xor:SI (match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "" "")))) + (clobber (match_operand:SI 3 "register_operand" ""))] + "GET_CODE (operands[2]) == CONST_INT + && !SMALL_INT32 (operands[2]) + && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" + [(set (match_dup 3) (match_dup 4)) + (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))] + " +{ + operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff); +}") + +;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b). +;; Combine now canonicalizes to the rightmost expression. +(define_insn "*xor_not_di_sp32" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (not:DI (xor:DI (match_operand:DI 1 "register_operand" "r,b") + (match_operand:DI 2 "register_operand" "r,b"))))] + "! TARGET_ARCH64" + "@ + # + fxnor\\t%1, %2, %0" + [(set_attr "length" "2,1") + (set_attr "type" "ialu,fp")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (not:DI (xor:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" ""))))] + "! TARGET_ARCH64 + && reload_completed + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32))" + [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5)))) + (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + operands[3] = gen_highpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[1]); + operands[5] = gen_highpart (SImode, operands[2]); + operands[6] = gen_lowpart (SImode, operands[0]); + operands[7] = gen_lowpart (SImode, operands[1]); + operands[8] = gen_lowpart (SImode, operands[2]);") + +(define_insn "*xor_not_di_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,b") + (match_operand:DI 2 "arith_double_operand" "rHI,b"))))] + "TARGET_ARCH64" + "@ + xnor\\t%r1, %2, %0 + fxnor\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +(define_insn "*xor_not_si" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,d") + (match_operand:SI 2 "arith_operand" "rI,d"))))] + "" + "@ + xnor\\t%r1, %2, %0 + fxnors\\t%1, %2, %0" + [(set_attr "type" "ialu,fp") + (set_attr "length" "1,1")]) + +;; These correspond to the above in the case where we also (or only) +;; want to set the condition code. + +(define_insn "*cmp_cc_arith_op" + [(set (reg:CC 100) + (compare:CC + (match_operator:SI 2 "cc_arithop" + [(match_operand:SI 0 "arith_operand" "%r") + (match_operand:SI 1 "arith_operand" "rI")]) + (const_int 0)))] + "! TARGET_LIVE_G0" + "%A2cc\\t%0, %1, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_arith_op" + [(set (reg:CCX 100) + (compare:CCX + (match_operator:DI 2 "cc_arithop" + [(match_operand:DI 0 "arith_double_operand" "%r") + (match_operand:DI 1 "arith_double_operand" "rHI")]) + (const_int 0)))] + "TARGET_ARCH64" + "%A2cc\\t%0, %1, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_arith_op_set" + [(set (reg:CC 100) + (compare:CC + (match_operator:SI 3 "cc_arithop" + [(match_operand:SI 1 "arith_operand" "%r") + (match_operand:SI 2 "arith_operand" "rI")]) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (match_dup 3))] + "" + "%A3cc\\t%1, %2, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_arith_op_set" + [(set (reg:CCX 100) + (compare:CCX + (match_operator:DI 3 "cc_arithop" + [(match_operand:DI 1 "arith_double_operand" "%r") + (match_operand:DI 2 "arith_double_operand" "rHI")]) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (match_dup 3))] + "TARGET_ARCH64" + "%A3cc\\t%1, %2, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_xor_not" + [(set (reg:CC 100) + (compare:CC + (not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ") + (match_operand:SI 1 "arith_operand" "rI"))) + (const_int 0)))] + "! TARGET_LIVE_G0" + "xnorcc\\t%r0, %1, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_xor_not" + [(set (reg:CCX 100) + (compare:CCX + (not:DI (xor:DI (match_operand:DI 0 "reg_or_0_operand" "%rJ") + (match_operand:DI 1 "arith_double_operand" "rHI"))) + (const_int 0)))] + "TARGET_ARCH64" + "xnorcc\\t%r0, %1, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_xor_not_set" + [(set (reg:CC 100) + (compare:CC + (not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") + (match_operand:SI 2 "arith_operand" "rI"))) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (not:SI (xor:SI (match_dup 1) (match_dup 2))))] + "" + "xnorcc\\t%r1, %2, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_xor_not_set" + [(set (reg:CCX 100) + (compare:CCX + (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") + (match_operand:DI 2 "arith_double_operand" "rHI"))) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (not:DI (xor:DI (match_dup 1) (match_dup 2))))] + "TARGET_ARCH64" + "xnorcc\\t%r1, %2, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_arith_op_not" + [(set (reg:CC 100) + (compare:CC + (match_operator:SI 2 "cc_arithopn" + [(not:SI (match_operand:SI 0 "arith_operand" "rI")) + (match_operand:SI 1 "reg_or_0_operand" "rJ")]) + (const_int 0)))] + "! TARGET_LIVE_G0" + "%B2cc\\t%r1, %0, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_arith_op_not" + [(set (reg:CCX 100) + (compare:CCX + (match_operator:DI 2 "cc_arithopn" + [(not:DI (match_operand:DI 0 "arith_double_operand" "rHI")) + (match_operand:DI 1 "reg_or_0_operand" "rJ")]) + (const_int 0)))] + "TARGET_ARCH64" + "%B2cc\\t%r1, %0, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_arith_op_not_set" + [(set (reg:CC 100) + (compare:CC + (match_operator:SI 3 "cc_arithopn" + [(not:SI (match_operand:SI 1 "arith_operand" "rI")) + (match_operand:SI 2 "reg_or_0_operand" "rJ")]) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (match_dup 3))] + "" + "%B3cc\\t%r2, %1, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_arith_op_not_set" + [(set (reg:CCX 100) + (compare:CCX + (match_operator:DI 3 "cc_arithopn" + [(not:DI (match_operand:DI 1 "arith_double_operand" "rHI")) + (match_operand:DI 2 "reg_or_0_operand" "rJ")]) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (match_dup 3))] + "TARGET_ARCH64" + "%B3cc\\t%r2, %1, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +;; We cannot use the "neg" pseudo insn because the Sun assembler +;; does not know how to make it work for constants. + +(define_expand "negdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (neg:DI (match_operand:DI 1 "register_operand" "r")))] + "" + " +{ + if (! TARGET_ARCH64) + { + emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, + gen_rtx_SET (VOIDmode, operand0, + gen_rtx_NEG (DImode, operand1)), + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (CCmode, SPARC_ICC_REG))))); + DONE; + } +}") + +(define_insn "*negdi2_sp32" + [(set (match_operand:DI 0 "register_operand" "=r") + (neg:DI (match_operand:DI 1 "register_operand" "r"))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64 + && ! TARGET_LIVE_G0" + "#" + [(set_attr "type" "unary") + (set_attr "length" "2")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (neg:DI (match_operand:DI 1 "register_operand" ""))) + (clobber (reg:CC 100))] + "! TARGET_ARCH64 + && ! TARGET_LIVE_G0 + && reload_completed" + [(parallel [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5)) + (const_int 0))) + (set (match_dup 4) (minus:SI (const_int 0) (match_dup 5)))]) + (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3)) + (ltu:SI (reg:CC 100) (const_int 0))))] + "operands[2] = gen_highpart (SImode, operands[0]); + operands[3] = gen_highpart (SImode, operands[1]); + operands[4] = gen_lowpart (SImode, operands[0]); + operands[5] = gen_lowpart (SImode, operands[1]);") + +(define_insn "*negdi2_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (neg:DI (match_operand:DI 1 "register_operand" "r")))] + "TARGET_ARCH64" + "sub\\t%%g0, %1, %0" + [(set_attr "type" "unary") + (set_attr "length" "1")]) + +(define_expand "negsi2" + [(set (match_operand:SI 0 "register_operand" "") + (neg:SI (match_operand:SI 1 "arith_operand" "")))] + "" + " +{ + if (TARGET_LIVE_G0) + { + rtx zero_reg = gen_reg_rtx (SImode); + + emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_MINUS (SImode, zero_reg, + operands[1]))); + DONE; + } +}") + +(define_insn "*negsi2_not_liveg0" + [(set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] + "! TARGET_LIVE_G0" + "sub\\t%%g0, %1, %0" + [(set_attr "type" "unary") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_neg" + [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI")) + (const_int 0)))] + "! TARGET_LIVE_G0" + "subcc\\t%%g0, %0, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_neg" + [(set (reg:CCX_NOOV 100) + (compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_double_operand" "rHI")) + (const_int 0)))] + "TARGET_ARCH64" + "subcc\\t%%g0, %0, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_set_neg" + [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (neg:SI (match_operand:SI 1 "arith_operand" "rI")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (neg:SI (match_dup 1)))] + "! TARGET_LIVE_G0" + "subcc\\t%%g0, %1, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_set_neg" + [(set (reg:CCX_NOOV 100) + (compare:CCX_NOOV (neg:DI (match_operand:DI 1 "arith_double_operand" "rHI")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (neg:DI (match_dup 1)))] + "TARGET_ARCH64" + "subcc\\t%%g0, %1, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +;; We cannot use the "not" pseudo insn because the Sun assembler +;; does not know how to make it work for constants. +(define_expand "one_cmpldi2" + [(set (match_operand:DI 0 "register_operand" "") + (not:DI (match_operand:DI 1 "register_operand" "")))] + "" + "") + +(define_insn "*one_cmpldi2_sp32" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (not:DI (match_operand:DI 1 "register_operand" "r,b")))] + "! TARGET_ARCH64" + "@ + # + fnot1\\t%1, %0" + [(set_attr "type" "unary,fp") + (set_attr "length" "2,1")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (not:DI (match_operand:DI 1 "register_operand" "")))] + "! TARGET_ARCH64 + && reload_completed + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32))" + [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0)))) + (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + operands[2] = gen_highpart (SImode, operands[0]); + operands[3] = gen_highpart (SImode, operands[1]); + operands[4] = gen_lowpart (SImode, operands[0]); + operands[5] = gen_lowpart (SImode, operands[1]);") + +(define_insn "*one_cmpldi2_sp64" + [(set (match_operand:DI 0 "register_operand" "=r,b") + (not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))] + "TARGET_ARCH64" + "@ + xnor\\t%%g0, %1, %0 + fnot1\\t%1, %0" + [(set_attr "type" "unary,fp") + (set_attr "length" "1")]) + +(define_expand "one_cmplsi2" + [(set (match_operand:SI 0 "register_operand" "") + (not:SI (match_operand:SI 1 "arith_operand" "")))] + "" + " +{ + if (TARGET_LIVE_G0 + && GET_CODE (operands[1]) == CONST_INT) + { + rtx zero_reg = gen_reg_rtx (SImode); + + emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx)); + emit_insn (gen_rtx_SET (VOIDmode, + operands[0], + gen_rtx_NOT (SImode, + gen_rtx_XOR (SImode, + zero_reg, + operands[1])))); + DONE; + } +}") + +(define_insn "*one_cmplsi2_not_liveg0" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (not:SI (match_operand:SI 1 "arith_operand" "rI,d")))] + "! TARGET_LIVE_G0" + "@ + xnor\\t%%g0, %1, %0 + fnot1s\\t%1, %0" + [(set_attr "type" "unary,fp") + (set_attr "length" "1,1")]) + +(define_insn "*one_cmplsi2_liveg0" + [(set (match_operand:SI 0 "register_operand" "=r,d") + (not:SI (match_operand:SI 1 "arith_operand" "r,d")))] + "TARGET_LIVE_G0" + "@ + xnor\\t%1, 0, %0 + fnot1s\\t%1, %0" + [(set_attr "type" "unary,fp") + (set_attr "length" "1,1")]) + +(define_insn "*cmp_cc_not" + [(set (reg:CC 100) + (compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI")) + (const_int 0)))] + "! TARGET_LIVE_G0" + "xnorcc\\t%%g0, %0, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_not" + [(set (reg:CCX 100) + (compare:CCX (not:DI (match_operand:DI 0 "arith_double_operand" "rHI")) + (const_int 0)))] + "TARGET_ARCH64" + "xnorcc\\t%%g0, %0, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_set_not" + [(set (reg:CC 100) + (compare:CC (not:SI (match_operand:SI 1 "arith_operand" "rI")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (not:SI (match_dup 1)))] + "! TARGET_LIVE_G0" + "xnorcc\\t%%g0, %1, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_ccx_set_not" + [(set (reg:CCX 100) + (compare:CCX (not:DI (match_operand:DI 1 "arith_double_operand" "rHI")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (not:DI (match_dup 1)))] + "TARGET_ARCH64" + "xnorcc\\t%%g0, %1, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +;; Floating point arithmetic instructions. + +(define_insn "addtf3" + [(set (match_operand:TF 0 "register_operand" "=e") + (plus:TF (match_operand:TF 1 "register_operand" "e") + (match_operand:TF 2 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "faddq\\t%1, %2, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "adddf3" + [(set (match_operand:DF 0 "register_operand" "=e") + (plus:DF (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU" + "faddd\\t%1, %2, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "addsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (plus:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_FPU" + "fadds\\t%1, %2, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "subtf3" + [(set (match_operand:TF 0 "register_operand" "=e") + (minus:TF (match_operand:TF 1 "register_operand" "e") + (match_operand:TF 2 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fsubq\\t%1, %2, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "subdf3" + [(set (match_operand:DF 0 "register_operand" "=e") + (minus:DF (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU" + "fsubd\\t%1, %2, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "subsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (minus:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_FPU" + "fsubs\\t%1, %2, %0" + [(set_attr "type" "fp") + (set_attr "length" "1")]) + +(define_insn "multf3" + [(set (match_operand:TF 0 "register_operand" "=e") + (mult:TF (match_operand:TF 1 "register_operand" "e") + (match_operand:TF 2 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fmulq\\t%1, %2, %0" + [(set_attr "type" "fpmul") + (set_attr "length" "1")]) + +(define_insn "muldf3" + [(set (match_operand:DF 0 "register_operand" "=e") + (mult:DF (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU" + "fmuld\\t%1, %2, %0" + [(set_attr "type" "fpmul") + (set_attr "length" "1")]) + +(define_insn "mulsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (mult:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_FPU" + "fmuls\\t%1, %2, %0" + [(set_attr "type" "fpmul") + (set_attr "length" "1")]) + +(define_insn "*muldf3_extend" + [(set (match_operand:DF 0 "register_operand" "=e") + (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f")) + (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))] + "(TARGET_V8 || TARGET_V9) && TARGET_FPU" + "fsmuld\\t%1, %2, %0" + [(set_attr "type" "fpmul") + (set_attr "length" "1")]) + +(define_insn "*multf3_extend" + [(set (match_operand:TF 0 "register_operand" "=e") + (mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e")) + (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))] + "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD" + "fdmulq\\t%1, %2, %0" + [(set_attr "type" "fpmul") + (set_attr "length" "1")]) + +;; don't have timing for quad-prec. divide. +(define_insn "divtf3" + [(set (match_operand:TF 0 "register_operand" "=e") + (div:TF (match_operand:TF 1 "register_operand" "e") + (match_operand:TF 2 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fdivq\\t%1, %2, %0" + [(set_attr "type" "fpdivd") + (set_attr "length" "1")]) + +(define_insn "divdf3" + [(set (match_operand:DF 0 "register_operand" "=e") + (div:DF (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU" + "fdivd\\t%1, %2, %0" + [(set_attr "type" "fpdivd") + (set_attr "length" "1")]) + +(define_insn "divsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (div:SF (match_operand:SF 1 "register_operand" "f") + (match_operand:SF 2 "register_operand" "f")))] + "TARGET_FPU" + "fdivs\\t%1, %2, %0" + [(set_attr "type" "fpdivs") + (set_attr "length" "1")]) + +(define_expand "negtf2" + [(set (match_operand:TF 0 "register_operand" "=e,e") + (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] + "TARGET_FPU" + "") + +(define_insn "*negtf2_notv9" + [(set (match_operand:TF 0 "register_operand" "=e,e") + (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] + ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. + "TARGET_FPU + && ! TARGET_V9" + "@ + fnegs\\t%0, %0 + #" + [(set_attr "type" "fpmove") + (set_attr "length" "1,2")]) + +(define_split + [(set (match_operand:TF 0 "register_operand" "") + (neg:TF (match_operand:TF 1 "register_operand" "")))] + "TARGET_FPU + && ! TARGET_V9 + && reload_completed + && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" + [(set (match_dup 2) (neg:SF (match_dup 3))) + (set (match_dup 4) (match_dup 5)) + (set (match_dup 6) (match_dup 7))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + if (GET_CODE (operands[1]) == SUBREG) + operands[1] = alter_subreg (operands[1]); + operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); + operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); + operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); + operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); + operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); + operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + +(define_insn "*negtf2_v9" + [(set (match_operand:TF 0 "register_operand" "=e,e") + (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] + ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. + "TARGET_FPU && TARGET_V9" + "@ + fnegd\\t%0, %0 + #" + [(set_attr "type" "fpmove") + (set_attr "length" "1,2")]) + +(define_split + [(set (match_operand:TF 0 "register_operand" "") + (neg:TF (match_operand:TF 1 "register_operand" "")))] + "TARGET_FPU + && TARGET_V9 + && reload_completed + && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" + [(set (match_dup 2) (neg:DF (match_dup 3))) + (set (match_dup 4) (match_dup 5))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + if (GET_CODE (operands[1]) == SUBREG) + operands[1] = alter_subreg (operands[1]); + operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); + operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); + operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); + operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + +(define_expand "negdf2" + [(set (match_operand:DF 0 "register_operand" "") + (neg:DF (match_operand:DF 1 "register_operand" "")))] + "TARGET_FPU" + "") + +(define_insn "*negdf2_notv9" + [(set (match_operand:DF 0 "register_operand" "=e,e") + (neg:DF (match_operand:DF 1 "register_operand" "0,e")))] + "TARGET_FPU && ! TARGET_V9" + "@ + fnegs\\t%0, %0 + #" + [(set_attr "type" "fpmove") + (set_attr "length" "1,2")]) + +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (neg:DF (match_operand:DF 1 "register_operand" "")))] + "TARGET_FPU + && ! TARGET_V9 + && reload_completed + && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" + [(set (match_dup 2) (neg:SF (match_dup 3))) + (set (match_dup 4) (match_dup 5))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + if (GET_CODE (operands[1]) == SUBREG) + operands[1] = alter_subreg (operands[1]); + operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); + operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); + operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); + operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);") + +(define_insn "*negdf2_v9" + [(set (match_operand:DF 0 "register_operand" "=e") + (neg:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_V9" + "fnegd\\t%1, %0" + [(set_attr "type" "fpmove") + (set_attr "length" "1")]) + +(define_insn "negsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (neg:SF (match_operand:SF 1 "register_operand" "f")))] + "TARGET_FPU" + "fnegs\\t%1, %0" + [(set_attr "type" "fpmove") + (set_attr "length" "1")]) + +(define_expand "abstf2" + [(set (match_operand:TF 0 "register_operand" "") + (abs:TF (match_operand:TF 1 "register_operand" "")))] + "TARGET_FPU" + "") + +(define_insn "*abstf2_notv9" + [(set (match_operand:TF 0 "register_operand" "=e,e") + (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] + ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. + "TARGET_FPU && ! TARGET_V9" + "@ + fabss\\t%0, %0 + #" + [(set_attr "type" "fpmove") + (set_attr "length" "1,2")]) + +(define_split + [(set (match_operand:TF 0 "register_operand" "=e,e") + (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] + "TARGET_FPU + && ! TARGET_V9 + && reload_completed + && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" + [(set (match_dup 2) (abs:SF (match_dup 3))) + (set (match_dup 4) (match_dup 5)) + (set (match_dup 6) (match_dup 7))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + if (GET_CODE (operands[1]) == SUBREG) + operands[1] = alter_subreg (operands[1]); + operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); + operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); + operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); + operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); + operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); + operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + +(define_insn "*abstf2_hq_v9" + [(set (match_operand:TF 0 "register_operand" "=e,e") + (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] + "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD" + "@ + fabsd\\t%0, %0 + fabsq\\t%1, %0" + [(set_attr "type" "fpmove") + (set_attr "length" "1")]) + +(define_insn "*abstf2_v9" + [(set (match_operand:TF 0 "register_operand" "=e,e") + (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] + "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD" + "@ + fabsd\\t%0, %0 + #" + [(set_attr "type" "fpmove") + (set_attr "length" "1,2")]) + +(define_split + [(set (match_operand:TF 0 "register_operand" "=e,e") + (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] + "TARGET_FPU + && TARGET_V9 + && reload_completed + && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" + [(set (match_dup 2) (abs:DF (match_dup 3))) + (set (match_dup 4) (match_dup 5))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + if (GET_CODE (operands[1]) == SUBREG) + operands[1] = alter_subreg (operands[1]); + operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); + operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); + operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); + operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + +(define_expand "absdf2" + [(set (match_operand:DF 0 "register_operand" "") + (abs:DF (match_operand:DF 1 "register_operand" "")))] + "TARGET_FPU" + "") + +(define_insn "*absdf2_notv9" + [(set (match_operand:DF 0 "register_operand" "=e,e") + (abs:DF (match_operand:DF 1 "register_operand" "0,e")))] + "TARGET_FPU && ! TARGET_V9" + "@ + fabss\\t%0, %0 + #" + [(set_attr "type" "fpmove") + (set_attr "length" "1,2")]) + +(define_split + [(set (match_operand:DF 0 "register_operand" "=e,e") + (abs:DF (match_operand:DF 1 "register_operand" "0,e")))] + "TARGET_FPU + && ! TARGET_V9 + && reload_completed + && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" + [(set (match_dup 2) (abs:SF (match_dup 3))) + (set (match_dup 4) (match_dup 5))] + "if (GET_CODE (operands[0]) == SUBREG) + operands[0] = alter_subreg (operands[0]); + if (GET_CODE (operands[1]) == SUBREG) + operands[1] = alter_subreg (operands[1]); + operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); + operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); + operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); + operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);") + +(define_insn "*absdf2_v9" + [(set (match_operand:DF 0 "register_operand" "=e") + (abs:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_V9" + "fabsd\\t%1, %0" + [(set_attr "type" "fpmove") + (set_attr "length" "1")]) + +(define_insn "abssf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (abs:SF (match_operand:SF 1 "register_operand" "f")))] + "TARGET_FPU" + "fabss\\t%1, %0" + [(set_attr "type" "fpmove") + (set_attr "length" "1")]) + +(define_insn "sqrttf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (sqrt:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fsqrtq\\t%1, %0" + [(set_attr "type" "fpsqrt") + (set_attr "length" "1")]) + +(define_insn "sqrtdf2" + [(set (match_operand:DF 0 "register_operand" "=e") + (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU" + "fsqrtd\\t%1, %0" + [(set_attr "type" "fpsqrt") + (set_attr "length" "1")]) + +(define_insn "sqrtsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] + "TARGET_FPU" + "fsqrts\\t%1, %0" + [(set_attr "type" "fpsqrt") + (set_attr "length" "1")]) + +;;- arithmetic shift instructions + +(define_insn "ashlsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"sll\\t%1, %2, %0\"; +}" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +;; We special case multiplication by two, as add can be done +;; in both ALUs, while shift only in IEU0 on UltraSPARC. +(define_insn "*ashlsi3_const1" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (match_operand:SI 1 "register_operand" "r") + (const_int 1)))] + "" + "add\\t%1, %1, %0" + [(set_attr "type" "binary") + (set_attr "length" "1")]) + +(define_expand "ashldi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "TARGET_ARCH64 || TARGET_V8PLUS" + " +{ + if (! TARGET_ARCH64) + { + if (GET_CODE (operands[2]) == CONST_INT) + FAIL; + emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}") + +;; We special case multiplication by two, as add can be done +;; in both ALUs, while shift only in IEU0 on UltraSPARC. +(define_insn "*ashldi3_const1" + [(set (match_operand:DI 0 "register_operand" "=r") + (ashift:DI (match_operand:DI 1 "register_operand" "r") + (const_int 1)))] + "TARGET_ARCH64" + "add\\t%1, %1, %0" + [(set_attr "type" "binary") + (set_attr "length" "1")]) + +(define_insn "*ashldi3_sp64" + [(set (match_operand:DI 0 "register_operand" "=r") + (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "TARGET_ARCH64" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"sllx\\t%1, %2, %0\"; +}" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +;; XXX UGH! +(define_insn "ashldi3_v8plus" + [(set (match_operand:DI 0 "register_operand" "=&h,&h,r") + (ashift:DI (match_operand:DI 1 "arith_operand" "rI,0,rI") + (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) + (clobber (match_scratch:SI 3 "=X,X,&h"))] + "TARGET_V8PLUS" + "*return sparc_v8plus_shift (operands, insn, \"sllx\");" + [(set_attr "length" "5,5,6")]) + +;; Optimize (1LL<<x)-1 +;; XXX this also needs to be fixed to handle equal subregs +;; XXX first before we could re-enable it. +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=h") + (plus:DI (ashift:DI (const_int 1) + (match_operand:SI 2 "arith_operand" "rI")) + (const_int -1)))] + "0 && TARGET_V8PLUS" + "* +{ + if (GET_CODE (operands[2]) == REG && REGNO (operands[2]) == REGNO (operands[0])) + return \"mov 1,%L0\;sllx %L0,%2,%L0\;sub %L0,1,%L0\;srlx %L0,32,%H0\"; + return \"mov 1,%H0\;sllx %H0,%2,%L0\;sub %L0,1,%L0\;srlx %L0,32,%H0\"; +}" + [(set_attr "length" "4")]) + +(define_insn "*cmp_cc_ashift_1" + [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r") + (const_int 1)) + (const_int 0)))] + "! TARGET_LIVE_G0" + "addcc\\t%0, %0, %%g0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "*cmp_cc_set_ashift_1" + [(set (reg:CC_NOOV 100) + (compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r") + (const_int 1)) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (match_dup 1) (const_int 1)))] + "" + "addcc\\t%1, %1, %0" + [(set_attr "type" "compare") + (set_attr "length" "1")]) + +(define_insn "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"sra\\t%1, %2, %0\"; +}" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +(define_insn "*ashrsi3_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "r"))))] + "TARGET_ARCH64" + "sra\\t%1, %2, %0" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +;; This handles the case as above, but with constant shift instead of +;; register. Combiner "simplifies" it for us a little bit though. +(define_insn "*ashrsi3_extend2" + [(set (match_operand:DI 0 "register_operand" "=r") + (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0) + (const_int 32)) + (match_operand:SI 2 "small_int_or_double" "n")))] + "TARGET_ARCH64 + && ((GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) < 64) + || (GET_CODE (operands[2]) == CONST_DOUBLE + && !CONST_DOUBLE_HIGH (operands[2]) + && CONST_DOUBLE_LOW (operands[2]) >= 32 + && CONST_DOUBLE_LOW (operands[2]) < 64))" + "* +{ + operands[2] = GEN_INT (INTVAL (operands[2]) - 32); + + return \"sra\\t%1, %2, %0\"; +}" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +(define_expand "ashrdi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "TARGET_ARCH64 || TARGET_V8PLUS" + " +{ + if (! TARGET_ARCH64) + { + if (GET_CODE (operands[2]) == CONST_INT) + FAIL; /* prefer generic code in this case */ + emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "TARGET_ARCH64" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"srax\\t%1, %2, %0\"; +}" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +;; XXX +(define_insn "ashrdi3_v8plus" + [(set (match_operand:DI 0 "register_operand" "=&h,&h,r") + (ashiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI") + (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) + (clobber (match_scratch:SI 3 "=X,X,&h"))] + "TARGET_V8PLUS" + "*return sparc_v8plus_shift (operands, insn, \"srax\");" + [(set_attr "length" "5,5,6")]) + +(define_insn "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + + return \"srl\\t%1, %2, %0\"; +}" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +;; This handles the case where +;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))), +;; but combiner "simplifies" it for us. +(define_insn "*lshrsi3_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "r")) 0) + (match_operand 3 "" "")))] + "TARGET_ARCH64 + && ((GET_CODE (operands[3]) == CONST_DOUBLE + && CONST_DOUBLE_HIGH (operands[3]) == 0 + && CONST_DOUBLE_LOW (operands[3]) == 0xffffffff) +#if HOST_BITS_PER_WIDE_INT >= 64 + || (GET_CODE (operands[3]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff) +#endif + )" + "srl\\t%1, %2, %0" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +;; This handles the case where +;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32)) +;; but combiner "simplifies" it for us. +(define_insn "*lshrsi3_extend2" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0) + (match_operand 2 "small_int_or_double" "n") + (const_int 32)))] + "TARGET_ARCH64 + && ((GET_CODE (operands[2]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32) + || (GET_CODE (operands[2]) == CONST_DOUBLE + && CONST_DOUBLE_HIGH (operands[2]) == 0 + && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))" + "* +{ + operands[2] = GEN_INT (32 - INTVAL (operands[2])); + + return \"srl\\t%1, %2, %0\"; +}" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +(define_expand "lshrdi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "TARGET_ARCH64 || TARGET_V8PLUS" + " +{ + if (! TARGET_ARCH64) + { + if (GET_CODE (operands[2]) == CONST_INT) + FAIL; + emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2])); + DONE; + } +}") + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI")))] + "TARGET_ARCH64" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + + return \"srlx\\t%1, %2, %0\"; +}" + [(set_attr "type" "shift") + (set_attr "length" "1")]) + +;; XXX +(define_insn "lshrdi3_v8plus" + [(set (match_operand:DI 0 "register_operand" "=&h,&h,r") + (lshiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI") + (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) + (clobber (match_scratch:SI 3 "=X,X,&h"))] + "TARGET_V8PLUS" + "*return sparc_v8plus_shift (operands, insn, \"srlx\");" + [(set_attr "length" "5,5,6")]) + +;; Unconditional and other jump instructions +;; On the Sparc, by setting the annul bit on an unconditional branch, the +;; following insn is never executed. This saves us a nop. Dbx does not +;; handle such branches though, so we only use them when optimizing. +(define_insn "jump" + [(set (pc) (label_ref (match_operand 0 "" "")))] + "" + "* +{ + /* TurboSparc is reported to have problems with + with + foo: b,a foo + i.e. an empty loop with the annul bit set. The workaround is to use + foo: b foo; nop + instead. */ + + if (! TARGET_V9 && flag_delayed_branch + && (insn_addresses[INSN_UID (operands[0])] + == insn_addresses[INSN_UID (insn)])) + return \"b\\t%l0%#\"; + else + return TARGET_V9 ? \"ba,pt%*\\t%%xcc, %l0%(\" : \"b%*\\t%l0%(\"; +}" + [(set_attr "type" "uncond_branch")]) + +(define_expand "tablejump" + [(parallel [(set (pc) (match_operand 0 "register_operand" "r")) + (use (label_ref (match_operand 1 "" "")))])] + "" + " +{ + if (GET_MODE (operands[0]) != CASE_VECTOR_MODE) + abort (); + + /* In pic mode, our address differences are against the base of the + table. Add that base value back in; CSE ought to be able to combine + the two address loads. */ + if (flag_pic) + { + rtx tmp, tmp2; + tmp = gen_rtx_LABEL_REF (Pmode, operands[1]); + tmp2 = operands[0]; + if (CASE_VECTOR_MODE != Pmode) + tmp2 = gen_rtx_SIGN_EXTEND (Pmode, tmp2); + tmp = gen_rtx_PLUS (Pmode, tmp2, tmp); + operands[0] = memory_address (Pmode, tmp); + } +}") + +(define_insn "*tablejump_sp32" + [(set (pc) (match_operand:SI 0 "address_operand" "p")) + (use (label_ref (match_operand 1 "" "")))] + "! TARGET_PTR64" + "jmp\\t%a0%#" + [(set_attr "type" "uncond_branch")]) + +(define_insn "*tablejump_sp64" + [(set (pc) (match_operand:DI 0 "address_operand" "p")) + (use (label_ref (match_operand 1 "" "")))] + "TARGET_PTR64" + "jmp\\t%a0%#" + [(set_attr "type" "uncond_branch")]) + +;; This pattern recognizes the "instruction" that appears in +;; a function call that wants a structure value, +;; to inform the called function if compiled with Sun CC. +;(define_insn "*unimp_insn" +; [(match_operand:SI 0 "immediate_operand" "")] +; "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) > 0" +; "unimp\\t%0" +; [(set_attr "type" "marker")]) + +;;- jump to subroutine +(define_expand "call" + ;; Note that this expression is not used for generating RTL. + ;; All the RTL is generated explicitly below. + [(call (match_operand 0 "call_operand" "") + (match_operand 3 "" "i"))] + ;; operands[2] is next_arg_register + ;; operands[3] is struct_value_size_rtx. + "" + " +{ + rtx fn_rtx, nregs_rtx; + + if (GET_MODE (operands[0]) != FUNCTION_MODE) + abort (); + + if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF) + { + /* This is really a PIC sequence. We want to represent + it as a funny jump so its delay slots can be filled. + + ??? But if this really *is* a CALL, will not it clobber the + call-clobbered registers? We lose this if it is a JUMP_INSN. + Why cannot we have delay slots filled if it were a CALL? */ + + if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0) + emit_jump_insn + (gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (3, + gen_rtx_SET (VOIDmode, pc_rtx, + XEXP (operands[0], 0)), + operands[3], + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (Pmode, 15))))); + else + emit_jump_insn + (gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, + gen_rtx_SET (VOIDmode, pc_rtx, + XEXP (operands[0], 0)), + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (Pmode, 15))))); + goto finish_call; + } + + fn_rtx = operands[0]; + + /* Count the number of parameter registers being used by this call. + if that argument is NULL, it means we are using them all, which + means 6 on the sparc. */ +#if 0 + if (operands[2]) + nregs_rtx = GEN_INT (REGNO (operands[2]) - 8); + else + nregs_rtx = GEN_INT (6); +#else + nregs_rtx = const0_rtx; +#endif + + if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0) + emit_call_insn + (gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (3, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx), + operands[3], + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (Pmode, 15))))); + else + emit_call_insn + (gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx), + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_REG (Pmode, 15))))); + + finish_call: +#if 0 + /* If this call wants a structure value, + emit an unimp insn to let the called function know about this. */ + if (! TARGET_ARCH64 && INTVAL (operands[3]) > 0) + { + rtx insn = emit_insn (operands[3]); + SCHED_GROUP_P (insn) = 1; + } +#endif + + DONE; +}") + +;; We can't use the same pattern for these two insns, because then registers +;; in the address may not be properly reloaded. + +(define_insn "*call_address_sp32" + [(call (mem:SI (match_operand:SI 0 "address_operand" "p")) + (match_operand 1 "" "")) + (clobber (reg:SI 15))] + ;;- Do not use operand 1 for most machines. + "! TARGET_PTR64" + "call\\t%a0, %1%#" + [(set_attr "type" "call")]) + +(define_insn "*call_symbolic_sp32" + [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s")) + (match_operand 1 "" "")) + (clobber (reg:SI 15))] + ;;- Do not use operand 1 for most machines. + "! TARGET_PTR64" + "call\\t%a0, %1%#" + [(set_attr "type" "call")]) + +(define_insn "*call_address_sp64" + [(call (mem:SI (match_operand:DI 0 "address_operand" "p")) + (match_operand 1 "" "")) + (clobber (reg:DI 15))] + ;;- Do not use operand 1 for most machines. + "TARGET_PTR64" + "call\\t%a0, %1%#" + [(set_attr "type" "call")]) + +(define_insn "*call_symbolic_sp64" + [(call (mem:SI (match_operand:DI 0 "symbolic_operand" "s")) + (match_operand 1 "" "")) + (clobber (reg:DI 15))] + ;;- Do not use operand 1 for most machines. + "TARGET_PTR64" + "call\\t%a0, %1%#" + [(set_attr "type" "call")]) + +;; This is a call that wants a structure value. +;; There is no such critter for v9 (??? we may need one anyway). +(define_insn "*call_address_struct_value_sp32" + [(call (mem:SI (match_operand:SI 0 "address_operand" "p")) + (match_operand 1 "" "")) + (match_operand 2 "immediate_operand" "") + (clobber (reg:SI 15))] + ;;- Do not use operand 1 for most machines. + "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0" + "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2" + [(set_attr "type" "call_no_delay_slot")]) + +;; This is a call that wants a structure value. +;; There is no such critter for v9 (??? we may need one anyway). +(define_insn "*call_symbolic_struct_value_sp32" + [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s")) + (match_operand 1 "" "")) + (match_operand 2 "immediate_operand" "") + (clobber (reg:SI 15))] + ;;- Do not use operand 1 for most machines. + "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0" + "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2" + [(set_attr "type" "call_no_delay_slot")]) + +;; This is a call that may want a structure value. This is used for +;; untyped_calls. +(define_insn "*call_address_untyped_struct_value_sp32" + [(call (mem:SI (match_operand:SI 0 "address_operand" "p")) + (match_operand 1 "" "")) + (match_operand 2 "immediate_operand" "") + (clobber (reg:SI 15))] + ;;- Do not use operand 1 for most machines. + "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" + "call\\t%a0, %1\\n\\tnop\\n\\tnop" + [(set_attr "type" "call_no_delay_slot")]) + +;; This is a call that wants a structure value. +(define_insn "*call_symbolic_untyped_struct_value_sp32" + [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s")) + (match_operand 1 "" "")) + (match_operand 2 "immediate_operand" "") + (clobber (reg:SI 15))] + ;;- Do not use operand 1 for most machines. + "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" + "call\\t%a0, %1\\n\\tnop\\n\\tnop" + [(set_attr "type" "call_no_delay_slot")]) + +(define_expand "call_value" + ;; Note that this expression is not used for generating RTL. + ;; All the RTL is generated explicitly below. + [(set (match_operand 0 "register_operand" "=rf") + (call (match_operand:SI 1 "" "") + (match_operand 4 "" "")))] + ;; operand 2 is stack_size_rtx + ;; operand 3 is next_arg_register + "" + " +{ + rtx fn_rtx, nregs_rtx; + rtvec vec; + + if (GET_MODE (operands[1]) != FUNCTION_MODE) + abort (); + + fn_rtx = operands[1]; + +#if 0 + if (operands[3]) + nregs_rtx = GEN_INT (REGNO (operands[3]) - 8); + else + nregs_rtx = GEN_INT (6); +#else + nregs_rtx = const0_rtx; +#endif + + vec = gen_rtvec (2, + gen_rtx_SET (VOIDmode, operands[0], + gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx)), + gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15))); + + emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec)); + + DONE; +}") + +(define_insn "*call_value_address_sp32" + [(set (match_operand 0 "" "=rf") + (call (mem:SI (match_operand:SI 1 "address_operand" "p")) + (match_operand 2 "" ""))) + (clobber (reg:SI 15))] + ;;- Do not use operand 2 for most machines. + "! TARGET_PTR64" + "call\\t%a1, %2%#" + [(set_attr "type" "call")]) + +(define_insn "*call_value_symbolic_sp32" + [(set (match_operand 0 "" "=rf") + (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s")) + (match_operand 2 "" ""))) + (clobber (reg:SI 15))] + ;;- Do not use operand 2 for most machines. + "! TARGET_PTR64" + "call\\t%a1, %2%#" + [(set_attr "type" "call")]) + +(define_insn "*call_value_address_sp64" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "address_operand" "p")) + (match_operand 2 "" ""))) + (clobber (reg:DI 15))] + ;;- Do not use operand 2 for most machines. + "TARGET_PTR64" + "call\\t%a1, %2%#" + [(set_attr "type" "call")]) + +(define_insn "*call_value_symbolic_sp64" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "symbolic_operand" "s")) + (match_operand 2 "" ""))) + (clobber (reg:DI 15))] + ;;- Do not use operand 2 for most machines. + "TARGET_PTR64" + "call\\t%a1, %2%#" + [(set_attr "type" "call")]) + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + int i; + + /* Pass constm1 to indicate that it may expect a structure value, but + we don't know what size it is. */ + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, constm1_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "" + [(set_attr "length" "0")]) + +;; Prepare to return any type including a structure value. + +(define_expand "untyped_return" + [(match_operand:BLK 0 "memory_operand" "") + (match_operand 1 "" "")] + "" + " +{ + rtx valreg1 = gen_rtx_REG (DImode, 24); + rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32); + rtx result = operands[0]; + + if (! TARGET_ARCH64) + { + rtx rtnreg = gen_rtx_REG (SImode, (current_function_uses_only_leaf_regs + ? 15 : 31)); + rtx value = gen_reg_rtx (SImode); + + /* Fetch the instruction where we will return to and see if it's an unimp + instruction (the most significant 10 bits will be zero). If so, + update the return address to skip the unimp instruction. */ + emit_move_insn (value, + gen_rtx_MEM (SImode, plus_constant (rtnreg, 8))); + emit_insn (gen_lshrsi3 (value, value, GEN_INT (22))); + emit_insn (gen_update_return (rtnreg, value)); + } + + /* Reload the function value registers. */ + emit_move_insn (valreg1, change_address (result, DImode, XEXP (result, 0))); + emit_move_insn (valreg2, + change_address (result, TARGET_ARCH64 ? TFmode : DFmode, + plus_constant (XEXP (result, 0), 8))); + + /* Put USE insns before the return. */ + emit_insn (gen_rtx_USE (VOIDmode, valreg1)); + emit_insn (gen_rtx_USE (VOIDmode, valreg2)); + + /* Construct the return. */ + expand_null_return (); + + DONE; +}") + +;; This is a bit of a hack. We're incrementing a fixed register (%i7), +;; and parts of the compiler don't want to believe that the add is needed. + +(define_insn "update_return" + [(unspec:SI [(match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "register_operand" "r")] 1)] + "! TARGET_ARCH64" + "cmp %1,0\;be,a .+8\;add %0,4,%0" + [(set_attr "type" "multi")]) + +(define_insn "return" + [(return) + (use (reg:SI 31))] + "! TARGET_EPILOGUE" + "* return output_return (operands);" + [(set_attr "type" "return")]) + +(define_peephole + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "arith_operand" "rI")) + (parallel [(return) + (use (reg:SI 31))])] + "sparc_return_peephole_ok (operands[0], operands[1])" + "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0") + +(define_insn "nop" + [(const_int 0)] + "" + "nop" + [(set_attr "type" "ialu") + (set_attr "length" "1")]) + +(define_expand "indirect_jump" + [(set (pc) (match_operand 0 "address_operand" "p"))] + "" + "") + +(define_insn "*branch_sp32" + [(set (pc) (match_operand:SI 0 "address_operand" "p"))] + "! TARGET_PTR64" + "jmp\\t%a0%#" + [(set_attr "type" "uncond_branch")]) + +(define_insn "*branch_sp64" + [(set (pc) (match_operand:DI 0 "address_operand" "p"))] + "TARGET_PTR64" + "jmp\\t%a0%#" + [(set_attr "type" "uncond_branch")]) + +;; ??? Doesn't work with -mflat. +(define_expand "nonlocal_goto" + [(match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "general_operand" "") + (match_operand:SI 2 "general_operand" "") + (match_operand:SI 3 "" "")] + "" + " +{ +#if 0 + rtx chain = operands[0]; +#endif + rtx fp = operands[1]; + rtx stack = operands[2]; + rtx lab = operands[3]; + rtx labreg; + + /* Trap instruction to flush all the register windows. */ + emit_insn (gen_flush_register_windows ()); + + /* Load the fp value for the containing fn into %fp. This is needed + because STACK refers to %fp. Note that virtual register instantiation + fails if the virtual %fp isn't set from a register. */ + if (GET_CODE (fp) != REG) + fp = force_reg (Pmode, fp); + emit_move_insn (virtual_stack_vars_rtx, fp); + + /* Find the containing function's current nonlocal goto handler, + which will do any cleanups and then jump to the label. */ + labreg = gen_rtx_REG (Pmode, 8); + emit_move_insn (labreg, lab); + + /* Restore %fp from stack pointer value for containing function. + The restore insn that follows will move this to %sp, + and reload the appropriate value into %fp. */ + emit_move_insn (frame_pointer_rtx, stack); + + /* USE of frame_pointer_rtx added for consistency; not clear if + really needed. */ + /*emit_insn (gen_rtx_USE (VOIDmode, frame_pointer_rtx));*/ + emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); + +#if 0 + /* Return, restoring reg window and jumping to goto handler. */ + if (TARGET_V9 && GET_CODE (chain) == CONST_INT + && ! (INTVAL (chain) & ~(HOST_WIDE_INT)0xffffffff)) + { + emit_insn (gen_goto_handler_and_restore_v9 (labreg, static_chain_rtx, + chain)); + emit_barrier (); + DONE; + } + /* Put in the static chain register the nonlocal label address. */ + emit_move_insn (static_chain_rtx, chain); +#endif + + emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx)); + emit_insn (gen_goto_handler_and_restore (labreg)); + emit_barrier (); + DONE; +}") + +;; Special trap insn to flush register windows. +(define_insn "flush_register_windows" + [(unspec_volatile [(const_int 0)] 1)] + "" + "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "goto_handler_and_restore" + [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)] + "" + "jmp\\t%0+0\\n\\trestore" + [(set_attr "type" "misc") + (set_attr "length" "2")]) + +;;(define_insn "goto_handler_and_restore_v9" +;; [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r") +;; (match_operand:SI 1 "register_operand" "=r,r") +;; (match_operand:SI 2 "const_int_operand" "I,n")] 3)] +;; "TARGET_V9 && ! TARGET_ARCH64" +;; "@ +;; return\\t%0+0\\n\\tmov\\t%2, %Y1 +;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" +;; [(set_attr "type" "misc") +;; (set_attr "length" "2,3")]) +;; +;;(define_insn "*goto_handler_and_restore_v9_sp64" +;; [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r") +;; (match_operand:DI 1 "register_operand" "=r,r") +;; (match_operand:SI 2 "const_int_operand" "I,n")] 3)] +;; "TARGET_V9 && TARGET_ARCH64" +;; "@ +;; return\\t%0+0\\n\\tmov\\t%2, %Y1 +;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" +;; [(set_attr "type" "misc") +;; (set_attr "length" "2,3")]) + +;; Pattern for use after a setjmp to store FP and the return register +;; into the stack area. + +(define_expand "setjmp" + [(const_int 0)] + "" + " +{ + if (TARGET_ARCH64) + emit_insn (gen_setjmp_64 ()); + else + emit_insn (gen_setjmp_32 ()); + DONE; +}") + +(define_expand "setjmp_32" + [(set (mem:SI (plus:SI (reg:SI 14) (const_int 56))) (match_dup 0)) + (set (mem:SI (plus:SI (reg:SI 14) (const_int 60))) (reg:SI 31))] + "" + " +{ operands[0] = frame_pointer_rtx; }") + +(define_expand "setjmp_64" + [(set (mem:DI (plus:DI (reg:DI 14) (const_int 112))) (match_dup 0)) + (set (mem:DI (plus:DI (reg:DI 14) (const_int 120))) (reg:DI 31))] + "" + " +{ operands[0] = frame_pointer_rtx; }") + +;; Special pattern for the FLUSH instruction. + +(define_insn "flush" + [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 4)] + "" + "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +;; find first set. + +;; The scan instruction searches from the most significant bit while ffs +;; searches from the least significant bit. The bit index and treatment of +;; zero also differ. It takes at least 7 instructions to get the proper +;; result. Here is an obvious 8 instruction sequence. + +;; XXX +(define_insn "ffssi2" + [(set (match_operand:SI 0 "register_operand" "=&r") + (ffs:SI (match_operand:SI 1 "register_operand" "r"))) + (clobber (match_scratch:SI 2 "=&r"))] + "TARGET_SPARCLITE || TARGET_SPARCLET" + "* +{ + if (TARGET_LIVE_G0) + output_asm_insn (\"and %%g0,0,%%g0\", operands); + return \"sub %%g0,%1,%0\;and %0,%1,%0\;scan %0,0,%0\;mov 32,%2\;sub %2,%0,%0\;sra %0,31,%2\;and %2,31,%2\;add %2,%0,%0\"; +}" + [(set_attr "type" "multi") + (set_attr "length" "8")]) + +;; ??? This should be a define expand, so that the extra instruction have +;; a chance of being optimized away. + +;; Disabled because none of the UltraSparcs implement popc. The HAL R1 +;; does, but no one uses that and we don't have a switch for it. +; +;(define_insn "ffsdi2" +; [(set (match_operand:DI 0 "register_operand" "=&r") +; (ffs:DI (match_operand:DI 1 "register_operand" "r"))) +; (clobber (match_scratch:DI 2 "=&r"))] +; "TARGET_ARCH64" +; "neg %1,%2\;xnor %1,%2,%2\;popc %2,%0\;movzr %1,0,%0" +; [(set_attr "type" "multi") +; (set_attr "length" "4")]) + + +;; Peepholes go at the end. + +;; Optimize consecutive loads or stores into ldd and std when possible. +;; The conditions in which we do this are very restricted and are +;; explained in the code for {registers,memory}_ok_for_ldd functions. + +(define_peephole + [(set (match_operand:SI 0 "memory_operand" "") + (const_int 0)) + (set (match_operand:SI 1 "memory_operand" "") + (const_int 0))] + "TARGET_V9 + && ! MEM_VOLATILE_P (operands[0]) + && ! MEM_VOLATILE_P (operands[1]) + && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[1], 0))" + "stx\\t%%g0, %0") + +(define_peephole + [(set (match_operand:SI 0 "memory_operand" "") + (const_int 0)) + (set (match_operand:SI 1 "memory_operand" "") + (const_int 0))] + "TARGET_V9 + && ! MEM_VOLATILE_P (operands[0]) + && ! MEM_VOLATILE_P (operands[1]) + && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[0], 0))" + "stx\\t%%g0, %1") + +(define_peephole + [(set (match_operand:SI 0 "register_operand" "=rf") + (match_operand:SI 1 "memory_operand" "")) + (set (match_operand:SI 2 "register_operand" "=rf") + (match_operand:SI 3 "memory_operand" ""))] + "registers_ok_for_ldd_peep (operands[0], operands[2]) + && ! MEM_VOLATILE_P (operands[1]) + && ! MEM_VOLATILE_P (operands[3]) + && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" + "ldd\\t%1, %0") + +(define_peephole + [(set (match_operand:SI 0 "memory_operand" "") + (match_operand:SI 1 "register_operand" "rf")) + (set (match_operand:SI 2 "memory_operand" "") + (match_operand:SI 3 "register_operand" "rf"))] + "registers_ok_for_ldd_peep (operands[1], operands[3]) + && ! MEM_VOLATILE_P (operands[0]) + && ! MEM_VOLATILE_P (operands[2]) + && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" + "std\\t%1, %0") + +(define_peephole + [(set (match_operand:SF 0 "register_operand" "=fr") + (match_operand:SF 1 "memory_operand" "")) + (set (match_operand:SF 2 "register_operand" "=fr") + (match_operand:SF 3 "memory_operand" ""))] + "registers_ok_for_ldd_peep (operands[0], operands[2]) + && ! MEM_VOLATILE_P (operands[1]) + && ! MEM_VOLATILE_P (operands[3]) + && addrs_ok_for_ldd_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" + "ldd\\t%1, %0") + +(define_peephole + [(set (match_operand:SF 0 "memory_operand" "") + (match_operand:SF 1 "register_operand" "fr")) + (set (match_operand:SF 2 "memory_operand" "") + (match_operand:SF 3 "register_operand" "fr"))] + "registers_ok_for_ldd_peep (operands[1], operands[3]) + && ! MEM_VOLATILE_P (operands[0]) + && ! MEM_VOLATILE_P (operands[2]) + && addrs_ok_for_ldd_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" + "std\\t%1, %0") + +(define_peephole + [(set (match_operand:SI 0 "register_operand" "=rf") + (match_operand:SI 1 "memory_operand" "")) + (set (match_operand:SI 2 "register_operand" "=rf") + (match_operand:SI 3 "memory_operand" ""))] + "registers_ok_for_ldd_peep (operands[2], operands[0]) + && ! MEM_VOLATILE_P (operands[3]) + && ! MEM_VOLATILE_P (operands[1]) + && addrs_ok_for_ldd_peep (XEXP (operands[3], 0), XEXP (operands[1], 0))" + "ldd\\t%3, %2") + +(define_peephole + [(set (match_operand:SI 0 "memory_operand" "") + (match_operand:SI 1 "register_operand" "rf")) + (set (match_operand:SI 2 "memory_operand" "") + (match_operand:SI 3 "register_operand" "rf"))] + "registers_ok_for_ldd_peep (operands[3], operands[1]) + && ! MEM_VOLATILE_P (operands[2]) + && ! MEM_VOLATILE_P (operands[0]) + && addrs_ok_for_ldd_peep (XEXP (operands[2], 0), XEXP (operands[0], 0))" + "std\\t%3, %2") + +(define_peephole + [(set (match_operand:SF 0 "register_operand" "=fr") + (match_operand:SF 1 "memory_operand" "")) + (set (match_operand:SF 2 "register_operand" "=fr") + (match_operand:SF 3 "memory_operand" ""))] + "registers_ok_for_ldd_peep (operands[2], operands[0]) + && ! MEM_VOLATILE_P (operands[3]) + && ! MEM_VOLATILE_P (operands[1]) + && addrs_ok_for_ldd_peep (XEXP (operands[3], 0), XEXP (operands[1], 0))" + "ldd\\t%3, %2") + +(define_peephole + [(set (match_operand:SF 0 "memory_operand" "") + (match_operand:SF 1 "register_operand" "fr")) + (set (match_operand:SF 2 "memory_operand" "") + (match_operand:SF 3 "register_operand" "fr"))] + "registers_ok_for_ldd_peep (operands[3], operands[1]) + && ! MEM_VOLATILE_P (operands[2]) + && ! MEM_VOLATILE_P (operands[0]) + && addrs_ok_for_ldd_peep (XEXP (operands[2], 0), XEXP (operands[0], 0))" + "std\\t%3, %2") + +;; Optimize the case of following a reg-reg move with a test +;; of reg just moved. Don't allow floating point regs for operand 0 or 1. +;; This can result from a float to fix conversion. + +(define_peephole + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "register_operand" "r")) + (set (reg:CC 100) + (compare:CC (match_operand:SI 2 "register_operand" "r") + (const_int 0)))] + "(rtx_equal_p (operands[2], operands[0]) + || rtx_equal_p (operands[2], operands[1])) + && ! FP_REG_P (operands[0]) + && ! FP_REG_P (operands[1])" + "orcc\\t%1, 0, %0") + +(define_peephole + [(set (match_operand:DI 0 "register_operand" "=r") + (match_operand:DI 1 "register_operand" "r")) + (set (reg:CCX 100) + (compare:CCX (match_operand:DI 2 "register_operand" "r") + (const_int 0)))] + "TARGET_ARCH64 + && (rtx_equal_p (operands[2], operands[0]) + || rtx_equal_p (operands[2], operands[1])) + && ! FP_REG_P (operands[0]) + && ! FP_REG_P (operands[1])" + "orcc\\t%1, 0, %0") + +;; Return peepholes. First the "normal" ones. +;; These are necessary to catch insns ending up in the epilogue delay list. + +(define_insn "*return_qi" + [(set (match_operand:QI 0 "restore_operand" "") + (match_operand:QI 1 "arith_operand" "rI")) + (return)] + "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "* +{ + if (! TARGET_ARCH64 && current_function_returns_struct) + return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT + || IN_OR_GLOBAL_P (operands[1]))) + return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + else + return \"ret\\n\\trestore %%g0, %1, %Y0\"; +}" + [(set_attr "type" "multi")]) + +(define_insn "*return_hi" + [(set (match_operand:HI 0 "restore_operand" "") + (match_operand:HI 1 "arith_operand" "rI")) + (return)] + "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "* +{ + if (! TARGET_ARCH64 && current_function_returns_struct) + return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT + || IN_OR_GLOBAL_P (operands[1]))) + return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + else + return \"ret\;restore %%g0, %1, %Y0\"; +}" + [(set_attr "type" "multi")]) + +(define_insn "*return_si" + [(set (match_operand:SI 0 "restore_operand" "") + (match_operand:SI 1 "arith_operand" "rI")) + (return)] + "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "* +{ + if (! TARGET_ARCH64 && current_function_returns_struct) + return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT + || IN_OR_GLOBAL_P (operands[1]))) + return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + else + return \"ret\;restore %%g0, %1, %Y0\"; +}" + [(set_attr "type" "multi")]) + +;; The following pattern is only generated by delayed-branch scheduling, +;; when the insn winds up in the epilogue. This can happen not only when +;; ! TARGET_FPU because we move complex types around by parts using +;; SF mode SUBREGs. +(define_insn "*return_sf_no_fpu" + [(set (match_operand:SF 0 "restore_operand" "r") + (match_operand:SF 1 "register_operand" "r")) + (return)] + "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "* +{ + if (! TARGET_ARCH64 && current_function_returns_struct) + return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])) + return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + else + return \"ret\;restore %%g0, %1, %Y0\"; +}" + [(set_attr "type" "multi")]) + +(define_insn "*return_addsi" + [(set (match_operand:SI 0 "restore_operand" "") + (plus:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "arith_operand" "rI"))) + (return)] + "! TARGET_EPILOGUE && ! TARGET_LIVE_G0" + "* +{ + if (! TARGET_ARCH64 && current_function_returns_struct) + return \"jmp\\t%%i7+12\\n\\trestore %r1, %2, %Y0\"; + /* If operands are global or in registers, can use return */ + else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]) + && (GET_CODE (operands[2]) == CONST_INT + || IN_OR_GLOBAL_P (operands[2]))) + return \"return\\t%%i7+8\\n\\tadd\\t%Y1, %Y2, %Y0\"; + else + return \"ret\;restore %r1, %2, %Y0\"; +}" + [(set_attr "type" "multi")]) + +(define_insn "*return_di" + [(set (match_operand:DI 0 "restore_operand" "") + (match_operand:DI 1 "arith_double_operand" "rHI")) + (return)] + "TARGET_ARCH64 && ! TARGET_EPILOGUE" + "ret\;restore %%g0, %1, %Y0" + [(set_attr "type" "multi")]) + +(define_insn "*return_adddi" + [(set (match_operand:DI 0 "restore_operand" "") + (plus:DI (match_operand:DI 1 "arith_operand" "%r") + (match_operand:DI 2 "arith_double_operand" "rHI"))) + (return)] + "TARGET_ARCH64 && ! TARGET_EPILOGUE" + "ret\;restore %r1, %2, %Y0" + [(set_attr "type" "multi")]) + +;; The following pattern is only generated by delayed-branch scheduling, +;; when the insn winds up in the epilogue. +(define_insn "*return_sf" + [(set (reg:SF 32) + (match_operand:SF 0 "register_operand" "f")) + (return)] + "! TARGET_EPILOGUE" + "ret\;fmovs\\t%0, %%f0" + [(set_attr "type" "multi")]) + +;; Now peepholes to do a call followed by a jump. + +(define_peephole + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:SI 1 "call_operand_address" "ps")) + (match_operand 2 "" ""))) + (clobber (reg:SI 15))]) + (set (pc) (label_ref (match_operand 3 "" "")))] + "short_branch (INSN_UID (insn), INSN_UID (operands[3])) + && in_same_eh_region (insn, operands[3]) + && in_same_eh_region (insn, ins1)" + "call\\t%a1, %2\\n\\tadd\\t%%o7, (%l3-.-4), %%o7") + +(define_peephole + [(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address" "ps")) + (match_operand 1 "" "")) + (clobber (reg:SI 15))]) + (set (pc) (label_ref (match_operand 2 "" "")))] + "short_branch (INSN_UID (insn), INSN_UID (operands[2])) + && in_same_eh_region (insn, operands[2]) + && in_same_eh_region (insn, ins1)" + "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7") + +(define_peephole + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "call_operand_address" "ps")) + (match_operand 2 "" ""))) + (clobber (reg:DI 15))]) + (set (pc) (label_ref (match_operand 3 "" "")))] + "TARGET_ARCH64 + && short_branch (INSN_UID (insn), INSN_UID (operands[3])) + && in_same_eh_region (insn, operands[3]) + && in_same_eh_region (insn, ins1)" + "call\\t%a1, %2\\n\\tadd\\t%%o7, (%l3-.-4), %%o7") + +(define_peephole + [(parallel [(call (mem:SI (match_operand:DI 0 "call_operand_address" "ps")) + (match_operand 1 "" "")) + (clobber (reg:DI 15))]) + (set (pc) (label_ref (match_operand 2 "" "")))] + "TARGET_ARCH64 + && short_branch (INSN_UID (insn), INSN_UID (operands[2])) + && in_same_eh_region (insn, operands[2]) + && in_same_eh_region (insn, ins1)" + "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7") + +;; After a nonlocal goto, we need to restore the PIC register, but only +;; if we need it. So do nothing much here, but we'll check for this in +;; finalize_pic. + +;; Make sure this unspec_volatile number agrees with finalize_pic. +(define_insn "nonlocal_goto_receiver" + [(unspec_volatile [(const_int 0)] 5)] + "flag_pic" + "" + [(set_attr "length" "0")]) + +(define_insn "trap" + [(trap_if (const_int 1) (const_int 5))] + "" + "ta\\t5" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_expand "conditional_trap" + [(trap_if (match_operator 0 "noov_compare_op" + [(match_dup 2) (match_dup 3)]) + (match_operand:SI 1 "arith_operand" ""))] + "" + "operands[2] = gen_compare_reg (GET_CODE (operands[0]), + sparc_compare_op0, sparc_compare_op1); + operands[3] = const0_rtx;") + +(define_insn "" + [(trap_if (match_operator 0 "noov_compare_op" [(reg:CC 100) (const_int 0)]) + (match_operand:SI 1 "arith_operand" "rM"))] + "" + "t%C0\\t%1" + [(set_attr "type" "misc") + (set_attr "length" "1")]) + +(define_insn "" + [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)]) + (match_operand:SI 1 "arith_operand" "rM"))] + "TARGET_V9" + "t%C0\\t%%xcc, %1" + [(set_attr "type" "misc") + (set_attr "length" "1")]) diff --git a/contrib/gcc/config/sparc/splet.h b/contrib/gcc/config/sparc/splet.h new file mode 100644 index 000000000000..d924e7089963 --- /dev/null +++ b/contrib/gcc/config/sparc/splet.h @@ -0,0 +1,69 @@ +/* Definitions of target machine for GNU compiler, for SPARClet. + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/aout.h" + +/* -mbroken-saverestore is not included here because the long term + default is -mno-broken-saverestore. */ +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE) + +/* -mlive-g0 is only supported on the sparclet. */ +#undef SUBTARGET_SWITCHES +#define SUBTARGET_SWITCHES \ +{"big-endian", -MASK_LITTLE_ENDIAN, "Generate code for big endian" }, \ +{"little-endian", MASK_LITTLE_ENDIAN, "Generate code for little endian" }, \ +{"live-g0", MASK_LIVE_G0, "Use g0 as a normal register" }, \ +{"no-live-g0", -MASK_LIVE_G0, "Register g0 is fixed with a zero value" }, \ +{"broken-saverestore", MASK_BROKEN_SAVERESTORE, "Enable save/restore bug workarounds" }, \ +{"no-broken-saverestore", -MASK_BROKEN_SAVERESTORE, "Disable save/restore bug workarouns" }, + +#undef ASM_SPEC +#define ASM_SPEC "%{mlittle-endian:-EL} %(asm_cpu)" + +/* Require the user to supply crt0.o. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "" + +#undef LINK_SPEC +#define LINK_SPEC "%{mlittle-endian:-EL}" + +/* sparclet chips are bi-endian. */ +#undef BYTES_BIG_ENDIAN +#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) +#undef WORDS_BIG_ENDIAN +#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) + +#undef SUBTARGET_OVERRIDE_OPTIONS +#define SUBTARGET_OVERRIDE_OPTIONS \ + do { \ + if (TARGET_LIVE_G0) \ + { \ + warning ("Option '-mlive-g0' deprecated."); \ + target_flags &= ~MASK_LIVE_G0; \ + } \ + else if (TARGET_BROKEN_SAVERESTORE) \ + { \ + warning ("Option '-mbroken-saverestore' deprecated."); \ + target_flags &= ~MASK_BROKEN_SAVERESTORE; \ + } \ + } while (0) + diff --git a/contrib/gcc/config/sparc/sun4gas.h b/contrib/gcc/config/sparc/sun4gas.h new file mode 100644 index 000000000000..3cea9560b4fe --- /dev/null +++ b/contrib/gcc/config/sparc/sun4gas.h @@ -0,0 +1,27 @@ +/* Definitions of target machine for GNU compiler, for SunOS 4.x with gas + Copyright (C) 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* gas supports unaligned data. */ +#define UNALIGNED_DOUBLE_INT_ASM_OP ".uaxword" +#define UNALIGNED_INT_ASM_OP ".uaword" +#define UNALIGNED_SHORT_ASM_OP ".uahalf" + +/* defaults.h will define DWARF2_UNWIND_INFO for us. */ +#undef DWARF2_UNWIND_INFO diff --git a/contrib/gcc/config/sparc/sun4o3.h b/contrib/gcc/config/sparc/sun4o3.h new file mode 100644 index 000000000000..d2a53c1f2372 --- /dev/null +++ b/contrib/gcc/config/sparc/sun4o3.h @@ -0,0 +1,29 @@ +#include "sparc/sparc.h" + +/* Override the name of the mcount profiling function. */ + +#undef MCOUNT_FUNCTION +#define MCOUNT_FUNCTION "*.mcount" + +/* LINK_SPEC is needed only for SunOS 4. */ + +#undef LINK_SPEC + +/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special + traps available which can get and set the condition codes + reliably. */ +#undef MACHINE_STATE_SAVE +#define MACHINE_STATE_SAVE(ID) \ + unsigned long int ms_flags, ms_saveret; \ + asm volatile("ta 0x20\n\t" \ + "mov %%g1, %0\n\t" \ + "mov %%g2, %1\n\t" \ + : "=r" (ms_flags), "=r" (ms_saveret)); + +#undef MACHINE_STATE_RESTORE +#define MACHINE_STATE_RESTORE(ID) \ + asm volatile("mov %0, %%g1\n\t" \ + "mov %1, %%g2\n\t" \ + "ta 0x21\n\t" \ + : /* no outputs */ \ + : "r" (ms_flags), "r" (ms_saveret)); diff --git a/contrib/gcc/config/sparc/sunos4.h b/contrib/gcc/config/sparc/sunos4.h new file mode 100644 index 000000000000..14c7a437d67c --- /dev/null +++ b/contrib/gcc/config/sparc/sunos4.h @@ -0,0 +1,49 @@ +/* Definitions of target machine for GNU compiler, for SunOS 4.x + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define SUNOS4_SHARED_LIBRARIES 1 + +/* Use N_BINCL stabs. */ + +#define DBX_USE_BINCL + +#include "sparc/sparc.h" + +/* The Sun as doesn't like unaligned data. */ +#define DWARF2_UNWIND_INFO 0 + +/* Override MACHINE_STATE_{SAVE,RESTORE} because we have special + traps available which can get and set the condition codes + reliably. */ +#undef MACHINE_STATE_SAVE +#define MACHINE_STATE_SAVE(ID) \ + unsigned long int ms_flags, ms_saveret; \ + asm volatile("ta 0x20\n\t" \ + "mov %%g1, %0\n\t" \ + "mov %%g2, %1\n\t" \ + : "=r" (ms_flags), "=r" (ms_saveret)); + +#undef MACHINE_STATE_RESTORE +#define MACHINE_STATE_RESTORE(ID) \ + asm volatile("mov %0, %%g1\n\t" \ + "mov %1, %%g2\n\t" \ + "ta 0x21\n\t" \ + : /* no outputs */ \ + : "r" (ms_flags), "r" (ms_saveret)); diff --git a/contrib/gcc/config/sparc/sysv4.h b/contrib/gcc/config/sparc/sysv4.h new file mode 100644 index 000000000000..5f9bba9e594d --- /dev/null +++ b/contrib/gcc/config/sparc/sysv4.h @@ -0,0 +1,216 @@ +/* Target definitions for GNU compiler for Sparc running System V.4 + Copyright (C) 1991, 92, 95, 96, 97, 1998 Free Software Foundation, Inc. + Contributed by Ron Guilmette (rfg@monkeys.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/sparc.h" + +/* Undefine some symbols which are defined in "sparc.h" but which are + appropriate only for SunOS 4.x, and not for svr4. */ + +#undef WORD_SWITCH_TAKES_ARG +#undef ASM_OUTPUT_SOURCE_LINE +#undef SELECT_SECTION +#undef ASM_DECLARE_FUNCTION_NAME +#undef TEXT_SECTION_ASM_OP +#undef DATA_SECTION_ASM_OP + +#include "svr4.h" + +/* ??? Put back the SIZE_TYPE/PTRDIFF_TYPE definitions set by sparc.h. + Why, exactly, is svr4.h messing with this? Seems like the chip + would know best. */ + +#undef SIZE_TYPE +#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") + +/* Undefined some symbols which are defined in "svr4.h" but which are + appropriate only for typical svr4 systems, but not for the specific + case of svr4 running on a Sparc. */ + +#undef INIT_SECTION_ASM_OP +#undef FINI_SECTION_ASM_OP +#undef CONST_SECTION_ASM_OP +#undef TYPE_OPERAND_FMT +#undef PUSHSECTION_FORMAT +#undef STRING_ASM_OP +#undef COMMON_ASM_OP +#undef SKIP_ASM_OP +#undef SET_ASM_OP /* Has no equivalent. See ASM_OUTPUT_DEF below. */ + +/* Provide a set of pre-definitions and pre-assertions appropriate for + the Sparc running svr4. __svr4__ is our extension. */ + +#define CPP_PREDEFINES \ +"-Dsparc -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4)" + +/* The native assembler can't compute differences between symbols in different + sections when generating pic code, so we must put jump tables in the + text section. */ +/* But we now defer the tables to the end of the function, so we make + this 0 to not confuse the branch shortening code. */ +#define JUMP_TABLES_IN_TEXT_SECTION 0 + +/* Pass -K to the assembler when PIC. */ +#undef ASM_SPEC +#define ASM_SPEC \ + "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \ + %{fpic:-K PIC} %{fPIC:-K PIC} %(asm_cpu)" + +/* Must use data section for relocatable constants when pic. */ +#undef SELECT_RTX_SECTION +#define SELECT_RTX_SECTION(MODE,RTX) \ +{ \ + if (flag_pic && symbolic_operand (RTX)) \ + data_section (); \ + else \ + const_section (); \ +} + +/* Define the names of various pseudo-op used by the Sparc/svr4 assembler. + Note that many of these are different from the typical pseudo-ops used + by most svr4 assemblers. That is probably due to a (misguided?) attempt + to keep the Sparc/svr4 assembler somewhat compatible with the Sparc/SunOS + assembler. */ + +#define STRING_ASM_OP ".asciz" +#define COMMON_ASM_OP ".common" +#define SKIP_ASM_OP ".skip" +#define UNALIGNED_DOUBLE_INT_ASM_OP ".uaxword" +#define UNALIGNED_INT_ASM_OP ".uaword" +#define UNALIGNED_SHORT_ASM_OP ".uahalf" +#define PUSHSECTION_ASM_OP ".pushsection" +#define POPSECTION_ASM_OP ".popsection" + +/* This is defined in sparc.h but is not used by svr4.h. */ +#undef ASM_LONG +#define ASM_LONG ".long" + +/* This is the format used to print the second operand of a .type pseudo-op + for the Sparc/svr4 assembler. */ + +#define TYPE_OPERAND_FMT "#%s" + +/* This is the format used to print a .pushsection pseudo-op (and its operand) + for the Sparc/svr4 assembler. */ + +#define PUSHSECTION_FORMAT "\t%s\t\"%s\"\n" + +#undef ASM_OUTPUT_CASE_LABEL +#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ +do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3); \ + ASM_OUTPUT_INTERNAL_LABEL ((FILE), PREFIX, NUM); \ + } while (0) + +/* This is how to equate one symbol to another symbol. The syntax used is + `SYM1=SYM2'. Note that this is different from the way equates are done + with most svr4 assemblers, where the syntax is `.set SYM1,SYM2'. */ + +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ + do { fprintf ((FILE), "\t"); \ + assemble_name (FILE, LABEL1); \ + fprintf (FILE, " = "); \ + assemble_name (FILE, LABEL2); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* Define how the Sparc registers should be numbered for Dwarf output. + The numbering provided here should be compatible with the native + svr4 SDB debugger in the Sparc/svr4 reference port. The numbering + is as follows: + + Assembly name gcc internal regno Dwarf regno + ---------------------------------------------------------- + g0-g7 0-7 0-7 + o0-o7 8-15 8-15 + l0-l7 16-23 16-23 + i0-i7 24-31 24-31 + f0-f31 32-63 40-71 +*/ + +#define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 32 ? (REGNO) : (REGNO) + 8) + +/* A set of symbol definitions for assembly pseudo-ops which will + get us switched to various sections of interest. These are used + in all places where we simply want to switch to a section, and + *not* to push the previous section name onto the assembler's + section names stack (as we do often in dwarfout.c). */ + +#define TEXT_SECTION_ASM_OP ".section\t\".text\"" +#define DATA_SECTION_ASM_OP ".section\t\".data\"" +#define BSS_SECTION_ASM_OP ".section\t\".bss\"" +#define CONST_SECTION_ASM_OP ".section\t\".rodata\"" +#define INIT_SECTION_ASM_OP ".section\t\".init\"" +#define FINI_SECTION_ASM_OP ".section\t\".fini\"" + +/* Define the pseudo-ops used to switch to the .ctors and .dtors sections. + + Note that we want to give these sections the SHF_WRITE attribute + because these sections will actually contain data (i.e. tables of + addresses of functions in the current root executable or shared library + file) and, in the case of a shared library, the relocatable addresses + will have to be properly resolved/relocated (and then written into) by + the dynamic linker when it actually attaches the given shared library + to the executing process. (Note that on SVR4, you may wish to use the + `-z text' option to the ELF linker, when building a shared library, as + an additional check that you are doing everything right. But if you do + use the `-z text' option when building a shared library, you will get + errors unless the .ctors and .dtors sections are marked as writable + via the SHF_WRITE attribute.) */ + +#undef CTORS_SECTION_ASM_OP +#define CTORS_SECTION_ASM_OP ".section\t\".ctors\",#alloc,#write" +#undef DTORS_SECTION_ASM_OP +#define DTORS_SECTION_ASM_OP ".section\t\".dtors\",#alloc,#write" +#undef EH_FRAME_SECTION_ASM_OP +#define EH_FRAME_SECTION_ASM_OP ".section\t\".eh_frame\",#alloc,#write" + +/* A C statement to output something to the assembler file to switch to section + NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or + NULL_TREE. Some target formats do not support arbitrary sections. Do not + define this macro in such cases. */ + +#undef ASM_OUTPUT_SECTION_NAME /* Override svr4.h's definition. */ +#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \ +do { \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \ + fprintf (FILE, ".section\t\"%s\",#alloc,#execinstr\n", \ + (NAME)); \ + else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \ + fprintf (FILE, ".section\t\"%s\",#alloc\n", (NAME)); \ + else \ + fprintf (FILE, ".section\t\"%s\",#alloc,#write\n", (NAME)); \ +} while (0) + +/* A C statement (sans semicolon) to output to the stdio stream + FILE the assembler definition of uninitialized global DECL named + NAME whose size is SIZE bytes and alignment is ALIGN bytes. + Try to use asm_output_aligned_bss to implement this macro. */ + +#undef ASM_OUTPUT_ALIGNED_BSS +#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ + asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) + +/* Override the name of the mcount profiling function. */ + +#undef MCOUNT_FUNCTION +#define MCOUNT_FUNCTION "*_mcount" diff --git a/contrib/gcc/config/sparc/t-elf b/contrib/gcc/config/sparc/t-elf new file mode 100644 index 000000000000..da9df38368ee --- /dev/null +++ b/contrib/gcc/config/sparc/t-elf @@ -0,0 +1,39 @@ +# we need to supply our own assembly versions of libgcc1.c files, +# since the user may not have native 'cc' available + +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = sparc/lb1spc.asm +LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 + +# crt0 is built elsewhere +LIBGCC1_TEST = + +# These are really part of libgcc1, but this will cause them to be +# built correctly, so... + +LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + cat $(srcdir)/config/fp-bit.c > dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +# MULTILIB_OPTIONS should have msparclite too, but we'd have to make +# gas build... +#MULTILIB_OPTIONS = msoft-float mcpu=v8 +MULTILIB_OPTIONS = msoft-float +#MULTILIB_DIRNAMES = soft v8 +MULTILIB_DIRNAMES = soft +#MULTILIB_MATCHES = msoft-float=mno-fpu mcpu?v8=mv8 +MULTILIB_MATCHES = msoft-float=mno-fpu + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +# Assemble startup files. +crti.o: $(srcdir)/config/sparc/sol2-ci.asm $(GCC_PASSES) + $(GCC_FOR_TARGET) -c -o crti.o -x assembler $(srcdir)/config/sparc/sol2-ci.asm +crtn.o: $(srcdir)/config/sparc/sol2-cn.asm $(GCC_PASSES) + $(GCC_FOR_TARGET) -c -o crtn.o -x assembler $(srcdir)/config/sparc/sol2-cn.asm diff --git a/contrib/gcc/config/sparc/t-halos b/contrib/gcc/config/sparc/t-halos new file mode 100644 index 000000000000..0bd5496ac238 --- /dev/null +++ b/contrib/gcc/config/sparc/t-halos @@ -0,0 +1,2 @@ +# For a native HALOS compile, we need to set -e1 for the assembler +AS=as -e1 diff --git a/contrib/gcc/config/sparc/t-linux64 b/contrib/gcc/config/sparc/t-linux64 new file mode 100644 index 000000000000..077cf69e7193 --- /dev/null +++ b/contrib/gcc/config/sparc/t-linux64 @@ -0,0 +1,21 @@ +MULTILIB_OPTIONS = m64/m32 +MULTILIB_DIRNAMES = 64 32 +MULTILIB_MATCHES = + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o + +tcrtbeginS.o: crtstuff.c $(GCC_PASSES) $(CONFIG_H) \ + defaults.h frame.h gbl-ctors.h + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \ + -finhibit-size-directive -fno-inline-functions -fno-exceptions $(CRTSTUFF_T_CFLAGS_S) \ + -c $(srcdir)/crtstuff.c -DCRT_BEGIN -o tcrtbeginS$(objext) + +tcrtendS.o: crtstuff.c $(GCC_PASSES) $(CONFIG_H) \ + defaults.h frame.h gbl-ctors.h + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \ + -finhibit-size-directive -fno-inline-functions -fno-exceptions $(CRTSTUFF_T_CFLAGS_S) \ + -c $(srcdir)/crtstuff.c -DCRT_END -o tcrtendS$(objext) + diff --git a/contrib/gcc/config/sparc/t-sol2 b/contrib/gcc/config/sparc/t-sol2 new file mode 100644 index 000000000000..a9b6ee147939 --- /dev/null +++ b/contrib/gcc/config/sparc/t-sol2 @@ -0,0 +1,30 @@ +# we need to supply our own assembly versions of libgcc1.c files, +# since the user may not have native 'cc' available + +LIBGCC1 = +CROSS_LIBGCC1 = +LIBGCC1_TEST = + +# gmon build rule: +$(T)gmon.o: $(srcdir)/config/sparc/gmon-sol2.c $(GCC_PASSES) $(CONFIG_H) stmp-int-hdrs + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) \ + -c $(srcdir)/config/sparc/gmon-sol2.c -o $(T)gmon.o + +# Assemble startup files. +$(T)crt1.o: $(srcdir)/config/sparc/sol2-c1.asm $(GCC_PASSES) + $(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $(T)crt1.o -x assembler-with-cpp $(srcdir)/config/sparc/sol2-c1.asm +$(T)crti.o: $(srcdir)/config/sparc/sol2-ci.asm $(GCC_PASSES) + $(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/sparc/sol2-ci.asm +$(T)crtn.o: $(srcdir)/config/sparc/sol2-cn.asm $(GCC_PASSES) + $(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/sparc/sol2-cn.asm +$(T)gcrt1.o: $(srcdir)/config/sparc/sol2-c1.asm $(GCC_PASSES) + $(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -DGCRT1 -o $(T)gcrt1.o -x assembler-with-cpp $(srcdir)/config/sparc/sol2-c1.asm + +# We need to use -fPIC when we are using gcc to compile the routines in +# crtstuff.c. This is only really needed when we are going to use gcc/g++ +# to produce a shared library, but since we don't know ahead of time when +# we will be doing that, we just always use -fPIC when compiling the +# routines in crtstuff.c. + +CRTSTUFF_T_CFLAGS = -fPIC +TARGET_LIBGCC2_CFLAGS = -fPIC diff --git a/contrib/gcc/config/sparc/t-sol2-64 b/contrib/gcc/config/sparc/t-sol2-64 new file mode 100644 index 000000000000..8d42c4453542 --- /dev/null +++ b/contrib/gcc/config/sparc/t-sol2-64 @@ -0,0 +1,8 @@ +MULTILIB_OPTIONS = m32/m64 +MULTILIB_DIRNAMES = sparcv7 sparcv9 +MULTILIB_MATCHES = + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o gmon.o crt1.o crti.o crtn.o gcrt1.o diff --git a/contrib/gcc/config/sparc/t-sp64 b/contrib/gcc/config/sparc/t-sp64 new file mode 100644 index 000000000000..99acd5d54235 --- /dev/null +++ b/contrib/gcc/config/sparc/t-sp64 @@ -0,0 +1,2 @@ +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/sparc/t-sparcbare b/contrib/gcc/config/sparc/t-sparcbare new file mode 100644 index 000000000000..8bd978b068d9 --- /dev/null +++ b/contrib/gcc/config/sparc/t-sparcbare @@ -0,0 +1,26 @@ +# configuration file for a bare sparc cpu + +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = sparc/lb1spc.asm +LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 + +# These are really part of libgcc1, but this will cause them to be +# built correctly, so... + +LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + cat $(srcdir)/config/fp-bit.c > dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +# MULTILIB_OPTIONS should have msparclite too, but we'd have to make +# gas build... +MULTILIB_OPTIONS = msoft-float mcpu=v8 +MULTILIB_DIRNAMES = soft v8 +MULTILIB_MATCHES = msoft-float=mno-fpu mcpu?v8=mv8 + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/config/sparc/t-sparclite b/contrib/gcc/config/sparc/t-sparclite new file mode 100644 index 000000000000..7cdfbb04551c --- /dev/null +++ b/contrib/gcc/config/sparc/t-sparclite @@ -0,0 +1,24 @@ +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = sparc/lb1spl.asm +LIB1ASMFUNCS = _divsi3 _udivsi3 _modsi3 _umodsi3 + +# These are really part of libgcc1, but this will cause them to be +# built correctly, so... + +LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define US_SOFTWARE_GOFAST' > dp-bit.c + cat $(srcdir)/config/fp-bit.c >> dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +MULTILIB_OPTIONS = mfpu mflat +MULTILIB_DIRNAMES = +MULTILIB_MATCHES = mfpu=mhard-float mfpu=mcpu?f934 + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/config/sparc/t-splet b/contrib/gcc/config/sparc/t-splet new file mode 100644 index 000000000000..3329e0bef072 --- /dev/null +++ b/contrib/gcc/config/sparc/t-splet @@ -0,0 +1,22 @@ +# configuration file for a bare sparclet cpu, aout format files + +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = sparc/lb1spc.asm +LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 + +# These are really part of libgcc1, but this will cause them to be +# built correctly, so... + +LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + cat $(srcdir)/config/fp-bit.c > dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +MULTILIB_OPTIONS = mlittle-endian mflat +MULTILIB_DIRNAMES = little flat +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/config/sparc/t-sunos40 b/contrib/gcc/config/sparc/t-sunos40 new file mode 100644 index 000000000000..3e10575eaea5 --- /dev/null +++ b/contrib/gcc/config/sparc/t-sunos40 @@ -0,0 +1,7 @@ +# SunOS 4.0.* +# /bin/as doesn't recognize the v8 instructions, so we can't do a v8 +# multilib build. + +LIBGCC1 = +CROSS_LIBGCC1 = +LIBGCC1_TEST = diff --git a/contrib/gcc/config/sparc/t-sunos41 b/contrib/gcc/config/sparc/t-sunos41 new file mode 100644 index 000000000000..5783d6a26258 --- /dev/null +++ b/contrib/gcc/config/sparc/t-sunos41 @@ -0,0 +1,16 @@ +# SunOS 4.1.* + +LIBGCC1 = +CROSS_LIBGCC1 = +LIBGCC1_TEST = + +MULTILIB_OPTIONS = fpic/fPIC mcpu=v8 +MULTILIB_DIRNAMES = pic ucpic v8 +MULTILIB_MATCHES = mcpu?v8=mv8 + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +# The native linker doesn't handle linking -fpic code with -fPIC code. Ugh. +# We cope by building both variants of libgcc. +#TARGET_LIBGCC2_CFLAGS = -fPIC diff --git a/contrib/gcc/config/sparc/t-vxsparc b/contrib/gcc/config/sparc/t-vxsparc new file mode 100644 index 000000000000..0c7a14a44295 --- /dev/null +++ b/contrib/gcc/config/sparc/t-vxsparc @@ -0,0 +1,17 @@ +LIBGCC1 = +CROSS_LIBGCC1 = + +# We don't want to build .umul, etc., because VxWorks provides them, +# which means that libgcc1-test will fail. +LIBGCC1_TEST = + +# We don't want to put exit in libgcc.a for VxWorks, because VxWorks +# does not have _exit. +TARGET_LIBGCC2_CFLAGS = -Dexit=unused_exit + +MULTILIB_OPTIONS=msoft-float mv8 +MULTILIB_DIRNAMES=soft v8 +MULTILIB_MATCHES=msoft-float=mno-fpu + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/config/sparc/vxsim.h b/contrib/gcc/config/sparc/vxsim.h new file mode 100644 index 000000000000..6c80375f56b9 --- /dev/null +++ b/contrib/gcc/config/sparc/vxsim.h @@ -0,0 +1,131 @@ +/* Definitions of target machine for GNU compiler, for SPARC VxSim + Copyright 1996 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Supposedly the same as vanilla sparc svr4, except for the stuff below: */ +#include "sparc/sysv4.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES \ + "-DCPU=SIMSPARCSOLARIS -D__vxworks -D__vxworks__ -Dsparc -D__svr4__ -D__SVR4 \ + -Asystem(embedded) -Asystem(svr4) -Acpu(sparc) -Amachine(sparc)\ + -D__GCC_NEW_VARARGS__" + +#undef CPP_SPEC +#define CPP_SPEC "" + +#undef CC1_SPEC +#define CC1_SPEC "-fno-builtin %{sun4:} %{target:}" + +/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). + It's safe to pass -s always, even if -g is not used. */ +#undef ASM_SPEC +#define ASM_SPEC \ + "%{V} %{v:%{!V:-V}} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \ + %{fpic:-K PIC} %{fPIC:-K PIC}" + +/* However it appears that Solaris 2.0 uses the same reg numbering as + the old BSD-style system did. */ + +#undef DBX_REGISTER_NUMBER +/* Same as sparc.h */ +#define DBX_REGISTER_NUMBER(REGNO) (REGNO) + +/* We use stabs-in-elf for debugging, because that is what the native + toolchain uses. */ +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +/* The Solaris 2 assembler uses .skip, not .zero, so put this back. */ +#undef ASM_OUTPUT_SKIP +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.skip %u\n", (SIZE)) + +#undef ASM_OUTPUT_ALIGNED_LOCAL +#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ +do { \ + fputs ("\t.local\t", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + putc ('\n', (FILE)); \ + ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN); \ +} while (0) + +#undef COMMON_ASM_OP +#define COMMON_ASM_OP "\t.common" + +/* This is how to output a definition of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".L%s%d:\n", PREFIX, NUM) + +/* This is how to output a reference to an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABELREF +#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ + fprintf (FILE, ".L%s%d", PREFIX, NUM) + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf (LABEL, "*.L%s%d", PREFIX, NUM) + + + +#undef LIB_SPEC +#define LIB_SPEC "" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "" + +#undef LINK_SPEC +#define LINK_SPEC "-r" + +/* This defines which switch letters take arguments. + It is as in svr4.h but with -R added. */ + +#undef SWITCH_TAKES_ARG +#define SWITCH_TAKES_ARG(CHAR) \ + ( (CHAR) == 'D' \ + || (CHAR) == 'U' \ + || (CHAR) == 'o' \ + || (CHAR) == 'e' \ + || (CHAR) == 'u' \ + || (CHAR) == 'I' \ + || (CHAR) == 'm' \ + || (CHAR) == 'L' \ + || (CHAR) == 'R' \ + || (CHAR) == 'A' \ + || (CHAR) == 'h' \ + || (CHAR) == 'z') + +/* ??? This does not work in SunOS 4.x, so it is not enabled in sparc.h. + Instead, it is enabled here, because it does work under Solaris. */ +/* Define for support of TFmode long double and REAL_ARITHMETIC. + Sparc ABI says that long double is 4 words. */ +#define LONG_DOUBLE_TYPE_SIZE 64 diff --git a/contrib/gcc/config/sparc/vxsparc.h b/contrib/gcc/config/sparc/vxsparc.h new file mode 100644 index 000000000000..18ce6ed97b70 --- /dev/null +++ b/contrib/gcc/config/sparc/vxsparc.h @@ -0,0 +1,61 @@ +/* Definitions of target machine for GNU compiler. Vxworks SPARC version. + Copyright (C) 1994, 1996 Free Software Foundation, Inc. + Contributed by David Henkel-Wallace (gumby@cygnus.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "sparc/aout.h" + +/* Specify what to link with. */ +/* VxWorks does all the library stuff itself. */ + +#undef LIB_SPEC +#define LIB_SPEC "" + +/* Provide required defaults for linker -e. */ +#undef LINK_SPEC +#define LINK_SPEC "%{!nostdlib:%{!r*:%{!e*:-e start}}}" + +/* VxWorks provides the functionality of crt0.o and friends itself. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dsparc -Acpu(sparc) -Amachine(sparc)" + +/* Note that we define CPU here even if the user has specified -ansi. + This violates user namespace, but the VxWorks headers, and potentially + user code, all explicitly rely upon the definition of CPU in order to get + the proper processor information. */ +#undef CPP_SPEC +#define CPP_SPEC "%(cpp_cpu) -DCPU=SPARC" + +#undef PTRDIFF_TYPE +#undef SIZE_TYPE +#undef WCHAR_TYPE +#undef WCHAR_TYPE_SIZE + +#define PTRDIFF_TYPE "long int" +#define SIZE_TYPE "unsigned int" +#define WCHAR_TYPE "char" +#define WCHAR_TYPE_SIZE 8 + +/* US Software GOFAST library support. */ +#include "gofast.h" +#undef INIT_SUBTARGET_OPTABS +#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS diff --git a/contrib/gcc/config/sparc/x-sysv4 b/contrib/gcc/config/sparc/x-sysv4 new file mode 100644 index 000000000000..2a661e359993 --- /dev/null +++ b/contrib/gcc/config/sparc/x-sysv4 @@ -0,0 +1,2 @@ +X_CFLAGS=-DSVR4 +ALLOCA=alloca.o diff --git a/contrib/gcc/config/sparc/xm-linux.h b/contrib/gcc/config/sparc/xm-linux.h new file mode 100644 index 000000000000..691c7d167847 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-linux.h @@ -0,0 +1,26 @@ +/* Configuration for GCC for SPARC running Linux-based GNU systems. + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Eddie C. Dost (ecd@skynet.be) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef inhibit_libc +#include <alloca.h> +#include <stdlib.h> +#include <string.h> +#endif diff --git a/contrib/gcc/config/sparc/xm-lynx.h b/contrib/gcc/config/sparc/xm-lynx.h new file mode 100644 index 000000000000..90fef8543b91 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-lynx.h @@ -0,0 +1,39 @@ +/* Configuration for GNU C-compiler for sparc platforms running LynxOS. + Copyright (C) 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <xm-lynx.h> + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +#define HOST_WORDS_BIG_ENDIAN 1 + +/* Include <sys/wait.h> to define the exit status access macros. */ +#include <sys/types.h> +#include <sys/wait.h> + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ + +#include "tm.h" diff --git a/contrib/gcc/config/sparc/xm-netbsd.h b/contrib/gcc/config/sparc/xm-netbsd.h new file mode 100644 index 000000000000..5f11b8d2f480 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-netbsd.h @@ -0,0 +1,4 @@ +/* Configuration for GCC for Sun SPARC running NetBSD as host. */ + +#include <sparc/xm-sparc.h> +#include <xm-netbsd.h> diff --git a/contrib/gcc/config/sparc/xm-openbsd.h b/contrib/gcc/config/sparc/xm-openbsd.h new file mode 100644 index 000000000000..2df7fb3e3639 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-openbsd.h @@ -0,0 +1,23 @@ +/* Configuration file for an host running sparc OpenBSD. + Copyright (C) 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <xm-openbsd.h> +#include <sparc/xm-sparc.h> + diff --git a/contrib/gcc/config/sparc/xm-pbd.h b/contrib/gcc/config/sparc/xm-pbd.h new file mode 100644 index 000000000000..1c3f47590c79 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-pbd.h @@ -0,0 +1,10 @@ +/* Host environment for the tti "Unicom" PBB 68020 boards */ + +#include "sparc/xm-sparc.h" + +#define USG + +#ifndef __GNUC__ +#define USE_C_ALLOCA +#endif + diff --git a/contrib/gcc/config/sparc/xm-sol2.h b/contrib/gcc/config/sparc/xm-sol2.h new file mode 100644 index 000000000000..5613b086b572 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-sol2.h @@ -0,0 +1,4 @@ +/* If not compiled with GNU C, include the system's <alloca.h> header. */ +#ifndef __GNUC__ +#include <alloca.h> +#endif diff --git a/contrib/gcc/config/sparc/xm-sp64.h b/contrib/gcc/config/sparc/xm-sp64.h new file mode 100644 index 000000000000..b673161282f4 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-sp64.h @@ -0,0 +1,27 @@ +/* Configuration for GCC for Sparc v9 running 64-bit native. + Copyright (C) 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <sparc/xm-sparc.h> + +/* This describes the machine the compiler is hosted on. */ +#if defined(__arch64__) || defined(__sparc_v9__) || defined(__sparcv9) +#undef HOST_BITS_PER_LONG +#define HOST_BITS_PER_LONG 64 +#endif diff --git a/contrib/gcc/config/sparc/xm-sparc.h b/contrib/gcc/config/sparc/xm-sparc.h new file mode 100644 index 000000000000..e553a0df0b25 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-sparc.h @@ -0,0 +1,49 @@ +/* Configuration for GNU C-compiler for Sun Sparc. + Copyright (C) 1988, 1993, 1995, 1997 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Doubles are stored in memory with the high order word first. This + matters when cross-compiling. */ +#define HOST_WORDS_BIG_ENDIAN 1 + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ +#include "tm.h" + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* If compiled with Sun CC, the use of alloca requires this #include. */ +#ifndef __GNUC__ +#include "alloca.h" +#endif diff --git a/contrib/gcc/config/sparc/xm-sysv4-64.h b/contrib/gcc/config/sparc/xm-sysv4-64.h new file mode 100644 index 000000000000..c506d22dd360 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-sysv4-64.h @@ -0,0 +1,27 @@ +/* Configuration for GCC for Sparc v9 running 64-bit native. + Copyright (C) 1998 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <sparc/xm-sysv4.h> + +/* This describes the machine the compiler is hosted on. */ +#if defined(__arch64__) || defined(__sparc_v9__) || defined(__sparcv9) +#undef HOST_BITS_PER_LONG +#define HOST_BITS_PER_LONG 64 +#endif diff --git a/contrib/gcc/config/sparc/xm-sysv4.h b/contrib/gcc/config/sparc/xm-sysv4.h new file mode 100644 index 000000000000..6e663d12cfa1 --- /dev/null +++ b/contrib/gcc/config/sparc/xm-sysv4.h @@ -0,0 +1,48 @@ +/* Configuration for GNU C-compiler for Sun Sparc running System V.4. + Copyright (C) 1992, 1993, 1998 Free Software Foundation, Inc. + Contributed by Ron Guilmette (rfg@netcom.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Doubles are stored in memory with the high order word first. This + matters when cross-compiling. */ +#define HOST_WORDS_BIG_ENDIAN 1 + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ +#include "tm.h" + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +#ifndef __GNUC__ +#define ONLY_INT_FIELDS +#endif diff --git a/contrib/gcc/config/x-netbsd b/contrib/gcc/config/x-netbsd new file mode 100644 index 000000000000..1c272f5a8dc8 --- /dev/null +++ b/contrib/gcc/config/x-netbsd @@ -0,0 +1,6 @@ +# Don't run fixproto +STMP_FIXPROTO = + +# We don't need GCC's own include files. +USER_H = +INSTALL_ASSERT_H = diff --git a/contrib/gcc/config/xm-netbsd.h b/contrib/gcc/config/xm-netbsd.h new file mode 100644 index 000000000000..099a9234ffa6 --- /dev/null +++ b/contrib/gcc/config/xm-netbsd.h @@ -0,0 +1,26 @@ +/* Configuration for GNU C-compiler for hosts running NetBSD. + Copyright (C) 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This file defines machine-independent things specific to a host + running NetBSD. This file should not be specified as $xm_file itself; + instead $xm_file should be CPU/xm-netbsd.h, which should include both + CPU/xm-CPU.h and this file xm-netbsd.h. */ + +#define HAVE_VPRINTF diff --git a/contrib/gcc/config/xm-siglist.h b/contrib/gcc/config/xm-siglist.h new file mode 100644 index 000000000000..d6133d6a194a --- /dev/null +++ b/contrib/gcc/config/xm-siglist.h @@ -0,0 +1,6 @@ +/* Some systems provide no sys_siglist, but do offer the same data under + another name. */ + +#define sys_siglist _sys_siglist +#undef SYS_SIGLIST_DECLARED +#define SYS_SIGLIST_DECLARED diff --git a/contrib/gcc/configure b/contrib/gcc/configure index 0578cd747d2f..afa0166923f1 100755 --- a/contrib/gcc/configure +++ b/contrib/gcc/configure @@ -1,6 +1,6 @@ #! /bin/sh -# $FreeBSD$ +# $FreeBSD: src/contrib/gcc/configure,v 1.8 2000/01/22 16:05:31 obrien Exp $ # Guess values for system-dependent variables and create Makefiles. # Generated automatically using autoconf version 2.13 diff --git a/contrib/gcc/cp/class.h b/contrib/gcc/cp/class.h new file mode 100644 index 000000000000..f2c21735cc4c --- /dev/null +++ b/contrib/gcc/cp/class.h @@ -0,0 +1,117 @@ +/* Variables and structures for overloading rules. + Copyright (C) 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* The following structure is used when comparing various alternatives + for overloading. The unsigned quantity `strikes.i' is used + for fast comparison of two possibilities. This number is an + aggregate of four constituents: + + EVIL: if this is non-zero, then the candidate should not be considered + ELLIPSIS: if this is non-zero, then some actual argument has been matched + against an ellipsis + USER: if this is non-zero, then a user-defined type conversion is needed + B_OR_D: if this is non-zero, then use a base pointer instead of the + type of the pointer we started with. + EASY: if this is non-zero, then we have a builtin conversion + (such as int to long, int to float, etc) to do. + + If two candidates require user-defined type conversions, and the + type conversions are not identical, then an ambiguity error + is reported. + + If two candidates agree on user-defined type conversions, + and one uses pointers of strictly higher type (derived where + another uses base), then that alternative is silently chosen. + + Note that this technique really only works for 255 arguments. Perhaps + this is not enough. */ + +/* These macros and harshness_code are used by the NEW METHOD. */ +#define EVIL_CODE (1<<7) +#define CONST_CODE (1<<6) +#define ELLIPSIS_CODE (1<<5) +#define USER_CODE (1<<4) +#define STD_CODE (1<<3) +#define PROMO_CODE (1<<2) +#define QUAL_CODE (1<<1) +#define TRIVIAL_CODE (1<<0) + +struct harshness_code +{ + /* What kind of conversion is involved. */ + unsigned short code; + + /* The inheritance distance. */ + short distance; + + /* For a PROMO_CODE, Any special penalties involved in integral conversions. + This exists because $4.1 of the ARM states that something like + `short unsigned int' should promote to `int', not `unsigned int'. + If, for example, it tries to match two fns, f(int) and f(unsigned), + f(int) should be a better match than f(unsigned) by this rule. Without + this extra metric, they both only appear as "integral promotions", which + will lead to an ambiguity. + For a TRIVIAL_CODE, This is also used by build_overload_call_real and + convert_harshness to keep track of other information we need. */ + unsigned short int_penalty; +}; + +struct candidate +{ + struct harshness_code h; /* Used for single-argument conversions. */ + + int h_len; /* The length of the harshness vector. */ + + tree function; /* A FUNCTION_DECL */ + tree basetypes; /* The path to function. */ + tree arg; /* first parm to function. */ + + /* Indexed by argument number, encodes evil, user, d_to_b, and easy + strikes for that argument. At end of array, we store the index+1 + of where we started using default parameters, or 0 if there are + none. */ + struct harshness_code *harshness; + + union + { + tree field; /* If no evil strikes, the FUNCTION_DECL of + the function (if a member function). */ + int bad_arg; /* the index of the first bad argument: + 0 if no bad arguments + > 0 is first bad argument + -1 if extra actual arguments + -2 if too few actual arguments. + -3 if const/non const method mismatch. + -4 if type unification failed. + -5 if contravariance violation. */ + } u; +}; +int rank_for_overload (); + +/* Variables shared between class.c and call.c. */ + +extern int n_vtables; +extern int n_vtable_entries; +extern int n_vtable_searches; +extern int n_vtable_elems; +extern int n_convert_harshness; +extern int n_compute_conversion_costs; +extern int n_build_method_call; +extern int n_inner_fields_searched; diff --git a/contrib/gcc/cp/decl.c b/contrib/gcc/cp/decl.c index bd69ca5f4bef..a61a9e5df06d 100644 --- a/contrib/gcc/cp/decl.c +++ b/contrib/gcc/cp/decl.c @@ -19,7 +19,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/cp/decl.c,v 1.4.2.2 2000/08/07 10:06:54 obrien Exp $ */ /* Process declarations and symbol lookup for C front end. diff --git a/contrib/gcc/cp/except.c b/contrib/gcc/cp/except.c index f2896c760f60..480b748f3fe7 100644 --- a/contrib/gcc/cp/except.c +++ b/contrib/gcc/cp/except.c @@ -21,7 +21,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/cp/except.c,v 1.5 1999/10/16 07:53:19 obrien Exp $ */ #include "config.h" diff --git a/contrib/gcc/cp/g++.c b/contrib/gcc/cp/g++.c new file mode 100644 index 000000000000..efb6231a20d1 --- /dev/null +++ b/contrib/gcc/cp/g++.c @@ -0,0 +1,582 @@ +/* G++ preliminary semantic processing for the compiler driver. + Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc. + Contributed by Brendan Kehoe (brendan@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This program is a wrapper to the main `gcc' driver. For GNU C++, + we need to do two special things: a) append `-lg++' in situations + where it's appropriate, to link in libg++, and b) add `-xc++'..`-xnone' + around file arguments named `foo.c' or `foo.i'. So, we do all of + this semantic processing then just exec gcc with the new argument + list. + + We used to do all of this in a small shell script, but many users + found the performance of this as a shell script to be unacceptable. + In situations where your PATH has a lot of NFS-mounted directories, + using a script that runs sed and other things would be a nasty + performance hit. With this program, we never search the PATH at all. */ + +#include "config.h" +#ifdef __STDC__ +#include <stdarg.h> +#else +#include <varargs.h> +#endif +#include <stdio.h> +#include <sys/types.h> +#if !defined(_WIN32) +#include <sys/file.h> /* May get R_OK, etc. on some systems. */ +#else +#include <process.h> +#endif +#include <errno.h> + +/* Defined to the name of the compiler; if using a cross compiler, the + Makefile should compile this file with the proper name + (e.g., "i386-aout-gcc"). */ +#ifndef GCC_NAME +#define GCC_NAME "gcc" +#endif + +/* This bit is set if we saw a `-xfoo' language specification. */ +#define LANGSPEC (1<<1) +/* This bit is set if they did `-lm' or `-lmath'. */ +#define MATHLIB (1<<2) + +#ifndef MATH_LIBRARY +#define MATH_LIBRARY "-lm" +#endif + +/* On MSDOS, write temp files in current dir + because there's no place else we can expect to use. */ +#ifdef __MSDOS__ +#ifndef P_tmpdir +#define P_tmpdir "." +#endif +#ifndef R_OK +#define R_OK 4 +#define W_OK 2 +#define X_OK 1 +#endif +#endif + +#ifndef VPROTO +#ifdef __STDC__ +#define PVPROTO(ARGS) ARGS +#define VPROTO(ARGS) ARGS +#define VA_START(va_list,var) va_start(va_list,var) +#else +#define PVPROTO(ARGS) () +#define VPROTO(ARGS) (va_alist) va_dcl +#define VA_START(va_list,var) va_start(va_list) +#endif +#endif + +#ifndef errno +extern int errno; +#endif + +extern int sys_nerr; +#ifndef HAVE_STRERROR +#if defined(bsd4_4) +extern const char *const sys_errlist[]; +#else +extern char *sys_errlist[]; +#endif +#else +extern char *strerror(); +#endif + +/* Name with which this program was invoked. */ +static char *programname; + +char * +my_strerror(e) + int e; +{ + +#ifdef HAVE_STRERROR + return strerror(e); + +#else + + static char buffer[30]; + if (!e) + return ""; + + if (e > 0 && e < sys_nerr) + return sys_errlist[e]; + + sprintf (buffer, "Unknown error %d", e); + return buffer; +#endif +} + +#ifdef HAVE_VPRINTF +/* Output an error message and exit */ + +static void +fatal VPROTO((char *format, ...)) +{ +#ifndef __STDC__ + char *format; +#endif + va_list ap; + + VA_START (ap, format); + +#ifndef __STDC__ + format = va_arg (ap, char*); +#endif + + fprintf (stderr, "%s: ", programname); + vfprintf (stderr, format, ap); + va_end (ap); + fprintf (stderr, "\n"); +#if 0 + /* XXX Not needed for g++ driver. */ + delete_temp_files (); +#endif + exit (1); +} + +static void +error VPROTO((char *format, ...)) +{ +#ifndef __STDC__ + char *format; +#endif + va_list ap; + + VA_START (ap, format); + +#ifndef __STDC__ + format = va_arg (ap, char*); +#endif + + fprintf (stderr, "%s: ", programname); + vfprintf (stderr, format, ap); + va_end (ap); + + fprintf (stderr, "\n"); +} + +#else /* not HAVE_VPRINTF */ + +static void +error (msg, arg1, arg2) + char *msg, *arg1, *arg2; +{ + fprintf (stderr, "%s: ", programname); + fprintf (stderr, msg, arg1, arg2); + fprintf (stderr, "\n"); +} + +static void +fatal (msg, arg1, arg2) + char *msg, *arg1, *arg2; +{ + error (msg, arg1, arg2); +#if 0 + /* XXX Not needed for g++ driver. */ + delete_temp_files (); +#endif + exit (1); +} + +#endif /* not HAVE_VPRINTF */ + +/* More 'friendly' abort that prints the line and file. + config.h can #define abort fancy_abort if you like that sort of thing. */ + +void +fancy_abort () +{ + fatal ("Internal g++ abort."); +} + +char * +xmalloc (size) + unsigned size; +{ + register char *value = (char *) malloc (size); + if (value == 0) + fatal ("virtual memory exhausted"); + return value; +} + +/* Return a newly-allocated string whose contents concatenate those + of s1, s2, s3. */ +static char * +concat (s1, s2, s3) + char *s1, *s2, *s3; +{ + int len1 = strlen (s1), len2 = strlen (s2), len3 = strlen (s3); + char *result = xmalloc (len1 + len2 + len3 + 1); + + strcpy (result, s1); + strcpy (result + len1, s2); + strcpy (result + len1 + len2, s3); + *(result + len1 + len2 + len3) = 0; + + return result; +} + +static void +pfatal_with_name (name) + char *name; +{ + fatal (concat ("%s: ", my_strerror (errno), ""), name); +} + +#ifdef __MSDOS__ +/* This is the common prefix we use to make temp file names. */ +char *temp_filename; + +/* Length of the prefix. */ +int temp_filename_length; + +/* Compute a string to use as the base of all temporary file names. */ +static char * +choose_temp_base_try (try, base) +char *try; +char *base; +{ + char *rv; + if (base) + rv = base; + else if (try == (char *)0) + rv = 0; + else if (access (try, R_OK | W_OK) != 0) + rv = 0; + else + rv = try; + return rv; +} + +static void +choose_temp_base () +{ + char *base = 0; + int len; + + base = choose_temp_base_try (getenv ("TMPDIR"), base); + base = choose_temp_base_try (getenv ("TMP"), base); + base = choose_temp_base_try (getenv ("TEMP"), base); + +#ifdef P_tmpdir + base = choose_temp_base_try (P_tmpdir, base); +#endif + + base = choose_temp_base_try ("/usr/tmp", base); + base = choose_temp_base_try ("/tmp", base); + + /* If all else fails, use the current directory! */ + if (base == (char *)0) + base = "./"; + + len = strlen (base); + temp_filename = xmalloc (len + sizeof("/ccXXXXXX")); + strcpy (temp_filename, base); + if (len > 0 && temp_filename[len-1] != '/') + temp_filename[len++] = '/'; + strcpy (temp_filename + len, "ccXXXXXX"); + + mktemp (temp_filename); + temp_filename_length = strlen (temp_filename); + if (temp_filename_length == 0) + abort (); +} + +static void +perror_exec (name) + char *name; +{ + char *s; + + if (errno < sys_nerr) + s = concat ("installation problem, cannot exec %s: ", + my_strerror( errno ), ""); + else + s = "installation problem, cannot exec %s"; + error (s, name); +} + +/* This is almost exactly what's in gcc.c:pexecute for MSDOS. */ +void +run_dos (program, argv) + char *program; + char *argv[]; +{ + char *scmd, *rf; + FILE *argfile; + int i; + + choose_temp_base (); /* not in gcc.c */ + + scmd = (char *) malloc (strlen (program) + strlen (temp_filename) + 10); + rf = scmd + strlen (program) + 6; + sprintf (scmd, "%s.exe @%s.gp", program, temp_filename); + + argfile = fopen (rf, "w"); + if (argfile == 0) + pfatal_with_name (rf); + + for (i=1; argv[i]; i++) + { + char *cp; + for (cp = argv[i]; *cp; cp++) + { + if (*cp == '"' || *cp == '\'' || *cp == '\\' || isspace (*cp)) + fputc ('\\', argfile); + fputc (*cp, argfile); + } + fputc ('\n', argfile); + } + fclose (argfile); + + i = system (scmd); + + remove (rf); + + if (i == -1) + perror_exec (program); +} +#endif /* __MSDOS__ */ + +int +main (argc, argv) + int argc; + char **argv; +{ + register int i, j = 0; + register char *p; + int verbose = 0; + + /* This will be 0 if we encounter a situation where we should not + link in libstdc++, or 2 if we should link in libg++ as well. */ + int library = 1; + + /* Used to track options that take arguments, so we don't go wrapping + those with -xc++/-xnone. */ + char *quote = NULL; + + /* The new argument list will be contained in this. */ + char **arglist; + + /* The name of the compiler we will want to run---by default, it + will be the definition of `GCC_NAME', e.g., `gcc'. */ + char *gcc = GCC_NAME; + + /* Non-zero if we saw a `-xfoo' language specification on the + command line. Used to avoid adding our own -xc++ if the user + already gave a language for the file. */ + int saw_speclang = 0; + + /* Non-zero if we saw `-lm' or `-lmath' on the command line. */ + char *saw_math = 0; + + /* The number of arguments being added to what's in argv, other than + libraries. We use this to track the number of times we've inserted + -xc++/-xnone. */ + int added = 0; + + /* An array used to flag each argument that needs a bit set for + LANGSPEC or MATHLIB. */ + int *args; + + p = argv[0] + strlen (argv[0]); + + /* If we're called as g++ (or i386-aout-g++), link in libg++ as well. */ + + if (strcmp (p - 3, "g++") == 0) + { + library = 2; + } + + while (p != argv[0] && p[-1] != '/') + --p; + programname = p; + + if (argc == 1) + fatal ("No input files specified"); + +#ifndef __MSDOS__ + /* We do a little magic to find out where the main gcc executable + is. If they ran us as /usr/local/bin/g++, then we will look + for /usr/local/bin/gcc; similarly, if they just ran us as `g++', + we'll just look for `gcc'. */ + if (p != argv[0]) + { + *--p = '\0'; + gcc = (char *) malloc ((strlen (argv[0]) + 1 + strlen (GCC_NAME) + 1) + * sizeof (char)); + sprintf (gcc, "%s/%s", argv[0], GCC_NAME); + } +#endif + + args = (int *) malloc (argc * sizeof (int)); + bzero ((char *) args, argc * sizeof (int)); + + for (i = 1; i < argc; i++) + { + /* If the previous option took an argument, we swallow it here. */ + if (quote) + { + quote = NULL; + continue; + } + + if (argv[i][0] == '\0' || argv[i][1] == '\0') + continue; + + if (argv[i][0] == '-') + { + if (library != 0 && strcmp (argv[i], "-nostdlib") == 0) + { + library = 0; + } + else if (strcmp (argv[i], "-lm") == 0 + || strcmp (argv[i], "-lmath") == 0) + args[i] |= MATHLIB; + else if (strcmp (argv[i], "-v") == 0) + { + verbose = 1; + if (argc == 2) + { + /* If they only gave us `-v', don't try to link + in libg++. */ + library = 0; + } + } + else if (strncmp (argv[i], "-x", 2) == 0) + saw_speclang = 1; + else if (((argv[i][2] == '\0' + && (char *)strchr ("bBVDUoeTuIYmLiA", argv[i][1]) != NULL) + || strcmp (argv[i], "-Tdata") == 0)) + quote = argv[i]; + else if (library != 0 && ((argv[i][2] == '\0' + && (char *) strchr ("cSEM", argv[i][1]) != NULL) + || strcmp (argv[i], "-MM") == 0)) + { + /* Don't specify libraries if we won't link, since that would + cause a warning. */ + library = 0; + } + else + /* Pass other options through. */ + continue; + } + else + { + int len; + + if (saw_speclang) + { + saw_speclang = 0; + continue; + } + + /* If the filename ends in .c or .i, put options around it. + But not if a specified -x option is currently active. */ + len = strlen (argv[i]); + if (len > 2 + && (argv[i][len - 1] == 'c' || argv[i][len - 1] == 'i') + && argv[i][len - 2] == '.') + { + args[i] |= LANGSPEC; + added += 2; + } + } + } + + if (quote) + fatal ("argument to `%s' missing\n", quote); + + if (added || library) + { + arglist = (char **) malloc ((argc + added + 4) * sizeof (char *)); + + for (i = 1, j = 1; i < argc; i++, j++) + { + arglist[j] = argv[i]; + + /* Make sure -lg++ is before the math library, since libg++ + itself uses those math routines. */ + if (!saw_math && (args[i] & MATHLIB) && library) + { + --j; + saw_math = argv[i]; + } + + /* Wrap foo.c and foo.i files in a language specification to + force the gcc compiler driver to run cc1plus on them. */ + if (args[i] & LANGSPEC) + { + int len = strlen (argv[i]); + if (argv[i][len - 1] == 'i') + arglist[j++] = "-xc++-cpp-output"; + else + arglist[j++] = "-xc++"; + arglist[j++] = argv[i]; + arglist[j] = "-xnone"; + } + } + + /* Add `-lg++' if we haven't already done so. */ + if (library == 2) + arglist[j++] = "-lg++"; + if (library) + arglist[j++] = "-lstdc++"; + if (saw_math) + arglist[j++] = saw_math; + else if (library) + arglist[j++] = MATH_LIBRARY; + + arglist[j] = NULL; + } + else + /* No need to copy 'em all. */ + arglist = argv; + + arglist[0] = gcc; + + if (verbose) + { + if (j == 0) + j = argc; + + for (i = 0; i < j; i++) + fprintf (stderr, " %s", arglist[i]); + fprintf (stderr, "\n"); + } +#if !defined(OS2) && !defined (_WIN32) +#ifdef __MSDOS__ + run_dos (gcc, arglist); +#else /* !__MSDOS__ */ + if (execvp (gcc, arglist) < 0) + pfatal_with_name (gcc); +#endif /* __MSDOS__ */ +#else /* OS2 or _WIN32 */ + if (spawnvp (1, gcc, arglist) < 0) + pfatal_with_name (gcc); +#endif + + return 0; +} diff --git a/contrib/gcc/cp/gc.c b/contrib/gcc/cp/gc.c new file mode 100644 index 000000000000..cff1635f53a4 --- /dev/null +++ b/contrib/gcc/cp/gc.c @@ -0,0 +1,1550 @@ +/* Garbage collection primitives for GNU C++. + Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +#include "config.h" +#include "tree.h" +#include "cp-tree.h" +#include "flags.h" +#include "output.h" + +#undef NULL +#define NULL 0 + +extern tree define_function (); +extern tree build_t_desc_overload (); +extern struct obstack *permanent_obstack; + +/* This is the function decl for the (pseudo-builtin) __gc_protect + function. Args are (class *value, int index); Returns value. */ +tree gc_protect_fndecl; + +/* This is the function decl for the (pseudo-builtin) __gc_unprotect + function. Args are (int index); void return. */ +tree gc_unprotect_fndecl; + +/* This is the function decl for the (pseudo-builtin) __gc_push + function. Args are (int length); void return. */ +tree gc_push_fndecl; + +/* This is the function decl for the (pseudo-builtin) __gc_pop + function. Args are void; void return. */ +tree gc_pop_fndecl; + +/* Special integers that are used to represent bits in gc-safe objects. */ +tree gc_nonobject; +tree gc_visible; +tree gc_white; +tree gc_offwhite; +tree gc_grey; +tree gc_black; + +/* in c-common.c */ +extern tree combine_strings PROTO((tree)); + +/* Predicate that returns non-zero if TYPE needs some kind of + entry for the GC. Returns zero otherwise. */ +int +type_needs_gc_entry (type) + tree type; +{ + tree ttype = type; + + if (! flag_gc || type == error_mark_node) + return 0; + + /* Aggregate types need gc entries if any of their members + need gc entries. */ + if (IS_AGGR_TYPE (type)) + { + tree binfos; + tree fields = TYPE_FIELDS (type); + int i; + + /* We don't care about certain pointers. Pointers + to virtual baseclasses are always up front. We also + cull out virtual function table pointers because it's + easy, and it simplifies the logic.*/ + while (fields + && (DECL_NAME (fields) == NULL_TREE + || VFIELD_NAME_P (DECL_NAME (fields)) + || VBASE_NAME_P (DECL_NAME (fields)) + || !strcmp (IDENTIFIER_POINTER (DECL_NAME (fields)), "__bits"))) + fields = TREE_CHAIN (fields); + + while (fields) + { + if (type_needs_gc_entry (TREE_TYPE (fields))) + return 1; + fields = TREE_CHAIN (fields); + } + + binfos = TYPE_BINFO_BASETYPES (type); + if (binfos) + for (i = TREE_VEC_LENGTH (binfos)-1; i >= 0; i--) + if (type_needs_gc_entry (BINFO_TYPE (TREE_VEC_ELT (binfos, i)))) + return 1; + + return 0; + } + + while (TREE_CODE (ttype) == ARRAY_TYPE + && TREE_CODE (TREE_TYPE (ttype)) == ARRAY_TYPE) + ttype = TREE_TYPE (ttype); + if ((TREE_CODE (ttype) == POINTER_TYPE + || TREE_CODE (ttype) == ARRAY_TYPE + || TREE_CODE (ttype) == REFERENCE_TYPE) + && IS_AGGR_TYPE (TREE_TYPE (ttype)) + && CLASSTYPE_RTTI (TREE_TYPE (ttype))) + return 1; + + return 0; +} + +/* Predicate that returns non-zero iff FROM is safe from the GC. + + If TO is nonzero, it means we know that FROM is being stored + in TO, which make make it safe. */ +int +value_safe_from_gc (to, from) + tree to, from; +{ + /* First, return non-zero for easy cases: parameters, + static variables. */ + if (TREE_CODE (from) == PARM_DECL + || (TREE_CODE (from) == VAR_DECL + && TREE_STATIC (from))) + return 1; + + /* If something has its address taken, it cannot be + in the heap, so it doesn't need to be protected. */ + if (TREE_CODE (from) == ADDR_EXPR || TREE_REFERENCE_EXPR (from)) + return 1; + + /* If we are storing into a static variable, then what + we store will be safe from the gc. */ + if (to && TREE_CODE (to) == VAR_DECL + && TREE_STATIC (to)) + return 1; + + /* Now recurse on structure of FROM. */ + switch (TREE_CODE (from)) + { + case COMPONENT_REF: + /* These guys are special, and safe. */ + if (TREE_CODE (TREE_OPERAND (from, 1)) == FIELD_DECL + && (VFIELD_NAME_P (DECL_NAME (TREE_OPERAND (from, 1))) + || VBASE_NAME_P (DECL_NAME (TREE_OPERAND (from, 1))))) + return 1; + /* fall through... */ + case NOP_EXPR: + case CONVERT_EXPR: + case NON_LVALUE_EXPR: + case WITH_CLEANUP_EXPR: + case SAVE_EXPR: + case PREDECREMENT_EXPR: + case PREINCREMENT_EXPR: + case POSTDECREMENT_EXPR: + case POSTINCREMENT_EXPR: + if (value_safe_from_gc (to, TREE_OPERAND (from, 0))) + return 1; + break; + + case VAR_DECL: + case PARM_DECL: + /* We can safely pass these things as parameters to functions. */ + if (to == 0) + return 1; + + case ARRAY_REF: + case INDIRECT_REF: + case RESULT_DECL: + case OFFSET_REF: + case CALL_EXPR: + case METHOD_CALL_EXPR: + break; + + case COMPOUND_EXPR: + case TARGET_EXPR: + if (value_safe_from_gc (to, TREE_OPERAND (from, 1))) + return 1; + break; + + case COND_EXPR: + if (value_safe_from_gc (to, TREE_OPERAND (from, 1)) + && value_safe_from_gc (to, TREE_OPERAND (from, 2))) + return 1; + break; + + case PLUS_EXPR: + case MINUS_EXPR: + if ((type_needs_gc_entry (TREE_TYPE (TREE_OPERAND (from, 0))) + || value_safe_from_gc (to, TREE_OPERAND (from, 0))) + && (type_needs_gc_entry (TREE_TYPE (TREE_OPERAND (from, 1))) == 0 + || value_safe_from_gc (to, TREE_OPERAND (from, 1)))) + return 1; + break; + + case RTL_EXPR: + /* Every time we build an RTL_EXPR in the front-end, we must + ensure that everything in it is safe from the garbage collector. + ??? This has only been done for `build_new'. */ + return 1; + + default: + my_friendly_abort (41); + } + + if (to == 0) + return 0; + + /* FROM wasn't safe. But other properties of TO might make it safe. */ + switch (TREE_CODE (to)) + { + case VAR_DECL: + case PARM_DECL: + /* We already culled out static VAR_DECLs above. */ + return 0; + + case COMPONENT_REF: + /* These guys are special, and safe. */ + if (TREE_CODE (TREE_OPERAND (to, 1)) == FIELD_DECL + && (VFIELD_NAME_P (DECL_NAME (TREE_OPERAND (to, 1))) + || VBASE_NAME_P (DECL_NAME (TREE_OPERAND (to, 1))))) + return 1; + /* fall through... */ + + case NOP_EXPR: + case NON_LVALUE_EXPR: + case WITH_CLEANUP_EXPR: + case SAVE_EXPR: + case PREDECREMENT_EXPR: + case PREINCREMENT_EXPR: + case POSTDECREMENT_EXPR: + case POSTINCREMENT_EXPR: + return value_safe_from_gc (TREE_OPERAND (to, 0), from); + + case COMPOUND_EXPR: + case TARGET_EXPR: + return value_safe_from_gc (TREE_OPERAND (to, 1), from); + + case COND_EXPR: + return (value_safe_from_gc (TREE_OPERAND (to, 1), from) + && value_safe_from_gc (TREE_OPERAND (to, 2), from)); + + case INDIRECT_REF: + case ARRAY_REF: + /* This used to be 0, but our current restricted model + allows this to be 1. We'll never get arrays this way. */ + return 1; + + default: + my_friendly_abort (42); + } + + /* Catch-all case is that TO/FROM is not safe. */ + return 0; +} + +/* Function to build a static GC entry for DECL. TYPE is DECL's type. + + For objects of type `class *', this is just an entry in the + static vector __PTR_LIST__. + + For objects of type `class[]', this requires building an entry + in the static vector __ARR_LIST__. + + For aggregates, this records all fields of type `class *' + and `class[]' in the respective lists above. */ +void +build_static_gc_entry (decl, type) + tree decl; + tree type; +{ + /* Now, figure out what sort of entry to build. */ + if (TREE_CODE (type) == POINTER_TYPE + || TREE_CODE (type) == REFERENCE_TYPE) + assemble_gc_entry (IDENTIFIER_POINTER (DECL_NAME (decl))); + else if (TREE_CODE (type) == RECORD_TYPE) + { + tree ref = get_temp_name (build_reference_type (type), 1); + DECL_INITIAL (ref) = build1 (ADDR_EXPR, TREE_TYPE (ref), decl); + TREE_CONSTANT (DECL_INITIAL (ref)) = 1; + cp_finish_decl (ref, DECL_INITIAL (ref), NULL_TREE, 0, 0); + } + else + { + /* Not yet implemented. + + Cons up a static variable that holds address and length info + and add that to ___ARR_LIST__. */ + my_friendly_abort (43); + } +} + +/* Protect FROM from the GC, assuming FROM is going to be + stored into TO. We handle three cases for TO here: + + case 1: TO is a stack variable. + case 2: TO is zero (which means it is a parameter). + case 3: TO is a return value. */ + +tree +protect_value_from_gc (to, from) + tree to, from; +{ + if (to == 0) + { + tree cleanup; + + to = get_temp_regvar (TREE_TYPE (from), from); + + /* Convert from integer to list form since we'll use it twice. */ + DECL_GC_OFFSET (to) = build_tree_list (NULL_TREE, DECL_GC_OFFSET (to)); + cleanup = build_function_call (gc_unprotect_fndecl, + DECL_GC_OFFSET (to)); + + if (! cp_expand_decl_cleanup (to, cleanup)) + { + compiler_error ("cannot unprotect parameter in this scope"); + return error_mark_node; + } + } + + /* Should never need to protect a value that's headed for static storage. */ + if (TREE_STATIC (to)) + my_friendly_abort (44); + + switch (TREE_CODE (to)) + { + case COMPONENT_REF: + case INDIRECT_REF: + return protect_value_from_gc (TREE_OPERAND (to, 0), from); + + case VAR_DECL: + case PARM_DECL: + { + tree rval; + if (DECL_GC_OFFSET (to) == NULL_TREE) + { + /* Because of a cast or a conversion, we might stick + a value into a variable that would not normally + have a GC entry. */ + DECL_GC_OFFSET (to) = size_int (++current_function_obstack_index); + } + + if (TREE_CODE (DECL_GC_OFFSET (to)) != TREE_LIST) + { + DECL_GC_OFFSET (to) + = build_tree_list (NULL_TREE, DECL_GC_OFFSET (to)); + } + + current_function_obstack_usage = 1; + rval = build_function_call (gc_protect_fndecl, + tree_cons (NULL_TREE, from, + DECL_GC_OFFSET (to))); + TREE_TYPE (rval) = TREE_TYPE (from); + return rval; + } + } + + /* If we fall through the switch, assume we lost. */ + my_friendly_abort (45); + /* NOTREACHED */ + return NULL_TREE; +} + +/* Given the expression EXP of type `class *', return the head + of the object pointed to by EXP. */ +tree +build_headof (exp) + tree exp; +{ + tree type = TREE_TYPE (exp); + tree vptr, offset; + + if (TREE_CODE (type) != POINTER_TYPE) + { + error ("`headof' applied to non-pointer type"); + return error_mark_node; + } + type = TREE_TYPE (type); + + if (!TYPE_VIRTUAL_P (type) || CLASSTYPE_VFIELD (type) == NULL_TREE) + return exp; + + vptr = fold (size_binop (PLUS_EXPR, + size_binop (FLOOR_DIV_EXPR, + DECL_FIELD_BITPOS (CLASSTYPE_VFIELD (type)), + size_int (BITS_PER_UNIT)), + exp)); + vptr = build1 (INDIRECT_REF, build_pointer_type (vtable_entry_type), vptr); + + if (flag_vtable_thunks) + offset = build_array_ref (vptr, integer_zero_node); + else + offset = build_component_ref (build_array_ref (vptr, integer_zero_node), + delta_identifier, + NULL_TREE, 0); + + type = build_type_variant (ptr_type_node, TREE_READONLY (exp), + TREE_THIS_VOLATILE (exp)); + return build (PLUS_EXPR, type, exp, + convert (ptrdiff_type_node, offset)); +} + +/* Return the type_info node associated with the expression EXP. If EXP is + a reference to a polymorphic class, return the dynamic type; otherwise + return the static type of the expression. */ +tree +build_typeid (exp) + tree exp; +{ + tree type; + + if (!flag_rtti) + cp_error ("cannot take typeid of object when -frtti is not specified"); + + if (exp == error_mark_node) + return error_mark_node; + + type = TREE_TYPE (exp); + + /* Strip top-level cv-qualifiers. */ + type = TYPE_MAIN_VARIANT (type); + + /* if b is an instance of B, typeid(b) == typeid(B). Do this before + reference trickiness. */ + if (TREE_CODE (exp) == VAR_DECL && TREE_CODE (type) == RECORD_TYPE) + return get_typeid (type); + + /* peel back references, so they match. */ + if (TREE_CODE (type) == REFERENCE_TYPE) + type = TREE_TYPE (type); + + /* Peel off cv qualifiers. */ + type = TYPE_MAIN_VARIANT (type); + + /* Apply trivial conversion T -> T& for dereferenced ptrs. */ + if (TREE_CODE (type) == RECORD_TYPE) + type = build_reference_type (type); + + /* If exp is a reference to polymorphic type, get the real type_info. */ + if (TREE_CODE (type) == REFERENCE_TYPE && TYPE_VIRTUAL_P (TREE_TYPE (type))) + { + /* build reference to type_info from vtable. */ + tree t; + + if (flag_vtable_thunks) + t = build_vfn_ref ((tree *) NULL_TREE, exp, integer_one_node); + else + t = build_vfn_ref ((tree *) NULL_TREE, exp, integer_zero_node); + + TREE_TYPE (t) = build_pointer_type (__class_desc_type_node); + t = build_indirect_ref (t, NULL); + return t; + } + + /* otherwise return the type_info for the static type of the expr. */ + return get_typeid (type); +} + +/* Return the type_info object for TYPE, creating it if necessary. */ +tree +get_typeid (type) + tree type; +{ + tree t, td; + + if (type == error_mark_node) + return error_mark_node; + + /* Is it useful (and/or correct) to have different typeids for `T &' + and `T'? */ + if (TREE_CODE (type) == REFERENCE_TYPE) + type = TREE_TYPE (type); + + td = build_t_desc (type, 1); + if (td == error_mark_node) + return error_mark_node; + + t = TREE_OPERAND (td, 0); + return t; +} + +/* Get a bad_cast node for the program to throw... + + See libstdc++::exception{,.cc} for __bad_cast_object */ +tree +get_bad_cast_node () +{ + static tree t; + if (t == NULL_TREE + && (t = lookup_name (get_identifier ("__bad_cast_object"), 0)) + == NULL_TREE) + { + error ("you must #include <typeinfo>"); + return error_mark_node; + } + return t; +} + +/* Execute a dynamic cast, as described in section 5.2.6 of the 9/93 working + paper. */ +tree +build_dynamic_cast (type, expr) + tree type, expr; +{ + enum tree_code tc = TREE_CODE (type); + tree exprtype = TREE_TYPE (expr); + enum tree_code ec = TREE_CODE (exprtype); + tree retval; + + if (type == error_mark_node || expr == error_mark_node) + return error_mark_node; + + switch (tc) + { + case POINTER_TYPE: + if (ec == REFERENCE_TYPE) + { + expr = convert_from_reference (expr); + exprtype = TREE_TYPE (expr); + ec = TREE_CODE (exprtype); + } + if (ec != POINTER_TYPE) + goto fail; + if (TREE_CODE (TREE_TYPE (exprtype)) != RECORD_TYPE) + goto fail; + if (TYPE_SIZE (TREE_TYPE (exprtype)) == 0) + goto fail; + if (TREE_READONLY (TREE_TYPE (exprtype)) && + ! TYPE_READONLY (TREE_TYPE (type))) + goto fail; + if (TYPE_MAIN_VARIANT (TREE_TYPE (type)) == void_type_node) + break; + /* else fall through */ + case REFERENCE_TYPE: + if (TREE_CODE (TREE_TYPE (type)) == RECORD_TYPE + && TYPE_SIZE (TREE_TYPE (type)) != NULL_TREE) + break; + /* else fall through */ + default: + goto fail; + } + + /* Apply trivial conversion T -> T& for dereferenced ptrs. */ + if (ec == RECORD_TYPE) + { + exprtype = build_type_variant (exprtype, TREE_READONLY (expr), + TREE_THIS_VOLATILE (expr)); + exprtype = build_reference_type (exprtype); + expr = convert_to_reference (exprtype, expr, CONV_IMPLICIT, + LOOKUP_NORMAL, NULL_TREE); + ec = REFERENCE_TYPE; + } + + if (tc == REFERENCE_TYPE) + { + if (ec != REFERENCE_TYPE) + goto fail; + if (TREE_CODE (TREE_TYPE (exprtype)) != RECORD_TYPE) + goto fail; + if (TYPE_SIZE (TREE_TYPE (exprtype)) == 0) + goto fail; + } + + /* If *type is an unambiguous accessible base class of *exprtype, + convert statically. */ + { + int distance; + tree path; + + distance = get_base_distance (TREE_TYPE (type), TREE_TYPE (exprtype), 1, + &path); + if (distance >= 0) + return build_vbase_path (PLUS_EXPR, type, expr, path, 0); + } + + /* Otherwise *exprtype must be a polymorphic class (have a vtbl). */ + if (TYPE_VIRTUAL_P (TREE_TYPE (exprtype))) + { + /* if TYPE is `void *', return pointer to complete object. */ + if (tc == POINTER_TYPE + && TYPE_MAIN_VARIANT (TREE_TYPE (type)) == void_type_node) + { + /* if b is an object, dynamic_cast<void *>(&b) == (void *)&b. */ + if (TREE_CODE (expr) == ADDR_EXPR + && TREE_CODE (TREE_OPERAND (expr, 0)) == VAR_DECL + && TREE_CODE (TREE_TYPE (TREE_OPERAND (expr, 0))) == RECORD_TYPE) + return build1 (NOP_EXPR, type, expr); + + return build_headof (expr); + } + else + { + tree retval; + tree result, td1, td2, elems, tmp1, expr1; + + /* If we got here, we can't convert statically. Therefore, + dynamic_cast<D&>(b) (b an object) cannot succeed. */ + if (ec == REFERENCE_TYPE) + { + if (TREE_CODE (expr) == VAR_DECL + && TREE_CODE (TREE_TYPE (expr)) == RECORD_TYPE) + { + cp_warning ("dynamic_cast of `%#D' to `%#T' can never succeed", + expr, type); + return build_throw (get_bad_cast_node ()); + } + } + /* Ditto for dynamic_cast<D*>(&b). */ + else if (TREE_CODE (expr) == ADDR_EXPR) + { + tree op = TREE_OPERAND (expr, 0); + if (TREE_CODE (op) == VAR_DECL + && TREE_CODE (TREE_TYPE (op)) == RECORD_TYPE) + { + cp_warning ("dynamic_cast of `%#D' to `%#T' can never succeed", + expr, type); + retval = build_int_2 (0, 0); + TREE_TYPE (retval) = type; + return retval; + } + } + + expr1 = expr; + if (tc == REFERENCE_TYPE) + expr1 = build_unary_op (ADDR_EXPR, expr1, 0); + + /* Build run-time conversion. */ + expr1 = build_headof (expr1); + + if (ec == POINTER_TYPE) + td1 = build_typeid (build_indirect_ref (expr, NULL_PTR)); + else + td1 = build_typeid (expr); + + if (tc == POINTER_TYPE) + td2 = get_typeid (TREE_TYPE (type)); + else + td2 = get_typeid (type); + + elems = tree_cons (NULL_TREE, td2, + tree_cons (NULL_TREE, build_int_2 (1, 0), + tree_cons (NULL_TREE, expr1, NULL_TREE))); + result = build_method_call (td1, + get_identifier ("__rtti_match"), elems, NULL_TREE, LOOKUP_NORMAL); + + if (tc == REFERENCE_TYPE) + { + expr1 = build_throw (get_bad_cast_node ()); + expr1 = build_compound_expr (tree_cons (NULL_TREE, expr1, + build_tree_list (NULL_TREE, convert (type, integer_zero_node)))); + TREE_TYPE (expr1) = type; + return build (COND_EXPR, type, result, result, expr1); + } + + /* Now back to the type we want from a void*. */ + result = convert (type, result); + return result; + } + } + + fail: + cp_error ("cannot dynamic_cast `%E' (of type `%#T') to type `%#T'", + expr, exprtype, type); + return error_mark_node; +} + +/* Build and initialize various sorts of descriptors. Every descriptor + node has a name associated with it (the name created by mangling). + For this reason, we use the identifier as our access to the __*_desc + nodes, instead of sticking them directly in the types. Otherwise we + would burden all built-in types (and pointer types) with slots that + we don't necessarily want to use. + + For each descriptor we build, we build a variable that contains + the descriptor's information. When we need this info at runtime, + all we need is access to these variables. + + Note: these constructors always return the address of the descriptor + info, since that is simplest for their mutual interaction. */ + +static tree +build_generic_desc (tdecl, type, elems) + tree tdecl; + tree type; + tree elems; +{ + tree init = elems; + int toplev = global_bindings_p (); + + TREE_CONSTANT (init) = 1; + TREE_STATIC (init) = 1; + TREE_READONLY (init) = 1; + + TREE_TYPE (tdecl) = type; + DECL_INITIAL (tdecl) = init; + TREE_STATIC (tdecl) = 1; + DECL_SIZE (tdecl) = NULL_TREE; + layout_decl (tdecl, 0); + if (! toplev) + push_to_top_level (); + cp_finish_decl (tdecl, init, NULL_TREE, 0, 0); + if (! toplev) + pop_from_top_level (); + + if (! TREE_USED (tdecl)) + { + assemble_external (tdecl); + TREE_USED (tdecl) = 1; + } + + return IDENTIFIER_AS_DESC (DECL_NAME (tdecl)); +} + +/* Build an initializer for a __bltn_desc node. */ +static tree +build_bltn_desc (tdecl, type) + tree tdecl; + tree type; +{ + tree elems, t; + + if (type == boolean_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_BOOL"), + 0, 0); + else if (type == char_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_CHAR"), + 0, 0); + else if (type == short_integer_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_SHORT"), + 0, 0); + else if (type == integer_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_INT"), + 0, 0); + else if (type == long_integer_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_LONG"), + 0, 0); + else if (type == long_long_integer_type_node) + t = lookup_field (__bltn_desc_type_node, + get_identifier("_RTTI_BI_LONGLONG"), 0, 0); + else if (type == float_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_FLOAT"), + 0, 0); + else if (type == double_type_node) + t = lookup_field (__bltn_desc_type_node, + get_identifier("_RTTI_BI_DOUBLE"), 0, 0); + else if (type == long_double_type_node) + t = lookup_field (__bltn_desc_type_node, + get_identifier("_RTTI_BI_LDOUBLE"), 0, 0); + else if (type == unsigned_char_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_UCHAR"), + 0, 0); + else if (type == short_unsigned_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_USHORT"), + 0, 0); + else if (type == unsigned_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_UINT"), + 0, 0); + else if (type == long_unsigned_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_ULONG"), + 0, 0); + else if (type == long_long_unsigned_type_node) + t = lookup_field (__bltn_desc_type_node, + get_identifier("_RTTI_BI_ULONGLONG"), 0, 0); + else if (type == signed_char_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_SCHAR"), + 0, 0); + else if (type == wchar_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_WCHAR"), + 0, 0); + else if (type == void_type_node) + t = lookup_field (__bltn_desc_type_node, get_identifier("_RTTI_BI_VOID"), + 0, 0); + else + { + cp_compiler_error ("type `%T' not handled as a built-in type"); + } + + elems = tree_cons (NULL_TREE, t, NULL_TREE); + return build_generic_desc (tdecl, __bltn_desc_type_node, elems); +} + +/* Build an initializer for a __user_desc node. */ +static tree +build_user_desc (tdecl) + tree tdecl; +{ + tree elems, name_string, t; + tree tname = DECL_NAME (tdecl); + + name_string = combine_strings (build_string + (IDENTIFIER_LENGTH (tname)+1, IDENTIFIER_POINTER (tname))); + elems = name_string; + return build_generic_desc (tdecl, __user_desc_type_node, elems); +} + +/* Build an initializer for a __class_type_info node. */ +static tree +build_class_desc (tdecl, type) + tree tdecl; + tree type; +{ + tree tname = DECL_NAME (tdecl); + tree name_string; + + int i = CLASSTYPE_N_BASECLASSES (type); + int n_base = i; + int base_cnt = 0; + tree binfos = TYPE_BINFO_BASETYPES (type); + tree vb = CLASSTYPE_VBASECLASSES (type); + tree base, elems, access, offset, isvir; + tree base_list, off_list, acc_list, isvir_list; + tree t; + static tree acc_pub = NULL_TREE; + static tree acc_pro = NULL_TREE; + static tree acc_pri = NULL_TREE; + + if (acc_pub == NULL_TREE) + { + acc_pub = lookup_field (__class_desc_type_node, + get_identifier("_RTTI_ACCESS_PUBLIC"), 0, 0); + acc_pro = lookup_field (__class_desc_type_node, + get_identifier("_RTTI_ACCESS_PROTECTED"), 0, 0); + acc_pri = lookup_field (__class_desc_type_node, + get_identifier("_RTTI_ACCESS_PRIVATE"), 0, 0); + } + + base_list = build_tree_list (NULL_TREE, integer_zero_node); + off_list = build_tree_list (NULL_TREE, integer_zero_node); + acc_list = build_tree_list (NULL_TREE, integer_zero_node); + isvir_list = build_tree_list (NULL_TREE, integer_zero_node); + while (--i >= 0) + { + tree binfo = TREE_VEC_ELT (binfos, i); + + base = build_t_desc (BINFO_TYPE (binfo), 1); + if (TREE_VIA_VIRTUAL (binfo)) + { + tree t = BINFO_TYPE (binfo); + char *name; + tree field; + int off; + + name = (char *) alloca (TYPE_NAME_LENGTH (t)+sizeof (VBASE_NAME)+1); + sprintf (name, VBASE_NAME_FORMAT, TYPE_NAME_STRING (t)); + field = lookup_field (type, get_identifier (name), 0, 0); + offset = size_binop (FLOOR_DIV_EXPR, + DECL_FIELD_BITPOS (field), size_int (BITS_PER_UNIT)); + } + else + offset = BINFO_OFFSET (binfo); + + if (TREE_VIA_PUBLIC (binfo)) + access = acc_pub; + else if (TREE_VIA_PROTECTED (binfo)) + access = acc_pro; + else + access = acc_pri; + if (TREE_VIA_VIRTUAL (binfo)) + isvir = build_int_2 (1, 0); + else + isvir = build_int_2 (0, 0); + + base_list = tree_cons (NULL_TREE, base, base_list); + isvir_list = tree_cons (NULL_TREE, isvir, isvir_list); + acc_list = tree_cons (NULL_TREE, access, acc_list); + off_list = tree_cons (NULL_TREE, offset, off_list); + base_cnt++; + } +#if 0 + i = n_base; + while (vb) + { + tree b; + access = acc_pub; + while (--i >= 0) + { + b = TREE_VEC_ELT (binfos, i); + if (BINFO_TYPE (vb) == BINFO_TYPE (b) && TREE_VIA_VIRTUAL (b)) + { + if (TREE_VIA_PUBLIC (b)) + access = acc_pub; + else if (TREE_VIA_PROTECTED (b)) + access = acc_pro; + else + access = acc_pri; + break; + } + } + base = build_t_desc (BINFO_TYPE (vb), 1); + offset = BINFO_OFFSET (vb); + isvir = build_int_2 (1, 0); + + base_list = tree_cons (NULL_TREE, base, base_list); + isvir_list = tree_cons (NULL_TREE, isvir, isvir_list); + acc_list = tree_cons (NULL_TREE, access, acc_list); + off_list = tree_cons (NULL_TREE, offset, off_list); + + base_cnt++; + vb = TREE_CHAIN (vb); + } +#endif + base_list = finish_table (NULL_TREE, build_pointer_type (__t_desc_type_node), + base_list, 0); + off_list = finish_table (NULL_TREE, integer_type_node, + off_list, 0); + isvir_list = finish_table (NULL_TREE, integer_type_node, + isvir_list, 0); + acc_list = finish_table (NULL_TREE, __access_mode_type_node, + acc_list, 0); + + + name_string = combine_strings (build_string (IDENTIFIER_LENGTH (tname)+1, IDENTIFIER_POINTER (tname))); + + elems = tree_cons (NULL_TREE, name_string, + tree_cons (NULL_TREE, default_conversion (base_list), + tree_cons (NULL_TREE, default_conversion (off_list), + tree_cons (NULL_TREE, default_conversion (isvir_list), + tree_cons (NULL_TREE, default_conversion (acc_list), + tree_cons (NULL_TREE, build_int_2 (base_cnt, 0), NULL_TREE)))))); + + return build_generic_desc (tdecl, __class_desc_type_node, elems); +} + +/* Build an initializer for a __pointer_type_info node. */ +static tree +build_ptr_desc (tdecl, type) + tree tdecl; + tree type; +{ + tree t, elems; + + t = TREE_TYPE (type); + t = build_t_desc (t, 1); + t = build_indirect_ref (t, NULL); + elems = tree_cons (NULL_TREE, t, NULL_TREE); + return build_generic_desc (tdecl, __ptr_desc_type_node, elems); +} + +/* Build an initializer for a __attr_type_info node. */ +static tree +build_attr_desc (tdecl, type) + tree tdecl; + tree type; +{ + tree elems, t, attrval; + + if (TYPE_READONLY (type)) + { + if (TYPE_VOLATILE (type)) + attrval = lookup_field (__attr_desc_type_node, + get_identifier("_RTTI_ATTR_CONSTVOL"), 0, 0); + else + attrval = lookup_field (__attr_desc_type_node, + get_identifier("_RTTI_ATTR_CONST"), 0, 0); + } + else + { + if (TYPE_VOLATILE (type)) + attrval = lookup_field (__attr_desc_type_node, + get_identifier("_RTTI_ATTR_VOLATILE"), 0, 0); + } + t = build_t_desc (TYPE_MAIN_VARIANT (type), 1); + t = build_indirect_ref (t , NULL); + elems = tree_cons (NULL_TREE, attrval, tree_cons (NULL_TREE, t, NULL_TREE)); + return build_generic_desc (tdecl, __attr_desc_type_node, elems); +} + +/* Build an initializer for a __func_type_info node. */ +static tree +build_func_desc (tdecl) + tree tdecl; +{ + tree elems, name_string; + tree tname = DECL_NAME (tdecl); + + name_string = combine_strings (build_string + (IDENTIFIER_LENGTH (tname)+1, IDENTIFIER_POINTER (tname))); + elems = name_string; + return build_generic_desc (tdecl, __func_desc_type_node, elems); +} + +/* Build an initializer for a __ptmf_type_info node. */ +static tree +build_ptmf_desc (tdecl, type) + tree tdecl; + tree type; +{ + tree elems, name_string; + tree tname = DECL_NAME (tdecl); + + name_string = combine_strings (build_string + (IDENTIFIER_LENGTH (tname)+1, IDENTIFIER_POINTER (tname))); + elems = name_string; + return build_generic_desc (tdecl, __ptmf_desc_type_node, elems); +} + +/* Build an initializer for a __ptmd_type_info node. */ +static tree +build_ptmd_desc (tdecl, type) + tree tdecl; + tree type; +{ + tree tc, t, elems; + tc = build_t_desc (TYPE_OFFSET_BASETYPE (type), 1); + tc = build_indirect_ref (tc , NULL); + t = build_t_desc (TREE_TYPE (type), 1); + t = build_indirect_ref (t , NULL); + elems = tree_cons (NULL_TREE, tc, + tree_cons (NULL_TREE, t, NULL_TREE)); + return build_generic_desc (tdecl, __ptmd_desc_type_node, elems); +} + +struct uninst_st { + tree type; + struct uninst_st *next; +}; +typedef struct uninst_st uninst_node; +static uninst_node * uninst_desc = (uninst_node *)NULL; + +static void +add_uninstantiated_desc (type) + tree type; +{ + uninst_node *t; + + t = (uninst_node *) xmalloc (sizeof (struct uninst_st)); + t->type = type; + t->next = uninst_desc; + uninst_desc = t; +} + +/* We may choose to link the emitting of certain high use TDs for certain + objects, we do that here. Return the type to link against if such a + link exists, otherwise just return TYPE. */ + +tree +get_def_to_follow (type) + tree type; +{ +#if 0 + /* For now we don't lay out T&, T* TDs with the main TD for the object. */ + /* Let T* and T& be written only when T is written (if T is an aggr). + We do this for const, but not for volatile, since volatile + is rare and const is not. */ + if (!TYPE_VOLATILE (taggr) + && (TREE_CODE (taggr) == POINTER_TYPE + || TREE_CODE (taggr) == REFERENCE_TYPE) + && IS_AGGR_TYPE (TREE_TYPE (taggr))) + taggr = TREE_TYPE (taggr); +#endif + return type; +} + +/* build a general type_info node. */ +tree +build_t_desc (type, definition) + tree type; + int definition; +{ + tree tdecl; + tree tname, name_string; + tree elems; + tree t, tt, taggr; + + if (__ptmd_desc_type_node == NULL_TREE) + { + init_type_desc(); + if (__ptmd_desc_type_node) + { + for ( ; uninst_desc; uninst_desc = uninst_desc->next ) + build_t_desc (uninst_desc->type, 1); + } + } + if (__t_desc_type_node == NULL_TREE) + { + static int warned = 0; + if (! warned) + { + cp_error ("failed to build type descriptor node of '%T', maybe typeinfo.h not included", type); + } + warned = 1; + return error_mark_node; + } + if (__ptmd_desc_type_node == NULL_TREE) + { + add_uninstantiated_desc (type); + definition = 0; + } + + push_obstacks (&permanent_obstack, &permanent_obstack); + tname = build_t_desc_overload (type); + + if (!IDENTIFIER_AS_DESC (tname)) + { + tdecl = build_decl (VAR_DECL, tname, __t_desc_type_node); + DECL_EXTERNAL (tdecl) = 1; + TREE_PUBLIC (tdecl) = 1; + tdecl = pushdecl_top_level (tdecl); + SET_IDENTIFIER_AS_DESC (tname, build_unary_op (ADDR_EXPR, tdecl, 0)); + if (!definition) + cp_finish_decl (tdecl, NULL_TREE, NULL_TREE, 0, 0); + } + else + tdecl = TREE_OPERAND (IDENTIFIER_AS_DESC (tname), 0); + + /* If it's not a definition, don't do anything more. */ + if (!definition) + return IDENTIFIER_AS_DESC (tname); + + /* If it has already been written, don't to anything more. */ + /* Should this be on tdecl? */ + if (TREE_ASM_WRITTEN (IDENTIFIER_AS_DESC (tname))) + return IDENTIFIER_AS_DESC (tname); + + /* If we previously defined it, return the defined result. */ + if (DECL_INITIAL (tdecl)) + return IDENTIFIER_AS_DESC (tname); + + taggr = get_def_to_follow (type); + + /* If we know that we don't need to write out this type's + vtable, then don't write out it's type_info. Somebody + else will take care of that. */ + if (IS_AGGR_TYPE (taggr) && CLASSTYPE_VFIELD (taggr)) + { + /* Let's play follow the vtable. */ + TREE_PUBLIC (tdecl) = CLASSTYPE_INTERFACE_KNOWN (taggr); + DECL_EXTERNAL (tdecl) = CLASSTYPE_INTERFACE_ONLY (taggr); + } + else + { + DECL_EXTERNAL (tdecl) = 0; + TREE_PUBLIC (tdecl) = (definition > 1); + } + + if (DECL_EXTERNAL (tdecl)) + return IDENTIFIER_AS_DESC (tname); + + /* Show that we are defining the t_desc for this type. */ + DECL_INITIAL (tdecl) = error_mark_node; + t = DECL_CONTEXT (tdecl); + if ( t && TREE_CODE_CLASS (TREE_CODE (t)) == 't') + pushclass (t, 2); + + if (TYPE_VOLATILE (type) || TYPE_READONLY (type)) + t = build_attr_desc (tdecl, type); + else if (TREE_CODE (type) == ARRAY_TYPE) + t = build_ptr_desc (tdecl, type); + else if (TREE_CODE (type) == POINTER_TYPE) + { + if (TREE_CODE (TREE_TYPE (type)) == OFFSET_TYPE) + { + type = TREE_TYPE (type); + t = build_ptmd_desc (tdecl, type); + } + else + { + t = build_ptr_desc (tdecl, type); + } + } + else if (TYPE_BUILT_IN (type)) + t = build_bltn_desc (tdecl, type); + else if (IS_AGGR_TYPE (type)) + { + if (TYPE_PTRMEMFUNC_P (type)) + { + t = build_ptmf_desc (tdecl, type); + } + else + { + t = build_class_desc (tdecl, type); + } + } + else if (TREE_CODE (type) == FUNCTION_TYPE) + t = build_func_desc (tdecl); + else + t = build_user_desc (tdecl); + + pop_obstacks (); + return t; +} + +#if 0 +/* This is the old dossier type descriptor generation code, it's much + more extended than rtti. It's reserved for later use. */ +/* Build an initializer for a __t_desc node. So that we can take advantage + of recursion, we accept NULL for TYPE. + DEFINITION is greater than zero iff we must define the type descriptor + (as opposed to merely referencing it). 1 means treat according to + #pragma interface/#pragma implementation rules. 2 means define as + global and public, no matter what. */ +tree +build_t_desc (type, definition) + tree type; + int definition; +{ + tree tdecl; + tree tname, name_string; + tree elems, fields; + tree parents, vbases, offsets, ivars, methods, target_type; + int method_count = 0, field_count = 0; + + if (type == NULL_TREE) + return NULL_TREE; + + tname = build_t_desc_overload (type); + if (IDENTIFIER_AS_DESC (tname) + && (!definition || TREE_ASM_WRITTEN (IDENTIFIER_AS_DESC (tname)))) + return IDENTIFIER_AS_DESC (tname); + + tdecl = lookup_name (tname, 0); + if (tdecl == NULL_TREE) + { + tdecl = build_decl (VAR_DECL, tname, __t_desc_type_node); + DECL_EXTERNAL (tdecl) = 1; + TREE_PUBLIC (tdecl) = 1; + tdecl = pushdecl_top_level (tdecl); + } + /* If we previously defined it, return the defined result. */ + else if (definition && DECL_INITIAL (tdecl)) + return IDENTIFIER_AS_DESC (tname); + + if (definition) + { + tree taggr = type; + /* Let T* and T& be written only when T is written (if T is an aggr). + We do this for const, but not for volatile, since volatile + is rare and const is not. */ + if (!TYPE_VOLATILE (taggr) + && (TREE_CODE (taggr) == POINTER_TYPE + || TREE_CODE (taggr) == REFERENCE_TYPE) + && IS_AGGR_TYPE (TREE_TYPE (taggr))) + taggr = TREE_TYPE (taggr); + + /* If we know that we don't need to write out this type's + vtable, then don't write out it's dossier. Somebody + else will take care of that. */ + if (IS_AGGR_TYPE (taggr) && CLASSTYPE_VFIELD (taggr)) + { + if (CLASSTYPE_VTABLE_NEEDS_WRITING (taggr)) + { + TREE_PUBLIC (tdecl) = ! CLASSTYPE_INTERFACE_ONLY (taggr) + && CLASSTYPE_INTERFACE_KNOWN (taggr); + DECL_EXTERNAL (tdecl) = 0; + } + else + { + if (write_virtuals != 0) + TREE_PUBLIC (tdecl) = 1; + } + } + else + { + DECL_EXTERNAL (tdecl) = 0; + TREE_PUBLIC (tdecl) = (definition > 1); + } + } + SET_IDENTIFIER_AS_DESC (tname, build_unary_op (ADDR_EXPR, tdecl, 0)); + + if (!definition || DECL_EXTERNAL (tdecl)) + { + /* That's it! */ + cp_finish_decl (tdecl, NULL_TREE, NULL_TREE, 0, 0); + return IDENTIFIER_AS_DESC (tname); + } + + /* Show that we are defining the t_desc for this type. */ + DECL_INITIAL (tdecl) = error_mark_node; + + parents = build_tree_list (NULL_TREE, integer_zero_node); + vbases = build_tree_list (NULL_TREE, integer_zero_node); + offsets = build_tree_list (NULL_TREE, integer_zero_node); + methods = NULL_TREE; + ivars = NULL_TREE; + + if (TYPE_LANG_SPECIFIC (type)) + { + int i = CLASSTYPE_N_BASECLASSES (type); + tree method_vec = CLASSTYPE_METHOD_VEC (type); + tree *meth, *end; + tree binfos = TYPE_BINFO_BASETYPES (type); + tree vb = CLASSTYPE_VBASECLASSES (type); + + while (--i >= 0) + parents = tree_cons (NULL_TREE, build_t_desc (BINFO_TYPE (TREE_VEC_ELT (binfos, i)), 0), parents); + + while (vb) + { + vbases = tree_cons (NULL_TREE, build_t_desc (BINFO_TYPE (vb), 0), vbases); + offsets = tree_cons (NULL_TREE, BINFO_OFFSET (vb), offsets); + vb = TREE_CHAIN (vb); + } + + if (method_vec) + for (meth = TREE_VEC_END (method_vec), + end = &TREE_VEC_ELT (method_vec, 0); meth-- != end; ) + if (*meth) + { + methods = tree_cons (NULL_TREE, build_m_desc (*meth), methods); + method_count++; + } + } + + if (IS_AGGR_TYPE (type)) + { + for (fields = TYPE_FIELDS (type); fields; fields = TREE_CHAIN (fields)) + if (TREE_CODE (fields) == FIELD_DECL + || TREE_CODE (fields) == VAR_DECL) + { + ivars = tree_cons (NULL_TREE, build_i_desc (fields), ivars); + field_count++; + } + ivars = nreverse (ivars); + } + + parents = finish_table (NULL_TREE, build_pointer_type (__t_desc_type_node), parents, 0); + vbases = finish_table (NULL_TREE, build_pointer_type (__t_desc_type_node), vbases, 0); + offsets = finish_table (NULL_TREE, integer_type_node, offsets, 0); + if (methods == NULL_TREE) + methods = null_pointer_node; + else + methods = build_unary_op (ADDR_EXPR, + finish_table (NULL_TREE, __m_desc_type_node, methods, 0), + 0); + if (ivars == NULL_TREE) + ivars = null_pointer_node; + else + ivars = build_unary_op (ADDR_EXPR, + finish_table (NULL_TREE, __i_desc_type_node, ivars, 0), + 0); + if (TREE_TYPE (type)) + target_type = build_t_desc (TREE_TYPE (type), definition); + else + target_type = integer_zero_node; + + name_string = combine_strings (build_string (IDENTIFIER_LENGTH (tname)+1, IDENTIFIER_POINTER (tname))); + + elems = tree_cons (NULL_TREE, build_unary_op (ADDR_EXPR, name_string, 0), + tree_cons (NULL_TREE, + TYPE_SIZE(type)? size_in_bytes(type) : integer_zero_node, + /* really should use bitfield initialization here. */ + tree_cons (NULL_TREE, integer_zero_node, + tree_cons (NULL_TREE, target_type, + tree_cons (NULL_TREE, build_int_2 (field_count, 2), + tree_cons (NULL_TREE, build_int_2 (method_count, 2), + tree_cons (NULL_TREE, ivars, + tree_cons (NULL_TREE, methods, + tree_cons (NULL_TREE, build_unary_op (ADDR_EXPR, parents, 0), + tree_cons (NULL_TREE, build_unary_op (ADDR_EXPR, vbases, 0), + build_tree_list (NULL_TREE, build_unary_op (ADDR_EXPR, offsets, 0)))))))))))); + return build_generic_desc (tdecl, elems); +} + +/* Build an initializer for a __i_desc node. */ +tree +build_i_desc (decl) + tree decl; +{ + tree elems, name_string; + tree taggr; + + name_string = DECL_NAME (decl); + name_string = combine_strings (build_string (IDENTIFIER_LENGTH (name_string)+1, IDENTIFIER_POINTER (name_string))); + + /* Now decide whether this ivar should cause it's type to get + def'd or ref'd in this file. If the type we are looking at + has a proxy definition, we look at the proxy (i.e., a + `foo *' is equivalent to a `foo'). */ + taggr = TREE_TYPE (decl); + + if ((TREE_CODE (taggr) == POINTER_TYPE + || TREE_CODE (taggr) == REFERENCE_TYPE) + && TYPE_VOLATILE (taggr) == 0) + taggr = TREE_TYPE (taggr); + + elems = tree_cons (NULL_TREE, build_unary_op (ADDR_EXPR, name_string, 0), + tree_cons (NULL_TREE, DECL_FIELD_BITPOS (decl), + build_tree_list (NULL_TREE, build_t_desc (TREE_TYPE (decl), + ! IS_AGGR_TYPE (taggr))))); + taggr = build (CONSTRUCTOR, __i_desc_type_node, NULL_TREE, elems); + TREE_CONSTANT (taggr) = 1; + TREE_STATIC (taggr) = 1; + TREE_READONLY (taggr) = 1; + return taggr; +} + +/* Build an initializer for a __m_desc node. */ +tree +build_m_desc (decl) + tree decl; +{ + tree taggr, elems, name_string; + tree parm_count, req_count, vindex, vcontext; + tree parms; + int p_count, r_count; + tree parm_types = NULL_TREE; + + for (parms = TYPE_ARG_TYPES (TREE_TYPE (decl)), p_count = 0, r_count = 0; + parms != NULL_TREE; parms = TREE_CHAIN (parms), p_count++) + { + taggr = TREE_VALUE (parms); + if ((TREE_CODE (taggr) == POINTER_TYPE + || TREE_CODE (taggr) == REFERENCE_TYPE) + && TYPE_VOLATILE (taggr) == 0) + taggr = TREE_TYPE (taggr); + + parm_types = tree_cons (NULL_TREE, build_t_desc (TREE_VALUE (parms), + ! IS_AGGR_TYPE (taggr)), + parm_types); + if (TREE_PURPOSE (parms) == NULL_TREE) + r_count++; + } + + parm_types = finish_table (NULL_TREE, build_pointer_type (__t_desc_type_node), + nreverse (parm_types), 0); + parm_count = build_int_2 (p_count, 0); + req_count = build_int_2 (r_count, 0); + + if (DECL_VINDEX (decl)) + vindex = DECL_VINDEX (decl); + else + vindex = integer_zero_node; + if (DECL_CONTEXT (decl) + && TREE_CODE_CLASS (TREE_CODE (DECL_CONTEXT (decl))) == 't') + vcontext = build_t_desc (DECL_CONTEXT (decl), 0); + else + vcontext = integer_zero_node; + name_string = DECL_NAME (decl); + if (name_string == NULL) + name_string = DECL_ASSEMBLER_NAME (decl); + name_string = combine_strings (build_string (IDENTIFIER_LENGTH (name_string)+1, IDENTIFIER_POINTER (name_string))); + + /* Now decide whether the return type of this mvar + should cause it's type to get def'd or ref'd in this file. + If the type we are looking at has a proxy definition, + we look at the proxy (i.e., a `foo *' is equivalent to a `foo'). */ + taggr = TREE_TYPE (TREE_TYPE (decl)); + + if ((TREE_CODE (taggr) == POINTER_TYPE + || TREE_CODE (taggr) == REFERENCE_TYPE) + && TYPE_VOLATILE (taggr) == 0) + taggr = TREE_TYPE (taggr); + + elems = tree_cons (NULL_TREE, build_unary_op (ADDR_EXPR, name_string, 0), + tree_cons (NULL_TREE, vindex, + tree_cons (NULL_TREE, vcontext, + tree_cons (NULL_TREE, build_t_desc (TREE_TYPE (TREE_TYPE (decl)), + ! IS_AGGR_TYPE (taggr)), + tree_cons (NULL_TREE, build_c_cast (build_pointer_type (default_function_type), build_unary_op (ADDR_EXPR, decl, 0), 0), + tree_cons (NULL_TREE, parm_count, + tree_cons (NULL_TREE, req_count, + build_tree_list (NULL_TREE, build_unary_op (ADDR_EXPR, parm_types, 0))))))))); + + taggr = build (CONSTRUCTOR, __m_desc_type_node, NULL_TREE, elems); + TREE_CONSTANT (taggr) = 1; + TREE_STATIC (taggr) = 1; + TREE_READONLY (taggr) = 1; + return taggr; +} +#endif /* dossier */ + + +/* Conditionally emit code to set up an unwind-protect for the + garbage collector. If this function doesn't do anything that involves + the garbage collector, then do nothing. Otherwise, call __gc_push + at the beginning and __gc_pop at the end. + + NOTE! The __gc_pop function must operate transparently, since + it comes where the logical return label lies. This means that + at runtime *it* must preserve any return value registers. */ + +void +expand_gc_prologue_and_epilogue () +{ + extern tree maybe_gc_cleanup; + struct rtx_def *last_parm_insn, *mark; + extern struct rtx_def *get_last_insn (); + extern struct rtx_def *get_first_nonparm_insn (); + extern struct rtx_def *previous_insn (); + tree action; + + /* If we didn't need the obstack, don't cons any space. */ + if (current_function_obstack_index == 0 + || current_function_obstack_usage == 0) + return; + + mark = get_last_insn (); + last_parm_insn = get_first_nonparm_insn (); + if (last_parm_insn == 0) last_parm_insn = mark; + else last_parm_insn = previous_insn (last_parm_insn); + + action = build_function_call (gc_push_fndecl, + build_tree_list (NULL_TREE, size_int (++current_function_obstack_index))); + expand_expr_stmt (action); + + reorder_insns (next_insn (mark), get_last_insn (), last_parm_insn); + + /* This will be expanded as a cleanup. */ + TREE_VALUE (maybe_gc_cleanup) + = build_function_call (gc_pop_fndecl, NULL_TREE); +} + +/* Some day we'll use this function as a call-back and clean + up all the unnecessary gc dribble that we otherwise create. */ +void +lang_expand_end_bindings (first, last) + struct rtx_def *first, *last; +{ +} + +void +init_gc_processing () +{ + tree parmtypes = hash_tree_chain (class_star_type_node, + hash_tree_chain (integer_type_node, NULL_TREE)); + gc_protect_fndecl = define_function ("__gc_protect", + build_function_type (class_star_type_node, parmtypes), + NOT_BUILT_IN, 0, 0); + + parmtypes = hash_tree_chain (integer_type_node, NULL_TREE); + gc_unprotect_fndecl = define_function ("__gc_unprotect", + build_function_type (void_type_node, parmtypes), + NOT_BUILT_IN, 0, 0); + + gc_push_fndecl = define_function ("__gc_push", + TREE_TYPE (gc_unprotect_fndecl), + NOT_BUILT_IN, 0, 0); + + gc_pop_fndecl = define_function ("__gc_pop", + build_function_type (void_type_node, + void_list_node), + NOT_BUILT_IN, 0, 0); + gc_nonobject = build_int_2 (0x80000000, 0); + gc_visible = build_int_2 (0x40000000, 0); + gc_white = integer_zero_node; + gc_offwhite = build_int_2 (0x10000000, 0); + gc_grey = build_int_2 (0x20000000, 0); + gc_black = build_int_2 (0x30000000, 0); +} diff --git a/contrib/gcc/cp/gpcompare.texi b/contrib/gcc/cp/gpcompare.texi new file mode 100644 index 000000000000..7b0d573105b6 --- /dev/null +++ b/contrib/gcc/cp/gpcompare.texi @@ -0,0 +1,236 @@ +@node ANSI +@chapter @sc{gnu} C++ Conformance to @sc{ansi} C++ + +These changes in the @sc{gnu} C++ compiler were made to comply more +closely with the @sc{ansi} base document, @cite{The Annotated C++ +Reference Manual} (the @sc{arm}). Further reducing the divergences from +@sc{ansi} C++ is a continued goal of the @sc{gnu} C++ Renovation +Project. + +@b{Section 3.4}, @i{Start and Termination}. It is now invalid to take +the address of the function @samp{main()}. + +@b{Section 4.8}, @i{Pointers to Members}. The compiler produces +an error for trying to convert between a pointer to a member and the type +@samp{void *}. + +@b{Section 5.2.5}, @i{Increment and Decrement}. It is an error to use +the increment and decrement operators on an enumerated type. + +@b{Section 5.3.2}, @i{Sizeof}. Doing @code{sizeof} on a function is now +an error. + +@b{Section 5.3.4}, @i{Delete}. The syntax of a @i{cast-expression} is +now more strictly controlled. + +@b{Section 7.1.1}, @i{Storage Class Specifiers}. Using the +@code{static} and @code{extern} specifiers can now only be applied to +names of objects, functions, and anonymous unions. + +@b{Section 7.1.1}, @i{Storage Class Specifiers}. The compiler no longer complains +about taking the address of a variable which has been declared to have @code{register} +storage. + +@b{Section 7.1.2}, @i{Function Specifiers}. The compiler produces an +error when the @code{inline} or @code{virtual} specifiers are +used on anything other than a function. + +@b{Section 8.3}, @i{Function Definitions}. It is now an error to shadow +a parameter name with a local variable; in the past, the compiler only +gave a warning in such a situation. + +@b{Section 8.4.1}, @i{Aggregates}. The rules concerning declaration of +an aggregate are now all checked in the @sc{gnu} C++ compiler; they +include having no private or protected members and no base classes. + +@b{Section 8.4.3}, @i{References}. Declaring an array of references is +now forbidden. Initializing a reference with an initializer list is +also considered an error. + +@b{Section 9.5}, @i{Unions}. Global anonymous unions must be declared +@code{static}. + +@b{Section 11.4}, @i{Friends}. Declaring a member to be a friend of a +type that has not yet been defined is an error. + +@b{Section 12.1}, @i{Constructors}. The compiler generates a +default copy constructor for a class if no constructor has been declared. + +@ignore +@b{Section 12.4}, @i{Destructors}. In accordance with the @sc{ansi} C++ +draft standard working paper, a pure virtual destructor must now be +defined. +@end ignore + +@b{Section 12.6.2}, @i{Special Member Functions}. When using a +@i{mem-initializer} list, the compiler will now initialize class members +in declaration order, not in the order in which you specify them. +Also, the compiler enforces the rule that non-static @code{const} +and reference members must be initialized with a @i{mem-initializer} +list when their class does not have a constructor. + +@b{Section 12.8}, @i{Copying Class Objects}. The compiler generates +default copy constructors correctly, and supplies default assignment +operators compatible with user-defined ones. + +@b{Section 13.4}, @i{Overloaded Operators}. An overloaded operator may +no longer have default arguments. + +@b{Section 13.4.4}, @i{Function Call}. An overloaded @samp{operator ()} +must be a non-static member function. + +@b{Section 13.4.5}, @i{Subscripting}. An overloaded @samp{operator []} +must be a non-static member function. + +@b{Section 13.4.6}, @i{Class Member Access}. An overloaded @samp{operator ->} +must be a non-static member function. + +@b{Section 13.4.7}, @i{Increment and Decrement}. The compiler will now +make sure a postfix @samp{@w{operator ++}} or @samp{@w{operator --}} has an +@code{int} as its second argument. + + +@node Encoding +@chapter Name Encoding in @sc{gnu} C++ + +@c FIXME!! rewrite name encoding section +@c ...to give complete rules rather than diffs from ARM. +@c To avoid plagiarism, invent some different way of structuring the +@c description of the rules than what ARM uses. + +@cindex mangling +@cindex name encoding +@cindex encoding information in names +In order to support its strong typing rules and the ability to provide +function overloading, the C++ programming language @dfn{encodes} +information about functions and objects, so that conflicts across object +files can be detected during linking. @footnote{This encoding is also +sometimes called, whimsically enough, @dfn{mangling}; the corresponding +decoding is sometimes called @dfn{demangling}.} These rules tend to be +unique to each individual implementation of C++. + +The scheme detailed in the commentary for 7.2.1 of @cite{The Annotated +Reference Manual} offers a description of a possible implementation +which happens to closely resemble the @code{cfront} compiler. The +design used in @sc{gnu} C++ differs from this model in a number of ways: + +@itemize @bullet +@item +In addition to the basic types @code{void}, @code{char}, @code{short}, +@code{int}, @code{long}, @code{float}, @code{double}, and @code{long +double}, @sc{gnu} C++ supports two additional types: @code{wchar_t}, the wide +character type, and @code{long long} (if the host supports it). The +encodings for these are @samp{w} and @samp{x} respectively. + +@item +According to the @sc{arm}, qualified names (e.g., @samp{foo::bar::baz}) are +encoded with a leading @samp{Q}. Followed by the number of +qualifications (in this case, three) and the respective names, this +might be encoded as @samp{Q33foo3bar3baz}. @sc{gnu} C++ adds a leading +underscore to the list, producing @samp{_Q33foo3bar3baz}. + +@item +The operator @samp{*=} is encoded as @samp{__aml}, not @samp{__amu}, to +match the normal @samp{*} operator, which is encoded as @samp{__ml}. + +@c XXX left out ->(), __wr +@item +In addition to the normal operators, @sc{gnu} C++ also offers the minimum and +maximum operators @samp{>?} and @samp{<?}, encoded as @samp{__mx} and +@samp{__mn}, and the conditional operator @samp{?:}, encoded as @samp{__cn}. + +@cindex destructors, encoding of +@cindex constructors, encoding of +@item +Constructors are encoded as simply @samp{__@var{name}}, where @var{name} +is the encoded name (e.g., @code{3foo} for the @code{foo} class +constructor). Destructors are encoded as two leading underscores +separated by either a period or a dollar sign, depending on the +capabilities of the local host, followed by the encoded name. For +example, the destructor @samp{foo::~foo} is encoded as @samp{_$_3foo}. + +@item +Virtual tables are encoded with a prefix of @samp{_vt}, rather than +@samp{__vtbl}. The names of their classes are separated by dollar signs +(or periods), and not encoded as normal: the virtual table for +@code{foo} is @samp{__vt$foo}, and the table for @code{foo::bar} is +named @samp{__vt$foo$bar}. + +@item +Static members are encoded as a leading underscore, followed by the +encoded name of the class in which they appear, a separating dollar sign +or period, and finally the unencoded name of the variable. For example, +if the class @code{foo} contains a static member @samp{bar}, its +encoding would be @samp{_3foo$bar}. + +@item +@sc{gnu} C++ is not as aggressive as other compilers when it comes to always +generating @samp{Fv} for functions with no arguments. In particular, +the compiler does not add the sequence to conversion operators. The +function @samp{foo::bar()} is encoded as @samp{bar__3foo}, not +@samp{bar__3fooFv}. + +@item +The argument list for methods is not prefixed by a leading @samp{F}; it +is considered implied. + +@item +@sc{gnu} C++ approaches the task of saving space in encodings +differently from that noted in the @sc{arm}. It does use the +@samp{T@var{n}} and @samp{N@var{x}@var{y}} codes to signify copying the +@var{n}th argument's type, and making the next @var{x} arguments be the +type of the @var{y}th argument, respectively. However, the values for +@var{n} and @var{y} begin at zero with @sc{gnu} C++, whereas the +@sc{arm} describes them as starting at one. For the function @samp{foo +(bartype, bartype)}, @sc{gnu} C++ uses @samp{foo__7bartypeT0}, while +compilers following the @sc{arm} example generate @samp{foo__7bartypeT1}. + +@c Note it loses on `foo (int, int, int, int, int)'. +@item +@sc{gnu} C++ does not bother using the space-saving methods for types whose +encoding is a single character (like an integer, encoded as @samp{i}). +This is useful in the most common cases (two @code{int}s would result in +using three letters, instead of just @samp{ii}). +@end itemize + +@c @node Cfront +@c @chapter @code{cfront} Compared to @sc{gnu} C++ +@c +@c +@c FIXME!! Fill in. Consider points in the following: +@c +@c @display +@c Date: Thu, 2 Jan 92 21:35:20 EST +@c From: raeburn@@cygnus.com +@c Message-Id: <9201030235.AA10999@@cambridge.cygnus.com> +@c To: mrs@@charlie.secs.csun.edu +@c Cc: g++@@cygnus.com +@c Subject: Re: ARM and GNU C++ incompatabilities +@c +@c Along with that, we should probably describe how g++ differs from +@c cfront, in ways that the users will notice. (E.g., cfront supposedly +@c allows "free (new char[10])"; does g++? How do the template +@c implementations differ? "New" placement syntax?) +@c @end display +@c +@c XXX For next revision. +@c +@c GNU C++: +@c * supports expanding inline functions in many situations, +@c including those which have static objects, use `for' statements, +@c and other situations. Part of this versatility is due to is +@c ability to not always generate temporaries for assignments. +@c * deliberately allows divide by 0 and mod 0, since [according +@c to Wilson] there are actually situations where you'd like to allow +@c such things. Note on most systems it will cause some sort of trap +@c or bus error. Cfront considers it an error. +@c * does [appear to] support nested classes within templates. +@c * conversion functions among baseclasses are all usable by +@c a class that's derived from all of those bases. +@c * sizeof works even when the class is defined within its ()'s +@c * conditional expressions work with member fns and pointers to +@c members. +@c * can handle non-trivial declarations of variables within switch +@c statements. +@c +@c Cfront: diff --git a/contrib/gcc/cp/gxxint.texi b/contrib/gcc/cp/gxxint.texi index 5a665c72f942..95a99e1a6714 100644 --- a/contrib/gcc/cp/gxxint.texi +++ b/contrib/gcc/cp/gxxint.texi @@ -1,5 +1,5 @@ \input texinfo @c -*-texinfo-*- -@c %** $FreeBSD$ +@c %** $FreeBSD: src/contrib/gcc/cp/gxxint.texi,v 1.4.2.1 2000/07/04 06:01:43 obrien Exp $ @c %**start of header @setfilename g++int.info @settitle G++ internals diff --git a/contrib/gcc/cp/ptree.c b/contrib/gcc/cp/ptree.c index 3920c3071505..595edd269033 100644 --- a/contrib/gcc/cp/ptree.c +++ b/contrib/gcc/cp/ptree.c @@ -19,7 +19,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/cp/ptree.c,v 1.4 1999/10/16 07:57:37 obrien Exp $ */ #include "config.h" diff --git a/contrib/gcc/cp/reno.texi b/contrib/gcc/cp/reno.texi new file mode 100644 index 000000000000..d5f254a6929b --- /dev/null +++ b/contrib/gcc/cp/reno.texi @@ -0,0 +1,752 @@ +\input texinfo @c -*- Texinfo -*- +@setfilename reno-1.info + +@ifinfo +@format +START-INFO-DIR-ENTRY +* Reno 1: (reno). The GNU C++ Renovation Project, Phase 1. +END-INFO-DIR-ENTRY +@end format +@end ifinfo + +@ifinfo +Copyright @copyright{} 1992, 1993, 1994 Free Software Foundation, Inc. + +Permission is granted to make and distribute verbatim copies of +this manual provided the copyright notice and this permission notice +are preserved on all copies. + +@ignore +Permission is granted to process this file through TeX and print the +results, provided the printed document carries a copying permission +notice identical to this one except for the removal of this paragraph +(this paragraph not being relevant to the printed manual). + +@end ignore + +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided also that +the entire resulting derived work is distributed under the terms of a +permission notice identical to this one. + +Permission is granted to copy and distribute translations of this manual +into another language, under the above conditions for modified versions. +@end ifinfo + +@setchapternewpage odd +@settitle GNU C++ Renovation Project +@c @smallbook + +@titlepage +@finalout +@title GNU C++ Renovation Project +@subtitle Phase 1.3 +@author Brendan Kehoe, Jason Merrill, +@author Mike Stump, Michael Tiemann +@page + +Edited March, 1994 by Roland Pesch (@code{pesch@@cygnus.com}) +@vskip 0pt plus 1filll +Copyright @copyright{} 1992, 1993, 1994 Free Software Foundation, Inc. + +Permission is granted to make and distribute verbatim copies of +this manual provided the copyright notice and this permission notice +are preserved on all copies. + +@ignore +Permission is granted to process this file through Tex and print the +results, provided the printed document carries copying permission +notice identical to this one except for the removal of this paragraph +(this paragraph not being relevant to the printed manual). +@end ignore + +Permission is granted to copy and distribute modified versions of this +manual under the conditions for verbatim copying, provided also that +the entire resulting derived work is distributed under the terms of a +permission notice identical to this one. + +Permission is granted to copy and distribute translations of this manual +into another language, under the above conditions for modified versions. +@end titlepage + +@ifinfo +@node Top +@top @sc{gnu} C++ Renovation Project + +This file describes the goals of the @sc{gnu} C++ Renovation Project, +and its accomplishments to date (as of Phase 1.3). + +It also discusses the remaining divergences from @sc{gnu} C++, and how the +name encoding in @sc{gnu} C++ differs from the sample encoding in +@cite{The Annotated C++ Reference Manual}. +@c This is not a good place to introduce the acronym ARM because it's +@c info-only. + +@menu +* Introduction:: What is the GNU C++ Renovation Project? +* Changes:: Summary of changes since previous GNU C++ releases. +* Plans:: Plans for Reno-2. +* Templates:: The template implementation. +* ANSI:: GNU C++ conformance to ANSI C++. +* Encoding:: Name encoding in GNU C++. +@end menu + +@end ifinfo + +@node Introduction +@chapter Introduction + +As you may remember, @sc{gnu} C++ was the first native-code C++ +compiler available under Unix (December 1987). In November 1988, it was +judged superior to the AT&T compiler in a Unix World review. In 1990 it +won a Sun Observer ``Best-Of'' award. But now, with new requirements +coming out of the @sc{ansi} C++ committee and a growing backlog of bugs, it's +clear that @sc{gnu} C++ needs an overhaul. + +The C++ language has been under development since 1982. It has +evolved significantly since its original incarnation (C with Classes), +addressing many commercial needs and incorporating many lessons +learned as more and more people started using ``object-oriented'' +programming techniques. In 1989, the first X3J16 committee meeting +was held in Washington DC; in the interest of users, C++ was going to +be standardized. + +As C++ has become more popular, more demands have been placed on its +compilers. Some compilers are up to the demands, others are not. +@sc{gnu} C++ was used to prototype several features which have since +been incorporated into the standard, most notably exception handling. +While @sc{gnu} C++ has been an excellent experimental vehicle, it did +not have the resources that AT&T, Borland, or Microsoft have at their +disposal. + +We believe that @sc{gnu} C++ is an important compiler, providing users with +many of the features that have made @sc{gnu} C so popular: fast compilation, +good error messages, innovative features, and full sources that may be +freely redistributed. The purpose of this overhaul, dubbed the @var{@sc{gnu} +C++ Renovation Project}, is to take advantage of the functionality that +@sc{gnu} C++ offers today, to strengthen its base technology, and put it in a +position to remain---as other @sc{gnu} software currently is---the technical +leader in the field. + +This release represents the latest phase of work in strengthening the +compiler on a variety of points. It includes many months of +work concentrated on fixing many of the more egregious bugs that +presented themselves in the compiler recently. +@ignore +@c FIXME-- update? +Nearly 85% of all bugs reported in the period of February to September +of 1992 were fixed as part of the work in the first phase. +@end ignore +In the coming months, we hope to continue expanding and enhancing the +quality and dependability of the industry's only freely redistributable +C++ compiler. + +@node Changes +@chapter Changes in Behavior in @sc{gnu} C++ + +The @sc{gnu} C++ compiler continues to improve and change. A major goal +of our work has been to continue to bring the compiler into compliance +with the draft @sc{ansi} C++ standard, and with @cite{The Annotated C++ +Reference Manual} (the @sc{arm}). This section outlines most of the +user-noticeable changes that might be encountered during the normal +course of use. + +@menu +* Summary of Phase 1.3:: +* Major changes:: +* New features:: +* Enhancements and bug fixes:: +* Problems with debugging:: +@end menu + +@node Summary of Phase 1.3 +@section Summary of Changes in Phase 1.3 + +The bulk of this note discusses the cumulative effects of the @sc{gnu} C++ +Renovation Project to date. The work during its most recent phase (1.3) +had these major effects: + +@itemize @bullet +@item The standard compiler driver @code{g++} is now the faster compiled +version, rather than a shell script. + +@item Nested types work much better; notably, nesting is no longer +restricted to nine levels. + +@item Better @sc{arm} conformance on member access control. + +@item The compiler now always generates default assignment operators +(@samp{operator =}), copy constructors (@samp{X::X(X&)}), and default +constructors (@samp{X::X()}) whenever they are required. + +@item The new draft @sc{ansi} standard keyword @code{mutable} is supported. + +@item @samp{-fansi-overloading} is the default, to comply better with +the @sc{arm} (at some cost in compatibility to earlier versions of @sc{gnu} C++). + +@item More informative error messages. + +@item System include files are automatically treated as if they were +wrapped in @samp{extern "C" @{ @}}. + +@item The new option @samp{-falt-external-templates} provides alternate +template instantiation semantics. + +@item Operator declarations are now checked more strictly. + +@item You can now use template type arguments in the template parameter list. + +@item You can call the destructor for any type. + +@item The compiler source code is better organized. + +@item You can specify where to instantiate template definitions explicitly. +@end itemize + +Much of the work in Phase 1.3 went to elimination of known bugs, as well +as the major items above. + +During the span of Phase 1.3, there were also two changes associated +with the compiler that, while not specifically part of the C++ +Renovation project, may be of interest: + +@itemize @bullet +@item @code{gcov}, a code coverage tool for @sc{gnu cc}, is now available +from Cygnus Support. (@code{gcov} is free software, but the @sc{fsf} has not +yet accepted it.) @xref{Gcov,, @code{gcov}: a Test Coverage Program, +gcc.info, Using GNU CC}, for more information (in Cygnus releases of +that manual). + +@item @sc{gnu} C++ now supports @dfn{signatures}, a language extension to +provide more flexibility in abstract type definitions. @xref{C++ +Signatures,, Type Abstraction using Signatures, gcc.info, Using GNU CC}. +@end itemize + +@node Major changes +@section Major Changes + +This release includes four wholesale rewrites of certain areas of +compiler functionality: + +@enumerate 1 +@item Argument matching. @sc{gnu} C++ is more compliant with the rules +described in Chapter 13, ``Overloading'', of the @sc{arm}. This behavior is +the default, though you can specify it explicitly with +@samp{-fansi-overloading}. For compatibility with earlier releases of +@sc{gnu} C++, specify @samp{-fno-ansi-overloading}; this makes the compiler +behave as it used to with respect to argument matching and name overloading. + +@item Default constructors/destructors. Section 12.8 of the @sc{arm}, ``Copying +Class Objects'', and Section 12.1, ``Constructors'', state that a +compiler must declare such default functions if the user does not +specify them. @sc{gnu} C++ now declares, and generates when necessary, +the defaults for constructors and destructors you might omit. In +particular, assignment operators (@samp{operator =}) behave the same way +whether you define them, or whether the compiler generates them by +default; taking the address of the default @samp{operator =} is now +guaranteed to work. Default copy constructors (@samp{X::X(X&)}) now +function correctly, rather than calling the copy assignment operator for +the base class. Finally, constructors (@samp{X::X()}), as well as +assignment operators and copy constructors, are now available whenever +they are required. + +@c XXX This may be taken out eventually... +@item Binary incompatibility. There are no new binary incompatibilities +in Phase 1.3, but Phase 1.2 introduced two binary incompatibilities with +earlier releases. First, the functionality of @samp{operator +new} and @samp{operator delete} changed. Name encoding +(``mangling'') of virtual table names changed as well. Libraries +built with versions of the compiler earlier than Phase 1.2 must be +compiled with the new compiler. (This includes the Cygnus Q2 +progressive release and the FSF 2.4.5 release.) + +@item New @code{g++} driver. +A new binary @code{g++} compiler driver replaces the shell script. +The new driver executes faster. +@end enumerate + +@node New features +@section New features + +@itemize @bullet +@item +The compiler warns when a class contains only private constructors +or destructors, and has no friends. At the request of some of our +customers, we have added a new option, @samp{-Wctor-dtor-privacy} (on by +default), and its negation, @samp{-Wno-ctor-dtor-privacy}, to control +the emission of this warning. If, for example, you are working towards +making your code compile warning-free, you can use @w{@samp{-Wall +-Wno-ctor-dtor-privacy}} to find the most common warnings. + +@item +There is now a mechanism which controls exactly when templates are +expanded, so that you can reduce memory usage and program size and also +instantiate them exactly once. You can control this mechanism with the +option @samp{-fexternal-templates} and its corresponding negation +@samp{-fno-external-templates}. Without this feature, space consumed by +template instantiations can grow unacceptably in large-scale projects +with many different source files. The default is +@samp{-fno-external-templates}. + +You do not need to use the @samp{-fexternal-templates} option when +compiling a file that does not define and instantiate templates used in +other files, even if those files @emph{are} compiled with +@samp{-fexternal-templates}. The only side effect is an increase in +object size for each file that was compiled without +@samp{-fexternal-templates}. + +When your code is compiled with @samp{-fexternal-templates}, all +template instantiations are external; this requires that the templates +be under the control of @samp{#pragma interface} and @samp{#pragma +implementation}. All instantiations that will be needed should be in +the implementation file; you can do this with a @code{typedef} that +references the instantiation needed. Conversely, when you compile using +the option @samp{-fno-external-templates}, all template instantiations are +explicitly internal. + +@samp{-fexternal-templates} also allows you to finally separate class +template function definitions from their declarations, thus speeding up +compilation times for every file that includes the template declaration. +Now you can have tens or even hundreds of lines in template +declarations, and thousands or tens of thousands of lines in template +definitions, with the definitions only going through the compiler once +instead of once for each source file. It is important to note that you +must remember to externally instantiate @emph{all} templates that are +used from template declarations in interface files. If you forget to do +this, unresolved externals will occur. + +In the example below, the object file generated (@file{example.o}) will +contain the global instantiation for @samp{Stack<int>}. If other types +of @samp{Stack} are needed, they can be added to @file{example.cc} or +placed in a new file, in the same spirit as @file{example.cc}. + +@code{foo.h}: +@smallexample +@group +#pragma interface "foo.h" +template<class T> +class Stack @{ + static int statc; + static T statc2; + Stack() @{ @} + virtual ~Stack() @{ @} + int bar(); +@}; +@end group +@end smallexample + +@code{example.cc}: +@smallexample +@group +#pragma implementation "foo.h" +#include "foo.h" + +typedef Stack<int> t; +int Stack<int>::statc; +int Stack<int>::statc2; +int Stack<int>::bar() @{ @} +@end group +@end smallexample + +Note that using @samp{-fexternal-templates} does not reduce memory usage +from completely different instantiations (@samp{Stack<Name>} vs. +@samp{Stack<Net_Connection>}), but only collapses different occurrences +of @samp{Stack<Name>} so that only one @samp{Stack<Name>} is generated. + +@samp{-falt-external-templates} selects a slight variation in the +semantics described above (incidentally, you need not specify both +options; @samp{-falt-external-templates} implies +@samp{-fexternal-templates}). + +With @samp{-fexternal-templates}, the compiler emits a definition in the +implementation file that includes the header definition, @emph{even if} +instantiation is triggered from a @emph{different} implementation file +(e.g. with a template that uses another template). + +With @samp{-falt-external-templates}, the definition always goes in the +implementation file that triggers instantiation. + +For instance, with these two header files--- + +@example +@exdent @file{a.h}: +#pragma interface +template <class T> class A @{ @dots{} @}; + +@exdent @file{b.h}: +#pragma interface +class B @{ @dots{} @}; +void f (A<B>); +@end example + +Under @samp{-fexternal-templates}, the definition of @samp{A<B>} ends up +in the implementation file that includes @file{a.h}. Under +@samp{-falt-external-templates}, the same definition ends up in the +implementation file that includes @file{b.h}. + +@item +You can control explicitly where a template is instantiated, without +having to @emph{use} the template to get an instantiation. + +To instantiate a class template explicitly, write @samp{template +class @var{name}<paramvals>}, where @var{paramvals} is a list of values +for the template parameters. For example, you might write + +@example +template class A<int> +@end example + +Similarly, to instantiate a function template explicitly, write +@samp{template @var{fnsign}} where @var{fnsign} is the particular +function signature you need. For example, you might write + +@example +template void foo (int, int) +@end example + +This syntax for explicit template instantiation agrees with recent +extensions to the draft @sc{ansi} standard. + +@item +The compiler's actions on @sc{ansi}-related warnings and errors have +been further enhanced. The @samp{-pedantic-errors} option produces +error messages in a number of new situations: using @code{return} in a +non-@code{void} function (one returning a value); declaring a local +variable that shadows a parameter (e.g., the function takes an argument +@samp{a}, and has a local variable @samp{a}); and use of the @samp{asm} +keyword. Finally, the compiler by default now issues a warning when +converting from an @code{int} to an enumerated type. This is likely to +cause many new warnings in code that hadn't triggered them before. For +example, when you compile this code, + +@smallexample +@group +enum boolean @{ false, true @}; +void +f () +@{ + boolean x; + + x = 1; //@i{assigning an @code{int} to an @code{enum} now triggers a warning} +@} +@end group +@end smallexample + +@noindent +you should see the warning ``@code{anachronistic conversion from integer +type to enumeral type `boolean'}''. Instead of assigning the value 1, +assign the original enumerated value @samp{true}. +@end itemize + +@node Enhancements and bug fixes +@section Enhancements and bug fixes + +@itemize @bullet +@cindex nested types in template parameters +@item +You can now use nested types in a template parameter list, even if the nested +type is defined within the same class that attempts to use the template. +For example, given a template @code{list}, the following now works: + +@smallexample +struct glyph @{ + @dots{} + struct stroke @{ @dots{} @}; + list<stroke> l; + @dots{} +@} +@end smallexample + +@cindex function pointers vs template parameters +@item +Function pointers now work in template parameter lists. For +example, you might want to instantiate a parameterized @code{list} class +in terms of a pointer to a function like this: + +@smallexample +list<int (*)(int, void *)> fnlist; +@end smallexample + +@item +@c FIXME! Really no limit? Jason said "deeper than 9" now OK... +Nested types are now handled correctly. In particular, there is no +longer a limit to how deeply you can nest type definitions. + +@item +@sc{gnu} C++ now conforms to the specifications in Chapter 11 of the +@sc{arm}, ``Member Access Control''. + +@item +The @sc{ansi} C++ committee has introduced a new keyword @code{mutable}. +@sc{gnu} C++ supports it. Use @code{mutable} to specify that some +particular members of a @code{const} class are @emph{not} constant. For +example, you can use this to include a cache in a data structure that +otherwise represents a read-only database. + +@item +Error messages now explicitly specify the declaration, type, or +expression that contains an error. + +@item +To avoid copying and editing all system include files during @sc{gnu} +C++ installation, the compiler now automatically recognizes system +include files as C language definitions, as if they were wrapped in +@samp{extern "C" @{ @dots{} @}}. + +@item +The compiler checks operator declarations more strictly. For example, +you may no longer declare an @samp{operator +} with three arguments. + +@item +You can now use template type arguments in the same template +parameter list where the type argument is specified (as well as in the +template body). For example, you may write + +@example +template <class T, T t> class A @{ @dots{} @}; +@end example + +@item +Destructors are now available for all types, even built-in ones; for +example, you can call @samp{int::~int}. (Destructors for types like +@code{int} do not actually do anything, but their existence provides a +level of generality that permits smooth template expansion in more +cases.) + +@item +Enumerated types declared inside a class are now handled correctly. + +@item +An argument list for a function may not use an initializer list for its default +value. For example, @w{@samp{void foo ( T x = @{ 1, 2 @} )}} is not permitted. + +@item +A significant amount of work went into improving the ability of the +compiler to act accurately on multiple inheritance and virtual +functions. Virtual function dispatch has been enhanced as well. + +@item +The warning concerning a virtual inheritance environment with a +non-virtual destructor has been disabled, since it is not clear that +such a warning is warranted. + +@item +Until exception handling is fully implemented in the Reno-2 release, use +of the identifiers @samp{catch}, @samp{throw}, or @samp{try} results +in the warning: + +@smallexample +t.C:1: warning: `catch', `throw', and `try' + are all C++ reserved words +@end smallexample + +@item +When giving a warning or error concerning initialization of a member in a +class, the compiler gives the name of the member if it has one. + +@item +Detecting friendship between classes is more accurately checked. + +@item +The syntaxes of @w{@samp{#pragma implementation "file.h"}} and +@samp{#pragma interface} are now more strictly controlled. The compiler +notices (and warns) when any text follows @file{file.h} in the +implementation pragma, or follows the word @samp{interface}. Any such +text is otherwise ignored. + +@item +Trying to declare a template on a variable or type is now considered an +error, not an unimplemented feature. + +@item +When an error occurs involving a template, the compiler attempts to +tell you at which point of instantiation the error occurred, in +addition to noting the line in the template declaration which had the +actual error. + +@item +The symbol names for function templates in the resulting assembly file +are now encoded according to the arguments, rather than just being +emitted as, for example, two definitions of a function @samp{foo}. + +@item +Template member functions that are declared @code{static} no longer +receive a @code{this} pointer. + +@item +Case labels are no longer allowed to have commas to make up their +expressions. + +@item +Warnings concerning the shift count of a left or right shift now tell +you if it was a @samp{left} or @samp{right} shift. + +@item +The compiler now warns when a decimal constant is so large that it +becomes @code{unsigned}. + +@item +Union initializers which are raw constructors are now handled properly. + +@item +The compiler no longer gives incorrect errors when initializing a +union with an empty initializer list. + +@item +Anonymous unions are now correctly used when nested inside a class. + +@item +Anonymous unions declared as static class members are now handled +properly. + +@item +The compiler now notices when a field in a class is declared both as +a type and a non-type. + +@item +The compiler now warns when a user-defined function shadows a +built-in function, rather than emitting an error. + +@item +A conflict between two function declarations now produces an error +regardless of their language context. + +@item +Duplicate definitions of variables with @samp{extern "C"} linkage are no +longer considered in error. (Note in C++ linkage---the default---you may +not have more than one definition of a variable.) + +@item +Referencing a label that is not defined in any function is now an error. + +@item +The syntax for pointers to methods has been improved; there are still +some minor bugs, but a number of cases should now be accepted by the +compiler. + +@item +In error messages, arguments are now numbered starting at 1, instead of +0. Therefore, in the function @samp{void foo (int a, int b)}, the +argument @samp{a} is argument 1, and @samp{b} is argument 2. There is +no longer an argument 0. + +@item +The tag for an enumerator, rather than its value, used as a default +argument is now shown in all error messages. For example, @w{@samp{void +foo (enum x (= true))}} is shown instead of @w{@samp{void foo (enum x (= +1))}}. + +@item +The @samp{__asm__} keyword is now accepted by the C++ front-end. + +@item +Expressions of the form @samp{foo->~Class()} are now handled properly. + +@item +The compiler now gives better warnings for situations which result in +integer overflows (e.g., in storage sizes, enumerators, unary +expressions, etc). + +@item +@code{unsigned} bitfields are now promoted to @code{signed int} if the +field isn't as wide as an @code{int}. + +@item +Declaration and usage of prefix and postfix @samp{operator ++} and +@samp{operator --} are now handled correctly. For example, + +@smallexample +@group +class foo +@{ +public: + operator ++ (); + operator ++ (int); + operator -- (); + operator -- (int); +@}; + +void +f (foo *f) +@{ + f++; // @i{call @code{f->operator++(int)}} + ++f; // @i{call @code{f->operator++()}} + f--; // @i{call @code{f->operator++(int)}} + --f; // @i{call @code{f->operator++()}} +@} +@end group +@end smallexample + +@item +In accordance with @sc{arm} section 10.1.1, ambiguities and dominance are now +handled properly. The rules described in section 10.1.1 are now fully +implemented. + +@end itemize + +@node Problems with debugging +@section Problems with debugging + +Two problems remain with regard to debugging: + +@itemize @bullet +@item +Debugging of anonymous structures on the IBM RS/6000 host is incorrect. + +@item +Symbol table size is overly large due to redundant symbol information; +this can make @code{gdb} coredump under certain circumstances. This +problem is not host-specific. +@end itemize + +@node Plans +@chapter Plans for Reno-2 + +The overall goal for the second phase of the @sc{gnu} C++ Renovation +Project is to bring @sc{gnu} C++ to a new level of reliability, quality, +and competitiveness. As particular elements of this strategy, we intend +to: + +@enumerate 0 +@item +Fully implement @sc{ansi} exception handling. + +@item +With the exception handling, add Runtime Type Identification +(@sc{rtti}), if the @sc{ansi} committee adopts it into the standard. + +@item +Bring the compiler into closer compliance with the @sc{arm} and the draft +@sc{ansi} standard, and document what points in the @sc{arm} we do not yet comply, +or agree, with. + +@item +Add further support for the @sc{dwarf} debugging format. + +@item +Finish the work to make the compiler compliant with @sc{arm} Section 12.6.2, +initializing base classes in declaration order, rather than in the order +that you specify them in a @var{mem-initializer} list. + +@item +Perform a full coverage analysis on the compiler, and weed out unused +code, for a gain in performance and a reduction in the size of the compiler. + +@item +Further improve the multiple inheritance implementation in the +compiler to make it cleaner and more complete. +@end enumerate + +@noindent +As always, we encourage you to make suggestions and ask questions about +@sc{gnu} C++ as a whole, so we can be sure that the end of this project +will bring a compiler that everyone will find essential for C++ and will +meet the needs of the world's C++ community. + +@include templates.texi + +@include gpcompare.texi + +@contents + +@bye diff --git a/contrib/gcc/cp/templates.texi b/contrib/gcc/cp/templates.texi new file mode 100644 index 000000000000..2a6db07f42b2 --- /dev/null +++ b/contrib/gcc/cp/templates.texi @@ -0,0 +1,235 @@ +@node Templates +@chapter The Template Implementation + +@cindex templates +@cindex function templates +@cindex class templates +@cindex parameterized types +@cindex types, parameterized +The C++ template@footnote{Class templates are also known as +@dfn{parameterized types}.} facility, which effectively allows use of +variables for types in declarations, is one of the newest features of +the language. + +@sc{gnu} C++ is one of the first compilers to implement many +of the template facilities currently defined by the @sc{ansi} committee. + +Nevertheless, the template implementation is not yet complete. This +chapter maps the current limitations of the @sc{gnu} C++ template +implementation. + +@menu +* Template limitations:: Limitations for function and class templates +* Function templates:: Limitations for function templates +* Class templates:: Limitations for class templates +* Template debugging:: Debugging information for templates +@end menu + +@node Template limitations +@section Limitations for function and class templates + +@cindex template limitations +@cindex template bugs +@cindex bugs, templates +These limitations apply to any use of templates (function templates or +class templates) with @sc{gnu} C++: + +@table @emph +@item Template definitions must be visible +When you compile code with templates, the template definitions must come +first (before the compiler needs to expand them), and template +definitions you use must be visible in the current scope. +@c FIXME! Is this a defined property of templates, rather than a +@c temporary limitation? +@c ANSWER: It's a limitation, but it's hard to say why it's a limitation +@c to someone. We need an infinite link-cycle, in one camp, to +@c accomplish things so you don't need the template definitions around. + +@cindex static data in template classes +@cindex template classes, static data in +@item Individual initializers needed for static data +Templates for static data in template classes do not work. @xref{Class +templates,,Limitations for class templates}. +@end table + +@node Function templates +@section Limitations for function templates + +@cindex function template limitations +Function templates are implemented for the most part. The compiler can +correctly determine template parameter values, and will delay +instantiation of a function that uses templates until the requisite type +information is available. + +@noindent +The following limitations remain: + +@itemize @bullet +@cindex template vs declaration, functions +@cindex declaration vs template, functions +@cindex function declaration vs template +@item +Narrowed specification: function declarations should not prevent +template expansion. When you declare a function, @sc{gnu} C++ +interprets the declaration as an indication that you will provide a +definition for that function. Therefore, @sc{gnu} C++ does not use a +template expansion if there is also an applicable declaration. @sc{gnu} +C++ only expands the template when there is no such declaration. + +The specification in Bjarne Stroustrup's @cite{The C++ Programming +Language, Second Edition} is narrower, and the @sc{gnu} C++ +implementation is now clearly incorrect. With this new specification, a +declaration that corresponds to an instantiation of a function template +only affects whether conversions are needed to use that version of the +function. It should no longer prevent expansion of the template +definition. + +For example, this code fragment must be treated differently: + +@smallexample +template <class X> X min (X& x1, X& x2) @{ @dots{} @} +int min (int, int); +@dots{} +int i; short s; +min (i, s); // @r{should call} min(int,int) + // @r{derived from template} +@dots{} +@end smallexample + +@item +The compiler does not yet understand function signatures where types are +nested within template parameters. For example, a function like the +following produces a syntax error on the closing @samp{)} of the +definition of the function @code{f}: + +@smallexample +template <class T> class A @{ public: T x; class Y @{@}; @}; +template <class X> int f (A<X>::Y y) @{ @dots{} @} +@end smallexample + +@cindex @code{inline} and function templates +@cindex function templates and @code{inline} +@item +If you declare an @code{inline} function using templates, the compiler +can only inline the code @emph{after} the first time you use +that function with whatever particular type signature the template +was instantiated. + +Removing this limitation is akin to supporting nested function +definitions in @sc{gnu} C++; the limitation will probably remain until the +more general problem of nested functions is solved. + +@item +All the @emph{method} templates (templates for member functions) for a +class must be visible to the compiler when the class template is +instantiated. +@end itemize + +@node Class templates +@section Limitations for class templates + +@cindex class template limitations +@ignore +FIXME!! Include a comprehensible version of this if someone can explain it. + (Queried Brendan and Raeburn w/full orig context, 26may1993---pesch) + - [RHP: I don't understand what the following fragment refers to. If it's + the "BIG BUG" section in the original, why does it say "overriding class + declarations" here when the more detailed text refers to *function* + declarations? Here's the fragment I don't understand:] + there are problems with user-supplied overriding class declarations (see + below). +@end ignore + +@itemize @bullet +@ignore +@cindex static data, not working in templates +@item +Templates for static data in template classes do not work. +Currently, you must initialize each case of such data +individually. +@c FIXME!! Brendan to see if still true. +@c ANSWER: This section presumes that it's incorrect to have to +@c initialize for each type you instantiate with. It's not, it's the +@c right way to do it. +@end ignore + +Unfortunately, individual initializations of this sort are likely to be +considered errors eventually; since they're needed now, you might want to +flag places where you use them with comments to mark the need for a +future transition. + +@cindex nested type results vs templates +@item +Member functions in template classes may not have results of nested +type; @sc{gnu} C++ signals a syntax error on the attempt. The following +example illustrates this problem with an @code{enum} type @code{alph}: + +@smallexample +template <class T> class list @{ + @dots{} + enum alph @{a,b,c@}; + alph bar(); + @dots{} +@}; + +template <class T> +list<int>::alph list<int>::bar() // @i{Syntax error here} +@{ +@dots{} +@} +@end smallexample + +@cindex preprocessor conditionals in templates +@cindex conditionals (preprocessor) in templates +@item +A parsing bug makes it difficult to use preprocessor conditionals within +templates. For example, in this code: + +@smallexample +template <class T> +class list @{ + @dots{} +#ifdef SYSWRONG + T x; +#endif + @dots{} +@} +@end smallexample + +The preprocessor output leaves sourcefile line number information (lines +like @samp{# 6 "foo.cc"} when it expands the @code{#ifdef} block. These +lines confuse the compiler while parsing templates, giving a syntax +error. + +If you cannot avoid preprocessor conditionals in templates, you can +suppress the line number information using the @samp{-P} preprocessor +option (but this will make debugging more difficult), by compiling the +affected modules like this: + +@smallexample +g++ -P foo.cc -o foo +@end smallexample + +@cindex parsing errors, templates +@item +Parsing errors are reported when templates are first +@emph{instantiated}---not on the template definition itself. In +particular, if you do not instantiate a template definition at all, the +compiler never reports any parsing errors that may be in the template +definition. +@end itemize + +@node Template debugging +@section Debugging information for templates + +@cindex templates and debugging information +@cindex debugging information and templates +Debugging information for templates works for some object code formats, +but not others. It works for stabs@footnote{Except that insufficient +debugging information for methods of template classes is generated in +stabs.} (used primarily in @sc{a.out} object code, but also in the Solaris 2 +version of @sc{elf}), and the @sc{mips} version of @sc{coff} debugging +format. + +@sc{dwarf} support is currently minimal, and requires further +development. diff --git a/contrib/gcc/cp/tree.def b/contrib/gcc/cp/tree.def new file mode 100644 index 000000000000..82b7954e29c0 --- /dev/null +++ b/contrib/gcc/cp/tree.def @@ -0,0 +1,116 @@ +/* This file contains the definitions and documentation for the + additional tree codes used in the GNU C++ compiler (see tree.def + for the standard codes). + Copyright (C) 1987, 1988, 1990, 1993 Free Software Foundation, Inc. + Hacked by Michael Tiemann (tiemann@cygnus.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* Reference to the contents of an offset + (a value whose type is an OFFSET_TYPE). + Operand 0 is the object within which the offset is taken. + Operand 1 is the offset. The language independent OFFSET_REF + just won't work for us. */ +DEFTREECODE (CP_OFFSET_REF, "cp_offset_ref", "r", 2) + +/* For DELETE_EXPR, operand 0 is the store to be destroyed. + Operand 1 is the value to pass to the destroying function + saying whether the store should be deallocated as well. */ +DEFTREECODE (DELETE_EXPR, "dl_expr", "e", 2) +DEFTREECODE (VEC_DELETE_EXPR, "vec_dl_expr", "e", 2) + +/* For a UNSAVE_EXPR, operand 0 is the value to unsave. By unsave, we + mean that all _EXPRs such as TARGET_EXPRs, SAVE_EXPRs, + WITH_CLEANUP_EXPRs, CALL_EXPRs and RTL_EXPRs, that are protected + from being evaluated more than once should be reset so that a new + expand_expr call of this expr will cause those to be re-evaluated. + This is useful when we want to reuse a tree in different places, + but where we must re-expand. */ +DEFTREECODE (UNSAVE_EXPR, "unsave_expr", "e", 1) + +/* Value is reference to particular overloaded class method. + Operand 0 is the class name (an IDENTIFIER_NODE); + operand 1 is the field (also an IDENTIFIER_NODE). + The COMPLEXITY field holds the class level (usually 0). */ +DEFTREECODE (SCOPE_REF, "scope_ref", "r", 2) + +/* When composing an object with a member, this is the result. + Operand 0 is the object. Operand 1 is the member (usually + a dereferenced pointer to member). */ +DEFTREECODE (MEMBER_REF, "member_ref", "r", 2) + +/* Type conversion operator in C++. TREE_TYPE is type that this + operator converts to. Operand is expression to be converted. */ +DEFTREECODE (TYPE_EXPR, "type_expr", "e", 1) + +/* For CPLUS_NEW_EXPR, operand 0 is function which performs initialization, + operand 1 is argument list to initialization function, + and operand 2 is the slot which was allocated for this expression. */ +DEFTREECODE (NEW_EXPR, "nw_expr", "e", 3) +DEFTREECODE (VEC_NEW_EXPR, "vec_nw_expr", "e", 3) + +/* A throw expression. operand 0 is the expression, if there was one, + else it is NULL_TREE. */ +DEFTREECODE (THROW_EXPR, "throw_expr", "e", 1) + +/* Template definition. The following fields have the specified uses, + although there are other macros in cp-tree.h that should be used for + accessing this data. + DECL_ARGUMENTS template parm vector + DECL_TEMPLATE_INFO template text &c + DECL_VINDEX list of instantiations already produced; + only done for functions so far + For class template: + DECL_INITIAL associated templates (methods &c) + DECL_RESULT null + For non-class templates: + TREE_TYPE type of object to be constructed + DECL_RESULT decl for object to be created + (e.g., FUNCTION_DECL with tmpl parms used) + */ +DEFTREECODE (TEMPLATE_DECL, "template_decl", "d", 0) + +/* Index into a template parameter list. This parameter must be a type. + Use TYPE_FIELDS to find parmlist and index. */ +DEFTREECODE (TEMPLATE_TYPE_PARM, "template_type_parm", "t", 0) + +/* Index into a template parameter list. This parameter must not be a + type. */ +DEFTREECODE (TEMPLATE_CONST_PARM, "template_const_parm", "c", 2) + +/* For uninstantiated parameterized types. + TYPE_VALUES tree list: + TREE_PURPOSE template decl + TREE_VALUE parm vector + TREE_CHAIN null + Other useful fields to be defined later. */ +DEFTREECODE (UNINSTANTIATED_P_TYPE, "uninstantiated_p_type", "t", 0) + +/* A thunk is a stub function. + + Thunks are used to implement multiple inheritance: + At run-time, such a thunk subtracts THUNK_DELTA (an int, not a tree) + from the this pointer, and then jumps to DECL_INITIAL + (which is an ADDR_EXPR whose operand is a FUNCTION_DECL). + + Other kinds of thunks may be defined later. */ +DEFTREECODE (THUNK_DECL, "thunk_decl", "d", 0) + +/* A namespace declaration. */ +DEFTREECODE (NAMESPACE_DECL, "namespace_decl", "d", 0) diff --git a/contrib/gcc/cpp.in b/contrib/gcc/cpp.in new file mode 100644 index 000000000000..5e85c0b54de5 --- /dev/null +++ b/contrib/gcc/cpp.in @@ -0,0 +1,41 @@ +#! /bin/sh + +# Copyright (C) 1999 Free Software Foundation, Inc. +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the +# Free Software Foundation; either version 2, or (at your option) any +# later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +# cpp: wrapper script for `gcc -E' + +# Check whether an input file was specified. +# This has some limited awareness of which switches take arguments. + +stdin="-" +next_is_arg= +for arg +do + if [ -n "$next_is_arg" ] + then next_is_arg= + else + case "$arg" in + -i* | -o | -x) next_is_arg=t;; + -) stdin= ;; + -*) ;; + *) stdin= ;; + esac + fi +done + +# Hand off to the gcc driver, with -E (preprocess only) +# and -xc (treat unknown files as source, not linker scripts) +exec @GCC@ -E -xc ${1+"$@"} $stdin diff --git a/contrib/gcc/dbxout.c b/contrib/gcc/dbxout.c index 3f561d631437..7389654223fb 100644 --- a/contrib/gcc/dbxout.c +++ b/contrib/gcc/dbxout.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/dbxout.c,v 1.4 1999/10/26 08:47:58 obrien Exp $ */ /* Output dbx-format symbol table data. diff --git a/contrib/gcc/dwarfout.c b/contrib/gcc/dwarfout.c index 6bdd954fb17b..e13098892039 100644 --- a/contrib/gcc/dwarfout.c +++ b/contrib/gcc/dwarfout.c @@ -19,7 +19,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/dwarfout.c,v 1.4 1999/10/26 08:38:21 obrien Exp $ */ #include "config.h" diff --git a/contrib/gcc/extend.texi b/contrib/gcc/extend.texi index b72a02ac4360..171bfe962f45 100644 --- a/contrib/gcc/extend.texi +++ b/contrib/gcc/extend.texi @@ -2,7 +2,7 @@ @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. -@c $FreeBSD$ +@c $FreeBSD: src/contrib/gcc/extend.texi,v 1.4 1999/10/27 09:41:10 obrien Exp $ @node C Extensions @chapter Extensions to the C Language Family diff --git a/contrib/gcc/final.c b/contrib/gcc/final.c index 9769409d1363..bebf41af065e 100644 --- a/contrib/gcc/final.c +++ b/contrib/gcc/final.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/final.c,v 1.7 1999/11/07 10:38:07 obrien Exp $ */ /* This is the final pass of the compiler. diff --git a/contrib/gcc/fixinc.dgux b/contrib/gcc/fixinc.dgux new file mode 100755 index 000000000000..422ba5f725fd --- /dev/null +++ b/contrib/gcc/fixinc.dgux @@ -0,0 +1,185 @@ +#!/bin/sh +# +# modified for dgux by hassey@dg-rtp.dg.com based on +# +# fixinc.svr4 written by Ron Guilmette (rfg@ncd.com). +# +# This file is part of GNU CC. +# +# GNU CC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU CC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU CC; see the file COPYING. If not, write to +# the Free Software Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# +# +# See README-fixinc for more information. + +# Directory containing the original header files. +INPUT=${2-${INPUT-/usr/include}} + +# Fail if no arg to specify a directory for the output. +if [ x$1 = x ] +then echo fixincludes: no output directory specified +exit 1 +fi + +# Directory in which to store the results. +LIB=${1?"fixincludes: output directory not specified"} + +# Make sure it exists. +if [ ! -d $LIB ]; then + mkdir $LIB || exit 1 +fi + +ORIG_DIR=`pwd` + +# Make LIB absolute if it is relative. +# Don't do this if not necessary, since may screw up automounters. +case $LIB in +/*) + ;; +*) + cd $LIB; LIB=`${PWDCMD-pwd}` + ;; +esac + +echo 'Building fixincludes in ' ${LIB} + +# Determine whether this filesystem has symbolic links. +if ln -s X $LIB/ShouldNotExist 2>/dev/null; then + rm -f $LIB/ShouldNotExist + LINKS=true +else + LINKS=false +fi + +echo 'Making directories:' +cd ${INPUT} +if $LINKS; then + files=`ls -LR | sed -n s/:$//p` +else + files=`find . -type d -print | sed '/^.$/d'` +fi +for file in $files; do + rm -rf $LIB/$file + if [ ! -d $LIB/$file ] + then mkdir $LIB/$file + fi +done + +# treetops gets an alternating list +# of old directories to copy +# and the new directories to copy to. +treetops="${INPUT} ${LIB}" + +if $LINKS; then + echo 'Making internal symbolic directory links' + for file in $files; do + dest=`ls -ld $file | sed -n 's/.*-> //p'` + if [ "$dest" ]; then + cwd=`pwd` + # In case $dest is relative, get to $file's dir first. + cd ${INPUT} + cd `echo ./$file | sed -n 's&[^/]*$&&p'` + # Check that the target directory exists. + # Redirections changed to avoid bug in sh on Ultrix. + (cd $dest) > /dev/null 2>&1 + if [ $? = 0 ]; then + cd $dest + # X gets the dir that the link actually leads to. + x=`pwd` + # If link leads back into ${INPUT}, + # make a similar link here. + if expr $x : "${INPUT}/.*" > /dev/null; then + # Y gets the actual target dir name, relative to ${INPUT}. + y=`echo $x | sed -n "s&${INPUT}/&&p"` + # DOTS is the relative path from ${LIB}/$file's dir back to ${LIB}. + dots=`echo "$file" | + sed -e 's@^./@@' -e 's@/./@/@g' -e 's@[^/][^/]*@..@g' -e 's@..$@@'` + echo $file '->' $dots$y ': Making link' + rm -fr ${LIB}/$file > /dev/null 2>&1 + ln -s $dots$y ${LIB}/$file > /dev/null 2>&1 + else + # If the link is to outside ${INPUT}, + # treat this directory as if it actually contained the files. +# This line used to have $dest instead of $x. +# $dest seemed to be wrong for links found in subdirectories +# of ${INPUT}. Does this change break anything? + treetops="$treetops $x ${LIB}/$file" + fi + fi + cd $cwd + fi + done +fi + +# Completely replace <_int_varargs.h> with a file that defines +# va_list and gnuc_va_list + +file=_int_varargs.h +if [ -r ${INPUT}/$file ]; then + echo Replacing $file + cat > ${LIB}/$file << EOF +/* This file was generated by fixinc.dgux. */ +#ifndef __INT_VARARGS_H +#define __INT_VARARGS_H + +#if defined(__m88k__) && defined (__DGUX__) +#ifndef __GNUC_VA_LIST +#define __GNUC_VA_LIST +typedef struct +{ + int __va_arg; /* argument number */ + int *__va_stk; /* start of args passed on stack */ + int *__va_reg; /* start of args passed in regs */ +} __gnuc_va_list; +#endif /* not __GNUC_VA_LIST */ +#endif /* 88k && dgux */ + +#ifndef _VA_LIST_ +#define _VA_LIST_ +typedef __gnuc_va_list va_list; +#endif /* _VA_LIST_ */ + +#endif /* __INT_VARARGS_H */ + +EOF + chmod a+r ${LIB}/$file +fi + +echo 'Removing unneeded directories:' +cd $LIB +files=`find . -type d -print | sort -r` +for file in $files; do + rmdir $LIB/$file > /dev/null 2>&1 +done + +if $LINKS; then + echo 'Making internal symbolic non-directory links' + cd ${INPUT} + files=`find . -type l -print` + for file in $files; do + dest=`ls -ld $file | sed -n 's/.*-> //p'` + if expr "$dest" : '[^/].*' > /dev/null; then + target=${LIB}/`echo file | sed "s|[^/]*\$|$dest|"` + if [ -f $target ]; then + ln -s $dest ${LIB}/$file >/dev/null 2>&1 + fi + fi + done +fi + +cd ${ORIG_DIR} + +exit 0 + diff --git a/contrib/gcc/fixinc.irix b/contrib/gcc/fixinc.irix new file mode 100755 index 000000000000..337289a121ed --- /dev/null +++ b/contrib/gcc/fixinc.irix @@ -0,0 +1,190 @@ +#! /bin/sh +# Install modified versions of certain problematic Irix include files. +# Copyright (C) 1997 Free Software Foundation, Inc. +# Contributed by Brendan Kehoe (brendan@cygnus.com). +# +# This file is part of GNU CC. +# +# GNU CC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU CC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU CC; see the file COPYING. If not, write to +# the Free Software Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# +# See README-fixinc for more information. + +# Directory containing the original header files. +INPUT=${2-${INPUT-/usr/include}} + +# Fail if no arg to specify a directory for the output. +if [ x$1 = x ] +then echo fixincludes: no output directory specified +exit 1 +fi + +# Directory in which to store the results. +LIB=${1?"fixincludes: output directory not specified"} + +# Make sure it exists. +if [ ! -d $LIB ]; then + mkdir $LIB || exit 1 +fi + +ORIG_DIR=`pwd` + +# Make LIB absolute if it is relative. +# Don't do this if not necessary, since may screw up automounters. +case $LIB in +/*) + ;; +*) + LIB=$ORIG_DIR/$LIB + ;; +esac + +echo 'Building fixincludes in ' ${LIB} + +# +# Note: For Irix, we deliberately don't try to create the directory trees, +# since we only modify math.h, limits.h and unistd.h. If we +# ADD ANY OTHERS, the "Making directories:" and symlinks code from +# fixinc.svr4 may have to go back in. + +# The Irix math.h defines struct exception, which conflicts with +# the class exception defined in the C++ file std/stdexcept.h. We +# redefine it to __math_exception. This is not a great fix, but I +# haven't been able to think of anything better. +file=math.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e '/struct exception/i\ +#ifdef __cplusplus\ +#define exception __math_exception\ +#endif'\ + -e '/struct exception/a\ +#ifdef __cplusplus\ +#undef exception\ +#endif' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# In limits.h, put #ifndefs around things that are supposed to be defined +# in float.h to avoid redefinition errors if float.h is included first. + +file=limits.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e '/[ ]FLT_MIN[ ]/i\ +#ifndef FLT_MIN +'\ + -e '/[ ]FLT_MIN[ ]/a\ +#endif +'\ + -e '/[ ]FLT_MAX[ ]/i\ +#ifndef FLT_MAX +'\ + -e '/[ ]FLT_MAX[ ]/a\ +#endif +'\ + -e '/[ ]FLT_DIG[ ]/i\ +#ifndef FLT_DIG +'\ + -e '/[ ]FLT_DIG[ ]/a\ +#endif +'\ + -e '/[ ]DBL_MIN[ ]/i\ +#ifndef DBL_MIN +'\ + -e '/[ ]DBL_MIN[ ]/a\ +#endif +'\ + -e '/[ ]DBL_MAX[ ]/i\ +#ifndef DBL_MAX +'\ + -e '/[ ]DBL_MAX[ ]/a\ +#endif +'\ + -e '/[ ]DBL_DIG[ ]/i\ +#ifndef DBL_DIG +'\ + -e '/[ ]DBL_DIG[ ]/a\ +#endif +' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# The Irix unistd.h will introduce a call to __vfork in its libc, but the +# function is never actually prototyped. +file=unistd.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e '/__vfork/i\ +extern pid_t __vfork(void);'\ + $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +exit 0 diff --git a/contrib/gcc/fixinc.ptx b/contrib/gcc/fixinc.ptx new file mode 100644 index 000000000000..93a8f2c5d0e8 --- /dev/null +++ b/contrib/gcc/fixinc.ptx @@ -0,0 +1,257 @@ +#! /bin/sh +# Install modified versions of certain ANSI-incompatible +# native Sequent DYNIX/ptx System V Release 3.2 system include files. +# Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc. +# Contributed by Bill Burton <billb@progress.com> +# Portions adapted from fixinc.svr4 and fixincludes. +# +# This file is part of GNU CC. +# +# GNU CC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU CC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU CC; see the file COPYING. If not, write to +# the Free Software Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# +# This script munges the native include files provided with DYNIX/ptx +# so as to remove things which are violations of the ANSI C standard. +# This is done by first running fixinc.svr4 which does most of the +# work. A few includes have fixes made to them afterwards by this +# script. Once munged, the resulting new system include files are +# placed in a directory that GNU C will search *before* searching the +# /usr/include directory. This script should work properly for most +# DYNIX/ptx systems. For other types of systems, you should use the +# `fixincludes' script instead. +# +# See README-fixinc for more information. + +# Directory containing the original header files. +INPUT=${2-${INPUT-/usr/include}} + +# Fail if no arg to specify a directory for the output. +if [ x$1 = x ] +then echo fixincludes: no output directory specified +exit 1 +fi + +# Directory in which to store the results. +LIB=${1?"fixincludes: output directory not specified"} + +# Make sure it exists. +if [ ! -d $LIB ]; then + mkdir $LIB || exit 1 +fi + +ORIG_DIR=`pwd` + +# Make LIB absolute if it is relative. +# Don't do this if not necessary, since may screw up automounters. +case $LIB in +/*) + ;; +*) + LIB=$ORIG_DIR/$LIB + ;; +esac + +echo 'Running fixinc.svr4' +# DYNIX/ptx has dirname so this is no problem +`dirname $0`/fixinc.svr4 $* +echo 'Finished fixinc.svr4' + +echo 'Building fixincludes in ' ${LIB} + +# Copied from fixincludes. +# Don't use or define the name va_list in stdio.h. +# This is for ANSI and also to interoperate properly with gcc's varargs.h. +file=stdio.h +if [ -r $file ] && [ ! -r ${LIB}/$file ]; then + cp $file ${LIB}/$file >/dev/null 2>&1 || echo "Can't copy $file" + chmod +w ${LIB}/$file 2>/dev/null + chmod a+r ${LIB}/$file 2>/dev/null +fi + +if [ -r ${LIB}/$file ]; then + echo Fixing $file, use of va_list + # Arrange for stdio.h to use stdarg.h to define __gnuc_va_list + (echo "#define __need___va_list" + echo "#include <stdarg.h>") > ${LIB}/${file}.sed + # Use __gnuc_va_list in arg types in place of va_list. + # On 386BSD use __gnuc_va_list instead of _VA_LIST_. We're hoping the + # trailing parentheses and semicolon save all other systems from this. + # Define __va_list__ (something harmless and unused) instead of va_list. + # Don't claim to have defined va_list. + sed -e 's@ va_list @ __gnuc_va_list @' \ + -e 's@ va_list)@ __gnuc_va_list)@' \ + -e 's@ _VA_LIST_));@ __gnuc_va_list));@' \ + -e 's@ va_list@ __va_list__@' \ + -e 's@\*va_list@*__va_list__@' \ + -e 's@ __va_list)@ __gnuc_va_list)@' \ + -e 's@_NEED___VA_LIST@_NEED___Va_LIST@' \ + -e 's@VA_LIST@DUMMY_VA_LIST@' \ + -e 's@_NEED___Va_LIST@_NEED___VA_LIST@' \ + ${LIB}/$file >> ${LIB}/${file}.sed + + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + if cmp $file ${LIB}/$file >/dev/null 2>&1; then + rm -f ${LIB}/$file + fi +fi + +# In pwd.h, PTX 1.x needs stdio.h included since FILE * was added in a +# prototype later on in the file. +file=pwd.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep stdio $file_to_fix > /dev/null; then + true + else + sed -e '/#include <sys\/types\.h>/a\ +\ +#if defined(__STDC__) || defined(__cplusplus)\ +#include <stdio.h>\ +#endif /* __STDC__ */ +' \ + $file_to_fix > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + echo Fixed $file_to_fix + fi +fi + +# Copied from fixincludes. +# math.h puts the declaration of matherr before the definition +# of struct exception, so the prototype (added by fixproto) causes havoc. +file=math.h +if [ -r $file ] && [ ! -r ${LIB}/$file ]; then + cp $file ${LIB}/$file >/dev/null 2>&1 || echo "Can't copy $file" + chmod +w ${LIB}/$file 2>/dev/null + chmod a+r ${LIB}/$file 2>/dev/null +fi + +if [ -r ${LIB}/$file ]; then + echo Fixing $file, matherr declaration + sed -e '/^struct exception/,$b' \ + -e '/matherr/i\ +struct exception; +'\ + ${LIB}/$file > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + if cmp $file ${LIB}/$file >/dev/null 2>&1; then + rm -f ${LIB}/$file + fi +fi + +# In netinet/in.h, the network byte swapping asm functions supported by the +# native cc compiler on PTX 1.x and 2.x is not supported in gcc. Instead, +# include <sys/byteorder.h> written out by the fixinc.svr4 script which has +# these same routines written in an asm format supported by gcc. +file=netinet/in.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep __GNUC__ $file_to_fix > /dev/null; then + true + else + sed -e '/#define NETSWAP/a\ +\ +#if defined (__GNUC__) || defined (__GNUG__)\ +#include <sys/byteorder.h>\ +#else /* not __GNUC__ */ +' \ + -e '/#endif[ ]*\/\* NETSWAP \*\//i\ +#endif /* not __GNUC__ */ +' \ + $file_to_fix > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + echo Fixed $file_to_fix + fi +fi + +# /usr/include/sys/mc_param.h has an embedded asm for the cpuid instruction +# on the P5. This is not used by anything else so we ifdef it out. +file=sys/mc_param.h +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep __GNUC__ $file_to_fix > /dev/null; then + true + else + sed -e '/__asm/,/}/{ +/__asm/i\ +#if !defined (__GNUC__) && !defined (__GNUG__) +/}/a\ +#endif +}' \ + $file_to_fix > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + echo Fixed $file_to_fix + fi +fi + +# /usr/include/sys/mc_param.h has an embedded asm for the cpuid instruction +# on the P5. This is not used by anything else so we ifdef it out. +file=sys/mc_param.h +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep __GNUC__ $file_to_fix > /dev/null; then + true + else + sed -e '/__asm/,/}/{ +/__asm/i\ +#if !defined (__GNUC__) && !defined (__GNUG__) +/}/a\ +#endif +}' \ + $file_to_fix > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + echo Fixed $file_to_fix + fi +fi + +exit 0 + diff --git a/contrib/gcc/fixinc.sco b/contrib/gcc/fixinc.sco new file mode 100755 index 000000000000..5caaf7fc3854 --- /dev/null +++ b/contrib/gcc/fixinc.sco @@ -0,0 +1,427 @@ +#! /bin/sh +# +# fixinc.sco -- Install modified versions of SCO system include +# files. +# +# Based on fixinc.svr4 script by Ron Guilmette (rfg@ncd.com) (SCO +# modifications by Ian Lance Taylor (ian@airs.com)). +# +# Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc. +# +# This file is part of GNU CC. +# +# GNU CC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU CC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU CC; see the file COPYING. If not, write to +# the Free Software Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# +# This script munges the native include files provided with SCO +# 3.2v4 systems so as to provide a reasonable namespace when +# compiling with gcc. The header files by default do not +# provide many essential definitions and declarations if +# __STDC__ is 1. This script modifies the header files to check +# for __STRICT_ANSI__ being defined instead. Once munged, the +# resulting new system include files are placed in a directory +# that GNU C will search *before* searching the /usr/include +# directory. This script should work properly for most SCO +# 3.2v4 systems. For other types of systems, you should use the +# `fixincludes' or the `fixinc.svr4' script instead. +# +# See README-fixinc for more information. + +# Directory containing the original header files. +INPUT=${2-${INPUT-/usr/include}} + +# Fail if no arg to specify a directory for the output. +if [ x$1 = x ] +then echo fixincludes: no output directory specified +exit 1 +fi + +# Directory in which to store the results. +LIB=${1?"fixincludes: output directory not specified"} + +# Make sure it exists. +if [ ! -d $LIB ]; then + mkdir $LIB || exit 1 +fi + +ORIG_DIR=`pwd` + +# Make LIB absolute if it is relative. +# Don't do this if not necessary, since may screw up automounters. +case $LIB in +/*) + ;; +*) + cd $LIB; LIB=`${PWDCMD-pwd}` + ;; +esac + +echo 'Building fixincludes in ' ${LIB} + +# Determine whether this filesystem has symbolic links. +if ln -s X $LIB/ShouldNotExist 2>/dev/null; then + rm -f $LIB/ShouldNotExist + LINKS=true +else + LINKS=false +fi + +echo 'Making directories:' +cd ${INPUT} +if $LINKS; then + files=`ls -LR | sed -n s/:$//p` +else + files=`find . -type d -print | sed '/^.$/d'` +fi +for file in $files; do + rm -rf $LIB/$file + if [ ! -d $LIB/$file ] + then mkdir $LIB/$file + fi +done + +# treetops gets an alternating list +# of old directories to copy +# and the new directories to copy to. +treetops="${INPUT} ${LIB}" + +if $LINKS; then + echo 'Making internal symbolic directory links' + for file in $files; do + dest=`ls -ld $file | sed -n 's/.*-> //p'` + if [ "$dest" ]; then + cwd=`pwd` + # In case $dest is relative, get to $file's dir first. + cd ${INPUT} + cd `echo ./$file | sed -n 's&[^/]*$&&p'` + # Check that the target directory exists. + # Redirections changed to avoid bug in sh on Ultrix. + (cd $dest) > /dev/null 2>&1 + if [ $? = 0 ]; then + cd $dest + # X gets the dir that the link actually leads to. + x=`pwd` + # If link leads back into ${INPUT}, + # make a similar link here. + if expr $x : "${INPUT}/.*" > /dev/null; then + # Y gets the actual target dir name, relative to ${INPUT}. + y=`echo $x | sed -n "s&${INPUT}/&&p"` + echo $file '->' $y ': Making link' + rm -fr ${LIB}/$file > /dev/null 2>&1 + ln -s ${LIB}/$y ${LIB}/$file > /dev/null 2>&1 + else + # If the link is to outside ${INPUT}, + # treat this directory as if it actually contained the files. +# This line used to have $dest instead of $x. +# $dest seemed to be wrong for links found in subdirectories +# of ${INPUT}. Does this change break anything? + treetops="$treetops $x ${LIB}/$file" + fi + fi + cd $cwd + fi + done +fi + +set - $treetops +while [ $# != 0 ]; do + # $1 is an old directory to copy, and $2 is the new directory to copy to. + echo "Finding header files in $1:" + cd ${INPUT} + cd $1 + files=`find . -name '*.h' -type f -print` + echo 'Checking header files:' + for file in $files; do + if egrep '!__STDC__' $file >/dev/null; then + if [ -r $file ]; then + cp $file $2/$file >/dev/null 2>&1 || echo "Can't copy $file" + chmod +w $2/$file + chmod a+r $2/$file + +# The following have been removed from the sed command below +# because it is more useful to leave these things in. +# The only reason to remove them was for -pedantic, +# which isn't much of a reason. -- rms. +# /^[ ]*#[ ]*ident/d + + sed -e ' + s/!__STDC__/!defined (__STRICT_ANSI__)/g + ' $2/$file > $2/$file.sed + mv $2/$file.sed $2/$file + if cmp $file $2/$file >/dev/null 2>&1; then + rm $2/$file + else + echo Fixed $file + fi + fi + fi + done + shift; shift +done + +# We shouldn't stay in the directory we just copied. +cd ${INPUT} + +# Fix first broken decl of getcwd present on some svr4 systems. + +file=stdlib.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e 's/getcwd(char \{0,\}\*, int)/getcwd(char *, size_t)/' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Fix second broken decl of getcwd present on some svr4 systems. Also +# fix the incorrect decl of profil present on some svr4 systems. + +file=unistd.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e 's/getcwd(char \*, int)/getcwd(char *, size_t)/' $file_to_fix \ + | sed -e 's/profil(unsigned short \*, unsigned int, unsigned int, unsigned int)/profil(unsigned short *, size_t, int, unsigned)/' > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Fix third broken decl of getcwd on SCO. Also fix incorrect decl of +# link. +file=prototypes.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e 's/getcwd(char \*, int)/getcwd(char *, size_t)/' $file_to_fix \ + | sed -e 's/const int link(const char \*, char \*)/extern int link(const char *, const char *)/' > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Fix an error in this file: the #if says _cplusplus, not the double +# underscore __cplusplus that it should be +file=tinfo.h +if [ -r $file ] && [ ! -r ${LIB}/$file ]; then + mkdir ${LIB}/rpcsvc 2>/dev/null + cp $file ${LIB}/$file >/dev/null 2>&1 || echo "Can't copy $file" + chmod +w ${LIB}/$file 2>/dev/null + chmod a+r ${LIB}/$file 2>/dev/null +fi + +if [ -r ${LIB}/$file ]; then + echo Fixing $file, __cplusplus macro + sed -e 's/[ ]_cplusplus/ __cplusplus/' ${LIB}/$file > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + if cmp $file ${LIB}/$file >/dev/null 2>&1; then + rm ${LIB}/$file + fi +fi + +# Fix prototype declaration of utime in sys/times.h. In 3.2v4.0 the +# const is missing. +file=sys/times.h +if [ -r $file ] && [ ! -r ${LIB}/$file ]; then + cp $file ${LIB}/$file >/dev/null 2>&1 || echo "Can't copy $file" + chmod +w ${LIB}/$file 2>/dev/null + chmod a+r ${LIB}/$file 2>/dev/null +fi + +if [ -r ${LIB}/$file ]; then + echo Fixing $file, utime prototype + sed -e 's/(const char \*, struct utimbuf \*);/(const char *, const struct utimbuf *);/' ${LIB}/$file > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + if cmp $file ${LIB}/$file >/dev/null 2>&1; then + rm ${LIB}/$file + fi +fi + +# This function is borrowed from fixinclude.svr4 +# The OpenServer math.h defines struct exception, which conflicts with +# the class exception defined in the C++ file std/stdexcept.h. We +# redefine it to __math_exception. This is not a great fix, but I +# haven't been able to think of anything better. +# +# OpenServer's math.h declares abs as inline int abs... Unfortunately, +# we blow over that one (with C++ linkage) and stick a new one in stdlib.h +# with C linkage. So we eat the one out of math.h. +file=math.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e '/struct exception/i\ +#ifdef __cplusplus\ +#define exception __math_exception\ +#endif'\ + -e '/struct exception/a\ +#ifdef __cplusplus\ +#undef exception\ +#endif' \ + -e 's@inline int abs(int [a-z][a-z]*) {.*}@extern "C" int abs(int);@' \ + $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# +# Also, the static functions lstat() and fchmod() in <sys/stat.h> +# cause G++ grief since they're not wrapped in "if __cplusplus". +# Fix that up now. +# +file=sys/stat.h +if [ -r $file ] && [ ! -r ${LIB}/$file ]; then + cp $file ${LIB}/$file >/dev/null 2>&1 || echo "Can't copy $file" + chmod +w ${LIB}/$file 2>/dev/null + chmod a+r ${LIB}/$file 2>/dev/null +fi + +if [ -r ${LIB}/$file ]; then + echo Fixing $file, static definitions not C++-aware. + sed -e '/^static int[ ]*/i\ +#if __cplusplus\ +extern "C"\ +{\ +#endif /* __cplusplus */ \ +' \ +-e '/^}$/a\ +#if __cplusplus\ +}\ +#endif /* __cplusplus */ \ +' ${LIB}/$file > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + if cmp $file ${LIB}/$file >/dev/null 2>&1; then + rm -f ${LIB}/$file + fi +fi + +# This fix has the regex modified from the from fixinc.wrap +# Avoid the definition of the bool type in the following files when using +# g++, since it's now an official type in the C++ language. +for file in term.h tinfo.h +do + if [ -r $INPUT/$file ]; then + echo Checking $INPUT/$file + w='[ ]' + if grep "typedef$w.*char$w.*bool$w*;" $INPUT/$file >/dev/null + then + echo Fixed $file + rm -f $LIB/$file + cat << __EOF__ >$LIB/$file +#ifndef _CURSES_H_WRAPPER +#ifdef __cplusplus +# define bool __curses_bool_t +#endif +#include_next <$file> +#ifdef __cplusplus +# undef bool +#endif +#define _CURSES_H_WRAPPER +#endif /* _CURSES_H_WRAPPER */ +__EOF__ + # Define _CURSES_H_WRAPPER at the end of the wrapper, not the start, + # so that if #include_next gets another instance of the wrapper, + # this will follow the #include_next chain until we arrive at + # the real system include file. + chmod a+r $LIB/$file + fi + fi +done + +echo 'Removing unneeded directories:' +cd $LIB +files=`find . -type d -print | sort -r` +for file in $files; do + rmdir $LIB/$file > /dev/null 2>&1 +done + +if $LINKS; then + echo 'Making internal symbolic non-directory links' + cd ${INPUT} + files=`find . -type l -print` + for file in $files; do + dest=`ls -ld $file | sed -n 's/.*-> //p'` + if expr "$dest" : '[^/].*' > /dev/null; then + target=${LIB}/`echo file | sed "s|[^/]*\$|$dest|"` + if [ -f $target ]; then + ln -s $dest ${LIB}/$file >/dev/null 2>&1 + fi + fi + done +fi + +exit 0 diff --git a/contrib/gcc/fixinc.svr4 b/contrib/gcc/fixinc.svr4 new file mode 100755 index 000000000000..46e07ce0ac9f --- /dev/null +++ b/contrib/gcc/fixinc.svr4 @@ -0,0 +1,1726 @@ +#! /bin/sh +# Install modified versions of certain ANSI-incompatible +# native System V Release 4 system include files. +# Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc. +# Contributed by Ron Guilmette (rfg@monkeys.com). +# +# This file is part of GNU CC. +# +# GNU CC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU CC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU CC; see the file COPYING. If not, write to +# the Free Software Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# +# This script munges the native include files provided with System V +# Release 4 systems so as to remove things which are violations of the +# ANSI C standard. Once munged, the resulting new system include files +# are placed in a directory that GNU C will search *before* searching +# the /usr/include directory. This script should work properly for most +# System V Release 4 systems. For other types of systems, you should +# use the `fixincludes' script instead. +# +# See README-fixinc for more information. + +# Directory containing the original header files. +INPUT=${2-${INPUT-/usr/include}} + +# Fail if no arg to specify a directory for the output. +if [ x$1 = x ] +then echo fixincludes: no output directory specified +exit 1 +fi + +# Directory in which to store the results. +LIB=${1?"fixincludes: output directory not specified"} + +# Make sure it exists. +if [ ! -d $LIB ]; then + mkdir $LIB || exit 1 +fi + +ORIG_DIR=`pwd` + +# Make LIB absolute if it is relative. +# Don't do this if not necessary, since may screw up automounters. +case $LIB in +/*) + ;; +*) + LIB=$ORIG_DIR/$LIB + ;; +esac + +echo 'Building fixincludes in ' ${LIB} + +# Determine whether this filesystem has symbolic links. +if ln -s X $LIB/ShouldNotExist 2>/dev/null; then + rm -f $LIB/ShouldNotExist + LINKS=true +else + LINKS=false +fi + +echo 'Making directories:' +cd ${INPUT} +if $LINKS; then + files=`find . -follow -type d -print 2>/dev/null | sed '/^.$/d'` +else + files=`find . -type d -print | sed '/^.$/d'` +fi +for file in $files; do + rm -rf $LIB/$file + if [ ! -d $LIB/$file ] + then mkdir $LIB/$file + fi +done + +# treetops gets an alternating list +# of old directories to copy +# and the new directories to copy to. +treetops="${INPUT} ${LIB}" + +if $LINKS; then + echo 'Making internal symbolic directory links' + for file in $files; do + dest=`ls -ld $file | sed -n 's/.*-> //p'` + if [ "$dest" ]; then + cwd=`pwd` + # In case $dest is relative, get to $file's dir first. + cd ${INPUT} + cd `echo ./$file | sed -n 's&[^/]*$&&p'` + rwd=`pwd` + # Check that the target directory exists. + # Redirections changed to avoid bug in sh on Ultrix. + (cd $dest) > /dev/null 2>&1 + if [ $? = 0 ]; then + cd $dest + # X gets the dir that the link actually leads to. + x=`pwd` + # If link leads back into ${INPUT}, + # make a similar link here. + if expr "$dest" : '[^/][^/]*' >/dev/null && [ ! -h $dest ]; then + echo $file '->' $dest': Making link' + rm -fr ${LIB}/$file > /dev/null 2>&1 + ln -s $dest ${LIB}/$file > /dev/null 2>&1 + elif expr $x : "${INPUT}/.*" > /dev/null; then + # Y gets the actual target dir name, relative to ${INPUT}. + y=`echo $x | sed -n "s&${INPUT}/&&p"` + # DOTS is the relative path from ${LIB}/$file's dir back to ${LIB}. + dots=`echo "$file" | + sed -e 's@^./@@' -e 's@/./@/@g' -e 's@[^/][^/]*@..@g' -e 's@..$@@'` + echo $file '->' $dots$y ': Making link' + rm -fr ${LIB}/$file > /dev/null 2>&1 + ln -s $dots$y ${LIB}/$file > /dev/null 2>&1 + elif expr $x : "${rwd}/.*" > /dev/null; then + # Y gets the actual target dir name, relative to the directory where the link is. + y=`echo $x | sed -n "s&${rwd}/&&p"` + # DOTS is the relative path from ${LIB}/$file's dir back to ${LIB}. + dots=`echo "$file" | + sed -e 's@^./@@' -e 's@/./@/@g' -e 's@[^/][^/]*@..@g' -e 's@..$@@'` + echo $file '->' $dots$y ': Making link' + rm -fr ${LIB}/$file > /dev/null 2>&1 + ln -s $dots$y ${LIB}/$file > /dev/null 2>&1 + else + # If the link is to outside ${INPUT}, + # treat this directory as if it actually contained the files. +# This line used to have $dest instead of $x. +# $dest seemed to be wrong for links found in subdirectories +# of ${INPUT}. Does this change break anything? + treetops="$treetops $x ${LIB}/$file" + fi + fi + cd $cwd + fi + done +fi + +set - $treetops +while [ $# != 0 ]; do + # $1 is an old directory to copy, and $2 is the new directory to copy to. + echo "Finding header files in $1:" + cd ${INPUT} + cd $1 + files=`find . -name '*.h' -type f -print` + echo 'Checking header files:' + for file in $files; do + if [ -r $file ]; then + cp $file $2/$file >/dev/null 2>&1 || echo "Can't copy $file" + chmod +w $2/$file + chmod a+r $2/$file + +# The following have been removed from the sed command below +# because it is more useful to leave these things in. +# The only reason to remove them was for -pedantic, +# which isn't much of a reason. -- rms. +# /^[ ]*#[ ]*ident/d + +# This code makes Solaris SCSI fail, because it changes the +# alignment within some critical structures. See <sys/scsi/impl/commands.h>. +# s/u_char\([ ][ ]*[a-zA-Z0-9_][a-zA-Z0-9_]*[ ]*:[ ]*[0-9][0-9]*\)/u_int\1/ +# Disable these also, since they probably aren't safe either. +# s/u_short\([ ][ ]*[a-zA-Z0-9_][a-zA-Z0-9_]*[ ]*:[ ]*[0-9][0-9]*\)/u_int\1/ +# s/ushort\([ ][ ]*[a-zA-Z0-9_][a-zA-Z0-9_]*[ ]*:[ ]*[0-9][0-9]*\)/u_int\1/ +# s/evcm_t\([ ][ ]*[a-zA-Z0-9_][a-zA-Z0-9_]*[ ]*:[ ]*[0-9][0-9]*\)/u_int\1/ +# s/Pbyte\([ ][ ]*[a-zA-Z0-9_][a-zA-Z0-9_]*[ ]*:[ ]*SEQSIZ\)/unsigned int\1/ + +# The change of u_char, etc, to u_int +# applies to bit fields. + sed -e ' + s%^\([ ]*#[ ]*else\)[ ]*/[^*].*%\1% + s%^\([ ]*#[ ]*else\)[ ]*[^/ ].*%\1% + s%^\([ ]*#[ ]*endif\)[ ]*/[^*].*%\1% + s%^\([ ]*#[ ]*endif\)[ ]*[^/ ].*%\1% + s/#lint(on)/defined(lint)/g + s/#lint(off)/!defined(lint)/g + s/#machine(\([^)]*\))/defined(__\1__)/g + s/#system(\([^)]*\))/defined(__\1__)/g + s/#cpu(\([^)]*\))/defined(__\1__)/g + /#[a-z]*if.*[ (]m68k/ s/\([^_]\)m68k/\1__m68k__/g + /#[a-z]*if.*[ (]__i386\([^_]\)/ s/__i386/__i386__/g + /#[a-z]*if.*[ (]i386/ s/\([^_]\)i386/\1__i386__/g + /#[a-z]*if.*[ (!]__i860\([^_]\)/ s/__i860/__i860__/g + /#[a-z]*if.*[ (!]i860/ s/\([^_]\)i860/\1__i860__/g + /#[a-z]*if.*[ (]sparc/ s/\([^_]\)sparc/\1__sparc__/g + /#[a-z]*if.*[ (]mc68000/ s/\([^_]\)mc68000/\1__mc68000__/g + /#[a-z]*if.*[ (]vax/ s/\([^_]\)vax/\1__vax__/g + /#[a-z]*if.*[ (]sun/ s/\([^_]\)\(sun[a-z0-9]*\)\([^a-z0-9_]\)/\1__\2__\3/g + /#[a-z]*if.*[ (]sun/ s/\([^_]\)\(sun[a-z0-9]*\)$/\1__\2__/g + /#[a-z]*if.*[ (]ns32000/ s/\([^_]\)ns32000/\1__ns32000__/g + /#[a-z]*if.*[ (]pyr/ s/\([^_]\)pyr/\1__pyr__/g + /#[a-z]*if.*[ (]is68k/ s/\([^_]\)is68k/\1__is68k__/g + s/__STDC__[ ][ ]*==[ ][ ]*0/!defined (__STRICT_ANSI__)/g + s/__STDC__[ ][ ]*==[ ][ ]*1/defined (__STRICT_ANSI__)/g + s/__STDC__[ ][ ]*!=[ ][ ]*0/defined (__STRICT_ANSI__)/g + s/__STDC__[ ][ ]*!=[ ][ ]*1/!defined (__STRICT_ANSI__)/g + s/__STDC__ - 0 == 0/!defined (__STRICT_ANSI__)/g + s/__STDC__ - 0 == 1/defined (__STRICT_ANSI__)/g + /^typedef[ ][ ]*[unsigned ]*long[ ][ ]*[u_]*longlong_t;/s/long/long long/ + ' $2/$file > $2/$file.sed + mv $2/$file.sed $2/$file + if cmp $file $2/$file >/dev/null 2>&1; then + rm $2/$file + else + echo Fixed $file + fi + fi + done + shift; shift +done + +# Install the proper definition of the three standard types in header files +# that they come from. +for file in sys/types.h stdlib.h sys/stdtypes.h stddef.h memory.h unistd.h; do + if [ -r $file ] && [ ! -r ${LIB}/$file ]; then + cp $file ${LIB}/$file >/dev/null 2>&1 || echo "Can't copy $file" + chmod +w ${LIB}/$file 2>/dev/null + chmod a+r ${LIB}/$file 2>/dev/null + fi + + if [ -r ${LIB}/$file ]; then + echo Fixing size_t, ptrdiff_t and wchar_t in $file + sed \ + -e '/typedef[ ][ ]*[a-z_][ a-z_]*[ ]size_t/i\ +#ifndef __SIZE_TYPE__\ +#define __SIZE_TYPE__ long unsigned int\ +#endif +' \ + -e 's/typedef[ ][ ]*[a-z_][ a-z_]*[ ]size_t/typedef __SIZE_TYPE__ size_t/' \ + -e '/typedef[ ][ ]*[a-z_][ a-z_]*[ ]ptrdiff_t/i\ +#ifndef __PTRDIFF_TYPE__\ +#define __PTRDIFF_TYPE__ long int\ +#endif +' \ + -e 's/typedef[ ][ ]*[a-z_][ a-z_]*[ ]ptrdiff_t/typedef __PTRDIFF_TYPE__ ptrdiff_t/' \ + -e '/typedef[ ][ ]*[a-z_][ a-z_]*[ ]wchar_t/i\ +#ifndef __WCHAR_TYPE__\ +#define __WCHAR_TYPE__ int\ +#endif +' \ + -e 's/typedef[ ][ ]*[a-z_][ a-z_]*[ ]wchar_t/typedef __WCHAR_TYPE__ wchar_t/' \ + ${LIB}/$file > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + if cmp $file ${LIB}/$file >/dev/null 2>&1; then + rm ${LIB}/$file + fi + fi +done + +# Fix first broken decl of getcwd present on some svr4 systems. + +file=stdlib.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e 's/getcwd(char \*, int)/getcwd(char *, size_t)/' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Fix second broken decl of getcwd present on some svr4 systems. Also +# fix the incorrect decl of profil present on some svr4 systems. + +file=unistd.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e 's/getcwd(char \*, int)/getcwd(char *, size_t)/' $file_to_fix \ + | sed -e 's/profil(unsigned short \*, unsigned int, unsigned int, unsigned int)/profil(unsigned short *, size_t, int, unsigned)/' > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Fix the definition of NULL in <sys/param.h> so that it is conditional +# and so that it is correct for both C and C++. + +file=sys/param.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + chmod a+r /tmp/$base + sed -e '/^#define[ ]*NULL[ ]*0$/c\ +#ifndef NULL\ +#ifdef __cplusplus\ +#define __NULL_TYPE\ +#else /* !defined(__cplusplus) */\ +#define __NULL_TYPE (void *)\ +#endif /* !defined(__cplusplus) */\ +#define NULL (__NULL_TYPE 0)\ +#endif /* !defined(NULL) */' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Likewise fix the definition of NULL in <stdio.h> so that it is conditional +# and so that it is correct for both C and C++. + +file=stdio.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/^#define[ ]*NULL[ ]*0$/c\ +#ifdef __cplusplus\ +#define __NULL_TYPE\ +#else /* !defined(__cplusplus) */\ +#define __NULL_TYPE (void *)\ +#endif /* !defined(__cplusplus) */\ +#define NULL (__NULL_TYPE 0)' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Likewise fix the definition of NULL in <dbm.h> so that it is conditional +# and so that it is correct for both C and C++. + +file=dbm.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/^#define[ ]*NULL[ ]*((char \*) 0)$/c\ +#ifndef NULL\ +#ifdef __cplusplus\ +#define __NULL_TYPE\ +#else /* !defined(__cplusplus) */\ +#define __NULL_TYPE (void *)\ +#endif /* !defined(__cplusplus) */\ +#define NULL (__NULL_TYPE 0)\ +#endif /* !defined(NULL) */' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Add a prototyped declaration of mmap to <sys/mman.h>. + +file=sys/mman.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/^extern caddr_t mmap();$/c\ +#ifdef __STDC__\ +extern caddr_t mmap (caddr_t, size_t, int, int, int, off_t);\ +#else /* !defined(__STDC__) */\ +extern caddr_t mmap ();\ +#endif /* !defined(__STDC__) */' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Fix declarations of `ftw' and `nftw' in <ftw.h>. On some/most SVR4 systems +# the file <ftw.h> contains extern declarations of these functions followed +# by explicitly `static' definitions of these functions... and that's not +# allowed according to ANSI C. (Note however that on Solaris, this header +# file glitch has been pre-fixed by Sun. In the Solaris version of <ftw.h> +# there are no static definitions of any function so we don't need to do +# any of this stuff when on Solaris. + +file=ftw.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if test -z "$file_to_fix" || grep 'define ftw' $file_to_fix > /dev/null; then +# Either we have no <ftw.h> file at all, or else we have the pre-fixed Solaris +# one. Either way, we don't have to do anything. + true +else + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/^extern int ftw(const/i\ +#if !defined(_STYPES)\ +static\ +#else\ +extern\ +#endif +'\ + -e 's/extern \(int ftw(const.*\)$/\1/' \ + -e '/^extern int nftw/i\ +#if defined(_STYPES)\ +static\ +#else\ +extern\ +#endif +'\ + -e 's/extern \(int nftw.*\)$/\1/' \ + -e '/^extern int ftw(),/c\ +#if !defined(_STYPES)\ +static\ +#else\ +extern\ +#endif\ + int ftw();\ +#if defined(_STYPES)\ +static\ +#else\ +extern\ +#endif\ + int nftw();' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Avoid the definition of the bool type in the Solaris 2.x curses.h when using +# g++, since it's now an official type in the C++ language. +file=curses.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi + +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e 's,^typedef[ ]char[ ]bool;$,#ifndef __cplusplus\ +typedef char bool;\ +#endif /* !defined __cplusplus */,' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Add a `static' declaration of `getrnge' into <regexp.h>. + +# Don't do this if there is already a `static void getrnge' declaration +# present, since this would cause a redeclaration error. Solaris 2.x has +# such a declaration. + +file=regexp.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep "static void getrnge" $file_to_fix > /dev/null; then + true + else + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/^static int[ ]*size;/c\ +static int size ;\ +\ +static int getrnge ();' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Disable apparent native compiler optimization cruft in SVR4.2 <string.h> +# that is visible to any ANSI compiler using this include. Simply +# delete the lines that #define some string functions to internal forms. + +file=string.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/#define.*__std_hdr_/d' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Delete any #defines of `__i386' which may be present in <ieeefp.h>. They +# tend to conflict with the compiler's own definition of this symbol. (We +# will use the compiler's definition.) +# Likewise __sparc, for Solaris, and __i860, and a few others +# (guessing it is necessary for all of them). + +file=ieeefp.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/#define[ ]*__i386 /d' -e '/#define[ ]*__sparc /d' \ + -e '/#define[ ]*__i860 /d' -e '/#define[ ]*__m88k /d' \ + -e '/#define[ ]*__mips /d' -e '/#define[ ]*__m68k /d' \ + /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Add a #define of _SIGACTION_ into <sys/signal.h>. +# Also fix types of SIG_DFL, SIG_ERR, SIG_IGN, and SIG_HOLD. + +file=sys/signal.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/^struct sigaction {/c\ +#define _SIGACTION_\ +struct sigaction {' \ + -e '1,$s/(void *(\*)())/(void (*)(int))/' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Fix declarations of `makedev', `major', and `minor' in <sys/mkdev.h>. + +file=sys/mkdev.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/^dev_t makedev(const/c\ +static dev_t makedev(const major_t, const minor_t);' \ + -e '/^dev_t makedev()/c\ +static dev_t makedev();' \ + -e '/^major_t major(const/c\ +static major_t major(const dev_t);' \ + -e '/^major_t major()/c\ +static major_t major();' \ + -e '/^minor_t minor(const/c\ +static minor_t minor(const dev_t);' \ + -e '/^minor_t minor()/c\ +static minor_t minor();' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Fix reference to NMSZ in <sys/adv.h>. + +file=sys/adv.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed 's/\[NMSZ\]/\[RFS_NMSZ\]/g' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Fix reference to NC_NPI_RAW in <sys/netcspace.h>. Also fix types of +# array initializers. + +file=sys/netcspace.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed 's/NC_NPI_RAW/NC_TPI_RAW/g' $file_to_fix \ + | sed 's/NC_/(unsigned long) NC_/' > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Conditionalize all of <fs/rfs/rf_cache.h> on _KERNEL being defined. + +file=fs/rfs/rf_cache.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep _KERNEL $file_to_fix > /dev/null; then + true + else + echo '#ifdef _KERNEL' > /tmp/$base + cat $file_to_fix >> /tmp/$base + echo '#endif /* defined(_KERNEL) */' >> /tmp/$base + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + rm -f /tmp/$base + fi +fi + +# Conditionalize all of <sys/erec.h> on _KERNEL being defined. + +file=sys/erec.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep _KERNEL $file_to_fix > /dev/null; then + true + else + echo '#ifdef _KERNEL' > /tmp/$base + cat $file_to_fix >> /tmp/$base + echo '#endif /* defined(_KERNEL) */' >> /tmp/$base + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + rm -f /tmp/$base + fi +fi + +# Conditionalize all of <sys/err.h> on _KERNEL being defined. + +file=sys/err.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep _KERNEL $file_to_fix > /dev/null; then + true + else + echo '#ifdef _KERNEL' > /tmp/$base + cat $file_to_fix >> /tmp/$base + echo '#endif /* defined(_KERNEL) */' >> /tmp/$base + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + rm -f /tmp/$base + fi +fi + +# Conditionalize all of <sys/char.h> on _KERNEL being defined. + +file=sys/char.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep _KERNEL $file_to_fix > /dev/null; then + true + else + echo '#ifdef _KERNEL' > /tmp/$base + cat $file_to_fix >> /tmp/$base + echo '#endif /* defined(_KERNEL) */' >> /tmp/$base + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + rm -f /tmp/$base + fi +fi + +# Conditionalize all of <sys/getpages.h> on _KERNEL being defined. + +file=sys/getpages.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep _KERNEL $file_to_fix > /dev/null; then + true + else + echo '#ifdef _KERNEL' > /tmp/$base + cat $file_to_fix >> /tmp/$base + echo '#endif /* defined(_KERNEL) */' >> /tmp/$base + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + rm -f /tmp/$base + fi +fi + +# Conditionalize all of <sys/map.h> on _KERNEL being defined. + +file=sys/map.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep _KERNEL $file_to_fix > /dev/null; then + true + else + echo '#ifdef _KERNEL' > /tmp/$base + cat $file_to_fix >> /tmp/$base + echo '#endif /* defined(_KERNEL) */' >> /tmp/$base + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + rm -f /tmp/$base + fi +fi + +# Conditionalize all of <sys/cmn_err.h> on _KERNEL being defined. + +file=sys/cmn_err.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep _KERNEL $file_to_fix > /dev/null; then + true + else + echo '#ifdef _KERNEL' > /tmp/$base + cat $file_to_fix >> /tmp/$base + echo '#endif /* defined(_KERNEL) */' >> /tmp/$base + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + rm -f /tmp/$base + fi +fi + +# Conditionalize all of <sys/kdebugger.h> on _KERNEL being defined. + +file=sys/kdebugger.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep _KERNEL $file_to_fix > /dev/null; then + true + else + echo '#ifdef _KERNEL' > /tmp/$base + cat $file_to_fix >> /tmp/$base + echo '#endif /* defined(_KERNEL) */' >> /tmp/$base + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + rm -f /tmp/$base + fi +fi + +# Conditionalize some of <netinet/in.h> on _KERNEL being defined. +# This has been taken out because it breaks on some versions of +# DYNIX/ptx, and it does not seem to do much good on any system. +# file=netinet/in.h +# base=`basename $file` +# if [ -r ${LIB}/$file ]; then +# file_to_fix=${LIB}/$file +# else +# if [ -r ${INPUT}/$file ]; then +# file_to_fix=${INPUT}/$file +# else +# file_to_fix="" +# fi +# fi +# if [ \! -z "$file_to_fix" ]; then +# echo Checking $file_to_fix +# if grep _KERNEL $file_to_fix > /dev/null; then +# true +# else +# sed -e '/#ifdef INKERNEL/i\ +# #ifdef _KERNEL +# ' \ +# -e '/#endif[ ]*\/\* INKERNEL \*\//a\ +# #endif /* _KERNEL */ +# ' \ +# $file_to_fix > ${LIB}/${file}.sed +# rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file +# echo Fixed $file_to_fix +# fi +# fi + +# Conditionalize some of <sys/endian.h> on __GNUC__ and __GNUG__. + +file=sys/endian.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + if grep __GNUC__ $file_to_fix > /dev/null; then + true + else + sed -e '/# ifdef __STDC__/i\ +# if !defined (__GNUC__) && !defined (__GNUG__) +' \ + -e '/# include <sys\/byteorder.h>/s/ / /'\ + -e '/# include <sys\/byteorder.h>/i\ +# endif /* !defined (__GNUC__) && !defined (__GNUG__) */ +'\ + $file_to_fix > ${LIB}/${file}.sed + rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file + echo Fixed $file_to_fix + fi +fi + +# Commented out because tmcconne@sedona.intel.com says we don't clearly need it +# and the text in types.h is not erroneous. +## In sys/types.h, don't name the enum for booleans. +# +#file=sys/types.h +#base=`basename $file` +#if [ -r ${LIB}/$file ]; then +# file_to_fix=${LIB}/$file +#else +# if [ -r ${INPUT}/$file ]; then +# file_to_fix=${INPUT}/$file +# else +# file_to_fix="" +# fi +#fi +#if [ \! -z "$file_to_fix" ]; then +# echo Checking $file_to_fix +# if grep "enum boolean" $file_to_fix > /dev/null; then +# sed -e 's/enum boolean/enum/' ${LIB}/$file > ${LIB}/${file}.sed +# rm -f ${LIB}/$file; mv ${LIB}/${file}.sed ${LIB}/$file +# echo Fixed $file_to_fix +# else +# true +# fi +#fi + +# Remove useless extern keyword from struct forward declarations in +# <sys/stream.h> and <sys/strsubr.h> + +file=sys/stream.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e ' + s/extern struct stdata;/struct stdata;/g + s/extern struct strevent;/struct strevent;/g + ' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +file=sys/strsubr.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e ' + s/extern struct strbuf;/struct strbuf;/g + s/extern struct uio;/struct uio;/g + s/extern struct thread;/struct thread;/g + s/extern struct proc;/struct proc;/g + ' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Put storage class at start of decl, to avoid warning. +file=rpc/types.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e ' + s/const extern/extern const/g + ' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Convert functions to prototype form, and fix arg names in <sys/stat.h>. + +file=sys/stat.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e '/^stat([ ]*[^c]/{ +N +N +s/(.*)\n/( / +s/;\n/, / +s/;$/)/ +}' \ + -e '/^lstat([ ]*[^c]/{ +N +N +s/(.*)\n/( / +s/;\n/, / +s/;$/)/ +}' \ + -e '/^fstat([ ]*[^i]/{ +N +N +s/(.*)\n/( / +s/;\n/, / +s/;$/)/ +}' \ + -e '/^mknod([ ]*[^c]/{ +N +N +N +s/(.*)\n/( / +s/;\n/, /g +s/;$/)/ +}' \ + -e '1,$s/\([^A-Za-z]\)path\([^A-Za-z]\)/\1__path\2/g' \ + -e '1,$s/\([^A-Za-z]\)buf\([^A-Za-z]\)/\1__buf\2/g' \ + -e '1,$s/\([^A-Za-z]\)fd\([^A-Za-z]\)/\1__fd\2/g' \ + -e '1,$s/ret\([^u]\)/__ret\1/g' \ + -e '1,$s/\([^_]\)mode\([^_]\)/\1__mode\2/g' \ + -e '1,$s/\([^_r]\)dev\([^_]\)/\1__dev\2/g' /tmp/$base > /tmp/$base.sed + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base.sed ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base /tmp/$base.sed +fi + +# Sony NEWSOS 5.0 does not support the complete ANSI C standard. + +if [ -x /bin/sony ]; then + if /bin/sony; then + + # Change <stdio.h> to not define __filbuf, __flsbuf, and __iob + + file=stdio.h + base=`basename $file` + if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file + else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi + fi + if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e ' + s/__filbuf/_filbuf/g + s/__flsbuf/_flsbuf/g + s/__iob/_iob/g + ' /tmp/$base > /tmp/$base.sed + mv /tmp/$base.sed /tmp/$base + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base + fi + + # Change <ctype.h> to not define __ctype + + file=ctype.h + base=`basename $file` + if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file + else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi + fi + if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + cp $file_to_fix /tmp/$base + chmod +w /tmp/$base + sed -e ' + s/__ctype/_ctype/g + ' /tmp/$base > /tmp/$base.sed + mv /tmp/$base.sed /tmp/$base + if cmp $file_to_fix /tmp/$base.sed >/dev/null 2>&1; then + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base + fi + fi +fi + +# In limits.h, put #ifndefs around things that are supposed to be defined +# in float.h to avoid redefinition errors if float.h is included first. +# Solaris 2.1 has this problem. + +file=limits.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e '/[ ]FLT_MIN[ ]/i\ +#ifndef FLT_MIN +'\ + -e '/[ ]FLT_MIN[ ]/a\ +#endif +'\ + -e '/[ ]FLT_MAX[ ]/i\ +#ifndef FLT_MAX +'\ + -e '/[ ]FLT_MAX[ ]/a\ +#endif +'\ + -e '/[ ]FLT_DIG[ ]/i\ +#ifndef FLT_DIG +'\ + -e '/[ ]FLT_DIG[ ]/a\ +#endif +'\ + -e '/[ ]DBL_MIN[ ]/i\ +#ifndef DBL_MIN +'\ + -e '/[ ]DBL_MIN[ ]/a\ +#endif +'\ + -e '/[ ]DBL_MAX[ ]/i\ +#ifndef DBL_MAX +'\ + -e '/[ ]DBL_MAX[ ]/a\ +#endif +'\ + -e '/[ ]DBL_DIG[ ]/i\ +#ifndef DBL_DIG +'\ + -e '/[ ]DBL_DIG[ ]/a\ +#endif +' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Completely replace <sys/varargs.h> with a file that includes gcc's +# stdarg.h or varargs.h files as appropriate. + +file=sys/varargs.h +if [ -r ${INPUT}/$file ]; then + echo Replacing $file + cat > ${LIB}/$file << EOF +/* This file was generated by fixincludes. */ +#ifndef _SYS_VARARGS_H +#define _SYS_VARARGS_H + +#ifdef __STDC__ +#include <stdarg.h> +#else +#include <varargs.h> +#endif + +#endif /* _SYS_VARARGS_H */ +EOF + chmod a+r ${LIB}/$file +fi + +# In math.h, put #ifndefs around things that might be defined in a gcc +# specific math-*.h file. + +file=math.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e '/define[ ]HUGE_VAL[ ]/i\ +#ifndef HUGE_VAL +'\ + -e '/define[ ]HUGE_VAL[ ]/a\ +#endif +' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +# Solaris math.h and floatingpoint.h define __P without protection, +# which conflicts with the fixproto definition. The fixproto +# definition and the Solaris definition are used the same way. +for file in math.h floatingpoint.h; do + base=`basename $file` + if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file + else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi + fi + if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e '/^#define[ ]*__P/i\ +#ifndef __P +'\ + -e '/^#define[ ]*__P/a\ +#endif +' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base + fi +done + +# The Solaris math.h defines struct exception, which conflicts with +# the class exception defined in the C++ file std/stdexcept.h. We +# redefine it to __math_exception. This is not a great fix, but I +# haven't been able to think of anything better. +file=math.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e '/struct exception/i\ +#ifdef __cplusplus\ +#define exception __math_exception\ +#endif'\ + -e '/struct exception/a\ +#ifdef __cplusplus\ +#undef exception\ +#endif' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >/dev/null 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +echo 'Removing unneeded directories:' +cd $LIB +files=`find . -type d -print | sort -r` +for file in $files; do + rmdir $LIB/$file > /dev/null 2>&1 +done + +if $LINKS; then + echo 'Making internal symbolic non-directory links' + cd ${INPUT} + files=`find . -type l -print` + for file in $files; do + dest=`ls -ld $file | sed -n 's/.*-> //p'` + if expr "$dest" : '[^/].*' > /dev/null; then + target=${LIB}/`echo $file | sed "s|[^/]*\$|$dest|"` + if [ -f $target ]; then + ln -s $dest ${LIB}/$file >/dev/null 2>&1 + fi + fi + done +fi + +cd ${ORIG_DIR} + +echo 'Replacing <sys/byteorder.h>' +if [ \! -d $LIB/sys ]; then + mkdir $LIB/sys +fi +rm -f ${LIB}/sys/byteorder.h +cat <<'__EOF__' >${LIB}/sys/byteorder.h +#ifndef _SYS_BYTEORDER_H +#define _SYS_BYTEORDER_H + +/* Functions to convert `short' and `long' quantities from host byte order + to (internet) network byte order (i.e. big-endian). + + Written by Ron Guilmette (rfg@ncd.com). + + This isn't actually used by GCC. It is installed by fixinc.svr4. + + For big-endian machines these functions are essentially no-ops. + + For little-endian machines, we define the functions using specialized + asm sequences in cases where doing so yields better code (e.g. i386). */ + +#if !defined (__GNUC__) && !defined (__GNUG__) +#error You lose! This file is only useful with GNU compilers. +#endif + +#ifndef __BYTE_ORDER__ +/* Byte order defines. These are as defined on UnixWare 1.1, but with + double underscores added at the front and back. */ +#define __LITTLE_ENDIAN__ 1234 +#define __BIG_ENDIAN__ 4321 +#define __PDP_ENDIAN__ 3412 +#endif + +#ifdef __STDC__ +static __inline__ unsigned long htonl (unsigned long); +static __inline__ unsigned short htons (unsigned int); +static __inline__ unsigned long ntohl (unsigned long); +static __inline__ unsigned short ntohs (unsigned int); +#endif /* defined (__STDC__) */ + +#if defined (__i386__) + +#ifndef __BYTE_ORDER__ +#define __BYTE_ORDER__ __LITTLE_ENDIAN__ +#endif + +/* Convert a host long to a network long. */ + +/* We must use a new-style function definition, so that this will also + be valid for C++. */ +static __inline__ unsigned long +htonl (unsigned long __arg) +{ + register unsigned long __result; + + __asm__ ("xchg%B0 %b0,%h0\n\ + ror%L0 $16,%0\n\ + xchg%B0 %b0,%h0" : "=q" (__result) : "0" (__arg)); + return __result; +} + +/* Convert a host short to a network short. */ + +static __inline__ unsigned short +htons (unsigned int __arg) +{ + register unsigned short __result; + + __asm__ ("xchg%B0 %b0,%h0" : "=q" (__result) : "0" (__arg)); + return __result; +} + +#elif ((defined (__i860__) && !defined (__i860_big_endian__)) \ + || defined (__ns32k__) || defined (__vax__) \ + || defined (__spur__) || defined (__arm__)) + +#ifndef __BYTE_ORDER__ +#define __BYTE_ORDER__ __LITTLE_ENDIAN__ +#endif + +/* For other little-endian machines, using C code is just as efficient as + using assembly code. */ + +/* Convert a host long to a network long. */ + +static __inline__ unsigned long +htonl (unsigned long __arg) +{ + register unsigned long __result; + + __result = (__arg >> 24) & 0x000000ff; + __result |= (__arg >> 8) & 0x0000ff00; + __result |= (__arg << 8) & 0x00ff0000; + __result |= (__arg << 24) & 0xff000000; + return __result; +} + +/* Convert a host short to a network short. */ + +static __inline__ unsigned short +htons (unsigned int __arg) +{ + register unsigned short __result; + + __result = (__arg << 8) & 0xff00; + __result |= (__arg >> 8) & 0x00ff; + return __result; +} + +#else /* must be a big-endian machine */ + +#ifndef __BYTE_ORDER__ +#define __BYTE_ORDER__ __BIG_ENDIAN__ +#endif + +/* Convert a host long to a network long. */ + +static __inline__ unsigned long +htonl (unsigned long __arg) +{ + return __arg; +} + +/* Convert a host short to a network short. */ + +static __inline__ unsigned short +htons (unsigned int __arg) +{ + return __arg; +} + +#endif /* big-endian */ + +/* Convert a network long to a host long. */ + +static __inline__ unsigned long +ntohl (unsigned long __arg) +{ + return htonl (__arg); +} + +/* Convert a network short to a host short. */ + +static __inline__ unsigned short +ntohs (unsigned int __arg) +{ + return htons (__arg); +} + +__EOF__ + +if [ -r ${INPUT}/sys/byteorder.h ]; then + if grep BYTE_ORDER ${INPUT}/sys/byteorder.h >/dev/null 2>/dev/null; then + cat <<'__EOF__' >>${LIB}/sys/byteorder.h +#ifndef BYTE_ORDER +#define LITTLE_ENDIAN __LITTLE_ENDIAN__ +#define BIG_ENDIAN __BIG_ENDIAN__ +#define PDP_ENDIAN __PDP_ENDIAN__ +#define BYTE_ORDER __BYTE_ORDER__ +#endif + +__EOF__ + fi +fi + +cat <<'__EOF__' >>${LIB}/sys/byteorder.h +#endif /* !defined (_SYS_BYTEORDER_H) */ +__EOF__ + +chmod a+r ${LIB}/sys/byteorder.h + +exit 0 + diff --git a/contrib/gcc/fixinc.winnt b/contrib/gcc/fixinc.winnt new file mode 100644 index 000000000000..915ac723b85e --- /dev/null +++ b/contrib/gcc/fixinc.winnt @@ -0,0 +1,232 @@ +#! sh +# +# fixinc.winnt -- Install modified versions of Windows NT system include +# files. +# +# Based on fixinc.sco script by Ian Lance Taylor (ian@airs.com)). +# Modifications by Douglas Rupp (drupp@cs.washington.edu) +# +# This file is part of GNU CC. +# +# GNU CC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU CC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU CC; see the file COPYING. If not, write to +# the Free Software Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. +# +# This script munges the native include files provided with Windows NT +# 3.5 SDK systems so as to provide a reasonable namespace when +# compiling with gcc. The header files by default do not +# provide many essential definitions and declarations if +# __STDC__ is 1. This script modifies the header files to check +# for __STRICT_ANSI__ being defined instead. Once munged, the +# resulting new system include files are placed in a directory +# that GNU C will search *before* searching the Include +# directory. +# +# See README-fixinc for more information. + +ORIG_DIR=`pwd` + +# Directory containing the original header files. +cd $2; SEDFILE=`${PWDCMD-pwd}`/fixinc-nt.sed +echo $SEDFILE +if [ ! -f $SEDFILE ] +then echo fixincludes: sed script 'fixinc-nt.sed' not found +exit 1 +fi +echo 'Using sed script: ' ${SEDFILE} + +cd $ORIG_DIR + +INPUT=${INCLUDE} +echo 'Using the Include environment variable to find header files to fix' + +# Fail if no arg to specify a directory for the output. +if [ x$1 = x ] +then echo fixincludes: no output directory specified +exit 1 +fi + +# Directory in which to store the results. +LIB=${1?"fixincludes: output directory not specified"} + +# Make sure it exists. +if [ ! -d $LIB ]; then + mkdir $LIB || exit 1 +fi + +ORIG_DIR=`pwd` + +# Make LIB absolute if it is relative. +# Don't do this if not necessary, since may screw up automounters. +case $LIB in +/*) + ;; +*) + cd $LIB; LIB=`${PWDCMD-pwd}` + ;; +esac + +echo 'Building fixincludes in ' ${LIB} + +# Determine whether this filesystem has symbolic links. +if ln -s X $LIB/ShouldNotExist 2>NUL; then + rm -f $LIB/ShouldNotExist + LINKS=true +else + LINKS=false +fi + +echo 'Making directories:' +cd ${INPUT} +if $LINKS; then + files=`ls -LR | sed -n s/:$//p` +else + files=`find . -type d -print | sed '/^.$/d'` +fi +for file in $files; do + rm -rf $LIB/$file + if [ ! -d $LIB/$file ] + then mkdir $LIB/$file + fi +done + +# treetops gets an alternating list +# of old directories to copy +# and the new directories to copy to. +treetops="${INPUT} ${LIB}" + +set - $treetops +while [ $# != 0 ]; do + # $1 is an old directory to copy, and $2 is the new directory to copy to. + echo "Finding header files in $1:" + cd ${INPUT} + cd $1 + files=`find . -name '*.[hH]' -type f -print` + echo 'Checking header files:' + for file in $files; do + echo $file + if egrep "!__STDC__" $file >NUL; then + if [ -r $file ]; then + cp $file $2/$file >NUL 2>&1 || echo "Can't copy $file" + chmod +w,a+r $2/$file + +# The following have been removed from the sed command below +# because it is more useful to leave these things in. +# The only reason to remove them was for -pedantic, +# which isn't much of a reason. -- rms. +# /^[ ]*#[ ]*ident/d + + sed -e ' + s/!__STDC__/!defined (__STRICT_ANSI__)/g + ' $2/$file > $2/$file.sed + mv $2/$file.sed $2/$file + if cmp $file $2/$file >NUL 2>&1; then + rm $2/$file + else + echo Fixed $file + fi + fi + fi + done + shift; shift +done + +# Fix first broken decl of getcwd present on some svr4 systems. + +file=direct.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e 's/getcwd(char \*, int)/getcwd(char *, size_t)/' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >NUL 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +file=rpcndr.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e 's/Format\[\]/Format\[1\]/' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >NUL 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +file=winnt.h +base=`basename $file` +if [ -r ${LIB}/$file ]; then + file_to_fix=${LIB}/$file +else + if [ -r ${INPUT}/$file ]; then + file_to_fix=${INPUT}/$file + else + file_to_fix="" + fi +fi +if [ \! -z "$file_to_fix" ]; then + echo Checking $file_to_fix + sed -e ' + s/^#if !defined (__cplusplus)/#if 0/ + s/^#define DECLSPEC_IMPORT __declspec(dllimport)/#define DECLSPEC_IMPORT/ + ' $file_to_fix > /tmp/$base + if cmp $file_to_fix /tmp/$base >NUL 2>&1; then \ + true + else + echo Fixed $file_to_fix + rm -f ${LIB}/$file + cp /tmp/$base ${LIB}/$file + chmod a+r ${LIB}/$file + fi + rm -f /tmp/$base +fi + +echo 'Removing unneeded directories:' +cd $LIB +files=`find . -type d -print | sort -r` +for file in $files; do + rmdir $LIB/$file > NUL 2>&1 +done + +exit 0 diff --git a/contrib/gcc/fixinc.wrap b/contrib/gcc/fixinc.wrap new file mode 100755 index 000000000000..406c87e9c03b --- /dev/null +++ b/contrib/gcc/fixinc.wrap @@ -0,0 +1,86 @@ +#! /bin/sh +# Create wrappers for include files instead of replacing them. +# +# This script is designed for systems whose include files can be fixed +# by creating small wrappers around them. +# An advantage of this method is that if the system include files are changed +# (e.g. by OS upgrade), you need not re-run fixincludes. +# +# See README-fixinc for more information. + +# Directory containing the original header files. +# (This was named INCLUDES, but that conflicts with a name in Makefile.in.) +INPUT=${2-${INPUT-/usr/include}} + +# Directory in which to store the results. +LIB=${1?"fixincludes: output directory not specified"} + +# Make sure it exists. +if [ ! -d $LIB ]; then + mkdir $LIB || exit 1 +fi + +echo Building fixed headers in ${LIB} + +# Some math.h files define struct exception, which conflicts with +# the class exception defined in the C++ file std/stdexcept.h. We +# redefine it to __math_exception. This is not a great fix, but I +# haven't been able to think of anything better. +file=math.h +if [ -r $INPUT/$file ]; then + echo Checking $INPUT/$file + if grep 'struct exception' $INPUT/$file >/dev/null + then + echo Fixed $file + rm -f $LIB/$file + cat <<'__EOF__' >$LIB/$file +#ifndef _MATH_H_WRAPPER +#ifdef __cplusplus +# define exception __math_exception +#endif +#include_next <math.h> +#ifdef __cplusplus +# undef exception +#endif +#define _MATH_H_WRAPPER +#endif /* _MATH_H_WRAPPER */ +__EOF__ + # Define _MATH_H_WRAPPER at the end of the wrapper, not the start, + # so that if #include_next gets another instance of the wrapper, + # this will follow the #include_next chain until we arrive at + # the real <math.h>. + chmod a+r $LIB/$file + fi +fi + +# Avoid the definition of the bool type in the Solaris 2.x curses.h when using +# g++, since it's now an official type in the C++ language. +file=curses.h +if [ -r $INPUT/$file ]; then + echo Checking $INPUT/$file + w='[ ]' + if grep "typedef$w$w*char$w$w*bool$w*;" $INPUT/$file >/dev/null + then + echo Fixed $file + rm -f $LIB/$file + cat <<'__EOF__' >$LIB/$file +#ifndef _CURSES_H_WRAPPER +#ifdef __cplusplus +# define bool __curses_bool_t +#endif +#include_next <curses.h> +#ifdef __cplusplus +# undef bool +#endif +#define _CURSES_H_WRAPPER +#endif /* _CURSES_H_WRAPPER */ +__EOF__ + # Define _CURSES_H_WRAPPER at the end of the wrapper, not the start, + # so that if #include_next gets another instance of the wrapper, + # this will follow the #include_next chain until we arrive at + # the real <curses.h>. + chmod a+r $LIB/$file + fi +fi + +exit 0 diff --git a/contrib/gcc/flags.h b/contrib/gcc/flags.h index a7c1b7e2c151..b69704ce8408 100644 --- a/contrib/gcc/flags.h +++ b/contrib/gcc/flags.h @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/flags.h,v 1.4 1999/10/26 08:45:23 obrien Exp $ */ /* Name of the input .c file being compiled. */ extern char *main_input_filename; diff --git a/contrib/gcc/function.c b/contrib/gcc/function.c index cd8f2490f165..9d9c70713ecb 100644 --- a/contrib/gcc/function.c +++ b/contrib/gcc/function.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/function.c,v 1.6.2.1 2000/07/04 06:01:24 obrien Exp $ */ /* This file handles the generation of rtl code from tree structure diff --git a/contrib/gcc/gcc.1 b/contrib/gcc/gcc.1 index d81841d4308c..60f307812a47 100644 --- a/contrib/gcc/gcc.1 +++ b/contrib/gcc/gcc.1 @@ -1,4 +1,4 @@ -.\" $FreeBSD$ +.\" $FreeBSD: src/contrib/gcc/gcc.1,v 1.15 1999/10/26 08:57:00 obrien Exp $ .\" Copyright (c) 1991, 1992, 1993, 1994 Free Software Foundation -*-Text-*- .\" See section COPYING for conditions for redistribution .\" diff --git a/contrib/gcc/gcc.c b/contrib/gcc/gcc.c index 3128db0d88de..54260fa4a50b 100644 --- a/contrib/gcc/gcc.c +++ b/contrib/gcc/gcc.c @@ -21,7 +21,7 @@ Boston, MA 02111-1307, USA. This paragraph is here to try to keep Sun CC from dying. The number of chars here seems crucial!!!! */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/gcc.c,v 1.17 2000/03/09 10:11:08 obrien Exp $ */ /* This program is the user interface to the C compiler and possibly to other compilers. It is used because compilation is a complicated procedure diff --git a/contrib/gcc/ginclude/stdarg.h b/contrib/gcc/ginclude/stdarg.h index e3842f78639f..8f54c27693a5 100644 --- a/contrib/gcc/ginclude/stdarg.h +++ b/contrib/gcc/ginclude/stdarg.h @@ -3,7 +3,7 @@ actual type **after default promotions**. Thus, va_arg (..., short) is not valid. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/ginclude/stdarg.h,v 1.4 1999/10/16 07:12:34 obrien Exp $ */ #ifndef _STDARG_H #ifndef _ANSI_STDARG_H_ diff --git a/contrib/gcc/ginclude/stddef.h b/contrib/gcc/ginclude/stddef.h index 11093912068a..744ec7bcf799 100644 --- a/contrib/gcc/ginclude/stddef.h +++ b/contrib/gcc/ginclude/stddef.h @@ -1,4 +1,4 @@ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/ginclude/stddef.h,v 1.3 1999/10/13 15:55:31 obrien Exp $ */ #if (!defined(_STDDEF_H) && !defined(_STDDEF_H_) && !defined(_ANSI_STDDEF_H) \ && !defined(__STDDEF_H__)) \ diff --git a/contrib/gcc/ginclude/varargs.h b/contrib/gcc/ginclude/varargs.h index 65191402ea5a..fa1639ac3257 100644 --- a/contrib/gcc/ginclude/varargs.h +++ b/contrib/gcc/ginclude/varargs.h @@ -1,6 +1,6 @@ /* Record that this is varargs.h; this turns off stdarg.h. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/ginclude/varargs.h,v 1.4 1999/10/16 07:12:34 obrien Exp $ */ #ifndef _VARARGS_H #define _VARARGS_H diff --git a/contrib/gcc/invoke.texi b/contrib/gcc/invoke.texi index 962a7073535a..53a4714ece55 100644 --- a/contrib/gcc/invoke.texi +++ b/contrib/gcc/invoke.texi @@ -2,7 +2,7 @@ @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. -@c $FreeBSD$ +@c $FreeBSD: src/contrib/gcc/invoke.texi,v 1.6.2.1 2000/07/04 06:01:25 obrien Exp $ @node Invoking GCC @chapter GCC Command Options diff --git a/contrib/gcc/libgcc2.c b/contrib/gcc/libgcc2.c index 6618dfe3cf1d..aaf480fe2fd9 100644 --- a/contrib/gcc/libgcc2.c +++ b/contrib/gcc/libgcc2.c @@ -26,7 +26,7 @@ Boston, MA 02111-1307, USA. */ This exception does not however invalidate any other reasons why the executable file might be covered by the GNU General Public License. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/libgcc2.c,v 1.4 1999/10/27 09:45:47 obrien Exp $ */ /* It is incorrect to include config.h here, because this file is being compiled for the target, and hence definitions concerning only the host diff --git a/contrib/gcc/objc/NXConstStr.h b/contrib/gcc/objc/NXConstStr.h new file mode 100644 index 000000000000..c9799544a029 --- /dev/null +++ b/contrib/gcc/objc/NXConstStr.h @@ -0,0 +1,44 @@ +/* Interface for the NXConstantString class for Objective-C. + Copyright (C) 1995 Free Software Foundation, Inc. + Contributed by Pieter J. Schoenmakers <tiggr@es.ele.tue.nl> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#ifndef __nxconstantstring_INCLUDE_GNU +#define __nxconstantstring_INCLUDE_GNU + +#include "objc/Object.h" + +@interface NXConstantString: Object +{ + char *c_string; + unsigned int len; +} + +-(const char *) cString; +-(unsigned int) length; + +@end + +#endif diff --git a/contrib/gcc/objc/NXConstStr.m b/contrib/gcc/objc/NXConstStr.m new file mode 100644 index 000000000000..4d2f3e1d7fc0 --- /dev/null +++ b/contrib/gcc/objc/NXConstStr.m @@ -0,0 +1,42 @@ +/* Implementation of the NXConstantString class for Objective-C. + Copyright (C) 1995 Free Software Foundation, Inc. + Contributed by Pieter J. Schoenmakers <tiggr@es.ele.tue.nl> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#include "objc/NXConstStr.h" + +@implementation NXConstantString + +-(const char *) cString +{ + return (c_string); +} /* -cString */ + +-(unsigned int) length +{ + return (len); +} /* -length */ + +@end diff --git a/contrib/gcc/objc/Object.h b/contrib/gcc/objc/Object.h new file mode 100644 index 000000000000..a762acc3f7db --- /dev/null +++ b/contrib/gcc/objc/Object.h @@ -0,0 +1,124 @@ +/* Interface for the Object class for Objective-C. + Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled + with GCC to produce an executable, this does not cause the resulting + executable to be covered by the GNU General Public License. This + exception does not however invalidate any other reasons why the + executable file might be covered by the GNU General Public License. */ + +#ifndef __object_INCLUDE_GNU +#define __object_INCLUDE_GNU + +#include <objc/objc.h> +#include <objc/typedstream.h> + +/* + * All classes are derived from Object. As such, + * this is the overhead tacked onto those objects. + */ +@interface Object +{ + Class isa; /* A pointer to the instance's class structure */ +} + + /* Initializing classes and instances */ ++ initialize; +- init; + + /* Creating, freeing, and copying instances */ ++ new; ++ alloc; +- free; +- copy; +- shallowCopy; +- deepen; +- deepCopy; + + /* Identifying classes */ +- (Class)class; +- (Class)superClass; +- (MetaClass)metaClass; +- (const char *)name; + + /* Identifying and comparing objects */ +- self; +- (unsigned int)hash; +- (BOOL)isEqual:anObject; +- (int)compare:anotherObject; + + /* Testing object type */ +- (BOOL)isMetaClass; +- (BOOL)isClass; +- (BOOL)isInstance; + + /* Testing inheritance relationships */ +- (BOOL)isKindOf:(Class)aClassObject; +- (BOOL)isMemberOf:(Class)aClassObject; +- (BOOL)isKindOfClassNamed:(const char *)aClassName; +- (BOOL)isMemberOfClassNamed:(const char *)aClassName; + + /* Testing class functionality */ ++ (BOOL)instancesRespondTo:(SEL)aSel; +- (BOOL)respondsTo:(SEL)aSel; + + /* Testing protocol conformance */ +- (BOOL)conformsTo:(Protocol*)aProtocol; + + /* Introspection */ ++ (IMP)instanceMethodFor:(SEL)aSel; +- (IMP)methodFor:(SEL)aSel; ++ (struct objc_method_description *)descriptionForInstanceMethod:(SEL)aSel; +- (struct objc_method_description *)descriptionForMethod:(SEL)aSel; + + /* Sending messages determined at run time */ +- perform:(SEL)aSel; +- perform:(SEL)aSel with:anObject; +- perform:(SEL)aSel with:anObject1 with:anObject2; + + /* Forwarding */ +- (retval_t)forward:(SEL)aSel :(arglist_t)argFrame; +- (retval_t)performv:(SEL)aSel :(arglist_t)argFrame; + + /* Posing */ ++ poseAs:(Class)aClassObject; +- (Class)transmuteClassTo:(Class)aClassObject; + + /* Enforcing intentions */ +- subclassResponsibility:(SEL)aSel; +- notImplemented:(SEL)aSel; +- shouldNotImplement:(SEL)aSel; + + /* Error handling */ +- doesNotRecognize:(SEL)aSel; +- error:(const char *)aString, ...; + + /* Archiving */ ++ (int)version; ++ setVersion:(int)aVersion; ++ (int)streamVersion: (TypedStream*)aStream; + +- read: (TypedStream*)aStream; +- write: (TypedStream*)aStream; +- awake; + +@end + +#endif diff --git a/contrib/gcc/objc/Object.m b/contrib/gcc/objc/Object.m new file mode 100644 index 000000000000..64b52f483687 --- /dev/null +++ b/contrib/gcc/objc/Object.m @@ -0,0 +1,387 @@ +/* The implementation of class Object for Objective-C. + Copyright (C) 1993, 1994, 1995, 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled + with GCC to produce an executable, this does not cause the resulting + executable to be covered by the GNU General Public License. This + exception does not however invalidate any other reasons why the + executable file might be covered by the GNU General Public License. */ + +#include <stdarg.h> +#include "objc/Object.h" +#include "objc/Protocol.h" +#include "objc/objc-api.h" + +extern int errno; + +#define MAX_CLASS_NAME_LEN 256 + +@implementation Object + ++ initialize +{ + return self; +} + +- init +{ + return self; +} + ++ new +{ + return [[self alloc] init]; +} + ++ alloc +{ + return class_create_instance(self); +} + +- free +{ + return object_dispose(self); +} + +- copy +{ + return [[self shallowCopy] deepen]; +} + +- shallowCopy +{ + return object_copy(self); +} + +- deepen +{ + return self; +} + +- deepCopy +{ + return [self copy]; +} + +- (Class)class +{ + return object_get_class(self); +} + +- (Class)superClass +{ + return object_get_super_class(self); +} + +- (MetaClass)metaClass +{ + return object_get_meta_class(self); +} + +- (const char *)name +{ + return object_get_class_name(self); +} + +- self +{ + return self; +} + +- (unsigned int)hash +{ + return (size_t)self; +} + +- (BOOL)isEqual:anObject +{ + return self==anObject; +} + +- (int)compare:anotherObject; +{ + if ([self isEqual:anotherObject]) + return 0; + // Ordering objects by their address is pretty useless, + // so subclasses should override this is some useful way. + else if (self > anotherObject) + return 1; + else + return -1; +} + +- (BOOL)isMetaClass +{ + return NO; +} + +- (BOOL)isClass +{ + return object_is_class(self); +} + +- (BOOL)isInstance +{ + return object_is_instance(self); +} + +- (BOOL)isKindOf:(Class)aClassObject +{ + Class class; + + for (class = self->isa; class!=Nil; class = class_get_super_class(class)) + if (class==aClassObject) + return YES; + return NO; +} + +- (BOOL)isMemberOf:(Class)aClassObject +{ + return self->isa==aClassObject; +} + +- (BOOL)isKindOfClassNamed:(const char *)aClassName +{ + Class class; + + if (aClassName!=NULL) + for (class = self->isa; class!=Nil; class = class_get_super_class(class)) + if (!strcmp(class_get_class_name(class), aClassName)) + return YES; + return NO; +} + +- (BOOL)isMemberOfClassNamed:(const char *)aClassName +{ + return ((aClassName!=NULL) + &&!strcmp(class_get_class_name(self->isa), aClassName)); +} + ++ (BOOL)instancesRespondTo:(SEL)aSel +{ + return class_get_instance_method(self, aSel)!=METHOD_NULL; +} + +- (BOOL)respondsTo:(SEL)aSel +{ + return ((object_is_instance(self) + ?class_get_instance_method(self->isa, aSel) + :class_get_class_method(self->isa, aSel))!=METHOD_NULL); +} + ++ (IMP)instanceMethodFor:(SEL)aSel +{ + return method_get_imp(class_get_instance_method(self, aSel)); +} + +// Indicates if the receiving class or instance conforms to the given protocol +// not usually overridden by subclasses +// +// Modified 9/5/94 to always search the class object's protocol list, rather +// than the meta class. + ++ (BOOL) conformsTo: (Protocol*)aProtocol +{ + int i; + struct objc_protocol_list* proto_list; + id parent; + + for (proto_list = ((Class)self)->protocols; + proto_list; proto_list = proto_list->next) + { + for (i=0; i < proto_list->count; i++) + { + if ([proto_list->list[i] conformsTo: aProtocol]) + return YES; + } + } + + if ((parent = [self superClass])) + return [parent conformsTo: aProtocol]; + else + return NO; +} + +- (BOOL) conformsTo: (Protocol*)aProtocol +{ + return [[self class] conformsTo:aProtocol]; +} + +- (IMP)methodFor:(SEL)aSel +{ + return (method_get_imp(object_is_instance(self) + ?class_get_instance_method(self->isa, aSel) + :class_get_class_method(self->isa, aSel))); +} + ++ (struct objc_method_description *)descriptionForInstanceMethod:(SEL)aSel +{ + return ((struct objc_method_description *) + class_get_instance_method(self, aSel)); +} + +- (struct objc_method_description *)descriptionForMethod:(SEL)aSel +{ + return ((struct objc_method_description *) + (object_is_instance(self) + ?class_get_instance_method(self->isa, aSel) + :class_get_class_method(self->isa, aSel))); +} + +- perform:(SEL)aSel +{ + IMP msg = objc_msg_lookup(self, aSel); + if (!msg) + return [self error:"invalid selector passed to %s", sel_get_name(_cmd)]; + return (*msg)(self, aSel); +} + +- perform:(SEL)aSel with:anObject +{ + IMP msg = objc_msg_lookup(self, aSel); + if (!msg) + return [self error:"invalid selector passed to %s", sel_get_name(_cmd)]; + return (*msg)(self, aSel, anObject); +} + +- perform:(SEL)aSel with:anObject1 with:anObject2 +{ + IMP msg = objc_msg_lookup(self, aSel); + if (!msg) + return [self error:"invalid selector passed to %s", sel_get_name(_cmd)]; + return (*msg)(self, aSel, anObject1, anObject2); +} + +- (retval_t)forward:(SEL)aSel :(arglist_t)argFrame +{ + return (retval_t)[self doesNotRecognize: aSel]; +} + +- (retval_t)performv:(SEL)aSel :(arglist_t)argFrame +{ + return objc_msg_sendv(self, aSel, argFrame); +} + ++ poseAs:(Class)aClassObject +{ + return class_pose_as(self, aClassObject); +} + +- (Class)transmuteClassTo:(Class)aClassObject +{ + if (object_is_instance(self)) + if (class_is_class(aClassObject)) + if (class_get_instance_size(aClassObject)==class_get_instance_size(isa)) + if ([self isKindOf:aClassObject]) + { + Class old_isa = isa; + isa = aClassObject; + return old_isa; + } + return nil; +} + +- subclassResponsibility:(SEL)aSel +{ + return [self error:"subclass should override %s", sel_get_name(aSel)]; +} + +- notImplemented:(SEL)aSel +{ + return [self error:"method %s not implemented", sel_get_name(aSel)]; +} + +- shouldNotImplement:(SEL)aSel +{ + return [self error:"%s should not implement %s", + object_get_class_name(self), sel_get_name(aSel)]; +} + +- doesNotRecognize:(SEL)aSel +{ + return [self error:"%s does not recognize %s", + object_get_class_name(self), sel_get_name(aSel)]; +} + +#ifdef __alpha__ +extern size_t strlen(const char*); +#endif + +- error:(const char *)aString, ... +{ +#define FMT "error: %s (%s)\n%s\n" + char fmt[(strlen((char*)FMT)+strlen((char*)object_get_class_name(self)) + +((aString!=NULL)?strlen((char*)aString):0)+8)]; + va_list ap; + + sprintf(fmt, FMT, object_get_class_name(self), + object_is_instance(self)?"instance":"class", + (aString!=NULL)?aString:""); + va_start(ap, aString); + objc_verror(self, OBJC_ERR_UNKNOWN, fmt, ap); + va_end(ap); + return nil; +#undef FMT +} + ++ (int)version +{ + return class_get_version(self); +} + ++ setVersion:(int)aVersion +{ + class_set_version(self, aVersion); + return self; +} + ++ (int)streamVersion: (TypedStream*)aStream +{ + if (aStream->mode == OBJC_READONLY) + return objc_get_stream_class_version (aStream, self); + else + return class_get_version (self); +} + +// These are used to write or read the instance variables +// declared in this particular part of the object. Subclasses +// should extend these, by calling [super read/write: aStream] +// before doing their own archiving. These methods are private, in +// the sense that they should only be called from subclasses. + +- read: (TypedStream*)aStream +{ + // [super read: aStream]; + return self; +} + +- write: (TypedStream*)aStream +{ + // [super write: aStream]; + return self; +} + +- awake +{ + // [super awake]; + return self; +} + +@end diff --git a/contrib/gcc/objc/Protocol.h b/contrib/gcc/objc/Protocol.h new file mode 100644 index 000000000000..c7464cf17a9a --- /dev/null +++ b/contrib/gcc/objc/Protocol.h @@ -0,0 +1,58 @@ +/* Declare the class Protocol for Objective C programs. + Copyright (C) 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#ifndef __Protocol_INCLUDE_GNU +#define __Protocol_INCLUDE_GNU + +#include "objc/Object.h" + +@interface Protocol : Object +{ +@private + char *protocol_name; + struct objc_protocol_list *protocol_list; + struct objc_method_description_list *instance_methods, *class_methods; +} + +/* Obtaining attributes intrinsic to the protocol */ + +- (const char *)name; + +/* Testing protocol conformance */ + +- (BOOL) conformsTo: (Protocol *)aProtocolObject; + +/* Looking up information specific to a protocol */ + +- (struct objc_method_description *) descriptionForInstanceMethod:(SEL)aSel; +- (struct objc_method_description *) descriptionForClassMethod:(SEL)aSel; + +@end + + + + +#endif __Protocol_INCLUDE_GNU diff --git a/contrib/gcc/objc/Protocol.m b/contrib/gcc/objc/Protocol.m new file mode 100644 index 000000000000..43ba44eaf4f7 --- /dev/null +++ b/contrib/gcc/objc/Protocol.m @@ -0,0 +1,128 @@ +/* This file contains the implementation of class Protocol. + Copyright (C) 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#include "objc/Protocol.h" +#include "objc/objc-api.h" + +/* Method description list */ +struct objc_method_description_list { + int count; + struct objc_method_description list[1]; +}; + + +@implementation Protocol +{ +@private + char *protocol_name; + struct objc_protocol_list *protocol_list; + struct objc_method_description_list *instance_methods, *class_methods; +} + +/* Obtaining attributes intrinsic to the protocol */ + +- (const char *)name +{ + return protocol_name; +} + +/* Testing protocol conformance */ + +- (BOOL) conformsTo: (Protocol *)aProtocolObject +{ + int i; + struct objc_protocol_list* proto_list; + + if (!strcmp(aProtocolObject->protocol_name, self->protocol_name)) + return YES; + + for (proto_list = protocol_list; proto_list; proto_list = proto_list->next) + { + for (i=0; i < proto_list->count; i++) + { + if ([proto_list->list[i] conformsTo: aProtocolObject]) + return YES; + } + } + + return NO; +} + +/* Looking up information specific to a protocol */ + +- (struct objc_method_description *) descriptionForInstanceMethod:(SEL)aSel +{ + int i; + struct objc_protocol_list* proto_list; + const char* name = sel_get_name (aSel); + struct objc_method_description *result; + + for (i = 0; i < instance_methods->count; i++) + { + if (!strcmp ((char*)instance_methods->list[i].name, name)) + return &(instance_methods->list[i]); + } + + for (proto_list = protocol_list; proto_list; proto_list = proto_list->next) + { + for (i=0; i < proto_list->count; i++) + { + if ((result = [proto_list->list[i] + descriptionForInstanceMethod: aSel])) + return result; + } + } + + return NULL; +} + +- (struct objc_method_description *) descriptionForClassMethod:(SEL)aSel; +{ + int i; + struct objc_protocol_list* proto_list; + const char* name = sel_get_name (aSel); + struct objc_method_description *result; + + for (i = 0; i < class_methods->count; i++) + { + if (!strcmp ((char*)class_methods->list[i].name, name)) + return &(class_methods->list[i]); + } + + for (proto_list = protocol_list; proto_list; proto_list = proto_list->next) + { + for (i=0; i < proto_list->count; i++) + { + if ((result = [proto_list->list[i] + descriptionForClassMethod: aSel])) + return result; + } + } + + return NULL; +} + +@end diff --git a/contrib/gcc/objc/README.threads b/contrib/gcc/objc/README.threads new file mode 100644 index 000000000000..2cafb4ea7cf6 --- /dev/null +++ b/contrib/gcc/objc/README.threads @@ -0,0 +1,50 @@ +============================================================================== +README - Wed Nov 29 15:16:24 EST 1995 +------------------------------------------------------------------------------ + +Limited documentation is available in the THREADS file. + +This version has been tested on Sun Solaris, SGI Irix, and Windows NT. +It should also work on any single threaded system. + +Thanks go to the following people for help test and debug the library: + + Scott Christley, scottc@ocbi.com + Andrew McCallum, mccallum@cs.rochester.edu + +galen +gchunt@cs.rochester.edu + +Any questions, bug reports, etc should be directed to: + +Scott Christley, scottc@ocbi.com + +Please do not bug Galen with email as he no longer supports the code. + +============================================================================== +Changes from prior releases (in revered chronological order): +------------------------------------------------------------------------------ + +* Fixed bug in copy part of sarray_realloc. I had an < which should + have been <=. (Bug report from Scott). + +------------------------------------------------------------------------------ + +* Support for DEC OSF/1 is definitely broken. My programs always + seg-fault when I link with libpthreads.a. + +* Thread id's are no longer int's, but are instead of type + _objc_thread_t which is typedef'ed from a void *. An invalid thread + id is denoted by NULL and not -1 as before. + +------------------------------------------------------------------------------ + +* Renamed thread-winnt.c to thread-win32.c to better reflect support + for the API on both Windows NT and Windows 95 platforms. + (Who knows, maybe even Win32s :-). + +* Fixed bugs in Win32 support as per report from Scott Christley. + +* Fixed bug in sarray_get as per report from Scott Christley. + + diff --git a/contrib/gcc/objc/THREADS b/contrib/gcc/objc/THREADS new file mode 100644 index 000000000000..9dfbbed97af2 --- /dev/null +++ b/contrib/gcc/objc/THREADS @@ -0,0 +1,374 @@ +This file describes in little detail the modifications to the +Objective-C runtime needed to make it thread safe. + +First off, kudos to Galen Hunt who is the author of this great work. + +If you have an comments or just want to know where to +send me money to express your undying gratitude for threading the +Objective-C runtime you can reach Galen at: + + gchunt@cs.rochester.edu + +Any questions, comments, bug reports, etc. should send email either to the +GCC bug account or to: + + Scott Christley <scottc@net-community.com> + +* Sarray Threading: + +The most critical component of the Objective-C runtime is the sparse array +structure (sarray). Sarrays store object selectors and implementations. +Following in the tradition of the Objective-C runtime, my threading +support assumes that fast message dispatching is far more important +than *ANY* and *ALL* other operations. The message dispatching thus +uses *NO* locks on any kind. In fact, if you look in sarray.h, you +will notice that the message dispatching has not been modified. +Instead, I have modified the sarray management functions so that all +updates to the sarray data structure can be made in parallel will +message dispatching. + +To support concurrent message dispatching, no dynamically allocated +sarray data structures are freed while more than one thread is +operational. Sarray data structures that are no longer in use are +kept in a linked list of garbage and are released whenever the program +is operating with a single thread. The programmer can also flush the +garbage list by calling sarray_remove_garbage when the programmer can +ensure that no message dispatching is taking place concurrently. The +amount of un-reclaimed sarray garbage should normally be extremely +small in a real program as sarray structures are freed only when using +the "poseAs" functionality and early in program initialization, which +normally occurs while the program is single threaded. + +****************************************************************************** +* Static Variables: + +The following variables are either statically or globally defined. This list +does not include variables which are internal to implementation dependent +versions of thread-*.c. + +The following threading designations are used: + SAFE : Implicitly thread safe. + SINGLE : Must only be used in single thread mode. + MUTEX : Protected by single global mutex objc_runtime_mutex. + UNUSED : Not used in the runtime. + +Variable Name: Usage: Defined: Also used in: +=========================== ====== ============ ===================== +__objc_class_hash MUTEX class.c +__objc_class_links_resolved UNUSED class.c runtime.h +__objc_class_number MUTEX class.c +__objc_dangling_categories UNUSED init.c +__objc_module_list MUTEX init.c +__objc_selector_array MUTEX selector.c +__objc_selector_hash MUTEX selector.c +__objc_selector_max_index MUTEX selector.c sendmsg.c runtime.h +__objc_selector_names MUTEX selector.c +__objc_thread_exit_status SAFE thread.c +__objc_uninstalled_dtable MUTEX sendmsg.c selector.c +_objc_load_callback SAFE init.c objc-api.h +_objc_lookup_class SAFE class.c objc-api.h +_objc_object_alloc SINGLE objects.c objc-api.h +_objc_object_copy SINGLE objects.c objc-api.h +_objc_object_dispose SINGLE objects.c objc-api.h +frwd_sel SAFE2 sendmsg.c +idxsize MUTEX sarray.c sendmsg.c sarray.h +initialize_sel SAFE2 sendmsg.c +narrays MUTEX sarray.c sendmsg.c sarray.h +nbuckets MUTEX sarray.c sendmsg.c sarray.h +nindices MUTEX sarray.c sarray.h +previous_constructors SAFE1 init.c +proto_class SAFE1 init.c +unclaimed_categories MUTEX init.c +unclaimed_proto_list MUTEX init.c +uninitialized_statics MUTEX init.c + +Notes: +1) Initialized once in unithread mode. +2) Initialized value will always be same, guaranteed by lock on selector + hash table. + + +****************************************************************************** +* Frontend/Backend design: + +The design of the Objective-C runtime thread and mutex functions utilizes a +frontend/backend implementation. + +The frontend, as characterized by the files thr.h and thr.c, is a set +of platform independent structures and functions which represent the +user interface. Objective-C programs should use these structures and +functions for their thread and mutex work if they wish to maintain a +high degree of portability across platforms. + +The backend is composed of a file with the necessary code to map the ObjC +thread and mutex to a platform specific implementation. For example, the +file thr-solaris.c contains the implementation for Solaris. When you +configure GCC, it attempts to pick an appropriate backend file for the +target platform; however, you can override this choice by assign the +OBJC_THREAD_FILE make variable to the basename of the backend file. This +is especially useful on platforms which have multiple thread libraries. +For example: + + make OBJC_THREAD_FILE=thr-posix + +would indicate that the generic posix backend file, thr-posix.c, should be +compiled with the ObjC runtime library. If your platform does not support +threads then you should specify the OBJC_THREAD_FILE=thr-single backend file +to compile the ObjC runtime library without thread or mutex support; note +that programs which rely upon the ObjC thread and mutex functions will +compile and link correctly but attempting to create a thread or mutex will +result in an error. + +It is questionable whether it is really necessary to have both a +frontend and backend function for all available functionality. On the +one hand, it provides a clear, consistent differentiation between what +is public and what is private with the downside of having the overhead +of multiple functions calls. For example, the function to have a thread +yield the processor is objc_thread_yield; in the current implementation +this produces a function call set: + +objc_thread_yield() -> __objc_thread_yield() -> system yield function + +This has two extra function calls over calling the platform specific function +explicitly, but the issue is whether only the overhead of a single function +is necessary. + +objc_thread_yield() -> system yield function + +This breaks the public/private dichotomy between the frontend/backend +for the sake of efficiency. It is possible to just use a preprocessor +define so as to eliminate the extra function call: + +#define objc_thread_yield() __objc_thread_yield() + +This has the undesirable effect that if objc_thread_yield is actually +turned into a function based upon future need; then ObjC programs which +access the thread functions would need to be recompiled versus just +being relinked. + +****************************************************************************** +* Threads: + +The thread system attempts to create multiple threads using whatever +operating system or library thread support is available. It does +assume that all system functions are thread safe. Notably this means +that the system implementation of malloc and free must be thread safe. +If a system has multiple processors, the threads are configured for +full parallel processing. + +* Backend initialization functions + +__objc_init_thread_system(void), int + Initialize the thread subsystem. Called once by __objc_exec_class. + Return -1 if error otherwise return 0. + +__objc_close_thread_system(void), int + Closes the thread subsystem, not currently guaranteed to be called. + Return -1 if error otherwise return 0. + +***** +* Frontend thread functions +* User programs should use these functions. + +objc_thread_detach(SEL selector, id object, id argument), objc_thread_t + Creates and detaches a new thread. The new thread starts by + sending the given selector with a single argument to the + given object. + +objc_thread_set_priority(int priority), int + Sets a thread's relative priority within the program. Valid + options are: + + OBJC_THREAD_INTERACTIVE_PRIORITY + OBJC_THREAD_BACKGROUND_PRIORITY + OBJC_THREAD_LOW_PRIORITY + +objc_thread_get_priority(void), int + Query a thread's priority. + +objc_thread_yield(void), void + Yields processor to another thread with equal or higher + priority. It is up to the system scheduler to determine if + the processor is taken or not. + +objc_thread_exit(void), int + Terminates a thread. If this is the last thread executing + then the program will terminate. + +objc_thread_id(void), int + Returns the current thread's id. + +objc_thread_set_data(void *value), int + Set a pointer to the thread's local storage. Local storage is + thread specific. + +objc_thread_get_data(void), void * + Returns the pointer to the thread's local storage. + +***** +* Backend thread functions +* User programs should *NOT* directly call these functions. + +__objc_thread_detach(void (*func)(void *arg), void *arg), objc_thread_t + Spawns a new thread executing func, called by objc_thread_detach. + Return NULL if error otherwise return thread id. + +__objc_thread_set_priority(int priority), int + Set the thread's priority, called by objc_thread_set_priority. + Return -1 if error otherwise return 0. + +__objc_thread_get_priority(void), int + Query a thread's priority, called by objc_thread_get_priority. + Return -1 if error otherwise return the priority. + +__objc_thread_yield(void), void + Yields the processor, called by objc_thread_yield. + +__objc_thread_exit(void), int + Terminates the thread, called by objc_thread_exit. + Return -1 if error otherwise function does not return. + +__objc_thread_id(void), objc_thread_t + Returns the current thread's id, called by objc_thread_id. + Return -1 if error otherwise return thread id. + +__objc_thread_set_data(void *value), int + Set pointer for thread local storage, called by objc_thread_set_data. + Returns -1 if error otherwise return 0. + +__objc_thread_get_data(void), void * + Returns the pointer to the thread's local storage. + Returns NULL if error, called by objc_thread_get_data. + + +****************************************************************************** +* Mutexes: + +Mutexes can be locked recursively. Each locked mutex remembers +its owner (by thread id) and how many times it has been locked. The +last unlock on a mutex removes the system lock and allows other +threads to access the mutex. + +***** +* Frontend mutex functions +* User programs should use these functions. + +objc_mutex_allocate(void), objc_mutex_t + Allocates a new mutex. Mutex is initially unlocked. + Return NULL if error otherwise return mutex pointer. + +objc_mutex_deallocate(objc_mutex_t mutex), int + Free a mutex. Before freeing the mutex, makes sure that no + one else is using it. + Return -1 if error otherwise return 0. + +objc_mutex_lock(objc_mutex_t mutex), int + Locks a mutex. As mentioned earlier, the same thread may call + this routine repeatedly. + Return -1 if error otherwise return 0. + +objc_mutex_trylock(objc_mutex_t mutex), int + Attempts to lock a mutex. If lock on mutex can be acquired + then function operates exactly as objc_mutex_lock. + Return -1 if failed to acquire lock otherwise return 0. + +objc_mutex_unlock(objc_mutex_t mutex), int + Unlocks the mutex by one level. Other threads may not acquire + the mutex until this thread has released all locks on it. + Return -1 if error otherwise return 0. + +***** +* Backend mutex functions +* User programs should *NOT* directly call these functions. + +__objc_mutex_allocate(objc_mutex_t mutex), int + Allocates a new mutex, called by objc_mutex_allocate. + Return -1 if error otherwise return 0. + +__objc_mutex_deallocate(objc_mutex_t mutex), int + Free a mutex, called by objc_mutex_deallocate. + Return -1 if error otherwise return 0. + +__objc_mutex_lock(objc_mutex_t mutex), int + Locks a mutex, called by objc_mutex_lock. + Return -1 if error otherwise return 0. + +__objc_mutex_trylock(objc_mutex_t mutex), int + Attempts to lock a mutex, called by objc_mutex_trylock. + Return -1 if failed to acquire lock or error otherwise return 0. + +__objc_mutex_unlock(objc_mutex_t mutex), int + Unlocks the mutex, called by objc_mutex_unlock. + Return -1 if error otherwise return 0. + +****************************************************************************** +* Condition Mutexes: + +Mutexes can be locked recursively. Each locked mutex remembers +its owner (by thread id) and how many times it has been locked. The +last unlock on a mutex removes the system lock and allows other +threads to access the mutex. + +* +* Frontend condition mutex functions +* User programs should use these functions. +* + +objc_condition_allocate(void), objc_condition_t + Allocate a condition mutex. + Return NULL if error otherwise return condition pointer. + +objc_condition_deallocate(objc_condition_t condition), int + Deallocate a condition. Note that this includes an implicit + condition_broadcast to insure that waiting threads have the + opportunity to wake. It is legal to dealloc a condition only + if no other thread is/will be using it. Does NOT check for + other threads waiting but just wakes them up. + Return -1 if error otherwise return 0. + +objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex), int + Wait on the condition unlocking the mutex until objc_condition_signal() + or objc_condition_broadcast() are called for the same condition. The + given mutex *must* have the depth 1 so that it can be unlocked + here, for someone else can lock it and signal/broadcast the condition. + The mutex is used to lock access to the shared data that make up the + "condition" predicate. + Return -1 if error otherwise return 0. + +objc_condition_broadcast(objc_condition_t condition), int + Wake up all threads waiting on this condition. It is recommended that + the called would lock the same mutex as the threads in + objc_condition_wait before changing the "condition predicate" + and make this call and unlock it right away after this call. + Return -1 if error otherwise return 0. + +objc_condition_signal(objc_condition_t condition), int + Wake up one thread waiting on this condition. + Return -1 if error otherwise return 0. + +* +* Backend condition mutex functions +* User programs should *NOT* directly call these functions. +* + +__objc_condition_allocate(objc_condition_t condition), int + Allocate a condition mutex, called by objc_condition_allocate. + Return -1 if error otherwise return 0. + +__objc_condition_deallocate(objc_condition_t condition), int + Deallocate a condition, called by objc_condition_deallocate. + Return -1 if error otherwise return 0. + +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex), int + Wait on the condition, called by objc_condition_wait. + Return -1 if error otherwise return 0 when condition is met. + +__objc_condition_broadcast(objc_condition_t condition), int + Wake up all threads waiting on this condition. + Called by objc_condition_broadcast. + Return -1 if error otherwise return 0. + +__objc_condition_signal(objc_condition_t condition), int + Wake up one thread waiting on this condition. + Called by objc_condition_signal. + Return -1 if error otherwise return 0. diff --git a/contrib/gcc/objc/THREADS.MACH b/contrib/gcc/objc/THREADS.MACH new file mode 100644 index 000000000000..55de66378669 --- /dev/null +++ b/contrib/gcc/objc/THREADS.MACH @@ -0,0 +1,23 @@ +This readme refers to the file thr-mach.c. + +Under mach, thread priorities are kinda strange-- any given thread has +a MAXIMUM priority and a BASE priority. The BASE priority is the +current priority of the thread and the MAXIMUM is the maximum possible +priority the thread can assume. The developer can lower, but never +raise the maximum priority. + +The gcc concept of thread priorities is that they run at one of three +levels; interactive, background, and low. + +Under mach, this is translated to: + +interactive -- set priority to maximum +background -- set priority to 2/3 of maximum +low -- set priority to 1/3 of maximum + +This means that it is possible for a thread with the priority of +interactive to actually run at a lower priority than another thread +with a background, or even low, priority if the developer has modified +the maximum priority. + + diff --git a/contrib/gcc/objc/archive.c b/contrib/gcc/objc/archive.c new file mode 100644 index 000000000000..c762fe6186e5 --- /dev/null +++ b/contrib/gcc/objc/archive.c @@ -0,0 +1,1651 @@ +/* GNU Objective C Runtime archiving + Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include "config.h" +#include "runtime.h" +#include "typedstream.h" +#include "encoding.h" + +#ifdef HAVE_STDLIB_H +#include <stdlib.h> +#endif + +extern int fflush(FILE*); + +#define ROUND(V, A) \ + ({ typeof(V) __v=(V); typeof(A) __a=(A); \ + __a*((__v+__a-1)/__a); }) + +#define PTR2LONG(P) (((char*)(P))-(char*)0) +#define LONG2PTR(L) (((char*)0)+(L)) + +/* Declare some functions... */ + +static int +objc_read_class (struct objc_typed_stream* stream, Class* class); + +int objc_sizeof_type(const char* type); + +static int +objc_write_use_common (struct objc_typed_stream* stream, unsigned long key); + +static int +objc_write_register_common (struct objc_typed_stream* stream, + unsigned long key); + +static int +objc_write_class (struct objc_typed_stream* stream, + struct objc_class* class); + +const char* objc_skip_type (const char* type); + +static void __objc_finish_write_root_object(struct objc_typed_stream*); +static void __objc_finish_read_root_object(struct objc_typed_stream*); + +static __inline__ int +__objc_code_unsigned_char (unsigned char* buf, unsigned char val) +{ + if ((val&_B_VALUE) == val) + { + buf[0] = val|_B_SINT; + return 1; + } + else + { + buf[0] = _B_NINT|0x01; + buf[1] = val; + return 2; + } +} + +int +objc_write_unsigned_char (struct objc_typed_stream* stream, + unsigned char value) +{ + unsigned char buf[sizeof (unsigned char)+1]; + int len = __objc_code_unsigned_char (buf, value); + return (*stream->write)(stream->physical, buf, len); +} + +static __inline__ int +__objc_code_char (unsigned char* buf, char val) +{ + if (val >= 0) + return __objc_code_unsigned_char (buf, val); + else + { + buf[0] = _B_NINT|_B_SIGN|0x01; + buf[1] = -val; + return 2; + } +} + +int +objc_write_char (struct objc_typed_stream* stream, char value) +{ + unsigned char buf[sizeof (char)+1]; + int len = __objc_code_char (buf, value); + return (*stream->write)(stream->physical, buf, len); +} + +static __inline__ int +__objc_code_unsigned_short (unsigned char* buf, unsigned short val) +{ + if ((val&_B_VALUE) == val) + { + buf[0] = val|_B_SINT; + return 1; + } + else + { + int c, b; + + buf[0] = _B_NINT; + + for (c= sizeof(short); c != 0; c -= 1) + if (((val>>(8*(c-1)))%0x100) != 0) + break; + + buf[0] |= c; + + for (b = 1; c != 0; c--, b++) + { + buf[b] = (val >> (8*(c-1)))%0x100; + } + + return b; + } +} + +int +objc_write_unsigned_short (struct objc_typed_stream* stream, + unsigned short value) +{ + unsigned char buf[sizeof (unsigned short)+1]; + int len = __objc_code_unsigned_short (buf, value); + return (*stream->write)(stream->physical, buf, len); +} + +static __inline__ int +__objc_code_short (unsigned char* buf, short val) +{ + int sign = (val < 0); + int size = __objc_code_unsigned_short (buf, sign ? -val : val); + if (sign) + buf[0] |= _B_SIGN; + return size; +} + +int +objc_write_short (struct objc_typed_stream* stream, short value) +{ + unsigned char buf[sizeof (short)+1]; + int len = __objc_code_short (buf, value); + return (*stream->write)(stream->physical, buf, len); +} + + +static __inline__ int +__objc_code_unsigned_int (unsigned char* buf, unsigned int val) +{ + if ((val&_B_VALUE) == val) + { + buf[0] = val|_B_SINT; + return 1; + } + else + { + int c, b; + + buf[0] = _B_NINT; + + for (c= sizeof(int); c != 0; c -= 1) + if (((val>>(8*(c-1)))%0x100) != 0) + break; + + buf[0] |= c; + + for (b = 1; c != 0; c--, b++) + { + buf[b] = (val >> (8*(c-1)))%0x100; + } + + return b; + } +} + +int +objc_write_unsigned_int (struct objc_typed_stream* stream, unsigned int value) +{ + unsigned char buf[sizeof(unsigned int)+1]; + int len = __objc_code_unsigned_int (buf, value); + return (*stream->write)(stream->physical, buf, len); +} + +static __inline__ int +__objc_code_int (unsigned char* buf, int val) +{ + int sign = (val < 0); + int size = __objc_code_unsigned_int (buf, sign ? -val : val); + if (sign) + buf[0] |= _B_SIGN; + return size; +} + +int +objc_write_int (struct objc_typed_stream* stream, int value) +{ + unsigned char buf[sizeof(int)+1]; + int len = __objc_code_int (buf, value); + return (*stream->write)(stream->physical, buf, len); +} + +static __inline__ int +__objc_code_unsigned_long (unsigned char* buf, unsigned long val) +{ + if ((val&_B_VALUE) == val) + { + buf[0] = val|_B_SINT; + return 1; + } + else + { + int c, b; + + buf[0] = _B_NINT; + + for (c= sizeof(long); c != 0; c -= 1) + if (((val>>(8*(c-1)))%0x100) != 0) + break; + + buf[0] |= c; + + for (b = 1; c != 0; c--, b++) + { + buf[b] = (val >> (8*(c-1)))%0x100; + } + + return b; + } +} + +int +objc_write_unsigned_long (struct objc_typed_stream* stream, + unsigned long value) +{ + unsigned char buf[sizeof(unsigned long)+1]; + int len = __objc_code_unsigned_long (buf, value); + return (*stream->write)(stream->physical, buf, len); +} + +static __inline__ int +__objc_code_long (unsigned char* buf, long val) +{ + int sign = (val < 0); + int size = __objc_code_unsigned_long (buf, sign ? -val : val); + if (sign) + buf[0] |= _B_SIGN; + return size; +} + +int +objc_write_long (struct objc_typed_stream* stream, long value) +{ + unsigned char buf[sizeof(long)+1]; + int len = __objc_code_long (buf, value); + return (*stream->write)(stream->physical, buf, len); +} + + +int +objc_write_string (struct objc_typed_stream* stream, + const unsigned char* string, unsigned int nbytes) +{ + unsigned char buf[sizeof(unsigned int)+1]; + int len = __objc_code_unsigned_int (buf, nbytes); + + if ((buf[0]&_B_CODE) == _B_SINT) + buf[0] = (buf[0]&_B_VALUE)|_B_SSTR; + + else /* _B_NINT */ + buf[0] = (buf[0]&_B_VALUE)|_B_NSTR; + + if ((*stream->write)(stream->physical, buf, len) != 0) + return (*stream->write)(stream->physical, string, nbytes); + else + return 0; +} + +int +objc_write_string_atomic (struct objc_typed_stream* stream, + unsigned char* string, unsigned int nbytes) +{ + unsigned long key; + if ((key = PTR2LONG(hash_value_for_key (stream->stream_table, string)))) + return objc_write_use_common (stream, key); + else + { + int length; + hash_add (&stream->stream_table, LONG2PTR(key=PTR2LONG(string)), string); + if ((length = objc_write_register_common (stream, key))) + return objc_write_string (stream, string, nbytes); + return length; + } +} + +static int +objc_write_register_common (struct objc_typed_stream* stream, + unsigned long key) +{ + unsigned char buf[sizeof (unsigned long)+2]; + int len = __objc_code_unsigned_long (buf+1, key); + if (len == 1) + { + buf[0] = _B_RCOMM|0x01; + buf[1] &= _B_VALUE; + return (*stream->write)(stream->physical, buf, len+1); + } + else + { + buf[1] = (buf[1]&_B_VALUE)|_B_RCOMM; + return (*stream->write)(stream->physical, buf+1, len); + } +} + +static int +objc_write_use_common (struct objc_typed_stream* stream, unsigned long key) +{ + unsigned char buf[sizeof (unsigned long)+2]; + int len = __objc_code_unsigned_long (buf+1, key); + if (len == 1) + { + buf[0] = _B_UCOMM|0x01; + buf[1] &= _B_VALUE; + return (*stream->write)(stream->physical, buf, 2); + } + else + { + buf[1] = (buf[1]&_B_VALUE)|_B_UCOMM; + return (*stream->write)(stream->physical, buf+1, len); + } +} + +static __inline__ int +__objc_write_extension (struct objc_typed_stream* stream, unsigned char code) +{ + if (code <= _B_VALUE) + { + unsigned char buf = code|_B_EXT; + return (*stream->write)(stream->physical, &buf, 1); + } + else + { + objc_error(nil, OBJC_ERR_BAD_OPCODE, + "__objc_write_extension: bad opcode %c\n", code); + return -1; + } +} + +__inline__ int +__objc_write_object (struct objc_typed_stream* stream, id object) +{ + unsigned char buf = '\0'; + SEL write_sel = sel_get_any_uid ("write:"); + if (object) + { + __objc_write_extension (stream, _BX_OBJECT); + objc_write_class (stream, object->class_pointer); + (*objc_msg_lookup(object, write_sel))(object, write_sel, stream); + return (*stream->write)(stream->physical, &buf, 1); + } + else + return objc_write_use_common(stream, 0); +} + +int +objc_write_object_reference (struct objc_typed_stream* stream, id object) +{ + unsigned long key; + if ((key = PTR2LONG(hash_value_for_key (stream->object_table, object)))) + return objc_write_use_common (stream, key); + + __objc_write_extension (stream, _BX_OBJREF); + return objc_write_unsigned_long (stream, PTR2LONG (object)); +} + +int +objc_write_root_object (struct objc_typed_stream* stream, id object) +{ + int len = 0; + if (stream->writing_root_p) + objc_error (nil, OBJC_ERR_RECURSE_ROOT, + "objc_write_root_object called recursively"); + else + { + stream->writing_root_p = 1; + __objc_write_extension (stream, _BX_OBJROOT); + if((len = objc_write_object (stream, object))) + __objc_finish_write_root_object(stream); + stream->writing_root_p = 0; + } + return len; +} + +int +objc_write_object (struct objc_typed_stream* stream, id object) +{ + unsigned long key; + if ((key = PTR2LONG(hash_value_for_key (stream->object_table, object)))) + return objc_write_use_common (stream, key); + + else if (object == nil) + return objc_write_use_common(stream, 0); + + else + { + int length; + hash_add (&stream->object_table, LONG2PTR(key=PTR2LONG(object)), object); + if ((length = objc_write_register_common (stream, key))) + return __objc_write_object (stream, object); + return length; + } +} + +__inline__ int +__objc_write_class (struct objc_typed_stream* stream, struct objc_class* class) +{ + __objc_write_extension (stream, _BX_CLASS); + objc_write_string_atomic(stream, (char*)class->name, + strlen((char*)class->name)); + return objc_write_unsigned_long (stream, class->version); +} + + +static int +objc_write_class (struct objc_typed_stream* stream, + struct objc_class* class) +{ + unsigned long key; + if ((key = PTR2LONG(hash_value_for_key (stream->stream_table, class)))) + return objc_write_use_common (stream, key); + else + { + int length; + hash_add (&stream->stream_table, LONG2PTR(key=PTR2LONG(class)), class); + if ((length = objc_write_register_common (stream, key))) + return __objc_write_class (stream, class); + return length; + } +} + + +__inline__ int +__objc_write_selector (struct objc_typed_stream* stream, SEL selector) +{ + const char* sel_name; + __objc_write_extension (stream, _BX_SEL); + /* to handle NULL selectors */ + if ((SEL)0 == selector) + return objc_write_string (stream, "", 0); + sel_name = sel_get_name (selector); + return objc_write_string (stream, sel_name, strlen ((char*)sel_name)); +} + +int +objc_write_selector (struct objc_typed_stream* stream, SEL selector) +{ + const char* sel_name; + unsigned long key; + + /* to handle NULL selectors */ + if ((SEL)0 == selector) + return __objc_write_selector (stream, selector); + + sel_name = sel_get_name (selector); + if ((key = PTR2LONG(hash_value_for_key (stream->stream_table, sel_name)))) + return objc_write_use_common (stream, key); + else + { + int length; + hash_add (&stream->stream_table, + LONG2PTR(key=PTR2LONG(sel_name)), (char*)sel_name); + if ((length = objc_write_register_common (stream, key))) + return __objc_write_selector (stream, selector); + return length; + } +} + + + +/* +** Read operations +*/ + +__inline__ int +objc_read_char (struct objc_typed_stream* stream, char* val) +{ + unsigned char buf; + int len; + len = (*stream->read)(stream->physical, &buf, 1); + if (len != 0) + { + if ((buf & _B_CODE) == _B_SINT) + (*val) = (buf & _B_VALUE); + + else if ((buf & _B_NUMBER) == 1) + { + len = (*stream->read)(stream->physical, val, 1); + if (buf&_B_SIGN) + (*val) = -1*(*val); + } + + else + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected 8bit signed int, got %dbit int", + (int)(buf&_B_NUMBER)*8); + } + return len; +} + + +__inline__ int +objc_read_unsigned_char (struct objc_typed_stream* stream, unsigned char* val) +{ + unsigned char buf; + int len; + if ((len = (*stream->read)(stream->physical, &buf, 1))) + { + if ((buf & _B_CODE) == _B_SINT) + (*val) = (buf & _B_VALUE); + + else if ((buf & _B_NUMBER) == 1) + len = (*stream->read)(stream->physical, val, 1); + + else + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected 8bit unsigned int, got %dbit int", + (int)(buf&_B_NUMBER)*8); + } + return len; +} + +__inline__ int +objc_read_short (struct objc_typed_stream* stream, short* value) +{ + unsigned char buf[sizeof(short)+1]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + if ((buf[0] & _B_CODE) == _B_SINT) + (*value) = (buf[0] & _B_VALUE); + + else + { + int pos = 1; + int nbytes = buf[0] & _B_NUMBER; + if (nbytes > sizeof (short)) + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected short, got bigger (%dbits)", nbytes*8); + len = (*stream->read)(stream->physical, buf+1, nbytes); + (*value) = 0; + while (pos <= nbytes) + (*value) = ((*value)*0x100) + buf[pos++]; + if (buf[0] & _B_SIGN) + (*value) = -(*value); + } + } + return len; +} + +__inline__ int +objc_read_unsigned_short (struct objc_typed_stream* stream, + unsigned short* value) +{ + unsigned char buf[sizeof(unsigned short)+1]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + if ((buf[0] & _B_CODE) == _B_SINT) + (*value) = (buf[0] & _B_VALUE); + + else + { + int pos = 1; + int nbytes = buf[0] & _B_NUMBER; + if (nbytes > sizeof (short)) + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected short, got int or bigger"); + len = (*stream->read)(stream->physical, buf+1, nbytes); + (*value) = 0; + while (pos <= nbytes) + (*value) = ((*value)*0x100) + buf[pos++]; + } + } + return len; +} + + +__inline__ int +objc_read_int (struct objc_typed_stream* stream, int* value) +{ + unsigned char buf[sizeof(int)+1]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + if ((buf[0] & _B_CODE) == _B_SINT) + (*value) = (buf[0] & _B_VALUE); + + else + { + int pos = 1; + int nbytes = buf[0] & _B_NUMBER; + if (nbytes > sizeof (int)) + objc_error(nil, OBJC_ERR_BAD_DATA, "expected int, got bigger"); + len = (*stream->read)(stream->physical, buf+1, nbytes); + (*value) = 0; + while (pos <= nbytes) + (*value) = ((*value)*0x100) + buf[pos++]; + if (buf[0] & _B_SIGN) + (*value) = -(*value); + } + } + return len; +} + +__inline__ int +objc_read_long (struct objc_typed_stream* stream, long* value) +{ + unsigned char buf[sizeof(long)+1]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + if ((buf[0] & _B_CODE) == _B_SINT) + (*value) = (buf[0] & _B_VALUE); + + else + { + int pos = 1; + int nbytes = buf[0] & _B_NUMBER; + if (nbytes > sizeof (long)) + objc_error(nil, OBJC_ERR_BAD_DATA, "expected long, got bigger"); + len = (*stream->read)(stream->physical, buf+1, nbytes); + (*value) = 0; + while (pos <= nbytes) + (*value) = ((*value)*0x100) + buf[pos++]; + if (buf[0] & _B_SIGN) + (*value) = -(*value); + } + } + return len; +} + +__inline__ int +__objc_read_nbyte_uint (struct objc_typed_stream* stream, + unsigned int nbytes, unsigned int* val) +{ + int len, pos = 0; + unsigned char buf[sizeof(unsigned int)+1]; + + if (nbytes > sizeof (int)) + objc_error(nil, OBJC_ERR_BAD_DATA, "expected int, got bigger"); + + len = (*stream->read)(stream->physical, buf, nbytes); + (*val) = 0; + while (pos < nbytes) + (*val) = ((*val)*0x100) + buf[pos++]; + return len; +} + + +__inline__ int +objc_read_unsigned_int (struct objc_typed_stream* stream, + unsigned int* value) +{ + unsigned char buf[sizeof(unsigned int)+1]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + if ((buf[0] & _B_CODE) == _B_SINT) + (*value) = (buf[0] & _B_VALUE); + + else + len = __objc_read_nbyte_uint (stream, (buf[0] & _B_VALUE), value); + + } + return len; +} + +int +__objc_read_nbyte_ulong (struct objc_typed_stream* stream, + unsigned int nbytes, unsigned long* val) +{ + int len, pos = 0; + unsigned char buf[sizeof(unsigned long)+1]; + + if (nbytes > sizeof (long)) + objc_error(nil, OBJC_ERR_BAD_DATA, "expected long, got bigger"); + + len = (*stream->read)(stream->physical, buf, nbytes); + (*val) = 0; + while (pos < nbytes) + (*val) = ((*val)*0x100) + buf[pos++]; + return len; +} + + +__inline__ int +objc_read_unsigned_long (struct objc_typed_stream* stream, + unsigned long* value) +{ + unsigned char buf[sizeof(unsigned long)+1]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + if ((buf[0] & _B_CODE) == _B_SINT) + (*value) = (buf[0] & _B_VALUE); + + else + len = __objc_read_nbyte_ulong (stream, (buf[0] & _B_VALUE), value); + + } + return len; +} + +__inline__ int +objc_read_string (struct objc_typed_stream* stream, + char** string) +{ + unsigned char buf[sizeof(unsigned int)+1]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + unsigned long key = 0; + + if ((buf[0]&_B_CODE) == _B_RCOMM) /* register following */ + { + len = __objc_read_nbyte_ulong(stream, (buf[0] & _B_VALUE), &key); + len = (*stream->read)(stream->physical, buf, 1); + } + + switch (buf[0]&_B_CODE) { + case _B_SSTR: + { + int length = buf[0]&_B_VALUE; + (*string) = (char*)objc_malloc(length+1); + if (key) + hash_add (&stream->stream_table, LONG2PTR(key), *string); + len = (*stream->read)(stream->physical, *string, length); + (*string)[length] = '\0'; + } + break; + + case _B_UCOMM: + { + char *tmp; + len = __objc_read_nbyte_ulong(stream, (buf[0] & _B_VALUE), &key); + tmp = hash_value_for_key (stream->stream_table, LONG2PTR (key)); + *string = objc_malloc (strlen(tmp) + 1); + strcpy (*string, tmp); + } + break; + + case _B_NSTR: + { + unsigned int nbytes = buf[0]&_B_VALUE; + len = __objc_read_nbyte_uint(stream, nbytes, &nbytes); + if (len) { + (*string) = (char*)objc_malloc(nbytes+1); + if (key) + hash_add (&stream->stream_table, LONG2PTR(key), *string); + len = (*stream->read)(stream->physical, *string, nbytes); + (*string)[nbytes] = '\0'; + } + } + break; + + default: + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected string, got opcode %c\n", (buf[0]&_B_CODE)); + } + } + + return len; +} + + +int +objc_read_object (struct objc_typed_stream* stream, id* object) +{ + unsigned char buf[sizeof (unsigned int)]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + SEL read_sel = sel_get_any_uid ("read:"); + unsigned long key = 0; + + if ((buf[0]&_B_CODE) == _B_RCOMM) /* register common */ + { + len = __objc_read_nbyte_ulong(stream, (buf[0] & _B_VALUE), &key); + len = (*stream->read)(stream->physical, buf, 1); + } + + if (buf[0] == (_B_EXT | _BX_OBJECT)) + { + Class class; + + /* get class */ + len = objc_read_class (stream, &class); + + /* create instance */ + (*object) = class_create_instance(class); + + /* register? */ + if (key) + hash_add (&stream->object_table, LONG2PTR(key), *object); + + /* send -read: */ + if (__objc_responds_to (*object, read_sel)) + (*get_imp(class, read_sel))(*object, read_sel, stream); + + /* check null-byte */ + len = (*stream->read)(stream->physical, buf, 1); + if (buf[0] != '\0') + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected null-byte, got opcode %c", buf[0]); + } + + else if ((buf[0]&_B_CODE) == _B_UCOMM) + { + if (key) + objc_error(nil, OBJC_ERR_BAD_KEY, "cannot register use upcode..."); + len = __objc_read_nbyte_ulong(stream, (buf[0] & _B_VALUE), &key); + (*object) = hash_value_for_key (stream->object_table, LONG2PTR(key)); + } + + else if (buf[0] == (_B_EXT | _BX_OBJREF)) /* a forward reference */ + { + struct objc_list* other; + len = objc_read_unsigned_long (stream, &key); + other = (struct objc_list*)hash_value_for_key (stream->object_refs, + LONG2PTR(key)); + hash_add (&stream->object_refs, LONG2PTR(key), + (void*)list_cons(object, other)); + } + + else if (buf[0] == (_B_EXT | _BX_OBJROOT)) /* a root object */ + { + if (key) + objc_error(nil, OBJC_ERR_BAD_KEY, + "cannot register root object..."); + len = objc_read_object (stream, object); + __objc_finish_read_root_object (stream); + } + + else + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected object, got opcode %c", buf[0]); + } + return len; +} + +static int +objc_read_class (struct objc_typed_stream* stream, Class* class) +{ + unsigned char buf[sizeof (unsigned int)]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + unsigned long key = 0; + + if ((buf[0]&_B_CODE) == _B_RCOMM) /* register following */ + { + len = __objc_read_nbyte_ulong(stream, (buf[0] & _B_VALUE), &key); + len = (*stream->read)(stream->physical, buf, 1); + } + + if (buf[0] == (_B_EXT | _BX_CLASS)) + { + char* class_name; + unsigned long version; + + /* get class */ + len = objc_read_string (stream, &class_name); + (*class) = objc_get_class(class_name); + objc_free(class_name); + + /* register */ + if (key) + hash_add (&stream->stream_table, LONG2PTR(key), *class); + + objc_read_unsigned_long(stream, &version); + hash_add (&stream->class_table, (*class)->name, (void*)version); + } + + else if ((buf[0]&_B_CODE) == _B_UCOMM) + { + if (key) + objc_error(nil, OBJC_ERR_BAD_KEY, "cannot register use upcode..."); + len = __objc_read_nbyte_ulong(stream, (buf[0] & _B_VALUE), &key); + (*class) = hash_value_for_key (stream->stream_table, LONG2PTR(key)); + if (!*class) + objc_error(nil, OBJC_ERR_BAD_CLASS, + "cannot find class for key %lu", key); + } + + else + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected class, got opcode %c", buf[0]); + } + return len; +} + +int +objc_read_selector (struct objc_typed_stream* stream, SEL* selector) +{ + unsigned char buf[sizeof (unsigned int)]; + int len; + if ((len = (*stream->read)(stream->physical, buf, 1))) + { + unsigned long key = 0; + + if ((buf[0]&_B_CODE) == _B_RCOMM) /* register following */ + { + len = __objc_read_nbyte_ulong(stream, (buf[0] & _B_VALUE), &key); + len = (*stream->read)(stream->physical, buf, 1); + } + + if (buf[0] == (_B_EXT|_BX_SEL)) /* selector! */ + { + char* selector_name; + + /* get selector */ + len = objc_read_string (stream, &selector_name); + /* To handle NULL selectors */ + if (0 == strlen(selector_name)) + { + (*selector) = (SEL)0; + return 0; + } + else + (*selector) = sel_get_any_uid(selector_name); + objc_free(selector_name); + + /* register */ + if (key) + hash_add (&stream->stream_table, LONG2PTR(key), (void*)*selector); + } + + else if ((buf[0]&_B_CODE) == _B_UCOMM) + { + if (key) + objc_error(nil, OBJC_ERR_BAD_KEY, "cannot register use upcode..."); + len = __objc_read_nbyte_ulong(stream, (buf[0] & _B_VALUE), &key); + (*selector) = hash_value_for_key (stream->stream_table, + LONG2PTR(key)); + } + + else + objc_error(nil, OBJC_ERR_BAD_DATA, + "expected selector, got opcode %c", buf[0]); + } + return len; +} + +/* +** USER LEVEL FUNCTIONS +*/ + +/* +** Write one object, encoded in TYPE and pointed to by DATA to the +** typed stream STREAM. +*/ + +int +objc_write_type(TypedStream* stream, const char* type, const void* data) +{ + switch(*type) { + case _C_ID: + return objc_write_object (stream, *(id*)data); + break; + + case _C_CLASS: + return objc_write_class (stream, *(Class*)data); + break; + + case _C_SEL: + return objc_write_selector (stream, *(SEL*)data); + break; + + case _C_CHR: + return objc_write_char(stream, *(char*)data); + break; + + case _C_UCHR: + return objc_write_unsigned_char(stream, *(unsigned char*)data); + break; + + case _C_SHT: + return objc_write_short(stream, *(short*)data); + break; + + case _C_USHT: + return objc_write_unsigned_short(stream, *(unsigned short*)data); + break; + + case _C_INT: + return objc_write_int(stream, *(int*)data); + break; + + case _C_UINT: + return objc_write_unsigned_int(stream, *(unsigned int*)data); + break; + + case _C_LNG: + return objc_write_long(stream, *(long*)data); + break; + + case _C_ULNG: + return objc_write_unsigned_long(stream, *(unsigned long*)data); + break; + + case _C_CHARPTR: + return objc_write_string (stream, *(char**)data, strlen(*(char**)data)); + break; + + case _C_ATOM: + return objc_write_string_atomic (stream, *(char**)data, + strlen(*(char**)data)); + break; + + case _C_ARY_B: + { + int len = atoi(type+1); + while (isdigit(*++type)) + ; + return objc_write_array (stream, type, len, data); + } + break; + + case _C_STRUCT_B: + { + int acc_size = 0; + int align; + while (*type != _C_STRUCT_E && *type++ != '=') + ; /* skip "<name>=" */ + while (*type != _C_STRUCT_E) + { + align = objc_alignof_type (type); /* padd to alignment */ + acc_size += ROUND (acc_size, align); + objc_write_type (stream, type, ((char*)data)+acc_size); + acc_size += objc_sizeof_type (type); /* add component size */ + type = objc_skip_typespec (type); /* skip component */ + } + return 1; + } + + default: + { + objc_error(nil, OBJC_ERR_BAD_TYPE, + "objc_write_type: cannot parse typespec: %s\n", type); + return 0; + } + } +} + +/* +** Read one object, encoded in TYPE and pointed to by DATA to the +** typed stream STREAM. DATA specifies the address of the types to +** read. Expected type is checked against the type actually present +** on the stream. +*/ + +int +objc_read_type(TypedStream* stream, const char* type, void* data) +{ + char c; + switch(c = *type) { + case _C_ID: + return objc_read_object (stream, (id*)data); + break; + + case _C_CLASS: + return objc_read_class (stream, (Class*)data); + break; + + case _C_SEL: + return objc_read_selector (stream, (SEL*)data); + break; + + case _C_CHR: + return objc_read_char (stream, (char*)data); + break; + + case _C_UCHR: + return objc_read_unsigned_char (stream, (unsigned char*)data); + break; + + case _C_SHT: + return objc_read_short (stream, (short*)data); + break; + + case _C_USHT: + return objc_read_unsigned_short (stream, (unsigned short*)data); + break; + + case _C_INT: + return objc_read_int (stream, (int*)data); + break; + + case _C_UINT: + return objc_read_unsigned_int (stream, (unsigned int*)data); + break; + + case _C_LNG: + return objc_read_long (stream, (long*)data); + break; + + case _C_ULNG: + return objc_read_unsigned_long (stream, (unsigned long*)data); + break; + + case _C_CHARPTR: + case _C_ATOM: + return objc_read_string (stream, (char**)data); + break; + + case _C_ARY_B: + { + int len = atoi(type+1); + while (isdigit(*++type)) + ; + return objc_read_array (stream, type, len, data); + } + break; + + case _C_STRUCT_B: + { + int acc_size = 0; + int align; + while (*type != _C_STRUCT_E && *type++ != '=') + ; /* skip "<name>=" */ + while (*type != _C_STRUCT_E) + { + align = objc_alignof_type (type); /* padd to alignment */ + acc_size += ROUND (acc_size, align); + objc_read_type (stream, type, ((char*)data)+acc_size); + acc_size += objc_sizeof_type (type); /* add component size */ + type = objc_skip_typespec (type); /* skip component */ + } + return 1; + } + + default: + { + objc_error(nil, OBJC_ERR_BAD_TYPE, + "objc_read_type: cannot parse typespec: %s\n", type); + return 0; + } + } +} + +/* +** Write the object specified by the template TYPE to STREAM. Last +** arguments specify addresses of values to be written. It might +** seem surprising to specify values by address, but this is extremely +** convenient for copy-paste with objc_read_types calls. A more +** down-to-the-earth cause for this passing of addresses is that values +** of arbitrary size is not well supported in ANSI C for functions with +** variable number of arguments. +*/ + +int +objc_write_types (TypedStream* stream, const char* type, ...) +{ + va_list args; + const char *c; + int res = 0; + + va_start(args, type); + + for (c = type; *c; c = objc_skip_typespec (c)) + { + switch(*c) { + case _C_ID: + res = objc_write_object (stream, *va_arg (args, id*)); + break; + + case _C_CLASS: + res = objc_write_class (stream, *va_arg(args, Class*)); + break; + + case _C_SEL: + res = objc_write_selector (stream, *va_arg(args, SEL*)); + break; + + case _C_CHR: + res = objc_write_char (stream, *va_arg (args, char*)); + break; + + case _C_UCHR: + res = objc_write_unsigned_char (stream, + *va_arg (args, unsigned char*)); + break; + + case _C_SHT: + res = objc_write_short (stream, *va_arg(args, short*)); + break; + + case _C_USHT: + res = objc_write_unsigned_short (stream, + *va_arg(args, unsigned short*)); + break; + + case _C_INT: + res = objc_write_int(stream, *va_arg(args, int*)); + break; + + case _C_UINT: + res = objc_write_unsigned_int(stream, *va_arg(args, unsigned int*)); + break; + + case _C_LNG: + res = objc_write_long(stream, *va_arg(args, long*)); + break; + + case _C_ULNG: + res = objc_write_unsigned_long(stream, *va_arg(args, unsigned long*)); + break; + + case _C_CHARPTR: + { + char** str = va_arg(args, char**); + res = objc_write_string (stream, *str, strlen(*str)); + } + break; + + case _C_ATOM: + { + char** str = va_arg(args, char**); + res = objc_write_string_atomic (stream, *str, strlen(*str)); + } + break; + + case _C_ARY_B: + { + int len = atoi(c+1); + const char* t = c; + while (isdigit(*++t)) + ; + res = objc_write_array (stream, t, len, va_arg(args, void*)); + t = objc_skip_typespec (t); + if (*t != _C_ARY_E) + objc_error(nil, OBJC_ERR_BAD_TYPE, "expected `]', got: %s", t); + } + break; + + default: + objc_error(nil, OBJC_ERR_BAD_TYPE, + "objc_write_types: cannot parse typespec: %s\n", type); + } + } + va_end(args); + return res; +} + + +/* +** Last arguments specify addresses of values to be read. Expected +** type is checked against the type actually present on the stream. +*/ + +int +objc_read_types(TypedStream* stream, const char* type, ...) +{ + va_list args; + const char *c; + int res = 0; + + va_start(args, type); + + for (c = type; *c; c = objc_skip_typespec(c)) + { + switch(*c) { + case _C_ID: + res = objc_read_object(stream, va_arg(args, id*)); + break; + + case _C_CLASS: + res = objc_read_class(stream, va_arg(args, Class*)); + break; + + case _C_SEL: + res = objc_read_selector(stream, va_arg(args, SEL*)); + break; + + case _C_CHR: + res = objc_read_char(stream, va_arg(args, char*)); + break; + + case _C_UCHR: + res = objc_read_unsigned_char(stream, va_arg(args, unsigned char*)); + break; + + case _C_SHT: + res = objc_read_short(stream, va_arg(args, short*)); + break; + + case _C_USHT: + res = objc_read_unsigned_short(stream, va_arg(args, unsigned short*)); + break; + + case _C_INT: + res = objc_read_int(stream, va_arg(args, int*)); + break; + + case _C_UINT: + res = objc_read_unsigned_int(stream, va_arg(args, unsigned int*)); + break; + + case _C_LNG: + res = objc_read_long(stream, va_arg(args, long*)); + break; + + case _C_ULNG: + res = objc_read_unsigned_long(stream, va_arg(args, unsigned long*)); + break; + + case _C_CHARPTR: + case _C_ATOM: + { + char** str = va_arg(args, char**); + res = objc_read_string (stream, str); + } + break; + + case _C_ARY_B: + { + int len = atoi(c+1); + const char* t = c; + while (isdigit(*++t)) + ; + res = objc_read_array (stream, t, len, va_arg(args, void*)); + t = objc_skip_typespec (t); + if (*t != _C_ARY_E) + objc_error(nil, OBJC_ERR_BAD_TYPE, "expected `]', got: %s", t); + } + break; + + default: + objc_error(nil, OBJC_ERR_BAD_TYPE, + "objc_read_types: cannot parse typespec: %s\n", type); + } + } + va_end(args); + return res; +} + +/* +** Write an array of COUNT elements of TYPE from the memory address DATA. +** This is equivalent of objc_write_type (stream, "[N<type>]", data) +*/ + +int +objc_write_array (TypedStream* stream, const char* type, + int count, const void* data) +{ + int off = objc_sizeof_type(type); + const char* where = data; + + while (count-- > 0) + { + objc_write_type(stream, type, where); + where += off; + } + return 1; +} + +/* +** Read an array of COUNT elements of TYPE into the memory address +** DATA. The memory pointed to by data is supposed to be allocated +** by the callee. This is equivalent of +** objc_read_type (stream, "[N<type>]", data) +*/ + +int +objc_read_array (TypedStream* stream, const char* type, + int count, void* data) +{ + int off = objc_sizeof_type(type); + char* where = (char*)data; + + while (count-- > 0) + { + objc_read_type(stream, type, where); + where += off; + } + return 1; +} + +static int +__objc_fread(FILE* file, char* data, int len) +{ + return fread(data, len, 1, file); +} + +static int +__objc_fwrite(FILE* file, char* data, int len) +{ + return fwrite(data, len, 1, file); +} + +static int +__objc_feof(FILE* file) +{ + return feof(file); +} + +static int +__objc_no_write(FILE* file, char* data, int len) +{ + objc_error (nil, OBJC_ERR_NO_WRITE, "TypedStream not open for writing"); + return 0; +} + +static int +__objc_no_read(FILE* file, char* data, int len) +{ + objc_error (nil, OBJC_ERR_NO_READ, "TypedStream not open for reading"); + return 0; +} + +static int +__objc_read_typed_stream_signature (TypedStream* stream) +{ + char buffer[80]; + int pos = 0; + do + (*stream->read)(stream->physical, buffer+pos, 1); + while (buffer[pos++] != '\0') + ; + sscanf (buffer, "GNU TypedStream %d", &stream->version); + if (stream->version != OBJC_TYPED_STREAM_VERSION) + objc_error (nil, OBJC_ERR_STREAM_VERSION, + "cannot handle TypedStream version %d", stream->version); + return 1; +} + +static int +__objc_write_typed_stream_signature (TypedStream* stream) +{ + char buffer[80]; + sprintf(buffer, "GNU TypedStream %d", OBJC_TYPED_STREAM_VERSION); + stream->version = OBJC_TYPED_STREAM_VERSION; + (*stream->write)(stream->physical, buffer, strlen(buffer)+1); + return 1; +} + +static void __objc_finish_write_root_object(struct objc_typed_stream* stream) +{ + hash_delete (stream->object_table); + stream->object_table = hash_new(64, + (hash_func_type)hash_ptr, + (compare_func_type)compare_ptrs); +} + +static void __objc_finish_read_root_object(struct objc_typed_stream* stream) +{ + node_ptr node; + SEL awake_sel = sel_get_any_uid ("awake"); + cache_ptr free_list = hash_new (64, + (hash_func_type) hash_ptr, + (compare_func_type) compare_ptrs); + + /* resolve object forward references */ + for (node = hash_next (stream->object_refs, NULL); node; + node = hash_next (stream->object_refs, node)) + { + struct objc_list* reflist = node->value; + const void* key = node->key; + id object = hash_value_for_key (stream->object_table, key); + while(reflist) + { + *((id*)reflist->head) = object; + if (hash_value_for_key (free_list,reflist) == NULL) + hash_add (&free_list,reflist,reflist); + + reflist = reflist->tail; + } + } + + /* apply __objc_free to all objects stored in free_list */ + for (node = hash_next (free_list, NULL); node; + node = hash_next (free_list, node)) + objc_free ((void *) node->key); + + hash_delete (free_list); + + /* empty object reference table */ + hash_delete (stream->object_refs); + stream->object_refs = hash_new(8, (hash_func_type)hash_ptr, + (compare_func_type)compare_ptrs); + + /* call -awake for all objects read */ + if (awake_sel) + { + for (node = hash_next (stream->object_table, NULL); node; + node = hash_next (stream->object_table, node)) + { + id object = node->value; + if (__objc_responds_to (object, awake_sel)) + (*objc_msg_lookup(object, awake_sel))(object, awake_sel); + } + } + + /* empty object table */ + hash_delete (stream->object_table); + stream->object_table = hash_new(64, + (hash_func_type)hash_ptr, + (compare_func_type)compare_ptrs); +} + +/* +** Open the stream PHYSICAL in MODE +*/ + +TypedStream* +objc_open_typed_stream (FILE* physical, int mode) +{ + TypedStream* s = (TypedStream*)objc_malloc(sizeof(TypedStream)); + + s->mode = mode; + s->physical = physical; + s->stream_table = hash_new(64, + (hash_func_type)hash_ptr, + (compare_func_type)compare_ptrs); + s->object_table = hash_new(64, + (hash_func_type)hash_ptr, + (compare_func_type)compare_ptrs); + s->eof = (objc_typed_eof_func)__objc_feof; + s->flush = (objc_typed_flush_func)fflush; + s->writing_root_p = 0; + if (mode == OBJC_READONLY) + { + s->class_table = hash_new(8, (hash_func_type)hash_string, + (compare_func_type)compare_strings); + s->object_refs = hash_new(8, (hash_func_type)hash_ptr, + (compare_func_type)compare_ptrs); + s->read = (objc_typed_read_func)__objc_fread; + s->write = (objc_typed_write_func)__objc_no_write; + __objc_read_typed_stream_signature (s); + } + else if (mode == OBJC_WRITEONLY) + { + s->class_table = 0; + s->object_refs = 0; + s->read = (objc_typed_read_func)__objc_no_read; + s->write = (objc_typed_write_func)__objc_fwrite; + __objc_write_typed_stream_signature (s); + } + else + { + objc_close_typed_stream (s); + return NULL; + } + s->type = OBJC_FILE_STREAM; + return s; +} + +/* +** Open the file named by FILE_NAME in MODE +*/ + +TypedStream* +objc_open_typed_stream_for_file (const char* file_name, int mode) +{ + FILE* file = NULL; + TypedStream* s; + + if (mode == OBJC_READONLY) + file = fopen (file_name, "r"); + else + file = fopen (file_name, "w"); + + if (file) + { + s = objc_open_typed_stream (file, mode); + if (s) + s->type |= OBJC_MANAGED_STREAM; + return s; + } + else + return NULL; +} + +/* +** Close STREAM freeing the structure it self. If it was opened with +** objc_open_typed_stream_for_file, the file will also be closed. +*/ + +void +objc_close_typed_stream (TypedStream* stream) +{ + if (stream->mode == OBJC_READONLY) + { + __objc_finish_read_root_object (stream); /* Just in case... */ + hash_delete (stream->class_table); + hash_delete (stream->object_refs); + } + + hash_delete (stream->stream_table); + hash_delete (stream->object_table); + + if (stream->type == (OBJC_MANAGED_STREAM | OBJC_FILE_STREAM)) + fclose ((FILE*)stream->physical); + + objc_free(stream); +} + +BOOL +objc_end_of_typed_stream (TypedStream* stream) +{ + return (*stream->eof)(stream->physical); +} + +void +objc_flush_typed_stream (TypedStream* stream) +{ + (*stream->flush)(stream->physical); +} + +long +objc_get_stream_class_version (TypedStream* stream, Class class) +{ + if (stream->class_table) + return PTR2LONG(hash_value_for_key (stream->class_table, class->name)); + else + return class_get_version (class); +} + diff --git a/contrib/gcc/objc/class.c b/contrib/gcc/objc/class.c new file mode 100644 index 000000000000..44aa1b9f98eb --- /dev/null +++ b/contrib/gcc/objc/class.c @@ -0,0 +1,358 @@ +/* GNU Objective C Runtime class related functions + Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup and Dennis Glatting. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include "runtime.h" /* the kitchen sink */ +#include "sarray.h" + +/* The table of classname->class. Used for objc_lookup_class and friends */ +static cache_ptr __objc_class_hash = 0; /* !T:MUTEX */ + +/* This is a hook which is called by objc_get_class and + objc_lookup_class if the runtime is not able to find the class. + This may e.g. try to load in the class using dynamic loading */ +Class (*_objc_lookup_class)(const char* name) = 0; /* !T:SAFE */ + + +/* True when class links has been resolved */ +BOOL __objc_class_links_resolved = NO; /* !T:UNUSED */ + + +/* Initial number of buckets size of class hash table. */ +#define CLASS_HASH_SIZE 32 + +void __objc_init_class_tables() +{ + /* Allocate the class hash table */ + + if(__objc_class_hash) + return; + + objc_mutex_lock(__objc_runtime_mutex); + + __objc_class_hash + = hash_new (CLASS_HASH_SIZE, + (hash_func_type) hash_string, + (compare_func_type) compare_strings); + + objc_mutex_unlock(__objc_runtime_mutex); +} + +/* This function adds a class to the class hash table, and assigns the + class a number, unless it's already known */ +void +__objc_add_class_to_hash(Class class) +{ + Class h_class; + + objc_mutex_lock(__objc_runtime_mutex); + + /* make sure the table is there */ + assert(__objc_class_hash); + + /* make sure it's not a meta class */ + assert(CLS_ISCLASS(class)); + + /* Check to see if the class is already in the hash table. */ + h_class = hash_value_for_key (__objc_class_hash, class->name); + if (!h_class) + { + /* The class isn't in the hash table. Add the class and assign a class + number. */ + static unsigned int class_number = 1; + + CLS_SETNUMBER(class, class_number); + CLS_SETNUMBER(class->class_pointer, class_number); + + ++class_number; + hash_add (&__objc_class_hash, class->name, class); + } + + objc_mutex_unlock(__objc_runtime_mutex); +} + +/* Get the class object for the class named NAME. If NAME does not + identify a known class, the hook _objc_lookup_class is called. If + this fails, nil is returned */ +Class objc_lookup_class (const char* name) +{ + Class class; + + objc_mutex_lock(__objc_runtime_mutex); + + /* Make sure the class hash table exists. */ + assert (__objc_class_hash); + + class = hash_value_for_key (__objc_class_hash, name); + + objc_mutex_unlock(__objc_runtime_mutex); + + if (class) + return class; + + if (_objc_lookup_class) + return (*_objc_lookup_class)(name); + else + return 0; +} + +/* Get the class object for the class named NAME. If NAME does not + identify a known class, the hook _objc_lookup_class is called. If + this fails, an error message is issued and the system aborts */ +Class +objc_get_class (const char *name) +{ + Class class; + + objc_mutex_lock(__objc_runtime_mutex); + + /* Make sure the class hash table exists. */ + assert (__objc_class_hash); + + class = hash_value_for_key (__objc_class_hash, name); + + objc_mutex_unlock(__objc_runtime_mutex); + + if (class) + return class; + + if (_objc_lookup_class) + class = (*_objc_lookup_class)(name); + + if(class) + return class; + + objc_error(nil, OBJC_ERR_BAD_CLASS, + "objc runtime: cannot find class %s\n", name); + return 0; +} + +MetaClass +objc_get_meta_class(const char *name) +{ + return objc_get_class(name)->class_pointer; +} + +/* This function provides a way to enumerate all the classes in the + executable. Pass *ENUM_STATE == NULL to start the enumeration. The + function will return 0 when there are no more classes. + For example: + id class; + void *es = NULL; + while ((class = objc_next_class(&es))) + ... do something with class; +*/ +Class +objc_next_class(void **enum_state) +{ + objc_mutex_lock(__objc_runtime_mutex); + + /* make sure the table is there */ + assert(__objc_class_hash); + + *(node_ptr*)enum_state = + hash_next(__objc_class_hash, *(node_ptr*)enum_state); + + objc_mutex_unlock(__objc_runtime_mutex); + + if (*(node_ptr*)enum_state) + return (*(node_ptr*)enum_state)->value; + return (Class)0; +} + +/* Resolve super/subclass links for all classes. The only thing we + can be sure of is that the class_pointer for class objects point + to the right meta class objects */ +void __objc_resolve_class_links() +{ + node_ptr node; + Class object_class = objc_get_class ("Object"); + + assert(object_class); + + objc_mutex_lock(__objc_runtime_mutex); + + /* Assign subclass links */ + for (node = hash_next (__objc_class_hash, NULL); node; + node = hash_next (__objc_class_hash, node)) + { + Class class1 = node->value; + + /* Make sure we have what we think we have. */ + assert (CLS_ISCLASS(class1)); + assert (CLS_ISMETA(class1->class_pointer)); + + /* The class_pointer of all meta classes point to Object's meta class. */ + class1->class_pointer->class_pointer = object_class->class_pointer; + + if (!(CLS_ISRESOLV(class1))) + { + CLS_SETRESOLV(class1); + CLS_SETRESOLV(class1->class_pointer); + + if(class1->super_class) + { + Class a_super_class + = objc_get_class ((char *) class1->super_class); + + assert (a_super_class); + + DEBUG_PRINTF ("making class connections for: %s\n", + class1->name); + + /* assign subclass links for superclass */ + class1->sibling_class = a_super_class->subclass_list; + a_super_class->subclass_list = class1; + + /* Assign subclass links for meta class of superclass */ + if (a_super_class->class_pointer) + { + class1->class_pointer->sibling_class + = a_super_class->class_pointer->subclass_list; + a_super_class->class_pointer->subclass_list + = class1->class_pointer; + } + } + else /* a root class, make its meta object */ + /* be a subclass of Object */ + { + class1->class_pointer->sibling_class + = object_class->subclass_list; + object_class->subclass_list = class1->class_pointer; + } + } + } + + /* Assign superclass links */ + for (node = hash_next (__objc_class_hash, NULL); node; + node = hash_next (__objc_class_hash, node)) + { + Class class1 = node->value; + Class sub_class; + for (sub_class = class1->subclass_list; sub_class; + sub_class = sub_class->sibling_class) + { + sub_class->super_class = class1; + if(CLS_ISCLASS(sub_class)) + sub_class->class_pointer->super_class = class1->class_pointer; + } + } + + objc_mutex_unlock(__objc_runtime_mutex); +} + + + +#define CLASSOF(c) ((c)->class_pointer) + +Class +class_pose_as (Class impostor, Class super_class) +{ + node_ptr node; + Class class1; + + if (!CLS_ISRESOLV (impostor)) + __objc_resolve_class_links (); + + /* preconditions */ + assert (impostor); + assert (super_class); + assert (impostor->super_class == super_class); + assert (CLS_ISCLASS (impostor)); + assert (CLS_ISCLASS (super_class)); + assert (impostor->instance_size == super_class->instance_size); + + { + Class *subclass = &(super_class->subclass_list); + + /* move subclasses of super_class to impostor */ + while (*subclass) + { + Class nextSub = (*subclass)->sibling_class; + + if (*subclass != impostor) + { + Class sub = *subclass; + + /* classes */ + sub->sibling_class = impostor->subclass_list; + sub->super_class = impostor; + impostor->subclass_list = sub; + + /* It will happen that SUB is not a class object if it is + the top of the meta class hierarchy chain. (root + meta-class objects inherit their class object) If that is + the case... don't mess with the meta-meta class. */ + if (CLS_ISCLASS (sub)) + { + /* meta classes */ + CLASSOF (sub)->sibling_class = + CLASSOF (impostor)->subclass_list; + CLASSOF (sub)->super_class = CLASSOF (impostor); + CLASSOF (impostor)->subclass_list = CLASSOF (sub); + } + } + + *subclass = nextSub; + } + + /* set subclasses of superclass to be impostor only */ + super_class->subclass_list = impostor; + CLASSOF (super_class)->subclass_list = CLASSOF (impostor); + + /* set impostor to have no sibling classes */ + impostor->sibling_class = 0; + CLASSOF (impostor)->sibling_class = 0; + } + + /* check relationship of impostor and super_class is kept. */ + assert (impostor->super_class == super_class); + assert (CLASSOF (impostor)->super_class == CLASSOF (super_class)); + + /* This is how to update the lookup table. Regardless of + what the keys of the hashtable is, change all values that are + superclass into impostor. */ + + objc_mutex_lock(__objc_runtime_mutex); + + for (node = hash_next (__objc_class_hash, NULL); node; + node = hash_next (__objc_class_hash, node)) + { + class1 = (Class)node->value; + if (class1 == super_class) + { + node->value = impostor; /* change hash table value */ + } + } + + objc_mutex_unlock(__objc_runtime_mutex); + + /* next, we update the dispatch tables... */ + __objc_update_dispatch_table_for_class (CLASSOF (impostor)); + __objc_update_dispatch_table_for_class (impostor); + + return impostor; +} + + diff --git a/contrib/gcc/objc/encoding.c b/contrib/gcc/objc/encoding.c new file mode 100644 index 000000000000..e6f84aa04a4f --- /dev/null +++ b/contrib/gcc/objc/encoding.c @@ -0,0 +1,554 @@ +/* Encoding of types for Objective C. + Copyright (C) 1993, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#include "encoding.h" + +#define MAX(X, Y) \ + ({ typeof(X) __x = (X), __y = (Y); \ + (__x > __y ? __x : __y); }) + +#define MIN(X, Y) \ + ({ typeof(X) __x = (X), __y = (Y); \ + (__x < __y ? __x : __y); }) + +#define ROUND(V, A) \ + ({ typeof(V) __v=(V); typeof(A) __a=(A); \ + __a*((__v+__a-1)/__a); }) + + +static inline int +atoi (const char* str) +{ + int res = 0; + + while (isdigit (*str)) + res *= 10, res += (*str++ - '0'); + + return res; +} + +/* + return the size of an object specified by type +*/ + +int +objc_sizeof_type(const char* type) +{ + switch(*type) { + case _C_ID: + return sizeof(id); + break; + + case _C_CLASS: + return sizeof(Class); + break; + + case _C_SEL: + return sizeof(SEL); + break; + + case _C_CHR: + return sizeof(char); + break; + + case _C_UCHR: + return sizeof(unsigned char); + break; + + case _C_SHT: + return sizeof(short); + break; + + case _C_USHT: + return sizeof(unsigned short); + break; + + case _C_INT: + return sizeof(int); + break; + + case _C_UINT: + return sizeof(unsigned int); + break; + + case _C_LNG: + return sizeof(long); + break; + + case _C_ULNG: + return sizeof(unsigned long); + break; + + case _C_FLT: + return sizeof(float); + break; + + case _C_DBL: + return sizeof(double); + break; + + case _C_VOID: + return sizeof(void); + break; + case _C_PTR: + case _C_ATOM: + case _C_CHARPTR: + return sizeof(char*); + break; + + case _C_ARY_B: + { + int len = atoi(type+1); + while (isdigit(*++type)); + return len*objc_aligned_size (type); + } + break; + + case _C_STRUCT_B: + { + int acc_size = 0; + int align; + while (*type != _C_STRUCT_E && *type++ != '='); /* skip "<name>=" */ + while (*type != _C_STRUCT_E) + { + align = objc_alignof_type (type); /* padd to alignment */ + acc_size = ROUND (acc_size, align); + acc_size += objc_sizeof_type (type); /* add component size */ + type = objc_skip_typespec (type); /* skip component */ + } + return acc_size; + } + + case _C_UNION_B: + { + int max_size = 0; + while (*type != _C_UNION_E && *type++ != '=') /* do nothing */; + while (*type != _C_UNION_E) + { + max_size = MAX (max_size, objc_sizeof_type (type)); + type = objc_skip_typespec (type); + } + return max_size; + } + + default: + { + objc_error(nil, OBJC_ERR_BAD_TYPE, "unknown type %s\n", type); + return 0; + } + } +} + + +/* + Return the alignment of an object specified by type +*/ + +int +objc_alignof_type(const char* type) +{ + switch(*type) { + case _C_ID: + return __alignof__(id); + break; + + case _C_CLASS: + return __alignof__(Class); + break; + + case _C_SEL: + return __alignof__(SEL); + break; + + case _C_CHR: + return __alignof__(char); + break; + + case _C_UCHR: + return __alignof__(unsigned char); + break; + + case _C_SHT: + return __alignof__(short); + break; + + case _C_USHT: + return __alignof__(unsigned short); + break; + + case _C_INT: + return __alignof__(int); + break; + + case _C_UINT: + return __alignof__(unsigned int); + break; + + case _C_LNG: + return __alignof__(long); + break; + + case _C_ULNG: + return __alignof__(unsigned long); + break; + + case _C_FLT: + return __alignof__(float); + break; + + case _C_DBL: + return __alignof__(double); + break; + + case _C_PTR: + case _C_ATOM: + case _C_CHARPTR: + return __alignof__(char*); + break; + + case _C_ARY_B: + while (isdigit(*++type)) /* do nothing */; + return objc_alignof_type (type); + + case _C_STRUCT_B: + { + struct { int x; double y; } fooalign; + while(*type != _C_STRUCT_E && *type++ != '=') /* do nothing */; + if (*type != _C_STRUCT_E) + return MAX (objc_alignof_type (type), __alignof__ (fooalign)); + else + return __alignof__ (fooalign); + } + + case _C_UNION_B: + { + int maxalign = 0; + while (*type != _C_UNION_E && *type++ != '=') /* do nothing */; + while (*type != _C_UNION_E) + { + maxalign = MAX (maxalign, objc_alignof_type (type)); + type = objc_skip_typespec (type); + } + return maxalign; + } + + default: + { + objc_error(nil, OBJC_ERR_BAD_TYPE, "unknown type %s\n", type); + return 0; + } + } +} + +/* + The aligned size if the size rounded up to the nearest alignment. +*/ + +int +objc_aligned_size (const char* type) +{ + int size = objc_sizeof_type (type); + int align = objc_alignof_type (type); + return ROUND (size, align); +} + +/* + The size rounded up to the nearest integral of the wordsize, taken + to be the size of a void*. +*/ + +int +objc_promoted_size (const char* type) +{ + int size = objc_sizeof_type (type); + int wordsize = sizeof (void*); + + return ROUND (size, wordsize); +} + +/* + Skip type qualifiers. These may eventually precede typespecs + occurring in method prototype encodings. +*/ + +inline const char* +objc_skip_type_qualifiers (const char* type) +{ + while (*type == _C_CONST + || *type == _C_IN + || *type == _C_INOUT + || *type == _C_OUT + || *type == _C_BYCOPY + || *type == _C_ONEWAY) + { + type += 1; + } + return type; +} + + +/* + Skip one typespec element. If the typespec is prepended by type + qualifiers, these are skipped as well. +*/ + +const char* +objc_skip_typespec (const char* type) +{ + type = objc_skip_type_qualifiers (type); + + switch (*type) { + + case _C_ID: + /* An id may be annotated by the actual type if it is known + with the @"ClassName" syntax */ + + if (*++type != '"') + return type; + else + { + while (*++type != '"') /* do nothing */; + return type + 1; + } + + /* The following are one character type codes */ + case _C_CLASS: + case _C_SEL: + case _C_CHR: + case _C_UCHR: + case _C_CHARPTR: + case _C_ATOM: + case _C_SHT: + case _C_USHT: + case _C_INT: + case _C_UINT: + case _C_LNG: + case _C_ULNG: + case _C_FLT: + case _C_DBL: + case _C_VOID: + case _C_UNDEF: + return ++type; + break; + + case _C_ARY_B: + /* skip digits, typespec and closing ']' */ + + while(isdigit(*++type)); + type = objc_skip_typespec(type); + if (*type == _C_ARY_E) + return ++type; + else + { + objc_error(nil, OBJC_ERR_BAD_TYPE, "bad array type %s\n", type); + return 0; + } + + case _C_STRUCT_B: + /* skip name, and elements until closing '}' */ + + while (*type != _C_STRUCT_E && *type++ != '='); + while (*type != _C_STRUCT_E) { type = objc_skip_typespec (type); } + return ++type; + + case _C_UNION_B: + /* skip name, and elements until closing ')' */ + + while (*type != _C_UNION_E && *type++ != '='); + while (*type != _C_UNION_E) { type = objc_skip_typespec (type); } + return ++type; + + case _C_PTR: + /* Just skip the following typespec */ + + return objc_skip_typespec (++type); + + default: + { + objc_error(nil, OBJC_ERR_BAD_TYPE, "unknown type %s\n", type); + return 0; + } + } +} + +/* + Skip an offset as part of a method encoding. This is prepended by a + '+' if the argument is passed in registers. +*/ +inline const char* +objc_skip_offset (const char* type) +{ + if (*type == '+') type++; + while(isdigit(*++type)); + return type; +} + +/* + Skip an argument specification of a method encoding. +*/ +const char* +objc_skip_argspec (const char* type) +{ + type = objc_skip_typespec (type); + type = objc_skip_offset (type); + return type; +} + +/* + Return the number of arguments that the method MTH expects. + Note that all methods need two implicit arguments `self' and + `_cmd'. +*/ +int +method_get_number_of_arguments (struct objc_method* mth) +{ + int i = 0; + const char* type = mth->method_types; + while (*type) + { + type = objc_skip_argspec (type); + i += 1; + } + return i - 1; +} + +/* + Return the size of the argument block needed on the stack to invoke + the method MTH. This may be zero, if all arguments are passed in + registers. +*/ + +int +method_get_sizeof_arguments (struct objc_method* mth) +{ + const char* type = objc_skip_typespec (mth->method_types); + return atoi (type); +} + +/* + Return a pointer to the next argument of ARGFRAME. type points to + the last argument. Typical use of this look like: + + { + char *datum, *type; + for (datum = method_get_first_argument (method, argframe, &type); + datum; datum = method_get_next_argument (argframe, &type)) + { + unsigned flags = objc_get_type_qualifiers (type); + type = objc_skip_type_qualifiers (type); + if (*type != _C_PTR) + [portal encodeData: datum ofType: type]; + else + { + if ((flags & _F_IN) == _F_IN) + [portal encodeData: *(char**)datum ofType: ++type]; + } + } + } +*/ + +char* +method_get_next_argument (arglist_t argframe, + const char **type) +{ + const char *t = objc_skip_argspec (*type); + + if (*t == '\0') + return 0; + + *type = t; + t = objc_skip_typespec (t); + + if (*t == '+') + return argframe->arg_regs + atoi (++t); + else + return argframe->arg_ptr + atoi (t); +} + +/* + Return a pointer to the value of the first argument of the method + described in M with the given argumentframe ARGFRAME. The type + is returned in TYPE. type must be passed to successive calls of + method_get_next_argument. +*/ +char* +method_get_first_argument (struct objc_method* m, + arglist_t argframe, + const char** type) +{ + *type = m->method_types; + return method_get_next_argument (argframe, type); +} + +/* + Return a pointer to the ARGth argument of the method + M from the frame ARGFRAME. The type of the argument + is returned in the value-result argument TYPE +*/ + +char* +method_get_nth_argument (struct objc_method* m, + arglist_t argframe, int arg, + const char **type) +{ + const char* t = objc_skip_argspec (m->method_types); + + if (arg > method_get_number_of_arguments (m)) + return 0; + + while (arg--) + t = objc_skip_argspec (t); + + *type = t; + t = objc_skip_typespec (t); + + if (*t == '+') + return argframe->arg_regs + atoi (++t); + else + return argframe->arg_ptr + atoi (t); +} + +unsigned +objc_get_type_qualifiers (const char* type) +{ + unsigned res = 0; + BOOL flag = YES; + + while (flag) + switch (*type++) + { + case _C_CONST: res |= _F_CONST; break; + case _C_IN: res |= _F_IN; break; + case _C_INOUT: res |= _F_INOUT; break; + case _C_OUT: res |= _F_OUT; break; + case _C_BYCOPY: res |= _F_BYCOPY; break; + case _C_ONEWAY: res |= _F_ONEWAY; break; + default: flag = NO; + } + + return res; +} diff --git a/contrib/gcc/objc/hash.c b/contrib/gcc/objc/hash.c new file mode 100644 index 000000000000..7534330fa1c7 --- /dev/null +++ b/contrib/gcc/objc/hash.c @@ -0,0 +1,283 @@ +/* Hash tables for Objective C internal structures + Copyright (C) 1993, 1996, 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#include "assert.h" + +#include "objc/hash.h" + +#include "runtime.h" /* for DEBUG_PRINTF */ + +/* These two macros determine when a hash table is full and + by how much it should be expanded respectively. + + These equations are percentages. */ +#define FULLNESS(cache) \ + ((((cache)->size * 75) / 100) <= (cache)->used) +#define EXPANSION(cache) \ + ((cache)->size * 2) + +cache_ptr +hash_new (unsigned int size, hash_func_type hash_func, + compare_func_type compare_func) +{ + cache_ptr cache; + + /* Pass me a value greater than 0 and a power of 2. */ + assert (size); + assert (!(size & (size - 1))); + + /* Allocate the cache structure. calloc insures + its initialization for default values. */ + cache = (cache_ptr) objc_calloc (1, sizeof (struct cache)); + assert (cache); + + /* Allocate the array of buckets for the cache. + calloc initializes all of the pointers to NULL. */ + cache->node_table + = (node_ptr *) objc_calloc (size, sizeof (node_ptr)); + assert (cache->node_table); + + cache->size = size; + + /* This should work for all processor architectures? */ + cache->mask = (size - 1); + + /* Store the hashing function so that codes can be computed. */ + cache->hash_func = hash_func; + + /* Store the function that compares hash keys to + determine if they are equal. */ + cache->compare_func = compare_func; + + return cache; +} + + +void +hash_delete (cache_ptr cache) +{ + node_ptr node; + node_ptr next_node; + unsigned int i; + + /* Purge all key/value pairs from the table. */ + /* Step through the nodes one by one and remove every node WITHOUT + using hash_next. this makes hash_delete much more efficient. */ + for (i = 0;i < cache->size;i++) { + if ((node = cache->node_table[i])) { + /* an entry in the hash table has been found, now step through the + nodes next in the list and free them. */ + while ((next_node = node->next)) { + hash_remove (cache,node->key); + node = next_node; + } + + hash_remove (cache,node->key); + } + } + + /* Release the array of nodes and the cache itself. */ + objc_free(cache->node_table); + objc_free(cache); +} + + +void +hash_add (cache_ptr *cachep, const void *key, void *value) +{ + size_t indx = (*(*cachep)->hash_func)(*cachep, key); + node_ptr node = (node_ptr) objc_calloc (1, sizeof (struct cache_node)); + + + assert (node); + + /* Initialize the new node. */ + node->key = key; + node->value = value; + node->next = (*cachep)->node_table[indx]; + + /* Debugging. + Check the list for another key. */ +#ifdef DEBUG + { node_ptr node1 = (*cachep)->node_table[indx]; + + while (node1) { + + assert (node1->key != key); + node1 = node1->next; + } + } +#endif + + /* Install the node as the first element on the list. */ + (*cachep)->node_table[indx] = node; + + /* Bump the number of entries in the cache. */ + ++(*cachep)->used; + + /* Check the hash table's fullness. We're going + to expand if it is above the fullness level. */ + if (FULLNESS (*cachep)) { + + /* The hash table has reached its fullness level. Time to + expand it. + + I'm using a slow method here but is built on other + primitive functions thereby increasing its + correctness. */ + node_ptr node1 = NULL; + cache_ptr new = hash_new (EXPANSION (*cachep), + (*cachep)->hash_func, + (*cachep)->compare_func); + + DEBUG_PRINTF ("Expanding cache %#x from %d to %d\n", + *cachep, (*cachep)->size, new->size); + + /* Copy the nodes from the first hash table to the new one. */ + while ((node1 = hash_next (*cachep, node1))) + hash_add (&new, node1->key, node1->value); + + /* Trash the old cache. */ + hash_delete (*cachep); + + /* Return a pointer to the new hash table. */ + *cachep = new; + } +} + + +void +hash_remove (cache_ptr cache, const void *key) +{ + size_t indx = (*cache->hash_func)(cache, key); + node_ptr node = cache->node_table[indx]; + + + /* We assume there is an entry in the table. Error if it is not. */ + assert (node); + + /* Special case. First element is the key/value pair to be removed. */ + if ((*cache->compare_func)(node->key, key)) { + cache->node_table[indx] = node->next; + objc_free(node); + } else { + + /* Otherwise, find the hash entry. */ + node_ptr prev = node; + BOOL removed = NO; + + do { + + if ((*cache->compare_func)(node->key, key)) { + prev->next = node->next, removed = YES; + objc_free(node); + } else + prev = node, node = node->next; + } while (!removed && node); + assert (removed); + } + + /* Decrement the number of entries in the hash table. */ + --cache->used; +} + + +node_ptr +hash_next (cache_ptr cache, node_ptr node) +{ + /* If the scan is being started then reset the last node + visitied pointer and bucket index. */ + if (!node) + cache->last_bucket = 0; + + /* If there is a node visited last then check for another + entry in the same bucket; Otherwise step to the next bucket. */ + if (node) { + if (node->next) + /* There is a node which follows the last node + returned. Step to that node and retun it. */ + return node->next; + else + ++cache->last_bucket; + } + + /* If the list isn't exhausted then search the buckets for + other nodes. */ + if (cache->last_bucket < cache->size) { + /* Scan the remainder of the buckets looking for an entry + at the head of the list. Return the first item found. */ + while (cache->last_bucket < cache->size) + if (cache->node_table[cache->last_bucket]) + return cache->node_table[cache->last_bucket]; + else + ++cache->last_bucket; + + /* No further nodes were found in the hash table. */ + return NULL; + } else + return NULL; +} + + +/* Given KEY, return corresponding value for it in CACHE. + Return NULL if the KEY is not recorded. */ + +void * +hash_value_for_key (cache_ptr cache, const void *key) +{ + node_ptr node = cache->node_table[(*cache->hash_func)(cache, key)]; + void *retval = NULL; + + if (node) + do { + if ((*cache->compare_func)(node->key, key)) { + retval = node->value; + break; + } else + node = node->next; + } while (!retval && node); + + return retval; +} + +/* Given KEY, return YES if it exists in the CACHE. + Return NO if it does not */ + +BOOL +hash_is_key_in_hash (cache_ptr cache, const void *key) +{ + node_ptr node = cache->node_table[(*cache->hash_func)(cache, key)]; + + if (node) + do { + if ((*cache->compare_func)(node->key, key)) + return YES; + else + node = node->next; + } while (node); + + return NO; +} diff --git a/contrib/gcc/objc/hash.h b/contrib/gcc/objc/hash.h new file mode 100644 index 000000000000..bddb791c820c --- /dev/null +++ b/contrib/gcc/objc/hash.h @@ -0,0 +1,206 @@ +/* Hash tables for Objective C method dispatch. + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + + +#ifndef __hash_INCLUDE_GNU +#define __hash_INCLUDE_GNU + +#include <stddef.h> +#include <objc/objc.h> + +/* + * This data structure is used to hold items + * stored in a hash table. Each node holds + * a key/value pair. + * + * Items in the cache are really of type void *. + */ +typedef struct cache_node +{ + struct cache_node *next; /* Pointer to next entry on the list. + NULL indicates end of list. */ + const void *key; /* Key used to locate the value. Used + to locate value when more than one + key computes the same hash + value. */ + void *value; /* Value stored for the key. */ +} *node_ptr; + + +/* + * This data type is the function that computes a hash code given a key. + * Therefore, the key can be a pointer to anything and the function specific + * to the key type. + * + * Unfortunately there is a mutual data structure reference problem with this + * typedef. Therefore, to remove compiler warnings the functions passed to + * hash_new will have to be casted to this type. + */ +typedef unsigned int (*hash_func_type)(void *, const void *); + +/* + * This data type is the function that compares two hash keys and returns an + * integer greater than, equal to, or less than 0, according as the first + * parameter is lexicographically greater than, equal to, or less than the + * second. + */ + +typedef int (*compare_func_type)(const void *, const void *); + + +/* + * This data structure is the cache. + * + * It must be passed to all of the hashing routines + * (except for new). + */ +typedef struct cache +{ + /* Variables used to implement the hash itself. */ + node_ptr *node_table; /* Pointer to an array of hash nodes. */ + /* Variables used to track the size of the hash table so to determine + when to resize it. */ + unsigned int size; /* Number of buckets allocated for the hash table + (number of array entries allocated for + "node_table"). Must be a power of two. */ + unsigned int used; /* Current number of entries in the hash table. */ + unsigned int mask; /* Precomputed mask. */ + + /* Variables used to implement indexing through the hash table. */ + + unsigned int last_bucket; /* Tracks which entry in the array where + the last value was returned. */ + /* Function used to compute a hash code given a key. + This function is specified when the hash table is created. */ + hash_func_type hash_func; + /* Function used to compare two hash keys to see if they are equal. */ + compare_func_type compare_func; +} *cache_ptr; + + +/* Two important hash tables. */ +extern cache_ptr module_hash_table, class_hash_table; + +/* Allocate and initialize a hash table. */ + +cache_ptr hash_new (unsigned int size, + hash_func_type hash_func, + compare_func_type compare_func); + +/* Deallocate all of the hash nodes and the cache itself. */ + +void hash_delete (cache_ptr cache); + +/* Add the key/value pair to the hash table. If the + hash table reaches a level of fullness then it will be resized. + + assert if the key is already in the hash. */ + +void hash_add (cache_ptr *cachep, const void *key, void *value); + +/* Remove the key/value pair from the hash table. + assert if the key isn't in the table. */ + +void hash_remove (cache_ptr cache, const void *key); + +/* Used to index through the hash table. Start with NULL + to get the first entry. + + Successive calls pass the value returned previously. + ** Don't modify the hash during this operation *** + + Cache nodes are returned such that key or value can + be extracted. */ + +node_ptr hash_next (cache_ptr cache, node_ptr node); + +/* Used to return a value from a hash table using a given key. */ + +void *hash_value_for_key (cache_ptr cache, const void *key); + +/* Used to determine if the given key exists in the hash table */ + +BOOL hash_is_key_in_hash (cache_ptr cache, const void *key); + +/************************************************ + + Useful hashing functions. + + Declared inline for your pleasure. + +************************************************/ + +/* Calculate a hash code by performing some + manipulation of the key pointer. (Use the lowest bits + except for those likely to be 0 due to alignment.) */ + +static inline unsigned int +hash_ptr (cache_ptr cache, const void *key) +{ + return ((size_t)key / sizeof (void *)) & cache->mask; +} + + +/* Calculate a hash code by iterating over a NULL + terminate string. */ +static inline unsigned int +hash_string (cache_ptr cache, const void *key) +{ + unsigned int ret = 0; + unsigned int ctr = 0; + + + while (*(char*)key) { + ret ^= *(char*)key++ << ctr; + ctr = (ctr + 1) % sizeof (void *); + } + + return ret & cache->mask; +} + + +/* Compare two pointers for equality. */ +static inline int +compare_ptrs (const void *k1, const void *k2) +{ + return !(k1 - k2); +} + + +/* Compare two strings. */ +static inline int +compare_strings (const void *k1, const void *k2) +{ + if (k1 == k2) + return 1; + else if (k1 == 0 || k2 == 0) + return 0; + else + return !strcmp (k1, k2); +} + + +#endif /* not __hash_INCLUDE_GNU */ diff --git a/contrib/gcc/objc/init.c b/contrib/gcc/objc/init.c new file mode 100644 index 000000000000..f1fea8123186 --- /dev/null +++ b/contrib/gcc/objc/init.c @@ -0,0 +1,834 @@ +/* GNU Objective C Runtime initialization + Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +load support contributed by Ovidiu Predescu <ovidiu@net-community.com> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include "runtime.h" + +/* The version number of this runtime. This must match the number + defined in gcc (objc-act.c) */ +#define OBJC_VERSION 8 +#define PROTOCOL_VERSION 2 + +/* This list contains all modules currently loaded into the runtime */ +static struct objc_list* __objc_module_list = 0; /* !T:MUTEX */ + +/* This list contains all proto_list's not yet assigned class links */ +static struct objc_list* unclaimed_proto_list = 0; /* !T:MUTEX */ + +/* List of unresolved static instances. */ +static struct objc_list *uninitialized_statics = 0; /* !T:MUTEX */ + +/* Global runtime "write" mutex. */ +objc_mutex_t __objc_runtime_mutex = 0; + +/* Number of threads that are alive. */ +int __objc_runtime_threads_alive = 1; /* !T:MUTEX */ + +/* Check compiler vs runtime version */ +static void init_check_module_version (Module_t); + +/* Assign isa links to protos */ +static void __objc_init_protocols (struct objc_protocol_list* protos); + +/* Add protocol to class */ +static void __objc_class_add_protocols (Class, struct objc_protocol_list*); + +/* This is a hook which is called by __objc_exec_class every time a class + or a category is loaded into the runtime. This may e.g. help a + dynamic loader determine the classes that have been loaded when + an object file is dynamically linked in */ +void (*_objc_load_callback)(Class class, Category* category); /* !T:SAFE */ + +/* Is all categories/classes resolved? */ +BOOL __objc_dangling_categories = NO; /* !T:UNUSED */ + +extern SEL +__sel_register_typed_name (const char *name, const char *types, + struct objc_selector *orig, BOOL is_const); + +/* Sends +load to all classes and categories in certain situations. */ +static void objc_send_load (void); + +/* Inserts all the classes defined in module in a tree of classes that + resembles the class hierarchy. This tree is traversed in preorder and the + classes in its nodes receive the +load message if these methods were not + executed before. The algorithm ensures that when the +load method of a class + is executed all the superclasses have been already received the +load + message. */ +static void __objc_create_classes_tree (Module_t module); + +static void __objc_call_callback (Module_t module); + +/* A special version that works only before the classes are completely + installed in the runtime. */ +static BOOL class_is_subclass_of_class (Class class, Class superclass); + +typedef struct objc_class_tree { + Class class; + struct objc_list *subclasses; /* `head' is pointer to an objc_class_tree */ +} objc_class_tree; + +/* This is a linked list of objc_class_tree trees. The head of these trees + are root classes (their super class is Nil). These different trees + represent different class hierarchies. */ +static struct objc_list *__objc_class_tree_list = NULL; + +/* Keeps the +load methods who have been already executed. This hash should + not be destroyed during the execution of the program. */ +static cache_ptr __objc_load_methods = NULL; + +/* Creates a tree of classes whose topmost class is directly inherited from + `upper' and the bottom class in this tree is `bottom_class'. The classes + in this tree are super classes of `bottom_class'. `subclasses' member + of each tree node point to the next subclass tree node. */ +static objc_class_tree * +create_tree_of_subclasses_inherited_from (Class bottom_class, Class upper) +{ + Class superclass = bottom_class->super_class ? + objc_lookup_class ((char*)bottom_class->super_class) + : Nil; + + objc_class_tree *tree, *prev; + + DEBUG_PRINTF ("create_tree_of_subclasses_inherited_from:"); + DEBUG_PRINTF ("bottom_class = %s, upper = %s\n", + (bottom_class ? bottom_class->name : NULL), + (upper ? upper->name : NULL)); + + tree = prev = objc_calloc (1, sizeof (objc_class_tree)); + prev->class = bottom_class; + + while (superclass != upper) + { + tree = objc_calloc (1, sizeof (objc_class_tree)); + tree->class = superclass; + tree->subclasses = list_cons (prev, tree->subclasses); + superclass = (superclass->super_class ? + objc_lookup_class ((char*)superclass->super_class) + : Nil); + prev = tree; + } + + return tree; +} + +/* Insert the `class' into the proper place in the `tree' class hierarchy. This + function returns a new tree if the class has been successfully inserted into + the tree or NULL if the class is not part of the classes hierarchy described + by `tree'. This function is private to objc_tree_insert_class(), you should + not call it directly. */ +static objc_class_tree * +__objc_tree_insert_class (objc_class_tree *tree, Class class) +{ + DEBUG_PRINTF ("__objc_tree_insert_class: tree = %x, class = %s\n", + tree, class->name); + + if (tree == NULL) + return create_tree_of_subclasses_inherited_from (class, NULL); + else if (class == tree->class) + { + /* `class' has been already inserted */ + DEBUG_PRINTF ("1. class %s was previously inserted\n", class->name); + return tree; + } + else if ((class->super_class ? + objc_lookup_class ((char*)class->super_class) + : Nil) + == tree->class) + { + /* If class is a direct subclass of tree->class then add class to the + list of subclasses. First check to see if it wasn't already + inserted. */ + struct objc_list *list = tree->subclasses; + objc_class_tree *node; + + while (list) + { + /* Class has been already inserted; do nothing just return + the tree. */ + if (((objc_class_tree*)list->head)->class == class) + { + DEBUG_PRINTF ("2. class %s was previously inserted\n", + class->name); + return tree; + } + list = list->tail; + } + + /* Create a new node class and insert it into the list of subclasses */ + node = objc_calloc (1, sizeof (objc_class_tree)); + node->class = class; + tree->subclasses = list_cons (node, tree->subclasses); + DEBUG_PRINTF ("3. class %s inserted\n", class->name); + return tree; + } + else + { + /* The class is not a direct subclass of tree->class. Search for class's + superclasses in the list of subclasses. */ + struct objc_list *subclasses = tree->subclasses; + + /* Precondition: the class must be a subclass of tree->class; otherwise + return NULL to indicate our caller that it must take the next tree. */ + if (!class_is_subclass_of_class (class, tree->class)) + return NULL; + + for (; subclasses != NULL; subclasses = subclasses->tail) + { + Class aClass = ((objc_class_tree*)(subclasses->head))->class; + + if (class_is_subclass_of_class (class, aClass)) + { + /* If we found one of class's superclasses we insert the class + into its subtree and return the original tree since nothing + has been changed. */ + subclasses->head + = __objc_tree_insert_class (subclasses->head, class); + DEBUG_PRINTF ("4. class %s inserted\n", class->name); + return tree; + } + } + + /* We haven't found a subclass of `class' in the `subclasses' list. + Create a new tree of classes whose topmost class is a direct subclass + of tree->class. */ + { + objc_class_tree *new_tree + = create_tree_of_subclasses_inherited_from (class, tree->class); + tree->subclasses = list_cons (new_tree, tree->subclasses); + DEBUG_PRINTF ("5. class %s inserted\n", class->name); + return tree; + } + } +} + +/* This function inserts `class' in the right tree hierarchy classes. */ +static void +objc_tree_insert_class (Class class) +{ + struct objc_list *list_node; + objc_class_tree *tree; + + list_node = __objc_class_tree_list; + while (list_node) + { + tree = __objc_tree_insert_class (list_node->head, class); + if (tree) + { + list_node->head = tree; + break; + } + else + list_node = list_node->tail; + } + + /* If the list was finished but the class hasn't been inserted, insert it + here. */ + if (!list_node) + { + __objc_class_tree_list = list_cons (NULL, __objc_class_tree_list); + __objc_class_tree_list->head = __objc_tree_insert_class (NULL, class); + } +} + +/* Traverse tree in preorder. Used to send +load. */ +static void +objc_preorder_traverse (objc_class_tree *tree, + int level, + void (*function)(objc_class_tree*, int)) +{ + struct objc_list *node; + + (*function) (tree, level); + for (node = tree->subclasses; node; node = node->tail) + objc_preorder_traverse (node->head, level + 1, function); +} + +/* Traverse tree in postorder. Used to destroy a tree. */ +static void +objc_postorder_traverse (objc_class_tree *tree, + int level, + void (*function)(objc_class_tree*, int)) +{ + struct objc_list *node; + + for (node = tree->subclasses; node; node = node->tail) + objc_postorder_traverse (node->head, level + 1, function); + (*function) (tree, level); +} + +/* Used to print a tree class hierarchy. */ +#ifdef DEBUG +static void +__objc_tree_print (objc_class_tree *tree, int level) +{ + int i; + + for (i = 0; i < level; i++) + printf (" "); + printf ("%s\n", tree->class->name); +} +#endif + +/* Walks on a linked list of methods in the reverse order and executes all + the methods corresponding to `op' selector. Walking in the reverse order + assures the +load of class is executed first and then +load of categories + because of the way in which categories are added to the class methods. */ +static void +__objc_send_message_in_list (MethodList_t method_list, Class class, SEL op) +{ + int i; + + if (!method_list) + return; + + /* First execute the `op' message in the following method lists */ + __objc_send_message_in_list (method_list->method_next, class, op); + + /* Search the method list. */ + for (i = 0; i < method_list->method_count; i++) + { + Method_t mth = &method_list->method_list[i]; + + if (mth->method_name && sel_eq (mth->method_name, op) + && !hash_is_key_in_hash (__objc_load_methods, mth->method_name)) + { + /* The method was found and wasn't previously executed. */ + (*mth->method_imp) ((id)class, mth->method_name); + + /* Add this method into the +load hash table */ + hash_add (&__objc_load_methods, mth->method_imp, mth->method_imp); + + DEBUG_PRINTF ("sending +load in class: %s\n", class->name); + + break; + } + } +} + +static void +__objc_send_load (objc_class_tree *tree, int level) +{ + static SEL load_sel = 0; + Class class = tree->class; + MethodList_t method_list = class->class_pointer->methods; + + if (!load_sel) + load_sel = sel_register_name ("load"); + + __objc_send_message_in_list (method_list, class, load_sel); +} + +static void +__objc_destroy_class_tree_node (objc_class_tree *tree, int level) +{ + objc_free (tree); +} + +/* This is used to check if the relationship between two classes before the + runtime completely installs the classes. */ +static BOOL +class_is_subclass_of_class (Class class, Class superclass) +{ + for (; class != Nil;) + { + if (class == superclass) + return YES; + class = (class->super_class ? + objc_lookup_class ((char*)class->super_class) + : Nil); + } + + return NO; +} + +/* This list contains all the classes in the runtime system for whom their + superclasses are not yet know to the runtime. */ +static struct objc_list* unresolved_classes = 0; + +/* Static function used to reference the Object and NXConstantString classes. + */ +static void +__objc_force_linking (void) +{ + extern void __objc_linking (void); + __objc_linking (); + + /* Call the function to avoid compiler warning */ + __objc_force_linking (); +} + +/* Run through the statics list, removing modules as soon as all its statics + have been initialized. */ +static void +objc_init_statics (void) +{ + struct objc_list **cell = &uninitialized_statics; + struct objc_static_instances **statics_in_module; + + objc_mutex_lock(__objc_runtime_mutex); + + while (*cell) + { + int module_initialized = 1; + + for (statics_in_module = (*cell)->head; + *statics_in_module; statics_in_module++) + { + struct objc_static_instances *statics = *statics_in_module; + Class class = objc_lookup_class (statics->class_name); + + if (!class) + module_initialized = 0; + /* Actually, the static's class_pointer will be NULL when we + haven't been here before. However, the comparison is to be + reminded of taking into account class posing and to think about + possible semantics... */ + else if (class != statics->instances[0]->class_pointer) + { + id *inst; + + for (inst = &statics->instances[0]; *inst; inst++) + { + (*inst)->class_pointer = class; + + /* ??? Make sure the object will not be freed. With + refcounting, invoke `-retain'. Without refcounting, do + nothing and hope that `-free' will never be invoked. */ + + /* ??? Send the object an `-initStatic' or something to + that effect now or later on? What are the semantics of + statically allocated instances, besides the trivial + NXConstantString, anyway? */ + } + } + } + if (module_initialized) + { + /* Remove this module from the uninitialized list. */ + struct objc_list *this = *cell; + *cell = this->tail; + objc_free(this); + } + else + cell = &(*cell)->tail; + } + + objc_mutex_unlock(__objc_runtime_mutex); +} /* objc_init_statics */ + +/* This function is called by constructor functions generated for each + module compiled. (_GLOBAL_$I$...) The purpose of this function is to + gather the module pointers so that they may be processed by the + initialization routines as soon as possible */ + +void +__objc_exec_class (Module_t module) +{ + /* Have we processed any constructors previously? This flag is used to + indicate that some global data structures need to be built. */ + static BOOL previous_constructors = 0; + + static struct objc_list* unclaimed_categories = 0; + + /* The symbol table (defined in objc-api.h) generated by gcc */ + Symtab_t symtab = module->symtab; + + /* The statics in this module */ + struct objc_static_instances **statics + = symtab->defs[symtab->cls_def_cnt + symtab->cat_def_cnt]; + + /* Entry used to traverse hash lists */ + struct objc_list** cell; + + /* The table of selector references for this module */ + SEL selectors = symtab->refs; + + /* dummy counter */ + int i; + + DEBUG_PRINTF ("received module: %s\n", module->name); + + /* check gcc version */ + init_check_module_version(module); + + /* On the first call of this routine, initialize some data structures. */ + if (!previous_constructors) + { + /* Initialize thread-safe system */ + __objc_init_thread_system(); + __objc_runtime_threads_alive = 1; + __objc_runtime_mutex = objc_mutex_allocate(); + + __objc_init_selector_tables(); + __objc_init_class_tables(); + __objc_init_dispatch_tables(); + __objc_class_tree_list = list_cons (NULL, __objc_class_tree_list); + __objc_load_methods + = hash_new (128, (hash_func_type)hash_ptr, compare_ptrs); + previous_constructors = 1; + } + + /* Save the module pointer for later processing. (not currently used) */ + objc_mutex_lock(__objc_runtime_mutex); + __objc_module_list = list_cons(module, __objc_module_list); + + /* Replace referenced selectors from names to SEL's. */ + if (selectors) + { + for (i = 0; selectors[i].sel_id; ++i) + { + const char *name, *type; + name = (char*)selectors[i].sel_id; + type = (char*)selectors[i].sel_types; + /* Constructors are constant static data so we can safely store + pointers to them in the runtime structures. is_const == YES */ + __sel_register_typed_name (name, type, + (struct objc_selector*)&(selectors[i]), + YES); + } + } + + /* Parse the classes in the load module and gather selector information. */ + DEBUG_PRINTF ("gathering selectors from module: %s\n", module->name); + for (i = 0; i < symtab->cls_def_cnt; ++i) + { + Class class = (Class) symtab->defs[i]; + const char* superclass = (char*)class->super_class; + + /* Make sure we have what we think. */ + assert (CLS_ISCLASS(class)); + assert (CLS_ISMETA(class->class_pointer)); + DEBUG_PRINTF ("phase 1, processing class: %s\n", class->name); + + /* Initialize the subclass list to be NULL. + In some cases it isn't and this crashes the program. */ + class->subclass_list = NULL; + + /* Store the class in the class table and assign class numbers. */ + __objc_add_class_to_hash (class); + + /* Register all of the selectors in the class and meta class. */ + __objc_register_selectors_from_class (class); + __objc_register_selectors_from_class ((Class) class->class_pointer); + + /* Install the fake dispatch tables */ + __objc_install_premature_dtable(class); + __objc_install_premature_dtable(class->class_pointer); + + /* Register the instance methods as class methods, this is + only done for root classes. */ + __objc_register_instance_methods_to_class(class); + + if (class->protocols) + __objc_init_protocols (class->protocols); + + /* Check to see if the superclass is known in this point. If it's not + add the class to the unresolved_classes list. */ + if (superclass && !objc_lookup_class (superclass)) + unresolved_classes = list_cons (class, unresolved_classes); + } + + /* Process category information from the module. */ + for (i = 0; i < symtab->cat_def_cnt; ++i) + { + Category_t category = symtab->defs[i + symtab->cls_def_cnt]; + Class class = objc_lookup_class (category->class_name); + + /* If the class for the category exists then append its methods. */ + if (class) + { + + DEBUG_PRINTF ("processing categories from (module,object): %s, %s\n", + module->name, + class->name); + + /* Do instance methods. */ + if (category->instance_methods) + class_add_method_list (class, category->instance_methods); + + /* Do class methods. */ + if (category->class_methods) + class_add_method_list ((Class) class->class_pointer, + category->class_methods); + + if (category->protocols) + { + __objc_init_protocols (category->protocols); + __objc_class_add_protocols (class, category->protocols); + } + + /* Register the instance methods as class methods, this is + only done for root classes. */ + __objc_register_instance_methods_to_class(class); + } + else + { + /* The object to which the category methods belong can't be found. + Save the information. */ + unclaimed_categories = list_cons(category, unclaimed_categories); + } + } + + if (statics) + uninitialized_statics = list_cons (statics, uninitialized_statics); + if (uninitialized_statics) + objc_init_statics (); + + /* Scan the unclaimed category hash. Attempt to attach any unclaimed + categories to objects. */ + for (cell = &unclaimed_categories; + *cell; + ({ if (*cell) cell = &(*cell)->tail; })) + { + Category_t category = (*cell)->head; + Class class = objc_lookup_class (category->class_name); + + if (class) + { + DEBUG_PRINTF ("attaching stored categories to object: %s\n", + class->name); + + list_remove_head (cell); + + if (category->instance_methods) + class_add_method_list (class, category->instance_methods); + + if (category->class_methods) + class_add_method_list ((Class) class->class_pointer, + category->class_methods); + + if (category->protocols) + { + __objc_init_protocols (category->protocols); + __objc_class_add_protocols (class, category->protocols); + } + + /* Register the instance methods as class methods, this is + only done for root classes. */ + __objc_register_instance_methods_to_class(class); + } + } + + if (unclaimed_proto_list && objc_lookup_class ("Protocol")) + { + list_mapcar (unclaimed_proto_list,(void(*)(void*))__objc_init_protocols); + list_free (unclaimed_proto_list); + unclaimed_proto_list = 0; + } + + objc_send_load (); + + objc_mutex_unlock(__objc_runtime_mutex); +} + +static void objc_send_load (void) +{ + if (!__objc_module_list) + return; + + /* Try to find out if all the classes loaded so far also have their + superclasses known to the runtime. We suppose that the objects that are + allocated in the +load method are in general of a class declared in the + same module. */ + if (unresolved_classes) + { + Class class = unresolved_classes->head; + + while (objc_lookup_class ((char*)class->super_class)) + { + list_remove_head (&unresolved_classes); + if (unresolved_classes) + class = unresolved_classes->head; + else + break; + } + + /* + * If we still have classes for whom we don't have yet their super + * classes known to the runtime we don't send the +load messages. + */ + if (unresolved_classes) + return; + } + + /* Special check to allow creating and sending messages to constant strings + in +load methods. If these classes are not yet known, even if all the + other classes are known, delay sending of +load. */ + if (!objc_lookup_class ("NXConstantString") || + !objc_lookup_class ("Object")) + return; + + /* Iterate over all modules in the __objc_module_list and call on them the + __objc_create_classes_tree function. This function creates a tree of + classes that resembles the class hierarchy. */ + list_mapcar (__objc_module_list, (void(*)(void*))__objc_create_classes_tree); + + while (__objc_class_tree_list) + { +#ifdef DEBUG + objc_preorder_traverse (__objc_class_tree_list->head, + 0, __objc_tree_print); +#endif + objc_preorder_traverse (__objc_class_tree_list->head, + 0, __objc_send_load); + objc_postorder_traverse (__objc_class_tree_list->head, + 0, __objc_destroy_class_tree_node); + list_remove_head (&__objc_class_tree_list); + } + + list_mapcar (__objc_module_list, (void(*)(void*))__objc_call_callback); + list_free (__objc_module_list); + __objc_module_list = NULL; +} + +static void +__objc_create_classes_tree (Module_t module) +{ + /* The runtime mutex is locked in this point */ + + Symtab_t symtab = module->symtab; + int i; + + /* Iterate thru classes defined in this module and insert them in the classes + tree hierarchy. */ + for (i = 0; i < symtab->cls_def_cnt; i++) + { + Class class = (Class) symtab->defs[i]; + + objc_tree_insert_class (class); + } +} + +static void +__objc_call_callback (Module_t module) +{ + /* The runtime mutex is locked in this point */ + + Symtab_t symtab = module->symtab; + int i; + + /* Iterate thru classes defined in this module and call the callback for + each one. */ + for (i = 0; i < symtab->cls_def_cnt; i++) + { + Class class = (Class) symtab->defs[i]; + + /* Call the _objc_load_callback for this class. */ + if (_objc_load_callback) + _objc_load_callback(class, 0); + } + + /* Call the _objc_load_callback for categories. Don't register the instance + methods as class methods for categories to root classes since they were + already added in the class. */ + for (i = 0; i < symtab->cat_def_cnt; i++) + { + Category_t category = symtab->defs[i + symtab->cls_def_cnt]; + Class class = objc_lookup_class (category->class_name); + + if (_objc_load_callback) + _objc_load_callback(class, category); + } +} + +/* Sanity check the version of gcc used to compile `module'*/ +static void init_check_module_version(Module_t module) +{ + if ((module->version != OBJC_VERSION) || (module->size != sizeof (Module))) + { + int code; + + if(module->version > OBJC_VERSION) + code = OBJC_ERR_OBJC_VERSION; + else if (module->version < OBJC_VERSION) + code = OBJC_ERR_GCC_VERSION; + else + code = OBJC_ERR_MODULE_SIZE; + + objc_error(nil, code, "Module %s version %d doesn't match runtime %d\n", + module->name, (int)module->version, OBJC_VERSION); + } +} + +static void +__objc_init_protocols (struct objc_protocol_list* protos) +{ + int i; + static Class proto_class = 0; + + if (! protos) + return; + + objc_mutex_lock(__objc_runtime_mutex); + + if (!proto_class) + proto_class = objc_lookup_class("Protocol"); + + if (!proto_class) + { + unclaimed_proto_list = list_cons (protos, unclaimed_proto_list); + objc_mutex_unlock(__objc_runtime_mutex); + return; + } + +#if 0 + assert (protos->next == 0); /* only single ones allowed */ +#endif + + for(i = 0; i < protos->count; i++) + { + struct objc_protocol* aProto = protos->list[i]; + if (((size_t)aProto->class_pointer) == PROTOCOL_VERSION) + { + /* assign class pointer */ + aProto->class_pointer = proto_class; + + /* init super protocols */ + __objc_init_protocols (aProto->protocol_list); + } + else if (protos->list[i]->class_pointer != proto_class) + { + objc_error(nil, OBJC_ERR_PROTOCOL_VERSION, + "Version %d doesn't match runtime protocol version %d\n", + (int)((char*)protos->list[i]->class_pointer-(char*)0), + PROTOCOL_VERSION); + } + } + + objc_mutex_unlock(__objc_runtime_mutex); +} + +static void __objc_class_add_protocols (Class class, + struct objc_protocol_list* protos) +{ + /* Well... */ + if (! protos) + return; + + /* Add it... */ + protos->next = class->protocols; + class->protocols = protos; +} diff --git a/contrib/gcc/objc/libobjc.def b/contrib/gcc/objc/libobjc.def new file mode 100644 index 000000000000..a4a6049e816f --- /dev/null +++ b/contrib/gcc/objc/libobjc.def @@ -0,0 +1,161 @@ +; GNU Objective C Runtime DLL Export Definitions +; Copyright (C) 1997 Free Software Foundation, Inc. +; Contributed by Scott Christley <scottc@net-community.com> +; +; This file is part of GNU CC. +; +; GNU CC is free software; you can redistribute it and/or modify it under the +; terms of the GNU General Public License as published by the Free Software +; Foundation; either version 2, or (at your option) any later version. +; +; GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +; FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +; details. +; +; You should have received a copy of the GNU General Public License along with +; GNU CC; see the file COPYING. If not, write to the Free Software +; Foundation, 59 Temple Place - Suite 330, +; Boston, MA 02111-1307, USA. + +LIBRARY libobjc +EXPORTS +search_for_method_in_list +objc_get_uninstalled_dtable +hash_is_key_in_hash +objc_verror +_objc_load_callback +objc_malloc +objc_atomic_malloc +objc_valloc +objc_realloc +objc_calloc +objc_free +__objc_init_thread_system +objc_mutex_allocate +objc_mutex_deallocate +objc_mutex_lock +objc_mutex_trylock +objc_mutex_unlock +objc_thread_detach +objc_thread_exit +objc_thread_get_data +objc_thread_get_priority +objc_thread_id +objc_thread_set_data +objc_thread_set_priority +objc_thread_yield +__objc_class_name_Object +__objc_class_name_Protocol +__objc_class_name_NXConstantString +objc_error +__objc_object_alloc +__objc_object_copy +__objc_object_dispose +class_create_instance +object_copy +object_dispose +__objc_init_selector_tables +__objc_register_selectors_from_class +__sel_register_typed_name +sel_get_any_typed_uid +sel_get_any_uid +sel_get_name +sel_get_type +sel_get_typed_uid +sel_get_uid +sel_is_mapped +sel_register_name +sel_register_typed_name +sel_types_match +method_get_first_argument +method_get_next_argument +method_get_nth_argument +method_get_number_of_arguments +method_get_sizeof_arguments +objc_aligned_size +objc_alignof_type +objc_get_type_qualifiers +objc_promoted_size +objc_sizeof_type +objc_skip_argspec +objc_skip_offset +objc_skip_type_qualifiers +objc_skip_typespec +__objc_read_nbyte_uint +__objc_read_nbyte_ulong +__objc_write_class +__objc_write_object +__objc_write_selector +objc_close_typed_stream +objc_end_of_typed_stream +objc_flush_typed_stream +objc_get_stream_class_version +objc_open_typed_stream +objc_open_typed_stream_for_file +objc_read_array +objc_read_char +objc_read_int +objc_read_long +objc_read_object +objc_read_selector +objc_read_short +objc_read_string +objc_read_type +objc_read_types +objc_read_unsigned_char +objc_read_unsigned_int +objc_read_unsigned_long +objc_read_unsigned_short +objc_write_array +objc_write_char +objc_write_int +objc_write_long +objc_write_object +objc_write_object_reference +objc_write_root_object +objc_write_selector +objc_write_short +objc_write_string +objc_write_string_atomic +objc_write_type +objc_write_types +objc_write_unsigned_char +objc_write_unsigned_int +objc_write_unsigned_long +objc_write_unsigned_short +__objc_exec_class +__objc_init_dispatch_tables +__objc_install_premature_dtable +__objc_print_dtable_stats +__objc_responds_to +__objc_update_dispatch_table_for_class +class_add_method_list +class_get_class_method +class_get_instance_method +get_imp +nil_method +objc_msg_lookup +objc_msg_lookup_super +objc_msg_sendv +__objc_add_class_to_hash +__objc_init_class_tables +__objc_resolve_class_links +class_pose_as +objc_get_class +objc_get_meta_class +objc_lookup_class +objc_next_class +sarray_at_put +sarray_at_put_safe +sarray_free +sarray_lazy_copy +sarray_new +sarray_realloc +sarray_remove_garbage +hash_add +hash_delete +hash_new +hash_next +hash_remove +hash_value_for_key diff --git a/contrib/gcc/objc/libobjc_entry.c b/contrib/gcc/objc/libobjc_entry.c new file mode 100644 index 000000000000..2d584ab3c1ef --- /dev/null +++ b/contrib/gcc/objc/libobjc_entry.c @@ -0,0 +1,55 @@ +/* GNU Objective C Runtime DLL Entry + Copyright (C) 1997 Free Software Foundation, Inc. + Contributed by Scott Christley <scottc@net-community.com> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <windows.h> + +/* + DLL entry function for Objective-C Runtime library + This function gets called everytime a process/thread attaches to DLL + */ +WINBOOL WINAPI DllMain(HANDLE hInst, ULONG ul_reason_for_call, + LPVOID lpReserved) +{ + switch(ul_reason_for_call) + { + case DLL_PROCESS_ATTACH: + break; + case DLL_PROCESS_DETACH: + break; + case DLL_THREAD_ATTACH: + break; + case DLL_THREAD_DETACH: + break; + } + return TRUE; +} + +/* + This section terminates the list of imports under GCC. If you do not + include this then you will have problems when linking with DLLs. + */ +asm (".section .idata$3\n" ".long 0,0,0,0,0,0,0,0"); diff --git a/contrib/gcc/objc/linking.m b/contrib/gcc/objc/linking.m new file mode 100644 index 000000000000..8ecca0281106 --- /dev/null +++ b/contrib/gcc/objc/linking.m @@ -0,0 +1,40 @@ +/* Force linking of classes required by Objective C runtime. + Copyright (C) 1997 Free Software Foundation, Inc. + Contributed by Ovidiu Predescu (ovidiu@net-community.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <objc/Object.h> +#include <objc/NXConstStr.h> + +/* Generate references to Object and NXConstanstString classes since they are + needed by the runtime system to run correctly. */ + + +void __objc_linking (void) +{ + [Object name]; + [NXConstantString name]; +} + diff --git a/contrib/gcc/objc/makefile.dos b/contrib/gcc/objc/makefile.dos new file mode 100644 index 000000000000..3e1b1871e40e --- /dev/null +++ b/contrib/gcc/objc/makefile.dos @@ -0,0 +1,56 @@ +# GNU Objective C Runtime Makefile for compiling with djgpp +# Copyright (C) 1993, 1994, 1996 Free Software Foundation, Inc. +# +# This file is part of GNU CC. +# +# GNU CC is free software; you can redistribute it and/or modify it under the +# terms of the GNU General Public License as published by the Free Software +# Foundation; either version 2, or (at your option) any later version. +# +# GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +# details. +# +# You should have received a copy of the GNU General Public License along with +# GNU CC; see the file COPYING. If not, write to the Free Software +# Foundation, 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. + +# This Makefile is configured for GnuMAKE + +GCC_FOR_TARGET=gcc + +.SUFFIXES: .o .m + +OPTIMIZE = -O2 + +# Always search these dirs when compiling. +SUBDIR_INCLUDES = -I. -I.. -I../config + +.c.o: + $(GCC_FOR_TARGET) $(OPTIMIZE) \ + -c $(GCC_CFLAGS) $(SUBDIR_INCLUDES) $< + +.m.o: + $(GCC_FOR_TARGET) $(OPTIMIZE) -fgnu-runtime \ + -c $(GCC_CFLAGS) $(SUBDIR_INCLUDES) $< + +OBJC_O = hash.o sarray.o class.o sendmsg.o init.o archive.o \ + selector.o objects.o misc.o object.o protocol.o encoding.o thread.o + +libobjc.a: $(OBJC_O) + -rm -f libobjc.a + ar rc libobjc.a $(OBJC_O) + ranlib libobjc.a + +OBJC_H = hash.h objc-list.h sarray.h objc.h \ + objc-api.h \ + object.h protocol.h mutex.h \ + typedstream.h thread.h + +mostlyclean: + -rm -f *.o libobjc.a xforward fflags +clean: mostlyclean +distclean: mostlyclean +extraclean: mostlyclean diff --git a/contrib/gcc/objc/misc.c b/contrib/gcc/objc/misc.c new file mode 100644 index 000000000000..01f9d3bbafa8 --- /dev/null +++ b/contrib/gcc/objc/misc.c @@ -0,0 +1,152 @@ +/* GNU Objective C Runtime Miscellaneous + Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#define __USE_FIXED_PROTOTYPES__ +#include <stdlib.h> +#include "runtime.h" + +/* +** Error handler function +** NULL so that default is to just print to stderr +*/ +static objc_error_handler _objc_error_handler = NULL; + +/* Trigger an objc error */ +void +objc_error(id object, int code, const char* fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + objc_verror(object, code, fmt, ap); + va_end(ap); +} + +/* Trigger an objc error */ +void +objc_verror(id object, int code, const char* fmt, va_list ap) +{ + BOOL result = NO; + + /* Call the error handler if its there + Otherwise print to stderr */ + if (_objc_error_handler) + result = (*_objc_error_handler)(object, code, fmt, ap); + else + vfprintf (stderr, fmt, ap); + + /* Continue if the error handler says its ok + Otherwise abort the program */ + if (result) + return; + else + abort(); +} + +/* Set the error handler */ +objc_error_handler +objc_set_error_handler(objc_error_handler func) +{ + objc_error_handler temp = _objc_error_handler; + _objc_error_handler = func; + return temp; +} + +/* +** Standard functions for memory allocation and disposal. +** Users should use these functions in their ObjC programs so +** that they work properly with garbage collectors as well as +** can take advantage of the exception/error handling available. +*/ + +void * +objc_malloc(size_t size) +{ + void* res = (void*) (*_objc_malloc)(size); + if(!res) + objc_error(nil, OBJC_ERR_MEMORY, "Virtual memory exhausted\n"); + return res; +} + +void * +objc_atomic_malloc(size_t size) +{ + void* res = (void*) (*_objc_atomic_malloc)(size); + if(!res) + objc_error(nil, OBJC_ERR_MEMORY, "Virtual memory exhausted\n"); + return res; +} + +void * +objc_valloc(size_t size) +{ + void* res = (void*) (*_objc_valloc)(size); + if(!res) + objc_error(nil, OBJC_ERR_MEMORY, "Virtual memory exhausted\n"); + return res; +} + +void * +objc_realloc(void *mem, size_t size) +{ + void* res = (void*) (*_objc_realloc)(mem, size); + if(!res) + objc_error(nil, OBJC_ERR_MEMORY, "Virtual memory exhausted\n"); + return res; +} + +void * +objc_calloc(size_t nelem, size_t size) +{ + void* res = (void*) (*_objc_calloc)(nelem, size); + if(!res) + objc_error(nil, OBJC_ERR_MEMORY, "Virtual memory exhausted\n"); + return res; +} + +void +objc_free(void *mem) +{ + (*_objc_free)(mem); +} + +/* +** Hook functions for memory allocation and disposal. +** This makes it easy to substitute garbage collection systems +** such as Boehm's GC by assigning these function pointers +** to the GC's allocation routines. By default these point +** to the ANSI standard malloc, realloc, free, etc. +** +** Users should call the normal objc routines above for +** memory allocation and disposal within their programs. +*/ +void *(*_objc_malloc)(size_t) = malloc; +void *(*_objc_atomic_malloc)(size_t) = malloc; +void *(*_objc_valloc)(size_t) = malloc; +void *(*_objc_realloc)(void *, size_t) = realloc; +void *(*_objc_calloc)(size_t, size_t) = calloc; +void (*_objc_free)(void *) = free; diff --git a/contrib/gcc/objc/nil_method.c b/contrib/gcc/objc/nil_method.c new file mode 100644 index 000000000000..1b6212826bda --- /dev/null +++ b/contrib/gcc/objc/nil_method.c @@ -0,0 +1,40 @@ +/* GNU Objective C Runtime nil receiver function + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +/* This is the nil method, the function that is called when the receiver + of a method is nil */ + +#include "runtime.h" + +id +nil_method(id receiver, SEL op, ...) +{ + return receiver; +} + + + + diff --git a/contrib/gcc/objc/objc-api.h b/contrib/gcc/objc/objc-api.h new file mode 100644 index 000000000000..9eb000b5b391 --- /dev/null +++ b/contrib/gcc/objc/objc-api.h @@ -0,0 +1,584 @@ +/* GNU Objective-C Runtime API. + Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled + with GCC to produce an executable, this does not cause the resulting + executable to be covered by the GNU General Public License. This + exception does not however invalidate any other reasons why the + executable file might be covered by the GNU General Public License. */ + +#ifndef __objc_api_INCLUDE_GNU +#define __objc_api_INCLUDE_GNU + +#include "objc/objc.h" +#include "objc/hash.h" +#include "objc/thr.h" +#include <stdio.h> +#include <stdarg.h> + +/* For functions which return Method_t */ +#define METHOD_NULL (Method_t)0 + /* Boolean typedefs */ +/* +** Method descriptor returned by introspective Object methods. +** This is really just the first part of the more complete objc_method +** structure defined below and used internally by the runtime. +*/ +struct objc_method_description +{ + SEL name; /* this is a selector, not a string */ + char *types; /* type encoding */ +}; + +/* Filer types used to describe Ivars and Methods. */ +#define _C_ID '@' +#define _C_CLASS '#' +#define _C_SEL ':' +#define _C_CHR 'c' +#define _C_UCHR 'C' +#define _C_SHT 's' +#define _C_USHT 'S' +#define _C_INT 'i' +#define _C_UINT 'I' +#define _C_LNG 'l' +#define _C_ULNG 'L' +#define _C_FLT 'f' +#define _C_DBL 'd' +#define _C_BFLD 'b' +#define _C_VOID 'v' +#define _C_UNDEF '?' +#define _C_PTR '^' +#define _C_CHARPTR '*' +#define _C_ATOM '%' +#define _C_ARY_B '[' +#define _C_ARY_E ']' +#define _C_UNION_B '(' +#define _C_UNION_E ')' +#define _C_STRUCT_B '{' +#define _C_STRUCT_E '}' + + +/* +** Error handling +** +** Call objc_error() or objc_verror() to record an error; this error +** routine will generally exit the program but not necessarily if the +** user has installed his own error handler. +** +** Call objc_set_error_handler to assign your own function for +** handling errors. The function should return YES if it is ok +** to continue execution, or return NO or just abort if the +** program should be stopped. The default error handler is just to +** print a message on stderr. +** +** The error handler function should be of type objc_error_handler +** The first parameter is an object instance of relevance. +** The second parameter is an error code. +** The third parameter is a format string in the printf style. +** The fourth parameter is a variable list of arguments. +*/ +extern void objc_error(id object, int code, const char* fmt, ...); +extern void objc_verror(id object, int code, const char* fmt, va_list ap); +typedef BOOL (*objc_error_handler)(id, int code, const char *fmt, va_list ap); +objc_error_handler objc_set_error_handler(objc_error_handler func); + +/* +** Error codes +** These are used by the runtime library, and your +** error handling may use them to determine if the error is +** hard or soft thus whether execution can continue or abort. +*/ +#define OBJC_ERR_UNKNOWN 0 /* Generic error */ + +#define OBJC_ERR_OBJC_VERSION 1 /* Incorrect runtime version */ +#define OBJC_ERR_GCC_VERSION 2 /* Incorrect compiler version */ +#define OBJC_ERR_MODULE_SIZE 3 /* Bad module size */ +#define OBJC_ERR_PROTOCOL_VERSION 4 /* Incorrect protocol version */ + +#define OBJC_ERR_MEMORY 10 /* Out of memory */ + +#define OBJC_ERR_RECURSE_ROOT 20 /* Attempt to archive the root + object more than once. */ +#define OBJC_ERR_BAD_DATA 21 /* Didn't read expected data */ +#define OBJC_ERR_BAD_KEY 22 /* Bad key for object */ +#define OBJC_ERR_BAD_CLASS 23 /* Unknown class */ +#define OBJC_ERR_BAD_TYPE 24 /* Bad type specification */ +#define OBJC_ERR_NO_READ 25 /* Cannot read stream */ +#define OBJC_ERR_NO_WRITE 26 /* Cannot write stream */ +#define OBJC_ERR_STREAM_VERSION 27 /* Incorrect stream version */ +#define OBJC_ERR_BAD_OPCODE 28 /* Bad opcode */ + +#define OBJC_ERR_UNIMPLEMENTED 30 /* Method is not implemented */ + +#define OBJC_ERR_BAD_STATE 40 /* Bad thread state */ + +/* +** Set this variable nonzero to print a line describing each +** message that is sent. (this is currently disabled) +*/ +extern BOOL objc_trace; + + +/* For every class which happens to have statically allocated instances in + this module, one OBJC_STATIC_INSTANCES is allocated by the compiler. + INSTANCES is NULL terminated and points to all statically allocated + instances of this class. */ +struct objc_static_instances +{ + char *class_name; + id instances[0]; +}; + +/* +** Whereas a Module (defined further down) is the root (typically) of a file, +** a Symtab is the root of the class and category definitions within the +** module. +** +** A Symtab contains a variable length array of pointers to classes and +** categories defined in the module. +*/ +typedef struct objc_symtab { + unsigned long sel_ref_cnt; /* Unknown. */ + SEL refs; /* Unknown. */ + unsigned short cls_def_cnt; /* Number of classes compiled + (defined) in the module. */ + unsigned short cat_def_cnt; /* Number of categories + compiled (defined) in the + module. */ + + void *defs[1]; /* Variable array of pointers. + cls_def_cnt of type Class + followed by cat_def_cnt of + type Category_t, followed + by a NULL terminated array + of objc_static_instances. */ +} Symtab, *Symtab_t; + + +/* +** The compiler generates one of these structures for each module that +** composes the executable (eg main.m). +** +** This data structure is the root of the definition tree for the module. +** +** A collect program runs between ld stages and creates a ObjC ctor array. +** That array holds a pointer to each module structure of the executable. +*/ +typedef struct objc_module { + unsigned long version; /* Compiler revision. */ + unsigned long size; /* sizeof(Module). */ + const char* name; /* Name of the file where the + module was generated. The + name includes the path. */ + + Symtab_t symtab; /* Pointer to the Symtab of + the module. The Symtab + holds an array of + pointers to + the classes and categories + defined in the module. */ +} Module, *Module_t; + + +/* +** The compiler generates one of these structures for a class that has +** instance variables defined in its specification. +*/ +typedef struct objc_ivar* Ivar_t; +typedef struct objc_ivar_list { + int ivar_count; /* Number of structures (Ivar) + contained in the list. One + structure per instance + variable defined in the + class. */ + struct objc_ivar { + const char* ivar_name; /* Name of the instance + variable as entered in the + class definition. */ + const char* ivar_type; /* Description of the Ivar's + type. Useful for + debuggers. */ + int ivar_offset; /* Byte offset from the base + address of the instance + structure to the variable. */ + + } ivar_list[1]; /* Variable length + structure. */ +} IvarList, *IvarList_t; + + +/* +** The compiler generates one (or more) of these structures for a class that +** has methods defined in its specification. +** +** The implementation of a class can be broken into separate pieces in a file +** and categories can break them across modules. To handle this problem is a +** singly linked list of methods. +*/ +typedef struct objc_method Method; +typedef Method* Method_t; +typedef struct objc_method_list { + struct objc_method_list* method_next; /* This variable is used to link + a method list to another. It + is a singly linked list. */ + int method_count; /* Number of methods defined in + this structure. */ + struct objc_method { + SEL method_name; /* This variable is the method's + name. It is a char*. + The unique integer passed to + objc_msg_send is a char* too. + It is compared against + method_name using strcmp. */ + const char* method_types; /* Description of the method's + parameter list. Useful for + debuggers. */ + IMP method_imp; /* Address of the method in the + executable. */ + } method_list[1]; /* Variable length + structure. */ +} MethodList, *MethodList_t; + +struct objc_protocol_list { + struct objc_protocol_list *next; + int count; + Protocol *list[1]; +}; + +/* +** This is used to assure consistent access to the info field of +** classes +*/ +#ifndef HOST_BITS_PER_LONG +#define HOST_BITS_PER_LONG (sizeof(long)*8) +#endif + +#define __CLS_INFO(cls) ((cls)->info) +#define __CLS_ISINFO(cls, mask) ((__CLS_INFO(cls)&mask)==mask) +#define __CLS_SETINFO(cls, mask) (__CLS_INFO(cls) |= mask) + +/* The structure is of type MetaClass */ +#define _CLS_META 0x2L +#define CLS_ISMETA(cls) ((cls)&&__CLS_ISINFO(cls, _CLS_META)) + + +/* The structure is of type Class */ +#define _CLS_CLASS 0x1L +#define CLS_ISCLASS(cls) ((cls)&&__CLS_ISINFO(cls, _CLS_CLASS)) + +/* +** The class is initialized within the runtime. This means that +** it has had correct super and sublinks assigned +*/ +#define _CLS_RESOLV 0x8L +#define CLS_ISRESOLV(cls) __CLS_ISINFO(cls, _CLS_RESOLV) +#define CLS_SETRESOLV(cls) __CLS_SETINFO(cls, _CLS_RESOLV) + +/* +** The class has been send a +initialize message or a such is not +** defined for this class +*/ +#define _CLS_INITIALIZED 0x04L +#define CLS_ISINITIALIZED(cls) __CLS_ISINFO(cls, _CLS_INITIALIZED) +#define CLS_SETINITIALIZED(cls) __CLS_SETINFO(cls, _CLS_INITIALIZED) + +/* +** The class number of this class. This must be the same for both the +** class and its meta class object +*/ +#define CLS_GETNUMBER(cls) (__CLS_INFO(cls) >> (HOST_BITS_PER_LONG/2)) +#define CLS_SETNUMBER(cls, num) \ + ({ (cls)->info <<= (HOST_BITS_PER_LONG/2); \ + (cls)->info >>= (HOST_BITS_PER_LONG/2); \ + __CLS_SETINFO(cls, (((unsigned long)num) << (HOST_BITS_PER_LONG/2))); }) + +/* +** The compiler generates one of these structures for each category. A class +** may have many categories and contain both instance and factory methods. +*/ +typedef struct objc_category { + const char* category_name; /* Name of the category. Name + contained in the () of the + category definition. */ + const char* class_name; /* Name of the class to which + the category belongs. */ + MethodList_t instance_methods; /* Linked list of instance + methods defined in the + category. NULL indicates no + instance methods defined. */ + MethodList_t class_methods; /* Linked list of factory + methods defined in the + category. NULL indicates no + class methods defined. */ + struct objc_protocol_list *protocols; /* List of Protocols + conformed to */ +} Category, *Category_t; + +/* +** Structure used when a message is send to a class's super class. The +** compiler generates one of these structures and passes it to +** objc_msg_super. +*/ +typedef struct objc_super { + id self; /* Id of the object sending + the message. */ + Class class; /* Object's super class. */ +} Super, *Super_t; + +IMP objc_msg_lookup_super(Super_t super, SEL sel); + +retval_t objc_msg_sendv(id, SEL, arglist_t); + + + +/* +** This is a hook which is called by objc_lookup_class and +** objc_get_class if the runtime is not able to find the class. +** This may e.g. try to load in the class using dynamic loading. +** The function is guaranteed to be passed a non-NULL name string. +*/ +extern Class (*_objc_lookup_class)(const char *name); + +/* +** This is a hook which is called by __objc_exec_class every time a class +** or a category is loaded into the runtime. This may e.g. help a +** dynamic loader determine the classes that have been loaded when +** an object file is dynamically linked in. +*/ +extern void (*_objc_load_callback)(Class class, Category* category); + +/* +** Hook functions for allocating, copying and disposing of instances +*/ +extern id (*_objc_object_alloc)(Class class); +extern id (*_objc_object_copy)(id object); +extern id (*_objc_object_dispose)(id object); + +/* +** Standard functions for memory allocation and disposal. +** Users should use these functions in their ObjC programs so +** that they work properly with garbage collectors as well as +** can take advantage of the exception/error handling available. +*/ +void * +objc_malloc(size_t size); + +void * +objc_atomic_malloc(size_t size); + +void * +objc_valloc(size_t size); + +void * +objc_realloc(void *mem, size_t size); + +void * +objc_calloc(size_t nelem, size_t size); + +void +objc_free(void *mem); + +/* +** Hook functions for memory allocation and disposal. +** This makes it easy to substitute garbage collection systems +** such as Boehm's GC by assigning these function pointers +** to the GC's allocation routines. By default these point +** to the ANSI standard malloc, realloc, free, etc. +** +** Users should call the normal objc routines above for +** memory allocation and disposal within their programs. +*/ +extern void *(*_objc_malloc)(size_t); +extern void *(*_objc_atomic_malloc)(size_t); +extern void *(*_objc_valloc)(size_t); +extern void *(*_objc_realloc)(void *, size_t); +extern void *(*_objc_calloc)(size_t, size_t); +extern void (*_objc_free)(void *); + +Method_t class_get_class_method(MetaClass class, SEL aSel); + +Method_t class_get_instance_method(Class class, SEL aSel); + +Class class_pose_as(Class impostor, Class superclass); + +Class objc_get_class(const char *name); + +Class objc_lookup_class(const char *name); + +Class objc_next_class(void **enum_state); + +const char *sel_get_name(SEL selector); + +const char *sel_get_type(SEL selector); + +SEL sel_get_uid(const char *name); + +SEL sel_get_any_uid(const char *name); + +SEL sel_get_any_typed_uid(const char *name); + +SEL sel_get_typed_uid(const char *name, const char*); + +SEL sel_register_name(const char *name); + +SEL sel_register_typed_name(const char *name, const char*type); + + +BOOL sel_is_mapped (SEL aSel); + +extern id class_create_instance(Class class); + +static inline const char * +class_get_class_name(Class class) +{ + return CLS_ISCLASS(class)?class->name:((class==Nil)?"Nil":0); +} + +static inline long +class_get_instance_size(Class class) +{ + return CLS_ISCLASS(class)?class->instance_size:0; +} + +static inline MetaClass +class_get_meta_class(Class class) +{ + return CLS_ISCLASS(class)?class->class_pointer:Nil; +} + +static inline Class +class_get_super_class(Class class) +{ + return CLS_ISCLASS(class)?class->super_class:Nil; +} + +static inline int +class_get_version(Class class) +{ + return CLS_ISCLASS(class)?class->version:-1; +} + +static inline BOOL +class_is_class(Class class) +{ + return CLS_ISCLASS(class); +} + +static inline BOOL +class_is_meta_class(Class class) +{ + return CLS_ISMETA(class); +} + + +static inline void +class_set_version(Class class, long version) +{ + if (CLS_ISCLASS(class)) + class->version = version; +} + +static inline IMP +method_get_imp(Method_t method) +{ + return (method!=METHOD_NULL)?method->method_imp:(IMP)0; +} + +IMP get_imp (Class class, SEL sel); + +/* Redefine on NeXTSTEP so as not to conflict with system function */ +#ifdef __NeXT__ +#define object_copy gnu_object_copy +#define object_dispose gnu_object_dispose +#endif + +id object_copy(id object); + +id object_dispose(id object); + +static inline Class +object_get_class(id object) +{ + return ((object!=nil) + ? (CLS_ISCLASS(object->class_pointer) + ? object->class_pointer + : (CLS_ISMETA(object->class_pointer) + ? (Class)object + : Nil)) + : Nil); +} + +static inline const char * +object_get_class_name(id object) +{ + return ((object!=nil)?(CLS_ISCLASS(object->class_pointer) + ?object->class_pointer->name + :((Class)object)->name) + :"Nil"); +} + +static inline MetaClass +object_get_meta_class(id object) +{ + return ((object!=nil)?(CLS_ISCLASS(object->class_pointer) + ?object->class_pointer->class_pointer + :(CLS_ISMETA(object->class_pointer) + ?object->class_pointer + :Nil)) + :Nil); +} + +static inline Class +object_get_super_class +(id object) +{ + return ((object!=nil)?(CLS_ISCLASS(object->class_pointer) + ?object->class_pointer->super_class + :(CLS_ISMETA(object->class_pointer) + ?((Class)object)->super_class + :Nil)) + :Nil); +} + +static inline BOOL +object_is_class(id object) +{ + return CLS_ISCLASS((Class)object); +} + +static inline BOOL +object_is_instance(id object) +{ + return (object!=nil)&&CLS_ISCLASS(object->class_pointer); +} + +static inline BOOL +object_is_meta_class(id object) +{ + return CLS_ISMETA((Class)object); +} + +struct sarray* +objc_get_uninstalled_dtable(void); + +#endif /* not __objc_api_INCLUDE_GNU */ + + + diff --git a/contrib/gcc/objc/objc-list.h b/contrib/gcc/objc/objc-list.h new file mode 100644 index 000000000000..19760906238a --- /dev/null +++ b/contrib/gcc/objc/objc-list.h @@ -0,0 +1,147 @@ +/* Generic single linked list to keep various information + Copyright (C) 1993, 1994, 1996 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#ifndef __GNU_OBJC_LIST_H +#define __GNU_OBJC_LIST_H + +struct objc_list { + void *head; + struct objc_list *tail; +}; + +/* Return a cons cell produced from (head . tail) */ + +static inline struct objc_list* +list_cons(void* head, struct objc_list* tail) +{ + struct objc_list* cell; + + cell = (struct objc_list*)objc_malloc(sizeof(struct objc_list)); + cell->head = head; + cell->tail = tail; + return cell; +} + +/* Return the length of a list, list_length(NULL) returns zero */ + +static inline int +list_length(struct objc_list* list) +{ + int i = 0; + while(list) + { + i += 1; + list = list->tail; + } + return i; +} + +/* Return the Nth element of LIST, where N count from zero. If N + larger than the list length, NULL is returned */ + +static inline void* +list_nth(int index, struct objc_list* list) +{ + while(index-- != 0) + { + if(list->tail) + list = list->tail; + else + return 0; + } + return list->head; +} + +/* Remove the element at the head by replacing it by its successor */ + +static inline void +list_remove_head(struct objc_list** list) +{ + if ((*list)->tail) + { + struct objc_list* tail = (*list)->tail; /* fetch next */ + *(*list) = *tail; /* copy next to list head */ + objc_free(tail); /* free next */ + } + else /* only one element in list */ + { + objc_free(*list); + (*list) = 0; + } +} + + +/* Remove the element with `car' set to ELEMENT */ + +static inline void +list_remove_elem(struct objc_list** list, void* elem) +{ + while (*list) { + if ((*list)->head == elem) + list_remove_head(list); + list = &((*list)->tail); + } +} + +/* Map FUNCTION over all elements in LIST */ + +static inline void +list_mapcar(struct objc_list* list, void(*function)(void*)) +{ + while(list) + { + (*function)(list->head); + list = list->tail; + } +} + +/* Return element that has ELEM as car */ + +static inline struct objc_list** +list_find(struct objc_list** list, void* elem) +{ + while(*list) + { + if ((*list)->head == elem) + return list; + list = &((*list)->tail); + } + return NULL; +} + +/* Free list (backwards recursive) */ + +static void +list_free(struct objc_list* list) +{ + if(list) + { + list_free(list->tail); + objc_free(list); + } +} +#endif __GNU_OBJC_LIST_H diff --git a/contrib/gcc/objc/objc.h b/contrib/gcc/objc/objc.h new file mode 100644 index 000000000000..e48b0fd5bfb4 --- /dev/null +++ b/contrib/gcc/objc/objc.h @@ -0,0 +1,157 @@ +/* Basic data types for Objective C. + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#ifndef __objc_INCLUDE_GNU +#define __objc_INCLUDE_GNU + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stddef.h> + +/* +** Definition of the boolean type. +*/ +#ifdef __vxworks +typedef int BOOL; +#else +typedef unsigned char BOOL; +#endif +#define YES (BOOL)1 +#define NO (BOOL)0 + +/* +** Definition of a selector. Selectors themselves are not unique, but +** the sel_id is a unique identifier. +*/ +typedef const struct objc_selector +{ + void *sel_id; + const char *sel_types; +} *SEL; + +inline static BOOL +sel_eq (SEL s1, SEL s2) +{ + if (s1 == 0 || s2 == 0) + return s1 == s2; + else + return s1->sel_id == s2->sel_id; +} + + +/* +** ObjC uses this typedef for untyped instances. +*/ +typedef struct objc_object { + struct objc_class* class_pointer; +} *id; + +/* +** Definition of method type. When retrieving the implementation of a +** method, this is type of the pointer returned +*/ +typedef id (*IMP)(id, SEL, ...); + +/* +** More simple types... +*/ +#define nil (id)0 /* id of Nil instance */ +#define Nil (Class)0 /* id of Nil class */ +typedef char *STR; /* String alias */ + +/* +** The compiler generates one of these structures for each class. +** +** This structure is the definition for classes. +** +** This structure is generated by the compiler in the executable and used by +** the run-time during normal messaging operations. Therefore some members +** change type. The compiler generates "char* const" and places a string in +** the following member variables: super_class. +*/ +typedef struct objc_class *MetaClass; +typedef struct objc_class *Class; +struct objc_class { + MetaClass class_pointer; /* Pointer to the class's + meta class. */ + struct objc_class* super_class; /* Pointer to the super + class. NULL for class + Object. */ + const char* name; /* Name of the class. */ + long version; /* Unknown. */ + unsigned long info; /* Bit mask. See class masks + defined above. */ + long instance_size; /* Size in bytes of the class. + The sum of the class + definition and all super + class definitions. */ + struct objc_ivar_list* ivars; /* Pointer to a structure that + describes the instance + variables in the class + definition. NULL indicates + no instance variables. Does + not include super class + variables. */ + struct objc_method_list* methods; /* Linked list of instance + methods defined for the + class. */ + struct sarray * dtable; /* Pointer to instance + method dispatch table. */ + struct objc_class* subclass_list; /* Subclasses */ + struct objc_class* sibling_class; + + struct objc_protocol_list *protocols; /* Protocols conformed to */ +}; + +#ifndef __OBJC__ +typedef struct objc_protocol { + struct objc_class* class_pointer; + char *protocol_name; + struct objc_protocol_list *protocol_list; + struct objc_method_description_list *instance_methods, *class_methods; +} Protocol; + +#else /* __OBJC__ */ +@class Protocol; +#endif + +typedef void* retval_t; /* return value */ +typedef void(*apply_t)(void); /* function pointer */ +typedef union { + char *arg_ptr; + char arg_regs[sizeof (char*)]; +} *arglist_t; /* argument frame */ + + +IMP objc_msg_lookup(id receiver, SEL op); + +#ifdef __cplusplus +} +#endif + +#endif /* not __objc_INCLUDE_GNU */ diff --git a/contrib/gcc/objc/objects.c b/contrib/gcc/objc/objects.c new file mode 100644 index 000000000000..3e68334c924b --- /dev/null +++ b/contrib/gcc/objc/objects.c @@ -0,0 +1,92 @@ +/* GNU Objective C Runtime class related functions + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include "../tconfig.h" /* include defs of bzero for target */ +#include "runtime.h" /* the kitchen sink */ + +id __objc_object_alloc(Class); +id __objc_object_dispose(id); +id __objc_object_copy(id); + +id (*_objc_object_alloc)(Class) = __objc_object_alloc; /* !T:SINGLE */ +id (*_objc_object_dispose)(id) = __objc_object_dispose; /* !T:SINGLE */ +id (*_objc_object_copy)(id) = __objc_object_copy; /* !T:SINGLE */ + +id +class_create_instance(Class class) +{ + id new = nil; + if (CLS_ISCLASS(class)) + new = (*_objc_object_alloc)(class); + if (new!=nil) + { + memset (new, 0, class->instance_size); + new->class_pointer = class; + } + return new; +} + +id +object_copy(id object) +{ + if ((object!=nil)&&CLS_ISCLASS(object->class_pointer)) + return (*_objc_object_copy)(object); + else + return nil; +} + +id +object_dispose(id object) +{ + if ((object!=nil)&&CLS_ISCLASS(object->class_pointer)) + { + if (_objc_object_dispose) + (*_objc_object_dispose)(object); + else + objc_free(object); + } + return nil; +} + +id __objc_object_alloc(Class class) +{ + return (id)objc_malloc(class->instance_size); +} + +id __objc_object_dispose(id object) +{ + objc_free(object); + return 0; +} + +id __objc_object_copy(id object) +{ + id copy = class_create_instance(object->class_pointer); + memcpy(copy, object, object->class_pointer->instance_size); + return copy; +} + + diff --git a/contrib/gcc/objc/runtime.h b/contrib/gcc/objc/runtime.h new file mode 100644 index 000000000000..b0eae4a222d3 --- /dev/null +++ b/contrib/gcc/objc/runtime.h @@ -0,0 +1,88 @@ +/* GNU Objective C Runtime internal declarations + Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#ifndef __objc_runtime_INCLUDE_GNU +#define __objc_runtime_INCLUDE_GNU + +#include <stdarg.h> /* for varargs and va_list's */ + +#include <stdio.h> +#include <ctype.h> + +#include <stddef.h> /* so noone else will get system versions */ +#include "assert.h" + +#include "objc/objc.h" /* core data types */ +#include "objc/objc-api.h" /* runtime api functions */ + +#include "objc/thr.h" /* thread and mutex support */ + +#include "objc/hash.h" /* hash structures */ +#include "objc/objc-list.h" /* linear lists */ + +extern void __objc_add_class_to_hash(Class); /* (objc-class.c) */ +extern void __objc_init_selector_tables(void); /* (objc-sel.c) */ +extern void __objc_init_class_tables(void); /* (objc-class.c) */ +extern void __objc_init_dispatch_tables(void); /* (objc-dispatch.c) */ +extern void __objc_install_premature_dtable(Class); /* (objc-dispatch.c) */ +extern void __objc_resolve_class_links(void); /* (objc-class.c) */ +extern void __objc_register_selectors_from_class(Class); /* (objc-sel.c) */ +extern void __objc_update_dispatch_table_for_class (Class);/* (objc-msg.c) */ + +extern int __objc_init_thread_system(void); /* thread.c */ +extern int __objc_fini_thread_system(void); /* thread.c */ +extern void __objc_print_dtable_stats(void); /* sendmsg.c */ + +extern void class_add_method_list(Class, MethodList_t); + +/* Registering instance methods as class methods for root classes */ +extern void __objc_register_instance_methods_to_class(Class); +extern Method_t search_for_method_in_list(MethodList_t list, SEL op); + +/* True when class links has been resolved */ +extern BOOL __objc_class_links_resolved; + +/* Number of selectors stored in each of the selector tables */ +extern int __objc_selector_max_index; + +/* Mutex locking __objc_selector_max_index and its arrays. */ +extern objc_mutex_t __objc_runtime_mutex; + +/* Number of threads which are alive. */ +extern int __objc_runtime_threads_alive; + +#ifdef DEBUG +#define DEBUG_PRINTF(format, args...) printf (format, ## args) +#else +#define DEBUG_PRINTF(format, args...) +#endif + +BOOL __objc_responds_to (id object, SEL sel); /* for internal use only! */ +SEL __sel_register_typed_name (const char*, const char*, + struct objc_selector*, BOOL is_const); + +#endif /* not __objc_runtime_INCLUDE_GNU */ + + diff --git a/contrib/gcc/objc/sarray.c b/contrib/gcc/objc/sarray.c new file mode 100644 index 000000000000..7e40fba750f6 --- /dev/null +++ b/contrib/gcc/objc/sarray.c @@ -0,0 +1,522 @@ +/* Sparse Arrays for Objective C dispatch tables + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#include "objc/sarray.h" +#include "objc/runtime.h" +#include <stdio.h> +#include "assert.h" + +int nbuckets = 0; /* !T:MUTEX */ +int nindices = 0; /* !T:MUTEX */ +int narrays = 0; /* !T:MUTEX */ +int idxsize = 0; /* !T:MUTEX */ + +static void * first_free_data = NULL; /* !T:MUTEX */ + +#ifdef OBJC_SPARSE2 +const char* __objc_sparse2_id = "2 level sparse indices"; +#endif + +#ifdef OBJC_SPARSE3 +const char* __objc_sparse3_id = "3 level sparse indices"; +#endif + +#ifdef __alpha__ +const void *memcpy (void*, const void*, size_t); +#endif + +/* This function removes any structures left over from free operations + that were not safe in a multi-threaded environment. */ +void +sarray_remove_garbage(void) +{ + void **vp; + void *np; + + objc_mutex_lock(__objc_runtime_mutex); + + vp = first_free_data; + first_free_data = NULL; + + while (vp) { + np = *vp; + objc_free(vp); + vp = np; + } + + objc_mutex_unlock(__objc_runtime_mutex); +} + +/* Free a block of dynamically allocated memory. If we are in multi-threaded + mode, it is ok to free it. If not, we add it to the garbage heap to be + freed later. */ + +static void +sarray_free_garbage(void *vp) +{ + objc_mutex_lock(__objc_runtime_mutex); + + if (__objc_runtime_threads_alive == 1) { + objc_free(vp); + if (first_free_data) + sarray_remove_garbage(); + } + else { + *(void **)vp = first_free_data; + first_free_data = vp; + } + + objc_mutex_unlock(__objc_runtime_mutex); +} + +/* sarray_at_put : copies data in such a way as to be thread reader safe. */ +void +sarray_at_put(struct sarray* array, sidx index, void* element) +{ +#ifdef OBJC_SPARSE3 + struct sindex** the_index; + struct sindex* new_index; +#endif + struct sbucket** the_bucket; + struct sbucket* new_bucket; +#ifdef OBJC_SPARSE3 + size_t ioffset; +#endif + size_t boffset; + size_t eoffset; +#ifdef PRECOMPUTE_SELECTORS + union sofftype xx; + xx.idx = index; +#ifdef OBJC_SPARSE3 + ioffset = xx.off.ioffset; +#endif + boffset = xx.off.boffset; + eoffset = xx.off.eoffset; +#else /* not PRECOMPUTE_SELECTORS */ +#ifdef OBJC_SPARSE3 + ioffset = index/INDEX_CAPACITY; + boffset = (index/BUCKET_SIZE)%INDEX_SIZE; + eoffset = index%BUCKET_SIZE; +#else + boffset = index/BUCKET_SIZE; + eoffset = index%BUCKET_SIZE; +#endif +#endif /* not PRECOMPUTE_SELECTORS */ + + assert(soffset_decode(index) < array->capacity); /* Range check */ + +#ifdef OBJC_SPARSE3 + the_index = &(array->indices[ioffset]); + the_bucket = &((*the_index)->buckets[boffset]); +#else + the_bucket = &(array->buckets[boffset]); +#endif + + if ((*the_bucket)->elems[eoffset] == element) + return; /* great! we just avoided a lazy copy */ + +#ifdef OBJC_SPARSE3 + + /* First, perform lazy copy/allocation of index if needed */ + + if ((*the_index) == array->empty_index) { + + /* The index was previously empty, allocate a new */ + new_index = (struct sindex*)objc_malloc(sizeof(struct sindex)); + memcpy(new_index, array->empty_index, sizeof(struct sindex)); + new_index->version.version = array->version.version; + *the_index = new_index; /* Prepared for install. */ + the_bucket = &((*the_index)->buckets[boffset]); + + nindices += 1; + } else if ((*the_index)->version.version != array->version.version) { + + /* This index must be lazy copied */ + struct sindex* old_index = *the_index; + new_index = (struct sindex*)objc_malloc(sizeof(struct sindex)); + memcpy( new_index, old_index, sizeof(struct sindex)); + new_index->version.version = array->version.version; + *the_index = new_index; /* Prepared for install. */ + the_bucket = &((*the_index)->buckets[boffset]); + + nindices += 1; + } + +#endif /* OBJC_SPARSE3 */ + + /* next, perform lazy allocation/copy of the bucket if needed */ + + if ((*the_bucket) == array->empty_bucket) { + + /* The bucket was previously empty (or something like that), */ + /* allocate a new. This is the effect of `lazy' allocation */ + new_bucket = (struct sbucket*)objc_malloc(sizeof(struct sbucket)); + memcpy((void *) new_bucket, (const void*)array->empty_bucket, + sizeof(struct sbucket)); + new_bucket->version.version = array->version.version; + *the_bucket = new_bucket; /* Prepared for install. */ + + nbuckets += 1; + + } else if ((*the_bucket)->version.version != array->version.version) { + + /* Perform lazy copy. */ + struct sbucket* old_bucket = *the_bucket; + new_bucket = (struct sbucket*)objc_malloc(sizeof(struct sbucket)); + memcpy( new_bucket, old_bucket, sizeof(struct sbucket)); + new_bucket->version.version = array->version.version; + *the_bucket = new_bucket; /* Prepared for install. */ + + nbuckets += 1; + + } + (*the_bucket)->elems[eoffset] = element; +} + +void +sarray_at_put_safe(struct sarray* array, sidx index, void* element) +{ + if(soffset_decode(index) >= array->capacity) + sarray_realloc(array, soffset_decode(index)+1); + sarray_at_put(array, index, element); +} + +struct sarray* +sarray_new (int size, void* default_element) +{ + struct sarray* arr; +#ifdef OBJC_SPARSE3 + size_t num_indices = ((size-1)/(INDEX_CAPACITY))+1; + struct sindex ** new_indices; +#else /* OBJC_SPARSE2 */ + size_t num_indices = ((size-1)/BUCKET_SIZE)+1; + struct sbucket ** new_buckets; +#endif + int counter; + + assert(size > 0); + + /* Allocate core array */ + arr = (struct sarray*) objc_malloc(sizeof(struct sarray)); + arr->version.version = 0; + + /* Initialize members */ +#ifdef OBJC_SPARSE3 + arr->capacity = num_indices*INDEX_CAPACITY; + new_indices = (struct sindex**) + objc_malloc(sizeof(struct sindex*)*num_indices); + + arr->empty_index = (struct sindex*) objc_malloc(sizeof(struct sindex)); + arr->empty_index->version.version = 0; + + narrays += 1; + idxsize += num_indices; + nindices += 1; + +#else /* OBJC_SPARSE2 */ + arr->capacity = num_indices*BUCKET_SIZE; + new_buckets = (struct sbucket**) + objc_malloc(sizeof(struct sbucket*)*num_indices); + + narrays += 1; + idxsize += num_indices; + +#endif + + arr->empty_bucket = (struct sbucket*) objc_malloc(sizeof(struct sbucket)); + arr->empty_bucket->version.version = 0; + + nbuckets += 1; + + arr->ref_count = 1; + arr->is_copy_of = (struct sarray*)0; + + for (counter=0; counter<BUCKET_SIZE; counter++) + arr->empty_bucket->elems[counter] = default_element; + +#ifdef OBJC_SPARSE3 + for (counter=0; counter<INDEX_SIZE; counter++) + arr->empty_index->buckets[counter] = arr->empty_bucket; + + for (counter=0; counter<num_indices; counter++) + new_indices[counter] = arr->empty_index; + +#else /* OBJC_SPARSE2 */ + + for (counter=0; counter<num_indices; counter++) + new_buckets[counter] = arr->empty_bucket; + +#endif + +#ifdef OBJC_SPARSE3 + arr->indices = new_indices; +#else /* OBJC_SPARSE2 */ + arr->buckets = new_buckets; +#endif + + return arr; +} + + +/* Reallocate the sparse array to hold `newsize' entries + Note: We really allocate and then free. We have to do this to ensure that + any concurrent readers notice the update. */ + +void +sarray_realloc(struct sarray* array, int newsize) +{ +#ifdef OBJC_SPARSE3 + size_t old_max_index = (array->capacity-1)/INDEX_CAPACITY; + size_t new_max_index = ((newsize-1)/INDEX_CAPACITY); + size_t rounded_size = (new_max_index+1)*INDEX_CAPACITY; + + struct sindex ** new_indices; + struct sindex ** old_indices; + +#else /* OBJC_SPARSE2 */ + size_t old_max_index = (array->capacity-1)/BUCKET_SIZE; + size_t new_max_index = ((newsize-1)/BUCKET_SIZE); + size_t rounded_size = (new_max_index+1)*BUCKET_SIZE; + + struct sbucket ** new_buckets; + struct sbucket ** old_buckets; + +#endif + + int counter; + + assert(newsize > 0); + + /* The size is the same, just ignore the request */ + if(rounded_size <= array->capacity) + return; + + assert(array->ref_count == 1); /* stop if lazy copied... */ + + /* We are asked to extend the array -- allocate new bucket table, */ + /* and insert empty_bucket in newly allocated places. */ + if(rounded_size > array->capacity) + { + +#ifdef OBJC_SPARSE3 + new_max_index += 4; + rounded_size = (new_max_index+1)*INDEX_CAPACITY; + +#else /* OBJC_SPARSE2 */ + new_max_index += 4; + rounded_size = (new_max_index+1)*BUCKET_SIZE; +#endif + + /* update capacity */ + array->capacity = rounded_size; + +#ifdef OBJC_SPARSE3 + /* alloc to force re-read by any concurrent readers. */ + old_indices = array->indices; + new_indices = (struct sindex**) + objc_malloc((new_max_index+1)*sizeof(struct sindex*)); +#else /* OBJC_SPARSE2 */ + old_buckets = array->buckets; + new_buckets = (struct sbucket**) + objc_malloc((new_max_index+1)*sizeof(struct sbucket*)); +#endif + + /* copy buckets below old_max_index (they are still valid) */ + for(counter = 0; counter <= old_max_index; counter++ ) { +#ifdef OBJC_SPARSE3 + new_indices[counter] = old_indices[counter]; +#else /* OBJC_SPARSE2 */ + new_buckets[counter] = old_buckets[counter]; +#endif + } + +#ifdef OBJC_SPARSE3 + /* reset entries above old_max_index to empty_bucket */ + for(counter = old_max_index+1; counter <= new_max_index; counter++) + new_indices[counter] = array->empty_index; +#else /* OBJC_SPARSE2 */ + /* reset entries above old_max_index to empty_bucket */ + for(counter = old_max_index+1; counter <= new_max_index; counter++) + new_buckets[counter] = array->empty_bucket; +#endif + +#ifdef OBJC_SPARSE3 + /* install the new indices */ + array->indices = new_indices; +#else /* OBJC_SPARSE2 */ + array->buckets = new_buckets; +#endif + +#ifdef OBJC_SPARSE3 + /* free the old indices */ + sarray_free_garbage(old_indices); +#else /* OBJC_SPARSE2 */ + sarray_free_garbage(old_buckets); +#endif + + idxsize += (new_max_index-old_max_index); + return; + } +} + + +/* Free a sparse array allocated with sarray_new */ + +void +sarray_free(struct sarray* array) { + +#ifdef OBJC_SPARSE3 + size_t old_max_index = (array->capacity-1)/INDEX_CAPACITY; + struct sindex ** old_indices; +#else + size_t old_max_index = (array->capacity-1)/BUCKET_SIZE; + struct sbucket ** old_buckets; +#endif + int counter = 0; + + assert(array->ref_count != 0); /* Freed multiple times!!! */ + + if(--(array->ref_count) != 0) /* There exists copies of me */ + return; + +#ifdef OBJC_SPARSE3 + old_indices = array->indices; +#else + old_buckets = array->buckets; +#endif + + if((array->is_copy_of) && ((array->is_copy_of->ref_count - 1) == 0)) + sarray_free(array->is_copy_of); + + /* Free all entries that do not point to empty_bucket */ + for(counter = 0; counter <= old_max_index; counter++ ) { +#ifdef OBJC_SPARSE3 + struct sindex* idx = old_indices[counter]; + if((idx != array->empty_index) && + (idx->version.version == array->version.version)) { + int c2; + for(c2=0; c2<INDEX_SIZE; c2++) { + struct sbucket* bkt = idx->buckets[c2]; + if((bkt != array->empty_bucket) && + (bkt->version.version == array->version.version)) + { + sarray_free_garbage(bkt); + nbuckets -= 1; + } + } + sarray_free_garbage(idx); + nindices -= 1; + } +#else /* OBJC_SPARSE2 */ + struct sbucket* bkt = array->buckets[counter]; + if ((bkt != array->empty_bucket) && + (bkt->version.version == array->version.version)) + { + sarray_free_garbage(bkt); + nbuckets -= 1; + } +#endif + } + +#ifdef OBJC_SPARSE3 + /* free empty_index */ + if(array->empty_index->version.version == array->version.version) { + sarray_free_garbage(array->empty_index); + nindices -= 1; + } +#endif + + /* free empty_bucket */ + if(array->empty_bucket->version.version == array->version.version) { + sarray_free_garbage(array->empty_bucket); + nbuckets -= 1; + } + idxsize -= (old_max_index+1); + narrays -= 1; + +#ifdef OBJC_SPARSE3 + /* free bucket table */ + sarray_free_garbage(array->indices); + +#else + /* free bucket table */ + sarray_free_garbage(array->buckets); + +#endif + + /* free array */ + sarray_free_garbage(array); +} + +/* This is a lazy copy. Only the core of the structure is actually */ +/* copied. */ + +struct sarray* +sarray_lazy_copy(struct sarray* oarr) +{ + struct sarray* arr; + +#ifdef OBJC_SPARSE3 + size_t num_indices = ((oarr->capacity-1)/INDEX_CAPACITY)+1; + struct sindex ** new_indices; +#else /* OBJC_SPARSE2 */ + size_t num_indices = ((oarr->capacity-1)/BUCKET_SIZE)+1; + struct sbucket ** new_buckets; +#endif + + /* Allocate core array */ + arr = (struct sarray*) objc_malloc(sizeof(struct sarray)); /* !!! */ + arr->version.version = oarr->version.version + 1; +#ifdef OBJC_SPARSE3 + arr->empty_index = oarr->empty_index; +#endif + arr->empty_bucket = oarr->empty_bucket; + arr->ref_count = 1; + oarr->ref_count += 1; + arr->is_copy_of = oarr; + arr->capacity = oarr->capacity; + +#ifdef OBJC_SPARSE3 + /* Copy bucket table */ + new_indices = (struct sindex**) + objc_malloc(sizeof(struct sindex*)*num_indices); + memcpy( new_indices,oarr->indices, + sizeof(struct sindex*)*num_indices); + arr->indices = new_indices; +#else + /* Copy bucket table */ + new_buckets = (struct sbucket**) + objc_malloc(sizeof(struct sbucket*)*num_indices); + memcpy( new_buckets,oarr->buckets, + sizeof(struct sbucket*)*num_indices); + arr->buckets = new_buckets; +#endif + + idxsize += num_indices; + narrays += 1; + + return arr; +} diff --git a/contrib/gcc/objc/sarray.h b/contrib/gcc/objc/sarray.h new file mode 100644 index 000000000000..74fa38652ba3 --- /dev/null +++ b/contrib/gcc/objc/sarray.h @@ -0,0 +1,237 @@ +/* Sparse Arrays for Objective C dispatch tables + Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + +#ifndef __sarray_INCLUDE_GNU +#define __sarray_INCLUDE_GNU + +#define OBJC_SPARSE2 /* 2-level sparse array */ +/* #define OBJC_SPARSE3 */ /* 3-level sparse array */ + +#ifdef OBJC_SPARSE2 +extern const char* __objc_sparse2_id; +#endif + +#ifdef OBJC_SPARSE3 +extern const char* __objc_sparse3_id; +#endif + +#include <stddef.h> + +#include "objc/thr.h" + +extern int nbuckets; /* for stats */ +extern int nindices; +extern int narrays; +extern int idxsize; + +#include <assert.h> + +/* An unsigned integer of same size as a pointer */ +#define SIZET_BITS (sizeof(size_t)*8) + +#if defined(__sparc__) || defined(OBJC_SPARSE2) +#define PRECOMPUTE_SELECTORS +#endif + +#ifdef OBJC_SPARSE3 + +/* Buckets are 8 words each */ +#define BUCKET_BITS 3 +#define BUCKET_SIZE (1<<BUCKET_BITS) +#define BUCKET_MASK (BUCKET_SIZE-1) + +/* Indices are 16 words each */ +#define INDEX_BITS 4 +#define INDEX_SIZE (1<<INDEX_BITS) +#define INDEX_MASK (INDEX_SIZE-1) + +#define INDEX_CAPACITY (BUCKET_SIZE*INDEX_SIZE) + +#else /* OBJC_SPARSE2 */ + +/* Buckets are 32 words each */ +#define BUCKET_BITS 5 +#define BUCKET_SIZE (1<<BUCKET_BITS) +#define BUCKET_MASK (BUCKET_SIZE-1) + +#endif /* OBJC_SPARSE2 */ + +typedef size_t sidx; + +#ifdef PRECOMPUTE_SELECTORS + +struct soffset { +#ifdef OBJC_SPARSE3 + unsigned int unused : SIZET_BITS/4; + unsigned int eoffset : SIZET_BITS/4; + unsigned int boffset : SIZET_BITS/4; + unsigned int ioffset : SIZET_BITS/4; +#else /* OBJC_SPARSE2 */ +#ifdef __sparc__ + unsigned int boffset : (SIZET_BITS - 2) - BUCKET_BITS; + unsigned int eoffset : BUCKET_BITS; + unsigned int unused : 2; +#else + unsigned int boffset : SIZET_BITS/2; + unsigned int eoffset : SIZET_BITS/2; +#endif +#endif /* OBJC_SPARSE2 */ +}; + +union sofftype { + struct soffset off; + sidx idx; +}; + +#endif /* not PRECOMPUTE_SELECTORS */ + +union sversion { + int version; + void *next_free; +}; + +struct sbucket { + void* elems[BUCKET_SIZE]; /* elements stored in array */ + union sversion version; /* used for copy-on-write */ +}; + +#ifdef OBJC_SPARSE3 + +struct sindex { + struct sbucket* buckets[INDEX_SIZE]; + union sversion version; /* used for copy-on-write */ +}; + +#endif /* OBJC_SPARSE3 */ + +struct sarray { +#ifdef OBJC_SPARSE3 + struct sindex** indices; + struct sindex* empty_index; +#else /* OBJC_SPARSE2 */ + struct sbucket** buckets; +#endif /* OBJC_SPARSE2 */ + struct sbucket* empty_bucket; + union sversion version; /* used for copy-on-write */ + short ref_count; + struct sarray* is_copy_of; + size_t capacity; +}; + +struct sarray* sarray_new(int, void* default_element); +void sarray_free(struct sarray*); +struct sarray* sarray_lazy_copy(struct sarray*); +void sarray_realloc(struct sarray*, int new_size); +void sarray_at_put(struct sarray*, sidx index, void* elem); +void sarray_at_put_safe(struct sarray*, sidx index, void* elem); + +struct sarray* sarray_hard_copy(struct sarray*); /* ... like the name? */ +void sarray_remove_garbage(void); + + +#ifdef PRECOMPUTE_SELECTORS +/* Transform soffset values to ints and vica verca */ +static inline unsigned int +soffset_decode(sidx index) +{ + union sofftype x; + x.idx = index; +#ifdef OBJC_SPARSE3 + return x.off.eoffset + + (x.off.boffset*BUCKET_SIZE) + + (x.off.ioffset*INDEX_CAPACITY); +#else /* OBJC_SPARSE2 */ + return x.off.eoffset + (x.off.boffset*BUCKET_SIZE); +#endif /* OBJC_SPARSE2 */ +} + +static inline sidx +soffset_encode(size_t offset) +{ + union sofftype x; + x.off.eoffset = offset%BUCKET_SIZE; +#ifdef OBJC_SPARSE3 + x.off.boffset = (offset/BUCKET_SIZE)%INDEX_SIZE; + x.off.ioffset = offset/INDEX_CAPACITY; +#else /* OBJC_SPARSE2 */ + x.off.boffset = offset/BUCKET_SIZE; +#endif + return (sidx)x.idx; +} + +#else /* not PRECOMPUTE_SELECTORS */ + +static inline size_t +soffset_decode(sidx index) +{ + return index; +} + +static inline sidx +soffset_encode(size_t offset) +{ + return offset; +} +#endif /* not PRECOMPUTE_SELECTORS */ + +/* Get element from the Sparse array `array' at offset `index' */ + +static inline void* sarray_get(struct sarray* array, sidx index) +{ +#ifdef PRECOMPUTE_SELECTORS + union sofftype x; + x.idx = index; +#ifdef OBJC_SPARSE3 + return + array-> + indices[x.off.ioffset]-> + buckets[x.off.boffset]-> + elems[x.off.eoffset]; +#else /* OBJC_SPARSE2 */ + return array->buckets[x.off.boffset]->elems[x.off.eoffset]; +#endif /* OBJC_SPARSE2 */ +#else /* not PRECOMPUTE_SELECTORS */ +#ifdef OBJC_SPARSE3 + return array-> + indices[index/INDEX_CAPACITY]-> + buckets[(index/BUCKET_SIZE)%INDEX_SIZE]-> + elems[index%BUCKET_SIZE]; +#else /* OBJC_SPARSE2 */ + return array->buckets[index/BUCKET_SIZE]->elems[index%BUCKET_SIZE]; +#endif /* not OBJC_SPARSE3 */ +#endif /* not PRECOMPUTE_SELECTORS */ +} + +static inline void* sarray_get_safe(struct sarray* array, sidx index) +{ + if(soffset_decode(index) < array->capacity) + return sarray_get(array, index); + else + return (array->empty_bucket->elems[0]); +} + +#endif /* __sarray_INCLUDE_GNU */ diff --git a/contrib/gcc/objc/selector.c b/contrib/gcc/objc/selector.c new file mode 100644 index 000000000000..83c70e4ae0f1 --- /dev/null +++ b/contrib/gcc/objc/selector.c @@ -0,0 +1,458 @@ +/* GNU Objective C Runtime selector related functions + Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include "runtime.h" +#include "objc/sarray.h" +#include "encoding.h" + +/* Initial selector hash table size. Value doesn't matter much */ +#define SELECTOR_HASH_SIZE 128 + +/* Tables mapping selector names to uid and opposite */ +static struct sarray* __objc_selector_array = 0; /* uid -> sel !T:MUTEX */ +static struct sarray* __objc_selector_names = 0; /* uid -> name !T:MUTEX */ +static cache_ptr __objc_selector_hash = 0; /* name -> uid !T:MUTEX */ + +static void register_selectors_from_list(MethodList_t); + +/* Number of selectors stored in each of the above tables */ +int __objc_selector_max_index = 0; /* !T:MUTEX */ + +void __objc_init_selector_tables() +{ + __objc_selector_array = sarray_new (SELECTOR_HASH_SIZE, 0); + __objc_selector_names = sarray_new (SELECTOR_HASH_SIZE, 0); + __objc_selector_hash + = hash_new (SELECTOR_HASH_SIZE, + (hash_func_type) hash_string, + (compare_func_type) compare_strings); +} + +/* This routine is given a class and records all of the methods in its class + structure in the record table. */ +void +__objc_register_selectors_from_class (Class class) +{ + MethodList_t method_list; + + method_list = class->methods; + while (method_list) + { + register_selectors_from_list (method_list); + method_list = method_list->method_next; + } +} + + +/* This routine is given a list of methods and records each of the methods in + the record table. This is the routine that does the actual recording + work. + + This one is only called for Class objects. For categories, + class_add_method_list is called. + */ +static void +register_selectors_from_list (MethodList_t method_list) +{ + int i = 0; + while (i < method_list->method_count) + { + Method_t method = &method_list->method_list[i]; + method->method_name + = sel_register_typed_name ((const char*)method->method_name, + method->method_types); + i += 1; + } +} + + +/* Register instance methods as class methods for root classes */ +void __objc_register_instance_methods_to_class(Class class) +{ + MethodList_t method_list; + MethodList_t class_method_list; + int max_methods_no = 16; + MethodList_t new_list; + Method_t curr_method; + + /* Only if a root class. */ + if(class->super_class) + return; + + /* Allocate a method list to hold the new class methods */ + new_list = objc_calloc(sizeof(struct objc_method_list) + + sizeof(struct objc_method[max_methods_no]), 1); + method_list = class->methods; + class_method_list = class->class_pointer->methods; + curr_method = &new_list->method_list[0]; + + /* Iterate through the method lists for the class */ + while (method_list) + { + int i; + + /* Iterate through the methods from this method list */ + for (i = 0; i < method_list->method_count; i++) + { + Method_t mth = &method_list->method_list[i]; + if (mth->method_name + && !search_for_method_in_list (class_method_list, + mth->method_name)) + { + /* This instance method isn't a class method. + Add it into the new_list. */ + *curr_method = *mth; + + /* Reallocate the method list if necessary */ + if(++new_list->method_count == max_methods_no) + new_list = + objc_realloc(new_list, sizeof(struct objc_method_list) + + sizeof(struct + objc_method[max_methods_no += 16])); + curr_method = &new_list->method_list[new_list->method_count]; + } + } + + method_list = method_list->method_next; + } + + /* If we created any new class methods + then attach the method list to the class */ + if (new_list->method_count) + { + new_list = + objc_realloc(new_list, sizeof(struct objc_method_list) + + sizeof(struct objc_method[new_list->method_count])); + new_list->method_next = class->class_pointer->methods; + class->class_pointer->methods = new_list; + } + + __objc_update_dispatch_table_for_class (class->class_pointer); +} + + +/* Returns YES iff t1 and t2 have same method types, but we ignore + the argframe layout */ +BOOL +sel_types_match (const char* t1, const char* t2) +{ + if (!t1 || !t2) + return NO; + while (*t1 && *t2) + { + if (*t1 == '+') t1++; + if (*t2 == '+') t2++; + while (isdigit(*t1)) t1++; + while (isdigit(*t2)) t2++; + /* xxx Remove these next two lines when qualifiers are put in + all selectors, not just Protocol selectors. */ + t1 = objc_skip_type_qualifiers(t1); + t2 = objc_skip_type_qualifiers(t2); + if (!*t1 && !*t2) + return YES; + if (*t1 != *t2) + return NO; + t1++; + t2++; + } + return NO; +} + +/* return selector representing name */ +SEL +sel_get_typed_uid (const char *name, const char *types) +{ + struct objc_list *l; + sidx i; + + objc_mutex_lock(__objc_runtime_mutex); + + i = (sidx) hash_value_for_key (__objc_selector_hash, name); + if (i == 0) + { + objc_mutex_unlock(__objc_runtime_mutex); + return 0; + } + + for (l = (struct objc_list*)sarray_get_safe (__objc_selector_array, i); + l; l = l->tail) + { + SEL s = (SEL)l->head; + if (types == 0 || s->sel_types == 0) + { + if (s->sel_types == types) + { + objc_mutex_unlock(__objc_runtime_mutex); + return s; + } + } + else if (sel_types_match (s->sel_types, types)) + { + objc_mutex_unlock(__objc_runtime_mutex); + return s; + } + } + + objc_mutex_unlock(__objc_runtime_mutex); + return 0; +} + +/* Return selector representing name; prefer a selector with non-NULL type */ +SEL +sel_get_any_typed_uid (const char *name) +{ + struct objc_list *l; + sidx i; + SEL s = NULL; + + objc_mutex_lock(__objc_runtime_mutex); + + i = (sidx) hash_value_for_key (__objc_selector_hash, name); + if (i == 0) + { + objc_mutex_unlock(__objc_runtime_mutex); + return 0; + } + + for (l = (struct objc_list*)sarray_get_safe (__objc_selector_array, i); + l; l = l->tail) + { + s = (SEL) l->head; + if (s->sel_types) + { + objc_mutex_unlock(__objc_runtime_mutex); + return s; + } + } + + objc_mutex_unlock(__objc_runtime_mutex); + return s; +} + +/* return selector representing name */ +SEL +sel_get_any_uid (const char *name) +{ + struct objc_list *l; + sidx i; + + objc_mutex_lock(__objc_runtime_mutex); + + i = (sidx) hash_value_for_key (__objc_selector_hash, name); + if (soffset_decode (i) == 0) + { + objc_mutex_unlock(__objc_runtime_mutex); + return 0; + } + + l = (struct objc_list*)sarray_get_safe (__objc_selector_array, i); + objc_mutex_unlock(__objc_runtime_mutex); + + if (l == 0) + return 0; + + return (SEL)l->head; +} + +/* return selector representing name */ +SEL +sel_get_uid (const char *name) +{ + return sel_register_typed_name (name, 0); +} + +/* Get name of selector. If selector is unknown, the empty string "" + is returned */ +const char* +sel_get_name (SEL selector) +{ + const char *ret; + + objc_mutex_lock(__objc_runtime_mutex); + if ((soffset_decode((sidx)selector->sel_id) > 0) + && (soffset_decode((sidx)selector->sel_id) <= __objc_selector_max_index)) + ret = sarray_get_safe (__objc_selector_names, (sidx) selector->sel_id); + else + ret = 0; + objc_mutex_unlock(__objc_runtime_mutex); + return ret; +} + +BOOL +sel_is_mapped (SEL selector) +{ + unsigned int idx = soffset_decode ((sidx)selector->sel_id); + return ((idx > 0) && (idx <= __objc_selector_max_index)); +} + + +const char* +sel_get_type (SEL selector) +{ + if (selector) + return selector->sel_types; + else + return 0; +} + +/* The uninstalled dispatch table */ +extern struct sarray* __objc_uninstalled_dtable; + +/* Store the passed selector name in the selector record and return its + selector value (value returned by sel_get_uid). + Assumes that the calling function has locked down __objc_runtime_mutex. */ +/* is_const parameter tells us if the name and types parameters + are really constant or not. If YES then they are constant and + we can just store the pointers. If NO then we need to copy + name and types because the pointers may disappear later on. */ +SEL +__sel_register_typed_name (const char *name, const char *types, + struct objc_selector *orig, BOOL is_const) +{ + struct objc_selector* j; + sidx i; + struct objc_list *l; + + i = (sidx) hash_value_for_key (__objc_selector_hash, name); + if (soffset_decode (i) != 0) + { + for (l = (struct objc_list*)sarray_get_safe (__objc_selector_array, i); + l; l = l->tail) + { + SEL s = (SEL)l->head; + if (types == 0 || s->sel_types == 0) + { + if (s->sel_types == types) + { + if (orig) + { + orig->sel_id = (void*)i; + return orig; + } + else + return s; + } + } + else if (!strcmp (s->sel_types, types)) + { + if (orig) + { + orig->sel_id = (void*)i; + return orig; + } + else + return s; + } + } + if (orig) + j = orig; + else + j = objc_malloc (sizeof (struct objc_selector)); + + j->sel_id = (void*)i; + /* Can we use the pointer or must copy types? Don't copy if NULL */ + if ((is_const) || (types == 0)) + j->sel_types = (const char*)types; + else { + j->sel_types = (char *) objc_malloc(strlen(types)+1); + strcpy((char *)j->sel_types, types); + } + l = (struct objc_list*)sarray_get_safe (__objc_selector_array, i); + } + else + { + __objc_selector_max_index += 1; + i = soffset_encode(__objc_selector_max_index); + if (orig) + j = orig; + else + j = objc_malloc (sizeof (struct objc_selector)); + + j->sel_id = (void*)i; + /* Can we use the pointer or must copy types? Don't copy if NULL */ + if ((is_const) || (types == 0)) + j->sel_types = (const char*)types; + else { + j->sel_types = (char *) objc_malloc(strlen(types)+1); + strcpy((char *)j->sel_types, types); + } + l = 0; + } + + DEBUG_PRINTF ("Record selector %s[%s] as: %ld\n", name, types, + soffset_decode (i)); + + { + int is_new = (l == 0); + const char *new_name; + + /* Can we use the pointer or must copy name? Don't copy if NULL */ + if ((is_const) || (name == 0)) + new_name = name; + else { + new_name = (char *) objc_malloc(strlen(name)+1); + strcpy((char *)new_name, name); + } + + l = list_cons ((void*)j, l); + sarray_at_put_safe (__objc_selector_names, i, (void *) new_name); + sarray_at_put_safe (__objc_selector_array, i, (void *) l); + if (is_new) + hash_add (&__objc_selector_hash, (void *) new_name, (void *) i); + } + + sarray_realloc(__objc_uninstalled_dtable, __objc_selector_max_index+1); + + return (SEL) j; +} + +SEL +sel_register_name (const char *name) +{ + SEL ret; + + objc_mutex_lock(__objc_runtime_mutex); + /* Assume that name is not constant static memory and needs to be + copied before put into a runtime structure. is_const == NO */ + ret = __sel_register_typed_name (name, 0, 0, NO); + objc_mutex_unlock(__objc_runtime_mutex); + + return ret; +} + +SEL +sel_register_typed_name (const char *name, const char *type) +{ + SEL ret; + + objc_mutex_lock(__objc_runtime_mutex); + /* Assume that name and type are not constant static memory and need to + be copied before put into a runtime structure. is_const == NO */ + ret = __sel_register_typed_name (name, type, 0, NO); + objc_mutex_unlock(__objc_runtime_mutex); + + return ret; +} + diff --git a/contrib/gcc/objc/sendmsg.c b/contrib/gcc/objc/sendmsg.c new file mode 100644 index 000000000000..24229c1b3cab --- /dev/null +++ b/contrib/gcc/objc/sendmsg.c @@ -0,0 +1,653 @@ +/* GNU Objective C Runtime message lookup + Copyright (C) 1993, 1995, 1996, 1997, 1998 Free Software Foundation, Inc. + Contributed by Kresten Krab Thorup + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +/* $FreeBSD: src/contrib/gcc/objc/sendmsg.c,v 1.3 1999/09/18 11:14:59 obrien Exp $ */ + +#include "../tconfig.h" +#include "runtime.h" +#include "sarray.h" +#include "encoding.h" +#include "runtime-info.h" + +/* this is how we hack STRUCT_VALUE to be 1 or 0 */ +#define gen_rtx(args...) 1 +#define gen_rtx_MEM(args...) 1 +#define rtx int + +#if !defined(STRUCT_VALUE) || STRUCT_VALUE == 0 +#define INVISIBLE_STRUCT_RETURN 1 +#else +#define INVISIBLE_STRUCT_RETURN 0 +#endif + +/* The uninstalled dispatch table */ +struct sarray* __objc_uninstalled_dtable = 0; /* !T:MUTEX */ + +/* Send +initialize to class */ +static void __objc_send_initialize(Class); + +static void __objc_install_dispatch_table_for_class (Class); + +/* Forward declare some functions */ +static void __objc_init_install_dtable(id, SEL); + +/* Various forwarding functions that are used based upon the + return type for the selector. + __objc_block_forward for structures. + __objc_double_forward for floats/doubles. + __objc_word_forward for pointers or types that fit in registers. + */ +static double __objc_double_forward(id, SEL, ...); +static id __objc_word_forward(id, SEL, ...); +typedef struct { id many[8]; } __big; +#if INVISIBLE_STRUCT_RETURN +static __big +#else +static id +#endif +__objc_block_forward(id, SEL, ...); +static Method_t search_for_method_in_hierarchy (Class class, SEL sel); +Method_t search_for_method_in_list(MethodList_t list, SEL op); +id nil_method(id, SEL, ...); + +/* Given a selector, return the proper forwarding implementation. */ +__inline__ +IMP +__objc_get_forward_imp (SEL sel) +{ + const char *t = sel->sel_types; + + if (t && (*t == '[' || *t == '(' || *t == '{') +#ifdef OBJC_MAX_STRUCT_BY_VALUE + && objc_sizeof_type(t) > OBJC_MAX_STRUCT_BY_VALUE +#endif + ) + return (IMP)__objc_block_forward; + else if (t && (*t == 'f' || *t == 'd')) + return (IMP)__objc_double_forward; + else + return (IMP)__objc_word_forward; +} + +/* Given a class and selector, return the selector's implementation. */ +__inline__ +IMP +get_imp (Class class, SEL sel) +{ + void* res = sarray_get_safe (class->dtable, (size_t) sel->sel_id); + if (res == 0) + { + /* Not a valid method */ + if(class->dtable == __objc_uninstalled_dtable) + { + /* The dispatch table needs to be installed. */ + objc_mutex_lock(__objc_runtime_mutex); + __objc_install_dispatch_table_for_class (class); + objc_mutex_unlock(__objc_runtime_mutex); + /* Call ourselves with the installed dispatch table + and get the real method */ + res = get_imp(class, sel); + } + else + { + /* The dispatch table has been installed so the + method just doesn't exist for the class. + Return the forwarding implementation. */ + res = __objc_get_forward_imp(sel); + } + } + return res; +} + +/* Query if an object can respond to a selector, returns YES if the +object implements the selector otherwise NO. Does not check if the +method can be forwarded. */ +__inline__ +BOOL +__objc_responds_to (id object, SEL sel) +{ + void* res; + + /* Install dispatch table if need be */ + if (object->class_pointer->dtable == __objc_uninstalled_dtable) + { + objc_mutex_lock(__objc_runtime_mutex); + __objc_install_dispatch_table_for_class (object->class_pointer); + objc_mutex_unlock(__objc_runtime_mutex); + } + + /* Get the method from the dispatch table */ + res = sarray_get_safe (object->class_pointer->dtable, (size_t) sel->sel_id); + return (res != 0); +} + +/* This is the lookup function. All entries in the table are either a + valid method *or* zero. If zero then either the dispatch table + needs to be installed or it doesn't exist and forwarding is attempted. */ +__inline__ +IMP +objc_msg_lookup(id receiver, SEL op) +{ + IMP result; + if(receiver) + { + result = sarray_get_safe (receiver->class_pointer->dtable, + (sidx)op->sel_id); + if (result == 0) + { + /* Not a valid method */ + if(receiver->class_pointer->dtable == __objc_uninstalled_dtable) + { + /* The dispatch table needs to be installed. + This happens on the very first method call to the class. */ + __objc_init_install_dtable(receiver, op); + + /* Get real method for this in newly installed dtable */ + result = get_imp(receiver->class_pointer, op); + } + else + { + /* The dispatch table has been installed so the + method just doesn't exist for the class. + Attempt to forward the method. */ + result = __objc_get_forward_imp(op); + } + } + return result; + } + else + return nil_method; +} + +IMP +objc_msg_lookup_super (Super_t super, SEL sel) +{ + if (super->self) + return get_imp (super->class, sel); + else + return nil_method; +} + +int method_get_sizeof_arguments (Method*); + +retval_t +objc_msg_sendv(id object, SEL op, arglist_t arg_frame) +{ + Method* m = class_get_instance_method(object->class_pointer, op); + const char *type; + *((id*)method_get_first_argument (m, arg_frame, &type)) = object; + *((SEL*)method_get_next_argument (arg_frame, &type)) = op; + return __builtin_apply((apply_t)m->method_imp, + arg_frame, + method_get_sizeof_arguments (m)); +} + +void +__objc_init_dispatch_tables() +{ + __objc_uninstalled_dtable + = sarray_new(200, 0); +} + +/* This function is called by objc_msg_lookup when the + dispatch table needs to be installed; thus it is called once + for each class, namely when the very first message is sent to it. */ +static void +__objc_init_install_dtable(id receiver, SEL op) +{ + /* This may happen, if the programmer has taken the address of a + method before the dtable was initialized... too bad for him! */ + if(receiver->class_pointer->dtable != __objc_uninstalled_dtable) + return; + + objc_mutex_lock(__objc_runtime_mutex); + + if(CLS_ISCLASS(receiver->class_pointer)) + { + /* receiver is an ordinary object */ + assert(CLS_ISCLASS(receiver->class_pointer)); + + /* install instance methods table */ + __objc_install_dispatch_table_for_class (receiver->class_pointer); + + /* call +initialize -- this will in turn install the factory + dispatch table if not already done :-) */ + __objc_send_initialize(receiver->class_pointer); + } + else + { + /* receiver is a class object */ + assert(CLS_ISCLASS((Class)receiver)); + assert(CLS_ISMETA(receiver->class_pointer)); + + /* Install real dtable for factory methods */ + __objc_install_dispatch_table_for_class (receiver->class_pointer); + + if (strcmp (sel_get_name (op), "initialize")) + __objc_send_initialize((Class)receiver); + else + CLS_SETINITIALIZED((Class)receiver); + } + objc_mutex_unlock(__objc_runtime_mutex); +} + +/* Install dummy table for class which causes the first message to + that class (or instances hereof) to be initialized properly */ +void +__objc_install_premature_dtable(Class class) +{ + assert(__objc_uninstalled_dtable); + class->dtable = __objc_uninstalled_dtable; +} + +/* Send +initialize to class if not already done */ +static void +__objc_send_initialize(Class class) +{ + /* This *must* be a class object */ + assert(CLS_ISCLASS(class)); + assert(!CLS_ISMETA(class)); + + if (!CLS_ISINITIALIZED(class)) + { + CLS_SETINITIALIZED(class); + CLS_SETINITIALIZED(class->class_pointer); + + if(class->super_class) + __objc_send_initialize(class->super_class); + + { + SEL op = sel_register_name ("initialize"); + Class tmpclass = class; + IMP imp = 0; + + while (!imp && tmpclass) { + MethodList_t method_list = tmpclass->class_pointer->methods; + + while(!imp && method_list) { + int i; + Method_t method; + + for (i=0;i<method_list->method_count;i++) { + method = &(method_list->method_list[i]); + if (method->method_name + && method->method_name->sel_id == op->sel_id) { + imp = method->method_imp; + break; + } + } + + method_list = method_list->method_next; + + } + + tmpclass = tmpclass->super_class; + } + if (imp) + (*imp)((id)class, op); + + } + } +} + +/* Walk on the methods list of class and install the methods in the reverse + order of the lists. Since methods added by categories are before the methods + of class in the methods list, this allows categories to substitute methods + declared in class. However if more than one category replaces the same + method nothing is guaranteed about what method will be used. + Assumes that __objc_runtime_mutex is locked down. */ +static void +__objc_install_methods_in_dtable (Class class, MethodList_t method_list) +{ + int i; + + if (!method_list) + return; + + if (method_list->method_next) + __objc_install_methods_in_dtable (class, method_list->method_next); + + for (i = 0; i < method_list->method_count; i++) + { + Method_t method = &(method_list->method_list[i]); + sarray_at_put_safe (class->dtable, + (sidx) method->method_name->sel_id, + method->method_imp); + } +} + +/* Assumes that __objc_runtime_mutex is locked down. */ +static void +__objc_install_dispatch_table_for_class (Class class) +{ + Class super; + + /* If the class has not yet had its class links resolved, we must + re-compute all class links */ + if(!CLS_ISRESOLV(class)) + __objc_resolve_class_links(); + + super = class->super_class; + + if (super != 0 && (super->dtable == __objc_uninstalled_dtable)) + __objc_install_dispatch_table_for_class (super); + + /* Allocate dtable if necessary */ + if (super == 0) + { + objc_mutex_lock(__objc_runtime_mutex); + class->dtable = sarray_new (__objc_selector_max_index, 0); + objc_mutex_unlock(__objc_runtime_mutex); + } + else + class->dtable = sarray_lazy_copy (super->dtable); + + __objc_install_methods_in_dtable (class, class->methods); +} + +void +__objc_update_dispatch_table_for_class (Class class) +{ + Class next; + struct sarray *arr; + + /* not yet installed -- skip it */ + if (class->dtable == __objc_uninstalled_dtable) + return; + + objc_mutex_lock(__objc_runtime_mutex); + + arr = class->dtable; + __objc_install_premature_dtable (class); /* someone might require it... */ + sarray_free (arr); /* release memory */ + + /* could have been lazy... */ + __objc_install_dispatch_table_for_class (class); + + if (class->subclass_list) /* Traverse subclasses */ + for (next = class->subclass_list; next; next = next->sibling_class) + __objc_update_dispatch_table_for_class (next); + + objc_mutex_unlock(__objc_runtime_mutex); +} + + +/* This function adds a method list to a class. This function is + typically called by another function specific to the run-time. As + such this function does not worry about thread safe issues. + + This one is only called for categories. Class objects have their + methods installed right away, and their selectors are made into + SEL's by the function __objc_register_selectors_from_class. */ +void +class_add_method_list (Class class, MethodList_t list) +{ + int i; + + /* Passing of a linked list is not allowed. Do multiple calls. */ + assert (!list->method_next); + + /* Check for duplicates. */ + for (i = 0; i < list->method_count; ++i) + { + Method_t method = &list->method_list[i]; + + if (method->method_name) /* Sometimes these are NULL */ + { + /* This is where selector names are transmogrified to SEL's */ + method->method_name = + sel_register_typed_name ((const char*)method->method_name, + method->method_types); + } + } + + /* Add the methods to the class's method list. */ + list->method_next = class->methods; + class->methods = list; + + /* Update the dispatch table of class */ + __objc_update_dispatch_table_for_class (class); +} + +Method_t +class_get_instance_method(Class class, SEL op) +{ + return search_for_method_in_hierarchy(class, op); +} + +Method_t +class_get_class_method(MetaClass class, SEL op) +{ + return search_for_method_in_hierarchy(class, op); +} + + +/* Search for a method starting from the current class up its hierarchy. + Return a pointer to the method's method structure if found. NULL + otherwise. */ + +static Method_t +search_for_method_in_hierarchy (Class cls, SEL sel) +{ + Method_t method = NULL; + Class class; + + if (! sel_is_mapped (sel)) + return NULL; + + /* Scan the method list of the class. If the method isn't found in the + list then step to its super class. */ + for (class = cls; ((! method) && class); class = class->super_class) + method = search_for_method_in_list (class->methods, sel); + + return method; +} + + + +/* Given a linked list of method and a method's name. Search for the named + method's method structure. Return a pointer to the method's method + structure if found. NULL otherwise. */ +Method_t +search_for_method_in_list (MethodList_t list, SEL op) +{ + MethodList_t method_list = list; + + if (! sel_is_mapped (op)) + return NULL; + + /* If not found then we'll search the list. */ + while (method_list) + { + int i; + + /* Search the method list. */ + for (i = 0; i < method_list->method_count; ++i) + { + Method_t method = &method_list->method_list[i]; + + if (method->method_name) + if (method->method_name->sel_id == op->sel_id) + return method; + } + + /* The method wasn't found. Follow the link to the next list of + methods. */ + method_list = method_list->method_next; + } + + return NULL; +} + +static retval_t __objc_forward (id object, SEL sel, arglist_t args); + +/* Forwarding pointers/integers through the normal registers */ +static id +__objc_word_forward (id rcv, SEL op, ...) +{ + void *args, *res; + + args = __builtin_apply_args (); + res = __objc_forward (rcv, op, args); + if (res) + __builtin_return (res); + else + return res; +} + +/* Specific routine for forwarding floats/double because of + architectural differences on some processors. i386s for + example which uses a floating point stack versus general + registers for floating point numbers. This forward routine + makes sure that GCC restores the proper return values */ +static double +__objc_double_forward (id rcv, SEL op, ...) +{ + void *args, *res; + + args = __builtin_apply_args (); + res = __objc_forward (rcv, op, args); + __builtin_return (res); +} + +#if INVISIBLE_STRUCT_RETURN +static __big +#else +static id +#endif +__objc_block_forward (id rcv, SEL op, ...) +{ + void *args, *res; + + args = __builtin_apply_args (); + res = __objc_forward (rcv, op, args); + if (res) + __builtin_return (res); + else +#if INVISIBLE_STRUCT_RETURN + return (__big) {{0, 0, 0, 0, 0, 0, 0, 0}}; +#else + return nil; +#endif +} + + +/* This function is installed in the dispatch table for all methods which are + not implemented. Thus, it is called when a selector is not recognized. */ +static retval_t +__objc_forward (id object, SEL sel, arglist_t args) +{ + IMP imp; + static SEL frwd_sel = 0; /* !T:SAFE2 */ + SEL err_sel; + + /* first try if the object understands forward:: */ + if (!frwd_sel) + frwd_sel = sel_get_any_uid("forward::"); + + if (__objc_responds_to (object, frwd_sel)) + { + imp = get_imp(object->class_pointer, frwd_sel); + return (*imp)(object, frwd_sel, sel, args); + } + + /* If the object recognizes the doesNotRecognize: method then we're going + to send it. */ + err_sel = sel_get_any_uid ("doesNotRecognize:"); + if (__objc_responds_to (object, err_sel)) + { + imp = get_imp (object->class_pointer, err_sel); + return (*imp) (object, err_sel, sel); + } + + /* The object doesn't recognize the method. Check for responding to + error:. If it does then sent it. */ + { + size_t strlen (const char*); + char msg[256 + strlen ((const char*)sel_get_name (sel)) + + strlen ((const char*)object->class_pointer->name)]; + + sprintf (msg, "(%s) %s does not recognize %s", + (CLS_ISMETA(object->class_pointer) + ? "class" + : "instance" ), + object->class_pointer->name, sel_get_name (sel)); + + err_sel = sel_get_any_uid ("error:"); + if (__objc_responds_to (object, err_sel)) + { + imp = get_imp (object->class_pointer, err_sel); + return (*imp) (object, sel_get_any_uid ("error:"), msg); + } + + /* The object doesn't respond to doesNotRecognize: or error:; Therefore, + a default action is taken. */ + objc_error (object, OBJC_ERR_UNIMPLEMENTED, "%s\n", msg); + + return 0; + } +} + +void +__objc_print_dtable_stats() +{ + int total = 0; + + objc_mutex_lock(__objc_runtime_mutex); + + printf("memory usage: (%s)\n", +#ifdef OBJC_SPARSE2 + "2-level sparse arrays" +#else + "3-level sparse arrays" +#endif + ); + + printf("arrays: %d = %ld bytes\n", narrays, + (long)narrays*sizeof(struct sarray)); + total += narrays*sizeof(struct sarray); + printf("buckets: %d = %ld bytes\n", nbuckets, + (long)nbuckets*sizeof(struct sbucket)); + total += nbuckets*sizeof(struct sbucket); + + printf("idxtables: %d = %ld bytes\n", idxsize, (long)idxsize*sizeof(void*)); + total += idxsize*sizeof(void*); + printf("-----------------------------------\n"); + printf("total: %d bytes\n", total); + printf("===================================\n"); + + objc_mutex_unlock(__objc_runtime_mutex); +} + +/* Returns the uninstalled dispatch table indicator. + If a class' dispatch table points to __objc_uninstalled_dtable + then that means it needs its dispatch table to be installed. */ +__inline__ +struct sarray* +objc_get_uninstalled_dtable() +{ + return __objc_uninstalled_dtable; +} diff --git a/contrib/gcc/objc/thr-dce.c b/contrib/gcc/objc/thr-dce.c new file mode 100644 index 000000000000..0f7063b7e836 --- /dev/null +++ b/contrib/gcc/objc/thr-dce.c @@ -0,0 +1,281 @@ +/* GNU Objective C Runtime Thread Interface + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <pthread.h> +#include <objc/thr.h> +#include "runtime.h" + +/* Key structure for maintaining thread specific storage */ +static pthread_key_t _objc_thread_storage; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* Initialize the thread storage key */ + return pthread_keycreate(&_objc_thread_storage, NULL); +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + /* Destroy the thread storage key */ + /* Not implemented yet */ + /* return pthread_key_delete(&_objc_thread_storage); */ + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + objc_thread_t thread_id; + pthread_t new_thread_handle; + + if (pthread_create(&new_thread_handle, pthread_attr_default, + (void *)func, arg) == 0) + { + /* ??? May not work! (64bit) */ + thread_id = *(objc_thread_t *)&new_thread_handle; + pthread_detach(&new_thread_handle); /* Fully detach thread. */ + } + else + thread_id = NULL; + + return thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + int sys_priority = 0; + + switch (priority) + { + case OBJC_THREAD_INTERACTIVE_PRIORITY: + sys_priority = (PRI_FG_MIN_NP + PRI_FG_MAX_NP) / 2; + break; + default: + case OBJC_THREAD_BACKGROUND_PRIORITY: + sys_priority = (PRI_BG_MIN_NP + PRI_BG_MAX_NP) / 2; + break; + case OBJC_THREAD_LOW_PRIORITY: + sys_priority = (PRI_BG_MIN_NP + PRI_BG_MAX_NP) / 2; + break; + } + + /* Change the priority. */ + if (pthread_setprio(pthread_self(), sys_priority) >= 0) + return 0; + else + /* Failed */ + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + int sys_priority; + + if ((sys_priority = pthread_getprio(pthread_self())) >= 0) { + if (sys_priority >= PRI_FG_MIN_NP && sys_priority <= PRI_FG_MAX_NP) + return OBJC_THREAD_INTERACTIVE_PRIORITY; + if (sys_priority >= PRI_BG_MIN_NP && sys_priority <= PRI_BG_MAX_NP) + return OBJC_THREAD_BACKGROUND_PRIORITY; + return OBJC_THREAD_LOW_PRIORITY; + } + + /* Failed */ + return -1; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + pthread_yield(); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* exit the thread */ + pthread_exit(&__objc_thread_exit_status); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + pthread_t self = pthread_self(); + + return (objc_thread_t) pthread_getunique_np (&self); +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + return pthread_setspecific(_objc_thread_storage, value); +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + void *value = NULL; + + if ( !(pthread_getspecific(_objc_thread_storage, &value)) ) + return value; + + return NULL; +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + if (pthread_mutex_init((pthread_mutex_t *)(&(mutex->backend)), + pthread_mutexattr_default)) + return -1; + else + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + if (pthread_mutex_destroy((pthread_mutex_t *)(&(mutex->backend)))) + return -1; + else + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + return pthread_mutex_lock((pthread_mutex_t *)(&(mutex->backend))); +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + if (pthread_mutex_trylock((pthread_mutex_t *)(&(mutex->backend))) != 1) + return -1; + else + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + return pthread_mutex_unlock((pthread_mutex_t *)(&(mutex->backend))); +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; + + /* + if (pthread_cond_init((pthread_cond_t *)(&(condition->backend)), NULL)) + return -1; + else + return 0; + */ +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; + + /* + return pthread_cond_destroy((pthread_cond_t *)(&(condition->backend))); + */ +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + /* Unimplemented. */ + return -1; + + /* + return pthread_cond_wait((pthread_cond_t *)(&(condition->backend)), + (pthread_mutex_t *)(&(mutex->backend))); + */ +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; + + /* + return pthread_cond_broadcast((pthread_cond_t *)(&(condition->backend))); + */ +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; + + /* + return pthread_cond_signal((pthread_cond_t *)(&(condition->backend))); + */ +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-decosf1.c b/contrib/gcc/objc/thr-decosf1.c new file mode 100644 index 000000000000..0f7063b7e836 --- /dev/null +++ b/contrib/gcc/objc/thr-decosf1.c @@ -0,0 +1,281 @@ +/* GNU Objective C Runtime Thread Interface + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <pthread.h> +#include <objc/thr.h> +#include "runtime.h" + +/* Key structure for maintaining thread specific storage */ +static pthread_key_t _objc_thread_storage; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* Initialize the thread storage key */ + return pthread_keycreate(&_objc_thread_storage, NULL); +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + /* Destroy the thread storage key */ + /* Not implemented yet */ + /* return pthread_key_delete(&_objc_thread_storage); */ + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + objc_thread_t thread_id; + pthread_t new_thread_handle; + + if (pthread_create(&new_thread_handle, pthread_attr_default, + (void *)func, arg) == 0) + { + /* ??? May not work! (64bit) */ + thread_id = *(objc_thread_t *)&new_thread_handle; + pthread_detach(&new_thread_handle); /* Fully detach thread. */ + } + else + thread_id = NULL; + + return thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + int sys_priority = 0; + + switch (priority) + { + case OBJC_THREAD_INTERACTIVE_PRIORITY: + sys_priority = (PRI_FG_MIN_NP + PRI_FG_MAX_NP) / 2; + break; + default: + case OBJC_THREAD_BACKGROUND_PRIORITY: + sys_priority = (PRI_BG_MIN_NP + PRI_BG_MAX_NP) / 2; + break; + case OBJC_THREAD_LOW_PRIORITY: + sys_priority = (PRI_BG_MIN_NP + PRI_BG_MAX_NP) / 2; + break; + } + + /* Change the priority. */ + if (pthread_setprio(pthread_self(), sys_priority) >= 0) + return 0; + else + /* Failed */ + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + int sys_priority; + + if ((sys_priority = pthread_getprio(pthread_self())) >= 0) { + if (sys_priority >= PRI_FG_MIN_NP && sys_priority <= PRI_FG_MAX_NP) + return OBJC_THREAD_INTERACTIVE_PRIORITY; + if (sys_priority >= PRI_BG_MIN_NP && sys_priority <= PRI_BG_MAX_NP) + return OBJC_THREAD_BACKGROUND_PRIORITY; + return OBJC_THREAD_LOW_PRIORITY; + } + + /* Failed */ + return -1; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + pthread_yield(); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* exit the thread */ + pthread_exit(&__objc_thread_exit_status); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + pthread_t self = pthread_self(); + + return (objc_thread_t) pthread_getunique_np (&self); +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + return pthread_setspecific(_objc_thread_storage, value); +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + void *value = NULL; + + if ( !(pthread_getspecific(_objc_thread_storage, &value)) ) + return value; + + return NULL; +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + if (pthread_mutex_init((pthread_mutex_t *)(&(mutex->backend)), + pthread_mutexattr_default)) + return -1; + else + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + if (pthread_mutex_destroy((pthread_mutex_t *)(&(mutex->backend)))) + return -1; + else + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + return pthread_mutex_lock((pthread_mutex_t *)(&(mutex->backend))); +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + if (pthread_mutex_trylock((pthread_mutex_t *)(&(mutex->backend))) != 1) + return -1; + else + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + return pthread_mutex_unlock((pthread_mutex_t *)(&(mutex->backend))); +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; + + /* + if (pthread_cond_init((pthread_cond_t *)(&(condition->backend)), NULL)) + return -1; + else + return 0; + */ +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; + + /* + return pthread_cond_destroy((pthread_cond_t *)(&(condition->backend))); + */ +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + /* Unimplemented. */ + return -1; + + /* + return pthread_cond_wait((pthread_cond_t *)(&(condition->backend)), + (pthread_mutex_t *)(&(mutex->backend))); + */ +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; + + /* + return pthread_cond_broadcast((pthread_cond_t *)(&(condition->backend))); + */ +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; + + /* + return pthread_cond_signal((pthread_cond_t *)(&(condition->backend))); + */ +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-irix.c b/contrib/gcc/objc/thr-irix.c new file mode 100644 index 000000000000..528a3e3a434d --- /dev/null +++ b/contrib/gcc/objc/thr-irix.c @@ -0,0 +1,235 @@ +/* GNU Objective C Runtime Thread Interface - SGI IRIX Implementation + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <stdlib.h> +#include <sys/types.h> +#include <sys/sysmp.h> +#include <sys/prctl.h> +#include <ulocks.h> +#include <objc/thr.h> +#include "runtime.h" + +/* Key structure for maintaining thread specific storage */ +static void * __objc_shared_arena_handle = NULL; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* Name of IRIX arena. */ + char arena_name[64]; + + DEBUG_PRINTF("__objc_init_thread_system\n"); + + /* Construct a temporary name for arena. */ + sprintf(arena_name, "/usr/tmp/objc_%05u", (unsigned)getpid()); + + /* Up to 256 threads. Arena only for threads. */ + usconfig(CONF_INITUSERS, 256); + usconfig(CONF_ARENATYPE, US_SHAREDONLY); + + /* Initialize the arena */ + if (!(__objc_shared_arena_handle = usinit(arena_name))) + /* Failed */ + return -1; + + return 0; +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + objc_thread_t thread_id; + int sys_id; + + if ((sys_id = sproc((void *)func, PR_SALL, arg)) >= 0) + thread_id = (objc_thread_t)sys_id; + else + thread_id = NULL; + + return thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + /* Not implemented yet */ + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + /* Not implemented yet */ + return OBJC_THREAD_INTERACTIVE_PRIORITY; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + sginap(0); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* IRIX only has exit. */ + exit(__objc_thread_exit_status); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + /* Threads are processes. */ + return (objc_thread_t)get_pid(); +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + *((void **)&PRDA->usr_prda) = value; + return 0; +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + return *((void **)&PRDA->usr_prda); +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + if (!( (ulock_t)(mutex->backend) = usnewlock(__objc_shared_arena_handle) )) + return -1; + else + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + usfreelock((ulock_t)(mutex->backend), __objc_shared_arena_handle); + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + if (ussetlock((ulock_t)(mutex->backend)) == 0) + return -1; + else + return 0; +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + if (ustestlock((ulock_t)(mutex->backend)) == 0) + return -1; + else + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + usunsetlock((ulock_t)(mutex->backend)); + return 0; +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + /* Unimplemented. */ + return -1; +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-mach.c b/contrib/gcc/objc/thr-mach.c new file mode 100644 index 000000000000..44af0c1e2869 --- /dev/null +++ b/contrib/gcc/objc/thr-mach.c @@ -0,0 +1,312 @@ +/* GNU Objective C Runtime Thread Implementation + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + Modified for Mach threads by Bill Bumgarner <bbum@friday.com> + Condition functions added by Mircea Oancea <mircea@first.elcom.pub.ro> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <mach/mach.h> +#include <mach/cthreads.h> +#include <objc/thr.h> +#include "runtime.h" + +/* + Obtain the maximum thread priority that can set for t. Under the + mach threading model, it is possible for the developer to adjust the + maximum priority downward only-- cannot be raised without superuser + privileges. Once lowered, it cannot be raised. + */ +static int __mach_get_max_thread_priority(cthread_t t, int *base) +{ + thread_t threadP; + kern_return_t error; + struct thread_sched_info info; + unsigned int info_count=THREAD_SCHED_INFO_COUNT; + + if (t == NULL) + return -1; + + threadP = cthread_thread(t); /* get thread underlying */ + + error=thread_info(threadP, THREAD_SCHED_INFO, + (thread_info_t)&info, &info_count); + + if (error != KERN_SUCCESS) + return -1; + + if (base != NULL) + *base = info.base_priority; + + return info.max_priority; +} + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + return 0; +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + objc_thread_t thread_id; + cthread_t new_thread_handle; + + /* create thread */ + new_thread_handle = cthread_fork((cthread_fn_t)func, arg); + + if(new_thread_handle) + { + /* this is not terribly portable */ + thread_id = *(objc_thread_t *)&new_thread_handle; + cthread_detach(new_thread_handle); + } + else + thread_id = NULL; + + return thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + objc_thread_t *t = objc_thread_id(); + cthread_t cT = (cthread_t) t; + int maxPriority = __mach_get_max_thread_priority(cT, NULL); + int sys_priority = 0; + + if (maxPriority == -1) + return -1; + + switch (priority) + { + case OBJC_THREAD_INTERACTIVE_PRIORITY: + sys_priority = maxPriority; + break; + case OBJC_THREAD_BACKGROUND_PRIORITY: + sys_priority = (maxPriority * 2) / 3; + break; + case OBJC_THREAD_LOW_PRIORITY: + sys_priority = maxPriority / 3; + break; + default: + return -1; + } + + if (sys_priority == 0) + return -1; + + /* Change the priority */ + if (cthread_priority(cT, sys_priority, 0) == KERN_SUCCESS) + return 0; + else + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + objc_thread_t *t = objc_thread_id(); + cthread_t cT = (cthread_t) t; /* see objc_thread_id() */ + int basePriority; + int maxPriority; + int sys_priority = 0; + + int interactiveT, backgroundT, lowT; /* thresholds */ + + maxPriority = __mach_get_max_thread_priority(cT, &basePriority); + + if(maxPriority == -1) + return -1; + + if (basePriority > ( (maxPriority * 2) / 3)) + return OBJC_THREAD_INTERACTIVE_PRIORITY; + + if (basePriority > ( maxPriority / 3)) + return OBJC_THREAD_BACKGROUND_PRIORITY; + + return OBJC_THREAD_LOW_PRIORITY; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + cthread_yield(); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* exit the thread */ + cthread_exit(&__objc_thread_exit_status); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + cthread_t self = cthread_self(); + + return *(objc_thread_t *)&self; +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + cthread_set_data(cthread_self(), (any_t) value); + return 0; +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + return (void *) cthread_data(cthread_self()); +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + int err = 0; + mutex->backend = objc_malloc(sizeof(struct mutex)); + + err = mutex_init((mutex_t)(mutex->backend)); + + if (err != 0) + { + objc_free(mutex->backend); + return -1; + } + else + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + mutex_clear((mutex_t)(mutex->backend)); + + objc_free(mutex->backend); + mutex->backend = NULL; + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + mutex_lock((mutex_t)(mutex->backend)); + return 0; +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + if (mutex_try_lock((mutex_t)(mutex->backend)) == 0) + return -1; + else + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + mutex_unlock((mutex_t)(mutex->backend)); + return 0; +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + condition->backend = objc_malloc(sizeof(struct condition)); + condition_init((condition_t)(condition->backend)); + return 0; +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + condition_clear((condition_t)(condition->backend)); + objc_free(condition->backend); + condition->backend = NULL; + return 0; +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + condition_wait((condition_t)(condition->backend), + (mutex_t)(mutex->backend)); + return 0; +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + condition_broadcast((condition_t)(condition->backend)); + return 0; +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + condition_signal((condition_t)(condition->backend)); + return 0; +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-os2.c b/contrib/gcc/objc/thr-os2.c new file mode 100644 index 000000000000..a0d7d436613e --- /dev/null +++ b/contrib/gcc/objc/thr-os2.c @@ -0,0 +1,267 @@ +/* GNU Objective C Runtime Thread Interface - OS/2 emx Implementation + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Thomas Baier (baier@ci.tuwien.ac.at) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <objc/thr.h> +#include "runtime.h" + +#define INCL_DOSSEMAPHORES +#define INCL_DOSPROCESS + +/* + * conflicts with objc.h: SEL, BOOL, id + * solution: prefixing those with _OS2_ before including <os2.h> + */ +#define SEL _OS2_SEL +#define BOOL _OS2_BOOL +#define id _OS2_id +#include <os2.h> +#undef id +#undef SEL +#undef BOOL + +#include <stdlib.h> + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + return 0; +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + int thread_id = 0; + + if ((thread_id = _beginthread (func,NULL,32768,arg)) < 0) + thread_id = 0; + + return (objc_thread_t)thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + ULONG sys_class = 0; + ULONG sys_priority = 0; + + /* OBJC_THREAD_INTERACTIVE_PRIORITY -> PRTYC_FOREGROUNDSERVER + * OBJC_THREAD_BACKGROUND_PRIORITY -> PRTYC_REGULAR + * OBJC_THREAD_LOW_PRIORITY -> PRTYC_IDLETIME */ + + switch (priority) { + case OBJC_THREAD_INTERACTIVE_PRIORITY: + sys_class = PRTYC_REGULAR; + sys_priority = 10; + break; + default: + case OBJC_THREAD_BACKGROUND_PRIORITY: + sys_class = PRTYC_IDLETIME; + sys_priority = 25; + break; + case OBJC_THREAD_LOW_PRIORITY: + sys_class = PRTYC_IDLETIME; + sys_priority = 0; + break; + } + + /* Change priority */ + if (!DosSetPriority (PRTYS_THREAD,sys_class,sys_priority,*_threadid)) + return 0; + else + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + PTIB ptib; + PPIB ppib; + + /* get information about current thread */ + DosGetInfoBlocks (&ptib,&ppib); + + switch (ptib->tib_ptib2->tib2_ulpri) + { + case PRTYC_IDLETIME: + case PRTYC_REGULAR: + case PRTYC_TIMECRITICAL: + case PRTYC_FOREGROUNDSERVER: + default: + return OBJC_THREAD_INTERACTIVE_PRIORITY; + } + + return -1; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + DosSleep (0); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* terminate the thread, NEVER use DosExit () */ + _endthread (); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + return (objc_thread_t) *_threadid; +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + *_threadstore () = value; + + return 0; +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + return *_threadstore (); +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + if (DosCreateMutexSem (NULL, (HMTX)(&(mutex->backend)),0L,0) > 0) + return -1; + else + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + DosCloseMutexSem ((HMTX)(mutex->backend)); + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + if (DosRequestMutexSem ((HMTX)(mutex->backend),-1L) != 0) + return -1; + else + return 0; +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + if (DosRequestMutexSem ((HMTX)(mutex->backend),0L) != 0) + return -1; + else + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + if (DosReleaseMutexSem((HMTX)(mutex->backend)) != 0) + return -1; + else + return 0; +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + /* Unimplemented. */ + return -1; +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-posix.c b/contrib/gcc/objc/thr-posix.c new file mode 100644 index 000000000000..5b40f711be80 --- /dev/null +++ b/contrib/gcc/objc/thr-posix.c @@ -0,0 +1,229 @@ +/* GNU Objective C Runtime Thread Interface for POSIX compliant threads + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + Modified for Linux/Pthreads by Kai-Uwe Sattler (kus@iti.cs.uni-magdeburg.de) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <objc/thr.h> +#include "runtime.h" +#include <pthread.h> + +/* Key structure for maintaining thread specific storage */ +static pthread_key_t _objc_thread_storage; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* Initialize the thread storage key */ + return pthread_key_create(&_objc_thread_storage, NULL); +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + objc_thread_t thread_id; + pthread_t new_thread_handle; + + if ( !(pthread_create(&new_thread_handle, NULL, (void *)func, arg)) ) + thread_id = *(objc_thread_t *)&new_thread_handle; + else + thread_id = NULL; + + return thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + /* Not implemented yet */ + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + /* Not implemented yet */ + return -1; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + sched_yield(); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* exit the thread */ + pthread_exit(&__objc_thread_exit_status); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + pthread_t self = pthread_self(); + + return *(objc_thread_t *)&self; +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + return pthread_setspecific(_objc_thread_storage, value); +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + return pthread_getspecific(_objc_thread_storage); +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + mutex->backend = objc_malloc(sizeof(pthread_mutex_t)); + + if (pthread_mutex_init((pthread_mutex_t *)mutex->backend, NULL)) + { + objc_free(mutex->backend); + mutex->backend = NULL; + return -1; + } + + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + if (pthread_mutex_destroy((pthread_mutex_t *)mutex->backend)) + return -1; + + objc_free(mutex->backend); + mutex->backend = NULL; + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + return pthread_mutex_lock((pthread_mutex_t *)mutex->backend); +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + return pthread_mutex_trylock((pthread_mutex_t *)mutex->backend); +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + return pthread_mutex_unlock((pthread_mutex_t *)mutex->backend); +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + condition->backend = objc_malloc(sizeof(pthread_cond_t)); + + if (pthread_cond_init((pthread_cond_t *)condition->backend, NULL)) + { + objc_free(condition->backend); + condition->backend = NULL; + return -1; + } + + return 0; +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + if (pthread_cond_destroy((pthread_cond_t *)condition->backend)) + return -1; + + objc_free(condition->backend); + condition->backend = NULL; + return 0; +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + return pthread_cond_wait((pthread_cond_t *)condition->backend, + (pthread_mutex_t *)mutex->backend); +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + return pthread_cond_broadcast((pthread_cond_t *)condition->backend); +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + return pthread_cond_signal((pthread_cond_t *)condition->backend); +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-pthreads.c b/contrib/gcc/objc/thr-pthreads.c new file mode 100644 index 000000000000..2efdd15bc541 --- /dev/null +++ b/contrib/gcc/objc/thr-pthreads.c @@ -0,0 +1,218 @@ +/* GNU Objective C Runtime Thread Implementation for PCThreads under GNU/Linux. + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Scott Christley <scottc@net-community.com> + Condition functions added by: Mircea Oancea <mircea@first.elcom.pub.ro> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <pcthread.h> +#include <objc/thr.h> +#include "runtime.h" + +/* Key structure for maintaining thread specific storage */ +static pthread_key_t _objc_thread_storage; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* Initialize the thread storage key */ + return pthread_key_create(&_objc_thread_storage, NULL); +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + /* Destroy the thread storage key */ + /* Not implemented yet */ + /* return pthread_key_delete(&_objc_thread_storage); */ + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + objc_thread_t thread_id; + pthread_t new_thread_handle; + + if ( !(pthread_create(&new_thread_handle, NULL, (void *)func, arg)) ) + thread_id = *(objc_thread_t *)&new_thread_handle; + else + thread_id = NULL; + + return thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + /* Not implemented yet */ + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + /* Not implemented yet */ + return OBJC_THREAD_INTERACTIVE_PRIORITY; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + pthread_yield(NULL); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* exit the thread */ + pthread_exit(&__objc_thread_exit_status); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + pthread_t self = pthread_self(); + + return *(objc_thread_t *)&self; +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + return pthread_setspecific(_objc_thread_storage, value); +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + void *value = NULL; + + if ( !(pthread_getspecific(_objc_thread_storage, &value)) ) + return value; + + return NULL; +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + if (pthread_mutex_init((pthread_mutex_t *)(&(mutex->backend)), NULL)) + return -1; + else + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + if (pthread_mutex_destroy((pthread_mutex_t *)(&(mutex->backend)))) + return -1; + else + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + return pthread_mutex_lock((pthread_mutex_t *)(&(mutex->backend))); +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + return pthread_mutex_trylock((pthread_mutex_t *)(&(mutex->backend))); +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + return pthread_mutex_unlock((pthread_mutex_t *)(&(mutex->backend))); +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + if (pthread_cond_init((pthread_cond_t *)(&(condition->backend)), NULL)) + return -1; + else + return 0; +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + return pthread_cond_destroy((pthread_cond_t *)(&(condition->backend))); +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + return pthread_cond_wait((pthread_cond_t *)(&(condition->backend)), + (pthread_mutex_t *)(&(mutex->backend))); +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + return pthread_cond_broadcast((pthread_cond_t *)(&(condition->backend))); +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + return pthread_cond_signal((pthread_cond_t *)(&(condition->backend))); +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-single.c b/contrib/gcc/objc/thr-single.c new file mode 100644 index 000000000000..b196677c6b69 --- /dev/null +++ b/contrib/gcc/objc/thr-single.c @@ -0,0 +1,192 @@ +/* GNU Objective C Runtime Thread Implementation + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <objc/thr.h> +#include "runtime.h" + +/* Thread local storage for a single thread */ +static void *thread_local_storage = NULL; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* No thread support available */ + return -1; +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + /* No thread support available */ + return -1; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + /* No thread support available */ + return NULL; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + /* No thread support available */ + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + return OBJC_THREAD_INTERACTIVE_PRIORITY; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + return; +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* No thread support available */ + /* Should we really exit the program */ + /* exit(&__objc_thread_exit_status); */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + /* No thread support, use 1. */ + return (objc_thread_t)1; +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + thread_local_storage = value; + return 0; +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + return thread_local_storage; +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + /* There can only be one thread, so we always get the lock */ + return 0; +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + /* There can only be one thread, so we always get the lock */ + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + return 0; +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + return 0; +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + return 0; +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + return 0; +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + return 0; +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + return 0; +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-solaris.c b/contrib/gcc/objc/thr-solaris.c new file mode 100644 index 000000000000..90351b43cf6c --- /dev/null +++ b/contrib/gcc/objc/thr-solaris.c @@ -0,0 +1,259 @@ +/* GNU Objective C Runtime Thread Interface + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + Conditions added by Mircea Oancea (mircea@first.elcom.pub.ro) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <objc/thr.h> +#include "runtime.h" + +#include <thread.h> +#include <synch.h> +#include <errno.h> + +/* Key structure for maintaining thread specific storage */ +static thread_key_t __objc_thread_data_key; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* Initialize the thread storage key */ + if (thr_keycreate(&__objc_thread_data_key, NULL) == 0) + return 0; + else + return -1; +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + objc_thread_t thread_id; + thread_t new_thread_id = 0; + + if (thr_create(NULL, 0, (void *)func, arg, + THR_DETACHED | THR_NEW_LWP, + &new_thread_id) == 0) + thread_id = *(objc_thread_t *)&new_thread_id; + else + thread_id = NULL; + + return thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + int sys_priority = 0; + + switch (priority) + { + case OBJC_THREAD_INTERACTIVE_PRIORITY: + sys_priority = 300; + break; + default: + case OBJC_THREAD_BACKGROUND_PRIORITY: + sys_priority = 200; + break; + case OBJC_THREAD_LOW_PRIORITY: + sys_priority = 1000; + break; + } + + /* Change priority */ + if (thr_setprio(thr_self(), sys_priority) == 0) + return 0; + else + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + int sys_priority; + + if (thr_getprio(thr_self(), &sys_priority) == 0) + { + if (sys_priority >= 250) + return OBJC_THREAD_INTERACTIVE_PRIORITY; + else if (sys_priority >= 150) + return OBJC_THREAD_BACKGROUND_PRIORITY; + return OBJC_THREAD_LOW_PRIORITY; + } + + /* Couldn't get priority. */ + return -1; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + thr_yield(); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* exit the thread */ + thr_exit(&__objc_thread_exit_status); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + return (objc_thread_t)thr_self(); +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + if (thr_setspecific(__objc_thread_data_key, value) == 0) + return 0; + else + return -1; +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + void *value = NULL; + + if (thr_getspecific(__objc_thread_data_key, &value) == 0) + return value; + + return NULL; +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + if (mutex_init( (mutex_t *)(&(mutex->backend)), USYNC_THREAD, 0)) + return -1; + else + return 0; +} + + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + mutex_destroy((mutex_t *)(&(mutex->backend))); + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + if (mutex_lock((mutex_t *)(&(mutex->backend))) != 0) + return -1; + else + return 0; +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + if (mutex_trylock((mutex_t *)(&(mutex->backend))) != 0) + return -1; + else + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + if (mutex_unlock((mutex_t *)(&(mutex->backend))) != 0) + return -1; + else + return 0; +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + return cond_init((cond_t *)(&(condition->backend)), USYNC_THREAD, NULL); +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + return cond_destroy((cond_t *)(&(condition->backend))); +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + return cond_wait((cond_t *)(&(condition->backend)), + (mutex_t *)(&(mutex->backend))); +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + return cond_broadcast((cond_t *)(&(condition->backend))); +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + return cond_signal((cond_t *)(&(condition->backend))); +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-vxworks.c b/contrib/gcc/objc/thr-vxworks.c new file mode 100644 index 000000000000..b196677c6b69 --- /dev/null +++ b/contrib/gcc/objc/thr-vxworks.c @@ -0,0 +1,192 @@ +/* GNU Objective C Runtime Thread Implementation + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <objc/thr.h> +#include "runtime.h" + +/* Thread local storage for a single thread */ +static void *thread_local_storage = NULL; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* No thread support available */ + return -1; +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + /* No thread support available */ + return -1; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + /* No thread support available */ + return NULL; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + /* No thread support available */ + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + return OBJC_THREAD_INTERACTIVE_PRIORITY; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + return; +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* No thread support available */ + /* Should we really exit the program */ + /* exit(&__objc_thread_exit_status); */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + /* No thread support, use 1. */ + return (objc_thread_t)1; +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + thread_local_storage = value; + return 0; +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + return thread_local_storage; +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + /* There can only be one thread, so we always get the lock */ + return 0; +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + /* There can only be one thread, so we always get the lock */ + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + return 0; +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + return 0; +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + return 0; +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + return 0; +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + return 0; +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + return 0; +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr-win32.c b/contrib/gcc/objc/thr-win32.c new file mode 100644 index 000000000000..8570ffd997ef --- /dev/null +++ b/contrib/gcc/objc/thr-win32.c @@ -0,0 +1,272 @@ +/* GNU Objective C Runtime Thread Interface - Win32 Implementation + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <objc/thr.h> +#include "runtime.h" + +#ifndef __OBJC__ +#define __OBJC__ +#endif +#include <windows.h> + +/* Key structure for maintaining thread specific storage */ +static DWORD __objc_data_tls = (DWORD)-1; + +/* Backend initialization functions */ + +/* Initialize the threads subsystem. */ +int +__objc_init_thread_system(void) +{ + /* Initialize the thread storage key */ + if ((__objc_data_tls = TlsAlloc()) != (DWORD)-1) + return 0; + else + return -1; +} + +/* Close the threads subsystem. */ +int +__objc_close_thread_system(void) +{ + if (__objc_data_tls != (DWORD)-1) + TlsFree(__objc_data_tls); + return 0; +} + +/* Backend thread functions */ + +/* Create a new thread of execution. */ +objc_thread_t +__objc_thread_detach(void (*func)(void *arg), void *arg) +{ + DWORD thread_id = 0; + HANDLE win32_handle; + + if (!(win32_handle = CreateThread(NULL, 0, (LPTHREAD_START_ROUTINE)func, + arg, 0, &thread_id))) + thread_id = 0; + + return (objc_thread_t)thread_id; +} + +/* Set the current thread's priority. */ +int +__objc_thread_set_priority(int priority) +{ + int sys_priority = 0; + + switch (priority) + { + case OBJC_THREAD_INTERACTIVE_PRIORITY: + sys_priority = THREAD_PRIORITY_NORMAL; + break; + default: + case OBJC_THREAD_BACKGROUND_PRIORITY: + sys_priority = THREAD_PRIORITY_BELOW_NORMAL; + break; + case OBJC_THREAD_LOW_PRIORITY: + sys_priority = THREAD_PRIORITY_LOWEST; + break; + } + + /* Change priority */ + if (SetThreadPriority(GetCurrentThread(), sys_priority)) + return 0; + else + return -1; +} + +/* Return the current thread's priority. */ +int +__objc_thread_get_priority(void) +{ + int sys_priority; + + sys_priority = GetThreadPriority(GetCurrentThread()); + + switch (sys_priority) + { + case THREAD_PRIORITY_HIGHEST: + case THREAD_PRIORITY_TIME_CRITICAL: + case THREAD_PRIORITY_ABOVE_NORMAL: + case THREAD_PRIORITY_NORMAL: + return OBJC_THREAD_INTERACTIVE_PRIORITY; + + default: + case THREAD_PRIORITY_BELOW_NORMAL: + return OBJC_THREAD_BACKGROUND_PRIORITY; + + case THREAD_PRIORITY_IDLE: + case THREAD_PRIORITY_LOWEST: + return OBJC_THREAD_LOW_PRIORITY; + } + + /* Couldn't get priority. */ + return -1; +} + +/* Yield our process time to another thread. */ +void +__objc_thread_yield(void) +{ + Sleep(0); +} + +/* Terminate the current thread. */ +int +__objc_thread_exit(void) +{ + /* exit the thread */ + ExitThread(__objc_thread_exit_status); + + /* Failed if we reached here */ + return -1; +} + +/* Returns an integer value which uniquely describes a thread. */ +objc_thread_t +__objc_thread_id(void) +{ + return (objc_thread_t)GetCurrentThreadId(); +} + +/* Sets the thread's local storage pointer. */ +int +__objc_thread_set_data(void *value) +{ + if (TlsSetValue(__objc_data_tls, value)) + return 0; + else + return -1; +} + +/* Returns the thread's local storage pointer. */ +void * +__objc_thread_get_data(void) +{ + return TlsGetValue(__objc_data_tls); /* Return thread data. */ +} + +/* Backend mutex functions */ + +/* Allocate a mutex. */ +int +__objc_mutex_allocate(objc_mutex_t mutex) +{ + if ((mutex->backend = (void *)CreateMutex(NULL, 0, NULL)) == NULL) + return -1; + else + return 0; +} + +/* Deallocate a mutex. */ +int +__objc_mutex_deallocate(objc_mutex_t mutex) +{ + CloseHandle((HANDLE)(mutex->backend)); + return 0; +} + +/* Grab a lock on a mutex. */ +int +__objc_mutex_lock(objc_mutex_t mutex) +{ + int status; + + status = WaitForSingleObject((HANDLE)(mutex->backend), INFINITE); + if (status != WAIT_OBJECT_0 && status != WAIT_ABANDONED) + return -1; + else + return 0; +} + +/* Try to grab a lock on a mutex. */ +int +__objc_mutex_trylock(objc_mutex_t mutex) +{ + int status; + + status = WaitForSingleObject((HANDLE)(mutex->backend), 0); + if (status != WAIT_OBJECT_0 && status != WAIT_ABANDONED) + return -1; + else + return 0; +} + +/* Unlock the mutex */ +int +__objc_mutex_unlock(objc_mutex_t mutex) +{ + if (ReleaseMutex((HANDLE)(mutex->backend)) == 0) + return -1; + else + return 0; +} + +/* Backend condition mutex functions */ + +/* Allocate a condition. */ +int +__objc_condition_allocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Deallocate a condition. */ +int +__objc_condition_deallocate(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Wait on the condition */ +int +__objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + /* Unimplemented. */ + return -1; +} + +/* Wake up all threads waiting on this condition. */ +int +__objc_condition_broadcast(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* Wake up one thread waiting on this condition. */ +int +__objc_condition_signal(objc_condition_t condition) +{ + /* Unimplemented. */ + return -1; +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr.c b/contrib/gcc/objc/thr.c new file mode 100644 index 000000000000..f1c957aaa15c --- /dev/null +++ b/contrib/gcc/objc/thr.c @@ -0,0 +1,534 @@ +/* GNU Objective C Runtime Thread Interface + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled with + GCC to produce an executable, this does not cause the resulting executable + to be covered by the GNU General Public License. This exception does not + however invalidate any other reasons why the executable file might be + covered by the GNU General Public License. */ + +#include <stdlib.h> +#include "runtime.h" + +/* Global exit status. */ +int __objc_thread_exit_status = 0; + +/* Flag which lets us know if we ever became multi threaded */ +int __objc_is_multi_threaded = 0; + +/* The hook function called when the runtime becomes multi threaded */ +objc_thread_callback _objc_became_multi_threaded = NULL; + +/* + Use this to set the hook function that will be called when the + runtime initially becomes multi threaded. + The hook function is only called once, meaning only when the + 2nd thread is spawned, not for each and every thread. + + It returns the previous hook function or NULL if there is none. + + A program outside of the runtime could set this to some function so + it can be informed; for example, the GNUstep Base Library sets it + so it can implement the NSBecomingMultiThreaded notification. + */ +objc_thread_callback objc_set_thread_callback(objc_thread_callback func) +{ + objc_thread_callback temp = _objc_became_multi_threaded; + _objc_became_multi_threaded = func; + return temp; +} + +/* + Private functions + + These functions are utilized by the frontend, but they are not + considered part of the public interface. + */ + +/* + First function called in a thread, starts everything else. + + This function is passed to the backend by objc_thread_detach + as the starting function for a new thread. + */ +struct __objc_thread_start_state +{ + SEL selector; + id object; + id argument; +}; + +static volatile void +__objc_thread_detach_function(struct __objc_thread_start_state *istate) +{ + /* Valid state? */ + if (istate) { + id (*imp)(id,SEL,id); + SEL selector = istate->selector; + id object = istate->object; + id argument = istate->argument; + + /* Don't need anymore so free it */ + objc_free(istate); + + /* Clear out the thread local storage */ + objc_thread_set_data(NULL); + + /* Check to see if we just became multi threaded */ + if (!__objc_is_multi_threaded) + { + __objc_is_multi_threaded = 1; + + /* Call the hook function */ + if (_objc_became_multi_threaded != NULL) + (*_objc_became_multi_threaded)(); + } + + /* Call the method */ + if ((imp = (id(*)(id, SEL, id))objc_msg_lookup(object, selector))) + (*imp)(object, selector, argument); + else + objc_error(object, OBJC_ERR_UNIMPLEMENTED, + "objc_thread_detach called with bad selector.\n"); + } + else + objc_error(nil, OBJC_ERR_BAD_STATE, + "objc_thread_detach called with NULL state.\n"); + + /* Exit the thread */ + objc_thread_exit(); +} + +/* + Frontend functions + + These functions constitute the public interface to the Objective-C thread + and mutex functionality. + */ + +/* Frontend thread functions */ + +/* + Detach a new thread of execution and return its id. Returns NULL if fails. + Thread is started by sending message with selector to object. Message + takes a single argument. + */ +objc_thread_t +objc_thread_detach(SEL selector, id object, id argument) +{ + struct __objc_thread_start_state *istate; + objc_thread_t thread_id = NULL; + + /* Allocate the state structure */ + if (!(istate = (struct __objc_thread_start_state *) + objc_malloc(sizeof(*istate)))) + return NULL; + + /* Initialize the state structure */ + istate->selector = selector; + istate->object = object; + istate->argument = argument; + + /* lock access */ + objc_mutex_lock(__objc_runtime_mutex); + + /* Call the backend to spawn the thread */ + if ((thread_id = __objc_thread_detach((void *)__objc_thread_detach_function, + istate)) == NULL) + { + /* failed! */ + objc_mutex_unlock(__objc_runtime_mutex); + objc_free(istate); + return NULL; + } + + /* Increment our thread counter */ + __objc_runtime_threads_alive++; + objc_mutex_unlock(__objc_runtime_mutex); + + return thread_id; +} + +/* Set the current thread's priority. */ +int +objc_thread_set_priority(int priority) +{ + /* Call the backend */ + return __objc_thread_set_priority(priority); +} + +/* Return the current thread's priority. */ +int +objc_thread_get_priority(void) +{ + /* Call the backend */ + return __objc_thread_get_priority(); +} + +/* + Yield our process time to another thread. Any BUSY waiting that is done + by a thread should use this function to make sure that other threads can + make progress even on a lazy uniprocessor system. + */ +void +objc_thread_yield(void) +{ + /* Call the backend */ + __objc_thread_yield(); +} + +/* + Terminate the current tread. Doesn't return. + Actually, if it failed returns -1. + */ +int +objc_thread_exit(void) +{ + /* Decrement our counter of the number of threads alive */ + objc_mutex_lock(__objc_runtime_mutex); + __objc_runtime_threads_alive--; + objc_mutex_unlock(__objc_runtime_mutex); + + /* Call the backend to terminate the thread */ + return __objc_thread_exit(); +} + +/* + Returns an integer value which uniquely describes a thread. Must not be + NULL which is reserved as a marker for "no thread". + */ +objc_thread_t +objc_thread_id(void) +{ + /* Call the backend */ + return __objc_thread_id(); +} + +/* + Sets the thread's local storage pointer. + Returns 0 if successful or -1 if failed. + */ +int +objc_thread_set_data(void *value) +{ + /* Call the backend */ + return __objc_thread_set_data(value); +} + +/* + Returns the thread's local storage pointer. Returns NULL on failure. + */ +void * +objc_thread_get_data(void) +{ + /* Call the backend */ + return __objc_thread_get_data(); +} + +/* Frontend mutex functions */ + +/* + Allocate a mutex. Return the mutex pointer if successful or NULL if the + allocation failed for any reason. + */ +objc_mutex_t +objc_mutex_allocate(void) +{ + objc_mutex_t mutex; + + /* Allocate the mutex structure */ + if (!(mutex = (objc_mutex_t)objc_malloc(sizeof(struct objc_mutex)))) + return NULL; + + /* Call backend to create the mutex */ + if (__objc_mutex_allocate(mutex)) + { + /* failed! */ + objc_free(mutex); + return NULL; + } + + /* Initialize mutex */ + mutex->owner = NULL; + mutex->depth = 0; + return mutex; +} + +/* + Deallocate a mutex. Note that this includes an implicit mutex_lock to + insure that no one else is using the lock. It is legal to deallocate + a lock if we have a lock on it, but illegal to deallocate a lock held + by anyone else. + Returns the number of locks on the thread. (1 for deallocate). + */ +int +objc_mutex_deallocate(objc_mutex_t mutex) +{ + int depth; + + /* Valid mutex? */ + if (!mutex) + return -1; + + /* Acquire lock on mutex */ + depth = objc_mutex_lock(mutex); + + /* Call backend to destroy mutex */ + if (__objc_mutex_deallocate(mutex)) + return -1; + + /* Free the mutex structure */ + objc_free(mutex); + + /* Return last depth */ + return depth; +} + +/* + Grab a lock on a mutex. If this thread already has a lock on this mutex + then we increment the lock count. If another thread has a lock on the + mutex we block and wait for the thread to release the lock. + Returns the lock count on the mutex held by this thread. + */ +int +objc_mutex_lock(objc_mutex_t mutex) +{ + objc_thread_t thread_id; + int status; + + /* Valid mutex? */ + if (!mutex) + return -1; + + /* If we already own the lock then increment depth */ + thread_id = objc_thread_id(); + if (mutex->owner == thread_id) + return ++mutex->depth; + + /* Call the backend to lock the mutex */ + status = __objc_mutex_lock(mutex); + + /* Failed? */ + if (status) + return status; + + /* Successfully locked the thread */ + mutex->owner = thread_id; + return mutex->depth = 1; +} + +/* + Try to grab a lock on a mutex. If this thread already has a lock on + this mutex then we increment the lock count and return it. If another + thread has a lock on the mutex returns -1. + */ +int +objc_mutex_trylock(objc_mutex_t mutex) +{ + objc_thread_t thread_id; + int status; + + /* Valid mutex? */ + if (!mutex) + return -1; + + /* If we already own the lock then increment depth */ + thread_id = objc_thread_id(); + if (mutex->owner == thread_id) + return ++mutex->depth; + + /* Call the backend to try to lock the mutex */ + status = __objc_mutex_trylock(mutex); + + /* Failed? */ + if (status) + return status; + + /* Successfully locked the thread */ + mutex->owner = thread_id; + return mutex->depth = 1; +} + +/* + Unlocks the mutex by one level. + Decrements the lock count on this mutex by one. + If the lock count reaches zero, release the lock on the mutex. + Returns the lock count on the mutex. + It is an error to attempt to unlock a mutex which this thread + doesn't hold in which case return -1 and the mutex is unaffected. + */ +int +objc_mutex_unlock(objc_mutex_t mutex) +{ + objc_thread_t thread_id; + int status; + + /* Valid mutex? */ + if (!mutex) + return -1; + + /* If another thread owns the lock then abort */ + thread_id = objc_thread_id(); + if (mutex->owner != thread_id) + return -1; + + /* Decrement depth and return */ + if (mutex->depth > 1) + return --mutex->depth; + + /* Depth down to zero so we are no longer the owner */ + mutex->depth = 0; + mutex->owner = NULL; + + /* Have the backend unlock the mutex */ + status = __objc_mutex_unlock(mutex); + + /* Failed? */ + if (status) + return status; + + return 0; +} + +/* Frontend condition mutex functions */ + +/* + Allocate a condition. Return the condition pointer if successful or NULL + if the allocation failed for any reason. + */ +objc_condition_t +objc_condition_allocate(void) +{ + objc_condition_t condition; + + /* Allocate the condition mutex structure */ + if (!(condition = + (objc_condition_t)objc_malloc(sizeof(struct objc_condition)))) + return NULL; + + /* Call the backend to create the condition mutex */ + if (__objc_condition_allocate(condition)) + { + /* failed! */ + objc_free(condition); + return NULL; + } + + /* Success! */ + return condition; +} + +/* + Deallocate a condition. Note that this includes an implicit + condition_broadcast to insure that waiting threads have the opportunity + to wake. It is legal to dealloc a condition only if no other + thread is/will be using it. Here we do NOT check for other threads + waiting but just wake them up. + */ +int +objc_condition_deallocate(objc_condition_t condition) +{ + /* Broadcast the condition */ + if (objc_condition_broadcast(condition)) + return -1; + + /* Call the backend to destroy */ + if (__objc_condition_deallocate(condition)) + return -1; + + /* Free the condition mutex structure */ + objc_free(condition); + + return 0; +} + +/* + Wait on the condition unlocking the mutex until objc_condition_signal() + or objc_condition_broadcast() are called for the same condition. The + given mutex *must* have the depth set to 1 so that it can be unlocked + here, so that someone else can lock it and signal/broadcast the condition. + The mutex is used to lock access to the shared data that make up the + "condition" predicate. + */ +int +objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex) +{ + objc_thread_t thread_id; + + /* Valid arguments? */ + if (!mutex || !condition) + return -1; + + /* Make sure we are owner of mutex */ + thread_id = objc_thread_id(); + if (mutex->owner != thread_id) + return -1; + + /* Cannot be locked more than once */ + if (mutex->depth > 1) + return -1; + + /* Virtually unlock the mutex */ + mutex->depth = 0; + mutex->owner = (objc_thread_t)NULL; + + /* Call the backend to wait */ + __objc_condition_wait(condition, mutex); + + /* Make ourselves owner of the mutex */ + mutex->owner = thread_id; + mutex->depth = 1; + + return 0; +} + +/* + Wake up all threads waiting on this condition. It is recommended that + the called would lock the same mutex as the threads in objc_condition_wait + before changing the "condition predicate" and make this call and unlock it + right away after this call. + */ +int +objc_condition_broadcast(objc_condition_t condition) +{ + /* Valid condition mutex? */ + if (!condition) + return -1; + + return __objc_condition_broadcast(condition); +} + +/* + Wake up one thread waiting on this condition. It is recommended that + the called would lock the same mutex as the threads in objc_condition_wait + before changing the "condition predicate" and make this call and unlock it + right away after this call. + */ +int +objc_condition_signal(objc_condition_t condition) +{ + /* Valid condition mutex? */ + if (!condition) + return -1; + + return __objc_condition_signal(condition); +} + +/* End of File */ diff --git a/contrib/gcc/objc/thr.h b/contrib/gcc/objc/thr.h new file mode 100644 index 000000000000..f904733695a8 --- /dev/null +++ b/contrib/gcc/objc/thr.h @@ -0,0 +1,143 @@ +/* Thread and mutex controls for Objective C. + Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Contributed by Galen C. Hunt (gchunt@cs.rochester.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +GNU CC is free software; you can redistribute it and/or modify it under the +terms of the GNU General Public License as published by the Free Software +Foundation; either version 2, or (at your option) any later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +details. + +You should have received a copy of the GNU General Public License along with +GNU CC; see the file COPYING. If not, write to the Free Software +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files + compiled with GCC to produce an executable, this does not cause + the resulting executable to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + + +#ifndef __thread_INCLUDE_GNU +#define __thread_INCLUDE_GNU + +#include "objc/objc.h" + +/************************************************************************* + * Universal static variables: + */ +extern int __objc_thread_exit_status; /* Global exit status. */ + +/******** + * Thread safe implementation types and functions. + */ + +/* Thread priorities */ +#define OBJC_THREAD_INTERACTIVE_PRIORITY 2 +#define OBJC_THREAD_BACKGROUND_PRIORITY 1 +#define OBJC_THREAD_LOW_PRIORITY 0 + +/* A thread */ +typedef void * objc_thread_t; + +/* This structure represents a single mutual exclusion lock. */ +struct objc_mutex +{ + volatile objc_thread_t owner; /* Id of thread that owns. */ + volatile int depth; /* # of acquires. */ + void * backend; /* Specific to backend */ +}; +typedef struct objc_mutex *objc_mutex_t; + +/* This structure represents a single condition mutex */ +struct objc_condition +{ + void * backend; /* Specific to backend */ +}; +typedef struct objc_condition *objc_condition_t; + +/* Frontend mutex functions */ +objc_mutex_t objc_mutex_allocate(void); +int objc_mutex_deallocate(objc_mutex_t mutex); +int objc_mutex_lock(objc_mutex_t mutex); +int objc_mutex_unlock(objc_mutex_t mutex); +int objc_mutex_trylock(objc_mutex_t mutex); + +/* Frontend condition mutex functions */ +objc_condition_t objc_condition_allocate(void); +int objc_condition_deallocate(objc_condition_t condition); +int objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex); +int objc_condition_signal(objc_condition_t condition); +int objc_condition_broadcast(objc_condition_t condition); + +/* Frontend thread functions */ +objc_thread_t objc_thread_detach(SEL selector, id object, id argument); +void objc_thread_yield(void); +int objc_thread_exit(void); +int objc_thread_set_priority(int priority); +int objc_thread_get_priority(void); +void * objc_thread_get_data(void); +int objc_thread_set_data(void *value); +objc_thread_t objc_thread_id(void); + +/* + Use this to set the hook function that will be called when the + runtime initially becomes multi threaded. + The hook function is only called once, meaning only when the + 2nd thread is spawned, not for each and every thread. + + It returns the previous hook function or NULL if there is none. + + A program outside of the runtime could set this to some function so + it can be informed; for example, the GNUstep Base Library sets it + so it can implement the NSBecomingMultiThreaded notification. + */ +typedef void (*objc_thread_callback)(); +objc_thread_callback objc_set_thread_callback(objc_thread_callback func); + +/* Backend initialization functions */ +int __objc_init_thread_system(void); +int __objc_fini_thread_system(void); + +/* Backend mutex functions */ +int __objc_mutex_allocate(objc_mutex_t mutex); +int __objc_mutex_deallocate(objc_mutex_t mutex); +int __objc_mutex_lock(objc_mutex_t mutex); +int __objc_mutex_trylock(objc_mutex_t mutex); +int __objc_mutex_unlock(objc_mutex_t mutex); + +/* Backend condition mutex functions */ +int __objc_condition_allocate(objc_condition_t condition); +int __objc_condition_deallocate(objc_condition_t condition); +int __objc_condition_wait(objc_condition_t condition, objc_mutex_t mutex); +int __objc_condition_broadcast(objc_condition_t condition); +int __objc_condition_signal(objc_condition_t condition); + +/* Backend thread functions */ +objc_thread_t __objc_thread_detach(void (*func)(void *arg), void *arg); +int __objc_thread_set_priority(int priority); +int __objc_thread_get_priority(void); +void __objc_thread_yield(void); +int __objc_thread_exit(void); +objc_thread_t __objc_thread_id(void); +int __objc_thread_set_data(void *value); +void * __objc_thread_get_data(void); + +#endif /* not __thread_INCLUDE_GNU */ diff --git a/contrib/gcc/objc/typedstream.h b/contrib/gcc/objc/typedstream.h new file mode 100644 index 000000000000..eb4642f344be --- /dev/null +++ b/contrib/gcc/objc/typedstream.h @@ -0,0 +1,132 @@ +/* GNU Objective-C Typed Streams interface. + Copyright (C) 1993, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +GNU CC is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with files compiled + with GCC to produce an executable, this does not cause the resulting + executable to be covered by the GNU General Public License. This + exception does not however invalidate any other reasons why the + executable file might be covered by the GNU General Public License. */ + +#ifndef __typedstream_INCLUDE_GNU +#define __typedstream_INCLUDE_GNU + +#include "objc/objc.h" +#include "objc/hash.h" +#include <stdio.h> + +typedef int (*objc_typed_read_func)(void*, char*, int); +typedef int (*objc_typed_write_func)(void*, const char*, int); +typedef int (*objc_typed_flush_func)(void*); +typedef int (*objc_typed_eof_func)(void*); + +#define OBJC_READONLY 0x01 +#define OBJC_WRITEONLY 0x02 + +#define OBJC_MANAGED_STREAM 0x01 +#define OBJC_FILE_STREAM 0x02 +#define OBJC_MEMORY_STREAM 0x04 + +#define OBJC_TYPED_STREAM_VERSION 0x01 + +typedef struct objc_typed_stream { + void* physical; + cache_ptr object_table; /* read/written objects */ + cache_ptr stream_table; /* other read/written but shared things.. */ + cache_ptr class_table; /* class version mapping */ + cache_ptr object_refs; /* forward references */ + int mode; /* OBJC_READONLY or OBJC_WRITEONLY */ + int type; /* MANAGED, FILE, MEMORY etc bit string */ + int version; /* version used when writing */ + int writing_root_p; + objc_typed_read_func read; + objc_typed_write_func write; + objc_typed_eof_func eof; + objc_typed_flush_func flush; +} TypedStream; + +/* opcode masks */ +#define _B_VALUE 0x1fU +#define _B_CODE 0xe0U +#define _B_SIGN 0x10U +#define _B_NUMBER 0x0fU + +/* standard opcodes */ +#define _B_INVALID 0x00U +#define _B_SINT 0x20U +#define _B_NINT 0x40U +#define _B_SSTR 0x60U +#define _B_NSTR 0x80U +#define _B_RCOMM 0xa0U +#define _B_UCOMM 0xc0U +#define _B_EXT 0xe0U + +/* eXtension opcodes */ +#define _BX_OBJECT 0x00U +#define _BX_CLASS 0x01U +#define _BX_SEL 0x02U +#define _BX_OBJREF 0x03U +#define _BX_OBJROOT 0x04U +#define _BX_EXT 0x1fU + +/* +** Read and write objects as specified by TYPE. All the `last' +** arguments are pointers to the objects to read/write. +*/ + +int objc_write_type (TypedStream* stream, const char* type, const void* data); +int objc_read_type (TypedStream* stream, const char* type, void* data); + +int objc_write_types (TypedStream* stream, const char* type, ...); +int objc_read_types (TypedStream* stream, const char* type, ...); + +int objc_write_object_reference (TypedStream* stream, id object); +int objc_write_root_object (TypedStream* stream, id object); + +long objc_get_stream_class_version (TypedStream* stream, Class class); + + +/* +** Convenience functions +*/ + +int objc_write_array (TypedStream* stream, const char* type, + int count, const void* data); +int objc_read_array (TypedStream* stream, const char* type, + int count, void* data); + +int objc_write_object (TypedStream* stream, id object); +int objc_read_object (TypedStream* stream, id* object); + + + +/* +** Open a typed stream for reading or writing. MODE may be either of +** OBJC_READONLY or OBJC_WRITEONLY. +*/ + +TypedStream* objc_open_typed_stream (FILE* physical, int mode); +TypedStream* objc_open_typed_stream_for_file (const char* file_name, int mode); + +void objc_close_typed_stream (TypedStream* stream); + +BOOL objc_end_of_typed_stream (TypedStream* stream); +void objc_flush_typed_stream (TypedStream* stream); + +#endif /* not __typedstream_INCLUDE_GNU */ diff --git a/contrib/gcc/pexecute.c b/contrib/gcc/pexecute.c index cd24f5b99613..78d90f573920 100644 --- a/contrib/gcc/pexecute.c +++ b/contrib/gcc/pexecute.c @@ -23,7 +23,7 @@ Boston, MA 02111-1307, USA. */ /* This file lives in at least two places: libiberty and gcc. Don't change one without the other. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/pexecute.c,v 1.3 1999/11/04 10:26:31 obrien Exp $ */ #ifdef HAVE_CONFIG_H #include "config.h" diff --git a/contrib/gcc/print-tree.c b/contrib/gcc/print-tree.c index 7b2945415737..3d94a9431692 100644 --- a/contrib/gcc/print-tree.c +++ b/contrib/gcc/print-tree.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/print-tree.c,v 1.4 1999/10/26 09:17:58 obrien Exp $ */ #include "config.h" diff --git a/contrib/gcc/reload.c b/contrib/gcc/reload.c index 7be6edc1b4b4..c8e835a45d59 100644 --- a/contrib/gcc/reload.c +++ b/contrib/gcc/reload.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/reload.c,v 1.4 1999/10/27 09:23:37 obrien Exp $ */ /* This file contains subroutines used only from the file reload1.c. diff --git a/contrib/gcc/toplev.c b/contrib/gcc/toplev.c index 217305acfcae..44ccfda06f02 100644 --- a/contrib/gcc/toplev.c +++ b/contrib/gcc/toplev.c @@ -18,7 +18,7 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* $FreeBSD$ */ +/* $FreeBSD: src/contrib/gcc/toplev.c,v 1.6.2.1 2000/07/04 05:55:22 obrien Exp $ */ /* This is the top level of cc1/c++. It parses command args, opens files, invokes the various passes |