diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp | 228 |
1 files changed, 114 insertions, 114 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp b/contrib/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp index 2ffa5e389f89..89b5bcebd61c 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp @@ -35,6 +35,7 @@ #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DebugLoc.h" #include "llvm/IR/Metadata.h" +#include "llvm/InitializePasses.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Pass.h" @@ -82,15 +83,15 @@ namespace { /// Everything we know about a live virtual register. struct LiveReg { MachineInstr *LastUse = nullptr; ///< Last instr to use reg. - unsigned VirtReg; ///< Virtual register number. + Register VirtReg; ///< Virtual register number. MCPhysReg PhysReg = 0; ///< Currently held here. unsigned short LastOpNum = 0; ///< OpNum on LastUse. bool Dirty = false; ///< Register needs spill. - explicit LiveReg(unsigned VirtReg) : VirtReg(VirtReg) {} + explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} unsigned getSparseSetIndex() const { - return TargetRegisterInfo::virtReg2Index(VirtReg); + return Register::virtReg2Index(VirtReg); } }; @@ -128,7 +129,7 @@ namespace { /// Maps each physical register to a RegState enum or a virtual register. std::vector<unsigned> PhysRegState; - SmallVector<unsigned, 16> VirtDead; + SmallVector<Register, 16> VirtDead; SmallVector<MachineInstr *, 32> Coalesced; using RegUnitSet = SparseSet<uint16_t, identity<uint16_t>>; @@ -184,14 +185,14 @@ namespace { void allocateInstruction(MachineInstr &MI); void handleDebugValue(MachineInstr &MI); void handleThroughOperands(MachineInstr &MI, - SmallVectorImpl<unsigned> &VirtDead); + SmallVectorImpl<Register> &VirtDead); bool isLastUseOfLocalReg(const MachineOperand &MO) const; void addKillFlag(const LiveReg &LRI); void killVirtReg(LiveReg &LR); - void killVirtReg(unsigned VirtReg); + void killVirtReg(Register VirtReg); void spillVirtReg(MachineBasicBlock::iterator MI, LiveReg &LR); - void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); + void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg); void usePhysReg(MachineOperand &MO); void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg, @@ -199,34 +200,34 @@ namespace { unsigned calcSpillCost(MCPhysReg PhysReg) const; void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg); - LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { - return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); + LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { + return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); } - LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { - return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); + LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { + return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); } - void allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint); + void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint); void allocVirtRegUndef(MachineOperand &MO); - MCPhysReg defineVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg, - unsigned Hint); - LiveReg &reloadVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg, - unsigned Hint); + MCPhysReg defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg, + Register Hint); + LiveReg &reloadVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg, + Register Hint); void spillAll(MachineBasicBlock::iterator MI, bool OnlyLiveOut); bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg); - unsigned traceCopies(unsigned VirtReg) const; - unsigned traceCopyChain(unsigned Reg) const; + Register traceCopies(Register VirtReg) const; + Register traceCopyChain(Register Reg) const; - int getStackSpaceFor(unsigned VirtReg); - void spill(MachineBasicBlock::iterator Before, unsigned VirtReg, + int getStackSpaceFor(Register VirtReg); + void spill(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg AssignedReg, bool Kill); - void reload(MachineBasicBlock::iterator Before, unsigned VirtReg, + void reload(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg PhysReg); - bool mayLiveOut(unsigned VirtReg); - bool mayLiveIn(unsigned VirtReg); + bool mayLiveOut(Register VirtReg); + bool mayLiveIn(Register VirtReg); void dumpState(); }; @@ -244,7 +245,7 @@ void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) { /// This allocates space for the specified virtual register to be held on the /// stack. -int RegAllocFast::getStackSpaceFor(unsigned VirtReg) { +int RegAllocFast::getStackSpaceFor(Register VirtReg) { // Find the location Reg would belong... int SS = StackSlotForVirtReg[VirtReg]; // Already has space allocated? @@ -263,8 +264,8 @@ int RegAllocFast::getStackSpaceFor(unsigned VirtReg) { } /// Returns false if \p VirtReg is known to not live out of the current block. -bool RegAllocFast::mayLiveOut(unsigned VirtReg) { - if (MayLiveAcrossBlocks.test(TargetRegisterInfo::virtReg2Index(VirtReg))) { +bool RegAllocFast::mayLiveOut(Register VirtReg) { + if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) { // Cannot be live-out if there are no successors. return !MBB->succ_empty(); } @@ -272,7 +273,7 @@ bool RegAllocFast::mayLiveOut(unsigned VirtReg) { // If this block loops back to itself, it would be necessary to check whether // the use comes after the def. if (MBB->isSuccessor(MBB)) { - MayLiveAcrossBlocks.set(TargetRegisterInfo::virtReg2Index(VirtReg)); + MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); return true; } @@ -282,7 +283,7 @@ bool RegAllocFast::mayLiveOut(unsigned VirtReg) { unsigned C = 0; for (const MachineInstr &UseInst : MRI->reg_nodbg_instructions(VirtReg)) { if (UseInst.getParent() != MBB || ++C >= Limit) { - MayLiveAcrossBlocks.set(TargetRegisterInfo::virtReg2Index(VirtReg)); + MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); // Cannot be live-out if there are no successors. return !MBB->succ_empty(); } @@ -292,8 +293,8 @@ bool RegAllocFast::mayLiveOut(unsigned VirtReg) { } /// Returns false if \p VirtReg is known to not be live into the current block. -bool RegAllocFast::mayLiveIn(unsigned VirtReg) { - if (MayLiveAcrossBlocks.test(TargetRegisterInfo::virtReg2Index(VirtReg))) +bool RegAllocFast::mayLiveIn(Register VirtReg) { + if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) return !MBB->pred_empty(); // See if the first \p Limit def of the register are all in the current block. @@ -301,7 +302,7 @@ bool RegAllocFast::mayLiveIn(unsigned VirtReg) { unsigned C = 0; for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { if (DefInst.getParent() != MBB || ++C >= Limit) { - MayLiveAcrossBlocks.set(TargetRegisterInfo::virtReg2Index(VirtReg)); + MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); return !MBB->pred_empty(); } } @@ -311,7 +312,7 @@ bool RegAllocFast::mayLiveIn(unsigned VirtReg) { /// Insert spill instruction for \p AssignedReg before \p Before. Update /// DBG_VALUEs with \p VirtReg operands with the stack slot. -void RegAllocFast::spill(MachineBasicBlock::iterator Before, unsigned VirtReg, +void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg AssignedReg, bool Kill) { LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in " << printReg(AssignedReg, TRI)); @@ -339,7 +340,7 @@ void RegAllocFast::spill(MachineBasicBlock::iterator Before, unsigned VirtReg, } /// Insert reload instruction for \p PhysReg before \p Before. -void RegAllocFast::reload(MachineBasicBlock::iterator Before, unsigned VirtReg, +void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg PhysReg) { LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " << printReg(PhysReg, TRI) << '\n'); @@ -393,8 +394,8 @@ void RegAllocFast::killVirtReg(LiveReg &LR) { } /// Mark virtreg as no longer available. -void RegAllocFast::killVirtReg(unsigned VirtReg) { - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && +void RegAllocFast::killVirtReg(Register VirtReg) { + assert(Register::isVirtualRegister(VirtReg) && "killVirtReg needs a virtual register"); LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); if (LRI != LiveVirtRegs.end() && LRI->PhysReg) @@ -404,8 +405,8 @@ void RegAllocFast::killVirtReg(unsigned VirtReg) { /// This method spills the value specified by VirtReg into the corresponding /// stack slot if needed. void RegAllocFast::spillVirtReg(MachineBasicBlock::iterator MI, - unsigned VirtReg) { - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && + Register VirtReg) { + assert(Register::isVirtualRegister(VirtReg) && "Spilling a physical register is illegal!"); LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); assert(LRI != LiveVirtRegs.end() && LRI->PhysReg && @@ -455,9 +456,8 @@ void RegAllocFast::usePhysReg(MachineOperand &MO) { if (MO.isUndef()) return; - unsigned PhysReg = MO.getReg(); - assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && - "Bad usePhysReg operand"); + Register PhysReg = MO.getReg(); + assert(PhysReg.isPhysical() && "Bad usePhysReg operand"); markRegUsedInInstr(PhysReg); switch (PhysRegState[PhysReg]) { @@ -521,7 +521,7 @@ void RegAllocFast::usePhysReg(MachineOperand &MO) { void RegAllocFast::definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg, RegState NewState) { markRegUsedInInstr(PhysReg); - switch (unsigned VirtReg = PhysRegState[PhysReg]) { + switch (Register VirtReg = PhysRegState[PhysReg]) { case regDisabled: break; default: @@ -537,7 +537,7 @@ void RegAllocFast::definePhysReg(MachineBasicBlock::iterator MI, setPhysRegState(PhysReg, NewState); for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { MCPhysReg Alias = *AI; - switch (unsigned VirtReg = PhysRegState[Alias]) { + switch (Register VirtReg = PhysRegState[Alias]) { case regDisabled: break; default: @@ -563,7 +563,7 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { << " is already used in instr.\n"); return spillImpossible; } - switch (unsigned VirtReg = PhysRegState[PhysReg]) { + switch (Register VirtReg = PhysRegState[PhysReg]) { case regDisabled: break; case regFree: @@ -585,7 +585,7 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { unsigned Cost = 0; for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { MCPhysReg Alias = *AI; - switch (unsigned VirtReg = PhysRegState[Alias]) { + switch (Register VirtReg = PhysRegState[Alias]) { case regDisabled: break; case regFree: @@ -609,7 +609,7 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { /// proper container for VirtReg now. The physical register must not be used /// for anything else when this is called. void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) { - unsigned VirtReg = LR.VirtReg; + Register VirtReg = LR.VirtReg; LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to " << printReg(PhysReg, TRI) << '\n'); assert(LR.PhysReg == 0 && "Already assigned a physreg"); @@ -622,13 +622,13 @@ static bool isCoalescable(const MachineInstr &MI) { return MI.isFullCopy(); } -unsigned RegAllocFast::traceCopyChain(unsigned Reg) const { +Register RegAllocFast::traceCopyChain(Register Reg) const { static const unsigned ChainLengthLimit = 3; unsigned C = 0; do { - if (TargetRegisterInfo::isPhysicalRegister(Reg)) + if (Reg.isPhysical()) return Reg; - assert(TargetRegisterInfo::isVirtualRegister(Reg)); + assert(Reg.isVirtual()); MachineInstr *VRegDef = MRI->getUniqueVRegDef(Reg); if (!VRegDef || !isCoalescable(*VRegDef)) @@ -641,28 +641,28 @@ unsigned RegAllocFast::traceCopyChain(unsigned Reg) const { /// Check if any of \p VirtReg's definitions is a copy. If it is follow the /// chain of copies to check whether we reach a physical register we can /// coalesce with. -unsigned RegAllocFast::traceCopies(unsigned VirtReg) const { +Register RegAllocFast::traceCopies(Register VirtReg) const { static const unsigned DefLimit = 3; unsigned C = 0; for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) { if (isCoalescable(MI)) { - unsigned Reg = MI.getOperand(1).getReg(); + Register Reg = MI.getOperand(1).getReg(); Reg = traceCopyChain(Reg); - if (Reg != 0) + if (Reg.isValid()) return Reg; } if (++C >= DefLimit) break; } - return 0; + return Register(); } /// Allocates a physical register for VirtReg. -void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint0) { - const unsigned VirtReg = LR.VirtReg; +void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint0) { + const Register VirtReg = LR.VirtReg; - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && + assert(Register::isVirtualRegister(VirtReg) && "Can only allocate virtual registers"); const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); @@ -671,8 +671,8 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint0) { << " with hint " << printReg(Hint0, TRI) << '\n'); // Take hint when possible. - if (TargetRegisterInfo::isPhysicalRegister(Hint0) && - MRI->isAllocatable(Hint0) && RC.contains(Hint0)) { + if (Hint0.isPhysical() && MRI->isAllocatable(Hint0) && + RC.contains(Hint0)) { // Ignore the hint if we would have to spill a dirty register. unsigned Cost = calcSpillCost(Hint0); if (Cost < spillDirty) { @@ -687,14 +687,13 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint0) { << "occupied\n"); } } else { - Hint0 = 0; + Hint0 = Register(); } // Try other hint. - unsigned Hint1 = traceCopies(VirtReg); - if (TargetRegisterInfo::isPhysicalRegister(Hint1) && - MRI->isAllocatable(Hint1) && RC.contains(Hint1) && - !isRegUsedInInstr(Hint1)) { + Register Hint1 = traceCopies(VirtReg); + if (Hint1.isPhysical() && MRI->isAllocatable(Hint1) && + RC.contains(Hint1) && !isRegUsedInInstr(Hint1)) { // Ignore the hint if we would have to spill a dirty register. unsigned Cost = calcSpillCost(Hint1); if (Cost < spillDirty) { @@ -709,7 +708,7 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint0) { << "occupied\n"); } } else { - Hint1 = 0; + Hint1 = Register(); } MCPhysReg BestReg = 0; @@ -752,8 +751,8 @@ void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint0) { void RegAllocFast::allocVirtRegUndef(MachineOperand &MO) { assert(MO.isUndef() && "expected undef use"); - unsigned VirtReg = MO.getReg(); - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Expected virtreg"); + Register VirtReg = MO.getReg(); + assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg"); LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg); MCPhysReg PhysReg; @@ -777,15 +776,14 @@ void RegAllocFast::allocVirtRegUndef(MachineOperand &MO) { /// Allocates a register for VirtReg and mark it as dirty. MCPhysReg RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum, - unsigned VirtReg, unsigned Hint) { - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && - "Not a virtual register"); + Register VirtReg, Register Hint) { + assert(Register::isVirtualRegister(VirtReg) && "Not a virtual register"); LiveRegMap::iterator LRI; bool New; std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); if (!LRI->PhysReg) { // If there is no hint, peek at the only use of this register. - if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) && + if ((!Hint || !Hint.isPhysical()) && MRI->hasOneNonDBGUse(VirtReg)) { const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg); // It's a copy, use the destination register as a hint. @@ -810,10 +808,9 @@ MCPhysReg RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum, /// Make sure VirtReg is available in a physreg and return it. RegAllocFast::LiveReg &RegAllocFast::reloadVirtReg(MachineInstr &MI, unsigned OpNum, - unsigned VirtReg, - unsigned Hint) { - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && - "Not a virtual register"); + Register VirtReg, + Register Hint) { + assert(Register::isVirtualRegister(VirtReg) && "Not a virtual register"); LiveRegMap::iterator LRI; bool New; std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); @@ -866,7 +863,7 @@ bool RegAllocFast::setPhysReg(MachineInstr &MI, MachineOperand &MO, } // Handle subregister index. - MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); + MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register()); MO.setIsRenamable(true); MO.setSubReg(0); @@ -888,13 +885,13 @@ bool RegAllocFast::setPhysReg(MachineInstr &MI, MachineOperand &MO, // Handles special instruction operand like early clobbers and tied ops when // there are additional physreg defines. void RegAllocFast::handleThroughOperands(MachineInstr &MI, - SmallVectorImpl<unsigned> &VirtDead) { + SmallVectorImpl<Register> &VirtDead) { LLVM_DEBUG(dbgs() << "Scanning for through registers:"); - SmallSet<unsigned, 8> ThroughRegs; + SmallSet<Register, 8> ThroughRegs; for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(Reg)) + Register Reg = MO.getReg(); + if (!Reg.isVirtual()) continue; if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) || (MO.getSubReg() && MI.readsVirtualRegister(Reg))) { @@ -908,8 +905,9 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, LLVM_DEBUG(dbgs() << "\nChecking for physdef collisions.\n"); for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg() || !MO.isDef()) continue; - unsigned Reg = MO.getReg(); - if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; + Register Reg = MO.getReg(); + if (!Reg || !Reg.isPhysical()) + continue; markRegUsedInInstr(Reg); for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { if (ThroughRegs.count(PhysRegState[*AI])) @@ -917,13 +915,14 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, } } - SmallVector<unsigned, 8> PartialDefs; + SmallVector<Register, 8> PartialDefs; LLVM_DEBUG(dbgs() << "Allocating tied uses.\n"); for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) { MachineOperand &MO = MI.getOperand(I); if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; + Register Reg = MO.getReg(); + if (!Register::isVirtualRegister(Reg)) + continue; if (MO.isUse()) { if (!MO.isTied()) continue; LLVM_DEBUG(dbgs() << "Operand " << I << "(" << MO @@ -947,8 +946,9 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) { const MachineOperand &MO = MI.getOperand(I); if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; + Register Reg = MO.getReg(); + if (!Register::isVirtualRegister(Reg)) + continue; if (!MO.isEarlyClobber()) continue; // Note: defineVirtReg may invalidate MO. @@ -961,15 +961,16 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, UsedInInstr.clear(); for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; - unsigned Reg = MO.getReg(); - if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; + Register Reg = MO.getReg(); + if (!Reg || !Reg.isPhysical()) + continue; LLVM_DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI) << " as used in instr\n"); markRegUsedInInstr(Reg); } // Also mark PartialDefs as used to avoid reallocation. - for (unsigned PartialDef : PartialDefs) + for (Register PartialDef : PartialDefs) markRegUsedInInstr(PartialDef); } @@ -1002,10 +1003,8 @@ void RegAllocFast::dumpState() { e = LiveVirtRegs.end(); i != e; ++i) { if (!i->PhysReg) continue; - assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) && - "Bad map key"); - assert(TargetRegisterInfo::isPhysicalRegister(i->PhysReg) && - "Bad map value"); + assert(i->VirtReg.isVirtual() && "Bad map key"); + assert(Register::isPhysicalRegister(i->PhysReg) && "Bad map value"); assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map"); } } @@ -1015,8 +1014,8 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { const MCInstrDesc &MCID = MI.getDesc(); // If this is a copy, we may be able to coalesce. - unsigned CopySrcReg = 0; - unsigned CopyDstReg = 0; + Register CopySrcReg; + Register CopyDstReg; unsigned CopySrcSub = 0; unsigned CopyDstSub = 0; if (MI.isCopy()) { @@ -1045,9 +1044,9 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { continue; } if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); if (!Reg) continue; - if (TargetRegisterInfo::isVirtualRegister(Reg)) { + if (Register::isVirtualRegister(Reg)) { VirtOpEnd = i+1; if (MO.isUse()) { hasTiedOps = hasTiedOps || @@ -1084,7 +1083,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) { handleThroughOperands(MI, VirtDead); // Don't attempt coalescing when we have funny stuff going on. - CopyDstReg = 0; + CopyDstReg = Register(); // Pretend we have early clobbers so the use operands get marked below. // This is not necessary for the common case of a single tied use. hasEarlyClobbers = true; @@ -1096,8 +1095,9 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { for (unsigned I = 0; I != VirtOpEnd; ++I) { MachineOperand &MO = MI.getOperand(I); if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; + Register Reg = MO.getReg(); + if (!Reg.isVirtual()) + continue; if (MO.isUse()) { if (MO.isUndef()) { HasUndefUse = true; @@ -1124,8 +1124,8 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { for (MachineOperand &MO : MI.uses()) { if (!MO.isReg() || !MO.isUse()) continue; - unsigned Reg = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(Reg)) + Register Reg = MO.getReg(); + if (!Reg.isVirtual()) continue; assert(MO.isUndef() && "Should only have undef virtreg uses left"); @@ -1139,8 +1139,9 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { if (hasEarlyClobbers) { for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; + Register Reg = MO.getReg(); + if (!Reg || !Reg.isPhysical()) + continue; // Look for physreg defs and tied uses. if (!MO.isDef() && !MO.isTied()) continue; markRegUsedInInstr(Reg); @@ -1166,10 +1167,9 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { const MachineOperand &MO = MI.getOperand(I); if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) continue; - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); - if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg) || - !MRI->isAllocatable(Reg)) + if (!Reg || !Reg.isPhysical() || !MRI->isAllocatable(Reg)) continue; definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved); } @@ -1180,15 +1180,15 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { const MachineOperand &MO = MI.getOperand(I); if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) continue; - unsigned Reg = MO.getReg(); + Register Reg = MO.getReg(); // We have already dealt with phys regs in the previous scan. - if (TargetRegisterInfo::isPhysicalRegister(Reg)) + if (Reg.isPhysical()) continue; MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, CopySrcReg); if (setPhysReg(MI, MI.getOperand(I), PhysReg)) { VirtDead.push_back(Reg); - CopyDstReg = 0; // cancel coalescing; + CopyDstReg = Register(); // cancel coalescing; } else CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0; } @@ -1197,7 +1197,7 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) { // register are allocated identically. We didn't need to do this for uses // because we are crerating our own kill flags, and they are always at the // last use. - for (unsigned VirtReg : VirtDead) + for (Register VirtReg : VirtDead) killVirtReg(VirtReg); VirtDead.clear(); @@ -1215,8 +1215,8 @@ void RegAllocFast::handleDebugValue(MachineInstr &MI) { // mostly constants and frame indices. if (!MO.isReg()) return; - unsigned Reg = MO.getReg(); - if (!TargetRegisterInfo::isVirtualRegister(Reg)) + Register Reg = MO.getReg(); + if (!Register::isVirtualRegister(Reg)) return; // See if this virtual register has already been allocated to a physical @@ -1235,7 +1235,7 @@ void RegAllocFast::handleDebugValue(MachineInstr &MI) { // We can't allocate a physreg for a DebugValue, sorry! LLVM_DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); - MO.setReg(0); + MO.setReg(Register()); } // If Reg hasn't been spilled, put this DBG_VALUE in LiveDbgValueMap so @@ -1253,7 +1253,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) { MachineBasicBlock::iterator MII = MBB.begin(); // Add live-in registers as live. - for (const MachineBasicBlock::RegisterMaskPair LI : MBB.liveins()) + for (const MachineBasicBlock::RegisterMaskPair &LI : MBB.liveins()) if (MRI->isAllocatable(LI.PhysReg)) definePhysReg(MII, LI.PhysReg, regReserved); |