diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp b/contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp index 195279719ad4..ce59452fd1b8 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/TargetSchedule.cpp @@ -300,7 +300,7 @@ computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, // TODO: The following hack exists because predication passes do not // correctly append imp-use operands, and readsReg() strangely returns false // for predicated defs. - unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); + Register Reg = DefMI->getOperand(DefOperIdx).getReg(); const MachineFunction &MF = *DefMI->getMF(); const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) |